Light-emitting device

Abstract

To provide a light emitting device capable of suppressing a variation in brightness between pixels due to a variation in the threshold voltage of a transistor.SOLUTION: There is provided a light emitting device including a transistor having a first gate and a second gate that overlap each other via a semiconductor film, a first capacitive element that holds a potential difference between one of the source and drain of the transistor and the first gate, a second capacitive element that holds a potential difference between one of the source and drain of the transistor and the second gate, a switch that controls the conduction state between the second gate of the above transistor and the wires, and a light emitting element to which the drain current of the above transistor is supplied.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine , a manufacture, or a composition of matter. In particular , one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a memory device, an information processing device, and their driving methods, or their manufacturing methods. In particular, one aspect of the present invention relates to a semiconductor device , a display device, a light-emitting device, a power storage device, a memory device, their driving methods, or their manufacturing methods.

Background Art

[0002] Although the configurations of active matrix type display devices using light-emitting elements are specifically proposed by different manufacturers, usually, at least a light-emitting element, a transistor (switching transistor) for controlling the input of a video signal to a pixel, and a transistor (driving transistor) for controlling the current value supplied to the light-emitting element are provided in each pixel. And, by making all the transistors provided in the pixel have the same polarity, in the manufacturing process of the transistor, steps such as adding an impurity element for imparting n-type conductivity to the semiconductor film can be partially omitted. Patent Document 1 below describes a light-emitting element type display in which pixels are composed of only n-channel type transistors.

[0003]

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, in a light-emitting device, since the drain current of a driving transistor is supplied to a light-emitting element, if there is a variation in the threshold voltage of the driving transistor between pixels, the variation will be reflected in the luminance of the light-emitting element. Therefore, a proposal for a pixel configuration capable of correcting the current value of a driving transistor in anticipation of the variation in the threshold voltage is an important issue in improving the image quality of a light-emitting device. When there is a variation in the threshold voltage of the driving transistor between pixels, the variation will be reflected in the luminance of the light-emitting element. Therefore, a proposal for a pixel configuration capable of correcting the current value of a driving transistor in anticipation of the variation in the threshold voltage is an important issue in improving the image quality of a light-emitting device. When there is a variation in the threshold voltage of the driving transistor between pixels, the variation will be reflected in the luminance of the light-emitting element. Therefore, a proposal for a pixel configuration capable of correcting the current value of a driving transistor in anticipation of the variation in the threshold voltage is an important issue in improving the image quality of a light-emitting device.

[0006] Under the technical background as described above, one of the problems is to provide a light-emitting device in which the variation in luminance between pixels due to the variation in the threshold voltage of the driving transistor is suppressed. Under the technical background as described above, one of the problems is to provide a light-emitting device in which the variation in luminance between pixels due to the variation in the threshold voltage of the driving transistor is suppressed.

[0007] Note that one aspect of the present invention is to provide a novel semiconductor device or the like. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0008] A light-emitting device according to one aspect of the present invention includes a transistor having a first gate and a second gate that overlap each other via a semiconductor film, a first capacitive element that holds a potential difference between one of the source and the drain of the transistor and the first gate, and a source of the transistor. A light-emitting device according to one aspect of the present invention includes a transistor having a first gate and a second gate that overlap each other via a semiconductor film, a first capacitive element that holds a potential difference between one of the source and the drain of the transistor and the first gate, and a source of the transistor. A light-emitting device according to one aspect of the present invention includes a transistor having a first gate and a second gate that overlap each other via a semiconductor film, a first capacitive element that holds a potential difference between one of the source and the drain of the transistor and the first gate, and a source of the transistor. A second capacitive element that holds the potential difference between one of the source and the drain and the second gate. A switch that controls the conduction state between the second gate of the transistor and a wiring, And a light-emitting element to which the drain current of the transistor is supplied.

Advantages of the Invention

[0009] According to one aspect of the present invention, it is possible to provide a light-emitting device in which variations in luminance between pixels due to variations in the threshold voltage of a transistor are suppressed. Moreover, according to one aspect of the present invention, it is possible to provide a novel semiconductor device or the like. Note that these descriptions of the effects do not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Other effects will be apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

[0010] Furthermore, according to one aspect of the present invention, it is possible to provide a novel semiconductor device or the like. Note that these descriptions of the effects do not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Other effects will be apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc. Moreover, according to one aspect of the present invention, it is possible to provide a novel semiconductor device or the like. Note that these descriptions of the effects do not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Other effects will be apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc. Moreover, according to one aspect of the present invention, it is possible to provide a novel semiconductor device or the like. Note that these descriptions of the effects do not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Other effects will be apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc. Moreover, according to one aspect of the present invention, it is possible to provide a novel semiconductor device or the like. Note that these descriptions of the effects do not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Other effects will be apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc. Moreover, according to one aspect of the present invention, it is possible to provide a novel semiconductor device or the like. Note that these descriptions of the effects do not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Other effects will be apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0011]

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Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as limited to the description of the embodiments shown below.

[0013] Note that in this specification, a light-emitting device includes a panel in which a light-emitting element is formed in each pixel, and a module in a state where an IC or the like including a drive circuit or a controller is mounted on the panel. Furthermore, a light-emitting device according to one aspect of the present invention includes, within its scope, an element substrate corresponding to a form before the light-emitting element is completed in the process of manufacturing the light-emitting device. The element substrate includes a transistor and a pixel electrode to which a voltage is supplied via the transistor, in a plurality. A number of pixels are provided.

[0014] The source of a transistor is a source region that is a part of the semiconductor film that functions as an active layer. The term "transistor" refers to a transistor region, or a source electrode electrically connected to the semiconductor film. The drain of the transistor is a drain region that is a part of the semiconductor film, or a region where an electric current is applied to the semiconductor film. "Gate" means a gate electrode that is electrically connected to the gate electrode.

[0015] The source and drain of a transistor are determined by the conductivity type of the transistor and the terminals. The name is changed depending on the potential that is applied. Generally, n-channel transistors In a transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. In addition, in a p-channel transistor, the terminal to which a low potential is applied is called the drain. The terminal to which the high potential is applied is called the input, and the terminal to which the high potential is applied is called the source. Explain the connection relationship of a transistor, assuming that the source and drain are fixed. In some cases, the names of the source and drain are interchangeable according to the above potential relationship. do.

[0016] In addition, when it is explicitly stated in this specification that X and Y are connected, is when X and Y are electrically connected and when X and Y are functionally connected. and the case where X and Y are directly connected are considered to be disclosed in this specification and the like. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be described in the drawings or text. do.

[0017] Here, let X and Y be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers , etc.).

[0018] As an example of the case where X and Y are directly connected, when an element (for example, a switch, transistor, capacitor, inductor, resistor, diode , display element, light-emitting element, load, etc.) that enables the electrical connection between X and Y is not connected between X and Y , and X and Y are connected without passing through an element (for example, a switch, transistor, capacitor , inductor, resistor, diode, display element, light-emitting element, load, etc.) that enables the electrical connection between X and Y . This is the case where X and Y are connected.

[0019] As an example of the case where X and Y are electrically connected, one or more elements (for example, a switch, transistor, capacitor, inductor, resistor, diode , display element, light-emitting element, load, etc.) that enable the electrical connection between X and Y can be connected between X and Y . Note that the switch has a function of controlling on / off. That is, the switch can be in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Or the switch has a function of selecting and switching the path through which current flows. Note that when X and Y are electrically connected, it includes the case where X and Y are directly connected. Y are directly connected.

[0020] As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (such as an inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit ​​Conversion circuits (such as DA conversion circuits, AD conversion circuits, gamma correction circuits), potential level conversion circuits (power source circuits (such as boost circuits, buck circuits), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplification circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected by one or more between X and Y. As an example, even if another circuit is sandwiched between X and Y, when the signal output from X is transmitted to Y, X and Y are considered to be functionally connected. When X and Y are functionally connected, it includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

[0021] When it is explicitly described that X and Y are electrically connected, it means the case where X and Y are electrically connected (that is, connected with another element or another circuit sandwiched between X and Y), the case where X and Y are functionally connected (that is, functionally connected with another circuit sandwiched between X and Y), and the case where X and Y are directly connected (that is, connected without another element or another circuit sandwiched between X and Y) shall be disclosed in this specification and the like. That is, when it is explicitly described as being electrically connected, it shall be disclosed in this specification and the like that the same content as when it is explicitly described simply as being connected is disclosed in this specification and the like.

[0022] <Example of Pixel Configuration> FIG. 1 shows, as an example, the configuration of pixel 10 of a light-emitting device according to one aspect of the present invention. As shown in FIG. 1 Each pixel 10 includes a transistor 11, a switch 16, a capacitor element 13, and a capacitor element 18. and a light-emitting element 14.

[0023] The light-emitting element 14 includes elements whose luminance is controlled by current or voltage, such as an LED (Light Emitting Diode) or an OLED ( Organic Light Emitting Diode). For example, an OLED includes an EL layer, an anode, and a cathode. The EL layer is provided between the anode and the cathode and is composed of a single layer or a plurality of layers, and at least includes a light-emitting layer containing a light-emitting substance among these layers. When the potential difference between the cathode and the anode is above the threshold voltage Vthe of the light-emitting element 14, electroluminescence is obtained by the current supplied. Electroluminescence includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state.

[0024] Also, one of the anode and the cathode of the light-emitting element 14 functions as a pixel electrode, and the other functions as a common electrode. In FIG. 1, the configuration of the pixel 10 using the anode of the light-emitting element 14 as the pixel electrode and the cathode of the light-emitting element 14 as the common electrode is illustrated.

[0025] In addition to a normal gate (first gate), the transistor 11 has a second gate that overlaps the first gate with a semiconductor film interposed therebetween. In FIG. 1, the first gate is illustrated as G1 and the second gate is illustrated as G2.

[0026] Also, the potential of the first gate of the transistor 11 follows the image signal supplied from the wiring SL. ​​is controlled. Switch 16 has a function of controlling the supply of the potential of wiring B to the second gate of transistor 11. It has a function of controlling the supply of the potential of L.

[0027] Note that switch 16 can be configured by using one or more transistors respectively. Alternatively, switch 16 may use a capacitive element in addition to one or more transistors. It may be used.

[0028] Capacitive element 13 has a function of holding the potential difference between the second gate of transistor 11 and one of the source and drain of transistor 11. Capacitive element 18 has a function of holding the potential difference between the first gate of transistor 11 and one of the source and drain of transistor 11. In FIG. 1, the case where transistor 11 is an n-channel type is illustrated. In this case, one of the source and drain of transistor 11 is electrically connected to the anode of light-emitting element 14. And the other of the source and drain of transistor 11 is electrically connected to wiring VL, and the cathode of light-emitting element 14 is electrically connected to wiring CL. It has a function of holding it.

[0029] In FIG. 1, the case where transistor 11 is an n-channel type is illustrated. In this case, one of the source and drain of transistor 11 is electrically connected to the anode of light-emitting element 14. And the other of the source and drain of transistor 11 is electrically connected to wiring VL, and the cathode of light-emitting element 14 is electrically connected to wiring CL. And the other of the source and drain of transistor 11 is electrically connected to wiring VL, and the cathode of light-emitting element 14 is electrically connected to wiring CL. And the cathode of light-emitting element 14 is electrically connected to wiring CL. Also, the potential of wiring VL is set to be higher than the potential obtained by adding the threshold voltage Vthe of light-emitting element 14 and the threshold voltage Vth of transistor 11 to the potential of wiring CL. Therefore, when the value of the drain current of transistor 11 is determined according to the image signal, the above drain current is supplied to light-emitting element 14, and light-emitting element 14 enters a light-emitting state. And the cathode of light-emitting element 14 is electrically connected to wiring CL. Therefore, when the value of the drain current of transistor 11 is determined according to the image signal, the above drain current is supplied to light-emitting element 14, and light-emitting element 14 enters a light-emitting state. When the above drain current is supplied to light-emitting element 14, light-emitting element 14 enters a light-emitting state.

[0030] When transistor 11 is a p-channel type, as shown in FIG. 35, transistor 11 Either the source or the drain of the transistor is electrically connected to the cathode of the light-emitting element 14. Then, the other of the source and the drain of the transistor 11 is electrically connected to the wiring VL, and the anode of the light-emitting element 14 is electrically connected to the wiring CL. Also, the potential of the wiring CL is set to be higher than the potential of the wiring VL plus the threshold voltage Vthe of the light-emitting element 14 and the threshold voltage Vth of the transistor 11. And, similar to the case where the transistor 11 is an n-channel type, when the transistor 11 is a p-channel type, when the value of the drain current of the transistor 11 is determined according to the image signal, the light-emitting element 14 emits light by supplying the above drain current to the light-emitting element 14.

[0031] And, in one aspect of the present invention, before determining the value of the drain current of the transistor 11 according to the image signal, by controlling the voltage Vbg between one of the source and the drain of the transistor 11 and the second gate, the threshold voltage Vth of the transistor 11 is corrected to prevent variations in the threshold voltage Vth of the transistor 11 among the pixels 10.

[0032] Specifically, by supplying the potential of the wiring BL to the second gate of the transistor 11 via the switch 16, the transistor 11 is set to be normally on. For example, when the transistor 11 is an n-channel type, increasing the voltage Vbg shifts the threshold voltage Vth in the negative direction, and the transistor 11 becomes normally on. Also, when the transistor 11 is a p-channel type, decreasing the voltage Vbg shifts the threshold voltage Vth in the positive direction, and the transistor 11 becomes normally on.

[0033] ​​​​​​​​Fig. 9 shows the relationship between the voltage Vbg and the threshold voltage Vth when the transistor 11 is of the n-channel type. Let the threshold voltage Vth of the transistor 11 when the voltage Vbg is 0 be Vth0. And when the voltage Vbg is shifted in the positive direction from 0 to Vbg1, the threshold voltage Vth is shifted in the negative direction from Vth0 and becomes Vth1 (Vth1 < 0). When the transistor 11 is in the normal-off state, keep the gate voltage Vgs, which is the potential difference between the first gate of the transistor 11 and one of the source and drain, at a constant value. Moreover, configure the drain current of the transistor 11 to flow through the second gate of the transistor 11 and the capacitor element 13. With the above configuration, the charge accumulated in the second gate of the transistor 11 and the capacitor element 13 moves, and the potential of one of the source and drain of the transistor 11 shifts. And as the potential of one of the source and drain of the transistor 11 shifts, since the voltage Vbg changes, the threshold voltage of the transistor 11 shifts in the direction of becoming normal-off. For example, when the transistor 11 is of the n-channel type, since the voltage Vbg shifts in the negative direction, the threshold voltage Vth shifts in the positive direction. Also, when the transistor 11 is of the p-channel type, since the voltage Vbg shifts in the positive direction, the threshold voltage Vth shifts in the negative direction. Finally, when the threshold voltage Vth of the transistor 11 approaches infinitely close to the gate voltage Vgs maintained at a constant value, the drain current converges to 0 and the transistor 11 turns off.

[0034]

[0035]

[0036] 。At this time, let the threshold voltage Vth of the transistor 11 be Vth2. As shown in FIG. 9 , when the voltage Vbg becomes Vbg2, the drain current of the transistor 11 with the gate voltage Vgs maintained at a constant value converges to 0. As a result, the threshold voltage Vth is corrected to Vth2 . The potential difference ΔV0 is held in the capacitor element 13.

[0037] In one aspect of the present invention, with the above configuration, variations in the threshold voltage of the transistor 11 that occur between the pixels 10 are prevented from affecting the value of the drain current of the transistor 11 . As a result, variations in luminance between the pixels can be suppressed.

[0038] Note that in FIG. 1, the configuration of the pixel 10 that can correct the threshold voltage Vth of the transistor 11 by controlling the voltage Vbg between one of the source and drain of the transistor 11 and the second gate is shown. However, the threshold voltage Vth of the transistor 11 may be corrected by controlling the voltage Vgs between one of the source and drain of the transistor 11 and the first gate . h.

[0039] FIG. 33 shows, as an example, the configuration of the pixel 10 that can correct the threshold voltage Vth of the transistor 11 by controlling the voltage Vgs. In the pixel 10 shown in FIG. 33, the potential of the second gate of the transistor 11 is controlled according to the image signal supplied from the wiring SL. The switch 16 has a function of controlling the supply of the potential of the wiring BL to the first gate of the transistor 11. The capacitor element 13 has a function of holding the potential difference between the first gate of the transistor 11 and one of the source and drain of the transistor 11. The capacitor element 18 ​​​​​​​, between the second gate of the transistor 11 and one of the source and drain of the transistor 11 has a function of holding the potential difference. In one aspect of the present invention, with the above configuration, before determining the value of the drain current of the transistor 11 according to the image signal , by controlling the voltage Vgs between one of the source and drain of the transistor 11 and the first gate, the threshold voltage Vth of the transistor 11 can be corrected, and the threshold voltage Vth of the transistor 11 can be prevented from varying among the pixels 10.

[0040] 〈Specific Configuration Example 1 of Pixel〉 FIG. 2(A) shows a specific configuration of the pixel 10 shown in FIG. 1 as an example.

[0041] The pixel 10 shown in FIG. 2(A) includes transistors 11, switches 12, capacitor elements 13, and light-emitting elements 14, and also includes switches 15 to 17 and capacitor element 18.

[0042] Specifically, in the pixel 10 shown in FIG. 2(A), the wiring SL is electrically connected to the first gate of the transistor 11 via the switch 15. Also, the wiring SL is electrically connected to the pixel electrode of the light-emitting element 14 via the switches 15 and 12. One of the source and drain of the transistor 11 is electrically connected to the pixel electrode of the light-emitting element 14, and the other of the source and drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL via the switch 16. The pixel electrode of the light-emitting element 14 is electrically connected to the wiring IL via the switch 17. One pair of electrodes of the capacitor element 13 has one connected to the second gate of the transistor 11 ​​​​​​​​​​​One is electrically connected to the other, and the other is electrically connected to the pixel electrode of the light-emitting element 14. One of the pair of electrodes of the capacitor element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14. The common electrode of the light-emitting element 1 4 is electrically connected to the wiring CL.

[0043] Next, FIG. 2(B) shows, as an example, another specific configuration of the pixel 10 shown in FIG. 1.

[0044] The pixel 10 shown in FIG. 2(B) differs in configuration from the pixel 10 shown in FIG. 2(A) in that it further has a switch 19. Specifically, in the pixel 10 shown in FIG. 2(B), the wiring SL is electrically connected to the first gate of the transistor 11 via the switch 15. Also, the wiring SL is electrically connected to the pixel electrode of the light-emitting element 14 via the switches 15,

[0045] 12, and the switch 19. One of the source and drain of the transistor 11 is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19, and the other of the source and drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL via the switch 16. The pixel electrode of the light-emitting element 14 is electrically connected to the wiring IL via the switches 17 and 19. One of the pair of electrodes of the capacitor element 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19. One of the pair of electrodes of the capacitor element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 via the switches 15, 12, and the switch 19. One of the source and drain of the transistor 11 is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19, and the other of the source and drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL via the switch 16. The pixel electrode of the light-emitting element 14 is electrically connected to the wiring IL via the switches 17 and 19. One of the pair of electrodes of the capacitor element 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19. One of the pair of electrodes of the capacitor element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19. One of the pair of electrodes of the capacitor element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19. One of the pair of electrodes of the capacitor element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19. One of the pair of electrodes of the capacitor element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19. One of the pair of electrodes of the capacitor element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19. One of the pair of electrodes of the capacitor element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19. One of the pair of electrodes of the capacitor element 18 is electrically connected to the first gate of the transistor 11, and the other wherein the other is electrically connected to the pixel electrode of the light-emitting element 14 via the switch 19 . The common electrode of the light-emitting element 14 is electrically connected to the wiring CL.

[0046] Next, in the pixel 10 shown in FIG. 2(A), when transistors are used for the respective switches, a configuration example of the pixel will be described. FIG. 3(A) shows a configuration example of the pixel 10 when transistors are used as the switch 12 and the switches 15 to 17, respectively.

[0047] The pixel 10 shown in FIG. 3(A) includes a transistor 11, a transistor 12t having the function of the switch 12, transistors 15t to 17t each having the function of the switches 15 to 17, a capacitor element 13, a capacitor element 18, and a light-emitting element 14.

[0048] Specifically, for the transistor 15t, one of the gate is connected to the wiring GLa, one of the source and the drain is connected to the wiring SL, and the other of the source and the drain is connected to the first gate of the transistor 11, respectively, electrically. For the transistor 12t, one of the gate is connected to the wiring GLb, one of the source and the drain is connected to the pixel electrode of the light-emitting element 14, and the other of the source and the drain is connected to the first gate of the transistor 11, respectively, electrically. For the transistor 11, one of the source and the drain is connected to the pixel electrode of the light-emitting element 14, and the other of the source and the drain is connected to the wiring VL, respectively, electrically. For the transistor 16t, one of the gate is connected to the wiring GLb, one of the source and the drain is connected to the wiring BL, and the other of the source and the drain is connected to the first gate of the transistor 11, ​​​​​​​They are each electrically connected to the second gate. Transistor 17t has its gate arranged on wiring GLd, one of the source and drain on wiring IL, and the other of the source and drain electrically connected to the pixel electrode of the light-emitting element 14, respectively.

[0049] Also, one of the pair of electrodes of capacitor element 13 is electrically connected to the second gate of transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14. One of the pair of electrodes of capacitor element 18 is electrically connected to the first gate of transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14. The common electrode

[0050] Next, in pixel 10 shown in FIG. 2(B), a configuration example of the pixel when transistors are used for each switch will be described. A configuration example of pixel 10 shown in FIG. 2(B) when transistors are used for switch 12, switches 15 to 17, and switch 19 is shown in FIG. 3(B).

[0051] Pixel 10 shown in FIG. 3(B) includes transistor 11, transistor 12t having the function of switch 12, transistors 15t to 17t each having the function of switches 15 to 17, transistor 19t having the function of switch 19, capacitor element 13, capacitor element 18, and light-emitting element 14.

[0052] Specifically, transistor 15t has its gate on wiring GLa, one of the source and drain on wiring SL, and the other of the source and drain on the first gate of transistor 11, are electrically connected. The transistor 12t has its gate connected to the wiring GLb, and its source and one of the drains connected to one of the source and drain of the transistor 19t, and the other of the source and drain is connected to the first gate of the transistor 11, respectively. The transistor 11 has one of its source and drain connected to one of the source and drain of the transistor 19t, and the other of the source and drain connected to the wiring VL, respectively. The transistor 16t has its gate connected to the wiring GLb, one of its source and drain connected to the wiring BL, and the other of the source and drain connected to the second gate of the transistor 11, respectively. The transistor 17t has its gate connected to the wiring GLd, one of its source and drain connected to the wiring IL, and the other of the source and drain connected to one of the source and drain of the transistor 19t, respectively. The transistor 19t has its gate connected to the wiring GLc, and the other of the source and drain connected to the pixel electrode of the light-emitting element 14, respectively.

[0053] Also, one of the pair of electrodes of the capacitor element 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to one of the source and drain of the transistor 19t. One of the pair of electrodes of the capacitor element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to one of the source and drain of the transistor 19t. The common electrode of the light-emitting element 14 is electrically connected to the wiring CL.

[0054] Next, regarding the pixel 10 shown in Fig. 2(B), the switch 12 and the switches 15 to 17 Another configuration example of the pixel 10 when using transistors respectively is shown in Fig. 4(A). .

[0055] In the pixel 10 shown in Fig. 4(A), one of the source and drain of the transistor 16t is electrically connected to the wiring VL instead of the wiring BL, which is different in configuration from the pixel 1 0 shown in Fig. 3(B).

[0056] Next, another configuration example of the pixel 10 when using transistors respectively for the switch 12, the switches 15 to 17 and the switch 19 in the pixel 10 shown in Fig. 2(B) is shown in Fig. 4(B). .

[0057] In the pixel 10 shown in Fig. 4(B), the gate of the transistor 17t is electrically connected to the wiring GLa instead of the wiring GLd, which is different in configuration from the pixel 10 shown in Fig. 3(B). .

[0058] 〈Specific operation example 1 of pixel〉 Next, taking the pixel 10 shown in Fig. 3(B) as an example, the operation of the pixel of the light-emitting device according to one aspect of the present invention will be described.

[0059] Fig. 5 shows the timing chart of the potentials input to the wirings GLa to GLd and the timing chart of the potential of the image signal Vdata input to the wiring SL. The timing chart shown in Fig. 5 illustrates the case where all the transistors included in the pixel 10 shown in Fig. 3(B) are n channel type. Also, Figs. 6 and 7 schematically show the operation of the pixel 10 in each period. However, in Figs. 6 and 7, for the sake of clearly showing the operation of the pixel 10, the transistors other than the transistor 11 are illustrated as switches. ​​​​​

[0060] First, in period t1, a low-level potential is applied to wiring GLa, a high-level potential is applied to wiring GLb, a low-level potential is applied to wiring GLc, and a high-level potential is applied to wiring GLd. Therefore, as shown in FIG. 6(A), transistors 12t, tran sistors 16t, and transistor 17t are turned on, and transistors 15t and tran sistor 19t are turned off.

[0061] Also, a potential Vano is applied to wiring VL, a potential V0 is applied to wiring BL, a potential V1 is applied to wiring IL, and a potential Vcat is applied to wiring CL that is electrically connected to the common electrode of light-emitting element 14, respectively. Therefore, a potential V1 is applied to the first gate (denoted as node A) of transistor 11, a potential V0 is applied to the second gate (denoted as node B) of transistor 11, and a potential V1 is applied to one of the source and drain of transistor 11 (denoted as node C).

[0062] The potential Vano is desirably higher than the potential obtained by adding the threshold voltage Vthe of the light-emitting element 14 and the threshold voltage Vth of transistor 11 to the potential Vcat. And the potential V0 is desirably a potential sufficiently higher than that of node C to shift the threshold voltage Vth of transistor 11 in the negative direction. Specifically, as shown in FIG. 9, assuming that the threshold voltage Vth of transistor 11 when Vbg is 0 is Vth0, and the voltage Vbg corresponding to the potential difference between node B and node C is Vbg1. Thereby, in period t1 , the threshold voltage Vth of transistor 11 becomes Vth1. With the above configuration, the transistor Since 11 becomes normal, even if the potential difference between node A and node C, that is, the gate voltage of transistor 11 is 0, transistor 11 can be turned on.

[0063] When transistor 11 is of p-channel type, the potential V0 is a potential sufficiently lower than that of node C to shift the threshold voltage Vth of transistor 11 in the positive direction. With the above configuration, since transistor 11 becomes normal, even if the potential difference between node A and node C, that is, the gate voltage of transistor 11 is 0, transistor 11 can be turned on.

[0064] Next, in period t2, a low-level potential is applied to wiring GLa, a high-level potential is applied to wiring GLb, a low-level potential is applied to wiring GLc, and a low-level potential is applied to wiring GLd. Therefore, as shown in FIG. 6(B), transistors 12t and transistor 16t are turned on, and transistors 15t, 17t, and transistor 19t are turned off.

[0065] Also, a potential Vano is applied to wiring VL and a potential V0 is applied to wiring BL, respectively. Therefore, the state where the potential V0 is applied to node B is maintained, and at the start of period t2 the threshold voltage Vth of transistor 11 remains shifted in the negative direction from Vth1, so transistor 11 is on. And in period t2, since the current path between wiring VL and wiring IL is blocked by switch 17, the potential of node A and node C starts to rise due to the drain current of transistor 11. When the potential of node C rises, node B the potential of node A and node C starts to rise due to the drain current of transistor 11. When the potential of node C rises, node B The voltage Vbg corresponding to the potential difference between the node C and the node becomes low, and the threshold voltage Vt of the transistor 11 h shifts in the positive direction. And finally, when the threshold voltage Vt of the transistor 11 h approaches 0 infinitely, the transistor 11 turns off. The threshold voltage of the transistor 11 Let the potential difference between the node B and the node C when Vth is 0 be V0 - V2.

[0066] That is, when the potential difference between the node B and the node C is V0 - V2, the transistor 11 The threshold voltage Vth is corrected to 0 so that the drain current converges to 0 with respect to the gate voltage 0. The potential difference V0 - V2 between the node B and the node C is applied to the capacitor element 13 is applied. is applied.

[0067] Next, in the period t3, a high-level potential is applied to the wiring GLa, a low-level potential is applied to the wiring GLb, a low-level potential is applied to the wiring GLc, and a high-level potential is applied to the wiring GLd. Therefore, as shown in FIG. 7(A), the transistor 15t and the transistor 17t turn on, and the transistor 12t, the transistor 16t, and the transistor 19t turn off.

[0068] Also, the potential Vano is applied to the wiring VL, the potential Vdata including the image information is applied to the wiring SL is applied, and the potential V1 is applied to the wiring IL. And since the node B is in a floating state, when the node C changes from the potential V2 to the potential V1, the capacitor element 13 causes the node B to change from the potential V0 to the potential V0 + V1 - V2. And since the potential difference V0 - V2 is held in the capacitor element 13 the threshold voltage Vth of the transistor 11 is 0 is maintained. Also, a potential Vdata is applied to node A, and the gate voltage of transistor 11 becomes Vdata - V1.

[0069] Next, in period t4, a low-level potential is applied to wiring GLa, a low- level potential is applied to wiring GLb, a high-level potential is applied to wiring GLc, and a low- level potential is applied to wiring GLd. Therefore, as shown in FIG. 7(B), transistor 19t turns on and transistors 12t, 15t, 16t, and 17t turn off.

[0070] Also, a potential Vano is applied to wiring VL, and a potential Vcat is applied to wiring CL that is electrically connected to the common electrode of light-emitting element 14. In period t4, when transistor 19t turns on, the potential of node C fluctuates and becomes potential V3. Then, node A becomes potential Vdata + V3 - V1, and node B becomes potential V0 - V2 + V3. Even when the potentials of node A, node B, and node C change, the potential difference V0 - V2 is maintained across capacitor element 13, and the potential difference Vdata - V1 is maintained across capacitor element 18. Then, a drain current corresponding to the gate voltage of transistor 11 flows between wiring VL and wiring CL. The luminance of light-emitting element 14 is determined according to the value of the above drain current.

[0071] In the light-emitting device having pixel 10 shown in FIG. 3(B), since the other of the source and drain of transistor 11 and the second gate of transistor 11 are electrically separated, their respective potentials can be controlled individually. Therefore, transistor 11 is in the normal When it is on, that is, when the original threshold voltage Vth0 of the transistor 11 has a negative value When it has, until one of the source and drain of the transistor 11 becomes higher than the potential V0 of the second gate in the period t2, It is possible to accumulate charge in the capacitive element 13. Therefore, in the light-emitting device according to one aspect of the present invention, even if the transistor 11 is normally on, In the period t2, the threshold voltage Vth can be corrected to 0 so that the drain current converges to 0 with respect to the gate voltage 0.

[0072] Therefore, in the pixel 10 shown in FIGS. 3(A), 3(B), and 4(B), in which the other of the source and drain of the transistor 11 is electrically separated from the second gate of the transistor 11, Even when the transistor 11 is normally on, for example, when an oxide semiconductor is used for the semiconductor film of the transistor 11, display unevenness can be reduced and high-quality display can be performed.

[0073] Note that FIGS. 2(A) and 2(B) etc. are shown as examples of the circuit configuration, but one aspect of the present invention is not limited to this. For example, the switch can be arranged at various positions. For example, in the case of FIG. 6(A), it has a configuration as shown in FIG. 36(A), and in the case of FIG. 6(B), it has a configuration as shown in FIG. 36(B), in the case of FIG. 7(A), it has a configuration as shown in FIG. 37(A), and in the case of FIG. 7(B), it may have a configuration as shown in FIG. 37(B). In each case, the switch may be arranged at an appropriate position so as to have such a configuration.

[0074] The above is the pixel 1 including correction of the threshold voltage (hereinafter referred to as internal correction) in the pixel 10.​​​​​​​ This corresponds to the operation example of 0. Next, in addition to internal correction, for the variation in luminance between pixels caused by the variation in threshold voltage, when suppressing it by correcting the image signal (hereinafter referred to as external correction), the operation of pixel 10 will be described.

[0075] Taking pixel 10 shown in Fig. 3(B) as an example, when performing external correction in addition to internal correction, the wiring The timing chart of the potential input to wirings GLa to GLd and the potential of the image signal Vdata input to wiring SL are shown in Fig. 8. Note that the timing chart shown in Fig. 8 illustrates the case where all the transistors included in pixel 10 shown in Fig. 3(B) are n-channel type.

[0076] First, from period t1 to period t4, similar to the timing chart shown in Fig. 5, pixel 10 operates according to the above description.

[0077] Next, in period t5, a low-level potential is applied to wiring GLa, a low-level potential is applied to wiring GLb, a low-level potential is applied to wiring GLc, and a high-level potential is applied to wiring GLd. Thus, transistor 17t turns on, and transistors 12 t, 15t, 16t, and 19t turn off.

[0078] Also, potential Vano is applied to wiring VL, and potential V1 is applied to wiring IL, respectively. Furthermore, wiring IL is electrically connected to the monitor circuit.

[0079] By the above operation, the drain current of transistor 11 is supplied to the monitor circuit through transistor 17t and wiring IL . The monitor circuit monitors the drain current flowing through wiring IL Using , a signal including the value of the drain current as information is generated. And in one aspect of the light-emitting device according to the present invention, using the above signal, the potential V of the image signal supplied to the pixel 10 data can be corrected.

[0080] Note that the operation of the external correction performed during the period t5 does not always need to be performed after the period t4. For example, in the light-emitting device, after repeating the operations of the periods t1 to t4 a plurality of times, the operation of the period t5 may be performed. Also, after performing the operation of the period t5 in the pixels 10 of one row, the image signal corresponding to the minimum gradation value 0 is written to the pixels 10 of the row where the operation has been performed. After turning off the light-emitting elements 14, the operation of the period t5 may be performed in the pixels 10 of the next row.

[0081] Note that even when performing external correction without performing internal correction, not only the variation in the threshold voltage of the transistor 11 existing between the pixels 10 but also the variation in the electrical characteristics of the transistor 11 other than the threshold voltage, such as mobility, can be corrected. However, when performing internal correction in addition to external correction, the correction of the negative shift or positive shift of the threshold voltage is performed by internal correction. Therefore, in external correction, it is only necessary to correct the variation in the electrical characteristics of the transistor 11 other than the threshold voltage, such as mobility. Therefore, when performing internal correction in addition to external correction, the amplitude of the potential of the image signal after correction can be made smaller than when performing only external correction. Therefore, since the amplitude of the potential of the image signal is too large, the potential difference of the image signal between gradation values becomes large, and the change in luminance in the image becomes a smooth gradation. ​​​​​​​​​​It is possible to prevent a situation where it becomes difficult to represent by ョン and prevent a deterioration in image quality. It can be prevented.

[0082] In addition, in the case of the pixel 10 shown in Fig. 3(A) as well, according to the timing chart of the potentials applied to the wiring GLa, wiring GL b, wiring GLd, and wiring SL shown in Fig. 5 or Fig. 8, it can be operated in the same manner. However, in the case of the pixel 10 shown in Fig. 3(A), in the period t2 , the potential V0 is set to be lower than the potential obtained by adding the threshold voltage Vthe of the light-emitting element 14 and the threshold voltage Vth of the transistor 15t to the potential Vca t so that the drain current of the transistor 11 does not flow into the light-emitting element 14. This is desirable.

[0083] Also, in the case of the pixel 10 shown in Fig. 4(A), according to the timing chart of the potentials applied to the wiring GLa, wiring GL b, wiring GLc, wiring GLd, and wiring SL shown in Fig. 5 or Fig. 8, it can be operated in the same manner.

[0084] Also, in the case of the pixel 10 shown in Fig. 4(B), according to the timing chart of the potentials applied to the wiring GLa, wiring GL b, wiring GLc, and wiring SL shown in Fig. 5 or Fig. 8, it can be operated in the same manner.

[0085] Note that, for example, in a case where no external correction is performed, the wiring IL may be connected to the wiring CL. Alternatively, the wiring IL may be omitted by combining the wiring IL and the wiring CL into one. Thereby, the number of wirings can be reduced. As an example, an example of the case where the wiring IL is omitted in Fig. 2(A) is shown in Fig. 38(A). Similarly, when applied to Fig. 2(B) , an example is shown in Fig. 38(B). ​​An example of the case is shown in FIG. 38(B). It can be similarly applied to other drawings.

[0086] <Example of the configuration of the pixel portion and the selection circuit> Next, FIG. 10 shows, as an example, the configuration of the pixel portion of a light-emitting device according to one aspect of the present invention. In FIG. 10, the pixel portion 40 has a plurality of pixels 10 arranged in a matrix. Further, the pixel portion 40 includes at least wiring GL, wiring SL, wiring VL, wiring BL, wiring IL, and wiring CL (not shown). Each of the plurality of pixels 10 is electrically connected to at least one of the wiring GL, at least one of the wiring SL, at least one of the wiring VL, at least one of the wiring BL, at least one of the wiring IL, and the wiring CL, respectively.

[0087] Note that the types and the number of the above wirings can be determined by the configuration, the number, and the arrangement of the pixels 10. Specifically, in the case of the pixel portion 40 shown in FIG. 10, the pixels 10 of x columns × y rows are electrically connected in a matrix. Then, a plurality of wirings GL indicated by wiring GL1 to wiring GLy, a plurality of wirings SL indicated by wiring SL1 to wiring SLx, a plurality of wirings VL indicated by wiring VL1 to wiring VLx, a plurality of wirings BL indicated by wiring BL1 to wiring BLx, a plurality of wirings IL indicated by wiring IL1 to wiring ILx, and one wiring CL are arranged in the pixel portion 40. This is an example of the case. And each wiring GL shown in FIG. 10 includes all or any plurality of wiring GLa, wiring GLb, wiring GLc, or wiring GLd.

[0088] Note that, as shown in FIG. 10, when the pixels 10 are connected in a matrix, in a certain row, it is assumed that each wiring GL shown in FIG. 10 includes all or any plurality of wiring GLa, wiring GLb, wiring GLc, or wiring GLd.

[0089] Note that, as shown in FIG. 10, when the pixels 10 are connected in a matrix, When, for example, operations such as those in FIGS. 6(A), 6(B), and 7(B) are being performed, separately in another row, for example, the operation of FIG. 7(A) can be performed. Therefore, operations such as those in FIG. 6(A) or FIG. 6(B) can be executed over a sufficiently long period. As a result, correction can be performed with high accuracy.

[0090] If the operations such as those in FIGS. 6(A) and 6(B) and the operation such as that in FIG. 7(A) are not performed simultaneously in separate rows, for example, wiring BL may be connected to wiring SL. Or, for example , by combining wiring BL and wiring SL into one, wiring BL may be omitted. This can reduce the number of wirings. As an example, in FIG. 2(A), an example of the case where wiring BL is omitted is shown in FIG. 39(A). Similarly, an example of the case when applied to FIG. 2(B) is shown in FIG. 39(B). The same can be applied to other drawings.

[0091] Also, in FIG. 7(A) etc., during the period when the potential Vdata of the image signal is input, since the operation of applying the potential difference V0 - V2 between node B and node C as shown in FIG. 6(B) to the capacitor element 13 is not performed, in FIG. 7(A) etc., the potential Vdata of the image signal can be input to the pixels in a dot sequential manner. An example of that case is shown in FIG. 40. Switches 60A, switches 60B, switches 60C, etc. are turned on in sequence while being controlled by circuit 61 . As a result, dot sequential driving can be performed. Here, circuit 61 has a function of being able to output a waveform that is shifted one by one . For example, circuit 61 has a function as a shift register . Therefore, switches 60A, switches 60B, switches 6 0C, Circuit 61 can also be said to have the function as a source line driving circuit.

[0092] Or, as another example, among a plurality of wirings SL indicated by wirings SL1 to SLx, among the plurality of wirings therein, any one wiring may be selected and the potential Vdata of the image signal may be input. For example, wiring SL1 and wiring SL2 may be selected by switch 62A and switch 62B, and wiring SL3 and wiring SL4 may be selected by switch 62C and switch 6 2D. An example in this case is shown in FIG. 41. In FIG. 41, when wiring 63A is selected, switch 62A and switch 62C are turned on, and when wiring 63B is selected, switch 62B and switch 62D etc. are turned on. Here, an example of selecting one wiring from two wirings SL is shown, but one aspect of the present invention is not limited to this. One wiring may be selected from more wirings SL.

[0093] Next, an example of the connection configuration of the pixel portion 40 and the selection circuit 41 of a light-emitting device having a function of performing external correction is shown in FIG. 11. The selection circuit 41 has a function of selecting either one of the wiring 42 to which the potential V1 is applied and the connection terminal TER of the monitor circuit. Either one of the selected wiring 42 and the connection terminal TER and the wiring IL can be brought into a conductive state. Specifically, the selection circuit 41 shown in FIG. 11 includes a switch 43 that controls the supply of the potential V1 of the wiring 42 to one wiring IL, and a switch 44 that controls the conductive state between the one wiring IL and the connection terminal TER.

[0094]

[0095] <Example of the configuration of the monitor circuit> Next, a configuration example of the monitor circuit 45 is shown in FIG. 12. The monitor circuit 45 shown in FIG. 12 includes an operational amplifier 46, a capacitive element 47, and a switch 48.

[0096] One of the pair of electrodes of the capacitive element 47 is connected to the inverting input terminal (−) of the operational amplifier 46 and the other of the pair of electrodes of the capacitive element 47 is connected to the output terminal of the operational amplifier 46. The switch 48 has a function of discharging the charge stored in the capacitive element 47, and specifically has a function of controlling the electrical conduction state between the pair of electrodes of the capacitive element 47. The non-inverting input terminal (+) of the operational amplifier 46 is connected to a wiring 49, and a potential V1 is supplied to the wiring 49.

[0097] In one aspect of the present invention, in order to perform internal correction, when supplying the potential V1 to the wiring IL of the pixel 10, the monitor circuit 45 is made to function as a voltage follower. Specifically, by turning on the switch 48, the potential V1 supplied to the wiring 49 can be supplied to the wiring IL via the monitor circuit 45.

[0098] Also, in order to perform external correction, when extracting a current from the pixel 10 via the wiring IL, first, by making the monitor circuit 45 function as a voltage follower, the potential V1 is supplied to the wiring IL, and then, by making the monitor circuit 45 function as an integrating circuit, the current extracted from the pixel 10 is converted into a voltage. Specifically, by turning on the switch 48, the potential V1 supplied to the wiring 49 is supplied to the wiring IL via the monitor circuit 45, and then the switch 48 is turned off. In a state where the switch 48 is off, the drain extracted from the pixel 10 When an in-current is supplied to the wiring TER, charges are accumulated in the capacitive element 47, and a voltage is generated between a pair of electrodes that the capacitive element 47 has. Since the above voltage is proportional to the total amount of the drain current supplied to the wiring TER, a potential corresponding to the total amount of the drain current within a predetermined period is given to the wiring OUT connected to the output terminal of the operational amplifier 46.

[0099] 〈Specific Configuration Example 2 of Pixel〉 FIG. 13(A) shows, as an example, a specific configuration of the pixel 10 shown in FIG. 1.

[0100] The pixel 10 shown in FIG. 13(A) includes, in addition to the transistor 11, the capacitive element 13, and the light-emitting element 14, switches 15 to 17 and a capacitive element 18.

[0101] Specifically, in the pixel 10 shown in FIG. 13(A), the wiring SL is electrically connected to the first gate of the transistor 11 via the switch 15. One of the source and the drain of the transistor 11 is electrically connected to the pixel electrode of the light-emitting element 14, and the other of the source and the drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL via the switch 16. The pixel electrode that the light-emitting element 14 has is electrically connected to the wiring IL via the switch 17. One of the pair of electrodes that the capacitive element 13 has is electrically connected to the second gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14. One of the pair of electrodes that the capacitive element 18 has is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14. The common electrode of the light-emitting element 14 is electrically connected to the wiring CL. ​

[0102] Next, FIG. 13B shows another specific configuration of the pixel 10 shown in FIG. .

[0103] The pixel 10 shown in FIG. 13(B) is similar to the pixel 10 shown in FIG. 13(A) in that it further includes a switch 19. 1. The pixel 10 shown in FIG.

[0104] Specifically, in the pixel 10 shown in FIG. 13B, the line SL is connected to a transistor via a switch 15. The transistor 11 is electrically connected to a first gate of the transistor 11. The transistor 11 has a source and One of the drains is electrically connected to the pixel electrode of the light emitting element 14 via a switch 19. The other of the source and the drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL via the switch 16. The pixel electrode of the element 14 is electrically connected to the wiring IL via the switch 17 and the switch 19. The capacitor 13 has a pair of electrodes, one of which is connected to the second The other is electrically connected to the pixel electrode of the light-emitting element 14 via a switch 19. The capacitor 18 has a pair of electrodes, one of which is electrically connected to a transistor. The other terminal is electrically connected to the first gate of the light-emitting element 1 through the switch 19. The common electrode of the light emitting element 14 is electrically connected to the wiring CL. is connected to

[0105] Next, in the pixel 10 shown in FIG. 13A, when transistors are used for each switch, An example of the pixel configuration will be described. FIG. 14 shows a configuration example of the pixel 10 when transistors are used as the switches 17 respectively. A).

[0106] The pixel 10 shown in FIG. 14(A) includes a transistor 11, switches 15 to 17, and transistors 15t to 17t each having the functions of the switches 15 to 17, a capacitive element 1 3, a capacitive element 18, and a light-emitting element 14.

[0107] Specifically, for the transistor 15t, one of the source and drain is electrically connected to the wiring GLa, the other of the source and drain is electrically connected to the wiring SL, and the other of the source and drain is electrically connected to the first gate of the transistor 11. For the transistor 11, one of the source and drain is electrically connected to the pixel electrode of the light-emitting element 1 4, and the other of the source and drain is electrically connected to the wiring VL. For the transistor 16t, one of the source and drain is electrically connected to the wiring GLb, the other of the source and drain is electrically connected to the wiring BL, and the other of the source and drain is electrically connected to the second gate of the transistor 11. For the transistor 17t, one of the source and drain is electrically connected to the wiring GLd, the other of the source and drain is electrically connected to the wiring IL, and the other of the source and drain is electrically connected to the pixel electrode of the light-emitting element 14.

[0108]

[0109] One of the pair of electrodes of the capacitive element 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14. One of the pair of electrodes of the capacitive element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light-emitting element 14. The common electrode of the light-emitting element 14 is electrically connected to the wiring CL.

[0109]

[0109] Next, in pixel 10 shown in FIG. 13(B), when transistors are used for each switch a configuration example of the pixel will be described. For the pixel 10 shown in FIG. 13(B), when transistors are used for switches 15 to switch 17 and switch 19 respectively, a configuration example of pixel 10 is shown in FIG. 14(B).

[0110] Pixel 10 shown in FIG. 14(B) includes transistor 11, switches 15 to 17 and transistors 15t to 17t each having the functions thereof, switch 1 9 and transistor 19t having the function thereof, capacitor element 13, capacitor element 18, and light-emitting element 14.

[0111] Specifically, for transistor 15t, one of the gate is connected to wiring GLa, one of the source and drain is connected to wiring SL, and the other of the source and drain is electrically connected to the first gate of transistor 11 respectively. For transistor 11, one of the source and drain is connected to one of the source and drain of transistor 19t, and the other of the source and drain is connected to wiring VL respectively. For transistor 16t, the gate is connected to wiring GLb, one of the source and drain is connected to wiring BL, and the other of the source and drain is electrically connected to the second gate of transistor 11 respectively. For transistor 17t, the gate is connected to wiring GL d, one of the source and drain is connected to wiring IL, and the other of the source and drain is electrically connected to one of the source and drain of transistor 19t respectively. For transistor 19t, the gate is connected to wiring GLc, and the other of the source and drain is electrically connected to the pixel electrode of light-emitting element 14 respectively. ​​​

[0112] Also, one of the pair of electrodes of the capacitive element 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to one of the source and drain of the transistor 19t. One of the pair of electrodes of the capacitive element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to one of the source and drain of the transistor 19t. The common electrode of the light-emitting element 14 is electrically connected to the wiring CL.

[0113] Next, FIG. 15(A) shows another configuration example of the pixel 10 when transistors are used as the switches 15 to 17 of the pixel 10 shown in FIG. 13(B).

[0114] The pixel 10 shown in FIG. 15(A) differs in configuration from the pixel 10 shown in FIG. 14(B) in that one of the source and drain of the transistor 16t is electrically connected to the wiring VL instead of the wiring BL.

[0115] Next, FIG. 15(B) shows another configuration example of the pixel 10 when transistors are used as the switches 15 to 17 and the switch 19 of the pixel 10 shown in FIG. 13(B).

[0116] The pixel 10 shown in FIG. 15(B) differs in configuration from the pixel 10 shown in FIG. 14(B) in that the gate of the transistor 17t is electrically connected to the wiring GLa instead of the wiring GLd.

[0117] <Specific Operational Example 2 of Pixel> Next, taking the pixel 10 shown in FIG. 14(B) as an example, the light-emitting device according to one aspect of the present invention ​​​​​​​​​​The operation of the pixel will now be described.

[0118] FIG. 16 is a timing chart of potentials input to the wirings GLa to GLd and a timing chart of potentials input to the wirings S FIG. 1 shows a timing chart of the potential of the image signal Vdata input to the input terminal L. The timing chart shown in FIG. 6 is based on the transistor included in the pixel 10 shown in FIG. This is an example in which all are n-channel types.

[0119] First, in a period t1, a high-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A potential of the line GLc is applied to the line GLd, a low-level potential is applied to the line GLc, and a high-level potential is applied to the line GLd. Therefore, the transistors 15t, 16t, and Transistor 17t is turned on and transistor 19t is turned off.

[0120] In addition, the wiring SL is applied with a potential V4, the wiring VL is applied with a potential Vano, and the wiring BL is applied with a potential V0. The wiring IL is connected to a potential V1, and the wiring CL is connected to a common electrode of the light-emitting element 14. The potential Vcat is applied to the first gate ( A potential V4 is applied to the second gate of the transistor 11 (denoted as node B A potential V0 is applied to one of the source and drain of the transistor 11 (node A potential V1 is applied to a terminal C.

[0121] The potential Vano is a potential Vcat plus the threshold voltage Vthe of the light emitting element 14 and the transistor 11 It is desirable to set the potential higher than the sum of the threshold voltage Vth of the potential V0 is set to a value at node C such that the threshold voltage Vth of transistor 11 is shifted in the negative direction. It is desirable that it be at a sufficiently high potential with respect to. Specifically, as shown in FIG. 9, assuming that the threshold voltage Vth of the transistor 11 when Vbg g is 0 is Vth0, in the period t1, the voltage Vbg corresponding to the potential difference between the node B and the node C is set to Vbg1, and thereby the threshold voltage Vth of the transistor 11 is set to Vth1. With the above configuration, since the transistor 11 becomes normally on, even if the potential difference between the node A and the node C, that is, the gate voltage of the transistor 11 is V4 - V1, the transistor 11 can be turned on.

[0122] In addition, when the transistor 11 is of p-channel type, the potential V0 is sufficiently low with respect to the node C to the extent that the threshold voltage Vth of the transistor 11 is shifted in the positive direction. With the above configuration, since the transistor 11 becomes normally on, even if the potential difference between the node A and the node C, that is, the gate voltage of the transistor 11 is V4 - V1, the transistor 11 can be turned on.

[0123] Next, in the period t2, a low-level potential is applied to the wiring GLa, a high-level potential is applied to the wiring GLb, a low-level potential is applied to the wiring GLc, and a low-level potential is applied to the wiring GLd. Therefore, the transistor 16t is turned on, and the transistors 15 t, 17t, and 19t are turned off.

[0124] Also, the potential Vano is applied to the wiring VL and the potential V0 is applied to the wiring BL, respectively. Therefore, the state where the potential V0 is applied to the node B is maintained, and at the start of the period t2 ​Since the threshold voltage Vth of transistor 11 remains shifted in the negative direction from Vth1, , transistor 11 is on. And in period t2, since the current path between wiring VL and wiring IL is blocked by switch 17, the potentials of node A and node C start to rise due to the drain current of transistor 11. When the potential of node C rises, the voltage Vbg corresponding to the potential difference between node B and node C becomes low, and the threshold voltage Vth of transistor 11 shifts in the positive direction. And finally, when the threshold voltage Vth of transistor 11 approaches infinitely close to the gate voltage V4 - V1 of transistor 11, transistor 11 turns off. Let the potential difference between node B and node C be V0 - V2 when the threshold voltage Vth of transistor 11 is V4 - V1. That is, transistor 11 has its threshold voltage Vth corrected to V4 - V1 so that the drain current converges to 0 with respect to the gate voltage V4 - V1 when the potential difference between node B and node C is V0 - V2. The potential difference V0 - V2 between node B and node C is applied to the capacitive element 13.

[0125]

[0126] Next, in period t3, a high-level potential is applied to wiring GLa, a low-level potential is applied to wiring GLb, a low-level potential is applied to wiring GLc, and a high-level potential is applied to wiring GLd. Thus, transistors 15t and 17t turn on, and transistors 16t and 19t turn off.

[0127] Also, potential Vano is applied to wiring VL, and potential Vdata containing image information is applied to wiring SL. Potential V1 is applied to each of the wirings IL. Since node B is in a floating state, when the potential of node C changes from potential V2 to potential V1, node B changes from potential V0 to potential V0 + V1 - V2 due to the capacitor element 13. Since the potential difference V0 - V2 is held in the capacitor element 13, the threshold voltage Vth of the transistor 11 is maintained at V4 - V1. Also, potential Vdata is applied to node A, and the gate voltage of the

[0128] transistor 11 becomes Vdata - V1. Next, in period t4, a low-level potential is applied to the wiring GLa, a low- level potential is applied to the wiring GLb, a high-level potential is applied to the wiring GLc, and a low-level potential is applied to the wiring GLd.

[0129] Therefore, the transistor 19t turns on, and the transistors 15t, 16t, and 17t turn off. Also, potential Vano is applied to the wiring VL, and potential Vcat is applied to the wiring CL which is electrically connected to the common electrode of the light-emitting element 14. In period t4, when the transistor 19t turns on and the potential of node C fluctuates and becomes potential V3, node A becomes potential Vdata + V3 - V1, and node B becomes potential V0 -

[0130] V2 + V3. Even when the potentials of node A, node B, and node C change, the potential difference V0 - V2 is held in the capacitor element 13, and the potential difference Vdata - V1 is held in the capacitor element 18. And a drain current corresponding to the gate voltage of the transistor 11 flows between the wiring VL and the wiring CL. The luminance of the light-

[0130] emitting element 14 is determined according to the value of the above drain

[0130] current.

[0130] In the light-emitting device having the pixel 10 shown in FIG. The other of the drains is electrically isolated from the second gate of the transistor 11. Therefore, the transistor 11 can be controlled to have a normal When the transistor 11 is turned on, that is, when the original threshold voltage Vth0 of the transistor 11 is a negative value, In the case where one of the source and drain of the transistor 11 is Charge is stored in the capacitance element 13 until the potential becomes higher than the potential V0 of the second gate. Therefore, in the light-emitting device according to one embodiment of the present invention, the transistor 11 is a normally-off transistor. Even in the case of the MOSFET, the drain current converges to 0 for the gate voltage V4-V1 during the period t2. In order to bundle, the threshold voltage Vth can be corrected to V4-V1.

[0131] Therefore, the other of the source and drain of the transistor 11 and the second The gate of the transistor is electrically isolated from the gate of the transistor shown in FIG. 14(A), FIG. 14(B), and FIG. 15(B). In a light-emitting device having a pixel 10, for example, an oxide semiconductor is used for the semiconductor film of a transistor 11. Even if the transistor 11 becomes normally on when the This allows for high quality display.

[0132] The above corresponds to an example of the operation of the pixel 10 including the internal correction. Next, in addition to the internal correction, When the brightness variation between pixels 10 caused by the variation in the threshold voltage is suppressed by external correction, The operation of the pixel 10 in this case will be described.

[0133] Taking the pixel 10 shown in FIG. 14B as an example, when external correction is performed in addition to internal correction, during the period From t1 to t4, the timing chart shown in FIG. 16 is the same as that shown in the above description. The pixel 10 operates in this manner.

[0134] Next, in a period t5 after the period t4, a low-level potential is applied to the line GLa, and A low-level potential is applied to the wiring Lb, a low-level potential is applied to the wiring GLc, and a low-level potential is applied to the wiring G A high-level potential is applied to Ld. This turns on the transistor 17t. Transistor 15t, transistor 16t, and transistor 19t are turned off.

[0135] A potential Vano is applied to the wiring VL, and a potential V1 is applied to the wiring IL. Furthermore, the wiring IL is electrically connected to a monitor circuit.

[0136] By the above operation, the drain current of the transistor 11 is The monitor circuit detects the drain current flowing through the line IL. A signal including the value of the drain current as information is generated using the above-mentioned. In the light emitting device according to the embodiment, the potential V of the image signal supplied to the pixel 10 is controlled by using the above signal. The data value can be corrected.

[0137] It should be noted that the external correction operation performed during the period t5 does not always need to be performed after the period t4. For example, in a light emitting device, after the operation of the periods t1 to t4 is repeated several times, The operation for the period t5 may be performed in the pixels 10 of one row. After this, an image signal corresponding to the minimum gradation value 0 is written to the pixels 10 in the row in which this operation was performed. After the light-emitting element 14 is put into a non-emitting state by writing the You may also perform the operation of t5.

[0138] In the case of the pixel 10 shown in FIG. 14(A) as well, it can be operated in the same manner according to the timing chart of the potentials applied to the wiring GLa, wiring GLb, wiring GLd, and wiring SL shown in FIG. 16. Also, the operation of external correction can be performed in the same manner as the pixel shown in FIG. 14(B). However, in the case of the pixel 10 shown in FIG. 14(A), in the period t2, the potential V0 is made lower than the potential obtained by adding the threshold voltage Vthe of the light-emitting element 14 and the threshold voltage Vth of the transistor 15t to the potential Vcat so that the drain current of the transistor 11 does not flow through the light-emitting element 14.

[0139] In the case of the pixel 10 shown in FIG. 15(A) as well, it can be operated in the same manner according to the timing chart of the potentials applied to the wiring GLa, wiring GLb, wiring GLc, wiring GLd, and wiring SL shown in FIG. 16. Also, the operation of external correction can be performed in the same manner as the pixel shown in FIG. 14(B).

[0140] In the case of the pixel 10 shown in FIG. 15(B) as well, it can be operated in the same manner according to the timing chart of the potentials applied to the wiring GLa, wiring GLb, wiring GLc, and wiring SL shown in FIG. 16. Also, the operation of external correction can be performed in the same manner as the pixel shown in FIG. 14(B).

[0141] <Example Configuration 1 of Transistor> Next, a transistor (OS transistor) in which a channel formation region is formed of an oxide semiconductor film will be described.

[0142] ​​​​​​​​​​​​​Figures 27(A), 27(B) and 27(C) show top views (layout diagrams) of three transistors (TA1, TA2, TB1) with different device structures, along with their respective circuit symbols. Figure 28 is a cross-sectional view of the transistors (TA1, TA2, TB1). Cross-sectional views of the transistors TA1 along lines a1 - a2 and b1 - b2, TA2 along lines a3 - a4 and b3 - b4, and TB1 along lines a5 - a6 and b5 - b6 are shown in Figures 28(A) and 28(B). The cross-sectional structure of these transistors in the channel length direction is shown in Figure 28(A), and the cross-sectional structure in the channel width direction is shown in Figure 28(B). As shown in Figures 28(A) and 28(B), the transistors (TA1, TA2, TB1) are integrated on the same insulating surface and can be fabricated in the same manufacturing process. Here, for clarity of the device structure, the electrical connections to the gates (G), sources (S), and drains (D) of each transistor, as well as the wiring for supplying power, are omitted. The transistors TA1 (Figure 27(A)) and TA2 (Figure 27(B)) are transistors having a gate (G) and a back gate (BG). Either one of the gate (G) and the back gate (BG) corresponds to the first gate, and the other corresponds to the second gate. The transistors TA1 and TA2 have a structure in which the back gate is connected to the gate. The transistor TB1 (Figure 27(C)) is a transistor without a BG. As shown in Figure 28, these transistors (TA1, TA2, TB1) are on the substrate 30.

[0143]

[0144] ​ They are formed. Hereinafter, with reference to FIGS. 27 and 28, the configuration of these transistors will be described .

[0145] (Transistor TA1) Transistor TA1 has a gate electrode GE1, a source electrode SE1, a drain electrode DE1, a back gate electrode BGE1, and an oxide semiconductor film OS1.

[0146] In the following description, transistor TA1 is referred to as TA1, the back gate is referred to as BG, the oxide semiconductor film OS1 is referred to as OS1 or film OS1, etc., and elements or components of the elements may be omitted when referring. Also, signals, potentials, circuits, etc. may be omitted in the same way.

[0147] Also, in this embodiment, the channel length of the OS transistor is the distance between the source electrode and the drain electrode . Also, the channel width of the OS transistor is the width of the source electrode or the drain electrode in the region where the oxide semiconductor film and the gate electrode overlap. The channel length of transistor TA1 is La1, and the channel width is Wa1.

[0148] Film OS1 overlaps electrode GE1 via insulating film 34. A pair of electrodes (SE1, DE1) are formed in contact with the upper surface and the side surface of film OS1. As shown in FIG. 27(A), film OS1 has a portion that does not overlap electrode GE1 and the pair of electrodes (SE1, DE1). Film OS1 has a length in the channel length direction that is longer than the channel length La1, and a length in the channel width direction that is longer than the channel width Wa1.

[0149] An insulating film 35 is formed covering film OS1, electrode GE1, electrode SE1, and electrode DE1. It exists. The electrode BGE1 is formed on the insulating film 35. The electrode BGE1 is provided so as to overlap with the electrode GE1. Here, as an example, the electrode BGE1 is provided to have the same shape and be arranged at the same position as the electrode GE1. The electrode BGE1 is in contact with the electrode GE1 at the opening CG1 that penetrates the insulating films 34, 35, and 36. Due to this structure, the gate and the back gate of the transistor TA1 are electrically connected. .

[0150] By connecting the back gate electrode BGE1 to the gate electrode GE1, the on-current of the transistor TA1 can be increased. By providing the back gate BGE1, the strength of the transistor TA1 can be improved. Against deformation such as bending of the substrate 30, the electrode BGE1 can serve as a reinforcing member to make the transistor TA1 less likely to break.

[0151] The film OS1 including the channel formation region has a multilayer structure. Here, as an example, it has a three-layer structure composed of three oxide semiconductor films (31, 32, 33). The oxide semiconductor films constituting the film OS1 are preferably metal oxide films containing at least one same metal element, and particularly preferably contain In. As the metal oxide containing In that can constitute the semiconductor film of the transistor, In-Ga oxide film, In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd) is typical. Also, a film obtained by adding other elements or materials to such a metal oxide film can also be used.

[0152] '32' is the film constituting the channel formation region of the transistor TA1. Also, '33' " constitutes the channel forming regions of the transistor TA2 and the transistor TB1 described later. Therefore, the required thickness of the transistor TA2 and the transistor TB1 is Depending on the electrical properties (e.g., field effect mobility, threshold voltage, etc.), oxides of appropriate composition are selected. For example, an oxide semiconductor film can be used so that a channel is formed at "33". It is preferable to adjust the composition of the metal elements that are the main components of the conductor films 31-32.

[0153] In the transistor TA1, a channel is formed at "32". This can prevent the panel formation region from contacting the insulating films 34 and 35. By making the body films 31 and 32 metal oxide films containing at least one of the same metal elements, At the interface between 『31』 and 『32』 and 『33』, interface scattering is unlikely to occur. This allows the field effect mobility of the transistor TA1 to be reduced. It can be made higher than TA2 and transistor TB1, and the drain voltage in the on state The current (on-current) can be increased.

[0154] (Transistor TA2) The transistor TA2 includes a gate electrode GE2, a source electrode SE2, a drain electrode DE2, and a The gate electrode BGE2 and the oxide semiconductor film OS2 are insulating The electrode GE2 is in contact with the opening CG2 penetrating the film 34 through the insulating film 36. The transistor TA2 is a modification of the transistor TA1, in which the film OS2 is not an oxide semiconductor film 33. The transistor TA1 is different from the transistor TA1 in that it has a single-layer structure. Then, the channel length La2 and the channel width Wa2 of the transistor TA2 are It is made equal to the channel length La1 and the channel width Wa1 of 1.

[0155] (Transistor TB1) Transistor TB1 has a gate electrode GE3, a source electrode SE3, a drain electrode DE3, and an oxide semiconductor film OS3. Transistor TB1 is a modified example of transistor TA2. Similar to transistor TA2, the film OS3 has a single-layer structure where it is not the oxide semiconductor film 33. It differs from transistor TA2 in that it does not have a back gate electrode. Also, the layout of the film OS3 and the electrodes (GE3, SE3, DE3) is different. As shown in FIG. 27(C), the region where the film OS3 does not overlap with the electrode GE3 overlaps with either the electrode SE3 or the electrode DE 3. Therefore, the channel width Wb1 of transistor TB1 is determined by the width of the film O S3. The channel length Lb1 is determined by the distance between the electrode SE 3 and the electrode DE3, and here it is made longer than the channel length La2 of transistor TA2.

[0156] [Insulating film] The insulating films 34, 35, and 36 are films formed over the entire region where the transistors (TA1, TA2 , TB1) on the substrate 30 are formed. The insulating films 34, 35, and the insulating film 36 are formed of a single-layer or multiple-layer insulating film. The insulating film 34 is a film that constitutes the gate insulating film of the transistors (TA1, TA2, TB1). Also, the insulating film 35 and the insulating film 36 are films that constitute the gate insulating film on the back channel side of the transistors (TA1, TA2, TB1). Also, the topmost insulating film 36 is the insulating film formed on the substrate 30 for the transistors It is preferably formed of a material that functions as a protective film for the resistor. The insulating film 36 may be provided as appropriate. To insulate the third electrode BGE1 and the second electrodes (SE1, DE1), it is sufficient that there is at least one insulating film between them.

[0157] The insulating films 34 to 36 can be formed of a single insulating film or a multi-layer insulating film of two or more layers. Examples of the insulating films constituting these insulating films 34 to 36 include films made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. Further, these insulating films can be formed using a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

[0158] [Oxide semiconductor film] Here, the oxide semiconductor film constituting the semiconductor film of the OS transistor will be described. When the semiconductor film has a multi-layer structure as in film OS1, the oxide semiconductor films constituting these are preferably metal oxide films containing at least one same metal element, and preferably contain In.

[0159] For example, when '31' is an In-Ga oxide film, the atomic ratio of In is made smaller than the atomic ratio of Ga. When it is an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), the atomic ratio of In is made smaller than the atomic ratio of M. In this case, the atomic ratio of Zn can be made the largest.

[0160] ​​​​​​​For example, when “32” is an In-Ga oxide film, the atomic ratio of In is made larger than the atomic ratio of Ga. When it is an In-M-Zn oxide film, the atomic ratio of In is made larger than the atomic ratio of M. In an In-M-Zn oxide film, it is preferable that the atomic ratio of In is larger than the atomic ratios of M and Zn.

[0161] For example, when “33” is an In-Ga oxide film, the atomic ratio of In is made the same as or smaller than the atomic ratio of Ga. When it is an In-M-Zn oxide film, the atomic ratio of In is made the same as the atomic ratio of M. In this case, the atomic ratio of Zn can be made larger than those of In and M. Here, “33” is also a film that constitutes the channel formation regions of transistor TA2 and transistor TB1 described later.

[0162] The atomic ratios of oxide semiconductor films 31 to 33 can be adjusted by adjusting the atomic ratios of the constituent materials of the target when forming the films by sputtering. Also, when forming the films by CVD, it is possible by adjusting the flow rate ratio of the source gases. Hereinafter, taking the case of forming an In-M-Zn oxide film by sputtering as an example for oxide semiconductor films 31 to 33, the targets used for film formation will be described. To form these films, targets made of In-M-Zn oxide are used. Let the atomic ratio of the metal elements of the target for “31” be In:M:Zn = x1:y1:z1.

[0163] 、 It is preferable that x1 / y1 is 1 / 6 or more and less than 1. Also, it is preferable that z1 / y1 is 1 / 3 or more and 6 or less, and further preferably 1 or more and 6 or less.

[0164] ​​​​​​​​As representative examples of the atomic ratio of the target metal elements, In:M:Zn = 1:3:2, In :M:Zn = 1:3:4, In:M:Zn = 1:3:6, In:M:Zn = 1:3:8, In:M:Zn = 1:4:4, In:M:Zn = 1:4:5, In:M:Zn = 1:4: 6, In:M:Zn = 1:4:7, In:M:Zn = 1:4:8, In:M:Zn = 1: 5:5, In:M:Zn = 1:5:6, In:M:Zn = 1:5:7, In:M:Zn = 1:5:8, In:M:Zn = 1:6:8, etc.

[0165] Let the atomic ratio of the target metal elements of '32' be In:M:Zn = x2:y2:z2 and 、 x2 / y2 is preferably greater than 1 and not more than 6. Also, z2 / y2 is preferably greater than 1 and not more than 6. As representative examples of the atomic ratio of the target metal elements are In:M:Zn = 2:1:1.5, In:M:Zn = 2:1:2.3, In:M:Z n = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 3:1:3, In:M :Zn = 3:1:4, etc.

[0166] Let the atomic ratio of the target metal elements of '33' be In:M:Zn = x3:y3:z3 and 、 x3 / y3 is preferably not less than 1 / 6 and not more than 1. Also, z3 / y3 is preferably not less than 1 / 3 and not more than 6, and more preferably not less than 1 and not more than 6. As the original atomic ratio of the target metal elements, representative examples include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1. 2, In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1: 3:6, In:M:Zn = 1:3:8, In:M:Zn = 1:4:4, In:M:Zn = 1:4:5, In:M:Zn=1:4:6, In:M:Zn=1:4:7, In:M:Z n=1:4:8, In:M:Zn=1:5:5, In:M:Zn=1:5:6, In:M :Zn=1:5:7, In:M:Zn=1:5:8, In:M:Zn=1:6:8 etc. do.

[0167] In the deposition target for the In-M-Zn oxide film, the atomic ratio of metal elements is In:M: When Zn=x:y:z, by setting 1≦z / y≦6, the In-M-Zn oxide film can be obtained. This is preferable because it is easy to form a CAAC-OS film. More details will be given later.

[0168] The oxide semiconductor films 31 to 33 are each formed of an oxide semiconductor having a low carrier density. For example, the oxide semiconductor films 31 to 33 are formed using oxide semiconductor films having a carrier density is 1×10 17 pieces / cm 3 Less than or equal to 1×10 15 pieces / cm 3 The following is more preferable: 1×10 13 pieces / cm 3 The following oxide semiconductor film is used. In particular, the oxide semiconductor film 31 The oxide semiconductor film 33 has a carrier density of 8×10 11 pieces / cm 3 Less than, better Preferably 1×10 11 pieces / cm 3 less than 1×10 10 pieces / cm 3 Less than Yes, and 1×10 -9 pieces / cm 3 It is preferable to use any of the above oxide semiconductor films.

[0169] As the oxide semiconductor films 31 to 33, by using an oxide semiconductor film with a low impurity concentration and a low defect level density, a transistor having more excellent electrical characteristics can be manufactured. Here, a low impurity concentration and a low defect level density (less oxygen deficiency) are called high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density may be reduced. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has electrical characteristics (also referred to as normally-on) in which the threshold voltage becomes negative less frequently. In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic may have a low trap level density because of its low defect level density. Further, an oxide semiconductor film that is high-purity intrinsic or 6 substantially high-purity intrinsic has an extremely small off-current, and even in an element with a channel width of 1×10 μm and a channel length L of 10 μm, when the voltage (drain voltage) between the source -13 electrode and the drain electrode is in the range of 1 V to 10 V, the off-current is below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 A or less. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly

[0170] reliable transistor. Examples of the impurity include hydrogen, nitrogen, an alkali metal, or an alkaline earth metal. Hydrogen contained in the oxide semiconductor film reacts with oxygen When hydrogen enters, carriers, i.e., electrons, may be generated. Also, part of the hydrogen may combine with oxygen that binds to metal atoms, generating carriers, i.e., electrons. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normal-on characteristics. Thus.

[0171] For this reason, it is preferable that the hydrogen content in the oxide semiconductor films 31 to 33 is reduced as much as possible while there is oxygen deficiency. Specifically, in the oxide semiconductor films 31 to 33, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Ma ss Spectrometry) is 5×10 atoms / cm 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, 5×10 18 at oms / cm 3 less, preferably 1×10 18 atoms / cm 3 or less, more preferably 5×10 17 atoms / cm 3 or less, even more preferably 1×10 16 atoms / cm 3 or less.

[0172] If the oxide semiconductor films 31 to 33 contain silicon or carbon, which is one of the group 14 elements, the oxygen deficiency in the films increases, and these films become n-type. For this reason, the concentration of silicon or carbon (the concentration obtained by secondary ion mass spectrometry) in the oxide semiconductor films 31 to 33 is 2×10 atoms / cm or less, preferably 2 18 atoms / cm 3 or less, preferably 2 ×1017 atoms / cm 3 Shall be as follows.

[0173] Further, in the oxide semiconductor films 31 to 33, by secondary ion mass spectrometry the concentration of an alkali metal or alkaline earth metal obtained is 1 × 10 18 atoms / c m 3 or less, preferably 2 × 10 16 atoms / cm 3 or less. Alkali metals and alkaline earth metals may generate carriers when combined with the oxide semiconductor, and the off-current of the transistor may increase. For this reason, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor films 31 to 33.

[0174] When the oxide semiconductor films 31 to 33 contain nitrogen, carriers, i.e., electrons, are generated, the carrier density increases, and n-type formation is likely. Therefore, since a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics, it is preferable that the nitrogen content of the oxide semiconductor films 31 to 33 is reduced as much as possible. For example, the nitrogen concentration obtained by secondary ion mass spectrometry is preferably 5 × 10 or less. 18 atoms / cm 3 be low.

[0175] As described above, the oxide semiconductor films 31 to 33 have been described, but it is not limited thereto. Depending on the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the required transistor, an oxide semiconductor film with an appropriate composition may be used. Also, depending on the required transistor In order to obtain semiconductor characteristics and electrical characteristics of the oxide semiconductor films 31 to 3 3. Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density It is preferable to set the degree, etc., appropriately.

[0176] The transistor TA1 is a Ga or M (M is Al, Ga, Y, Zr, La, Ce, or A channel is formed in the oxide semiconductor film 32 in which the atomic ratio of In is larger than the atomic ratio of Nd. This allows the field effect mobility to be increased. Typically, the field effect mobility is , 10cm 2 / Vs > 60cm 2 / Vs, preferably less than 15cm 2 / Vs or more 50cm 2 / Vs. Therefore, there is no possibility of causing a disturbance in the circuit of the active matrix display device. When the transistor TA1 is used, it is suitable for a drive circuit that requires high speed operation.

[0177] It is also preferable to provide the transistor TA1 in a light-shielded area. By providing a transistor TA1 having a high mobility in the drive circuit, the drive frequency can be increased. Therefore, a display device with higher resolution can be realized.

[0178] The transistors TA2 and TB1, in which the channel formation region is formed of the oxide semiconductor film 33, It has a lower field effect mobility than the transistor TA1 and its size is 3 cm 2 / Vs or more 10 cm 2 The transistors TA2 and TB1 have an oxide semiconductor film 32. Since it is not exposed to light, it is less susceptible to deterioration by light than the transistor TA1. The increase in current is small. Therefore, the channel formation region is formed in the oxide semiconductor film 33. The transistors TA2 and TB1 are suitable for a pixel portion that is irradiated with light.

[0179] The transistor TA1 has the following characteristics in comparison with the transistor TA2 that does not include the oxide semiconductor film 32: When light is irradiated, the current in the off state tends to increase. This is why it is suitable for peripheral driving circuits that are less affected by light than pixel areas where light cannot be sufficiently shielded. Of course, there are transistors with configurations like transistors TA2 and TB1. A capacitor may also be provided in the drive circuit.

[0180] The transistors (TA1, TA2, and TB1) and the oxide semiconductor film 31 to the oxide semiconductor film However, the present invention is not limited to this, and may be applied to any other film having the required semiconductor characteristics and The structure of the transistor may be changed depending on the electrical characteristics. For example, the back gate electrode The presence or absence of a gate electrode, a source electrode, and a drain electrode, a stacked structure of an oxide semiconductor film, The shape and arrangement of the rain electrodes can be changed as appropriate.

[0181] (Structure of oxide semiconductor) Next, the structure of the oxide semiconductor will be described.

[0182] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° to 100°. refers to a state. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Further, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0183] In addition, in this specification, when the crystal is trigonal or rhombohedral, it is expressed as a hexagonal system. .

[0184] The oxide semiconductor film can be divided into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. Also the oxide semiconductor can be divided into, for example, a crystalline oxide semiconductor and an amorphous oxide semiconductor.

[0185] Note that examples of the non-single crystal oxide semiconductor include CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, amorphous oxide semiconductor, and the like. Also, examples of the crystalline oxide semiconductor include single crystal oxide semiconductor, CAAC-OS, polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, and the like.

[0186] First, the CAAC-OS film will be described.

[0187] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts oriented in the c-axis direction.

[0188] By using a transmission electron microscope (TEM: Transmission Electron Micro scope), a plurality of crystal parts can be confirmed by observing a bright-field image and a composite analysis image of a diffraction pattern of the CAAC-OS film ( also referred to as a high-resolution TEM image). On the other hand, clear boundaries between crystal parts, that is, grain boundaries (grain boundaries ​​(Also referred to as undary.) cannot be confirmed. Therefore, it can be said that the CAAC-OS film is less likely to cause a decrease in electron mobility due to grain boundaries. It can be said that a decrease in electron mobility due to grain boundaries is unlikely to occur.

[0189] When observing a high-resolution TEM image of the cross-section of the CAAC-OS film from a direction substantially parallel to the sample surface, In the crystal part, it can be confirmed that metal atoms are arranged in layers. Each layer of metal atoms reflects the unevenness of the surface (also referred to as the surface to be formed.) or the upper surface of the CAAC-OS film. It has a shape and is arranged parallel to the surface to be formed or the upper surface of the CAAC-OS film.

[0190] On the other hand, when observing a high-resolution TEM image of the plane of the CAAC-OS film from a direction substantially perpendicular to the sample surface, it can be confirmed that in the crystal part, metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different crystal parts.

[0191] When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) apparatus, for example, in the analysis of the out-of-plane method of a CAAC-OS film having InGaZnO4 crystals, a peak may appear in the vicinity of a diffraction angle (2θ) of 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is substantially perpendicular to the surface to be formed or the upper surface.

[0192] In addition, in the analysis of the out-of-plane method of a CAAC-OS film having InGaZnO4 crystals, in addition to the peak at around 2θ of 31°, a peak also appears at around 2θ of 36°. ​​may occur. The peak near 2θ = 36° indicates that a part of the CAAC-OS film contains crystals without c-axis orientation. The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°.

[0193] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements with a stronger binding force to oxygen than the metal elements constituting the oxide semiconductor film, such as silicon, deprive the oxide semiconductor film of oxygen, disturbing the atomic arrangement of the oxide semiconductor film and reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), and when contained inside the oxide semiconductor film, they become factors that disturb the atomic arrangement of the oxide semiconductor film and reduce its crystallinity. Note that impurities contained in the oxide semiconductor film may serve as carrier traps or carrier generation sources.

[0194] Moreover, the CAAC-OS film is an oxide semiconductor film with a low defect level density. For example, oxygen vacancies in the oxide semiconductor film may serve as carrier traps or become carrier generation sources by capturing hydrogen.

[0195] A low impurity concentration and a low defect level density (few oxygen vacancies) are called high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film with high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using the oxide semiconductor film has electrical characteristics with a negative threshold voltage ( ​​​​It is also rarely (also referred to as normally on). In addition, an oxide semiconductor film having high-purity true or substantially high-purity true nature has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high defect level density may have unstable electrical characteristics. In addition, a transistor using a CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0196]

[0197] Next, the microcrystalline oxide semiconductor film will be described.

[0198] The microcrystalline oxide semiconductor film has a region where crystal parts can be confirmed and a region where clear crystal parts cannot be confirmed in a high-resolution TEM image. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystal) that are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less, is called an nc -OS (nanocrystalline Oxide Semiconductor) film. Also, in an nc-OS film, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly confirmed. The nc-OS film has a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly 1 nm or more

[0199] It has periodicity in the atomic arrangement in the region below 3 nm. Also, in the nc-OS film, no regularity is observed in the crystal orientation between different crystal parts. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an XRD apparatus with an X-ray having a diameter larger than that of the crystal part, no peak indicating the crystal plane is detected in the analysis by the out-of-plane method. Also, for the nc-OS film, when performing electron diffraction (also called limited field of view electron diffraction) using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than that of the crystal part for the nc-OS film spots are observed. Also, when performing nanobeam electron diffraction on the nc-OS film bright regions may be observed in a circular (ring-shaped) manner. Also, when performing nanobeam electron diffraction on the nc-OS film, multiple spots may be observed within the ring-shaped region. The nc-OS film is an oxide semiconductor film with higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect levels than an amorphous oxide semiconductor film. However,

[0200] no regularity is observed in the crystal orientation between different crystal parts in the nc-OS film. Therefore, the nc-O S film has a higher density of defect levels than the CAAC-OS film.

[0201]

[0202] Next, the amorphous oxide semiconductor film will be described.

[0202] An amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example. An oxide semiconductor film having an amorphous state such as quartz is an example.

[0203] In a high-resolution TEM image, no crystal part can be confirmed in the amorphous oxide semiconductor film.

[0204] When performing structural analysis on an amorphous oxide semiconductor film using an XRD apparatus, no peak indicating a crystal plane is detected in the out-of-plane method analysis. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed. When performing structural analysis on an amorphous oxide semiconductor film using an XRD apparatus, no peak indicating a crystal plane is detected in the out-of-plane method analysis. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

[0205] Note that an oxide semiconductor film may have a structure showing physical properties between an nc-OS film and an amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly called an amorphous-like oxide semiconductor (a-like OS: amorphous-like Oxide Semi-conductor) film. Note that an oxide semiconductor film may have a structure showing physical properties between an nc-OS film and an amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly called an amorphous-like oxide semiconductor (a-like OS: amorphous-like Oxide Semi-conductor) film. Note that an oxide semiconductor film may have a structure showing physical properties between an nc-OS film and an amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly called an amorphous-like oxide semiconductor (a-like OS: amorphous-like Oxide Semi-conductor) film.

[0206] In a high-resolution TEM image, voids (also called voids) may be observed in the a-like OS film. Also, in a high-resolution TEM image, there are regions where a crystal part can be clearly confirmed and regions where a crystal part cannot be confirmed. The a-like OS film may crystallize due to a very small amount of electron irradiation at the level of observation by TEM, and growth of the crystal part may be seen. On the other hand, in the case of a high-quality nc-OS film, crystallization due to a very small amount of electron irradiation at the level of observation by TEM is hardly seen. In a high-resolution TEM image, voids (also called voids) may be observed in the a-like OS film. Also, in a high-resolution TEM image, there are regions where a crystal part can be clearly confirmed and regions where a crystal part cannot be confirmed. In a high-resolution TEM image, there are regions where a crystal part can be clearly confirmed and regions where a crystal part cannot be confirmed. The a-like OS film may crystallize due to a very small amount of electron irradiation at the level of observation by TEM, and growth of the crystal part may be seen. The a-like OS film may crystallize due to a very small amount of electron irradiation at the level of observation by TEM, and growth of the crystal part may be seen. On the other hand, in the case of a high-quality nc-OS film, crystallization due to a very small amount of electron irradiation at the level of observation by TEM is hardly seen. On the other hand, in the case of a high-quality nc-OS film, crystallization due to a very small amount of electron irradiation at the level of observation by TEM is hardly seen.

[0207] ​​Note that the size of the crystalline part of the a-like OS film and the nc-OS film can be measured using a high-resolution T EM image. For example, the crystal of InGaZnO4 has a layered structure and has two Ga-Zn-O layers between In-O layers. The unit cell of the InGaZnO4 crystal has three In-O layers and six Ga-Zn-O layers, for a total of nine layers stacked in the c-axis direction in a layered structure. Therefore, the distance between these adjacent layers is approximately the same as the lattice plane spacing of the (009) plane (also referred to as the d value). From crystal structure analysis, this value is determined to be 0.29 nm . Therefore, by focusing on the lattice fringes in the high-resolution TEM image, where the distance between the lattice fringes is 0.28 nm or more and 0.30 nm or less, each lattice fringe corresponds to the a-b plane of the InG aZnO4 crystal.

[0208] In addition, the density of the oxide semiconductor film may vary depending on the structure. For example, if the composition of a certain oxide semiconductor film is known, the structure of the oxide semiconductor film can be estimated by comparing it with the density of a single crystal with the same composition. For example, compared to the density of a single crystal, the density of the a- like OS film is 78.6% or more and less than 92.3%. Also, for example, compared to the density of a single crystal , the density of the nc-OS film and the CAAC-OS film is 92.3% or more and less than 10 0%. Note that an oxide semiconductor film with a density less than 78% compared to the density of a single crystal is difficult to form itself.

[0209] The above will be described using specific examples. For example, in an oxide semiconductor film satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a single crystal InGaZnO4 having a rhombohedral crystal structure is 6.357 g / cm 3 ​It becomes. Therefore, for example, In:Ga:Zn = 1:1:1 [atomic ratio], in the oxide semiconductor film, the density of the a-like OS film is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 For example, in the oxide semiconductor film satisfying In:Ga:Zn = 1:1: 1 [atomic ratio], the density of the nc-OS film and the CAAC- OS film density is 5.9 g / cm 3 or more and less than 6.3 g / cm 3 It becomes less than.

[0210] Note that there may be no single crystal of the same composition. In that case, by combining single crystals with different compositions at an arbitrary ratio, the density corresponding to the single crystal of the desired composition can be calculated . The density of the single crystal of the desired composition may be calculated using the weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to calculate the density by combining as few types of single crystals as possible . .

[0211] Note that the oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film .

[0212] As described above, the OS transistor can realize extremely excellent off-current characteristics

[0213] [Substrate 30] As the substrate 30, various substrates can be used and are not limited to a specific one . As an example of the substrate 30, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, Substrates having stainless steel foils, tungsten substrates, tungsten foils There are substrates having them, flexible substrates, bonding films, paper containing fibrous materials, or base films and the like. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, bonding films, base films and the like include the following. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES)-represented plastics. Or, as an example, there are synthetic resins such as acrylic. Or, as an example, there are polypropylene, polyester, polyvinyl fluoride , or polyvinyl chloride. Or, as an example, there are polyamides, polyimides, aramids, epoxies, inorganic vapor deposition films, or papers. In particular, by manufacturing transistors using semiconductor substrates, single crystal substrates, or SOI substrates, etc., transistors with less variation in characteristics, size, or shape, high current capacity, and small size can be manufactured. When a circuit is configured with such transistors, power consumption reduction of the circuit or high integration of the circuit can be achieved. Before forming the gate electrodes (GE1, GE2, GE3), a base insulating film may be formed on the substrate 30 The base insulating film includes silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide , aluminum oxynitride, and the like. Note that as the base insulating film, silicon nitride, gallium oxide

[0214] Before forming the gate electrodes (GE1, GE2, GE3), a base insulating film may be formed on the substrate 30 Examples of the base insulating film include silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide , aluminum oxynitride, etc. Note that as the base insulating film, silicon nitride, gallium oxide , hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, etc. are used. Note that as the base insulating film, silicon nitride, gallium oxide ​By using tantalum oxide, hafnium oxide, yttrium oxide, aluminum oxide, etc., the substrate 30 Impurities (typically alkali metals, water, hydrogen, etc.) are removed from the oxide semiconductor film (OS1-OS3 ) can be suppressed.

[0215] [Gate electrodes (GE1, GE2, GE3)] The gate electrodes (GE1, GE2, GE3) are made of a single layer of conductive film or a stack of two or more conductive films. It is a multi-layered film. It is formed as gate electrodes (GE1, GE2, GE3). The conductive film is made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten. or an alloy containing the above-mentioned metal elements or the above-mentioned metal elements. It can be formed by using a combination of alloys, etc. Also, manganese, zirconium, etc. Alternatively, one or more metal elements selected from the above may be used. Select from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film or a nitride film made by combining one or more of the above may be used. Indium tin oxide, indium oxide with tungsten oxide, indium oxide with tungsten oxide Indium zinc oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide Oxide, indium zinc oxide, indium tin oxide containing silicon oxide, etc. A conductive material that is suitable for the purpose may also be applied.

[0216] For example, the gate electrodes (GE1, GE2, GE3) are aluminum films containing silicon. When the gate electrodes (GE1, GE2, GE3) have a two-layer structure, For example, a titanium film is formed on an aluminum film, or a titanium film is formed on a titanium nitride film. Form a tungsten film on the titanium nitride film, or form a tungsten film on the tantalum nitride film or tungsten nitride film. Also, when the gate electrodes (GE1, GE2, GE3) have a three-layer structure, for example, a titanium film, an aluminum film laminated on the titanium film, and a titanium film formed thereon may be used.

[0217] The gate electrodes (GE1, GE2, GE3) are formed by a sputtering method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, a thermal CVD method, or the like.

[0218] Note that the tungsten film can be formed by a film-forming apparatus using ALD. In this case, WF6 gas and B2H6 gas are sequentially introduced repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are introduced simultaneously to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0219] In addition to the above-described formation method, the gate electrodes GE1 - GE3 can be formed by an electrolytic plating method, a printing method, an inkjet method, or the like.

[0220] [Insulating film 34 (gate insulating film)] An insulating film 34 is formed to cover the gate electrodes GE1 - GE3. The insulating film 34 is a single-layer insulating film or an insulating film having a multi-layer structure of two or more layers. The insulating film formed as the insulating film 34 includes an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitroxide insulating film, etc. Note that in this specification, an oxynitride is a material having a higher oxygen content than nitrogen, and a nitroxide is a material having a higher nitrogen content than oxygen.

[0221] As the insulating film formed as the insulating film 34, for example, silicon oxide, silicon oxynitride , silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide or an insulating film made of a Ga-Zn based metal oxide or the like can be formed. Also, as such an insulating film, hafnium silicate (HfSiO x ), hafnium silicate with nitrogen added (HfSi O x O y N z ), hafnium aluminate with nitrogen added (Hf Al x O y N z ), a film made of a high-k material such as hafnium oxide, yttrium oxide, etc. can be formed. By using a high-k material, the gate leakage of the transistor can be reduced.

[0222] Since the insulating film 34 is a film constituting the gate insulating film, in order to improve the interface characteristics between the oxide semiconductor film (OS1, OS2, OS3) and the gate insulating film, in the insulating film 34, the region in contact with these layers (OS1, OS2, OS3) is preferably formed of an oxide insulating film or an oxynitride insulating film. For example, the topmost layer film of the insulating film 34 may be a silicon oxide film or a silicon oxynitride film.

[0223] The thickness of the insulating film 34 may be, for example, 5 nm or more and 400 nm or less. The thickness is preferably 10 nm or more and 300 nm or less, and more preferably 50 nm or more and 250 nm or less .

[0224] When forming the oxide semiconductor film (OS1, OS2, OS3) by sputtering, plasma Power supplies for generating a magnetic field can appropriately use an RF power supply, an AC power supply, a DC power supply, etc. It can be used as appropriate.

[0225] For the sputtering gas, an inert gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed gas of an inert gas and oxygen can be appropriately used. In the case of a mixed gas of an inert gas and oxygen, it is preferable to increase the gas ratio of oxygen with respect to the inert gas.

[0226] In addition, the target may be appropriately selected according to the composition of the oxide semiconductor film (OS1, OS2, OS3) to be formed.

[0227] When using the sputtering method to form the oxide semiconductor film (OS1, OS2, OS3), the substrate temperature is set to 150°C or higher and 750°C or lower, preferably 150°C or higher and 450°C or lower, and more preferably 200°C or higher and 350°C or lower, so that a CAAC-OS film can be formed as the oxide semiconductor film 31-32.

[0228] In addition, in order to form a CAAC-OS film, it is preferable to apply the following conditions.

[0229] By suppressing the incorporation of impurities during film formation, it is possible to suppress the breakdown of the crystal state due to impurities. For example, the impurity concentration (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film formation chamber may be reduced. Also, the impurity concentration in the film formation gas may be reduced. Specifically, a film formation gas with a dew point of - 80°C or lower, preferably -100°C or lower, is used.

[0230] In addition, it is preferable to reduce the plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing the power. The oxygen ratio in the film formation gas is preferably 30% by volume or more, and 100% by volume is more preferable. ​​​​​A product percentage is more preferable.

[0231] By forming a film while heating the oxide semiconductor film, or after forming the oxide semiconductor film, by performing a heat treatment, the hydrogen concentration in the oxide semiconductor film can be reduced to 2×10 20 atoms / cm 3 or less, preferably 5×10 or less, more preferably 1×10 19 atoms / cm 3 or less, even more preferably 1×10 19 at oms / cm 3 or less, 5×10 18 atoms / cm 3 less than, preferably 1×10 18 a toms / cm 3 or less, more preferably 5×10 17 atoms / cm 3 or less, even more preferably 1×10 16 atoms / cm 3 or less.

[0232] Note that the heat treatment is performed at a temperature higher than 350°C and 650°C or lower, preferably 450°C or higher and 600°C or lower, so that the CAAC conversion rate described later is 70% or higher and less than 100%, preferably 80% or higher and less than 100%, preferably 90% or higher and less than 100%, more preferably 95% or higher and 98 % or lower, and an oxide semiconductor film with a reduced content of hydrogen, water, etc. can be obtained. That is, an oxide semiconductor film with a low impurity concentration and a low defect level density can be formed.

[0233] An oxide semiconductor film can be formed by a film-forming apparatus using ALD. For example, when forming an InG aZnO X (X>0) film, In(CH3)3 gas and O3 gas are sequentially fed Repeatedly introduce to form an InO2 layer, and then simultaneously introduce Ga(CH3)3 gas and O3 gas to form a GaO layer, and then further simultaneously introduce Zn(CH3)2 gas and O3 gas to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, these gases can be mixed to form mixed compound layers such as InGaO2 layer, InZnO2 layer, GaInO layer, ZnInO layer, GaZnO layer. Note that instead of O3 gas, bubbled H2O gas with an inert gas such as Ar can be used, but it is preferable to use O3 gas without H . Also, instead of In(CH3)3 gas, In(C2H5)3 gas can be used. Also, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas can be used. Also, Z n(CH3)2 gas can be used.

[0234] The oxide semiconductor film 32 and the oxide semiconductor film 33 are films in which the channel of the transistor is formed and the film thickness can be set to 3 nm or more and 200 nm or less. Their thicknesses are preferably 3 nm or more and 100 nm or less, and more preferably 30 nm or more and 50 nm or less. The film thickness of the oxide semiconductor film 31 can be, for example, 3 nm or more and 100 nm or less and is preferably 3 nm or more and 30 nm or less, and more preferably 3 nm or more and 15 nm or less. The oxide semiconductor film 31 is preferably formed thinner than the oxide semiconductor film 32 and the oxide semiconductor film 33 .

[0235] Here, as the oxide semiconductor films 31, 32, and 33, an In-Ga-Zn film is formed by sputtering . The atomic ratio of the metal elements of the target used for these film formations (In:G a:Zn) is, for example, 1:3:6 for the oxide semiconductor film 31 and​ It is 3:1:2, and the oxide semiconductor film 33 can be made 1:1:1.2 or 1:1:1. Also, the thicknesses of the oxide semiconductor films 31, 32, and 33 can be 5 nm, 35 n m, and 35 nm respectively.

[0236] [Source electrode, drain electrode] The electrodes (SE1, DE1, SE2, DE2, SE3, DE3) can be formed in the same manner as the gate electrodes (GE1, GE 2, GE3).

[0237] For example, by laminating these films in the order of a copper-manganese alloy film with a thickness of 50 nm, a copper film with a thickness of 400 nm, and a copper-manganese alloy film with a thickness of 100 n m by sputtering, a three-layer structure electrode (SE1, DE1, SE2, DE2, SE3, DE3) can be formed.

[0238] For a transistor used in a driving circuit of a light-emitting device or the like and operating at high speed, it is preferable to shorten the channel length like the transistors (TA1, TA2) or the transistors (TA3, TA4, TC1). The channel length of such a transistor is preferably less than 2.5 μm. For example, it can be 2.2 μm or less. In the transistor of this embodiment, since the channel length is determined by the distance between the source electrode and the drain electrode, the minimum value of the channel length is restricted by the accuracy of processing the conductive film that becomes the electrodes (SE1, DE1, SE2, DE2, S E3, DE3). In the transistor of this embodiment, for example, the channel length can be 0.5 μm or more, or 1.0 μm or more.

[0239] [Insulating films 35, 36] For example, as the "35", an insulating film with a two-layer structure can be formed. Here, the first layer of the "3 5" film will be called the insulating film 35a, and the second layer of the film will be called the insulating film 35b.

[0240] As the insulating film 35a, for example, an oxide insulating film made of silicon oxide or the like, or an oxide insulating film containing nitrogen and having a small amount of defects can be formed. Representative examples of the oxide insulating film containing nitrogen and having a small amount of defects include a silicon oxynitride film, an aluminum oxynitride film and the like.

[0241] The oxide insulating film with few defects has, in the spectrum obtained by measurement with an ESR of 100 K or less, a first signal with a g value of 2.037 or more and 2.039 or less, a second signal with a g value of 2.001 or more and 2. 003 or less, and a third signal with a g value of 1.964 or more and 1.966 or less observed. Note that the split widths of the first signal and the second signal, and the split widths of the second signal and the third signal are about 5 m T in the X-band ESR measurement. Also, the first signal with a g value of 2.037 or more and 2.039 or less, the second signal with a g value of 2. 01 or more and 2.003 or less, and a third signal with a g value of 1.964 or more and 1.966 or less where the total spin density of the third signal is 1×10 18 spins / cm 3 is less than and typically is 1×10 17 spins / cm 3 or more and 1×10 18 spins / cm 3 less than is.

[0242] Note that in the ESR spectrum at 100 K or less, the g value is 2.037 or more and 2.039 or less The first signal, the second signal with a g value of 2.001 or more and 2.003 or less, and the g value of 1. The third signal of 964 or more and 1.966 or less corresponds to a signal caused by nitrogen oxides (NOx, where x is 0 or more and 2 or less , preferably 1 or more and 2 or less). Representative examples of nitrogen oxides include nitric oxide, nitrogen dioxide, and the like. That is, the first signal with a g value of 2.037 or more and 2.039 or less, the second signal with a g value of 2.001 or more and 2.003 or less, and the g value of 1.96 The smaller the total spin density of the third signal of 4 or more and 1.966 or less, the lower the content of nitrogen oxides contained in the oxide insulating film can be said.

[0243] Since the insulating film 35a is a film with a low content of nitrogen oxides, it is possible to reduce the trapping of carriers at the interface between the insulating film 35a and the layers (OS 1, OS2, OS3). As a result, it is possible to reduce the shift of the threshold voltage of the transistor, and the electrical characteristics of the transistor can be reduced. Moreover, in order to improve the reliability of the transistor, the insulating film 35a preferably has a nitrogen concentration of 6×10

[0244] measured by SIMS (Secondary Ion Mass Spectrometry) of / cm 2 0 or less. This is because nitrogen oxides are less likely to be generated in the insulating film 35 3 a during the manufacturing process of the transistor. As an example of an oxide insulating film containing nitrogen and having a small amount of defects as the insulating film 35a, a silicon oxynitride film can be formed by the CVD

[0245] method. In this case, as the source gas, ... It is preferable to use a depositable gas containing silicon and an oxidizing gas. Deposition of silicon Typical examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. Oxidation Examples of the oxidizing gas include nitrous oxide, nitrogen dioxide, etc.

[0246] Also, the oxidizing gas with respect to the depositable gas is more than 20 times and less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the processing chamber is less than 100 Pa, preferably less than 50 Pa. By using the CVD method it is possible to form an oxide insulating film containing nitrogen and having a small amount of defects as the insulating film 35a.

[0247] As the insulating film 35b, for example, it can be formed using an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition. The oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition releases a part of oxygen by heating. The oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition has an oxygen desorption amount of 1.0×10 or more, preferably 3.0×10 in terms of oxygen atoms converted by TDS analysis. The oxide insulating film is such that the oxygen desorption amount is 18 atoms / cm 3 or more, preferably 3.0×10 20 ato ms / cm 3 or more. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 500°C or less.

[0248] As the insulating film 35b, silicon oxide, silicon oxynitride, etc. with a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more and 4 00 nm or less can be used. As the insulating film 35 b, it can be formed using an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition. When forming, an oxide insulating film containing more oxygen than stoichiometric composition can be used as an acid nitride silicon film can be formed by using the CVD method.

[0249] When forming a silicon oxide film or a silicon oxynitride film as the insulating film 35b, film formation can be performed under the following conditions. The substrate placed in the evacuated processing chamber of the plasma CVD apparatus is held at 180 °C or higher and 280 °C or lower, more preferably 200 °C or higher and 240 °C or lower and the raw material gas is introduced into the processing chamber so that the pressure in the processing chamber is 100 Pa or higher and 250 P a or lower, more preferably 100 Pa or higher and 200 Pa or lower, and high-frequency power of 0.17 W / cm or higher and 0.5 W / cm or lower, more preferably 0.25 W / cm 2 or higher and 0.35 W / cm 2 or lower is supplied to the electrode provided in the processing chamber. 2 or higher and 0.35 W / cm 2 or lower is supplied.

[0250] As the insulating film 36, at least a film having a blocking effect on hydrogen and oxygen is used . Further, preferably, it has a blocking effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. Typically, a nitride insulating film such as silicon nitride may be formed. In addition to the silicon nitride film, a silicon oxynitride film, an aluminum nitride film, an aluminum oxynitride film etc. can also be used. In addition to the silicon nitride film, a silicon oxynitride film, an aluminum nitride film, an aluminum oxynitride film etc. can also be used.

[0251] Further, an oxide insulating film having a blocking effect on oxygen, hydrogen, water, etc. may be provided as the film constituting the insulating film 36. Such oxide insulating films include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride etc. There are yttrium, hafnium oxide, hafnium oxynitride, etc.

[0252] Further, the thickness of the insulating film 36 may be 50 nm or more and 300 nm or less, preferably 100 nm or more and 200 nm or less. By forming the insulating film 36 having a blocking effect against oxygen, hydrogen, water, etc., diffusion of oxygen from the oxide semiconductor film 31 to the oxide semiconductor film 33 to the outside can be prevented, and intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor film 31 to the oxide semiconductor film 33 can be prevented. When forming a silicon nitride film by plasma CVD as the insulating film 36, it is preferable to use a deposition gas containing silicon, nitrogen, and ammonia as source gases. By using these source gases, ammonia dissociates in the plasma and active species are generated. The active species break the bonds of silicon and hydrogen contained in the deposition gas containing silicon and the triple bond of nitrogen. As a result, the bond of silicon and nitrogen is promoted, the bond of silicon and hydrogen is less, the defects are less, and a dense silicon nitride film can be formed. On the other hand, in the source gas, if the amount of ammonia relative to nitrogen is large, the decomposition of the deposition gas containing silicon and nitrogen respectively does not proceed, the silicon and hydrogen bonds remain, the defects increase, and a rough silicon nitride film is formed. For these reasons, in the source gas, it is preferable to set the flow rate ratio of nitrogen to ammonia to 5 or more and 50 or less, preferably 10 or more and 50 or less. After forming the insulating film 35, a heat treatment may be performed. The temperature of the heat treatment is typically 150 °C or more and less than the substrate distortion point, preferably 200 °C or more and 450 °C or less, more preferably 3

[0253]

[0254] 00 °C or more and 400 °C or less. It shall be 0 °C or higher and 450 °C or lower. By this heat treatment, oxygen contained in the oxide insulating film constituting the second layer of the insulating film 35 is moved to the oxide semiconductor film 31 to the oxide semiconductor film 33, and oxygen deficiencies contained therein can be reduced. For the heat treatment, for example, in a mixed gas atmosphere containing nitrogen and oxygen, the heating temperature may be 350 °C and the heating time may be 1 hour. Also, after forming the insulating film 36, heat treatment may be performed for the purpose of releasing hydrogen or the like from the oxide semiconductor film 31 to the oxide semiconductor film 33. For this heat treatment, for example, in a mixed gas atmosphere containing nitrogen and oxygen, the heating temperature may be 350 °C and the heating time may be 1 hour.

[0255] <Back gate electrode> The back gate electrodes (BGE1, BGE2) can be formed in the same manner as the gate electrodes (GE1, GE2, GE3).

[0256] [Back gate electrode] The back gate electrodes (BGE1, BGE2) can be formed in the same manner as the gate electrodes (GE1, GE2, GE3).

[0257] Hereinafter, some other configuration examples of the transistor will be shown.

[0258] (Transistors TA3, TA4) FIG. 29(A) and FIG. 29(B) show the top views (layout diagrams) of the transistor TA3 and the transistor TA4, respectively, and their circuit symbols. FIG. 30(A) and FIG. 30(B) show cross-sectional views of the transistor TA3 taken along lines a7 - a8 and b7 - b8, and cross-sectional views of the transistor T A4 taken along lines a9 - a10 and b9 - b10. The transistor TA3 has a gate electrode GE4, an oxide semiconductor film OS4, a source electrode SE4, a drain electrode DE4, and a back gate electrode BGE4. The transistor TA3

[0259] has a gate electrode GE4, an oxide semiconductor film OS4, a source electrode SE4, a drain electrode DE4, and a back gate electrode BGE4. The transistor TA3 , a modified example of the transistor TA1, where the electrode BGE4 is in two openings CG4 and CG5 and is different from the transistor TA1 in that the point where it contacts the electrode GE4 is different, while the others are the same as the transistor TA 1. As shown in FIG. 30(B), in the channel width direction, the film OS4 is surrounded by the electrode GE4 and the electrode BGE4, and the strength of the transistor TA3 can be further improved .

[0260] The transistor TA4 has a gate electrode GE5, an oxide semiconductor film OS5, a source electrode SE5, a drain electrode DE5, and a back gate electrode BGE5. The transistor TA4 is a modified example of the transistor TA2, where the electrode BGE5 is not connected to the electrode GE5, and different signals or potentials can be input to the electrode BG E5 from the electrode GE5. For example, a signal for controlling the conduction state of the transistor TA4 can be input to the electrode GE5, and a signal or potential for correcting the threshold voltage of the transistor TA4 can be input to the electrode BGE5. .

[0261] (Transistors TC1, TB2, TD1) FIG. 31(A), FIG. 31(B), and FIG. 31(C) show the top views (layout diagrams) of the transistors TC1, the transistor TB2, and the transistor TD1, respectively, and their circuit symbols . FIG. 32(A) and FIG. 32(B) show cross-sectional views of the transistor TC1 along the lines a11 - a12 and b 11b12, cross-sectional views of the transistor TB2 along the lines a13 - a14 and b13 - b1 4, and cross-sectional views of the transistor TD1 along the lines a15 - a16 and b15 - b16 .

[0262] The transistor TC1 has a gate electrode GE6, an oxide semiconductor film OS6, a source electrode SE6, It has a drain electrode DE6 and a back gate electrode BGE6. The electrode BGE6 is in contact with the electrode GE6 at the opening C G6. The transistor TC1 is a modified example of the transistor TA1, and the film OS6 has a two-layer structure. The film OS6 consists of '32' and '33'. Similar to the transistor TA1, the transistor TC1 is also a transistor in which the channel formation region is formed of '32'. Therefore, the transistor TC1 is also a transistor with a relatively high field-effect mobility, typically a field-effect mobility greater than 10 cm / Vs and less than 60 cm / Vs, preferably a transistor with a field-effect mobility of 15 cm / Vs or more and less than 50 cm m 2 / Vs. Therefore, like the transistor TA1, the transistor TC1 is also suitable for a transistor that operates at high speed, such as a drive circuit. 2 / Vs, preferably 15 cm 2 / Vs or more and 50 cm 2 / Vs or less. Therefore, like the transistor TA1, the transistor TC1 is also suitable for a transistor that operates at high speed, such as a drive circuit. Similarly, the transistor TC1 is suitable for a transistor that operates at high speed, such as a drive circuit.

[0263] The transistor TB2 has a gate electrode GE7, an oxide semiconductor film OS7, a source electrode SE7, a drain electrode DE7, and a back gate electrode BGE7. The electrode BGE7 is in contact with the electrode GE7 at the opening C G7. The transistor TB2 is a modified example of the transistor TB1 and is different from the transistor TB2 in that it has an electrode BGE7. Since the transistor TB 2 has an electrode BGE7 connected to the electrode GE7, it has a higher on-current and improved mechanical strength than the transistor TB1. Since the transistor TB2 has an electrode BGE7 connected to the electrode GE7, it has a higher on-current and improved mechanical strength than the transistor TB1. Also, its mechanical strength is improved.

[0264] The transistor TD1 has a gate electrode GE8, an oxide semiconductor film OS8, a source electrode SE8, and a drain electrode DE8. The transistor TD1 is a modified example of the transistor TB1 This is an example where the entire film OS8 overlaps the electrode GE8 and has no portion outside the end of the electrode GE8. Thus, since the transistor TD1 has a structure in which the film OS8 is less likely to be exposed to light than the transistor TB1, it is suitable for the transistors in the pixel portion. The films (insulating films, oxide semiconductor films, metal oxide films, conductive films, etc.) constituting the transistor TA1, the transistor TA2, and the transistor TB1 can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, or a pulsed laser deposition (PLD) method. Alternatively, they can be formed by a coating method or a printing method. As film formation methods, the sputtering method and the plasma chemical vapor deposition (PECVD) method are representative, but a thermal CVD method may also be used.

[0265] As examples of the thermal CVD method, the MOCVD (metalorganic chemical vapor deposition) method or the ALD (atomic layer deposition) method may be used. (Insulating film, oxide semiconductor film, metal oxide film, conductive film, etc.) The thermal CVD method forms a film by setting the inside of the chamber to atmospheric pressure or reduced pressure, simultaneously feeding a source gas and an oxidizing agent into the chamber, and reacting them near or on the substrate to deposit them on the substrate. Thus, since the thermal CVD method is a film formation method that does not generate plasma, it has the advantage that defects are not generated due to plasma damage. The ALD method forms a film by setting the inside of the chamber to atmospheric pressure or reduced pressure, sequentially introducing source gases for the reaction into the chamber, and repeating the order of gas introduction. For example, by switching each switching valve (also called a high-speed valve), two or more types of source gases are sequentially supplied to the chamber so that the first source gas and the second source gas do not mix.

[0266] The thermal CVD method sets the inside of the chamber to atmospheric pressure or reduced pressure, simultaneously feeds a source gas and an oxidizing agent into the chamber, and reacts them near or on the substrate to deposit them on the substrate to form a film. Thus, since the thermal CVD method is a film formation method that does not generate plasma, it has the advantage that defects are not generated due to plasma damage. Moreover, the ALD method sets the inside of the chamber to atmospheric pressure or reduced pressure, and the source gases for the reaction are sequentially introduced into the chamber, and film formation is performed by repeating the order of gas introduction. For example, by switching each switching valve (also called a high-speed valve), two or more types of source gases are sequentially supplied to the chamber so that the first source gas and

[0267] the second source gas do not mix. For example, by switching each switching valve (also called a high-speed valve), two or more types of source gases are sequentially supplied to the chamber so that the first source gas and the second source gas do not mix. The second source gas are sequentially supplied to the chamber so that the first source gas and Simultaneously or subsequently, an inert gas (such as argon or nitrogen) is introduced, and a second raw material gas is introduced. When an inert gas is introduced simultaneously, the inert gas serves as a carrier gas , and it is also possible to introduce the inert gas simultaneously when the second raw material gas is introduced. Also , instead of introducing the inert gas, after discharging the first raw material gas by vacuum exhaust, the second raw material gas may be introduced. The first raw material gas adsorbs on the surface of the substrate to form the first single atomic layer , and reacts with the subsequently introduced second raw material gas, and the second single atomic layer is laminated on the first single atomic layer to form a thin film.

[0268] By repeating a plurality of times until the desired thickness is reached while controlling this gas introduction sequence, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted according to the number of times the gas introduction sequence is repeated , precise film thickness adjustment is possible, which is suitable for manufacturing fine transistors.

[0269] 〈Specific Configuration Example 3 of Pixel〉

[0270] FIG. 17 shows, as an example, the specific configuration of the pixel 10 shown in FIG. 1. The pixel 10 shown in FIG. 17 has a different position of the transistor 19t from the pixel 10 shown in FIG. 4(A). Specifically, in the pixel 10 shown in FIG. 17, the transistor 19t is connected between the wiring VL, the other of the source and drain of the transistor 11, and one of the source and drain of the transistor 16t , and is different in configuration from the pixel 10 shown in FIG. 4(A).

[0271] FIG. 18 shows, as an example, the specific configuration of the pixel 10 shown in FIG. 1. The pixel 10 is different in the position of the transistor 19t from the pixel 10 shown in FIG. 15(A). Specifically , in the pixel 10 shown in FIG. 18, the transistor 19t is connected between the wiring VL and the other of the source and drain of the transistor 11 and one of the source and drain of the transistor 16t, and the configuration is different from the pixel 10 shown in FIG. 15(A).

[0272] Note that in the pixel 10 of the light-emitting device according to one aspect of the present invention, transistors other than the transistor 11 may have at least a gate on one side of the semiconductor film, and may further have another gate that overlaps the gate with the semiconductor film interposed therebetween. When transistors other than the transistor 11 have a pair of gates, if one of the pair of gates is a back gate, the same height potential may be applied to the normal gate and the back gate, or only a fixed potential such as a ground potential may be applied to the back gate. By controlling the height of the potential applied to the back gate, the threshold voltage of the transistor can be controlled. Also, by providing a back gate, the channel formation region increases, and an increase in the drain current can be realized. Also, by providing a back gate, a depletion layer is likely to be formed in the semiconductor film, so that the S value can be improved.

[0273] 〈Configuration Example 2 of Transistor〉 The transistor used in the light-emitting device according to one aspect of the present invention may have a channel formation region in a semiconductor film or a semiconductor substrate such as amorphous, microcrystalline, polycrystalline or single crystal silicon or germanium. When forming a transistor using a thin film of silicon, the thin film is formed by a vapor growth method such as plasma CVD method or sputtering method ​​​​​​​​​​​​​​ Amorphous silicon that has been obtained, and the amorphous silicon is crystallized by a process such as laser annealing Polycrystalline silicon obtained by such crystallization, and single-crystalline silicon wafers into which hydrogen ions or the like are implanted and the surface layer portion is peeled off Single-crystalline silicon or the like can be used.

[0274] FIG. 34 illustrates a cross-sectional view of a transistor using a thin-film silicon film that can be used in a light-emitting device according to one embodiment of the present invention. In FIG. 34, an n-channel transistor 70 and a p-channel transistor 71 are shown.

[0275] The transistor 70 includes a conductive film 73 that functions as a gate on a substrate 72 having an insulating surface, an insulating film 74 on the conductive film 73, a semiconductor film 75 that overlaps the conductive film 73 with the insulating film 74 interposed therebetween, an insulating film 76 on the semiconductor film 75, and conductive films 77a and 77b that overlap the semiconductor film 75 with the insulating film 76 interposed therebetween and that also function as a gate, an insulating film 78 on the conductive films 77a and 77b, an insulating film 79 on the insulating film 78, and conductive films 80 and 81 that are electrically connected to the semiconductor film 75 at an opening provided in the insulating films 78 and 79 and that function as a source or a drain. The conductive film 77b has a width in the channel length direction that is shorter than that of the conductive film 77a, and the conductive films 77a and 77b are laminated in order from the insulating film 76 side. Further, the semiconductor film 75 has a channel formation region 82 at a position overlapping the conductive film 77b, a pair of LDD (Light Doped Drain) regions 83 positioned so as to sandwich the channel formation region 82 therebetween, and a pair of impurity regions 84 positioned so as to sandwich the channel formation region 82 and the LDD regions 83 therebetween.

[0276] It does so. The pair of impurity regions 84 function as a source region or a drain region. Also, L The LDD region 83 and the impurity regions 84 are impurity elements that impart an n-type conductivity type to the semiconductor film 75. For example, boron (B), aluminum (Al), gallium (Ga), etc. are added to it.

[0277] Also, the transistor 71 includes a conductive film 85 that functions as a gate on a substrate 72 having an insulating surface, an insulating film 74 on the conductive film 85, a semiconductor film 86 that overlaps the conductive film 85 with the insulating film 74 interposed therebetween, an insulating film 76 on the semiconductor film 86, a conductive film 87a and a conductive film 87b that overlap the semiconductor film 86 with the insulating film 76 interposed therebetween and also function as a gate, an insulating film 78 on the conductive films 87a and 87b, an insulating film 79 on the insulating film 78, a conductive film 88 and a conductive film 89 that are electrically connected to the semiconductor film 86 at an opening provided in the insulating films 78 and 79 and also function as a source or a drain.

[0278] The conductive film 87b has a width in the channel length direction that is shorter than that of the conductive film 87a, and the conductive films 87a and 87b are laminated in order from the insulating film 76 side. Also, the semiconductor film 75 has a channel formation region 90 at a position overlapping the conductive film 87b and a pair of impurity regions 91 positioned so as to sandwich the channel formation region 90 therebetween. The pair of impurity regions 91 function as a source region or a drain region. Also, the impurity regions 91 are impurity elements that impart a p-type conductivity type to the semiconductor film 86. For example, phosphorus (P), arsenic (As), etc. are added to it.

[0279] Note that the semiconductor film 75 or the semiconductor film 86 may be crystallized by various techniques. Various ​​​​​​​​​​​​As crystallization methods, there are a laser crystallization method using a laser beam and a crystallization method using a catalyst element. Alternatively, a crystallization method using a catalyst element and a laser crystallization method may be used in combination. When using a substrate 72 with excellent heat resistance such as quartz, a thermal crystallization method using an electric furnace, a lamp annealing crystallization method using infrared light, a crystallization method using a catalyst element, or a crystallization method combining a high-temperature annealing at about 950 °C may be used.

[0280] <Production Method 1 of Light-Emitting Device> Next, a production method of the light-emitting device 400 according to an aspect of the present invention will be described with reference to FIGS. 19 and 20.

[0281] First, an insulating film 420 is formed on a substrate 462, and a first element layer 410 is formed on the insulating film 420 (see FIG. 19(A)). A semiconductor element is provided in the first element layer 410. Alternatively, in addition to the semiconductor element, a display element or a part of a display element such as a pixel electrode may be provided in the first element layer 410.

[0282] The substrate 462 needs to have at least heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 462.

[0283] When using a glass substrate for the substrate 462, forming an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a silicon nitride oxide film between the substrate 462 and the insulating film 420 can prevent contamination from the glass substrate, which is preferable.

[0284] For the insulating film 420, for example, an epoxy resin, an aramid resin, an acrylic resin, a polyimide resin Organic resin films such as fats, polyamide resins, and polyamide-imide resins can be used. Among them it is preferable to use a polyimide resin because of its high heat resistance. As the insulating film 420, for example, when using a polyimide resin, the film thickness of the polyimide resin is 3 nm or more and 20 μm or less, preferably 500 nm or more and 2 μm or less. When using a polyimide resin as the insulating film 420 it can be formed by a spin coating method, a dip coating method, a doctor blade method, or the like. For example, when using a polyimide resin as the insulating film 420, by the doctor blade method, by removing a part of the film using the polyimide resin, an insulating film 420 having a desired thickness can be obtained.

[0285] Note that the temperature in the manufacturing process of the first element layer 410 is preferably room temperature or higher and 300 °C or lower. For example, the insulating film or conductive film using an inorganic material included in the first element layer 410 is preferably formed at a film formation temperature of 150 °C or higher and 300 °C or lower, more preferably 200 °C or higher and 270 °C or lower. Also, the insulating film or the like using an organic resin material included in the first element layer 410 is preferably formed at a film formation temperature of room temperature or higher and 100 °C or lower.

[0286] Further, for the oxide semiconductor film of the transistor included in the first element layer 410, it is preferable to use the aforementioned CAAC-OS. When using CAAC-OS for the oxide semiconductor film of the transistor, for example, when bending the light-emitting device 400, cracks and the like are less likely to enter the channel formation region, and it becomes possible to enhance the resistance to bending.

[0287] Further, as the conductive film included in the first element layer 410, indium added with silicon oxide ​​When using a tin oxide, when the light-emitting device 400 is bent, cracks or the like are likely to occur in the conductive film, which is preferable.

[0288] Next, the first element layer 410 and the temporary support substrate 466 are adhered using the release adhesive 464. Then, the insulating film 420 and the first element layer 410 are peeled off from the substrate 462. As a result, the insulating film 420 and the first element layer 410 are provided on the side of the temporary support substrate 466 (see Fig. 19(B)).

[0289] As the temporary support substrate 466, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, etc. can be used. Also, a plastic substrate having heat resistance that can withstand the processing temperature of the present embodiment may be used, or a flexible substrate such as a film may be used.

[0290] As the release adhesive 464, an adhesive that can be physically or chemically separated from the temporary support substrate 466 and the element layer 410 when necessary, such as one that is soluble in water or a solvent or can be plasticized by irradiation with ultraviolet light or the like, is used.

[0291] Note that various methods can be appropriately used for the step of transferring to the temporary support substrate 466. For example, by irradiating the insulating film 420 with a laser beam 468 from the side where the insulating film 420 of the substrate 462 is not formed, i.e., the lower side shown in Fig. 19(B), the insulating film 420 can be made fragile so that the substrate 462 and the insulating film 420 can be peeled off. Also, by adjusting the energy density of the irradiation of the laser beam 468, it is also possible to create regions with high adhesion between the substrate 462 and the insulating film 420 and regions with low adhesion between the substrate 462 and the insulating film 420 and then peel them off.

[0292] ​​​​​​ In this embodiment, a method of peeling at the interface between the substrate 462 and the insulating film 420 has been exemplified, but the method is not limited thereto. For example, peeling may be performed at the interface between the insulating film 420 and the first element layer 410. In this embodiment, a method of peeling at the interface between the substrate 462 and the insulating film 420 has been exemplified, but the method is not limited thereto. For example, peeling may be performed at the interface between the insulating film 420 and the first element layer 410. In this embodiment, a method of peeling at the interface between the substrate 462 and the insulating film 420 has been exemplified, but the method is not limited thereto. For example, peeling may be performed at the interface between the insulating film 420 and the first element layer 410.

[0293] Alternatively, a liquid may be infiltrated into the interface between the substrate 462 and the insulating film 420 to peel the insulating film 420 from the substrate 462. Or, a liquid may be infiltrated into the interface between the insulating film 420 and the first element layer 410 to peel the first element layer 410 from the insulating film 420. As the above liquid, for example, water, a polar solvent, or the like can be used. By infiltrating the liquid into the interface for peeling the insulating film 420, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410. Alternatively, a liquid may be infiltrated into the interface between the substrate 462 and the insulating film 420 to peel the insulating film 420 from the substrate 462. Or, a liquid may be infiltrated into the interface between the insulating film 420 and the first element layer 410 to peel the first element layer 410 from the insulating film 420. As the above liquid, for example, water, a polar solvent, or the like can be used. By infiltrating the liquid into the interface for peeling the insulating film 420, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410. Alternatively, a liquid may be infiltrated into the interface between the substrate 462 and the insulating film 420 to peel the insulating film 420 from the substrate 462. Or, a liquid may be infiltrated into the interface between the insulating film 420 and the first element layer 410 to peel the first element layer 410 from the insulating film 420. As the above liquid, for example, water, a polar solvent, or the like can be used. By infiltrating the liquid into the interface for peeling the insulating film 420, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410. Alternatively, a liquid may be infiltrated into the interface between the substrate 462 and the insulating film 420 to peel the insulating film 420 from the substrate 462. Or, a liquid may be infiltrated into the interface between the insulating film 420 and the first element layer 410 to peel the first element layer 410 from the insulating film 420. As the above liquid, for example, water, a polar solvent, or the like can be used. By infiltrating the liquid into the interface for peeling the insulating film 420, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410. Alternatively, a liquid may be infiltrated into the interface between the substrate 462 and the insulating film 420 to peel the insulating film 420 from the substrate 462. Or, a liquid may be infiltrated into the interface between the insulating film 420 and the first element layer 410 to peel the first element layer 410 from the insulating film 420. As the above liquid, for example, water, a polar solvent, or the like can be used. By infiltrating the liquid into the interface for peeling the insulating film 420, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410. Alternatively, a liquid may be infiltrated into the interface between the substrate 462 and the insulating film 420 to peel the insulating film 420 from the substrate 462. Or, a liquid may be infiltrated into the interface between the insulating film 420 and the first element layer 410 to peel the first element layer 410 from the insulating film 420. As the above liquid, for example, water, a polar solvent, or the like can be used. By infiltrating the liquid into the interface for peeling the insulating film 420, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410. Alternatively, a liquid may be infiltrated into the interface between the substrate 462 and the insulating film 420 to peel the insulating film 420 from the substrate 462. Or, a liquid may be infiltrated into the interface between the insulating film 420 and the first element layer 410 to peel the first element layer 410 from the insulating film 420. As the above liquid, for example, water, a polar solvent, or the like can be used. By infiltrating the liquid into the interface for peeling the insulating film 420, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410.

[0294] Next, the first substrate 401 is adhered to the insulating film 420 using the adhesive layer 418 (see FIG. 19(C)). Next, the first substrate 401 is adhered to the insulating film 420 using the adhesive layer 418 (see FIG. 19(C)).

[0295] Next, the peeling adhesive 464 is dissolved or plasticized to remove the peeling adhesive 464 and the temporary support substrate 466 from the first element layer 410 (see FIG. 19(D)). Next, the peeling adhesive 464 is dissolved or plasticized to remove the peeling adhesive 464 and the temporary support substrate 466 from the first element layer 410 (see FIG. 19(D)).

[0296] It is preferable to remove the peeling adhesive 464 with water, a solvent, or the like so that the surface of the first element layer 410 is exposed. It is preferable to remove the peeling adhesive 464 with water, a solvent, or the like so that the surface of the first element layer 410 is exposed.

[0297] Thus, the first element layer 410 can be formed on the first substrate 401.

[0298] Next, by a forming method similar to the steps shown in FIGS. 19(A) to 19(D), a second substrate 4 05, an adhesive layer 412 on the second substrate 405, an insulating film 440 on the adhesive layer 412, and a second element layer 411 are formed (see Fig. 20(A)).

[0299] As the insulating film 440 of the second element layer 411, a material similar to the insulating film 420 can be used here and can be formed using an organic resin.

[0300] Next, a sealing layer 432 is filled between the first element layer 410 and the second element layer 411, and the first element layer 410 and the second element layer 411 are bonded together (see Fig. 20(B)).

[0301] With the sealing layer 432, for example, solid sealing can be achieved. However, as the sealing layer 432 a flexible configuration is preferred. As the sealing layer 432, for example, glass materials such as glass frit or curable resins that cure at room temperature such as two-component mixed resins, photo-curable resins and thermosetting resins can be used as the resin material.

[0302] Through the above, the light-emitting device 400 can be manufactured.

[0303] 〈Manufacturing method 2 of the light-emitting device〉 Next, another manufacturing method of the light-emitting device 400 according to an aspect of the present invention will be described with reference to Fig. 21. In Fig. 21, a configuration using an inorganic insulating film as the insulating film 420 and the insulating film 440 will be described.

[0304] First, a release layer 463 is formed on the substrate 462. Next, an insulating film 420 is formed on the release layer 463, and a first element layer 410 is formed on the insulating film 420 (see Fig. 21(A)).

[0305] As the release layer 463, for example, tungsten, molybdenum, titanium, tantalum, niobium​ , an element selected from nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, osmium, iridium, silicon, an alloy material containing the element, or a compound material containing the element, and a single-layer or laminated structure can be used. Further, in the case of a layer containing silicon, the crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, polycrystalline, and single-crystalline.

[0306] The release layer 463 can be formed by a sputtering method, a PECVD method, a coating method, a printing method, or the like. The coating method includes a spin coating method, a droplet discharge method, and a dispensing method.

[0307] When the release layer 463 has a single-layer structure, it is preferable to form a layer containing tungsten, molybdenum, or a mixture of tungsten and molybdenum. Further, a layer containing an oxide or oxynitride of tungsten, a layer containing an oxide or oxynitride of molybdenum, or a layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum may be formed. Here, the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

[0308] Further, when forming a laminated structure of a layer containing tungsten and a layer containing an oxide of tungsten as the release layer 463, a layer containing tungsten is formed, and an insulating layer formed of an oxide is formed on the upper layer thereof, so that a layer containing an oxide of tungsten is formed at the interface between the tungsten layer and the insulating layer. This may be utilized. Further, the surface of the layer containing tungsten is subjected to heat oxidation treatment, oxygen plasma treatment, nitrous oxide (N2O) plasma treatment, or oxidation power such as ozone water. Treatment with a strong solution or the like may be performed to form a layer containing tungsten oxide. Also, the plasma treatment and heat treatment may be performed in an atmosphere of oxygen, nitrogen, nitrous oxide alone, or a mixed gas of the gas and other gases. By the above plasma treatment and heat treatment, the adhesion between the release layer 463 and the insulating film 420 formed later can be controlled by changing the surface state of the release layer 463. The insulating film 420 can be an inorganic insulating film with low moisture permeability such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or an aluminum oxide film. The above inorganic insulating film can be formed by using, for example, a sputtering method, a PECVD method, or the like.

[0309] Next, the first element layer 410 and the temporary support substrate 466 are adhered using the release adhesive 464, and the insulating film 420 and the first element layer 410 are peeled off from the release layer 463. As a result, the insulating film 420 and the first element layer 410 are provided on the side of the temporary support substrate 466 (see Fig. 21(B)). The transfer process to the temporary support substrate 466 can appropriately use various methods. For example, when a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal oxide film can be made fragile by crystallization to peel off the insulating film 420 from the release layer 463. When the release layer 463 is formed of a tungsten film, peeling may be performed while etching the tungsten film with a mixed solution of aqueous ammonia and hydrogen peroxide

[0310] water. Also, a liquid can be infiltrated at the interface between the release layer 463 and the insulating film 420 to peel off the insulating film from the release layer 463. )

[0311] Note that various methods can be appropriately used for the transfer process to the temporary support substrate 466. For example, when a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal oxide film can be made fragile by crystallization to peel off the insulating film 420 from the release layer 463. When the release layer 463 is formed of a tungsten film, peeling may be performed while etching the tungsten film with a mixed solution of aqueous ammonia and hydrogen peroxide water.

[0312] Also, a liquid can be infiltrated at the interface between the release layer 463 and the insulating film 420 to peel off the insulating film from the release layer 463.​​​ It is also possible to peel off 420. As the above liquid, for example, water, a polar solvent, or the like can be used. By allowing the liquid to penetrate into the interface for peeling off the insulating film 420, specifically, the interface between the peeling layer 463 and the insulating film 420, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410. It is also possible to peel off 420. As the above liquid, for example, water, a polar solvent, or the like can be used. By allowing the liquid to penetrate into the interface for peeling off the insulating film 420, specifically, the interface between the peeling layer 463 and the insulating film 420, it is possible to suppress the influence of static electricity or the like generated due to the peeling applied to the first element layer 410.

[0313] Next, the first substrate 401 is adhered to the insulating film 420 using the adhesive layer 418 (see Fig. 21(C)). Reference).

[0314] Next, the peeling adhesive 464 is dissolved or plasticized, and the peeling adhesive 464 and the temporary support substrate 466 are removed from the first element layer 410 (see Fig. 21(D)). Reference).

[0315] It is preferable to remove the peeling adhesive 464 with water, a solvent, or the like so that the surface of the first element layer 410 is exposed. Reference).

[0316] As described above, the first element layer 410 can be formed on the first substrate 401.

[0317] Next, in the same formation method as the steps shown in Figs. 21(A) to 21(D), a second substrate 4 05, an adhesive layer 412 on the second substrate 405, an insulating film 440 on the adhesive layer 412, and a second element layer 411 are formed. Then, a sealing layer 432 is filled between the first element layer 410 and the second element layer 411, and the first element layer 410 and the second element layer 411 are bonded together. Reference). Reference).

[0318] Finally, an anisotropic conductive film 380 and an FPC 408 are attached to the connection electrode 360. If necessary, an IC chip or the like may be mounted.

[0319] As described above, the light-emitting device 400 can be manufactured.

[0320] <Cross-sectional Structure of Light-Emitting Device> FIG. 22 shows, as an example, the cross-sectional structure of a pixel portion of a light-emitting device according to an aspect of the present invention. Note that , in FIG. 22, the cross-sectional structures of the transistor 11, the capacitor element 18, and the light-emitting element 14 included in the pixel 10 shown in FIG. 3(A) are illustrated.

[0321] Specifically, the light-emitting device shown in FIG. 22 has a transistor 11 and a capacitor element 18 on a substrate 500. The transistor 11 includes a conductive film 501 that functions as a first gate, an insulating film 502 on the conductive film 501, a semiconductor film 503 that overlaps the conductive film 501 with the insulating film 502 interposed therebetween, a conductive film 504 and a conductive film 505 that function as a source or a drain electrically connected to the semiconductor film 503, an insulating film 550 on the semiconductor film 503, the conductive film 504, and the conductive film 505, and a conductive film 551 that overlaps the conductive film 501 with the insulating film 550 interposed therebetween and functions as a second gate.

[0322] The capacitor element 18 includes a conductive film 501 that functions as an electrode, an insulating film 502 on the conductive film 501, and a conductive film 504 that overlaps the conductive film 501 with the insulating film 502 interposed therebetween and functions as an electrode.

[0323] As the insulating film 502, an insulating film containing at least one of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, oxynitride silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide may be used alone or in a stacked manner. Note that, in this specification, The oxynitride refers to a material having an oxygen content higher than that of nitrogen in its composition, i.e., the oxynitride refers to a material having a nitrogen content higher than that of oxygen in its composition.

[0324] Further, an insulating film 511 is provided on the semiconductor film 503, the conductive film 504, and the conductive film 505 When an oxide semiconductor is used as the semiconductor film 503, it is desirable to use a material capable of supplying oxygen to the semiconductor film 5 03 for the insulating film 511. By using the above material for the insulating film 5 11, it is possible to move the oxygen contained in the insulating film 511 to the semiconductor film 503 and reduce the oxygen deficiency amount of the semiconductor film 503. The transfer of the oxygen contained in the insulating film 511 to the semiconductor film 503 can be efficiently performed by performing a heat treatment after forming the insulating film 511 .

[0325] An insulating film 520 is provided on the insulating film 511, and a conductive film 524 is provided on the insulating film 520. The conductive film 524 is connected to the conductive film 504 at the opening provided in the insulating film 511 and the insulating film 520.

[0326] An insulating film 525 is provided on the insulating film 520 and the conductive film 524. The insulating film 525 has an opening at a position overlapping the conductive film 524. Further, on the insulating film 525, an insulating film 5 26 is provided at a position different from the opening of the insulating film 525. Then, on the insulating film 525 and the insulating film 526, an EL layer 527 and a conductive film 528 are provided so as to be laminated in order . The portion where the conductive film 524 and the conductive film 528 overlap with the EL layer 527 interposed therebetween functions as the light-emitting element 14. And one of the conductive film 524 and the conductive film 528 functions as the anode and the other functions as the cathode.

[0327] The light-emitting device also includes a substrate 530 that faces the substrate 500 with the light-emitting element 14 interposed therebetween. On the substrate 530, that is, on the surface of the substrate 530 closer to the light-emitting element 14, a shielding film 531 having a function of shielding light is provided. The shielding film 531 has an opening in a region overlapping with the light-emitting element 14. In the opening overlapping with the light-emitting element 14, a coloring layer 532 that transmits visible light in a specific wavelength range is provided on the substrate 530.

[0328] <Appearance of the Light-Emitting Device> FIG. 23(A) is a perspective view showing an example of the appearance of a light-emitting device according to an aspect of the present invention. The light-emitting device shown in FIG. 23(A) includes a panel 1601, a circuit board 1602 provided with a controller, a power supply circuit, an image processing circuit, an image memory, a CPU, etc., and a connection portion 1603. The panel 1601 includes a pixel portion 1604 provided with a plurality of pixels, a driving circuit 1605 that selects a plurality of pixels row by row, and a driving circuit 1606 that controls the input of an image signal Sig to the pixels within the selected row. Various signals and the potential of the power supply are input to the panel 1601 from the circuit board 1602 via the connection portion 1603. The connection portion 1603 can use an FPC (Flexible Printed Circuit), etc.

[0329] When a COF (Chip On Film) tape in which a chip is mounted on an FPC is used, a smaller area and higher-density mounting can be achieved. When a COF tape is used for the connection portion 1603, a part of the circuit in the circuit board 1602, or a part of the driving circuit 1605 or the driving circuit 1606 included in the panel 1601 Prepare separately on a chip, and it may be connected to a COF tape using the COF (Chip On Film) method.

[0330] Also, a perspective view showing an example of the appearance of a light-emitting device using a COF tape 1607 is shown in Fig. 23(B). as shown in.

[0331] The chip 1608 is a semiconductor bare chip (such as an IC or LSI) having terminals such as bumps on its surface. Further, CR components can also be mounted on the COF tape 1607, and the area of the circuit board 1602 can be reduced. The wiring pattern of the flexible substrate is formed in a plurality corresponding to the terminals of the chip to be mounted. The chip 1608 is positioned and arranged on a flexible substrate having a wiring pattern by a bonder device or the like, and is mounted by thermocompression bonding.

[0332] Fig. 23(B) shows an example of one COF tape 1607 on which one chip 1608 is mounted, but is not particularly limited. A plurality of rows of chips can be mounted on one side or both sides of one COF tape 1607, but in order to reduce costs, it is preferable to make it a single row, and more preferably to make it one.

[0333] 〈Example of circuit board configuration〉 Fig. 25 shows an external view of the circuit board 2003. The circuit board 2003 is provided with a communication device 2101, a microcomputer 2102, a storage device 2103, an FPGA 2104, a DA converter 2105, a charge control IC 2106, and a level shifter 2107 of the Bluetooth (registered trademark. Same as IEEE802.15.1) standard on an FPC 2201 having a slit 2211. ​​​​​​​​​​​has such a configuration. Further, the circuit board 2003 is electrically connected to the light-emitting device according to one aspect of the present invention via the input / output connector 2108. Further, by providing the slit 2211 in the FPC 2201, the flexibility of the circuit board 2003 using the FPC 2201 is enhanced. is electrically connected to the light-emitting device according to one aspect of the present invention. Further, by providing the slit 2211 in the FPC 2201, the flexibility of the circuit board 2003 using the FPC 2201 is enhanced. is electrically connected to the light-emitting device according to one aspect of the present invention. Further, by providing the slit 2211 in the FPC 2201, the flexibility of the circuit board 2003 using the FPC 2201 is enhanced.

[0334] By using a flexible substrate for the light-emitting device according to one aspect of the present invention, the light-emitting device can be curved together with the circuit board 200 3. Therefore, the light-emitting device using the flexible substrate and the circuit board 2003 can be repeatedly deformed according to the shape of the mounting site, and thus are suitable for use in electronic devices that can be worn on the body such as the arm and leg. and thus are suitable for use in electronic devices that can be worn on the body such as the arm and leg.

[0335] <Example Configuration of Information Processing Apparatus> FIG. 26(A) is a schematic diagram for explaining the appearance of an information processing apparatus 1000 according to one aspect of the present invention, and FIG. 26(B) is a cross-sectional view for explaining the structure of the cross-section at the cutting line X1-X2 shown in FIG. 26(A). Further, FIGS. 26(C) and 26(D) are schematic diagrams for explaining the appearance of an information processing apparatus 1 000 according to one aspect of the present invention, and FIG. 26(E) is a cross-sectional view for explaining the structure of the cross-section at the cutting line X3-X4 shown in FIGS. 26(C) and 26(D )). FIG. 26(C) is a schematic diagram for explaining the front of the information processing apparatus 1000. FIG. 26(D) is a schematic diagram for explaining the back of the information processing apparatus 10 00. FIG. 26(C) is a schematic diagram for explaining the front of the information processing apparatus 1000. FIG. 26(D) is a schematic diagram for explaining the back of the information processing apparatus 10 00.

[0336] As shown in FIGS. 26(C) and 26(D), the position input unit 1001 or the display unit 1002 may be provided not only on the front surface of the information processing apparatus 1000 but also on the side surface or the back surface. Further the position input unit 1001 or the display unit 1002 may be provided on the upper surface of the information processing apparatus 1000 It may be. Further, the position input unit 1001 or the display unit 1002 may be provided on the bottom surface of the information processing apparatus 100 0.

[0337] In addition to the position input unit 1001, the surface of the housing 1003 may have hardware buttons, external connection terminals, etc.

[0338] With such a configuration, instead of displaying only on the plane parallel to the front of the housing 1003 like a conventional information processing apparatus, it becomes possible to display on the side surface of the housing 1003 as well. In particular, when a display area is provided along two or more side surfaces of the housing 1003, the diversity of the display is further enhanced, which is preferable.

[0339] The display area arranged along the front of the information processing apparatus and each display area arranged along the side surface may be used as independent display areas to display different images, etc., or one image, etc. may be displayed across two or more display areas. For example, the image displayed in the display area arranged along the front of the information processing apparatus may be continuously displayed in the display area provided along the side surface of the information processing apparatus, etc.

[0340] Further, the arithmetic unit 1005 is provided inside the housing 1003. In FIG. 26(B), the arithmetic unit 1005 is provided at a position separated from the display unit 1002. In FIG. 26(E), the arithmetic unit 1005 is provided at a position overlapping the display unit 1002.

[0341] The position input unit 1001, as an example, includes a first area 1001(1), a second area 1001(2) facing the first area 100 1(1), and the first area 1001(1) and the second ​​​​is bent so that a third region 1001(3) is formed between the regions 1001(2). has flexibility that allows it to be bent (see Fig. 26(B)). As another example, the first region 1001(1), the third region 1001(3), and a fourth region 1001(4) facing the third region 1001(3) are formed so that it has flexibility that allows it to be bent (see Fig. 26(E)).

[0342] As another example, it may have flexibility that allows it to be bent so that the third region 1001(3), the fifth region 1001(5), and a fourth region 1001(4) facing the third region 1001(3) are formed.

[0343] Note that the arrangement of the second region 1001(2) facing the first region 1001(1) is not limited to being directly opposite the first region 1001(1), and includes an arrangement where it faces the first region 1001(1) with an inclination. Also, the arrangement of the fourth region 1001(4) facing the third region 1001(3) is not limited to being directly opposite the third region 1001(3), and includes an arrangement where it faces the third region 1001(3) with an inclination.

[0344] The display unit 1002 is arranged to overlap at least a part of the first region 1001(1), the second region 1001(2), the third region 1001(3), or the fourth region 1001(4).

[0345] The information processing apparatus 1000 includes a flexible position input unit 100 1 that detects things in proximity or contact. And the position input unit 1001, for example, the first region 1001( ​​​​(1) and a second region 1001(2) facing the first region, and a third region 1001(3) overlapping the display unit 1002 between the first region 1001(1) and the second region 1001(2) can be bent so as to be formed. Thereby, for example, the palm or the finger of the hand can be known whether it is close to any of the first region 1001(1) or the second region 1001(2). As a result, a human interface with excellent operability can be provided. Or, a novel information processing apparatus with excellent operability can be provided.

[0346] As the substrate used for the display unit 1002, a resin having a thickness with flexibility can be applied For the resin, for example, polyester, polyolefin, polyamide, polyimide, aramid, epoxy, polycarbonate, acrylic resin, etc. can be mentioned. Also as a normal substrate without flexibility, a glass substrate, a quartz substrate, a semiconductor substrate, etc. can be used

[0347] <Example of the configuration of an electronic device> The light-emitting device according to one aspect of the present invention can be used for a display device, a notebook personal computer, an image playback device equipped with a recording medium (typically a device having a display capable of playing a recording medium such as a DVD: Digital Versatile Disc and displaying its image) In addition, as an electronic device that can use the light-emitting device according to one aspect of the present invention, a mobile phone, a portable game machine, a portable information terminal, an e-book, a video camera, a digital still camera such as a camera, a goggle-type display (head-mounted display) a navigation system, an audio playback device (car audio, digital audio player) ​​​​​​​such as a yarn, a copying machine, a facsimile machine, a printer, a multifunction printer, an automated teller machine (ATM), a vending machine, etc. Specific examples of these electronic devices are shown in FIG. 24 Figure 24 shows specific examples of these electronic devices .

[0348] FIG. 24(A) is a display device and includes a housing 5001, a display unit 5002, a support base 5003, etc . The light-emitting device according to one aspect of the present invention can be used for the display unit 5002. Note that the display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, etc .

[0349] FIG. 24(B) is a portable information terminal and includes a housing 5101, a display unit 5102, operation keys 5103, etc . The light-emitting device according to one aspect of the present invention can be used for the display unit 5102

[0350] FIG. 24(C) is a display device and includes a housing 5701 having a curved surface, a display unit 5702, etc . By using a flexible substrate for the light-emitting device according to one aspect of the present invention, the light-emitting device can be used for the display unit 5702 supported by the housing 5701 having a curved surface, and a flexible, lightweight, and user-friendly display device can be provided

[0351] FIG. 24(D) is a portable game machine and includes a housing 5301, a housing 5302, display units 5303, display units 5304, a microphone 5305, a speaker 5306, operation keys 5307, a start button 5308, etc . The light-emitting device according to one aspect of the present invention can be used for the display unit 5303 or the display unit 5304. By using the light-emitting device according to one aspect of the present invention for the display unit 5303 or the display unit 5304, the user experience is excellent and quality degradation is less likely to occur ​​​​A portable game machine can be provided. Note that the portable game machine shown in Fig. 24(D) has two display units 5303 and 5304, but the number of display units owned by the portable game machine is not limited to this.

[0352] Fig. 24(E) is an e-book and has a housing 5601, a display unit 5602, etc. The light-emitting device according to one aspect of the present invention can be used for the display unit 5602. By using a flexible substrate, the light-emitting device can be made flexible, so that a flexible, lightweight, and easy-to-use e-book can be provided.

[0353] Fig. 24(F) is a mobile phone, and a display unit 5902, a microphone 5907, a speaker 5904, a camera 5903, an external connection unit 5906, and operation buttons 5905 are provided on the housing 5901. The light-emitting device according to one aspect of the present invention can be used for the display unit 5902. In addition, when the light-emitting device according to one aspect of the present invention is formed on a flexible substrate, the light-emitting device can be applied to the display unit 5902 having a curved surface as shown in Fig. 24( F).

[0354] <Example> In this example, a display device manufactured using the pixels shown in the above embodiment will be described.

[0355] First, the characteristics of the transistor used in the pixel were measured. The transistor used in the pixel is an OS transistor formed using a CA AC-OS film, and the CAAC-OS film is formed using In-Ga -Zn oxide.

[0356] ​​Figure 42(A) shows the measurement results of the I-V characteristics of the OS transistor. Here, the measurement results are shown for the cases where the voltage between the source and drain (Vds) is set to 0.1 V and 10 V. Note that the channel length L of the OS transistor is 6 μm, and the channel width W is 6 μm. In addition, the OS transistor is provided with a back gate, and the measurement was performed with the voltage between the back gate and the source (Vbgs) being 0 V.

[0357] The measurement was performed at 20 points within the same substrate. The median value of the threshold voltage of the OS transistor obtained by the measurement was 4.38 V, and the variation in the threshold voltage was 3σ = 0.88 V.

[0358] Note that by providing a back gate, the DIBL (Drain Induced Barrier Lowering) effect is reduced. In the case of a single-gate structure without a back gate, the channel length modulation coefficient was about 0.05 V whereas in the case of using a back gate, it was about 0.009 V -1 and the saturation was improved. -1

[0359] Next, the measurement results of the Vbgs dependence of the threshold voltage Vth of the OS transistor are shown in Figure 42(B). Figure 42(B) is a graph obtained by measuring the I-V characteristics while changing Vbgs with the source potential of the OS transistor fixed, and calculating and plotting the threshold voltage from the measurement results. Note that Figure 42(B) shows the measurement results for the case of Vds = 10 V.

[0360] It can be seen that when Vbgs changes to the positive side, the threshold voltage shifts to the negative side, and when Vbgs changes to the negative side, the threshold voltage shifts to the positive side. Furthermore, Vth is V It can be seen that it linearly shifts with respect to bgs. Note that the shift amount of the threshold voltage also depends on the film thickness of the interlayer film between the channel portion and the back gate portion and the dielectric constant of the interlayer film. The thicker the film thickness of the interlayer film and the lower the dielectric constant, the smaller the influence of Vbgs on the threshold voltage. becomes.

[0361] Pixels were configured using the above OS transistor. Fig. 43(A) shows the circuit configuration of the pixel. Note that the pixel shown in Fig. 43(A) corresponds to the pixel 10 shown in Fig. 3(B) and Fig. 4(B). Then, by driving the pixel shown in Fig. 43(A) according to the timing chart shown in Fig. 43(B), the threshold voltage was corrected. The operation of correcting the threshold voltage can refer to the description of the above embodiment. form. Note that in period I, G3 is at a high level, Tr4 is in an on state, and the source potential of the driving transistor DrTr is the potential obtained by adding the threshold Vth of the OLED to the CATHODE potential. OLED is added.

[0362] The specifications of the display device manufactured using the above pixels are shown in Table 1. The resolution of the display device was 302 ppi, and the aperture ratio was 61%. Also, the scan driver was built in on glass, and a COF was used for the source driver.

[0363]

Table 1

[0364] The display device was a top emission type using a white EL element and a color filter (CF). The structure of the display device is shown in Fig. 44(A).

[0365] ​​​In addition, the white EL element had a laminated structure as shown in Fig. 44(B). The white EL element had a two-layer tandem element structure in which a light-emitting unit using a blue fluorescent material and a light-emitting unit using green and red phosphorescent materials were connected in series.

[0366] Fig. 45 shows a display photo of the actually fabricated display device. It can be seen that there is no display unevenness or the like in the display photo and that the display is normal.

[0367] Fig. 46 shows the calculation results when the threshold voltage of the driving transistor DrTr shown in Fig. 43(A) is changed. Here, ΔVth, which is the horizontal axis of the graph, is the shift amount of Vth due to the correction of the threshold voltage. Also, Vgs-Vth, which is the vertical axis of the graph, is the value obtained by subtracting the threshold voltage of the driving transistor DrTr after the correction of the threshold voltage from Vgs of the driving transistor DrTr during the light-emitting period IV in Fig. 43(B). If the correction of the threshold voltage is performed normally, the value of Vgs-Vth does not depend on the threshold voltage, and thus the slope of the graph becomes 0.

[0368] From the calculation results shown in Fig. 46, it can be seen that the variation in the value of Vgs-Vth in the range where ΔVth is from -1.5 V to +1.5 V is suppressed to about 10% of the value of Vgs-Vth when ΔVth = 0.

[0369] Note that in the pixel shown in Fig. 43(A), when the threshold of the OLED is Vth OLED and the threshold voltage Vth of the driving transistor DrTr is a positive value, correction can be performed up to the range shifted by the potential of Vth = 0 to V0 -(Cathode + Vth OLED ) to the positive side. When the threshold voltage of the driving transistor DrTr is a negative value, Vt ​​​​​​​​​​​The variation in the threshold voltage can be corrected up to the range shifted to the negative side by the potential of Anode-V0 from h = 0. In addition, when the variation in the threshold voltage of the driving transistor DrTr is within the range of positive values, the power supply of V0 can be set to Anode. In this case, one power supply line V0 in the pixel can be reduced. As described above, by using the present invention, a display device with corrected threshold voltage and reduced display unevenness can be fabricated.

[0370] As described above, by using the present invention, a display device with corrected threshold voltage and reduced display unevenness can be fabricated. can be produced.

Explanation of Reference Numerals

[0371] 10 Pixel 11 Transistor 12 Switch 12t Transistor 13 Capacitive Element 14 Light-Emitting Element 15 Switch 15t Transistor 16 Switch 16t Transistor 17 Switch 17t Transistor 18 Capacitive Element 19 Switch 19t Transistor 30 Substrate 31 Oxide Semiconductor Film 31-32 Oxide Semiconductor Film 32 Oxide Semiconductor Film 33 Oxide Semiconductor Film 34 Insulating Film 35 Insulating Film 35a Insulating Film 35b Insulating Film 36 Insulating Film 40 Pixel Section 41 Selection Circuit 42 Wiring 43 Switch 44 Switch 45 Monitor Circuit 46 Operational Amplifier 47 Capacitive Element 48 Switch 49 Wiring 60A Switch 60B Switch 60C Switch 61 Circuit 62A Switch 62B Switch 62C Switch 63A Wiring 63B Wiring 70 Transistor 71 Transistor 72 Substrate 73 Conductive Film 74 Insulating Film 75 Semiconductor Film 76 Insulating Film 77a Conductive Film 77b Conductive Film 78 Insulating Film 79 Insulating Film 80 Conductive Film 81 Conductive Film 82 Channel Formation Region 83 LDD Region 84 Impurity Region 85 Conductive Film 86 Semiconductor Film 87a Conductive Film 87b Conductive Film 88 Conductive Film 89 Conductive Film 90 Channel Formation Region 91 Impurity Region 360 Connection Electrode 380 Anisotropic Conductive Film 400 Light-Emitting Device 401 Substrate 405 Substrate 408 FPC 410 Element Layer 411 Element Layer 412 Adhesive Layer 418 Adhesive Layer 420 Insulating Film 432 Encapsulation Layer 440 Insulating film 462 Substrate 463 Release layer 464 Release adhesive 466 Temporary support substrate 468 Laser beam 500 Substrate 501 Conductive film 502 Insulating film 503 Semiconductor film 504 Conductive film 505 Conductive film 511 Insulating film 520 Insulating film 524 Conductive film 525 Insulating film 526 Insulating film 527 EL layer 528 Conductive film 530 Substrate 531 Masking film 532 Coloring layer 550 Insulating film 551 Conductive film 802 IEEE 1000 Information processing device 1001 Position input section 1001(1) First region 1001(2) Second region 1001(3) Third region 1001(4) Fourth region 1002 Display section 1003 Housing 1005 Arithmetic unit 1601 Panel 1602 Circuit board 1603 Connection section 1604 Pixel section 1605 Driving circuit 1606 Driving circuit 1607 COF tape 1608 Chip 2003 Circuit board 2101 Communication device 2102 Microcontroller 2103 Storage device 2104 FPGA 2105 DA Converter 2106 Charge Control IC 2107 Level Shifter 2108 Input / Output Connector 2201 FPC 2211 Slit 5001 Housing 5002 Display Unit 5003 Support Stand 5101 Housing 5102 Display Unit 5103 Operation Key 5301 Housing 5302 Housing 5303 Display Unit 5304 Display Unit 5305 Microphone 5306 Speaker 5307 Operation Key 5308 Stylus 5601 Housing 5602 Display Unit 5701 Housing 5702 Display Unit 5901 Housing 5902 Display Unit 5903 Camera 5904 Speaker 5905 Button 5906 External Connection Port 5907 Microphone

Claims

1. A light-emitting device including a transistor, a first switch to a fifth switch, a first capacitor and a second capacitor, and a light-emitting element, wherein one terminal of the first switch is electrically connected to a first wiring, and the other terminal is electrically connected to a first gate of the transistor, wherein one of a source or a drain of the transistor is electrically connected to a second wiring, and the other of the source or the drain is electrically connected to one terminal of the fifth switch, wherein one terminal of the second switch is electrically connected to the first gate of the transistor, and the other terminal is electrically connected to one terminal of the fifth switch, wherein one terminal of the third switch is electrically connected to a third wiring, and the other terminal is electrically connected to a second gate of the transistor, wherein one terminal of the fourth switch is electrically connected to a fourth wiring, and the other terminal is electrically connected to one terminal of the fifth switch, wherein a first electrode of the first capacitor is electrically connected to the first gate of the transistor, and a second electrode is electrically connected to the other of the source or the drain of the transistor, wherein a first electrode of the second capacitor is electrically connected to the second gate of the transistor, and a second electrode is electrically connected to the other of the source or the drain of the transistor, wherein the other terminal of the fifth switch is electrically connected to a first electrode of the light-emitting element, wherein a second electrode of the light-emitting element is electrically connected to the fourth wiring, a first period in which the third switch is in an on state and the fourth switch is in an off state, and a second period in which the third switch is in an off state and the fourth switch is in an on state, wherein the first wiring has a function of supplying an image signal, wherein the second wiring has a function of supplying a first potential, wherein the third wiring has a function of supplying a second potential, and wherein the fourth wiring has a function of supplying a third potential, a light-emitting device.

2. A light-emitting device including a transistor, a first switch to a fifth switch, a first capacitor and a second capacitor, and a light-emitting element, wherein one terminal of the first switch is electrically connected to a first wiring, and the other terminal is electrically connected to a first gate of the transistor, One of the source or drain of the transistor is electrically connected to the second wiring, and the other of the source or drain is electrically connected to one of the terminals of the fifth switch. One of the terminals of the second switch is electrically connected to the first gate of the transistor, and the other of the terminals is electrically connected to one of the terminals of the fifth switch. One of the terminals of the third switch is electrically connected to the third wiring, and the other of the terminals is electrically connected to the second gate of the transistor. One of the terminals of the fourth switch is electrically connected to the fourth wiring, and the other of the terminals is electrically connected to one of the terminals of the fifth switch. For the first capacitor element, the first electrode is electrically connected to the first gate of the transistor, and the second electrode is electrically connected to the other of the source or drain of the transistor. For the second capacitor element, the first electrode is electrically connected to the second gate of the transistor, and the second electrode is electrically connected to the other of the source or drain of the transistor. The other of the terminals of the fifth switch is electrically connected to the first electrode of the light-emitting element. The second electrode of the light-emitting element is electrically connected to the fourth wiring. A first period in which the third switch is in an on state and the fourth switch is in an off state. A second period in which the third switch is in an off state and the fourth switch is in an on state. The first wiring has a function of supplying an image signal. The second wiring has a function of supplying a first potential. The third wiring has a function of supplying a second potential. The fourth wiring has a function of supplying a third potential. The transistor is a light-emitting device having an oxide semiconductor film in a channel formation region.

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