Control Program, Control Method, and Information Processing Apparatus

Abstract

To store a plurality of microcodes in a storage device.SOLUTION: A control program causes a computer to execute processing of determining whether a first microcode 14 stored in a first area 13b of a storage device 13 supports a processor 12 and decompressing one of a plurality of compressed second microcodes 14 stored in a second area 13e of the storage device 13 into the first area 13b when the first microcode 14 does not support the processor 12.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a control program, a control method, and an information processing apparatus.

Background Art

[0002] BIOS (Basic Input / Output System) is firmware incorporated in a computer motherboard or system board. When the computer is powered on, after initializing the CPU (Central Processing Unit) and memory, BIOS starts the OS (Operating System).

[0003] BIOS is stored in a ROM (Read Only Memory) sized as defined by the CPU architecture. For example, in the case of the intel 64 and IA-32 architecture, the size of the ROM is 16MB, which is a fixed size. The ROM storing BIOS stores microcode, which is the firmware of the CPU. Microcode is a program defined for each type of CPU, and a different CPU cannot use the microcode for a certain CPU. Therefore, when BIOS supports multiple types of CPUs, microcode is pre-stored in the ROM for each type of CPU.

[0004] However, as CPUs become more powerful, the scale of microcode is growing, making it difficult to store multiple microcodes in the ROM.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] According to one aspect, an object is to enable a storage device to store a plurality of microcodes.

Means for Solving the Problems

[0007] According to one aspect, a control program is provided for causing a computer to execute a process of determining whether a first microcode stored in a first area of a storage device corresponds to a processor, and if the first microcode does not correspond to the processor, expanding one of a plurality of compressed second microcodes stored in a second area of the storage device to the first area.

Advantages of the Invention

[0008] According to one aspect, a plurality of microcodes can be stored in a storage device.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0010] Before describing this embodiment, matters considered by the inventor of the present application will be described.

[0011] FIG. 1 is a hardware configuration diagram of a computer used for consideration. As shown in FIG. 1, this computer 1 includes a CPU 2 and a storage device 3. The storage device 3 is a ROM in which a BIOS program is stored, and includes a key area 3a, a microcode area 3b, a hash value area 3c, and a program area 3d.

[0012] Among these, the microcode area 3b is an area in which the microcode 4 of the CPU 2 is stored. As described above, the microcode 4 is firmware defined for each type of CPU 2. Therefore, when there are a plurality of types of CPUs 2 to be mounted on the computer 1, a plurality of microcodes 4 corresponding to each type are stored in the microcode area 3b. In the example of FIG. 1, a case is assumed in which a plurality of microcodes 4 corresponding to each of the types of CPUs 2 of "A", "B", and "C" are stored in the microcode area 3b.

[0013] Further, the hash value area 3c is an area in which the hash value 5 of the area combining the microcode area 3b and the program area 3d is stored. Note that the hash value 5 is stored in the hash value area 3c in an encrypted state. Also, both the microcode 4 and the hash value 5 are uncompressed data.

[0014] The key area 3a is an area in which the public key 6 corresponding to the secret key for encrypting the hash value 5 is stored. And the program area 3d is an area in which the BIOS program is stored. As an example, the program area 3d stores startup code and other codes that are executed when the BIOS is started.

[0015] Next, the processing performed by the CPU 2 will be described.

[0016] Figure 2 is a flowchart of the processing performed by the CPU 2. First, the CPU 2 selects a microcode 4 corresponding to its own type from among a plurality of microcodes 4 in the microcode area 3b (step S11). For example, when the type of the CPU 2 is "A", the CPU 2 selects and applies the microcode 4 of type "A".

[0017] Next, the CPU 2 calculates the hash value of the combined area of the microcode area 3b and the program area 3d using the same hash function as when calculating the hash value 5 (step S12).

[0018] Next, the CPU 2 decrypts the hash value 5 stored in the hash value area 3c using the public key 6 in the key area 3a (step S13).

[0019] After that, the CPU 2 determines whether the hash value 5 decrypted in step S13 is equal to the hash value calculated in step S12 (step S14). If this determination is negative, the process ends.

[0020] On the other hand, if the determination in step S14 is affirmative, the process proceeds to step S15. In step S15, the CPU 2 executes the BIOS program in the program area 3d. Thus, the basic processing performed by the CPU 2 according to this example ends.

[0021] In this example, as shown in FIG. 1, the microcodes 4 of each of the plurality of types of the CPU 2 are stored in the microcode area 3b. However, with the increasing functionality of the CPU 2, the size of the microcode 4 is increasing, and it is becoming difficult to store a plurality of microcodes 4 in the microcode area 3b.

[0022] Also, the number of types of the CPU 2 supported by one BIOS is increasing, and it is difficult to store all the microcodes 4 supported by one BIOS in the microcode area 3b.

[0023] In addition, as the generation of the CPU 2 increases, the code amount of the BIOS program also increases, so the program area 3d increases, and as a result, the free area of the storage device 3 available as the microcode area 3b is gradually decreasing.

[0024] Hereinafter, this embodiment in which a plurality of microcodes can be stored in a storage device will be described.

[0025] (This embodiment) FIG. 3 is a hardware configuration diagram of an information processing apparatus according to this embodiment. This information processing apparatus 11 is a computer such as a server or a PC, and includes a CPU 12 and a storage device 13.

[0026] The storage device 13 is a ROM in which a BIOS program is stored, and includes a key area 13a, a microcode area 13b, a hash value area 13c, a program area 13d, and a compressed data area 13e.

[0027] Among these, the microcode area 13b is an example of a first area, and is an area in which the uncompressed microcode 14a of the CPU 12 is stored. Different from the example of FIG. 1, in this embodiment, only the uncompressed microcode 14a corresponding to one of the plurality of types of the CPU 12 is stored in the microcode area 13b. Here, the case where the microcode 14 corresponding to the type “B” of the CPU 12 among each of the types “A”, “B”, and “C” is stored in the microcode area 13b is illustrated. Note that the microcode 14 corresponding to the type “B” of the CPU 12 in this way is an example of a first microcode. Further, instead of the type of the CPU 12, a product number or the like for identifying the CPU 12 may be adopted.

[0028] In addition, the hash value area 13c is an example of a third area, and is an area in which the uncompressed hash value 15a of the area combining the microcode area 13b and the program area 13d is stored. Note that the hash value 15 is stored in the hash value area 13c in an encrypted state.

[0029] The key area 13a is an area where a public key 16 corresponding to a secret key for encrypting an uncompressed hash value 15a is stored. And the program area 13d is an area where the BIOS program is stored. As an example, in the program area 13d, startup code and other codes that are executed when the BIOS starts up are stored.

[0030] The compressed data area 13e is an example of the second area, and is an area where a plurality of compressed microcodes 14, compressed hash values 15, and a compression order table 18 are stored.

[0031] Among these, each of the compressed microcodes 14 is a microcode corresponding to any one of all types of CPUs 12 to be installed in the information processing apparatus 11. In this example, it is assumed that all types of CPUs 12 to be installed in the information processing apparatus 11 are "A", "B", and "C". In this case, the compressed microcodes 14 corresponding to each of "A", "B", and "C" are stored in the compressed data area 13e.

[0032] Also, the compressed hash value 15 is data obtained by compressing the encrypted hash value of the area combining the microcode area 13b and the program area 13d when any one of the plurality of compressed microcodes 14 is expanded to the microcode area 13b. For example, consider the case where the microcode 14 corresponding to the type "A" is expanded to the microcode area 13b. In this case, the data obtained by compressing the encrypted hash value of the area combining the microcode area 13b and the program area 13d becomes the compressed hash value 15 corresponding to the type "A".

[0033] Hereinafter, the compressed microcode 14 and the compressed hash value 15 corresponding to the same type of CPU 12 are collectively referred to as compressed data 19.

[0034] Note that the algorithm for compressing the compressed microcode 14 and the compressed hash value 15 in the compressed data area 13e is not particularly limited. In this example, data compression is performed by the program "Tiano compression" of Intel Corporation.

[0035] The compression order table 18 is an example of correspondence information, which is information associating an identifier for identifying each of a plurality of compressed microcodes 14 with the address of the storage device 13 in which each compressed microcode 14 is stored.

[0036] Here, it is assumed that codes are assigned to the types of the CPU 12 as shown in FIG. 4(a). FIG. 4(a) is a diagram showing the correspondence between the CPU 12 and the codes.

[0037] The code is an integer that uniquely identifies a plurality of types of the CPU 12. In this example, it is assumed that the code for the type "A" is "10", and the code increases by 1 in order for the types "B" and "C".

[0038] FIG. 4(b) is a schematic diagram of the compression order table 18. As shown in FIG. 4(b), the compression order table 18 is information associating an index and an address offset. The index is an identifier that uniquely identifies each of a plurality of compressed microcodes 14. Here, the index of the microcode 14 corresponding to a certain type of the CPU 12 is defined as the difference between the code of that type and the code of the type "A". For example, the index of the compressed microcode 14 corresponding to the type "B" is 1 (= 11 - 10).

[0039] The address offset is the offset between the address of the storage device 13 storing the compressed microcode 14 of type "A" and the address of the storage device 13 storing a certain compressed microcode 14. In the example of FIG. 4(b), the offset between the address of the microcode 14 of type "C" and the address of the compressed microcode 14 of type "A" is "0850h" in hexadecimal notation. Note that instead of the address offset, the address itself of each compressed microcode 14 in the storage device 13 may be used.

[0040] Next, the process when storing data in the storage device 13 will be described.

[0041] FIG. 5 is a flowchart showing the process when storing data in the storage device 13. In the following, it is assumed that a computer such as a PC or a server executes each step. The computer may be the same as the information processing device 11 or may be a computer different from the information processing device 11.

[0042] First, the computer calculates the hash value 15 when storing the compressed microcode 14 corresponding to the CPU 12 of type "A" in the microcode area 13b (step S21). Similarly, the computer calculates the hash value 15 when storing the compressed microcodes 14 corresponding to the CPUs 12 of types "A" and "B" in the microcode area 13b.

[0043] Next, the computer encrypts the compressed hash value 15 corresponding to the type "A" with a secret key, and compresses the encrypted hash value 15 and the microcode 14 of type "A" to create compressed data 19 (step S22). Similarly, the computer creates compressed data 19 corresponding to each of the types "B" and "C".

[0044] Next, the computer stores the compressed data 19 corresponding to each of the types "A" to "C" in the compressed data area 13e (step S23).

[0045] Subsequently, the computer creates a compression order table 18 by associating the index of each compressed microcode 14 with the address offset (step S24).

[0046] Next, the computer stores the default uncompressed microcode 14a in the microcode area 13b (step S25). For example, the computer expands the microcode 14 corresponding to the type "B" as the default compressed microcode 14 and stores it in the microcode area 13b as the uncompressed microcode 14a.

[0047] Thus, the basic process for storing data in the storage device 13 is completed.

[0048] Next, the functional configuration of the information processing apparatus 11 according to the present embodiment will be described.

[0049] FIG. 6 is a functional configuration diagram of the information processing apparatus 11 according to the present embodiment. As shown in FIG. 6, the information processing apparatus 11 includes a control unit 31. The control unit 31 is a processing unit that controls each part of the information processing apparatus 11, and is realized by the CPU 12 executing the control program according to the present embodiment in cooperation with the storage device 13.

[0050] As an example, the control unit 31 includes a determination unit 32, a decompression unit 33, a decoding unit 34, a verification unit 35, and an execution unit 36.

[0051] Among these, the determination unit 32 is a processing unit that determines whether the uncompressed microcode 14a stored in the microcode area 13b of the storage device 13 corresponds to the CPU 12. The decompression unit 33 is a processing unit that decompresses one of the plurality of compressed microcodes 14 stored in the compressed data area 13e of the storage device 13 into the microcode area 13b.

[0052] Furthermore, the expansion unit 33 expands the compressed and encrypted hash value 15 in the compressed data area 13e into the non-compressed hash value 15a in the hash value area 13c in an encrypted state.

[0053] The decryption unit 34 is a processing unit that decrypts the non-compressed hash value 15a stored in the hash value area 13c using the public key 16 corresponding to the secret key for encrypting the non-compressed hash value 15a.

[0054] The verification unit 35 is a processing unit that verifies the non-compressed microcode 14a using the hash value decrypted by the decryption unit 34.

[0055] The execution unit 36 is a processing unit that executes the BIOS program stored in the program area 13d.

[0056] Next, the control method according to the present embodiment will be described.

[0057] FIG. 7 is a sequence diagram of the control method according to the present embodiment. First, the determination unit 32 determines whether the compressed microcode 14 stored in the microcode area 13b corresponds to the CPU 12 actually mounted on the information processing apparatus 11 (step S31).

[0058] Next, the verification unit 35 calculates the hash value of the area combining the microcode area 13b and the program area 13d (step S32).

[0059] Next, the decryption unit 34 decrypts the non-compressed hash value 15a stored in the hash value area 13c using the public key 16 (step S33).

[0060] Next, the verification unit 35 verifies the authenticity of the uncompressed microcode 14a stored in the microcode area 13b (step S34). Here, when the hash value calculated in step S32 is equal to the hash value decoded in step S33, the verification unit 35 determines that the uncompressed microcode 14a has not been tampered with and is authentic. On the other hand, when these hash values are different, the verification unit 35 determines that the uncompressed microcode 14a has been tampered with and is not authentic.

[0061] Here, consider the case where in step S31, the uncompressed microcode 14a in the microcode area 13b corresponds to the current CPU 12, and it is found by verification that the uncompressed microcode 14a is authentic. In this case, the execution unit 36 executes the BIOS program and ends the process.

[0062] On the other hand, if in step S31 the uncompressed microcode 14a in the microcode area 13b does not correspond to the CPU 12, and it is found by verification that the uncompressed microcode 14a is authentic, the process proceeds to step S35.

[0063] In step S35, the execution unit 36 starts executing the startup code in the program area 13d.

[0064] Thereafter, the execution unit 36 performs startup processing such as initializing the stack area of a memory (not shown) (step S36).

[0065] Next, the determination unit 32 identifies the type of the CPU 12 (step S37).

[0066] Subsequently, the determination unit 32 specifies an index corresponding to the type of the CPU 12 specified in step S37 (step S38). For example, as shown in FIG. 4(b), when the type of the CPU is "B", the index is "11". The method for specifying the index is not particularly limited. For example, as shown in FIG. 4(a), information indicating the correspondence between the CPU 12 and the code may be stored in advance in the storage device 13, and the determination unit 32 may specify the index based on the code included in this information.

[0067] Next, the determination unit 32 calculates an offset (step S39). As described above, the offset is defined as the difference between the index corresponding to the type "A" of the CPU 12 and the index of the current type of the CPU 12. For example, when the current type of the CPU is "B", the index is 1 (= 11 - 10).

[0068] Next, the expansion unit 33 expands one of the plurality of compressed microcodes 14 stored in the compressed data area 13e as an uncompressed microcode 14 in the microcode area 13b (step S40). For example, the expansion unit 33 specifies an address offset corresponding to the index calculated in step S39 by referring to the compression order table 18. Then, the expansion unit 33 decompresses the compressed microcode 14 stored at the specified address offset, and writes the decompressed microcode 14 as an uncompressed microcode 14a in the microcode area 13b.

[0069] Next, the expansion unit 33 expands the compressed hash value 15 corresponding to the uncompressed microcode 14a expanded in step S40 in the hash value area 13c (step S41). For example, the expansion unit 33 decompresses the compressed hash value 15 corresponding to the microcode 14 expanded in step S40, and writes the decompressed encrypted hash value 15a in the hash value area 13c.

[0070] Next, the execution unit 36 resets the CPU 12 (step S42). After that, the process returns to step S31 again.

[0071] Thus, the basic processing of the control method according to the present embodiment is completed.

[0072] According to the above-described present embodiment, a plurality of compressed microcodes 14 corresponding to each of a plurality of types of the CPU 12 are stored in advance in the compressed data area 13e. Therefore, as compared with the case where the microcode 14 is not compressed, the size of each of the plurality of compressed microcodes 14 can be reduced, and the plurality of microcodes 14 can be stored in the storage device 13 with limited capacity.

[0073] Furthermore, when the uncompressed microcode 14a in the microcode area 13b does not correspond to the type of the CPU 14, the decompression unit 33 decompresses one of the compressed microcodes 14 into the microcode area 13b. Thereby, the storage device 13 can support a plurality of types of CPUs 14.

[0074] Moreover, the decompression unit 33 refers to the compression order table 18 to specify the address offset corresponding to the type of the CPU 12, and decompresses the compressed microcode 14 stored at the address offset into the microcode area 13b. Thereby, even when the uncompressed microcode 14 stored in the microcode area 13b does not correspond to the current type of the CPU 12, the decompression unit 33 can decompress the microcode corresponding to the current type of the CPU 12 into the microcode area 13b.

[0075] Also, the decompression unit 33 decompresses the compressed hash value 15 corresponding to the uncompressed microcode 14a in the microcode area 13b, and expands it as the uncompressed hash value 15a into the hash value area 13c. Thereby, the verification unit 35 can verify the authenticity of the uncompressed microcode 14a using the uncompressed hash value 15a.

Explanation of Reference Numerals

[0076] 1... Computer, 3... Memory device, 3a... Key area, 3b... Microcode area, 3c... Hash value area, 3d... Program area, 4... Microcode, 5... Hash value, 6... Public key, 11... Information processing device, 12... Processor, 13... Memory device, 13a... Key area, 13b... First area, 13b... Microcode area, 13c... Hash value area, 13d... Program area, 13e... Second area, 13e... Compressed data area, 14... Compressed microcode, 14a... Uncompressed microcode, 15... Compressed hash value, 15a... Uncompressed hash value, 16... Public key, 18... Compression order table, 19... Compressed data, 31... Control unit, 32... Determination unit, 33... Decompression unit, 34... Decryption unit, 35... Verification unit, 36... Execution unit.

Claims

1. Determine whether the first microcode stored in the first area of the storage device corresponds to the processor, When the first microcode does not correspond to the processor, expand one of the plurality of compressed second microcodes stored in the second area of the storage device to the first area, A control program for causing a computer to execute a process.

2. Correspondence information associating an identifier for identifying each of the plurality of compressed second microcodes with an address of each of the plurality of compressed second microcodes in the second area is stored in the storage device, The process of expanding the second microcode refers to the correspondence information, specifies the address related to the identifier corresponding to the processor, and expands the second microcode stored at the address to the first area. The control program according to claim 1, wherein the control program is performed.

3. An encrypted hash value of each of the plurality of compressed second microcodes is stored in the second area in a compressed state, When expanding the second microcode to the first area, the encrypted hash value corresponding to the second microcode is expanded to the third area of the storage device. The control program according to claim 1, wherein the control program is performed.

4. A public key corresponding to the secret key for encrypting the hash value is stored in the storage device, Decrypt the hash value with the public key, Verify the first microcode with the decrypted hash value, The control program according to claim 3 for causing the computer to execute a process.

5. A computer, Determine whether the first microcode stored in the first area of the storage device corresponds to the processor, When the first microcode does not correspond to the processor, expand one of the plurality of compressed second microcodes stored in the second area of the storage device to the first area, A control method characterized by executing a process.

6. A determination unit that determines whether the first microcode stored in the first area of the storage device corresponds to the processor, When the first microcode does not correspond to the processor, a decompression unit that decompresses one of a plurality of compressed second microcodes stored in a second area of the storage device into the first area; An information processing apparatus, characterized by comprising the same.

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