Power Conversion System and Inrush Current Suppression Method

Abstract

To suppress a rush current at an initiation stage of a voltage type power converter of a multi-parallel configuration.SOLUTION: A power conversion system starts energization from a converter via each of first to third rush current suppression parts, and pre-charges each of first to third capacitors while suppressing a current by using an impedance of each rush current suppression part in response to the starting of the energization. For some of the respective rush current suppression parts, the pre-charging is terminated late. The power conversion system determines a timing of terminating the pre-charging late on the basis of the magnitude of a current generated due to the earlier termination of the pre-charging in the respective rush current suppression parts.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present invention relate to a power conversion system and an inrush current suppression method.

Background Art

[0002] A voltage-type inverter that generates AC power from DC power includes a capacitor for smoothing the DC. When starting such an inverter, initial charging may be performed so that the voltage applied to the capacitor becomes a desired voltage. During this initial charging period, the current is limited to charge without excessive inrush current. When the initial charging period is completed and the above current limit is released when the voltage applied to the capacitor has risen to an appropriate voltage, if there is a potential difference between the above desired voltage (power supply voltage) and the voltage applied to the capacitor, an inrush current corresponding to this potential difference may occur. In the case of a configuration where the capacitance of the capacitor and the number of capacitors connected in parallel increase, the peak value of the current tends to increase.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a power converter and an inrush current suppression method capable of suppressing the inrush current at the start-up stage of a voltage-type inverter having a multi-parallel configuration.

Means for Solving the Problems

[0005] The power conversion system of the embodiment is a multi-parallel type in which a plurality of inverters are connected in parallel to the DC side of a converter that outputs DC power. The power conversion system includes a first capacitor and a first inverter, a second capacitor and a second inverter, a third capacitor and a third inverter, a first inrush current suppression unit, a second inrush current suppression unit, a third inrush current suppression unit, and a control unit. The first capacitor and the first inverter are connected to the output of the converter. The second capacitor and the second inverter are connected to the output of the converter. The third capacitor and the third inverter are connected to the output of the converter. The first inrush current suppression unit is provided on a first connection conductor between the output of the converter and the first capacitor. The second inrush current suppression unit is provided on a second connection conductor between the output of the converter and the second capacitor. The third inrush current suppression unit is provided on a third connection conductor between the output of the converter and the third capacitor. The first inrush current suppression unit includes a first impedance element that reduces the inrush current of the first capacitor and a first switch connected in parallel to the first impedance element. The second inrush current suppression unit includes a second impedance element that reduces the inrush current of the second capacitor and a second switch connected in parallel to the second impedance element. The third inrush current suppression unit includes a third impedance element that reduces the inrush current of the third capacitor and a third switch connected in parallel to the third impedance element. The control unit By starting the energization from the converter with the first switch, the second switch, and the third switch in a closed state, uses the impedance of each of the first inrush current suppression unit to the third inrush current suppression unit Impedance element to suppress the current while performing pre-charging of each of the capacitors from the first capacitor to the third capacitor of pre-charge to start and then Thereafter, by closing each switch with a time difference in the order of the first switch, the second switch, and the third switch, the magnitude of the inrush current included in the output current of the converter is reduced. The control unit preliminarily charges each of the capacitors from the first capacitor to the third capacitor using each inrush current suppression unit respectively.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Modes for Carrying Out the Invention

[0007] Hereinafter, the power conversion system and the inrush current suppression method according to the embodiments will be described with reference to the drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals, and redundant descriptions of these components may be omitted. Note that being electrically connected may be simply referred to as "connected". In the following description, the case of "equal in magnitude" includes a case of being approximately equal.

[0008] FIG. 1 is a configuration diagram of a power conversion system 1 according to an embodiment.

[0009] The power conversion system 1 includes, for example, a converter 2 (CNV), an inverter 3 (INV), a capacitor 4, an inrush current suppression unit 5, a control unit 6, a current detection unit 8, and a power conversion control device 10 (not shown).

[0010] First, the configuration of the main circuit of the power conversion system 1 will be described in order. The DC output of the converter 2 and the DC input of the inverter 3 are electrically connected to each other between the positive electrodes (P) and between the negative electrodes (N) via a DC link.

[0011] The converter 2 is, for example, a three-phase AC input type rectifier or an AC-DC power converter, and its input part is electrically connected to the secondary winding of an input transformer (not shown). The converter 2 converts the AC power input from the input transformer into DC power by rectifying the AC. The capacitor 4 is provided in the DC link, and each terminal of the capacitor 4 is electrically connected to the positive electrode (P) and the negative electrode (N) of the DC link, respectively. The capacitor 4 smoothes the converted DC voltage.

[0012] The inverter 3 has its AC side connected to the windings of the AC motor M. The inverter 3, for example, converts DC power into AC power and outputs the converted AC power to each phase of the AC motor M. Note that an output transformer (not shown) may be provided between the inverter 3 and the AC motor M. The inverter 3 includes, for example, a switching element that converts DC power on the DC side into AC power and an anti-parallel diode connected in anti-parallel to the switching element. The switching element is an example of a semiconductor switching element. For example, the inverter 3 is configured to be divided into three, and each is a single-phase AC output type inverter device.

[0013] Next, the power conversion control device 10 will be described. The power conversion control device 10 performs speed control and current control of the inverter 3 to generate a gate signal for controlling the switching element of the inverter 3. This power conversion control device 10 can apply a general configuration and a general control method.

[0014] As shown in FIG. 1, the power conversion system 1 of the embodiment is formed in a multi-parallel type in which each part of the inverter 3 configured to be divided into a plurality of parts is connected in parallel to the DC side of the converter 2 that outputs DC power.

[0015] The inverter 3 includes a first inverter 31, a second inverter 32, and a third inverter 33. For example, the first inverter 31, the second inverter 32, and the third inverter 33 may be configured to supply power to an AC motor M that is an AC load common to each other.

[0016] The capacitor 4 includes a first capacitor 41, a second capacitor 42, and a third capacitor 43. Each capacitor of the capacitor 4 is a so-called smoothing capacitor.

[0017] For example, as shown in FIG. 1, the power conversion system 1 includes a set of a first capacitor 41 and a first inverter 31 connected to the output of the converter 2, a set of a second capacitor 42 and a second inverter 32 connected to the output of the converter 2, and a set of a third capacitor 43 and a third inverter 33 connected to the output of the converter 2.

[0018] For example, the first inrush current suppression unit 51 is provided on the first connection conductor between the output of the converter 2 and the first capacitor 41. The second inrush current suppression unit 52 is provided on the second connection conductor between the output of the converter 2 and the second capacitor 42. The third inrush current suppression unit 53 is provided on the third connection conductor between the output of the converter 2 and the third capacitor 43. In other words, the first inrush current suppression unit 51 is provided on the first connection conductor between the output of the converter 2 and the set of the first capacitor 41 and the first inverter 31. The second inrush current suppression unit 52 is provided on the second connection conductor between the output of the converter 2 and the set of the second capacitor 42 and the second inverter 32. The third inrush current suppression unit 53 is provided on the third connection conductor between the output of the converter 2 and the set of the third capacitor 43 and the third inverter 33.

[0019] The current detection unit 8 includes a first current detection unit 81, a second current detection unit 82, and a third current detection unit 83. The first current detection unit 81 detects the current flowing through the first inrush current suppression unit 51. The second current detection unit 82 detects the current flowing through the second inrush current suppression unit 52. The third current detection unit 83 detects the current flowing through the third inrush current suppression unit 53. There is no limitation on the positions where the first current detection unit 81, the second current detection unit 82, and the third current detection unit 83 are arranged.

[0020] The control unit 6 includes, for example, a first control unit 61, a second control unit 62, and a third control unit 63. The first control unit 61, the second control unit 62, and the third control unit 63 may have the same configuration as each other.

[0021] The first control unit 61 controls the first inrush current suppression unit 51 to pre-charge the first capacitor 41 while suppressing the current using the impedance of the first inrush current suppression unit 51. When the pre-charging of the first capacitor 41 is completed, the first control unit 61 places the first inrush current suppression unit 51 in a conductive state. Thereby, a desired DC voltage is supplied to the first inverter 21. The second control unit 62 controls the second inrush current suppression unit 52 to pre-charge the second capacitor 42 while suppressing the current using the impedance of the second inrush current suppression unit 52. When the pre-charging of the second capacitor 42 is completed, the second control unit 62 places the second inrush current suppression unit 52 in a conductive state. Thereby, a desired DC voltage is supplied to the second inverter 22. The third control unit 63 controls the third inrush current suppression unit 53 to pre-charge the third capacitor 43 while suppressing the current using the impedance of the third inrush current suppression unit 53. When the pre-charging of the third capacitor 43 is completed, the third control unit 63 places the third inrush current suppression unit 53 in a conductive state. Thereby, a desired DC voltage is supplied to the third inverter 23.

[0022] Note that the first control unit 61, the second control unit 62, and the third control unit 63 may be collectively described as the control unit 6. Specific examples of the control of the control unit 6 will be described later.

[0023] With reference to FIG. 2, the inrush current suppression method of the embodiment will be described. FIG. 2 is a diagram for explaining the inrush current suppression method of the embodiment. Examples of the comparative example are shown in the left columns (a1) and (a2) of FIG. 2, and examples of the present embodiment are shown in the right columns (b1) and (b2) of FIG. 2. Typical transient changes in the voltage of the capacitor 4 are shown in the upper rows (a1) and (b1) of FIG. 2, and transient changes in the inrush current are shown in the lower rows (a2) and (b2) of FIG. 2.

[0024] Each capacitor from the first capacitor 41 to the third capacitor 43 at the initial stage of FIG. 2 is in a state where the terminal voltage is absent due to discharge. Therefore, each of the capacitors from the first capacitor 41 to the third capacitor 43 is pre-charged by each of the inrush current suppression units from the first inrush current suppression unit 51 to the third inrush current suppression unit 53, respectively.

[0025] For example, the control unit 6 starts energization from the converter 2 to each of the inrush current suppression units from the first inrush current suppression unit to the third inrush current suppression unit at time t0. In response to this, each capacitor from the first capacitor 41 to the third capacitor 43 is pre-charged while suppressing the current using the impedance of each of the inrush current suppression units.

[0026] By the way, in the case of the comparative examples in the left columns (a1) and (a2) of FIG. 2, pre-charging (initial charging) is performed so that the voltage applied to the capacitor 4 becomes a desired voltage after time t0. During this initial charging period, charging is performed while limiting the current so that an excessive inrush current does not occur. The pre-charging is terminated at the timing when the desired voltage is reached.

[0027] In the case of this comparative example, the pre-charging of each capacitor from the first capacitor 41 to the third capacitor 43 is terminated collectively with the timings aligned. If there is a difference between the terminal voltage VC of each capacitor at that timing and the reference voltage of the DC link (referred to as voltage VDC), even if the inrush current is configured to be relatively small as described above, an inrush current is generated in each capacitor. Since the polarities of the inrush currents generated in this case are aligned, an inrush current of a magnitude corresponding to the added value of each inrush current is generated. Therefore, as the number of inverters (the number of capacitors) increases, the overall inrush current increases and can become so large that it cannot be ignored. There has been a requirement to reduce such an overall inrush current.

[0028] In contrast, the power conversion system 1 of the embodiment starts the preliminary charging of each capacitor from the first capacitor 41 to the third capacitor 43 in the same manner as the comparative examples in the left columns (a1) and (a2) of FIG. 2 (see the right columns (b1) and (b2) of FIG. 2). However, the timing for ending the preliminary charging of each capacitor from the first capacitor 41 to the third capacitor 43 is deliberately made uneven. As a result, it is charged in the same manner as in the case of the above-described comparative example up to the middle of the preliminary charging. However, since the timing of the end of the preliminary charging is made uneven, the timing at which the peak value of the inrush current occurs for each capacitor is shifted and dispersed in the time axis direction, thereby reducing the peak value of the overall inrush current. A more specific configuration example will be described below.

[0029] Referring to FIG. 3, a configuration example of the control unit 6 of the embodiment will be described. FIG. 3 is a configuration diagram of the control unit 6 of the embodiment. Here, the first control unit 61 is illustrated as an example.

[0030] The first control unit 61 includes an initial charge element on control unit 611 and a delay unit 612 (DELAY).

[0031] The initial charge element on control unit 611 controls the conduction state of the semiconductor switching element (initial charge element) in the first inrush current suppression unit 51 using the DC voltage VDC and the capacitor voltage VC1. For example, the initial charge element on control unit 611 detects that the potential difference ΔV between the DC voltage VDC and the capacitor voltage VC1 has become smaller than a predetermined value ΔVTH, and generates a switching signal sel for switching the conduction state of the semiconductor switching element in the first inrush current suppression unit 51 from off to on in response to this detection.

[0032] Note that the predetermined value ΔVTH is set to a value other than 0. The predetermined value ΔVTH may be determined so that it can be detected that the potential difference ΔV has become smaller than the predetermined value ΔVTH during the rising process of the capacitor voltage VC1 and before reaching the DC voltage VDC.

[0033] The delay unit 612 generates a next-stage input signal indicating the timing to turn on the next-stage second inrush current suppression unit 52 and a next-stage input time tk by using the switching signal sel generated by the initial charge element on control unit 611, the DC voltage VDC, the capacitor voltage VC1, and the detected current I. This input signal is supplied to the control unit 6 (second control unit 62) of the next stage.

[0034] Referring to FIG. 4, a configuration example of the delay unit 612 shown in FIG. 3 will be described. FIG. 4 is a configuration diagram of the delay unit 612 shown in FIG. 3. The delay unit 612 includes arithmetic blocks 612a to 612d. The arithmetic block 612a calculates the effective value Irms of the detected current I. The arithmetic block 612a calculates, for example, the effective value Irms of the detected current I from the input time tk of the k-th stage to the current time t by using the input time tk and the instantaneous value of the detected current I as input variables. The delay unit 612 is included in the first control unit 61 of the first stage among the control units 6. The value of k, which is the identification information of the number of stages, is 1 in the case of the delay unit 612.

[0035] The arithmetic block 612b forms a subtractor. The arithmetic block 612b subtracts the capacitor voltage VC, which is the second input variable, from the DC voltage VDC, which is the first input variable, to generate a potential difference ΔV.

[0036] The arithmetic block 612c outputs the capacitance C of the first capacitor 41. The value of this capacitance C may be a predetermined fixed value.

[0037] The arithmetic block 612d calculates an input time t(k + 1) for instructing the operation of the second inverter 32 of the next stage by using the effective value Irms of the detected current I, the capacitance C of the first capacitor 41, and the potential difference ΔV as input variables. The variable k of the input time t(k + 1) indicates the number of stages. For example, the value of k in the case of the first control unit 61 corresponding to the first stage is 1. The input time t2 in the above case indicates the timing at which the operation start of the second inverter 32 is instructed. In the case of the second control unit 62 corresponding to the second stage, the value of the variable k is 2, and the same processing can be applied.

[0038] The above description relates to the first-stage delay section 612, but the same configuration as that of the delay section 612 can also be applied to the second-stage delay section 622 (not shown) and the third-stage delay section 632 (not shown). For example, the second-stage delay section 622 may determine the turn-on time t for the third inverter 33 based on a signal indicating the completion of the initial charging of the second capacitor 42 in the second stage (the second unit), the effective value Irms of the inrush current (current I) in the second stage (the second unit), and the potential difference ΔV at the time of its turn-on.

[0039] The third-stage delay section 632 may acquire information on the turn-on time t for the third inverter 33 and the initial charging completion signal of the second capacitor 42 in the second unit, and turn on the main power supply of the third inverter 33 in the third stage after the turn-on time t.

[0040] Referring to FIG. 5, a configuration example of the control unit 6 of the embodiment will be described. FIG. 5 is a configuration diagram of the control unit 6 in FIG. 3. Here, an example is shown in which the control unit 6 includes a first control unit 61, a second control unit 62, and a third control unit 63, which are connected in series. In the connection configuration shown in this FIG. 5, the first control unit 61, the second control unit 62, and the third control unit 63 are cascade-connected in the described order. There is no limitation on the physical connection (topology), and other forms of connection configurations may also be used.

[0041] The first control unit 61 in the first stage generates an input signal indicating the completion of the initial charging of the first capacitor 41 in the first stage, the start of energization of the first inverter 31 in response thereto, and the turn-on time t2 indicating the timing for turning on the second inverter 32 in the next stage, and supplies this to the second control unit 62 in the next stage.

[0042] The second control unit 62 in the second stage receives the input signal supplied from the first control unit 61 and the input time t2, and based on these, controls the conduction state of the semiconductor switching element of the second inrush current suppression unit 52. More specifically, the second control unit 62 turns on the semiconductor switching element of the second inrush current suppression unit 52 by detecting the input signal to start energization of the second inverter 32. The second control unit 62 further generates an input signal for indicating that energization has started in the next stage and the input time t3, and supplies these to the third control unit 63 in the next stage.

[0043] The third control unit 63 in the third stage receives the input signal supplied from the second control unit 62 and the input time t3, and based on these, controls the conduction state of the semiconductor switching element of the third inrush current suppression unit 53.

[0044] Note that if there are inrush current suppression units in the fourth stage and subsequent stages, although not shown in the figure, similar to the second control unit 62, the third control unit 63 may generate an input signal indicating the completion of initial charging in the next stage and the input time, and supply these to the control unit in the next stage.

[0045] The duration t (pulse width) of the inrush current in each stage is approximated as follows. Based on Equation (1) showing the relationship between the charge Q stored in the capacitor with capacitance C by the voltage V according to Coulomb's law, and Equation (2) showing this using the current I and the energization time t, Equation (3) is obtained by relating them. The duration t of the inrush current in each stage is calculated using Equation (3).

[0046] Q = CV (1) I × t = CV (2) t = CV / I (3)

[0047] By using the above equations (1) to (3), the timing for applying a predetermined power supply voltage to the inverter 3 may be determined based on the duration t of the inrush current described above. By optimizing the shift amount of this application timing using the duration t of the inrush current described above, the pulses of the inrush current for each stage can be discretized in the time axis direction. If there is no period during which the individual inrush currents of each stage overlap, the inrush currents of the stages will not flow at the same time. Based on this, a current larger than the pulses of the inrush current for each stage will not flow.

[0048] Incidentally, by sufficiently separating the intervals between the pulses of the inrush current for each stage, the peak value of the current can be suppressed. On the other hand, since the energization of each inverter is started step by step, the time until all the inverters start up becomes longer.

[0049] The power conversion system 1 of the present embodiment shortens the time until all the inverters start up by bringing the intervals between the pulses of the inrush current for each stage closer to each other within a possible range.

[0050] The timing for sequentially applying power to the inverters of each stage may be set to a predetermined shift amount (fixed value), and without being limited to this, the timing for sequential application may be set to a shift amount (variable value) that can be adjusted according to the state of the device. A combination of the above-described shift amount of the fixed value and the shift amount of the variable value may be used.

[0051] For example, the second inverter 32 in the second stage (the second unit) is turned on after a certain period (fixed value) has elapsed since the first inverter 31 in the first stage (the first unit) was turned on. The timing for turning on the third inverter 33 in the third stage (the third unit) is obtained from the information on the turn-on time t for the third inverter 33 in the third stage (the third unit) and the initial charge completion signal of the second capacitor 42 in the second stage.

[0052] A more specific example will be described with reference to FIG. 6. FIG. 6 is a diagram for explaining a more specific example of the inrush current suppression method using the control unit 6 shown in FIG. 5.

[0053] The figure shown in FIG. 6 is a time chart that shows, in order from the upper stage side, the voltages VC1-3 of the capacitors in each stage, the conduction states of the first inrush current suppression unit 51 to the third inrush current suppression unit 53, the operating states of the first inverter 31 to the third inverter 33, the detected currents (I1 to I3) in each stage, and the added value (IT) of the detected currents in each stage.

[0054] For example, at time t0, energization of each stage is started. As a result, the voltages VC (VC1-3) of the capacitors in each stage gradually increase. The curve shown in the uppermost stage is an example of an ideal voltage change. If the environment does not change during charging, the change as shown in the uppermost stage of FIG. 6 can be observed. After the first predetermined period T1 has elapsed since the start of energization, the time t1 comes, which is the timing to release the current suppression of the first inrush current suppression unit 51. When time t1 arrives, the first control unit 61 releases the current suppression of the first inrush current suppression unit 51. In response to this, the first control unit 61 turns on the first inrush current suppression unit 51 and maintains it in this state. As a result, the first inverter 31 becomes the operating state (ON).

[0055] At this time, after the second predetermined period T2 has elapsed since the control unit 6 (the first control unit 61) released the current suppression of the first inrush current suppression unit 51, the time t2 comes, which is the timing to release the current suppression of the second inrush current suppression unit 52. When time t2 arrives, the second control unit 62 releases the current suppression of the second inrush current suppression unit 52. In response to this, the second control unit 62 turns on the second inrush current suppression unit 52 and maintains it in this state. As a result, the second inverter 32 becomes the operating state (ON).

[0056] Furthermore, when a third predetermined period T3 has elapsed after the control unit 6 (second control unit 62) releases the current suppression of the second inrush current suppression unit 52, the time t3 at which the current suppression of the third inrush current suppression unit 53 is released is reached. When the time t3 is reached, the third control unit 63 releases the current suppression of the third inrush current suppression unit 53. In response thereto, the third control unit 63 energizes (turns ON) the third inrush current suppression unit 53 and maintains it in this state. As a result, the third inverter 33 becomes operational (ON).

[0057] In the procedure of the above inrush current suppression method, by controlling the first inrush current suppression unit 51 to the third inrush current suppression unit 53 and shifting the timing of switching the conduction states of the respective units, it is possible to avoid the inrush current concentrating at a specific timing.

[0058] The above sequence is an example of the inrush current suppression method of the embodiment. The detailed conditions of this sequence can be changed. For example, the first predetermined period and the second predetermined period may be set to desired lengths respectively. In this case, the control unit 6 may adjust and determine the length of the above third predetermined period using the magnitude of the effective value Irms of the current I flowing from the output of the converter 2 during the second predetermined period and the output voltage VC2 of the converter 2. Note that the current flowing from the output of the converter 2 during this second predetermined period includes a component that can be regarded as an inrush current with a steeply changing amplitude.

[0059] According to the above embodiment, the power conversion system 1 of the embodiment is a multi-parallel type in which a plurality of inverters 3 are connected in parallel to the DC side of the converter 2 that outputs DC power. The power conversion system 1 includes a first capacitor 41 and a first inverter 31, a second capacitor 42 and a second inverter 32, a third capacitor 43 and a third inverter 33, a first inrush current suppression unit 51, a second inrush current suppression unit 52, a third inrush current suppression unit 53, and a control unit 6. The first capacitor 41 and the first inverter 31 are connected to the output of the converter 2. The second capacitor 42 and the second inverter 32 are connected to the output of the converter 2. The third capacitor 43 and the third inverter 33 are connected to the output of the converter 2. The first inrush current suppression unit 51 is provided on a first connection conductor between the output of the converter 2 and the first capacitor 41. The second inrush current suppression unit 52 is provided on a second connection conductor between the output of the converter 2 and the second capacitor 42. The third inrush current suppression unit 53 is provided on a third connection conductor between the output of the converter 2 and the third capacitor 43. Through each of the inrush current suppression units from the first inrush current suppression unit 51 to the third inrush current suppression unit 53, energization from the converter 2 is started, and accordingly, while suppressing the current using the impedance of each inrush current suppression unit, each of the capacitors from the first capacitor 41 to the third capacitor 43 is pre-charged, and there is an inrush current suppression unit that finishes pre-charging late among the inrush current suppression units, and based on the magnitude of the current generated by the fact that the pre-charging has finished earlier among the inrush current suppression units, the timing for finishing the pre-charging late is determined. Thereby, the inrush current at the starting stage of the voltage type power converter with a multi-parallel configuration can be suppressed.

[0060] Note that the second control unit 62 may acquire a signal indicating that the difference (potential difference ΔV) between the DC voltage VDC by the output of the converter 2 and the terminal voltage VC1 of the first capacitor 41 is within a predetermined range, and determine that the initial charging of the first capacitor 41 is completed. Thereby, the second control unit 62 can indirectly acquire the timing when the initial charging of the first capacitor 41 is completed.

[0061] The third control unit 63 may obtain a signal indicating that the difference between the DC voltage VDC due to the output of the converter 2 and the terminal voltage VC of the second capacitor 42 is within a predetermined range, and determine that the initial charging of the second capacitor 42 is completed. Thereby, the third control unit 63 can indirectly obtain the timing at which the initial charging of the second capacitor 42 is completed.

[0062] (First Modification Example of the Embodiment) The first control unit 61 to the third control unit 63 constituting the control unit 6 of the embodiment were configured to be able to directly exchange information. In this modification example, a case will be described in which the first control unit 61 to the third control unit 63 do not directly exchange information, but the host controller intervenes to exchange information and issue commands to each of the first control unit 61 to the third control unit 63.

[0063] For example, the first control unit 61 to the third control unit 63 provide the above information to the host controller so that each can share information regarding the state of the initial charging completion signal of each stage, the stage identification information (inverter identification number), and the state of the input signal indicating that the switching element related to the initial charging suppression of each stage is to be turned on.

[0064] The host controller collects the above information and distributes the collected information to the first control unit 61 to the third control unit 63. Each control unit that receives the distribution is independent and autonomously controls the inrush current suppression unit of the corresponding stage. In this case, when each of the first control unit 61 to the third control unit 63 turns on the switching element (referred to as the initial charging element) in the inrush current suppression unit of each stage, even in a situation where the initial charging is completed, the stages in which the initial charging element is not on are extracted, and among the extracted ones, for example, the stages are selected in ascending order of the stage identification number (INV No), and the initial charging element of the selected stage is turned on. According to this modification example, by using the information aggregated by the host controller, the host controller can make a judgment based on this and issue commands to each control unit in the control unit 6 according to the judgment result.

[0065] (Second Modification Example of the Embodiment) The embodiment shows a case where each control unit in the control unit 6 is configured to be able to directly exchange information. In the first modification example, each control unit in the control unit 6 does not perform direct information exchange, but the host controller collects information and makes a determination using the information aggregated by the host controller, and issues commands to each control unit in the control unit 6. In contrast, in this modification example, similar to the first modification example, each control unit in the control unit 6 does not perform direct information exchange, and the host controller collects information. However, a case will be described in which the host controller does not make a determination as in the first modification example, but allows each control unit in the control unit 6 to make an autonomous determination.

[0066] The host controller in this modification example distributes the collected information to each control unit in the control unit 6 and allows each control unit in the control unit 6 to share it. Each control unit in the control unit 6 may make an autonomous determination based on the shared information.

[0067] For example, each control unit in the control unit 6 uses the shared memory provided respectively to store the information provided by the host controller (information such as "INV No", "initial charging completed", "main power supply turned on"). Each control unit in the control unit 6, in a situation where the initial charging is completed, if the main power supply of the inverter at that stage is not turned on and the identification number ("INV No") of its own stage is the smallest number among them, it is advisable to turn on the initial charging element of that stage. The determination to select the target stage may be carried out, for example, at a predetermined timing. By each control unit in the control unit 6 using the above determination method, a series of controls can be implemented without depending on the determination by the host controller.

[0068] According to at least one embodiment described above, the power conversion system is a multi-parallel type in which a plurality of inverters are connected in parallel to the DC side of a converter that outputs DC power. The power conversion system includes a first capacitor and a first inverter, a second capacitor and a second inverter, a third capacitor and a third inverter, a first inrush current suppression unit, a second inrush current suppression unit, a third inrush current suppression unit, and a control unit. The first capacitor and the first inverter are connected to the output of the converter. The second capacitor and the second inverter are connected to the output of the converter. The third capacitor and the third inverter are connected to the output of the converter. The first inrush current suppression unit is provided on a first connection conductor between the output of the converter and the first capacitor. The second inrush current suppression unit is provided on a second connection conductor between the output of the converter and the second capacitor. The third inrush current suppression unit is provided on a third connection conductor between the output of the converter and the third capacitor. The power conversion system starts energization from the converter through each inrush current suppression unit from the first inrush current suppression unit to the third inrush current suppression unit, and accordingly, while suppressing the current using the impedance of each inrush current suppression unit, each capacitor from the first capacitor to the third capacitor is pre-charged, and there is an inrush current suppression unit that finishes the pre-charging late among the inrush current suppression units, and based on the magnitude of the current generated by finishing the pre-charging earlier among the inrush current suppression units, the timing for finishing the pre-charging late is determined. Thereby, the power conversion system can suppress the inrush current at the starting stage of the voltage source inverter with a multi-parallel configuration.

[0069] In the power conversion system 1 of the embodiment described above, some or all of the functional units of the control unit 6 and the power conversion control device 10 are realized as software functional units by executing, for example, a program (computer program, software component) stored in a storage unit (such as a memory) of a computer by a processor (hardware processor) of the computer. Note that some or all of the functional units of the control device 7 and the cell unit control unit 6CUC may be realized by hardware such as LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), or FPGA (Field-Programmable Gate Array), or may be realized by a combination of a software functional unit and hardware.

[0070] As described above, several embodiments have been described, but the configurations of the embodiments are not limited to the above examples. For example, the configurations of the respective embodiments may be implemented in combination with each other, and can be applied to the configuration parts for which the description has been omitted. For example, the description regarding the U phase which is the first phase of the above-described AC motor M may be applied to the V phase which is the second phase and the W phase which is the third phase of the AC motor M.

[0071] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Description of Reference Numerals

[0072] 1... Power conversion system, 2... Converter, 3... Inverter, 4... Capacitor, 5... Inrush current suppression unit, 6... Control unit, 8... Current detection unit, 10... Power conversion control device 31... First inverter, 32... Second inverter, 33... Third inverter, 41... First capacitor, 42... Second capacitor, 43... Third capacitor, 51... First inrush current suppression unit, 52... Second inrush current suppression unit, 53... Third inrush current suppression unit, 61... First control unit, 62... Second control unit, 63... Third control unit, 81... First current detection unit, 82... First current detection unit, 83... First current detection unit, M... AC motor

Claims

1. A multi-parallel power conversion system in which a plurality of inverters are connected in parallel to the DC side of a converter that outputs DC power, a first capacitor and a first inverter connected to the output of the converter, a second capacitor and a second inverter connected to the output of the converter, a third capacitor and a third inverter connected to the output of the converter, a first inrush current suppression unit provided in a first connection conductor between the output of the converter and the first capacitor, a second inrush current suppression unit provided in a second connection conductor between the output of the converter and the second capacitor, a third inrush current suppression unit provided in a third connection conductor between the output of the converter and the third capacitor, a control unit that pre-charges each of the capacitors from the first capacitor to the third capacitor using each of the inrush current suppression units, comprising, the first inrush current suppression unit, comprises a first impedance element that reduces the inrush current of the first capacitor and a first switch connected in parallel to the first impedance element, the second inrush current suppression unit, comprises a second impedance element that reduces the inrush current of the second capacitor and a second switch connected in parallel to the second impedance element, the third inrush current suppression unit, comprises a third impedance element that reduces the inrush current of the third capacitor and a third switch connected in parallel to the third impedance element, the control unit, by starting energization from the converter with the first switch, the second switch, and the third switch closed, starting pre-charging of each capacitor from the first capacitor to the third capacitor while suppressing the current using the impedance of each impedance element of the first inrush current suppression unit to the third inrush current suppression unit, thereafter, by closing each switch with a time difference in the order of the first switch, the second switch, and the third switch, reducing the magnitude of the inrush current included in the output current of the converter Power conversion system.

2. The control unit, by closing the first switch after a first predetermined period has elapsed since the start of the energization, releasing the suppression of the current of the first inrush current suppression unit, and accordingly putting the first inrush current suppression unit in an energized state and maintaining it, After a second predetermined period has elapsed since the suppression of the current in the first inrush current suppression unit is released, the second switch is closed to release the suppression of the current in the second inrush current suppression unit, and accordingly, the second inrush current suppression unit is energized and maintained in this state. After a third predetermined period has elapsed since the suppression of the current in the second inrush current suppression unit is released, the third switch is closed to release the suppression of the current in the third inrush current suppression unit, and accordingly, the third inrush current suppression unit is energized. The power conversion system according to claim 1.

3. The control unit uses the magnitude of the effective value of the current flowing from the output of the converter during the second predetermined period and the output voltage of the converter to adjust the length of the third predetermined period. The power conversion system according to claim 2.

4. The current flowing from the output of the converter during the second predetermined period includes a component whose amplitude changes abruptly. The power conversion system according to claim 2.

5. The first predetermined period and the second predetermined period are set to desired lengths respectively. The power conversion system according to claim 2.

6. The control unit acquires a signal indicating that the difference between the DC voltage VDC due to the output of the converter and the terminal voltage VC of the first capacitor is within a predetermined range, and determines that the initial charging of the first capacitor is completed. The power conversion system according to claim 2.

7. The control unit acquires a signal indicating that the difference between the DC voltage VDC due to the output of the converter and the terminal voltage VC of the first capacitor is within a predetermined range, and determines that the initial charging of the first capacitor is completed. The power conversion system according to claim 6.

8. The first inverter, the second inverter, and the third inverter supply power to a common AC load. The power conversion system according to any one of claims 1 to 7.

9. An inrush current suppression method for a multi-parallel type power conversion system in which a plurality of inverters are connected in parallel to the DC side of a converter that outputs DC power, The power conversion system is a first capacitor and a first inverter connected to the output of the converter, a second capacitor and a second inverter connected to the output of the converter, a third capacitor and a third inverter connected to the output of the converter, A first inrush current suppression unit provided on a first connection conductor between the output of the converter and the first capacitor; A second inrush current suppression unit provided on a second connection conductor between the output of the converter and the second capacitor; A third inrush current suppression unit provided on a third connection conductor between the output of the converter and the third capacitor; comprising: The first inrush current suppression unit includes a first impedance element for reducing the inrush current of the first capacitor and a first switch connected in parallel to the first impedance element. The second inrush current suppression unit includes a second impedance element for reducing the inrush current of the second capacitor and a second switch connected in parallel to the second impedance element. The third inrush current suppression unit includes a third impedance element for reducing the inrush current of the third capacitor and a third switch connected in parallel to the third impedance element. By starting energization from the converter with the first switch, the second switch, and the third switch closed, energization from the converter is started through each of the inrush current suppression units from the first inrush current suppression unit to the third inrush current suppression unit. Accordingly, preliminary charging of each capacitor from the first capacitor to the third capacitor is started while suppressing the current using the impedance of each inrush current suppression unit. Thereafter, by closing each switch with a time difference in the order of the first switch, the second switch, and the third switch, the step of reducing the magnitude of the inrush current included in the output current of the converter. An inrush current suppression method including the above steps.

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