Synchronous barrier

Abstract

To allow for increased parallelism when executing an application.SOLUTION: Apparatuses, systems, and techniques for implementing a barrier operation are provided. In at least one embodiment, a memory barrier operation causes accesses to memory by a plurality of groups of threads to occur in an order indicated by the memory barrier operation.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 216,430, filed Jun. 29, 2021, entitled "SYNCHRONIZTION BARRIER", the entire contents of which are hereby incorporated by reference.

[0002] At least one embodiment relates to processing resources used to execute programs that use parallel processing. For example, at least one embodiment relates to a processor or computing system used to execute one or more CUDA programs that use a synchronized thread group.

Background Art

[0003] Configuring an application program to utilize multiple processing resources in parallel can significantly increase the performance of the program. For example, by increasing the number of processing cores that can be used simultaneously, the time required to complete a program can be reduced. Therefore, techniques that enable a greater amount of parallelism are an important area of development.

Summary of the Invention

Means for Solving the Problems

[0004] Provide a synchronization barrier.

Brief Description of the Drawings

[0005]

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[0006] This specification describes systems and methods that enable increased parallelism when executing an application by enabling increased flexibility in the composition of cooperating thread groups. In at least one embodiment, a cooperating thread group is a group of threads that operate on a multi-core processor or a graphics processing unit (“GPU”) having multiple cores such as CUDA cores. In at least one embodiment, each thread is assigned to a dedicated core and operates concurrently with other threads in the group.

[0007] In at least one embodiment, a cooperative group is a library feature that implements a cooperative model, and multiple threads are specified by a single group handle or identifier. In at least one embodiment, such a handle can be used to instruct all threads in the group to perform operations collectively. In at least one embodiment, a cooperative group can be used to split a thread block into groups of at most 32 threads. In at least one embodiment, this limitation is imposed by hardware limitations of the processor, such as the maximum size of an HW warp on a GPU. In at least one embodiment, such a limitation can make it difficult to represent the decomposition of a problem into larger groups of 128 or 256 threads, unless each fragment is a separate thread block.

[0008] At least one embodiment adds support for thread groups of sizes 64, 128, 256, 512, and 1024 threads to operate as cooperative groups, despite the 32 - thread limit per warp. In at least one embodiment, thus, a group of 64 or more threads spans multiple warps. In at least one embodiment, such groups can be used to represent synchronization and collective operations using fragments of a thread block. In at least one embodiment, such fragments are independent. In at least one embodiment, different fragments of a thread block can be specialized for different types of computations.

[0009] In at least one embodiment, collective operations may include one or more of reduce, all, any, and shfl. In at least one embodiment, a portion of the memory is reserved for the synchronization barriers used by these groups. In at least one embodiment, additional memory is reserved for the collective. In at least one embodiment, a multi-warp barrier is implemented using atomicAdd to count the arriving warps and use the most significant bit as the barrier phase. In at least one embodiment, each group uses a separate barrier, and thus one barrier is allocated per possible group.

[0010] In at least one embodiment, since the number of warps in a cooperative group is limited by the hardware (to 32, 64, or some other implementation-specific value), the entire range of integers is not required to count the arriving warps. However, in at least one embodiment, it may not be possible to use fewer bits as the barrier because the hardware atomic addition operation does not support smaller data types.

[0011] However, instead of using a smaller barrier, at least one embodiment takes advantage of the 32-warp limit by representing each warp in the group with one bit in a 32-bit barrier. In at least one embodiment, the arriving warps use an atomic OR operation to set the corresponding bit for recording the arrival. In at least one embodiment, the old value reshaped by the atomic OR operation is compared with the group mask, and if the warp is the last warp that should arrive at the barrier, an atomic AND operation is performed to clear all the bits representing the warps of the cooperative group and release them from the barrier described above.

[0012] In at least one embodiment, a single barrier can be used for multiple groups, unless the groups have a common warp. In at least one embodiment, in this approach, instead of one barrier per possible group, one barrier is required for each possible size of the multi-warp group.

[0013] Numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. It will be apparent to those skilled in the art, however, that the inventive concept may be practiced without one or more of these specific details.

[0014] In at least one embodiment, collective operations, multi-warp groups, and other features require the allocation of a working space (memory) shared by cooperating groups. In at least one embodiment, the lifetime of this memory is often limited to the duration of the collective operation and at most the lifetime of the kernel.

[0015] In at least one embodiment, for a thread block or a smaller scope, the cooperating group working space may exist in shared memory or global memory. In at least one embodiment, for a grid block or a smaller scope, the cooperating group working space may exist in global memory. In at least one embodiment, for a multi-grid or a smaller scope, the cooperating group working space may exist in unified memory or system memory.

[0016] In at least one embodiment, the working space in shared memory can be provided only within the kernel as a cutout from the kernel's total shared memory. In at least one embodiment, the working space in global memory should be provided at kernel startup using this contract. In at least one embodiment, during execution, the kernel has exclusive use of the global memory working space and, upon termination, the kernel has no rights to the global memory working space.

[0017] In at least one embodiment, the working space is a memory cutout provided by the user. In at least one embodiment, the working space is allocated by the driver and passed to the CG runtime via a parameter.

[0018] At least one embodiment enables any object that satisfies the is_trivially_copyable constraint to access the SoL shuffle implementation form. In at least one embodiment, the implementation should be adjusted for some given size. For example, an object of [1-8] bytes can use the native __shfl_xxx intrinsics, and larger objects can use multiple device shuffles or, ultimately, an in-memory shuffle accelerated using shared memory or global memory.

[0019] In at least one embodiment, this enables cg::reduce(...) to shuffle custom types. In at least one embodiment, complex number types and vector types are enabled to operate with the API.

Number

[0020] In at least one embodiment, developers often use matrix types or other abstractions for which device intrinsics usually do not have overloads. For example,

Number

[0021] In at least one embodiment, this use case is supported within the cooperative group warp / tiling interface and provides an easy way to access the SoL intrinsics when the object is trivial. In at least one embodiment, this also automatically extends the warp and tile cooperative_groups::reduce(...) that enable efficient SoL reduction in the complex data type.

[0022] In at least one embodiment, when the user attempts to shuffle a trivial object, the following front end is referenced.

Number

[0023] In at least one embodiment, exemplary objects that should cause a compile error.

Number

[0024] In at least one embodiment, the interface for tile and warp group shuffling will be modified to use a shuffle dispatch structure that automatically determines the strategy for a given object.

Number

[0025] In at least one embodiment, the interface for shuffle_dispatch inherits the strategy most suitable for shuffling a given object.

Number

[0026] In at least one embodiment, the design for the shuffle strategy is as follows.

Number

[0027] In at least one embodiment, the single warp limit is a common complaint about more complex producer / consumer models. In at least one embodiment, instead of creating a single warp, the solution can call two warps, either together or pipelined, and create an equal number of another set of warp consumers. In at least one embodiment, even in a single warp producer scenario, the solution may require one consumer to synchronize with the producer, independent of the other consumers. In at least one embodiment, this would require two different groups of two warps, each with 64 threads.

[0028] In at least one embodiment, the cooperating group enables the thread block to be statically split into groups of at most 32 threads (the size of a hardware warp). In at least one embodiment, it makes it impossible to represent the decomposition of the problem into groups of 128 or 256 threads. In at least one embodiment, the implementation of a class representing a group across multiple warps will make it possible to represent such a decomposition using the cooperating group in the same way the warp partition is represented. In at least one embodiment, the implementation of a group of 128 threads requires that the cooperating group be able to expose the intrinsics to the user in this way.

[0029] At least one embodiment modifies the thread_block_tile class to allow for sizes of 64, 128, 256, and 512 in addition to the smaller size of the thread block. In at least one embodiment, the class exposes different interfaces based on the size of the group. In at least one embodiment, for size <= 32, the class interface introduces threads within a single warp, such that they are executed in parallel. In at least one embodiment, for size > 32, the class exposes some of the methods present in thread_block_tile, namely sync, thread_rank, size, meta_group_rank, and meta_group_size. In at least one embodiment, it also exposes several of the sets present in thread_block_tile, namely any, all, and shfl, although in the case of shfl, only calls with the same source index in all calling threads are supported (broadcast operation).

[0030] In at least one embodiment, an interface that accepts thread_block_tile and memcpy_async, such as reduce, also accepts thread_block_tile with the new size, except for the binary_partition and labeled_partition functions.

[0031] In at least one embodiment, to implement synchronization and gathering, the method of multi-warp thread_block_tiles uses shared memory. In at least one embodiment, the user uses the block_tile_memory structure to provide this shared memory to the new this_thread_block overload so that the user can partition the thread_block into tiles of a new size. In at least one embodiment, the structure is declared as a shared memory variable. In at least one embodiment, the Block_tile_memory structure has two template parameters, the maximum number of threads that the current block can consist of, and the amount of memory in bytes that each warp can use for collective operations. In at least one embodiment, these arguments are needed to determine how much shared memory needs to be allocated. In at least one embodiment, since the new this_thread_block overload prepares the shared memory before the partitioned group is used, it is then called by all the threads in the partitioned group. [Number]

[0032] In at least one embodiment, the multi-warp thread_block_tile provides an interface that is a subset of the methods of the single-warp thread_block_tile. In at least one embodiment, the implementation of those methods requires that each group that can be created has exclusive access to a 4B memory location that is used as a barrier during the synchronization of that group. In at least one embodiment, only groups of size that is a power of two are allowed, and thus the number of all possible groups that can be obtained through the partitioning of a cooperative thread array (CTA) is equal to the number of warps in that CTA - 2.

[0033] In at least one embodiment, to implement a collective, each warp uses some memory for data exchange. In at least one embodiment, the amount of memory that each warp has access to is configured through the TileCommunicationSize template parameter to block_tile_memory.

[0034] In at least one embodiment, each CTA uses T / 32*(4 + P) bytes of shared memory, where T is the specified maximum number of threads in the CTA and P is the specified number of bytes per warp for collective operations. In at least one embodiment, this memory is statically allocated to different groups and the warps within those groups, thereby determining which should be used by members of the multi-warp thread_block_tile from that group's thread_rank and size.

[0035] In at least one embodiment, each template parameter of block_tile_memory has a default parameter. In at least one embodiment, the maximum CTA size is default set to 1024 threads, which is a hardware limit for CTA size. In at least one embodiment, the default per-warp memory size is set to 8B to enable efficient operation of the collective using the most common data types.

Number

[0036] In at least one embodiment, the collective is implemented according to the following reduction algorithm with minor modifications depending on the collective.

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[0037] In at least one embodiment, in the case of shfl, instead of the last warp arriving, the source warp releases other threads from the barrier. In at least one embodiment, for sets that operate on a larger type than specified per warp size (size of the reduction location), multiple rounds of data transfer are performed between each warp and the warp that releases.

[0038] In at least one embodiment, methods involving rank / size calculations such as thread_rank or meta_group_size are reused from the current implementation of thread_block_tile because the static rank / size calculation method is the same.

[0039] FIG. 1 shows an example of a warp according to at least one embodiment. In at least one embodiment, an application utilizes parallel processing by defining a plurality of threads that can be executed in parallel on a plurality of processing cores. In at least one embodiment, one thread 102 operates on one core 104. In at least one embodiment, a thread can be a copy or instance of a program or program segment. In at least one embodiment, a kernel is a function specified to operate multiple times on multiple cores. In at least one embodiment, a warp is a group of threads that operate in parallel on a set of processor cores. In at least one embodiment, warp 106 includes at most 32 threads 108. In at least one embodiment, the maximum number of threads that can be in a warp is limited by the implementation of the multiprocessor.

[0040] In at least one embodiment, a multi-processor, such as a graphical processing unit (“GPU”), is provided with code that defines a plurality of threads to be executed. In at least one embodiment, the GPU distributes the threads across a plurality of cores, which enables the threads to operate in parallel. In at least one embodiment, the threads are divided into 32-thread warps, which are then scheduled to operate one or more warps at a time. In at least one embodiment, the maximum size of a warp can be larger or smaller based on the type of GPU. In at least one embodiment, warps can operate in parallel or serially.

[0041] In at least one embodiment, a programmer can specify a group of threads to be executed as a cooperating group. In at least one embodiment, a cooperating group is a group of threads that should operate simultaneously on a corresponding number of cores. In at least one embodiment, if the cooperating group fits within a warp, the threads of the cooperating group are placed within a single warp and can be executed simultaneously. In at least one embodiment, if the number of threads in a cooperating group exceeds the maximum size of a warp, a mechanism is required to synchronize two or more warps of threads that should operate simultaneously.

[0042] Figure 2 shows an example of an inter-thread group spanning two warps according to at least one embodiment. In at least one embodiment, the first warp 202 and the second warp 204 are synchronized such that they execute in parallel. In at least one embodiment, the first warp 202 includes a first thread block 206 of 32 threads, and the second warp 204 includes a second thread block 208 of 32 threads, for a total of 64 threads that can operate as an inter-thread group. In at least one embodiment, the synchronization between the first warp 202 and the second warp 204 is achieved using a barrier 210. In at least one embodiment, the barrier 210 is stored in shared memory that is accessible to any thread in either the first warp 202 or the second warp 204.

[0043] In at least one embodiment, the barrier 210 is a 32-bit value. In at least one embodiment, when each warp has completed, the barrier 210 is incremented using an atomic addition operation. In at least one embodiment, when the value of the barrier 210 reaches the number of warps in the inter-thread group, it can be determined that all threads in the inter-thread block are synchronized. In at least one embodiment, the barrier 210 can be used to release the block threads in the first warp 202 or the second warp 204.

[0044] Figure 3 shows an example of an inter-thread group spanning four warps according to at least one embodiment. In at least one embodiment, the inter-thread group includes four warps, a first warp 302, a second warp 304, a third warp 306, and a fourth warp 308. In at least one embodiment, each warp has 32 threads, the first warp 302 has a first group 310 of threads, the second warp 304 has a second group 312 of threads, the third warp 306 has a third group 314 of threads, and the fourth warp 308 has a fourth group 316 of threads.

[0045] In at least one embodiment, the first warp 302, the second warp 304, the third warp 306, and the fourth warp 308 are synchronized using a barrier 318. In at least one embodiment, the barrier is implemented as a counter that starts at 0 and increments each time a warp is synchronized until the counter reaches 4, which indicates that all warps are synchronized. In at least one embodiment, the barrier 318 blocks all threads and releases them when 4 bits are set. In at least one embodiment, the barrier 318 is implemented as a bit field, where each bit represents a different warp. In at least one embodiment, when properly synchronized, all four warps and their associated threads can be executed and operate in concert.

[0046] FIG. 4 shows an example of an array of cooperating threads having four groups, where each group spans four warps, according to at least one embodiment. In at least one embodiment, the array of cooperating threads 402 includes four cooperating thread groups, a first cooperating group 404, a second cooperating group 406, a third cooperating group 408, and a fourth cooperating group 410. In at least one embodiment, each cooperating group spans four warps of 32 threads.

[0047] In at least one embodiment, the first cooperating group 404, the second cooperating group 408, the third cooperating group 410, and the fourth cooperating group 412 are synchronized using a barrier for each cooperating group. In at least one embodiment, the barrier is implemented as four counters stored in shared memory, where the four counters each start at 0 and increment each time a warp in the corresponding group is synchronized until the counter reaches 4, which indicates that all warps in the corresponding group are synchronized. Different breakdowns of groups and warps are possible, and the number of barriers required depends on the number of groups.

[0048] Figure 5 shows an example of an inter-thread array with four groups, where each group spans eight warps, according to at least one embodiment. In at least one embodiment, the inter-thread array 502 includes four inter-thread groups, a first inter-thread group 504 and a second inter-thread group 506. In at least one embodiment, each inter-thread group spans eight warps of 32 threads.

[0049] In at least one embodiment, the first inter-thread group 504 and the second inter-thread group 508 are synchronized using barriers for each inter-thread group. In at least one embodiment, the barriers are implemented as two counters stored in shared memory, and the two counters each start at 0 and increment when each warp in the corresponding group is synchronized until the counter reaches 8, which indicates that all warps in the corresponding group are synchronized.

[0050] In at least one embodiment, a multi-warp barrier is implemented using an atomic addition operation such as atomicAdd to count the arriving warps and use the most significant bit as a barrier phase. In at least one embodiment, each group uses a separate barrier, and thus a single barrier is allocated for each possible group. In at least one embodiment, the barriers are allocated in shared memory before group composition is known, and thus all possible barriers are allocated. In at least one embodiment, since the number of warps in a group is limited to 32, the full range of int is not required to count the arriving warps, but atomicAdd does not support a smaller type for use as a barrier instead.

[0051] In at least one embodiment, instead of using a smaller barrier, it relies on a limit of 32 warps to represent each warp in the group with 1 bit out of 32 bits of the 32-bit barrier. In at least one embodiment, the arriving warp, upon arrival, will use atomicOr to mark that bit. In at least one embodiment, the old value adjusted by atomicOr will be compared with the corresponding group mask, and if the warp is the last warp in the group that should arrive on the barrier, it will perform an atomicAnd to clear all the bits of the warps in the group and release them from the barrier.

[0052] In at least one embodiment, as long as these groups do not have a common warp, a single barrier can be used for multiple groups. In at least one embodiment, instead of one barrier for each possible group, one barrier is used for each possible size of the multi-warp group. In at least one embodiment, the memory requirement for the barrier is significantly reduced as shown in the following table.

Table 1

[0053] In at least one embodiment, for all cases, 8 barriers are allocated to leave room for possible future use cases similar to the arrival-wait barrier in the thread_block and for simplicity options. In at least one embodiment, it can be reduced to 4 for smaller CTAs.

[0054] In at least one embodiment, this barrier implementation enables the implementation of the arrival-wait function described below without using registers to maintain the barrier phase between arrival and wait.

[0055] In at least one embodiment, an arrival wait barrier is added to the CUDA device-side API, enabling similar functionality in CG groups larger than a single warp. In at least one embodiment, arrival and wait are collective, and in the case of thread_block_tile and thread_block, must be called by all threads in the warp, and in the case of grid_group, by all threads in the thread block.

[0056] In at least one embodiment, arrival marks the calling warp or thread block as having arrived at the group barrier. In at least one embodiment, the call to wait will block the calling thread until all warps or thread blocks have called arrival.

[0057] In at least one embodiment, arrival and wait must be called in pairs, and calling the wait function on a group will result in undefined behavior if the matching arrival call is not made on the same group in the calling thread. In at least one embodiment, calling arrival twice without a wait in between will result in undefined behavior.

[0058] In at least one embodiment, the current implementation of group synchronization is already done in the arrival and wait steps, and the implementation of these new functions will simply use the same algorithm exposed as two separate steps.

[0059] In at least one embodiment, the only exception to this is the thread_block group that uses the built-in syncthreads(). In at least one embodiment, in this case, the arrival and wait functions will use the multi-warp group implementation of these functions. In at least one embodiment, the multi-warp group is limited to a size that is a power of two, but the synchronization mechanism is not limited to situations where the thread block is a power of two.

[0060] In at least one embodiment, a memory barrier may be referred to as a membar, a memory fence, or a fence instruction. In at least one embodiment, the barrier is implemented as a barrier instruction that enforces ordering constraints on memory operations issued before and after the barrier instruction to the processor. In at least one embodiment, this may be enforced in hardware or software. In at least one embodiment, it is guaranteed that operations issued before the barrier are performed before operations issued after the barrier. In at least one embodiment, this may be referred to as synchronization.

[0061] In at least one embodiment, the barrier may be used when implementing low-level machine code that operates on memory shared by multiple devices, threads, or processes. In at least one embodiment, such code includes synchronization primitives and lock-free data structures on a multiprocessor system and device drivers that communicate with computer hardware.

[0062] FIG. 6 shows an example of a counter-based barrier implementation according to at least one embodiment. In at least one embodiment, the counter is used as a barrier for each possible group. In at least one embodiment, a CTA may be divided into various groups of warps, where each group contains an identified number of warps. In at least one embodiment, the groups are limited to a number of warps that is a power of two.

[0063] In at least one embodiment, when a 1024 - thread CTA is divided into 16 groups of 2 warps each, 16 barriers 602 are used. In at least one embodiment, each of the 16 barriers 602 is a 32 - bit value, which is incremented when each warp arrives at its corresponding barrier. In at least one embodiment, a smaller value (such as an 8 - bit byte) can be used as a barrier if an atomic addition operation that functions on such a value is available.

[0064] In at least one embodiment, when a 1024 - thread CTA is divided into 8 groups of 4 warps each, 8 barriers 604 are used. In at least one embodiment, each of the 8 barriers 604 is a 32 - bit value, which is incremented when each warp arrives at its corresponding barrier. In at least one embodiment, a smaller value (such as an 8 - bit byte) can be used as a barrier if an atomic addition operation that functions on such a value is available.

[0065] In at least one embodiment, when a 1024 - thread CTA is divided into 4 groups of 8 warps each, 4 barriers 604 are used. In at least one embodiment, each of the 4 barriers 606 is a 32 - bit value, which is incremented when each warp arrives at its corresponding barrier. In at least one embodiment, a smaller value (such as an 8 - bit byte) can be used as a barrier if an atomic addition operation that functions on such a value is available.

[0066] In at least one embodiment, when a 1024 - thread CTA is divided into 2 groups of 16 warps each, 2 barriers 604 are used. In at least one embodiment, each of the 2 barriers 608 is a 32 - bit value, which is incremented when each warp arrives at its corresponding barrier. In at least one embodiment, a smaller value (such as an 8 - bit byte) can be used as a barrier if an atomic addition operation that functions on such a value is available.

[0067] In at least one embodiment, if any of these groups is made available for use with 1024-thread CTAs, a total of 16 + 8 + 4 + 2 barriers are required.

[0068] FIG. 7 shows an example of a process for updating barriers for a multi-warp group as a result of being implemented by a computer system, according to at least one embodiment. In at least one embodiment, at block 702, the computer system is notified that a warp within a cooperating group has completed. In at least one embodiment, the status of the work can be tracked by the GPU, by a multi-core processor, or by an operating system that codes software to monitor the execution of threads within a core.

[0069] In at least one embodiment, as a result of determining that a warp has completed or is in a synchronized state, execution proceeds to block 704 and the computer system increments a barrier for that warp group. In at least one embodiment, the barrier is incremented using an atomic addition operation. In at least one embodiment, at decision block 706, the computer system determines whether all of the warps in the group have completed or synchronized, based at least in part on the value of the barrier. In at least one embodiment, synchronization of the cooperating group is determined by determining that the barrier value is greater than or equal to the number of warps in the cooperating group.

[0070] In at least one embodiment, if the computer system determines that not all warps in a group have completed, execution proceeds to block 708 and the computer system waits for another warp to complete. In at least one embodiment, if the computer system determines that all warps in a group have completed and are synchronized, execution proceeds to block 710. In at least one embodiment, at block 712, the barrier associated with the cooperative group is reset to zero and all warps associated with the cooperative group are released.

[0071] FIG. 8 shows an example of a barrier implementation based on a bit field according to at least one embodiment. In at least one embodiment, the barrier is implemented as a bit field, and each bit in the bit field represents a different warp in a cooperative thread group. In at least one embodiment, the state of the cooperative group is obtained by applying a mask associated with the group to the barrier along with a logical AND operation. In at least one embodiment, the bit associated with a warp is set by applying a mask associated with the warp to the barrier along with a logical OR operation. In at least one embodiment, the barrier for a group can be reset by applying the inverse of the associated mask to the barrier along with a logical and.

[0072] In at least one embodiment, a CTA of 1024 threads is divided into 16 groups of 2 warps each. In at least one embodiment, a single 32-bit barrier can represent all of the synchronization data required for all 16 groups. In at least one embodiment, the first byte 802 stores synchronization information for groups 1-4. In at least one embodiment, the second byte 804 stores synchronization information for groups 5-8. In at least one embodiment, the third byte 806 stores synchronization information for groups 9-12. In at least one embodiment, the fourth byte 808 stores synchronization information for groups 13-16.

[0073] In at least one embodiment, a CTA of 1024 threads is divided into eight groups of four warps each. In at least one embodiment, a single 32-bit barrier can represent all of the synchronization data required for all eight groups. In at least one embodiment, the first byte 810 stores the synchronization information for groups 1 and 2. In at least one embodiment, the second byte 812 stores the synchronization information for groups 3 and 4. In at least one embodiment, the third byte 814 stores the synchronization information for groups 5 and 6. In at least one embodiment, the fourth byte 816 stores the synchronization information for groups 7 and 8.

[0074] In at least one embodiment, a CTA of 1024 threads is divided into four groups of eight warps each. In at least one embodiment, a single 32-bit barrier can represent all of the synchronization data required for all four groups. In at least one embodiment, the first byte 818 stores the synchronization information for group 1. In at least one embodiment, the second byte 820 stores the synchronization information for group 2. In at least one embodiment, the third byte 822 stores the synchronization information for group 3. In at least one embodiment, the fourth byte 824 stores the synchronization information for group 4.

[0075] In at least one embodiment, a CTA of 1024 threads is divided into two groups of sixteen warps each. In at least one embodiment, a single 32-bit barrier can represent all of the synchronization data required for both groups. In at least one embodiment, the first byte 826 and the second byte 828 store the synchronization information for group 1. In at least one embodiment, the third byte 830 and the fourth byte 832 store the synchronization information for group 2.

[0076] In at least one embodiment, since multiple groups can share a single barrier, significantly less storage space is required. In at least one embodiment, all of the above interlocked groups require only four 32-bit values, as opposed to 30 values using the technique shown in FIG. 6.

[0077] FIG. 9 shows an example of a process for updating a barrier for a multi-warp group as a result of being implemented by a computer system, according to at least one embodiment. In at least one embodiment, at block 902, the computer system detects the completion of a group of parallel threads, which in some examples is called a warp. In at least one embodiment, at block 904, it is determined whether the warp is part of an interlocked group, and if so, the bits associated with the warp in the barrier of the interlocked group are set. In at least one embodiment, at block 906, the computer system obtains a bit mask associated with the interlocked group. In at least one embodiment, the mask is a 32-bit field, where a 1 indicates a bit associated with a warp of the group. In at least one embodiment, the mask is applied to the barrier associated with this group to determine, at 908, whether all of the warps of this group have reached the barrier.

[0078] In at least one embodiment, at decision block 908, if the computer system determines that not all bits for the interlocked group have been set, execution is directed to block 910 and the computer system waits for another warp of the thread to complete. In at least one embodiment, at decision block 908, if the computer system determines that all bits for the interlocked group have been set, execution proceeds to block 912 and it is determined that all warps of the interlocked group are synchronized at the barrier. In at least one embodiment, at block 914, the barrier is reset by clearing the bits associated with the interlocked group and releasing the associated warps.

[0079] Data Center In at least one embodiment, the techniques described above may be implemented in a data center such as data center 1000 as described below. In at least one embodiment, an application running in the data center may be divided into dependent threads that run in parallel on multiple processors. In at least one embodiment, the processor may include any processor type described below. In at least one embodiment, one or more circuits cause two or more dependent threads to be executed in parallel using two or more separate multi-threaded processor cores. In at least one embodiment, the processor core may be a core in a multi-core CPU, an SMP core in a GPU, or other circuitry capable of executing storable instructions. In at least one embodiment, one or more circuits cause a first group of threads to be organized into two or more subgroups of threads to be executed in parallel using two or more processor cores. In at least one embodiment, the group of threads may be a cooperating group that runs in parallel. In at least one embodiment, the cooperating group includes a plurality of kernel threads arranged in a warp on the GPU. In at least one embodiment, synchronization operations between threads may be enabled by the use of a barrier. In at least one embodiment, one or more circuits perform a memory barrier operation to cause accesses to memory by multiple groups of threads to occur in the order indicated by the memory barrier operation. In at least one embodiment, the barrier operation may be an atomic operation such as a bitwise logical operation (e.g., AND, OR, XOR), or a mathematical operation such as an atomic addition or subtraction.

[0080] FIG. 10 shows an exemplary data center 1000 according to at least one embodiment. In at least one embodiment, the data center 1000 includes, without limitation, a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0081] In at least one embodiment, as shown in FIG. 10, the data center infrastructure layer 1010 may include a resource orchestrator 1012, grouped computing resources 1014, and node computing resources (“node C.R.”) 1016(1) to 1016(N), where “N” represents any positive integer. In at least one embodiment, the node C.R. 1016(1) to 1016(N) may include, without limitation, any number of central processing units (“CPU”), or other processors (including accelerators, field programmable gate arrays (“FPGA”), data processing units (“DPU”) in network devices, graphics processors, etc.), memory devices (e.g., dynamic random access memory), storage devices (e.g., solid state or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VM”), power modules, and cooling modules. In at least one embodiment, one or more of the node C.R. 1016(1) to 1016(N) may be servers having one or more of the above-described computing resources.

[0082] In at least one embodiment, the grouped computing resources 1014 can include a distinct grouping of node C.R.s stored within one or more racks (not shown), or many racks stored within a data center at various geographic locations (also not shown). A distinct grouping of node C.R.s within the grouped computing resources 1014 can include grouped computing resources, network resources, memory resources, or storage resources that are configured or allocated to support one or more workloads. In at least one embodiment, some node C.R.s that include a CPU or processor can be grouped within one or more racks to provide computing resources for supporting one or more workloads. In at least one embodiment, one or more racks can also include any number of power modules, cooling modules, and network switches in any combination.

[0083] In at least one embodiment, the resource orchestrator 1012 can configure or otherwise control one or more node C.R.s 1016(1)-1016(N) and / or the grouped computing resources 1014. In at least one embodiment, the resource orchestrator 1012 can include a software design infrastructure ("SDI") management entity for the data center 1000. In at least one embodiment, the resource orchestrator 1012 can include hardware, software, or some combination thereof.

[0084] In at least one embodiment, as shown in FIG. 10, the framework layer 1020 includes, without limitation, a job scheduler 1032, a configuration manager 1034, a resource manager 1036, and a distributed file system 1038. In at least one embodiment, the framework layer 1020 may include a framework for supporting the software 1052 of the software layer 1030 and / or one or more applications 1042 of the application layer 1040. In at least one embodiment, the software 1052 or the application(s) 1042 may each include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1020 may be a type of free and open-source software web application framework, such as Apache Spark (trademark) (hereinafter "Spark"), which may utilize the distributed file system 1038 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 1032 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 1000. In at least one embodiment, the configuration manager 1034 may be able to configure different layers, such as the software layer 1030 and the framework layer 1020 including Spark and the distributed file system 1038 for supporting large-scale data processing. In at least one embodiment, the resource manager 1036 may be able to manage clustered or grouped computing resources that are mapped or allocated to support the distributed file system 1038 and the job scheduler 1032.In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1014 in the data center infrastructure layer 1010. In at least one embodiment, the resource manager 1036 may manage these mapped or allocated computing resources in cooperation with the resource orchestrator 1012.

[0085] In at least one embodiment, the software 1052 included in the software layer 1030 may include software used by at least a portion of the node C.R. 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1038 of the framework layer 1020. One or more types of software may include, but are not limited to, Internet web page search software, email virus scan software, database software, and streaming video content software.

[0086] In at least one embodiment, the application(s) 1042 included in the application layer 1040 may include one or more types of applications used by at least a portion of the node C.R. 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1038 of the framework layer 1020. In at least one or more types of applications, it may include, but is not limited to, CUDA applications.

[0087] In at least one embodiment, any one of configuration manager 1034, resource manager 1036, and resource orchestrator 1012 can implement any number and type of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions can free the data center operator of data center 1000 from determining configurations that may be defective and optionally avoiding parts of the data center that are not fully utilized and / or have low performance.

[0088] Computer-based system The following figures depict an exemplary computer-based system that can be used to implement at least one embodiment, without limitation.

[0089] In at least one embodiment, the techniques described above may be implemented on a computer system as described below, such as computer system 1200 or exemplary integrated circuit 1400. In at least one embodiment, an application running on a computer system may be divided into dependent threads that run in parallel on multiple processors. In at least one embodiment, the processor may include any processor type described below, including processing system 1100 or processing subsystem 1501. In at least one embodiment, one or more circuits cause two or more dependent threads to be executed in parallel using two or more separate multi-threaded processor cores. In at least one embodiment, the processor core may be a core in a multi-core CPU, an SMP core in a GPU, or other circuitry capable of executing storable instructions. In at least one embodiment, one or more circuits cause a first group of threads to be organized into two or more subgroups of threads to be executed in parallel using two or more processor cores. In at least one embodiment, the group of threads may be a cooperating group that runs in parallel. In at least one embodiment, the cooperating group includes a plurality of kernel threads arranged in a warp on a GPU. In at least one embodiment, the synchronization operation between threads may be enabled by the use of a barrier. In at least one embodiment, one or more circuits perform a memory barrier operation to cause access to memory by multiple groups of threads to occur in the order indicated by the memory barrier operation. In at least one embodiment, the barrier operation may be an atomic operation such as a bitwise logical operation (e.g., AND, OR, XOR), or a mathematical operation such as an atomic addition or subtraction.

[0090] FIG. 11 shows a processing system 1100 according to at least one embodiment. In at least one embodiment, the processing system 1100 includes one or more processors 1102 and one or more graphics processors 1108 and can be a single-processor desktop system, a multi-processor workstation system, or a server system having a number of processors 1102 or processor cores 1107. In at least one embodiment, the processing system 1100 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in a mobile device, a handheld device, or an embedded device.

[0091] In at least one embodiment, the processing system 1100 can include or be incorporated within a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, the processing system 1100 is a mobile phone, a smartphone, a tablet computing device or a mobile Internet device. In at least one embodiment, the processing system 1100 can also include, be coupled to, or be incorporated within wearable devices such as smartwatch wearable devices, smart eyewear devices, augmented reality devices, or virtual reality devices. In at least one embodiment, the processing system 1100 is a television or set-top box device having one or more processors 1102 and a graphical interface generated by one or more graphics processors 1108.

[0092] In at least one embodiment, one or more processors 1102 each include one or more processor cores 1107 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1107 is configured to process a particular instruction set 1109. In at least one embodiment, the instruction set 1109 can facilitate computing via a complex instruction set computing ("CISC"), reduced instruction set computing ("RISC"), or very long instruction word ("VLIW"). In at least one embodiment, the processor cores 1107 can each process different instruction sets 1109, and the instruction sets 1109 can include instructions for facilitating the emulation of other instruction sets. In at least one embodiment, the processor cores 1107 can also include other processing devices such as a digital signal processor ("DSP").

[0093] In at least one embodiment, the processor 1102 includes a cache memory (“cache”) 1104. In at least one embodiment, the processor 1102 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of the processor 1102. In at least one embodiment, the processor 1102 also uses an external cache (e.g., a level 3 (“L3”) cache or a last level cache (“LLC”)), not shown, and the external cache can be shared among the processor cores 1107 using known cache coherence techniques. In at least one embodiment, additionally, a register file 1106 is included in the processor 1102, and the register file 1106 can include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 1106 can include general purpose registers or other registers.

[0094] In at least one embodiment, one or more processors 1102 are coupled to one or more interface buses 1110 to transmit communication signals, such as address, data, or control signals, between the processor 1102 and other components in the processing system 1100. In at least one embodiment, the interface bus 1110 in one embodiment can be a processor bus, such as a version of a Direct Media Interface ("DMI") bus. In at least one embodiment, the interface bus 1110 is not limited to the DMI bus and can include one or more peripheral component interconnect buses (e.g., "PCI": Peripheral Component Interconnect, PCI Express ("PCIe")), memory buses, or other types of interface buses. In at least one embodiment, the (one or more) processors 1102 include an integrated memory controller 1116 and a platform controller hub 1130. In at least one embodiment, the memory controller 1116 facilitates communication between the memory device and other components of the processing system 1100, and the platform controller hub ("PCH") 1130 provides connections to I / O devices via a local input / output ("I / O") bus.

[0095] In at least one embodiment, the memory device 1120 can be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, a phase change memory device, or any other memory device having suitable performance to act as a processor memory. In at least one embodiment, the memory device 1120 can operate as a system memory for the processing system 1100 to store data 1122 and instructions 1121 for use when one or more processors 1102 execute an application or process. In at least one embodiment, the memory controller 1116 can also be coupled to an optional external graphics processor 1112, and the external graphics processor 1112 can communicate with one or more graphics processors 1108 in the processor 1102 to perform graphics operations and media operations. In at least one embodiment, the display device 1111 can be connected to the (one or more) processors 1102. In at least one embodiment, the display device 1111 can include one or more of an internal display device, such as in the case of a mobile electronic device or a laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 1111 can include a head mounted display ("HMD"), such as a stereoscopic display device for use in a virtual reality ("VR") application or an augmented reality ("AR") application.

[0096] In at least one embodiment, the platform controller hub 1130 enables peripheral devices to be connected to the memory device 1120 and the processor 1102 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 1146, a network controller 1134, a firmware interface 1128, a wireless transceiver 1126, a touch sensor 1125, and a data storage device 1124 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 1124 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as PCI or PCIe. In at least one embodiment, the touch sensor 1125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (「LTE」) transceiver. In at least one embodiment, the firmware interface 1128 enables communication with system firmware and can be, for example, a unified extensible firmware interface (「UEFI」). In at least one embodiment, the network controller 1134 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 1110. In at least one embodiment, the audio controller 1146 is a multi-channel high-definition audio controller.In at least one embodiment, the processing system 1100 includes an optional legacy I / O controller 1140 for coupling a legacy (e.g., Personal System 2 ("PS / 2")) device to the processing system 1100. In at least one embodiment, the platform controller hub 1130 can also be connected to one or more Universal Serial Bus ("USB") controller 1142 connected input devices, such as a combination of a keyboard and a mouse 1143, a camera 1144, or other USB input devices.

[0097] In at least one embodiment, instances of the memory controller 1116 and the platform controller hub 1130 can be incorporated into a discrete external graphics processor, such as the external graphics processor 1112. In at least one embodiment, the platform controller hub 1130 and / or the memory controller 1116 can be external to one or more processors 1102. For example, in at least one embodiment, the processing system 1100 can include an external memory controller 1116 and a platform controller hub 1130, which can be configured as a memory controller hub and a peripheral controller hub within a system chipset that communicates with the processor(s) 1102.

[0098] FIG. 12 shows a computer system 1200 according to at least one embodiment. In at least one embodiment, the computer system 1200 can be a system, SOC, or some combination with interconnected devices and components. In at least one embodiment, the computer system 1200 is formed with a processor 1202 that can include an execution unit for executing instructions. In at least one embodiment, the computer system 1200 can include components such as the processor 1202 for employing an execution unit that includes logic for implementing algorithms for processing data, among other things. In at least one embodiment, the computer system 1200 can include a processor such as a PENTIUM® processor family, Xeon™, Itanium® , XScale™, and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessor available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) can also be used. In at least one embodiment, the computer system 1200 can execute a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces can also be used.

[0099] In at least one embodiment, computer system 1200 can be used in other devices such as a handheld device and an embedded application. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application can include a microcontroller, a digital signal processor (“DSP”), a system on a chip (“SoC”), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of performing one or more instructions.

[0100] In at least one embodiment, computer system 1200 can include, without limitation, a processor 1202, and the processor 802 can include, without limitation, one or more execution units 1208 configured to execute a Compute Unified Device Architecture (“CUDA”) (CUDA (registered trademark) is developed by NVIDIA Corporation of Santa Clara, California) program. In at least one embodiment, the CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 1200 is a single-processor desktop or server system. In at least one embodiment, computer system 1200 can be a multi-processor system. In at least one embodiment, processor 1202 can include, without limitation, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device such as, for example, a digital signal processor. In at least one embodiment, processor 1202 can be coupled to a processor bus 1210, and the processor bus 1210 can transmit data signals between processor 1202 and other components in computer system 1200.

[0101] In at least one embodiment, the processor 1202 may include, without limitation, a level 1 ("L1") internal cache memory ("cache") 1204. In at least one embodiment, the processor 1202 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may exist external to the processor 1202. In at least one embodiment, the processor 1202 may also include a combination of both internal and external caches. In at least one embodiment, the register file 1206 may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer registers.

[0102] In at least one embodiment, an execution unit 1208 including logic for performing, without limitation, integer and floating point operations may also exist within the processor 1202. The processor 1202 may also include a microcode ("u-code") read only memory ("ROM") that stores microcode for several macro instructions. In at least one embodiment, the execution unit 1208 may include logic for handling a packed instruction set 1209. In at least one embodiment, by including the packed instruction set 1209 in the instruction set of the general purpose processor 1202 along with associated circuitry for executing the instructions, operations used by many multimedia applications may be performed using packed data in the general purpose processor 1202. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0103] In at least one embodiment, execution unit 1208 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuitry. In at least one embodiment, computer system 1200 may include, without limitation, memory 1220. In at least one embodiment, memory 1220 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other memory device. Memory 1220 may store (one or more) instructions 1219 and / or data 1221 represented by data signals executable by processor 1202.

[0104] In at least one embodiment, a system logic chip may be coupled to processor bus 1210 and memory 1220. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 1216, and processor 1202 may communicate with MCH 1216 via processor bus 1210. In at least one embodiment, MCH 1216 may provide a high-bandwidth memory path 1218 to memory 1220 for instruction and data storage, as well as for graphics command, data, and texture storage. In at least one embodiment, MCH 1216 may direct data signals between processor 1202, memory 1220, and other components in computer system 1200, and may bridge data signals between processor bus 1210, memory 1220, and system I / O 1222. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1216 may be coupled to memory 1220 through high-bandwidth memory path 1218, and graphics / video card 1212 may be coupled to MCH 1216 via an Accelerated Graphics Port (“AGP”) interconnect 1214.

[0105] In at least one embodiment, the computer system 1200 may use a system I / O 1222, which is a proprietary hub interface bus for coupling the MCH 1216 to an I / O controller hub (“ICH”) 1230. In at least one embodiment, the ICH 1230 may provide direct connections to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripheral devices to the memory 1220, the chipset, and the processor 1202. Examples may include, without limitation, an audio controller 1229, a firmware hub (“Flash BIOS”) 1228, a wireless transceiver 1226, a data storage 1224, a legacy I / O controller 1223 including a user input interface 1225 and a keyboard interface, a serial expansion port 1227 such as a USB, and a network controller 1234. The data storage 1224 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0106] In at least one embodiment, FIG. 12 shows a system including interconnected hardware devices or “chips”. In at least one embodiment, FIG. 12 may show an exemplary SoC. In at least one embodiment, the devices shown in FIG. 12 may be interconnected by a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the system 1200 are interconnected using a Compute Express Link (“CXL”) interconnect.

[0107] FIG. 13 shows a system 1300 according to at least one embodiment. In at least one embodiment, system 1300 is an electronic device that utilizes a processor 1310. In at least one embodiment, system 1300 can be, for example, but not limited to, a notebook, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more in-premises service providers or cloud service providers, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0108] In at least one embodiment, system 1300 can include a processor 1310 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices, for example, but not limited to. In at least one embodiment, processor 1310 is I 2Coupled using a bus or interface such as a C bus, a System Management Bus ("SMBus"), a Low Pin Count ("LPC") bus, a Serial Peripheral Interface ("SPI"), a High Definition Audio ("HDA") bus, a Serial Advance Technology Attachment ("SATA") bus, USB (versions 1, 2, 3), or a Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, FIG. 13 shows a system that includes interconnected hardware devices or "chips". In at least one embodiment, FIG. 13 may show an exemplary SoC. In at least one embodiment, the devices shown in FIG. 13 may be interconnected by proprietary interconnects, standard interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 13 are interconnected using a CXL interconnect.

[0109] In at least one embodiment, FIG. 13 shows a display 1324, a touch screen 1325, a touch pad 1330, a near field communication unit (NFC) 1345, a sensor hub 1340, a thermal sensor 1346, an express chipset (EC) 1335, a trusted platform module (TPM) 1338, a BIOS / firmware / flash memory (BIOS, FW flash) 1322, a DSP 1360, a solid state disk (SSD) or a hard disk drive (HDD) 1320, a wireless local area network unit (WLAN) 1350, a Bluetooth unit 1352, a wireless wide area network unit (WWAN) 1356, a global positioning system (GPS) 1355, a camera such as a USB3.0 camera (USB3.0 camera) 1354, or, for example, a low power double data rate (LPDDR) memory unit (LPDDR3) 1315 implemented in accordance with the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0110] In at least one example, through the components described above, other components may be communicatively coupled to the processor 1310. In at least one example, an accelerometer 1341, an ambient light sensor ("ALS"), a compass 1343, and a gyroscope 1344 may be communicatively coupled to the sensor hub 1340. In at least one example, a thermal sensor 1339, a fan 1337, a keyboard 1336, and a touch pad 1330 may be communicatively coupled to the EC 1335. In at least one example, a speaker 1363, headphones 1364, and a microphone ("mic") 1365 may be communicatively coupled to an audio unit ("audio codec and class D amplifier") 1362, and the audio unit 1362 may be communicatively coupled to the DSP 1360. In at least one example, the audio unit 1362 may include, for example, but not limited to, an audio coder / decoder ("codec") and a class D amplifier. In at least one example, a SIM card ("SIM") 1357 may be communicatively coupled to the WWAN unit 1356. In at least one example, components such as the WLAN unit 1350 and the Bluetooth unit 1352, as well as the WWAN unit 1356, may be implemented in a next generation form factor ("NGFF").

[0111] FIG. 14 shows an exemplary integrated circuit 1400 according to at least one embodiment. In at least one embodiment, the exemplary integrated circuit 1400 is a SoC that can be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 1400 includes one or more application processors 1405 (e.g., CPU, DPU), at least one graphics processor 1410, and additionally may include an image processor 1415 and / or a video processor 1420, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1400 includes peripheral devices or bus logic including a USB controller 1425, a UART controller 1430, an SPI / SDIO controller 1435, and an I 2 S / I 2 2C controller 1440. In at least one embodiment, the integrated circuit 1400 can include a display device 1445 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1450 and a mobile industry processor interface (MIPI) display interface 1455. In at least one embodiment, storage can be provided by a flash memory subsystem 1460 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface can be provided via a memory controller 1465 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1470.

[0112] FIG. 15 shows a computing system 1500 according to at least one embodiment. In at least one embodiment, the computing system 1500 includes a processing subsystem 1501 having one or more processors 1502 and a system memory 1504 that communicate via an interconnect path that may include a memory hub 1505. In at least one embodiment, the memory hub 1505 may be a separate component within a chipset component or may be integrated within one or more processors 1502. In at least one embodiment, the memory hub 1505 is coupled to an I / O subsystem 1511 via a communication link 1506. In at least one embodiment, the I / O subsystem 1511 includes an I / O hub 1507 that enables the computing system 1500 to receive inputs from one or more input devices 1508. In at least one embodiment, the I / O hub 1507 enables a display controller that may be included within one or more processors 1502 to provide outputs to one or more display devices 1510A. In at least one embodiment, one or more display devices 1510A coupled to the I / O hub 1507 can include local, internal, or embedded display devices.

[0113] In at least one embodiment, the processing subsystem 1501 includes one or more parallel processors 1512 coupled to the memory hub 1505 via a bus or other communication link 1513. In at least one embodiment, the communication link 1513 can be one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCIe, or can be a vendor-specific communication interface or communication fabric. In at least one embodiment, the one or more parallel processors 1512 include a number of processing cores and / or processing clusters, such as many integrated core processors, to form a parallel or vector processing system focused on calculations. In at least one embodiment, the one or more parallel processors 1512 form a graphics processing subsystem that can output pixels to one of one or more display devices 1510A coupled via the I / O hub 1507. In at least one embodiment, the one or more parallel processors 1512 can also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1510B.

[0114] In at least one embodiment, the system storage unit 1514 can be connected to the I / O hub 1507 to provide a storage mechanism for the computing system 1500. In at least one embodiment, an I / O switch 1516 can be used to provide an interface mechanism to enable connections between the I / O hub 1507 and other components such as a network adapter 1518 and / or a wireless network adapter 1519 that can be incorporated into the platform, and various other devices that can be added via one or more add-in devices 1520. In at least one embodiment, the network adapter 1518 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1519 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more wireless radios.

[0115] In at least one embodiment, the computing system 1500 can include other components not explicitly shown that can also be connected to the I / O hub 1507, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the communication paths interconnecting the various components in FIG. 15 can be implemented using any suitable protocol such as a PCI-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols such as NVLink high-speed interconnects, or interconnect protocols.

[0116] In at least one embodiment, one or more parallel processors 1512 incorporate circuitry optimized for graphics and video processing, including for example a video output circuit element, and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1512 incorporate circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 1500 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1512, memory hub 1505, processor(s) 1502, and I / O hub 1507 can be incorporated into a System-on-a-Chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1500 can be incorporated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1500 can be incorporated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system. In at least one embodiment, I / O subsystem 1511 and display device 1510B are omitted from computing system 1500.

[0117] Processing system The following figures depict an exemplary processing system that can be used to implement at least one embodiment, without limitation.

[0118] In at least one embodiment, instead of a Streaming Multiprocessor (“SM”), a Stream Processing Unit (“SPU”) may be used. In at least one embodiment, a single SPU includes a plurality of SPs, a branch control unit, and a storage register. In at least one embodiment, the SPU is grouped into SIMD cores that include a thread sequencer (or scheduler) for scheduling threads on each SPU. In at least one embodiment, each SIMD core includes its own shared memory between SPU, as well as other components such as texture units and caches. In at least one embodiment, each GPU includes a plurality of SIMD cores, as well as global data storage (such as random access memory (“RAM”)) and caches in the form of.

[0119] In at least one embodiment, in GCN and later in RDNA, the SPU is no longer required. In at least one embodiment, the SPs are combined into SIMD cores. In at least one embodiment, in the case of GCN, the SIMD core has 16 SPs and registers for shared memory. In at least one embodiment, in the case of RDNA, each SIMD core has 32 SPs and more shared memory. In at least one embodiment, a plurality of SIMD cores are combined into one compute unit (“CU”). In at least one embodiment, in the case of GCN, a single CU has 4 SIMD cores along with a data and instruction cache, a branch unit, and a “scalar ALU”. In at least one embodiment, the scalar ALU is a special ALU for performing one-time mathematical operations such as log, sin / cos, etc.

[0120] In at least one embodiment, for RDNA, a single CU has two SIMD cores with a scheduler, registers, and a scalar ALU for each SIMD core. In at least one embodiment, these CUs have the same number of SPs as in the case of GCN, but they are grouped into larger groups. In at least one embodiment, this serves a purpose when thread grouping as described below. In at least one embodiment, RDNA also pairs two CUs into a Work - Group Processor (WGP) where data and instruction caches are shared across the CUs. In at least one embodiment, the number of CUs / WGPs in a GPU varies across models.

[0121] In at least one embodiment, instead of a warp, a wavefront can be used. In at least one embodiment, GCN has 64 threads per wavefront, while RDNA cuts this in half to 32 threads per wavefront. In at least one embodiment, this allows for simplified scheduling and faster execution, such that an entire wavefront can be executed by each SIMD core. In at least one embodiment, each CU can process 4 wavefronts (GCN), where each SIMD core functions on a separate wavefront. In at least one embodiment, the hardware scheduler addresses dispatching independent thread groups for each SIMD core within each CU. In at least one embodiment, each SIMD core has its own internal scheduler. In at least one embodiment, an Asynchronous Compute Engine (ACE) can be used to schedule workloads across CUs. In at least one embodiment, ACE addresses resource allocation, context switching, etc., and schedules wavefronts across CUs.

[0122] In at least one embodiment, an "execution unit" or EU can be used instead of an SP. In at least one embodiment, an EU is a single thread unit with two sets of 4-wide SIMD circuits. In at least one embodiment, one set of SIMD circuits has an FPU and an integer ALU, and one set of SIMD circuits has an FPU and a special function unit (SFU), sometimes called an "extended math" (EM) unit. In at least one embodiment, each EU has a thread control unit and registers / memory for tracking thread state and data. In at least one embodiment, this can be used instead of a "core" in a "streaming multiprocessor" or a "streaming processor".

[0123] In at least one embodiment, EUs are grouped into "sub-slices" or "sub slices", which is a set of 16 EUs with a thread dispatch unit, an instruction cache, a data cache, a texture cache, a load / store unit, and something sometimes called a "sampler". In at least one embodiment, a "sub slice" is used instead of an SM or SIMD core. In at least one embodiment, sub slices are grouped into Xe "slices" or "X slices". In at least one embodiment, a slice or X slice can be used instead of a CU.

[0124] In at least one embodiment, a warp can be replaced with a wave, wavefront, or group of threads. In at least one embodiment, a "wave", "wavefront", or "thread" consists of at least 8 threads.

[0125] In at least one embodiment, the techniques described above may be implemented on a computer system as described below, such as computer system 1200 or exemplary integrated circuit 1400. In at least one embodiment, an application running on a computer system may be divided into dependent threads that run in parallel on multiple processors. In at least one embodiment, the processor may include any processor type described below, including APU 1600, CPU 1700, graphics core 2000, graphics processor 1910, GPGPU 2030, parallel processor 2100, graphics multiprocessor 2134, graphics processor 2200, processor 2300, processor 2400, graphics processor core 2500, PPU 2600, GPC 2700, SM 2800, or accelerator integration slice 1890. In at least one embodiment, one or more circuits cause two or more dependent threads to be executed in parallel using two or more distinct multithreaded processor cores. In at least one embodiment, the processor core may be a core in a multi-core CPU, an SMP core in a GPU, or other circuitry capable of executing storable instructions. In at least one embodiment, one or more circuits cause a first group of threads to be organized into two or more subgroups of threads to be executed in parallel using two or more processor cores. In at least one embodiment, the group of threads may be a cooperating group that runs in parallel. In at least one embodiment, the cooperating group includes a plurality of kernel threads arranged in a warp on a GPU. In at least one embodiment, synchronization operations between threads may be enabled by the use of a barrier. In at least one embodiment, one or more circuits perform a memory barrier operation to cause accesses to memory by multiple groups of threads to occur in the order indicated by the memory barrier operation.In at least one embodiment, the barrier operation can be an atomic operation such as a bitwise logical operation (e.g., AND, OR, XOR), or a mathematical operation such as an atomic addition or subtraction.

[0126] FIG. 16 shows an accelerated processing unit (APU) 1600 according to at least one embodiment. In at least one embodiment, the APU 1600 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the APU 1600 can be configured to execute application programs such as CUDA programs. In at least one embodiment, the APU 1600 includes, without limitation, a core complex 1610, a graphics complex 1640, a fabric 1660, an I / O interface 1670, a memory controller 1680, a display controller 1692, and a multimedia engine 1694. In at least one embodiment, the APU 1600 can include any number of core complexes 1610, any number of graphics complexes 1650, any number of display controllers 1692, and any number of multimedia engines 1694, in any combination. For illustrative purposes, multiple instances of the same object are shown herein with a reference number identifying the object and, if necessary, a numbered parenthesis identifying the instance.

[0127] In at least one embodiment, core complex 1610 is a CPU, graphics complex 1640 is a GPU, and APU 1600 is a processing unit that incorporates 1610 and 1640, among other things, on a single chip. In at least one embodiment, some tasks may be assigned to core complex 1610 and other tasks may be assigned to graphics complex 1640. In at least one embodiment, core complex 1610 is configured to execute main control software related to APU 1600, such as an operating system. In at least one embodiment, core complex 1610 is the master processor of APU 1600 and controls and coordinates the operation of other processors. In at least one embodiment, core complex 1610 issues commands that control the operation of graphics complex 1640. In at least one embodiment, core complex 1610 may be configured to execute host-executable code derived from CUDA source code, and graphics complex 1640 may be configured to execute device-executable code derived from CUDA source code.

[0128] In at least one embodiment, core complex 1610 includes, among other things, cores 1620(1) to 1620(4) and L3 cache 1630. In at least one embodiment, core complex 1610 may include any number of cores 1620 and any number and type of caches in any combination. In at least one embodiment, core 1620 is configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1620 is a CPU core.

[0129] In at least one embodiment, each core 1620 includes, without limitation, a fetch / decode unit 1622, an integer execution engine 1624, a floating point execution engine 1626, and an L2 cache 1628. In at least one embodiment, the fetch / decode unit 1622 fetches instructions, decodes such instructions, generates micro-operations, and dispatches separate micro-instructions to the integer execution engine 1624 and the floating point execution engine 1626. In at least one embodiment, the fetch / decode unit 1622 can simultaneously dispatch a micro-instruction to the integer execution engine 1624 and another micro-instruction to the floating point execution engine 1626. In at least one embodiment, the integer execution engine 1624 executes, without limitation, integer and memory operations. In at least one embodiment, the floating point engine 1626 executes, without limitation, floating point and vector operations. In at least one embodiment, the fetch decode unit 1622 dispatches micro-instructions to a single execution engine that replaces both the integer execution engine 1624 and the floating point execution engine 1626.

[0130] In at least one embodiment, each core 1620(i), where i is an integer representing a particular instance of core 1620, can access the L2 cache 1628(i) included in core 1620(i). In at least one embodiment, each core 1620 included in a core complex 1610(j), where j is an integer representing a particular instance of core complex 1610, is connected to other cores 1620 included in core complex 1610(j) via the L3 cache 1630(j) included in core complex 1610(j). In at least one embodiment, the cores 1620 included in a core complex 1610(j), where j is an integer representing a particular instance of core complex 1610, can access all of the L3 cache 1630(j) included in core complex 1610(j). In at least one embodiment, the L3 cache 1630 can include, without limitation, any number of slices.

[0131] In at least one embodiment, the graphics complex 1640 may be configured to perform compute operations in a highly parallel fashion. In at least one embodiment, the graphics complex 1640 is configured to perform graphics pipeline operations such as draw commands, pixel operations, geometric calculations, and other operations related to rendering images to a display. In at least one embodiment, the graphics complex 1640 is configured to perform operations not related to graphics. In at least one embodiment, the graphics complex 1640 is configured to perform both operations related to graphics and operations not related to graphics.

[0132] In at least one embodiment, the graphics complex 1640 includes, without limitation, any number of compute units 1650 and an L2 cache 1642. In at least one embodiment, the compute units 1650 share the L2 cache 1642. In at least one embodiment, the L2 cache 1642 is partitioned. In at least one embodiment, the graphics complex 1640 includes, without limitation, any number of compute units 1650 and any number and type of caches (including zero). In at least one embodiment, the graphics complex 1640 includes, without limitation, any amount of dedicated graphics hardware.

[0133] In at least one embodiment, each compute unit 1650 includes, without limitation, any number of SIMD units 1652 and shared memory 1654. In at least one embodiment, each SIMD unit 1652 can be configured to implement a SIMD architecture and perform operations in parallel. In at least one embodiment, each compute unit 1650 can execute any number of thread blocks, where each thread block executes on a single compute unit 1650. In at least one embodiment, a thread block includes, without limitation, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1652 executes different warps. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can synchronize with each other and communicate via the shared memory 1654.

[0134] In at least one embodiment, fabric 1660 is a system interconnect that facilitates data and control transmissions across core complex 1610, graphics complex 1640, I / O interface 1670, memory controller 1680, display controller 1692, and multimedia engine 1694. In at least one embodiment, APU 1600 may include any amount and type of system interconnects, in addition to or instead of fabric 1660, that facilitate data and control transmissions across any number and type of directly or indirectly linked components, which may be internal or external to APU 1600. In at least one embodiment, I / O interface 1670 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1670. In at least one embodiment, peripheral devices coupled to I / O interface 1670 may include, but are not limited to, keyboard, mouse, printer, scanner, joystick or other type of game controller, media recording device, external storage device, network interface card, etc.

[0135] In at least one embodiment, the display controller AMD92 displays an image on one or more display devices, such as a liquid crystal display (「LCD」) device. In at least one embodiment, the multimedia engine 1694 includes any amount and type of circuit elements related to multimedia, such as, but not limited to, a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, the memory controller 1680 facilitates data transfer between the APU 1600 and the unified system memory 1690. In at least one embodiment, the core complex 1610 and the graphics complex 1640 share the unified system memory 1690.

[0136] In at least one embodiment, the APU 1600 implements a memory subsystem that includes any amount and type of memory controller 1680 and memory devices (e.g., shared memory 1654) that can be dedicated to one component or shared among multiple components. In at least one embodiment, the APU 1600 implements a cache subsystem that includes one or more cache memories (e.g., L2 cache 1728, L3 cache 1630, and L2 cache 1642), and one or more cache memories can each be private to any number of components (e.g., core 1620, core complex 1610, SIMD unit 1652, compute unit 1650, and graphics complex 1640) or shared among any number of components.

[0137] Figure 17 shows a CPU 1700 according to at least one embodiment. In at least one embodiment, the CPU 1700 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the CPU 1700 can be configured to execute application programs. In at least one embodiment, the CPU 1700 is configured to execute main control software such as an operating system. In at least one embodiment, the CPU 1700 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1700 can be configured to execute host-executable code derived from CUDA source code, and the external GPU can be configured to execute device-executable code derived from such CUDA source code. In at least one embodiment, the CPU 1700 includes, without limitation, any number of core complexes 1710, a fabric 1760, an I / O interface 1770, and a memory controller 1780.

[0138] In at least one embodiment, the core complex 1710 includes, without limitation, cores 1720(1) to 1720(4) and an L3 cache 1730. In at least one embodiment, the core complex 1710 can include any number of cores 1720 and any number and type of caches in any combination. In at least one embodiment, the core 1720 is configured to execute instructions of a specific ISA. In at least one embodiment, each core 1720 is a CPU core.

[0139] In at least one embodiment, each core 1720 includes, but is not limited to, a fetch / decode unit 1722, an integer execution engine 1724, a floating point execution engine 1726, and an L2 cache 1728. In at least one embodiment, the fetch / decode unit 1722 fetches instructions, decodes such instructions, generates micro-operations, and dispatches separate micro-instructions to the integer execution engine 1724 and the floating point execution engine 1726. In at least one embodiment, the fetch / decode unit 1722 can simultaneously dispatch a micro-instruction to the integer execution engine 1724 and a separate micro-instruction to the floating point execution engine 1726. In at least one embodiment, the integer execution engine 1724 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating point engine 1726 performs, but is not limited to, floating point and vector operations. In at least one embodiment, the fetch decode unit 1722 dispatches micro-instructions to a single execution engine that replaces both the integer execution engine 1724 and the floating point execution engine 1726.

[0140] In at least one embodiment, each core 1720(i), where i is an integer representing a particular instance of core 1720, can access the L2 cache 1728(i) included in core 1720(i). In at least one embodiment, each core 1720 included in a core complex 1710(j), where j is an integer representing a particular instance of core complex 1710, is connected to other cores 1720 in the core complex 1710(j) via an L3 cache 1730(j) included in the core complex 1710(j). In at least one embodiment, a core 1720 included in a core complex 1710(j), where j is an integer representing a particular instance of core complex 1710, can access all of the L3 cache 1730(j) included in the core complex 1710(j). In at least one embodiment, the L3 cache 1730 can include, but is not limited to, any number of slices.

[0141] In at least one embodiment, fabric 1760 is a system interconnect that facilitates data and control transmissions across core complexes 1710(1) - 1710(N), where N is an integer greater than 0, I / O interface 1770, and memory controller 1780. In at least one embodiment, CPU 1700 may include any amount and type of system interconnect, in addition to or instead of fabric 1760, which facilitates data and control transmissions across any number and type of directly or indirectly linked components, which may be internal or external to CPU 1700. In at least one embodiment, I / O interface 1770 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1770. In at least one embodiment, peripheral devices coupled to I / O interface 1770 may include, but are not limited to, a display, keyboard, mouse, printer, scanner, joystick or other type of game controller, media recording device, external storage device, network interface card, etc.

[0142] In at least one embodiment, memory controller 1780 facilitates data transfer between CPU 1700 and system memory 1790. In at least one embodiment, core complex 1710 and graphics complex 1740 share system memory 1790. In at least one embodiment, CPU 1700 implements a memory subsystem that includes any amount and type of memory controller 1780 and memory devices, which may be dedicated to one component or shared among multiple components, without limitation. In at least one embodiment, CPU 1700 implements a cache subsystem that includes one or more cache memories (e.g., L2 cache 1728 and L3 cache 1730), and each of the one or more cache memories may be private to any number of components (e.g., core 1720 and core complex 1710) or shared among any number of components.

[0143] FIG. 18 shows an exemplary accelerator integration slice 1890 according to at least one embodiment. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integration circuit. In at least one embodiment, the accelerator integration circuit provides cache management, memory access, context management, and interrupt management services in place of a plurality of graphics processing engines included in a graphics acceleration module. Each graphics processing engine may comprise a separate GPU. Alternatively, a graphics processing engine may comprise different types of graphics processing engines, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine, within a GPU. In at least one embodiment, the graphics acceleration module may be a GPU having a plurality of graphics processing engines. In at least one embodiment, a graphics processing engine may be an individual GPU incorporated on a common package, line card, or chip.

[0144] The application effective address space 1882 within the system memory 1814 stores the process element 1883. In one embodiment, the process element 1883 is stored in response to a GPU call 1881 from an application 1880 executing on the processor 1807. The process element 1883 includes the process state of the corresponding application 1880. The work descriptor ("WD") 1884 included in the process element 1883 can be a single job requested by the application or may include a pointer to a queue of jobs. In at least one embodiment, the WD 1884 is a pointer to a job request queue in the application effective address space 1882.

[0145] The graphics acceleration module 1846 and / or individual graphics processing engines can be shared by all or a subset of the processes in the system. In at least one embodiment, the infrastructure for setting the process state and sending the WD 1884 to the graphics acceleration module 1846 to initiate a job in a virtualized environment can be included.

[0146] In at least one embodiment, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 1846 or an individual graphics processing engine. Since the graphics acceleration module 1846 is owned by a single process, the hypervisor initializes the accelerator integration circuit for the owning partition, and when the graphics acceleration module 1846 is allocated, the operating system initializes the accelerator integration circuit for the owning process.

[0147] During operation, the WD fetch unit 1891 in the accelerator integration slice 1890 fetches the next WD 1884, which contains instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1846. As shown, the data from the WD 1884 is stored in the register 1845 and can be used by the memory management unit ("MMU": memory management unit) 1839, the interrupt management circuit 1847, and / or the context management circuit 1848. For example, one embodiment of the MMU 1839 includes segment / page walk circuit elements for accessing the segment / page table 1886 within the OS virtual address space 1885. The interrupt management circuit 1847 can process interrupt events ("INT": interrupt) 1892 received from the graphics acceleration module 1846. When performing a graphics operation, the effective address 1893 generated by the graphics processing engine is translated to a physical address by the MMU 1839.

[0148] In one embodiment, the same set of registers 1845 is replicated for each graphics processing engine and / or the graphics acceleration module 1846 and can be initialized by the hypervisor or the operating system. Each of these replicated registers can be included within the accelerator integration slice 1890. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

Table 2

[0149] Exemplary registers that can be initialized by the operating system are shown in Table 2.

Table 3

[0150] In one embodiment, each WD1884 is specific to a particular graphics acceleration module 1846 and / or a particular graphics processing engine. The WD1884 either contains all the information required by the graphics processing engine to perform the work, or the WD1884 can be a pointer to a memory location set by the application for the command queue of the work to be completed.

[0151] FIGS. 19A-19B show an exemplary graphics processor according to at least one embodiment. In at least one embodiment, any of the exemplary graphics processors can be fabricated using one or more IP cores. In addition to what is shown, in at least one embodiment, other logic and circuitry can be included, including additional graphics processor / cores, peripheral interface controllers, or general purpose processor cores. In at least one embodiment, the exemplary graphics processor is for use within a SoC.

[0152] FIG. 19A shows an exemplary graphics processor 1910 of a SoC integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. FIG. 19B shows an additional exemplary graphics processor 1940 of a SoC integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the graphics processor 1910 of FIG. 19A is a low-power graphics processor core. In at least one embodiment, the graphics processor 1940 of FIG. 19B is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1910, 1940 can be a variation of the graphics processor 1410 of FIG. 14.

[0153] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A - 1915N (e.g., 1915A, 1915B, 1915C, 1915D - 1915N - 1, and 1915N). In at least one embodiment, the graphics processor 1910 can execute different shader programs via separate logic, whereby the vertex processor 1905 is optimized to perform operations for vertex shader programs, and the one or more fragment processors 1915A - 1915N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1905 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the (one or more) fragment processors 1915A - 1915N use the primitives and vertex data generated by the vertex processor 1905 to create a frame buffer to be displayed on a display device. In at least one embodiment, the (one or more) fragment processors 1915A - 1915N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs as provided in the Direct 3D API.

[0154] In at least one embodiment, the graphics processor 1910 additionally includes one or more MMUs 1920A - 1920B, one or more caches 1925A - 1925B, and one or more circuit interconnects 1930A - 1930B. In at least one embodiment, the one or more MMUs 1920A - 1920B provide virtual - physical address mapping for the graphics processor 1910, which includes the vertex processor 1905 and / or one or more fragment processors 1915A - 1915N, and they can reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1925A - 1925B. In at least one embodiment, the one or more MMUs 1920A - 1920B can be synchronized with one or more other MMUs in the system, which include one or more MMUs associated with one or more of the application processors 1405, image processors 1415, and / or video processors 1420 of FIG. 14, such that each processor 1405 - 1420 can participate in a shared or unified virtual memory system. In at least one embodiment, the one or more circuit interconnects 1930A - 1930B enable the graphics processor 1910 to interface with other IP cores within the SoC either via the internal bus of the SoC or via a direct connection.

[0155] In at least one embodiment, the graphics processor 1940 includes one or more MMUs 1920A-1920B, caches 1925A-1925B, and circuit interconnects 1930A-1930B of the graphics processor 1910 of FIG. 19A. In at least one embodiment, the graphics processor 1940 includes one or more shader cores 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F-1955N-1, and 1955N), and the one or more shader cores 1955A-1955N provide a unified shader core architecture that can execute all types of programmable shader code, where a single core, or type, or core includes shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter-core task manager 1945 that acts as a thread dispatcher for dispatching execution threads to the one or more shader cores 1955A-1955N, and a tiling unit 1958 for accelerating tiling operations for tile-based rendering, where rendering operations for a scene are sub-divided in the image space, for example, to utilize local spatial coherence within the scene or to optimize the use of internal caches.

[0156] FIG. 20A shows a graphics core 2000 according to at least one embodiment. In at least one embodiment, the graphics core 2000 may be included within the graphics processor 1410 of FIG. 14. In at least one embodiment, the graphics core 2000 may be unified shader cores 1955A-1955N as in the case of FIG. 19B. In at least one embodiment, the graphics core 2000 includes a shared instruction cache 2002, a texture unit 2018, and a cache / shared memory 2020, which are common to the execution resources within the graphics core 2000. In at least one embodiment, the graphics core 2000 can include a plurality of slices 2001A-2001N, or partitions for each core, and the graphics processor can include a plurality of instances of the graphics core 2000. The slices 2001A-2001N can include support logic including local instruction caches 2004A-2004N, thread schedulers 2006A-2006N, thread dispatchers 2008A-2008N, and register sets 2010A-2010N. In at least one embodiment, the slices 2001A-2001N can include a set of additional function units ("AFU"), floating-point units ("FPU") 2014A-2014N, integer arithmetic logic units ("ALU") 2016-2016N, address computational units ("ACU") 2013A-2013N, double-precision floating-point units ("DPFPU") 2015A-2015N, and matrix processing units ("MPU") 2017A-2017N.

[0157] In at least one embodiment, FPU2014A~2014N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and DPFPU2015A~2015N perform double-precision (64-bit) floating-point operations. In at least one embodiment, ALU2016A~2016N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, MPU2017A~2017N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, MPU2017~2017N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix to matrix multiplication (「GEMM」). In at least one embodiment, AFU2012A~2012N can perform additional logical operations not supported by a floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0158] FIG. 20B shows a general-purpose graphics processing unit (GPGPU) 2030 according to at least one embodiment. In at least one embodiment, the GPGPU 2030 is highly parallel and suitable for introduction on a multi-chip module. In at least one embodiment, the GPGPU 2030 can be configured to enable highly parallel compute operations to be performed by an array of GPUs. In at least one embodiment, the GPGPU 2030 can be directly linked to other instances of the GPGPU 2030 to create a multi-GPU cluster to improve the execution time for CUDA programs. In at least one embodiment, the GPGPU 2030 includes a host interface 2032 to enable connection to a host processor. In at least one embodiment, the host interface 2032 is a PCIe interface. In at least one embodiment, the host interface 2032 can be a vendor-specific communication interface or communication fabric. In at least one embodiment, the GPGPU 2030 receives commands from the host processor and uses a global scheduler 2034 to distribute the execution threads associated with those commands across a set of compute clusters 2036A-2036H. In at least one embodiment, the compute clusters 2036A-2036H share a cache memory 2038. In at least one embodiment, the cache memory 2038 can act as a higher-level cache for the cache memories within the compute clusters 2036A-2036H.

[0159] In at least one embodiment, the GPGPU 2030 includes memories 2044A - 2044B coupled to compute clusters 2036A - 2036H via a set of memory controllers 2042A - 2042B. In at least one embodiment, the memories 2044A - 2044B can include various types of memory devices, including DRAM, or graphics random access memory such as synchronous graphics random access memory (SGRAM) including graphics double data rate (GDDR) memory.

[0160] In at least one embodiment, each of the compute clusters 2036A - 2036H includes a set of graphics cores such as the graphics core 2000 of FIG. 20A, and the set of graphics cores can include multiple types of integer and floating - point logic units capable of performing arithmetic operations at various precisions, including those suitable for calculations related to CUDA programs. For example, in at least one embodiment, at least a subset of the floating - point units in each of the compute clusters 2036A - 2036H can be configured to perform 16 - bit or 32 - bit floating - point arithmetic, and different subsets of the floating - point units can be configured to perform 64 - bit floating - point arithmetic.

[0161] In at least one embodiment, multiple instances of the GPGPU2030 can be configured to operate as a compute cluster. Compute clusters 2036A - 2036H can implement any technically feasible communication technique for synchronization and data exchange. In at least one embodiment, multiple instances of the GPGPU2030 communicate via the host interface 2032. In at least one embodiment, the GPGPU2030 includes an I / O hub 2039, and the I / O hub 2039 couples the GPGPU2030 to a GPU link 2040 that enables a direct connection to other instances of the GPGPU2030. In at least one embodiment, the GPU link 2040 is coupled to a dedicated GPU - GPU bridge that enables communication and synchronization between multiple instances of the GPGPU2030. In at least one embodiment, the GPU link 2040 is coupled to a high - speed interconnect to transmit and receive data to / from other GPGPU2030s or parallel processors. In at least one embodiment, multiple instances of the GPGPU2030 are located in separate data processing systems and communicate via a network device accessible via the host interface 2032. In at least one embodiment, the GPU link 2040 can be configured to enable a connection to the host processor in addition to, or as an alternative to, the host interface 2032. In at least one embodiment, the GPGPU2030 can be configured to execute CUDA programs.

[0162] FIG. 21A shows a parallel processor 2100 according to at least one embodiment. In at least one embodiment, the various components of the parallel processor 2100 can be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or FPGAs.

[0163] In at least one embodiment, the parallel processor 2100 includes a parallel processing unit 2102. In at least one embodiment, the parallel processing unit 2102 includes an I / O unit 2104 that enables communication with other devices, including other instances of the parallel processing unit 2102. In at least one embodiment, the I / O unit 2104 may be directly connected to other devices. In at least one embodiment, the I / O unit 2104 connects to other devices via the use of a hub or switch interface, such as a memory hub 2105. In at least one embodiment, the connection between the memory hub 2105 and the I / O unit 2104 forms a communication link. In at least one embodiment, the I / O unit 2104 connects to a host interface 2106 and a memory crossbar 2116, where the host interface 2106 receives commands targeted at performing processing operations and the memory crossbar 2116 receives commands targeted at performing memory operations.

[0164] In at least one embodiment, when host interface 2106 receives a command buffer via I / O unit 2104, host interface 2106 can direct a work operation for implementing those commands to front end 2108. In at least one embodiment, front end 2108 is coupled to scheduler 2110, and scheduler 2110 is configured to distribute commands or other work items to processing array 2112. In at least one embodiment, scheduler 2110 ensures that processing array 2112 is properly configured and in an active state before tasks are distributed to processing array 2112. In at least one embodiment, scheduler 2110 is implemented via firmware logic running on a microcontroller. In at least one embodiment, microcontroller-implemented scheduler 2110 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularities, enabling rapid preemption and context switching of threads running on processing array 2112. In at least one embodiment, host software can attest a workload for scheduling on processing array 2112 via one of a plurality of graphics processing portals. In at least one embodiment, the workload can then be automatically distributed across processing array 2112 by scheduler 2110 logic within the microcontroller including scheduler 2110.

[0165] In at least one embodiment, the processing array 2112 can include up to "N" clusters (e.g., cluster 2114A, cluster 2114B to cluster 2114N). In at least one embodiment, each cluster 2114A to 2114N of the processing array 2112 can execute a number of simultaneous threads. In at least one embodiment, the scheduler 2110 can use various scheduling and / or workload distribution algorithms to allocate work to the clusters 2114A to 2114N of the processing array 2112, and those algorithms can vary according to the workload generated for each type of program or calculation. In at least one embodiment, the scheduling can be dynamically handled by the scheduler 2110 or can be partially assisted by the compiler logic during the compilation of the program logic configured for execution by the processing array 2112. In at least one embodiment, different clusters 2114A to 2114N of the processing array 2112 can be allocated to process different types of programs or to perform different types of calculations.

[0166] In at least one embodiment, the processing array 2112 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 2112 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 2112 can include logic for executing processing tasks including filtering video and / or audio data, performing modeling operations including physical operations, and performing data conversion.

[0167] In at least one embodiment, the processing array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 2112 can include additional logic for supporting the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 2112 can be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2102 can transfer data from the system memory through the I / O unit 2104 for processing. In at least one embodiment, during processing, the transferred data can be stored in on-chip memory (e.g., parallel processor memory 2122) during processing and then written back to the system memory.

[0168] In at least one embodiment, when the parallel processing unit 2102 is used to perform graphics processing, the scheduler 2110 may be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to the plurality of clusters 2114A - 2114N of the processing array 2112. In at least one embodiment, portions of the processing array 2112 may be configured to perform different types of processing. For example, in at least one embodiment, for display, to create a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data created by one or more of the clusters 2114A - 2114N may be stored in a buffer to enable the intermediate data to be transmitted between the clusters 2114A - 2114N for further processing.

[0169] In at least one embodiment, the processing array 2112 can receive processing tasks to be executed via a scheduler 2110, and the scheduler 2110 receives commands defining the processing tasks from a front end 2108. In at least one embodiment, the processing tasks can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, and state parameters and commands defining how the data is to be processed (e.g., which program is to be executed). In at least one embodiment, the scheduler 2110 can be configured to fetch an index corresponding to a task or can receive an index from the front end 2108. In at least one embodiment, the front end 2108 can be configured to ensure that the processing array 2112 is configured in an active state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is started.

[0170] In at least one embodiment, each of one or more instances of the parallel processing unit 2102 can be coupled to a parallel processor - memory 2122. In at least one embodiment, the parallel processor - memory 2122 can be accessed via a memory crossbar 2116, and the memory crossbar 1716 can receive memory requests from the processing array 2112 as well as the I / O unit 2104. In at least one embodiment, the memory crossbar 2116 can access the parallel processor - memory 2122 via a memory interface 2118. In at least one embodiment, the memory interface 2118 can include a plurality of partition units (e.g., partition unit 2120A, partition unit 2120B - partition unit 2120N), and the plurality of partition units can each be coupled to a portion (e.g., a memory unit) of the parallel processor - memory 2122. In at least one embodiment, the number of partition units 2120A - 2120N is configured to be equal to the number of memory units, such that the first partition unit 2120A has a corresponding first memory unit 2124A, the second partition unit 2120B has a corresponding memory unit 2124B, and the Nth partition unit 2120N has a corresponding Nth memory unit 2124N. In at least one embodiment, the number of partition units 2120A - 2120N may not be equal to the number of memory devices.

[0171] In at least one embodiment, the memory units 2124A-2124N can include various types of memory devices, including DRAM or graphics random access memory, such as SGRAM including GDDR memory. In at least one embodiment, the memory units 2124A-2124N can also include 3D stacked memory, including but not limited to high bandwidth memory ("HBM"). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 2122, a render target, such as a frame buffer or texture map, can be stored across the memory units 2124A-2124N, enabling the partition units 2120A-2120N to write portions of each render target in parallel. In at least one embodiment, a local instance of the parallel processor memory 2122 can be excluded to be advantageous for a unified memory design that utilizes system memory in conjunction with local cache memory.

[0172] In at least one embodiment, any one of clusters 2114A - 2114N of processing array 2112 can process data that is to be written to any one of memory units 2124A - 2124N within parallel processor - memory 2122. In at least one embodiment, memory crossbar 2116 can be configured to transfer the output of each of clusters 2114A - 2114N to any of partition units 2120A - 2120N that can perform additional processing operations on the output, or to another one of clusters 2114A - 2114N. In at least one embodiment, each of clusters 2114A - 2114N can communicate with memory interface 2118 through memory crossbar 2116 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2116 has a connection to memory interface 2118 for communicating with I / O unit 2104, as well as a connection to a local instance of parallel processor - memory 2122, which enables processing units within different clusters 2114A - 2114N to communicate with system memory or other memory that is not local to parallel processing unit 2102. In at least one embodiment, memory crossbar 2116 can use virtual channels to separate traffic streams between clusters 2114A - 2114N and partition units 2120A - 2120N.

[0173] In at least one embodiment, multiple instances of the parallel processing unit 2102 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of the parallel processing unit 2102 can be configured to interoperate even if the different instances have differences in the number of processing cores, the amount of local parallel processor memory, and / or other configurations. For example, in at least one embodiment, some instances of the parallel processing unit 2102 can include a higher precision floating point unit than other instances. In at least one embodiment, a system incorporating one or more instances of the parallel processing unit 2102 or the parallel processor 2100 can be implemented in various configurations and form factors including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0174] FIG. 21B shows a processing cluster 2194 according to at least one embodiment. In at least one embodiment, the processing cluster 2194 is included within a parallel processing unit. In at least one embodiment, the processing cluster 2194 is one of the processing clusters 2114A-2114N of FIG. 21. In at least one embodiment, the processing cluster 2194 may be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, a single instruction multiple data ("SIMD") instruction issue technique is used to support parallel execution of a number of threads without providing a plurality of independent instruction units. In at least one embodiment, a single instruction multiple thread ("SIMT") technique is used to support parallel execution of a number of threads that are overall synchronized, using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 2194.

[0175] In at least one embodiment, the operation of processing cluster 2194 can be controlled via a pipeline manager 2132 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 2132 receives instructions from scheduler 2110 of FIG. 21 and manages the execution of those instructions via graphics multiprocessor 2134 and / or texture unit 2136. In at least one embodiment, graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures can be included within processing cluster 2194. In at least one embodiment, one or more instances of graphics multiprocessor 2134 can be included within processing cluster 2194. In at least one embodiment, graphics multiprocessor 2134 can process data, and data crossbar 2140 can be used to distribute the processed data to one of a plurality of possible destinations including other shader units. In at least one embodiment, pipeline manager 2132 can facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via data crossbar 2140.

[0176] In at least one embodiment, each graphics multiprocessor 2134 within processing cluster 2194 can include the same set of function execution logic (e.g., arithmetic logic units, load / store units (“LSU”), etc.). In at least one embodiment, the function execution logic can be configured in a pipeline fashion where new instructions can be issued before the previous instruction has completed. In at least one embodiment, the function execution logic supports various operations including integer and floating point arithmetic, comparison operations, boolean operations, bit shifts, and the calculation of various algebraic functions. In at least one embodiment, the same function unit hardware can be utilized to perform different operations, and any combination of function units can exist.

[0177] In at least one embodiment, the instructions sent to processing cluster 2194 constitute a thread. In at least one embodiment, a set of threads running across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a program on different input data. In at least one embodiment, each thread within the thread group can be assigned to a different processing engine within graphics multiprocessor 2134. In at least one embodiment, the thread group can include fewer threads than the number of processing engines within graphics multiprocessor 2134. In at least one embodiment, when the thread group includes fewer threads than the number of processing engines, one or more of the processing engines can be idle during the cycles in which the thread group is being processed. In at least one embodiment, the thread group can also include more threads than the number of processing engines within graphics multiprocessor 2134. In at least one embodiment, when the thread group includes more threads than the number of processing engines within graphics multiprocessor 2134, processing can be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 2134.

[0178] In at least one embodiment, the graphics multi-processor 2134 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multi-processor 2134 can forego the internal cache and use the cache memory (e.g., L1 cache 2148) within the processing cluster 2194. In at least one embodiment, each graphics multi-processor 2134 also has access to a level 2 (“L2”) cache within a partition unit (e.g., partition units 2120A-2120N of FIG. 21A), and those L2 caches are shared among all processing clusters 2194 and can be used to transfer data between threads. In at least one embodiment, the graphics multi-processor 2134 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to the parallel processing unit 2102 can be used as global memory. In at least one embodiment, the processing cluster 2194 includes multiple instances of the graphics multi-processor 2134, and the graphics multi-processor 2134 can share common instructions and data, and the common instructions and data can be stored in the L1 cache 2148.

[0179] In at least one embodiment, each processing cluster 2194 may include an MMU 2145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2145 may be present within the memory interface 2118 of FIG. 21. In at least one embodiment, the MMU 2145 includes a set of page table entries ("PTEs") used to map virtual addresses to the physical addresses of tiles and optionally cache line indices. In at least one embodiment, the MMU 2145 may include a translation lookaside buffer ("TLB") or cache, which may be present within the graphics multiprocessor 2134 or the L1 cache 2148 or the processing cluster 2194. In at least one embodiment, the physical addresses are processed to spread surface data access locality and enable efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0180] In at least one embodiment, processing cluster 2194 may be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 for performing texture mapping operations, such as determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2134 and, if necessary, fetched from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2134 outputs the processed task to the data crossbar 2140 to provide the processed task to another processing cluster 2194 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 2116. In at least one embodiment, a pre-raster operation unit ("pre-ROP") 2142 is configured to receive data from the graphics multiprocessor 2134 and direct the data to a ROP unit, which may be located with a partitioning unit (e.g., partitioning units 2120A - 2120N of FIG. 21) as described herein. In at least one embodiment, the pre-ROP 2142 can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0181] FIG. 21C shows a graphics multiprocessor 2196 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2196 is the graphics multiprocessor 2134 of FIG. 21B. In at least one embodiment, the graphics multiprocessor 2196 couples to a pipeline manager 2132 of a processing cluster 2194. In at least one embodiment, the graphics multiprocessor 2196 has an execution pipeline including, without limitation, an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more GPGPU cores 2162, and one or more LSUs 2166. The GPGPU cores 2162 and LSUs 2166 couple to a cache memory 2172 and a shared memory 2170 via a memory and cache interconnect 2168.

[0182] In at least one embodiment, the instruction cache 2152 receives a stream of instructions to execute from the pipeline manager 2132. In at least one embodiment, the instructions are cached in the instruction cache 2152 and dispatched for execution by the instruction unit 2154. In at least one embodiment, the instruction unit 2154 can dispatch instructions as a thread group (e.g., a warp), and each thread of the thread group is assigned to a different execution unit within the GPGPU core 2162. In at least one embodiment, instructions can access any of a local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, the address mapping unit 2156 can be used to translate an address in the unified address space to an individual memory address that can be accessed by the LSU 2166.

[0183] In at least one embodiment, register file 2158 provides a set of registers to the functional units of graphics multiprocessor 2196. In at least one embodiment, register file 2158 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 2162, LSU 2166) of graphics multiprocessor 2196. In at least one embodiment, register file 2158 is divided among each of the functional units such that each functional unit is allocated a dedicated portion of register file 2158. In at least one embodiment, register file 2158 is divided among different thread groups being executed by graphics multiprocessor 2196.

[0184] In at least one embodiment, each of GPGPU cores 2162 can include an FPU and / or an integer ALU used to execute the instructions of graphics multiprocessor 2196. GPGPU cores 2162 can have the same architecture or different architectures. In at least one embodiment, a first portion of GPGPU core 2162 includes a single-precision FPU and an integer ALU, and a second portion of GPGPU core 2162 includes a double-precision FPU. In at least one embodiment, the FPU can implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, graphics multiprocessor 2196 can additionally include one or more fixed-function units or special-function units for performing specific functions such as rectangle copy operations or pixel blending operations. In at least one embodiment, one or more of GPGPU cores 2162 can also include fixed or special-function logic.

[0185] In at least one embodiment, the GPGPU core 2162 includes SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2162 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core 2162 are generated at compile time by a shader compiler or can be automatically generated when executing a compiled program written for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0186] In at least one embodiment, the memory and cache interconnect 2168 is an interconnect network that connects each functional unit of the graphics multiprocessor 2196 to the register file 2158 and the shared memory 2170. In at least one embodiment, the memory and cache interconnect 2168 is a crossbar interconnect that enables the LSU 2166 to implement load and store operations between the shared memory 2170 and the register file 2158. In at least one embodiment, the register file 2158 can operate at the same frequency as the GPGPU core 2162, and thus, the data transfer between the GPGPU core 2162 and the register file 2158 has a very low latency. In at least one embodiment, the shared memory 2170 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2196. In at least one embodiment, the cache memory 2172 can be used as a data cache, for example, to cache texture data communicated between a functional unit and the texture unit 2136. In at least one embodiment, the shared memory 2170 can also be used as a cached and managed program. In at least one embodiment, a thread executing on the GPGPU core 2162 can programmatically store data in the shared memory in addition to automatically cached data stored in the cache memory 2172.

[0187] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor / core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU is integrated as a core on the same package or die and can be communicatively coupled to the core via a processor bus / interconnect internal to the package or die. In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic for efficiently processing these commands / instructions.

[0188] FIG. 22 shows a graphics processor 2200 according to at least one embodiment. In at least one embodiment, the graphics processor 2200 includes a ring interconnect 2202, a pipeline front end 2204, a media engine 2237, and graphics cores 2280A - 2280N. In at least one embodiment, the ring interconnect 2202 couples the graphics processor 2200 to other graphics processors or other processing units including one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2200 is one of many processors incorporated within a multi-core processing system.

[0189] In at least one embodiment, the graphics processor 2200 receives a batch of commands via the ring interconnect 2202. In at least one embodiment, incoming commands are interpreted by the command streamer 2203 in the pipeline front end 2204. In at least one embodiment, the graphics processor 2200 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 2280A - 2280N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2203 supplies the commands to the geometry pipeline 2236. In at least one embodiment, for at least some media processing commands, the command streamer 2203 supplies the commands to the video front end 2234, and the video front end 2234 is coupled to the media engine 2237. In at least one embodiment, the media engine 2237 includes a video quality engine (“VQE”) 2230 for video and image post - processing and a multi - format encode / decode (“MFX”) engine 2233 for providing hardware - accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2236 and the media engine 2237 each generate execution threads for the thread execution resources provided by at least one graphics core 2280A.

[0190] In at least one embodiment, the graphics processor 2200 includes a scalable thread execution resource characterized by modular graphics cores 2280A - 2280N (which may be referred to as core slices), each having a plurality of sub - cores 2250A - 2250N, 2260A - 2260N (which may be referred to as core sub - slices). In at least one embodiment, the graphics processor 2200 can have any number of graphics cores 2280A - 2280N. In at least one embodiment, the graphics processor 2200 includes a graphics core 2280A having at least a first sub - core 2250A and a second sub - core 2260A. In at least one embodiment, the graphics processor 2200 is a low - power processor having a single sub - core (e.g., sub - core 2250A). In at least one embodiment, the graphics processor 2200 includes a plurality of graphics cores 2280A - 2280N, each including a first set of sub - cores 2250A - 2250N and a second set of sub - cores 2260A - 2260N. In at least one embodiment, each sub - core in the first set of sub - cores 2250A - 2250N includes at least an execution unit ("EU") 2252A - 2252N and a first set of media / texture samplers 2254A - 2254N. In at least one embodiment, each sub - core in the second set of sub - cores 2260A - 2260N includes at least an execution unit 2262A - 2262N and a second set of samplers 2264A - 2264N. In at least one embodiment, each of the sub - cores 2250A - 2250N, 2260A - 2260N shares a set of shared resources 2270A - 2270N. In at least one embodiment, the shared resource 2270 includes a shared cache memory and pixel operation logic.

[0191] FIG. 23 shows a processor 2300 according to at least one embodiment. In at least one embodiment, the processor 2300 may include, without limitation, logic circuitry for executing instructions. In at least one embodiment, the processor 2300 may execute instructions including, without limitation, x86 instructions, AMR instructions, special instructions for ASICs, and the like. In at least one embodiment, the processor 2310 may include registers for storing packed data, such as 64-bit wide MMX registers in a microprocessor enabled by MMX (trademark) technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers available in both integer and floating-point formats may operate on packed data elements with SIMD and Streaming SIMD Extension (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or more (collectively referred to as “SSEx” technology) may hold such packed data operands. In at least one embodiment, the processor 2310 may execute instructions for accelerating CUDA programs.

[0192] In at least one embodiment, the processor 2300 includes an in-order front end (“front end”) 2301 that fetches instructions to be executed and prepares instructions to be used later in the processor pipeline. In at least one embodiment, the front end 2301 may include several units. In at least one embodiment, an instruction prefetcher 2326 fetches instructions from memory and feeds the instructions to an instruction decoder 2328, and the instruction decoder 2328 decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2328 decodes the received instruction into one or more operations called “microinstructions” or “microoperations” (also called “microops” or “uops”) for execution. In at least one embodiment, the instruction decoder 2328 parses the instruction into an opcode, corresponding data, and control fields that can be used by the microarchitecture to perform an operation. In at least one embodiment, a trace cache 2330 may assemble the decoded uops into a program-order sequence or trace in a uop queue 2334 for execution. In at least one embodiment, when the trace cache 2330 encounters a complex instruction, a microcode ROM 2332 provides the uops necessary to complete the operation.

[0193] In at least one embodiment, there are instructions that can be converted into a single micro-op, and there are also instructions that require several micro-ops to complete the entire operation. In at least one embodiment, if five or more micro-ops are required to complete an instruction, the instruction decoder 2328 may access the microcode ROM 2332 to execute the instruction. In at least one embodiment, an instruction can be decoded into a small number of micro-ops for processing in the instruction decoder 2328. In at least one embodiment, an instruction can be stored in the microcode ROM 2332 if several micro-ops are required to achieve the operation. In at least one embodiment, the trace cache 2330 determines the correct micro-instruction pointer for reading the microcode sequence by referring to an entry point programmable logic array ("PLA") to complete one or more instructions from the microcode ROM 2332. In at least one embodiment, after the microcode ROM 2332 finishes sequencing the micro-ops for an instruction, the front end 2301 of the machine may resume fetching micro-ops from the trace cache 2330.

[0194] In at least one embodiment, an out-of-order execution engine ("out-of-order engine") 2303 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has several buffers for smoothing the flow of instructions and reordering them in order to optimize performance when instructions flow down the pipeline and are scheduled for execution. The out-of-order execution engine 2303 includes, without limitation, an allocator / register renamer 2340, a memory uop queue 2342, an integer / floating point uop queue 2344, a memory scheduler 2346, a high-speed scheduler 2302, a low-speed / general-purpose floating point scheduler ("low-speed / general-purpose FP (floating point) scheduler") 2304, and a simple floating point scheduler ("simple FP scheduler") 2306. In at least one embodiment, the high-speed scheduler 2302, the low-speed / general-purpose floating point scheduler 2304, and the simple floating point scheduler 2306 are collectively also referred to herein as "uop schedulers 2302, 2304, 2306". The allocator / register renamer 2340 allocates the machine buffers and resources required by each uop for execution. In at least one embodiment, the allocator / register renamer 2340 renames logical registers upon entry into the register file. In at least one embodiment, the allocator / register renamer 2340 also allocates an entry for each uop in one of two uop queues, namely the memory uop queue 2342 for memory operations and the integer / floating point uop queue 2344 for non-memory operations, prior to the memory scheduler 2346 and the uop schedulers 2302, 2304, 2306. In at least one embodiment, the uop schedulers 2302, 2304, 2306 determine when a uop is ready to execute based on the availability of its dependent input register operand sources and the availability of the execution resources required by the uop to complete its operations.In at least one embodiment, the high-speed scheduler 2302 of at least one embodiment may schedule every half of the main clock cycle, and the low-speed / general-purpose floating-point scheduler 2304 and the simple floating-point scheduler 2306 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2302, 2304, 2306 arbitrate dispatch ports to schedule uops for execution.

[0195] In at least one embodiment, the execution block 2311 includes, but is not limited to, the integer register file / bypass network 2308, the floating-point register file / bypass network (the "FP register file / bypass network") 2310, the address generation units ("AGUs": address generation unit) 2312 and 2314, the high-speed ALUs 2316 and 2318, the low-speed ALU 2320, the floating-point ALU ("FP") 2322, and the floating-point shift unit ("FP shift") 2324. In at least one embodiment, the integer register file / bypass network 2308 and the floating-point register file / bypass network 2310 are also referred to herein as the "register files 2308, 2310". In at least one embodiment, the AGUs 2312 and 2314, the high-speed ALUs 2316 and 2318, the low-speed ALU 2320, the floating-point ALU 2322, and the floating-point shift unit 2324 are also referred to herein as the "execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324". In at least one embodiment, the execution block may include any number and type of register files, bypass networks, address generation units, and execution units (including zero) in any combination.

[0196] In at least one embodiment, register files 2308, 2310 can be disposed between uop schedulers 2302, 2304, 2306 and execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324. In at least one embodiment, integer register file / bypass network 2308 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2310 performs floating-point operations. In at least one embodiment, each of register files 2308, 2310 can include, without limitation, a bypass network that can bypass or forward a just-completed result that has not yet been written to the register file to a new dependent uop. In at least one embodiment, register files 2308, 2310 can communicate data with each other. In at least one embodiment, integer register file / bypass network 2308 can include, without limitation, two separate register files, namely, one register file for lower 32-bit data and a second register file for upper 32-bit data. In at least one embodiment, since floating-point instructions typically have operands with a width of 64 to 128 bits, floating-point register file / bypass network 2310 can include, without limitation, entries with a width of 128 bits.

[0197] In at least one embodiment, execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324 may execute instructions. In at least one embodiment, register files 2308, 2310 store integer and floating-point data operand values that need to be executed by microinstructions. In at least one embodiment, processor 2300 may include any number and combination of execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324, without limitation. In at least one embodiment, floating-point ALU 2322 and floating-point shift unit 2324 may execute floating-point, MMX, SIMD, AVX, and SSE, or other operations. In at least one embodiment, floating-point ALU 2322 may include, without limitation, a 64-bit floating-point divider for executing division, square root, and remainder micro-ops. In at least one embodiment, instructions with floating-point values may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2316, 2318. In at least one embodiment, fast ALUs 2316, 2318 may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, slow ALU 2320 may include, without limitation, integer execution hardware for long latency type operations such as multipliers, shifts, flag logic, and branch processing, so most complex integer operations proceed to slow ALU 2320. In at least one embodiment, memory load / store operations may be performed by AGUs 2312, 2314. In at least one embodiment, fast ALU 2316, fast ALU 2318, and slow ALU 2320 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2316, fast ALU 2318, and slow ALU 2320 may be implemented to support various data bit sizes including 16, 32, 128, 256, etc. In at least one embodiment, floating-point ALU 2322 and floating-point shift unit 2324 may be implemented to support various operands with various bit widths.In at least one embodiment, the floating point ALU 2322 and the floating point shift unit 2324 can operate on 128-bit wide packed data operands combined with SIMD and multimedia instructions.

[0198] In at least one embodiment, the uop schedulers 2302, 2304, 2306 dispatch dependent operations before the parent load finishes execution. In at least one embodiment, since uops can be scheduled and executed speculatively in the processor 2300, the processor 2300 may also include logic for handling memory misses. In at least one embodiment, when a data load misses in the data cache, there may be ongoing dependent operations in the pipeline that have passed through a scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations may need to be replayed and independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0199] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, a register may be accessible from outside the processor (from the perspective of a programmer). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuit elements within a processor using any number of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, combinations of dedicated physical registers and physically registers dynamically allocated, and the like. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0200] FIG. 24 shows a processor 2400 according to at least one embodiment. In at least one embodiment, the processor 2400 includes, without limitation, one or more processor cores ("cores") 2402A-2402N, an integrated memory controller 2414, and an integrated graphics processor 2408. In at least one embodiment, the processor 2400 can include additional cores up to an additional processor core 2402N represented by the dashed box. In at least one embodiment, each of the processor cores 2402A-2402N includes one or more internal cache units 2404A-2404N. In at least one embodiment, each processor core also has access to one or more shared cache units 2406.

[0201] In at least one embodiment, the internal cache units 2404A - 2404N and the shared cache unit 2406 represent the cache memory hierarchy within the processor 2400. In at least one embodiment, the cache memory units 2404A - 2404N can include at least one level of instruction and data cache within each processor core, and one or more levels of shared intermediate level caches such as L2, L3, level 4 ("L4"), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In at least one embodiment, cache coherence logic maintains coherence among the various cache units 2406 and 2404A - 2404N.

[0202] In at least one embodiment, the processor 2400 can also include a set of one or more bus controller units 2416 and a system agent core 2410. In at least one embodiment, the one or more bus controller units 2416 manage a set of peripheral buses such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2410 provides management functionality for the various processor components. In at least one embodiment, the system agent core 2410 includes one or more integrated memory controllers 2414 for managing access to various external memory devices (not shown).

[0203] In at least one embodiment, one or more of the processor cores 2402A-2402N include support for simultaneous multithreading. In at least one embodiment, the system agent core 2410 includes components for coordinating and operating the processor cores 2402A-2402N during multithreaded processing. In at least one embodiment, the system agent core 2410 may additionally include a power control unit ("PCU"), and the PCU includes logic and components for adjusting the power state of one or more of the processor cores 2402A-2402N and the graphics processor 2408.

[0204] In at least one embodiment, the processor 2400 additionally includes a graphics processor 2408 for performing graphics processing operations. In at least one embodiment, the graphics processor 2408 is coupled to a system agent core 2410 that includes a shared cache unit 2406 and one or more integrated memory controllers 2414. In at least one embodiment, the system agent core 2410 also includes a display controller 2411 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2411 may also be a separate module coupled to the graphics processor 2408 via at least one interconnect, or may be incorporated within the graphics processor 2408.

[0205] In at least one embodiment, a ring-based interconnect unit 2412 is used to couple the internal components of the processor 2400. In at least one embodiment, alternative interconnect units such as point-to-point interconnects, switched interconnects, or other techniques may be used. In at least one embodiment, the graphics processor 2408 is coupled to the ring interconnect 2412 via an I / O link 2413.

[0206] In at least one embodiment, the I / O link 2413 represents at least one of a plurality of types of I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 2418, such as eDRAM modules, an on-package I / O interconnect. In at least one embodiment, each of the processor cores 2402A-2402N and the graphics processor 2408 uses the embedded memory module 2418 as a shared LLC.

[0207] In at least one embodiment, the processor cores 2402A-2402N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2402A-2402N are heterogeneous from the perspective of the ISA, where one or more of the processor cores 2402A-2402N execute a common instruction set and one or more other cores of the processor cores 2402A-2402N execute a subset of the common instruction set, or a different instruction set. In at least one embodiment, the processor cores 2402A-2402N are heterogeneous from the perspective of the microarchitecture, where one or more cores with a relatively high power consumption are combined with one or more cores with a lower power consumption. In at least one embodiment, the processor 2400 can be implemented on one or more chips or as a SoC integrated circuit.

[0208] FIG. 25 shows a graphics processor core 2500 according to at least one of the embodiments described. In at least one embodiment, the graphics processor core 2500 is included within a graphics core array. In at least one embodiment, the graphics processor core 2500, sometimes referred to as a core slice, can be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2500 is an example of one graphics core slice, and the graphics processors described herein can include multiple graphics core slices based on a target power and performance envelope. In at least one embodiment, each graphics core 2500 can include a fixed function block 2530 coupled to a plurality of sub - cores 2501A - 2501F, also referred to as sub - slices, that include modular blocks of general - purpose and fixed - function logic.

[0209] In at least one embodiment, the fixed function block 2530 can include a geometry / fixed - function pipeline 2536 that is shared by all sub - cores in the graphics processor 2500, for example, in a lower performance and / or lower power graphics processor implementation. In at least one embodiment, the geometry / fixed - function pipeline 2536 includes a 3D fixed - function pipeline, a video front - end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0210] In at least one embodiment, the fixed function block 2530 also includes a graphics SoC interface 2537, a graphics microcontroller 2538, and a media pipeline 2539. The graphics SoC interface 2537 provides an interface between the graphics core 2500 and other processor cores within the SoC integrated circuit. In at least one embodiment, the graphics microcontroller 2538 is a programmable sub-processor that can be configured to manage various functions of the graphics processor 2500, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 2539 includes logic for facilitating the decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2539 implements media operations via requests to compute logic or sampling logic within sub-cores 2501 through 2501F.

[0211] In at least one embodiment, the SoC interface 2537 enables the graphics core 2500 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, and the other components within the SoC include memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or on-package DRAM. In at least one embodiment, the SoC interface 2537 can also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, enable the use of global memory atomic that can be shared between the graphics core 2500 and the CPU within the SoC, and / or implement it. In at least one embodiment, the SoC interface 2537 can also implement power management control for the graphics core 2500 and enable an interface between the clock domain of the graphics core 2500 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2537 enables receipt of a command buffer from a command streamer and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, the commands and instructions can be dispatched to the media pipeline 2539 when a media operation is to be performed, or to the geometry and fixed-function pipelines (e.g., geometry and fixed-function pipeline 2536, geometry and fixed-function pipeline 2514) when a graphics processing operation is to be performed.

[0212] In at least one embodiment, the graphics microcontroller 2538 can be configured to perform various scheduling and management tasks for the graphics core 2500. In at least one embodiment, the graphics microcontroller 2538 can perform graphics and / or calculate workload scheduling for the execution unit (EU) arrays 2502A - 2502F, 2504A - 2504F within the sub - cores 2501A - 2501F and various graphics parallel engines. In at least one embodiment, the host software running on the CPU core of the SoC including the graphics core 2500 can submit a workload to one of a plurality of graphics processor doorbells, and this doorbell calls a scheduling operation for an appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should run next, submitting the workload to a command streamer, preempting an existing workload running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In at least one embodiment, the graphics microcontroller 2538 can also promote a low - power or idle state for the graphics core 2500 and provide the graphics core 2500 with the ability to save and restore registers within the graphics core 2500 across low - power state transitions, independent of the operating system and / or the graphics driver software on the system.

[0213] In at least one embodiment, the graphics core 2500 can have up to N modular sub-cores, more or less than the six sub-cores 2501A - 2501F shown. For each set of N sub-cores, in at least one embodiment, the graphics core 2500 can also include shared function logic 2510, shared and / or cache memory 2512, geometry / fixed function pipeline 2514, and additional fixed function logic 2516 for accelerating various graphics and calculating processing operations. In at least one embodiment, the shared function logic 2510 can include logic units (e.g., samplers, math, and / or inter-thread communication logic) that can be shared by each of the N sub-cores within the graphics core 2500. The shared and / or cache memory 2512 can be an LLC for the N sub-cores 2501A - 2501F within the graphics core 2500 and can also act as shared memory accessible by multiple sub-cores. In at least one embodiment, the geometry / fixed function pipeline 2514 can be included instead of the geometry / fixed function pipeline 2536 within the fixed function block 2530 and can include the same or similar logic units.

[0214] In at least one embodiment, the graphics core 2500 includes additional fixed function logic 2516 which can include various fixed function acceleration logic for use by the graphics core 2500. In at least one embodiment, the additional fixed function logic 2516 includes an additional geometry pipeline for use in position only shading. In position only shading, there are at least two geometry pipelines, namely the full geometry pipeline within the geometry / fixed function pipelines 2516, 2536, and a cull pipeline, which can be an additional geometry pipeline included within the additional fixed function logic 2516. In at least one embodiment, the cull pipeline is a scaled-down version of the full geometry pipeline. In at least one embodiment, the full pipeline and the cull pipeline can execute different instances of an application, and each instance has a separate context. In at least one embodiment, position only shading can hide long cull runs of discarded triangles, which allows shading to complete faster in some instances. For example, in at least one embodiment, the cull pipeline fetches and shades the vertex position attributes without performing rasterization and rendering of pixels to the frame buffer, so the cull pipeline logic within the additional fixed function logic 2516 can execute the position shader in parallel with the main application and generate critical results faster than the full pipeline overall. In at least one embodiment, the cull pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether those triangles are culled. In at least one embodiment, the full pipeline (which may be called the replay pipeline in this instance) can consume the visibility information, skip the culled triangles, and shade only the visible triangles, which are ultimately passed to the rasterization phase.

[0215] In at least one embodiment, the additional fixed function logic 2516 can also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, to accelerate CUDA programs.

[0216] In at least one embodiment, each of the graphics sub-cores 2501A - 2501F includes a set of execution resources, and the set of execution resources can be used to perform graphics operations, media operations, and compute operations in response to requests by a graphics pipeline, a media pipeline, or a shader program. In at least one embodiment, the graphics sub-cores 2501A - 2501F include a plurality of EU arrays 2502A - 2502F, 2504A - 2504F, thread dispatch and inter-thread communication ("TD / IC") logic 2503A - 2503F, 3D (e.g., texture) samplers 2505A - 2505F, media samplers 2506A - 2506F, shader processors 2507A - 2507F, and shared local memory ("SLM") 2508A - 2508F. The EU arrays 2502A - 2502F, 2504A - 2504F each include a plurality of execution units, and the plurality of execution units are GPGPUs capable of performing floating-point and integer / fixed-point logical operations in the service of graphics operations, media operations, or compute operations including graphics, media, or compute shader programs. In at least one embodiment, the TD / IC logic 2503A - 2503F performs local thread dispatch and thread control operations for the execution units within the sub-core and facilitates communication between threads executing on the execution units of the sub-core. In at least one embodiment, the 3D samplers 2505A - 2505F can read texture or other 3D graphics-related data into memory. In at least one embodiment, the 3D sampler can read texture data in different ways based on the configured sample state and texture format associated with a given texture. In at least one embodiment, the media samplers 2506A - 2506F can perform similar read operations based on the types and formats associated with media data.In at least one embodiment, each of the graphics sub-cores 2501A - 2501F can alternatively include unified 3D and media samplers. In at least one embodiment, threads executing on execution units within each of the sub-cores 2501A - 2501F can utilize the shared local memories 2508A - 2508F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

[0217] FIG. 26 shows a parallel processing unit (“PPU”) 2600 according to at least one embodiment. In at least one embodiment, the PPU 2600 is composed of machine-readable code that, when executed by the PPU 2600, causes the PPU 2600 to implement some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2600 is a multi-threaded processor, and the multi-threaded processor is implemented on one or more integrated circuit devices and utilizes multi-threading as a latency hiding technique designed to process computer-readable instructions (also simply referred to as instructions) in parallel on multiple threads. In at least one embodiment, a thread refers to an instance of a set of instructions configured to be executed by the PPU 2600. In at least one embodiment, the PPU 2600 is a GPU configured to implement a graphics rendering pipeline for processing 3D graphics data to generate 2D image data for display on a display device such as an LCD device. In at least one embodiment, the PPU 2600 is utilized to perform calculations such as linear algebra operations and machine learning operations. FIG. 26 shows an exemplary parallel processor for illustrative purposes only and should be interpreted as a non-limiting example of a processor architecture that can be implemented in at least one embodiment.

[0218] In at least one embodiment, one or more PPU2600s are configured to accelerate high performance computing (HPC), data centers, and machine learning applications. In at least one embodiment, one or more PPU2600s are configured to accelerate CUDA programs. In at least one embodiment, the PPU2600 includes, without limitation, an I / O unit 2606, a front-end unit 2610, a scheduler unit 2612, a work distribution unit 2614, a hub 2616, a crossbar (X bar) 2620, one or more general processing clusters (GPCs) 2618, and one or more partition units (memory partition units) 2622. In at least one embodiment, the PPU2600 is connected to a host processor or another PPU2600 via one or more high-speed GPU interconnects (GPU interconnects) 2608. In at least one embodiment, the PPU2600 is connected to a host processor or other peripheral devices via a system bus or interconnect 2602. In at least one embodiment, the PPU2600 is connected to local memory with one or more memory devices (memory). In at least one embodiment, the memory device 2604 includes, without limitation, one or more dynamic random access memory (DRAM) devices. In at least one embodiment, one or more DRAM devices are configured as, and / or configurable as, a high bandwidth memory (HBM) subsystem with multiple DRAM dies stacked within each device.

[0219] In at least one embodiment, the high-speed GPU interconnect 2608 can refer to a wire-based multi-lane communication link, and the wire-based multi-lane communication link is used by the system to scale and include one or more PPU2600s in combination with one or more CPUs, and supports cache coherence and CPU mastering between the PPU2600 and the CPU. In at least one embodiment, data and / or commands are transmitted to / from other units of the PPU2600, such as one or more copy engines, video encoders, video decoders, power management units, and other components that may not be explicitly shown in FIG. 26, through the high-speed GPU interconnect 2608 and through the hub 2616.

[0220] In at least one embodiment, the I / O unit 2606 is configured to communicate (e.g., commands, data) with a host processor (not shown in FIG. 26) via the system bus 2602. In at least one embodiment, the I / O unit 2606 communicates with the host processor directly via the system bus 2602 or through one or more intermediate devices such as a memory bridge. In at least one embodiment, the I / O unit 2606 can communicate with one or more other processors such as one or more of the PPU2600s via the system bus 2602. In at least one embodiment, the I / O unit 2606 implements a PCIe interface for communication via the PCIe bus. In at least one embodiment, the I / O unit 2606 implements an interface for communicating with external devices.

[0221] In at least one embodiment, the I / O unit 2606 decodes packets received via the system bus 2602. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 2600 to perform various operations. In at least one embodiment, the I / O unit 2606 transmits the decoded commands to various other units of the PPU 2600 specified by the commands. In at least one embodiment, the commands are transmitted to the front-end unit 2610 and / or to other units of the PPU 2600 such as the hub 2616 or one or more copy engines, video encoders, video decoders, power management units (not explicitly shown in FIG. 26). In at least one embodiment, the I / O unit 2606 is configured to route communications between and among various logical units of the PPU 2600.

[0222] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides the workload to the PPU 2600 for processing. In at least one embodiment, the workload includes instructions and the data to be processed by those instructions. In at least one embodiment, the buffer is a region in memory that is accessible (e.g., readable / writable) by both the host processor and the PPU 2600, and the host interface unit may be configured to access the buffer in the system memory connected to the system bus 2602 via memory requests transmitted via the system bus 2602 by the I / O unit 2606. In at least one embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU 2600, whereby the front-end unit 2610 receives pointers to one or more command streams, manages the one or more command streams, reads commands from the command streams, and forwards the commands to various units of the PPU 2600.

[0223] In at least one embodiment, the front-end unit 2610 is coupled to a scheduler unit 2612 that configures various GPCs 2618 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2612 is configured to track state information related to the various tasks managed by the scheduler unit 2612, the state information may indicate, for example, which of the GPCs 2618 a task is assigned to, whether the task is active or inactive, the priority level associated with the task, and the like. In at least one embodiment, the scheduler unit 2612 manages the execution of multiple tasks on one or more of the GPCs 2618.

[0224] In at least one embodiment, the scheduler unit 2612 is coupled to a work distribution unit 2614 configured to dispatch tasks for execution on the GPCs 2618. In at least one embodiment, the work distribution unit 2614 tracks the number of scheduled tasks received from the scheduler unit 2612, and the work distribution unit 2614 manages a pending task pool and an active task pool for each of the GPCs 2618. In at least one embodiment, the pending task pool comprises a number of slots (e.g., 32 slots) containing tasks assigned to be processed by a particular GPC 2618, and the active task pool may comprise a number of slots (e.g., 4 slots) for tasks being actively processed by the GPC 2618, such that when one of the GPCs 2618 completes execution of a task, that task is removed from the active task pool for the GPC 2618 and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC 2618. In at least one embodiment, when an active task is idle on the GPC 2618, such as while waiting for data dependencies to be resolved, the active task is removed from the GPC 2618 and returned to the pending task pool, during which time another task in the pending task pool is selected and scheduled for execution on the GPC 2618.

[0225] In at least one embodiment, the work distribution unit 2614 communicates with one or more GPCs 2618 via an X-bar 2620. In at least one embodiment, the X-bar 2620 is an interconnect network that couples many of the units of the PPU 2600 to other units of the PPU 2600 and may be configured to couple the work distribution unit 2614 to a particular GPC 2618. In at least one embodiment, one or more other units of the PPU 2600 may also be connected to the X-bar 2620 via a hub 2616.

[0226] In at least one embodiment, the task is managed by a scheduler unit 2612 and dispatched to one of the GPCs 2618 by a work distribution unit 2614. The GPC 2618 is configured to process the task and generate a result. In at least one embodiment, the result can be consumed by other tasks within the GPC 2618, routed to a different GPC 2618 via the X-bar 2620, or stored in the memory 2604. In at least one embodiment, the result can be written to the memory 2604 via a partition unit 2622, which implements a memory interface for reading and writing data to / from the memory 2604. In at least one embodiment, the result can be sent to another PPU 2604 or CPU via the high-speed GPU interconnect 2608. In at least one embodiment, the PPU 2600 includes U partition units 2622 equal in number to the number of separate individual memory devices 2604 coupled to the PPU 2600, among other things.

[0227] In at least one embodiment, the host processor executes a driver kernel, and the driver kernel implements an application programming interface ("API") that enables one or more applications running on the host processor to schedule operations for execution on the PPU 2600. In at least one embodiment, multiple compute applications are executed simultaneously by the PPU 2600, and the PPU 2600 provides isolation, quality of service ("QoS"), and an independent address space for the multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 2600, and the driver kernel outputs the tasks to one or more streams being processed by the PPU 2600. In at least one embodiment, each task comprises one or more groups of related threads, sometimes referred to as warps. In at least one embodiment, a warp comprises multiple related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, cooperating threads can refer to multiple threads that include instructions for performing a task and exchange data through shared memory.

[0228] FIG. 27 shows a GPC2700 according to at least one embodiment. In at least one embodiment, the GPC2700 is the GPC2618 of FIG. 26. In at least one embodiment, each GPC2700 includes, without limitation, several hardware units for processing tasks, and each GPC2700 includes, without limitation, a pipeline manager 2702, a pre-raster operation unit (「PROP」) 2704, a raster engine 2708, a work distribution crossbar (「WDX」) 2716, an MMU 2718, one or more data processing clusters (「DPC」), and any suitable combination of parts.

[0229] In at least one embodiment, the operation of the GPC2700 is controlled by a pipeline manager 2702. In at least one embodiment, the pipeline manager 2702 manages the configuration of one or more DPCs 2706 for processing tasks assigned to the GPC2700. In at least one embodiment, the pipeline manager 2702 configures at least one of the one or more DPCs 2706 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 2706 is configured to execute a vertex shader program on a programmable streaming multiprocessor ("SM") 2714. In at least one embodiment, the pipeline manager 2702 is configured to route packets received from a work distribution unit to appropriate logical units within the GPC2700. In at least one embodiment, some packets may be routed to fixed function hardware units in the PROP2704 and / or the raster engine 2708, and other packets may be routed to the DPC 2706 for processing by the primitive engine 2712 or the SM 2714. In at least one embodiment, the pipeline manager 2702 configures at least one of the DPCs 2706 to implement a computing pipeline. In at least one embodiment, the pipeline manager 2702 configures at least one of the DPCs 2706 to execute at least a portion of a CUDA program.

[0230] In at least one embodiment, the PROP unit 2704 is configured to route data generated by the raster engine 2708 and the DPC 2706 to a raster operation (「ROP」) unit in a partition unit, such as the memory partition unit 2622 described in more detail above in conjunction with FIG. 26. In at least one embodiment, the PROP unit 2704 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, the raster engine 2708 includes several fixed function hardware units configured to perform various raster operations, including but not limited to, in at least one embodiment, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile merger engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates a plane equation associated with the geometric primitive defined by the vertices, and the plane equation is transmitted to the coarse raster engine to generate coverage information for the primitive (e.g., x, y coverage masks for tiles), and the output of the coarse raster engine is transmitted to the culling engine, where fragments associated with primitives that fail the z-test are culled and transmitted to the clipping engine, where fragments outside the frustum are clipped. In at least one embodiment, fragments that pass clipping and culling are passed to the fine raster engine to generate attributes for the pixel fragments based on the plane equation generated by the setup engine. In at least one embodiment, the output of the raster engine 2708 includes fragments to be processed by any suitable entity, such as by a fragment shader implemented within the DPC 2706.

[0231] In at least one embodiment, each DPC2706 included in GPC2700 includes, without limitation, an M pipe controller (“MPC”: M-Pipe Controller) 2710, a primitive engine 2712, one or more SMs 2714, and any suitable combination thereof. In at least one embodiment, the MPC2710 controls the operation of the DPC2706 to route the packets received from the pipeline manager 2702 to the appropriate units in the DPC2706. In at least one embodiment, packets related to vertices are routed to a primitive engine 2712 configured to fetch vertex attributes related to the vertices from memory, whereas, in contrast, packets related to shader programs can be sent to the SM2714.

[0232] In at least one embodiment, SM2714 includes a programmable streaming processor configured to process tasks represented by, but not limited to, a number of threads. In at least one embodiment, SM2714 is multi-threaded and configured to execute multiple threads (e.g., 32 threads) from a particular group of threads simultaneously, implements a SIMD architecture, and each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same set of instructions. In at least one embodiment, all threads in a group of threads execute the same instruction. In at least one embodiment, SM2714 implements a SIMT architecture and each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but individual threads in a group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp to enable simultaneous processing between warps and serial execution within a warp when threads within the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread to enable equal simultaneous processing between all threads, within and between warps. In at least one embodiment, an execution state is maintained for each individual thread and threads executing the same instruction can be converged and executed in parallel for better efficiency. At least one embodiment of SM2714 is described in further detail in conjunction with FIG. 28.

[0233] In at least one embodiment, the MMU 2718 provides an interface between the GPC 2700 and a memory partition unit (e.g., partition unit 2622 of FIG. 26), and the MMU 2718 provides virtual address to physical address translation, memory protection, and mediation of memory requests. In at least one embodiment, the MMU 2718 provides one or more translation lookaside buffers (TLBs) for performing translation from a virtual address to a physical address in memory.

[0234] FIG. 28 shows a streaming multiprocessor ( "SM") 2800 according to at least one embodiment. In at least one embodiment, SM2800 is the SM2714 of FIG. 27. In at least one embodiment, SM2800 includes, without limitation, an instruction cache 2802, one or more scheduler units 2804, a register file 2808, one or more processing cores ( "cores") 2810, one or more special function units ( "SFU": special function unit) 2812, one or more LSUs 2814, an interconnect network 2816, a shared memory / L1 cache 2818, and any suitable combination thereof. In at least one embodiment, the work distribution unit dispatches tasks for execution on the GPC of the parallel processing unit (PPU), and each task is assigned to a specific data processing cluster (DPC) within the GPC. When the task is related to a shader program, the task is assigned to one of the SM2800s. In at least one embodiment, the scheduler unit 2804 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to the SM2800. In at least one embodiment, the scheduler unit 2804 schedules thread blocks for execution as warps of parallel threads, and each thread block is assigned at least one warp. In at least one embodiment, each warp executes threads. In at least one embodiment, the scheduler unit 2804 manages multiple different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from multiple different cooperating groups to various functional units (e.g., processing cores 2810, SFU 2812, and LSU 2814) during each clock cycle.

[0235] In at least one embodiment, a "coordination group" may refer to a programming model for organizing a group of communicating threads, where the programming model enables a developer to express the granularity at which threads are communicating, enabling a richer and more efficient expression of parallel decomposition. In at least one embodiment, a coordination startup API supports synchronization between thread blocks for the execution of parallel algorithms. In at least one embodiment, APIs of conventional programming models provide a single simple construct for synchronizing coordinated threads, namely a barrier (e.g., the syncthreads() function) across all threads of a thread block. However, in at least one embodiment, a programmer can define a group of threads at a granularity smaller than a thread block, synchronize within the defined group, and enable higher performance, design flexibility, and software reuse in the form of a collective functional interface across the entire group. In at least one embodiment, a coordination group enables a programmer to explicitly define a group of threads at sub-block granularity and multi-block granularity and perform collective operations such as synchronization on the threads within the coordination group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, thereby enabling libraries and utility functions to synchronize safely within their local context without having to make assumptions about convergence. In at least one embodiment, coordination group primitives enable new patterns of coordinated parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across the grid of thread blocks.

[0236] In at least one embodiment, the dispatch unit 2806 is configured to send instructions to one or more of the functional units, and the scheduler unit 2804 includes two dispatch units 2806 that, without limitation, enable two different instructions from the same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit 2804 includes a single dispatch unit 2806 or additional dispatch units 2806.

[0237] In at least one embodiment, each SM2800 includes, in at least one embodiment, a register file 2808 that provides a set of registers to the functional units of the SM2800, without limitation. In at least one embodiment, the register file 2808 is divided among each of the functional units such that each functional unit is allocated a dedicated portion of the register file 2808. In at least one embodiment, the register file 2808 is divided among different warps being executed by the SM2800, and the register file 2808 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM2800 includes, without limitation, a plurality of L processing cores 2810. In at least one embodiment, the SM2800 includes, without limitation, a large number (e.g., more than 128) of individual processing cores 2810. In at least one embodiment, each processing core 2810 includes, without limitation, fully pipelined, single-precision, double-precision, and / or mixed-precision processing units, which include, without limitation, floating-point arithmetic logic units and integer arithmetic logic units. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 2810 includes, without limitation, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

[0238] In at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 2810. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolutional operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D = A×B + C, where A, B, C, and D are 4×4 matrices.

[0239] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating point matrices, and the sum matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, the tensor core operates on 16-bit floating point input data with 32-bit floating point sums. In at least one embodiment, the 16-bit floating point multiplication uses 64 operations, resulting in a full-precision product, which is then added using 32-bit floating point addition with other intermediate products for a 4×4×4 matrix multiplication. In at least one embodiment, the tensor core is used to perform much larger two-dimensional or even higher-dimensional matrix operations built from these small elements. In at least one embodiment, an API, such as the CUDA-C++ API, exposes special matrix load operations, matrix multiply and accumulate operations, and matrix store operations to efficiently use the tensor core from a CUDA-C++ program. In at least one embodiment, at the CUDA level, the warp-level interface assumes a 16×16 size matrix spanning all 32 threads of a warp.

[0240] In at least one embodiment, each SM2800 includes M SFU2812s that perform special functions (e.g., attribute evaluation, reciprocal square root, etc.), without limitation. In at least one embodiment, the SFU2812s include, without limitation, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFU2812s include, without limitation, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load a texture map (e.g., a 2D array of texels) from memory and a sample texture map and create sampled texture values for use in a shader program executed by the SM2800. In at least one embodiment, the texture map is stored in the shared memory / L1 cache 2818. In at least one embodiment, the texture unit implements texture operations such as filtering operations using mip maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM2800 includes, without limitation, two texture units.

[0241] In at least one embodiment, each SM2800 includes N LSU2814s that implement load and store operations between the shared memory / L1 cache 2818 and the register file 2808, without limitation. In at least one embodiment, each SM2800 includes, without limitation, an interconnect network 2816 that connects each of the functional units to the register file 2808 and connects the LSU2814 to the register file 2808 and the shared memory / L1 cache 2818. In at least one embodiment, the interconnect network 2816 is a crossbar that can be configured to connect any of the functional units to any of the registers in the register file 2808 and connect the LSU2814 to the register file 2808 and a memory location in the shared memory / L1 cache 2818.

[0242] In at least one embodiment, the shared memory / L1 cache 2818 is an array of on-chip memory that enables data storage and communication between the SM 2800 and the primitive engine and between threads within the SM 2800. In at least one embodiment, the shared memory / L1 cache 2818 has a storage capacity of, but not limited to, 128 KB and is in the path from the SM 2800 to the partition unit. In at least one embodiment, the shared memory / L1 cache 2818 is used to cache reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 2818, the L2 cache, and the memory are auxiliary stores.

[0243] In at least one embodiment, combining a data cache and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity can be used as a cache by a program that does not use shared memory, such as when the shared memory is configured to use half of the capacity and texture and load / store operations can use the remaining capacity. In at least one embodiment, the integration within the shared memory / L1 cache 2818 enables the shared memory / L1 cache 2818 to provide high-bandwidth and low-latency access to frequently reused data while functioning as a high-throughput pipe for streaming data. In at least one embodiment, when configured for general-purpose parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed to create a much simpler programming model. In at least one embodiment and in a general-purpose parallel computing configuration, the work distribution unit directly assigns and distributes blocks of threads to the DPC. In at least one embodiment, the threads within a block execute the same program using unique thread IDs in the computation to ensure that each thread generates a unique result, execute the program using the SM2800, perform the computation, communicate between threads using the shared memory / L1 cache 2818, and read and write global memory through the shared memory / L1 cache 2818 and the memory partition unit using the LSU2814. In at least one embodiment, when configured for general-purpose parallel computing, the SM2800 writes commands that can be used by the scheduler unit 2804 to launch new work on the DPC.

[0244] In at least one embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smart phone (e.g., a wireless handheld device), a PDA, a digital camera, a vehicle, a head-mounted display, a handheld electronic device, etc. In at least one embodiment, the PPU is embodied on a single semiconductor substrate. In at least one embodiment, the PPU is included in a SoC together with one or more other devices such as an additional PPU, a memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC").

[0245] In at least one embodiment, the PPU may be included on a graphics card that includes one or more memory devices. In at least one embodiment, the graphics card may be configured to interface with a PCIe slot on the motherboard of a desktop computer. In at least one embodiment, the PPU may be an integrated GPU ("iGPU") included in the chipset of the motherboard.

[0246] Software constructs for general computing The following figures describe exemplary software constructs for implementing at least one embodiment, without limitation.

[0247] In at least one embodiment, the techniques described above may be implemented on a computing service such as software stack 2900 or programming platform 3304, as described below. In at least one embodiment, an application running on a computer system may be divided into dependent threads that run in parallel on multiple processors. In at least one embodiment, the processor may include any processor type described below, including GPU 3792. In at least one embodiment, one or more circuits cause two or more dependent threads to be executed in parallel using two or more distinct multi-threaded processor cores. In at least one embodiment, the processor core may be a core in a multi-core CPU, an SMP core in a GPU, or other circuitry capable of executing storable instructions. In at least one embodiment, one or more circuits cause a first group of threads to be organized into two or more sub-groups of threads to be executed in parallel using two or more processor cores. In at least one embodiment, the group of threads may be a cooperating group that runs in parallel. In at least one embodiment, the cooperating group includes a plurality of kernel threads arranged in a warp on a GPU. In at least one embodiment, synchronization operations between threads may be enabled by the use of a barrier. In at least one embodiment, one or more circuits perform a memory barrier operation to cause access to memory by multiple groups of threads to occur in the order indicated by the memory barrier operation. In at least one embodiment, the barrier operation may be an atomic operation such as a bitwise logical operation (e.g., AND, OR, XOR), or a mathematical operation such as an atomic addition or subtraction.

[0248] Figure 29 shows a software stack of a programming platform according to at least one embodiment. In at least one embodiment, the programming platform is a platform for leveraging hardware on a computing system to accelerate compute tasks. In at least one embodiment, the programming platform may be accessible to software developers through libraries, compiler directives, and / or extensions to programming languages. In at least one embodiment, the programming platform may be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL™ is developed by the Khronos group), SYCL, or Intel One API.

[0249] In at least one embodiment, the software stack 2900 of the programming platform provides an execution environment for an application 2901. In at least one embodiment, the application 2901 may include any computer software that can be launched on the software stack 2900. In at least one embodiment, the application 2901 may include, but is not limited to, artificial intelligence (“AI”) / machine learning (“ML”) applications, high-performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”), or data center workloads.

[0250] In at least one embodiment, application 2901 and software stack 2900 operate on hardware 2907. In at least one embodiment, hardware 2907 can include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of compute devices that support a programming platform. In at least one embodiment, such as in the case of CUDA, the software stack 2900 is vendor-specific and may be compatible only with devices from a particular vendor or vendors. In at least one embodiment, such as in the case of OpenCL, the software stack 2900 can be used with devices from different vendors. In at least one embodiment, hardware 2907 includes a host connected to another device that can be accessed to perform compute tasks via application programming interface (API) calls. In at least one embodiment, in contrast to the host within hardware 2907, which can include, but is not limited to, a CPU (although it can also include a compute device) and its memory, the devices within hardware 2907 can include, but are not limited to, GPUs, FPGAs, AI engines, or other compute devices (although it can also include a CPU) and their memory.

[0251] In at least one embodiment, the software stack 2900 of the programming platform includes, but is not limited to, several libraries 2903, a runtime 2905, and a device kernel driver 2906. In at least one embodiment, each of the libraries 2903 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the libraries 2903 may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 2903 include functions optimized for execution on one or more types of devices. In at least one embodiment, the libraries 2903 may include functions for performing mathematics, deep learning, and / or other types of operations on the device. In at least one embodiment, the libraries 2903 are related to corresponding APIs 2902 that may include one or more APIs that expose the functions implemented in the libraries 2903.

[0252] In at least one embodiment, the application 2901 is written as source code that is compiled into executable code as will be described in more detail below in conjunction with FIGS. 34-36. In at least one embodiment, the executable code of the application 2901 can operate, at least in part, on the execution environment provided by the software stack 2900. In at least one embodiment, during the execution of the application 2901, code that needs to operate on the device, as opposed to the host, can be reached. In at least one embodiment, in such a case, the runtime 2905 can be called to load and start the essential code on the device. In at least one embodiment, the runtime 2905 may include any technically realizable runtime system that is capable of supporting the execution of the application S01.

[0253] In at least one embodiment, runtime 2905 is implemented as one or more runtime libraries associated with the corresponding API(s), shown as (one or more) APIs 2904. In at least one embodiment, one or more of such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization. In at least one embodiment, the memory management function may include, but is not limited to, functions for allocating, deallocating, copying device memory, and transferring data between host memory and device memory. In at least one embodiment, the execution control function may include, but is not limited to, functions for launching a function (which may be called a "kernel" when the function is a global function callable from the host) on the device and setting attribute values in a buffer maintained by a runtime library for a given function to be executed on the device.

[0254] In at least one embodiment, the runtime library and the corresponding API(s) 2904 may be implemented in any technically feasible manner. In at least one embodiment, one (or any number) of the APIs may expose a low-level set of functions for fine-grained control of the device, while another (or any number) of the APIs may expose a higher-level set of such functions. In at least one embodiment, the high-level runtime API may be built on top of the low-level API. In at least one embodiment, one or more of the runtime APIs may be language-specific APIs layered on top of language-independent runtime APIs.

[0255] In at least one embodiment, the device kernel driver 2906 is configured to facilitate communication with underlying devices. In at least one embodiment, the device kernel driver 2906 may provide low-level functionality on which an API such as the (one or more) APIs 2904 and / or other software may rely. In at least one embodiment, the device kernel driver 2906 may be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, in the case of CUDA, the device kernel driver 2906 may compile hardware-independent parallel thread execution ("PTX") IR code into binary code for a particular target device at runtime (with caching of the compiled binary code), which may also be referred to as "finalizing" the code. In at least one embodiment, doing so may allow the finalized code to operate on the target device, which may not exist when the source code is first compiled into PTX code. Alternatively, in at least one embodiment, the device source code may be compiled into binary code offline without the device kernel driver 2906 needing to compile the IR code at runtime.

[0256] FIG. 30 shows a CUDA implementation of the software stack 2900 of FIG. 29 according to at least one embodiment. In at least one embodiment, a CUDA software stack 3000 on which an application 3001 can be launched includes a CUDA library 3003, a CUDA runtime 3005, a CUDA driver 3007, and a device kernel driver 3008. In at least one embodiment, the CUDA software stack 3000 executes on hardware 3009, which may include a GPU, and the GPU supports CUDA and is developed by NVIDIA Corporation of Santa Clara, California.

[0257] In at least one embodiment, application 3001, CUDA runtime 3005, and device kernel driver 3008 may each implement functionality similar to application 2901, runtime 2905, and device kernel driver 2906, respectively, as described above in conjunction with FIG. 29. In at least one embodiment, CUDA driver 3007 includes a library (libcuda.so) that implements CUDA driver API 3006. In at least one embodiment, similar to CUDA runtime API 3004 implemented by CUDA runtime library (cudart), CUDA driver API 3006 may expose functions for, but not limited to, memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, CUDA driver API 3006 differs from CUDA runtime API 3004 in that CUDA runtime API 3004 simplifies device code management by providing implicit initialization, context management (similar to a process), and module management (similar to a dynamically loaded library). In at least one embodiment, in contrast to high-level CUDA runtime API 3004, CUDA driver API 3006 is a low-level API that provides more fine-grained control of the device, particularly with respect to context and module loading. In at least one embodiment, CUDA driver API 3006 may expose functions for context management not exposed by CUDA runtime API 3004. In at least one embodiment, CUDA driver API 3006 is also language independent and supports OpenCL, for example, in addition to CUDA runtime API 3004. Further, in at least one embodiment, a development library including CUDA runtime 3005 may be considered separate from driver components including user-mode CUDA driver 3007 and kernel-mode device driver 3008 (sometimes referred to as a "display" driver).

[0258] In at least one embodiment, the CUDA library 3003 may include, without limitation, a math library, a deep learning library, a parallel algorithm library, and / or a signal / image / video processing library, which may be utilized by a parallel computing application such as the application 3001. In at least one embodiment, the CUDA library 3003 may include, among other things, the cuBLAS library, which is an implementation of basic linear algebra subprograms (BLAS) for performing linear algebra operations, the cuFFT library for calculating the fast Fourier transform (FFT), and the cuRAND library for generating random numbers, etc., a math library. In at least one embodiment, the CUDA library 3003 may include, among other things, the cuDNN library of primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference, etc., a deep learning library.

[0259] FIG. 31 shows an ROCm implementation of the software stack 2900 of FIG. 29 according to at least one embodiment. In at least one embodiment, the ROCm software stack 3100 on which the application 3101 may be launched includes a language runtime 3103, a system runtime 3105, a thunk 3107, and an ROCm kernel driver 3108. In at least one embodiment, the ROCm software stack 3100 runs on the hardware 3109, which may include a GPU that supports ROCm and is developed by AMD Corporation of Santa Clara, California.

[0260] In at least one embodiment, application 3101 may implement functionality similar to application 2901 described above in conjunction with FIG. 29. In at least one embodiment, further, language runtime 3103 and system runtime 3105 may implement functionality similar to runtime 2905 described above in conjunction with FIG. 29. In at least one embodiment, language runtime 3103 and system runtime 3105 are different in that system runtime 3105 implements the ROCr system runtime API 3104 and utilizes a heterogeneous system architecture (HSA) runtime API, which is a language-independent runtime. In at least one embodiment, the HSA runtime API exposes an interface for accessing and interacting with an AMD GPU, which includes functions for, among other things, memory management, execution control via designed dispatch of kernels, error handling, system and agent information, and runtime initialization and shutdown, and is a thin user-mode API. In contrast to system runtime 3105, in at least one embodiment, language runtime 3103 is an implementation of a language-specific runtime API 3102 layered on top of the ROCr system runtime API 3104. In at least one embodiment, the language runtime API may include, but is not limited to, among other things, a heterogeneous compute interface for portability (HIP) language runtime API, a heterogeneous compute compiler (HCC) language runtime API, or an OpenCL API. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes functions similar to those of the CUDA runtime API 3004 described above in conjunction with FIG. 30, such as functions for memory management, execution control, device management, error handling, and synchronization.

[0261] In at least one embodiment, the ROCt 3107 is an interface 3106 that can be used to interact with the underlying ROCm driver 3108. In at least one embodiment, the ROCm driver 3108 is a ROCk driver that is a combination of an AMDGPU driver and an HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for a GPU developed by AMD that implements functionality similar to the device kernel driver 2906 described above in conjunction with FIG. 29. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more effectively share system resources via hardware features.

[0262] In at least one embodiment, various libraries (not shown) are included in the ROCm software stack 3100 above the language runtime 3103 and can provide functional similarities to the CUDA libraries 3003 described above in conjunction with FIG. 30. In at least one embodiment, the various libraries can include, but are not limited to, mathematical, deep learning, and / or other libraries, such as, among others, the hipBLAS library that implements functionality similar to that of CUDA cuBLAS, the rocFFT library for calculating FFTs similar to CUDA cuFFT.

[0263] FIG. 32 shows an OpenCL implementation of the software stack 2900 of FIG. 29 according to at least one embodiment. In at least one embodiment, an OpenCL software stack 3200 on which an application 3201 can be launched includes an OpenCL framework 3210, an OpenCL runtime 3206, and a driver 3207. In at least one embodiment, the OpenCL software stack 3200 runs on non-vendor-specific hardware 3009. In at least one embodiment, since OpenCL is supported by devices developed by different vendors, a specific OpenCL driver may be required to interact with the hardware from such vendors.

[0264] In at least one embodiment, the application 3201, the OpenCL runtime 3206, the device kernel driver 3207, and the hardware 3208 may each implement functionality similar to the application 2901, the runtime 2905, the device kernel driver 2906, and the hardware 2907, respectively, described above in conjunction with FIG. 29. In at least one embodiment, the application 3201 further includes an OpenCL kernel 3202 having code to be executed on a device.

[0265] In at least one embodiment, OpenCL defines a "platform" that enables a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides platform layer APIs and runtime APIs, shown as platform API 3203 and runtime API 3205. In at least one embodiment, the runtime API 3205 uses a context to manage kernel execution on a device. In at least one embodiment, each identified device can be associated with a respective context, and the runtime API 3205 uses each context to manage, among other things, command queues, program objects, and kernel objects for that device, and can share memory objects. In at least one embodiment, the platform API 3203 exposes a function that allows a device context to be used, among other things, to select and initialize a device, submit work to the device via a command queue, and enable data transfer between the device, and further provides various built-in functions (not shown), including, among other things, mathematical functions, relational functions, and image processing functions.

[0266] In at least one embodiment, the compiler 3204 is also included within the OpenCL framework 3210. In at least one embodiment, the source code can be compiled offline before running the application or can be compiled online during the execution of the application. In contrast to CUDA and ROCm, in at least one embodiment, an OpenCL application can be compiled online by the compiler 3204, and the compiler 2804 can be included to represent any number of compilers that can be used to compile source code and / or IR code into binary code, such as standard portable intermediate representation (SPIR-V) code. Alternatively, in at least one embodiment, the OpenCL application can be compiled offline before the execution of such an application.

[0267] FIG. 33 shows software supported by a programming platform according to at least one embodiment. In at least one embodiment, the programming platform 3304 is configured to support various programming models 3303, middleware and / or libraries 3302, and frameworks 3301 that an application 3300 can rely on. In at least one embodiment, the application 3300 can be an AI / ML application implemented using a deep learning framework, such as MXNet, PyTorch, or TensorFlow, for example, which can rely on libraries such as cuDNN, NVIDIA Collective Communications Library (NCCL), and / or NVIDA Developer Data Loading Library (DALI®) CUDA libraries to provide accelerated computing on the underlying hardware.

[0268] In at least one embodiment, the programming platform 3304 can be one of the CUDA, ROCm, or OpenCL platforms, respectively, described above in conjunction with FIGS. 30, 31, and 32. In at least one embodiment, the programming platform 3304 supports a plurality of programming models 3303 that are abstractions of a computing system that allows for the representation of algorithms and data structures. In at least one embodiment, the programming model 3303 can expose the characteristics of the underlying hardware to improve performance. In at least one embodiment, the programming model 3303 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++ AMP"), Open Multi-Processing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute.

[0269] In at least one embodiment, the library and / or middleware 3302 provides an implementation of the abstraction of the programming model 3304. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, such middleware includes software that provides services to applications in addition to the software available from the programming platform 3304. In at least one embodiment, the library and / or middleware 3302 can include, but is not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Further, in at least one embodiment, the library and / or middleware 3302 can include the NCCL and the ROCm Communication Collectives Library ("RCCL") library that provides communication routines for the GPU, the MIOpen library for deep learning acceleration, and / or the Eigen library for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0270] In at least one embodiment, the application framework 3301 depends on the library and / or middleware 3302. In at least one embodiment, each of the application frameworks 3301 is a software framework used to implement the standard structure of application software. In at least one embodiment, returning to the AI / ML examples described above, the AI / ML application can be implemented using a framework such as the Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning framework.

[0271] Figure 34 shows compiling code for execution on one of the programming platforms of FIGS. 29-32 according to at least one embodiment. In at least one embodiment, compiler 3401 receives source code 3400 that includes both host code and device code. In at least one embodiment, compiler 3401 is configured to convert source code 3400 into host-executable code 3402 for execution on the host and device-executable code 3403 for execution on the device. In at least one embodiment, source code 3400 can be compiled either offline before execution of the application or online during execution of the application.

[0272] In at least one embodiment, source code 3400 can include code in any programming language supported by compiler 3401, such as C++, C, Fortran, etc. In at least one embodiment, source code 3400 can be included in a single source file having a mixture of host code and device code, with the location of the device code being indicated therein. In at least one embodiment, the single source file can be a.cu file that includes CUDA code, or a.hip.cpp file that includes HIP code. Alternatively, in at least one embodiment, source code 3400 can include multiple source code files rather than a single source file in which the host code and device code are separated.

[0273] In at least one embodiment, compiler 3401 is configured to compile source code 3400 into host-executable code 3402 for execution on a host and device-executable code 3403 for execution on a device. In at least one embodiment, compiler 3401 performs operations including parsing source code 3400 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3400 includes a single source file, compiler 3401 separates device code from host code in such a single source file, compiles the device code and the host code into device-executable code 3403 and host-executable code 3402 respectively, and may link device-executable code 3403 and host-executable code 3402 to each other in a single file, as will be described in more detail below with respect to FIG. 35.

[0274] In at least one embodiment, host-executable code 3402 and device-executable code 3403 can be in any suitable format, such as binary code and / or IR code. In at least one embodiment, in the case of CUDA, host-executable code 3402 can include native object code, and device-executable code 3403 can include code in PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host-executable code 3402 and device-executable code 3403 can include target binary code.

[0275] FIG. 35 is a more detailed diagram of compiling code for execution on one of the programming platforms of FIGS. 29-32 according to at least one embodiment. In at least one embodiment, compiler 3501 is configured to receive source code 3500, compile source code 3500, and output an executable file 3510. In at least one embodiment, source code 3500 is a single source file, such as a.cu file,.hip.cpp file, or a file in another format, that includes both host code and device code. In at least one embodiment, compiler 3501 can be, but is not limited to, an NVIDIA CUDA compiler ("NVCC": NVIDIA CUDA compiler) for compiling CUDA code in a.cu file, or an HCC compiler for compiling HIP code in a.hip.cpp file.

[0276] In at least one embodiment, compiler 3501 includes a compiler front-end 3502, a host compiler 3505, a device compiler 3506, and a linker 3509. In at least one embodiment, compiler front-end 3502 is configured to separate device code 3504 from host code 3503 in source code 3500. In at least one embodiment, device code 3504 is compiled by device compiler 3506 into device-executable code 3508, which may include binary code or IR code, as described. In at least one embodiment, separately, host code 3503 is compiled by host compiler 3505 into host-executable code 3507. In at least one embodiment, in the case of NVCC, host compiler 3505 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3506 may be, but is not limited to, a low-level virtual machine (LLVM)-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, in the case of HCC, both host compiler 3505 and device compiler 3506 may be, but are not limited to, LLVM-based compilers that output target binary code.

[0277] In at least one embodiment, after compiling source code 3500 into host-executable code 3507 and device-executable code 3508, linker 3509 links host-executable code 3507 and device-executable code 3508 to each other in executable file 3510. In at least one embodiment, native object code for the host and PTX or binary code for the device can be linked to each other in an Executable and Linkable Format (「ELF」) file, which is a container format used to store object code.

[0278] FIG. 36 shows translating source code prior to compiling the source code according to at least one embodiment. In at least one embodiment, source code 3600 is passed through translation tool 3601, and translation tool 3601 translates source code 3600 into translated source code 3602. In at least one embodiment, compiler 3603 is used to compile translated source code 3602 into host-executable code 3604 and device-executable code 3605 in a process similar to the compilation of source code 3400 by compiler 3401 into host-executable code 3402 and device-executable 3403 as described above in conjunction with FIG. 34.

[0279] In at least one embodiment, the translation performed by the translation tool 3601 is used to port the source 3600 for execution in an environment different from the environment in which it was originally intended to operate. In at least one embodiment, the translation tool 3601 may include a HIP translator that is used to "hipify" CUDA code targeting the CUDA platform into HIP code that can be compiled and executed on the ROCm platform, among other things. In at least one embodiment, the translation of the source code 3600 may include parsing the source code 3600 and converting calls to the (one or more) APIs provided by a certain programming model (e.g., CUDA) into corresponding calls to the (one or more) APIs provided by another programming model (e.g., HIP), as will be described in more detail below in conjunction with FIGS. 37A-38. Returning to an example of hipifying CUDA code, calls to the CUDA runtime API, the CUDA driver API, and / or the CUDA library may be converted into corresponding HIP API calls. In at least one embodiment, the automatic translation performed by the translation tool 3601 is sometimes incomplete and may require additional manual effort to fully port the source code 3600.

[0280] Configuring a GPU for general computing The following figures depict an exemplary architecture for compiling and executing compute source code, according to at least one embodiment, among other things.

[0281] FIG. 37A shows a system 37A00 configured to compile and execute CUDA source code 3710 using different types of processing units according to at least one embodiment. In at least one embodiment, the system 37A00 includes, without limitation, CUDA source code 3710, a CUDA compiler 3750, host-executable code 3770(1), host-executable code 3770(2), CUDA device-executable code 3784, a CPU 3790, a CUDA-capable GPU 3794, a GPU 3792, a CUDA-to-HIP translation tool 3720, HIP source code 3730, a HIP compiler driver 3740, an HCC 3760, and HCC device-executable code 3782.

[0282] In at least one embodiment, the CUDA source code 3710 is a set of human-readable code in the CUDA programming language. In at least one embodiment, the CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, without limitation, a mechanism for defining device code and distinguishing between device code and host code. In at least one embodiment, the device code is source code that is executable in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-capable GPU 3790, GPU 37192, or another GPGPU. In at least one embodiment, the host code is source code that is executable on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU 3790.

[0283] In at least one embodiment, the CUDA source code 3710 includes, without limitation, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, the global functions 3712, device functions 3714, host functions 3716, and host / device functions 3718 may be intermixed within the CUDA source code 3710. In at least one embodiment, each of the global functions 3712 is executable on the device and callable from the host. In at least one embodiment, one or more of the global functions 3712 can thus serve as an entry point to the device. In at least one embodiment, each of the global functions 3712 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more of the global functions 3712 define a kernel, and the kernel is executable on the device and callable from such a device. In at least one embodiment, the kernel is executed N times in parallel by N different threads on the device during execution, where N is any positive integer.

[0284] In at least one embodiment, each of the device functions 3714 is executed on the device and callable only from such a device. In at least one embodiment, each of the host functions 3716 is executed on the host and callable only from such a host. In at least one embodiment, each of the host / device functions 3716 defines both a host version of the function that is executable on the host and callable only from such a host, and a device version of the function that is executable on the device and callable only from such a device.

[0285] In at least one embodiment, the CUDA source code 3710 may also include any number of calls to any number of functions defined via the CUDA runtime API 3702, among other things. In at least one embodiment, the CUDA runtime API 3702 may include any number of functions that execute on the host, such as, among other things, allocating device memory, deallocating device memory, transferring data between host memory and device memory, and managing a system with multiple devices. In at least one embodiment, the CUDA source code 3710 may also include any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, the CUDA API may be any API designed for use by CUDA code. In at least one embodiment, the CUDA API may include, among other things, the CUDA runtime API 3702, the CUDA driver API, APIs for any number of CUDA libraries, and the like. In at least one embodiment, and with respect to the CUDA runtime API 3702, the CUDA driver API is a lower-level API that provides more fine-grained control of the device. In at least one embodiment, examples of CUDA libraries may include, among other things, cuBLAS, cuFFT, cuRAND, cuDNN, and the like.

[0286] In at least one embodiment, the CUDA compiler 3750 compiles input CUDA code (e.g., the CUDA source code 3710) to produce host-executable code 3770(1) and CUDA device-executable code 3784. In at least one embodiment, the CUDA compiler 3750 is NVCC. In at least one embodiment, the host-executable code 3770(1) is a compiled version of the host code included in the input source code that is executable on the CPU 3790. In at least one embodiment, the CPU 3790 may be any processor optimized for sequential instruction processing.

[0287] In at least one embodiment, the CUDA device-executable code 3784 is a compiled version of device code included in the input source code that is executable on a CUDA-enabled GPU 3794. In at least one embodiment, the CUDA device-executable code 3784 includes, without limitation, binary code. In at least one embodiment, the CUDA device-executable code 3784 includes, without limitation, IR code such as PTX code, which is further compiled at runtime by the device driver into binary code for a particular target device (e.g., CUDA-enabled GPU 3794). In at least one embodiment, the CUDA-enabled GPU 3794 can be any processor that is optimized for parallel instruction processing and supports CUDA. In at least one embodiment, the CUDA-enabled GPU 3794 is developed by NVIDIA Corporation of Santa Clara, California.

[0288] In at least one embodiment, the CUDA-to-HIP translation tool 3720 is configured to translate CUDA source code 3710 into functionally similar HIP source code 3730. In at least one embodiment, the HIP source code 3730 is a set of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language that includes, but is not limited to, a functionally similar version of the CUDA mechanism for defining device code and distinguishing device code from host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, one or more mechanisms for defining a global function 3712, but such a HIP programming language may not support dynamic parallelism, and thus the global function 3712 defined in the HIP code may be callable only from the host.

[0289] In at least one embodiment, the HIP source code 3730 includes, without limitation, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, the HIP source code 3730 may also include any number of calls to any number of functions specified in the HIP runtime API 3732. In at least one embodiment, the HIP runtime API 3732 includes, without limitation, a functionally similar version of a subset of the functions included in the CUDA runtime API 3702. In at least one embodiment, the HIP source code 3730 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, the HIP API can be any API designed for use with HIP code and / or ROCm. In at least one embodiment, the HIP API includes, without limitation, the HIP runtime API 3732, the HIP driver API, the API for any number of HIP libraries, the API for any number of ROCm libraries, and the like.

[0290] In at least one embodiment, the CUDA-to-HIP translation tool 3720 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax and converts any number of other CUDA calls in the CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, the CUDA call is a call to a function specified in the CUDA API, and the HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA-to-HIP translation tool 3720 converts any number of calls to functions specified in the CUDA runtime API 3702 to any number of calls to functions specified in the HIP runtime API 3732.

[0291] In at least one embodiment, the CUDA-to-HIP translation tool 3720 is a tool known as hipify-perl that performs a text-based translation process. In at least one embodiment, the CUDA-to-HIP translation tool 3720 is a tool known as hipify-clang, which performs a more complex and robust translation process involving parsing CUDA code using clang (a compiler front-end) and then translating the resulting symbols. In at least one embodiment, properly converting CUDA code to HIP code may require modifications (e.g., manual editing) in addition to the modifications performed by the CUDA-to-HIP translation tool 3720.

[0292] In at least one embodiment, the HIP compiler driver 3740 is a front-end that determines the target device 3746 and then configures a compiler compatible with the target device 3746 to compile the HIP source code 3730. In at least one embodiment, the target device 3746 is a processor optimized for parallel instruction processing. In at least one embodiment, the HIP compiler driver 3740 may determine the target device 3746 in any technically feasible manner.

[0293] In at least one embodiment, when the target device 3746 is compatible with CUDA (e.g., a CUDA-compatible GPU 3794), the HIP compiler driver 3740 generates a HIP / NVCC compile command 3742. In at least one embodiment, and as described in more detail in conjunction with FIG. 37B, the HIP / NVCC compile command 3742 configures the CUDA compiler 3750 to compile the HIP source code 3730 using, without limitation, a HIP-to-CUDA translation header and the CUDA runtime library. In at least one embodiment, and in response to the HIP / NVCC compile command 3742, the CUDA compiler 3750 generates host-executable code 3770(1) and CUDA device-executable code 3784.

[0294] In at least one embodiment, if the target device 3746 is not compatible with CUDA, the HIP compiler driver 3740 generates a HIP / HCC compile command 3744. In at least one embodiment, and as described in more detail in conjunction with FIG. 37C, the HIP / HCC compile command 3744 configures HCC 3760 to compile HIP source code 3730 using, without limitation, HCC headers and the HIP / HCC runtime library. In at least one embodiment, and in response to the HIP / HCC compile command 3744, HCC 3760 generates host-executable code 3770(2) and HCC device-executable code 3782. In at least one embodiment, the HCC device-executable code 3782 is a compiled version of the device code included in the HIP source code 3730 that is executable on the GPU 3792. In at least one embodiment, the GPU 3792 can be any processor that is optimized for parallel instruction processing, is not compatible with CUDA, and is compatible with HCC. In at least one embodiment, the GPU 3792 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the GPU 3792 is a CUDA-incompatible GPU 3792.

[0295] For illustrative purposes only, three different flows that may be implemented in at least one example for compiling the CUDA source code 3710 for execution on the CPU 3790 and different devices are illustrated in FIG. 37A. In at least one example, the direct CUDA flow compiles the CUDA source code 3710 for execution on the CPU 3790 and the CUDA-capable GPU 3794 without translating the CUDA source code 3710 to HIP source code 3730. In at least one example, the indirect CUDA flow translates the CUDA source code 3710 to HIP source code 3730 and then compiles the HIP source code 3730 for execution on the CPU 3790 and the CUDA-capable GPU 3794. In at least one example, the CUDA / HCC flow translates the CUDA source code 3710 to HIP source code 3730 and then compiles the HIP source code 3730 for execution on the CPU 3790 and the GPU 3792.

[0296] A direct CUDA flow that may be implemented in at least one embodiment is illustrated via a series of bubbles annotated with dashed lines and A1 - A3. In at least one embodiment, as illustrated by the bubble annotated with A1, the CUDA compiler 3750 receives CUDA source code 3710 and a CUDA compile command 3748 that configures the CUDA compiler 3750 to compile the CUDA source code 3710. In at least one embodiment, the CUDA source code 3710 used in the direct CUDA flow is written in a CUDA programming language based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, in response to the CUDA compile command 3748, the CUDA compiler 3750 generates host - executable code 3770(1) and CUDA device - executable code 3784 (illustrated by the bubble annotated with A2). In at least one embodiment, as illustrated by the bubble annotated with A3, the host - executable code 3770(1) and CUDA device - executable code 3784 may be executed on the CPU 3790 and CUDA - enabled GPU 3794, respectively. In at least one embodiment, the CUDA device - executable code 3784 includes, without limitation, binary code. In at least one embodiment, the CUDA device - executable code 3784 includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime.

[0297] An indirect CUDA flow that can be implemented in at least one embodiment is illustrated via a series of bubbles annotated with dotted lines and B1 - B6. In at least one embodiment, as illustrated by the bubble annotated with B1, the CUDA - to - HIP translation tool 3720 receives the CUDA source code 3710. In at least one embodiment, as illustrated by the bubble annotated with B2, the CUDA - to - HIP translation tool 3720 translates the CUDA source code 3710 into HIP source code 3730. In at least one embodiment, as illustrated by the bubble annotated with B3, the HIP compiler driver 3740 receives the HIP source code 3730 and determines that the target device 3746 is CUDA - compatible.

[0298] In at least one example, as illustrated by the bubble annotated with B4, the HIP compiler driver 3740 generates a HIP / NVCC compile command 3742 and sends both the HIP / NVCC compile command 3742 and the HIP source code 3730 to the CUDA compiler 3750. In at least one example, as described in more detail in conjunction with FIG. 37B, the HIP / NVCC compile command 3742 configures the CUDA compiler 3750 to compile the HIP source code 3730 using, without limitation, a HIP-to-CUDA translation header and the CUDA runtime library. In at least one example, in response to the HIP / NVCC compile command 3742, the CUDA compiler 3750 generates host-executable code 3770(1) and CUDA device-executable code 3784 (illustrated by the bubble annotated with B5). In at least one example, as illustrated by the bubble annotated with B6, the host-executable code 3770(1) and the CUDA device-executable code 3784 can be executed on the CPU 3790 and the CUDA-capable GPU 3794, respectively. In at least one example, the CUDA device-executable code 3784 includes, without limitation, binary code. In at least one example, the CUDA device-executable code 3784 includes, without limitation, PTX code and is further compiled into binary code for a particular target device at runtime.

[0299] The CUDA / HCC flow that can be implemented in at least one embodiment is illustrated via a series of bubbles annotated with solid lines and C1 - C6. In at least one embodiment, as illustrated by the bubble annotated with C1, the CUDA - to - HIP translation tool 3720 receives the CUDA source code 3710. In at least one embodiment, as illustrated by the bubble annotated with C2, the CUDA - to - HIP translation tool 3720 translates the CUDA source code 3710 into HIP source code 3730. In at least one embodiment, as illustrated by the bubble annotated with C3, the HIP compiler driver 3740 receives the HIP source code 3730 and determines that the target device 3746 is not CUDA - compatible.

[0300] In at least one embodiment, the HIP compiler driver 3740 generates a HIP / HCC compile command 3744 and sends both the HIP / HCC compile command 3744 and the HIP source code 3730 to HCC3760 (illustrated by the bubble annotated with C4). In at least one embodiment, as will be described in more detail in conjunction with FIG. 37C, the HIP / HCC compile command 3744 configures HCC3760 to compile the HIP source code 3730 using, without limitation, HCC headers and the HIP / HCC runtime library. In at least one embodiment, in response to the HIP / HCC compile command 3744, HCC3760 generates host - executable code 3770(2) and HCC device - executable code 3782 (illustrated by the bubble annotated with C5). In at least one embodiment, as illustrated by the bubble annotated with C6, the host - executable code 3770(2) and the HCC device - executable code 3782 can be executed on the CPU3790 and the GPU3792, respectively.

[0301] In at least one embodiment, after the CUDA source code 3710 is translated into HIP source code 3730, the HIP compiler driver 3740 can then be used to generate executable code for either the CUDA-capable GPU 3794 or GPU 3792 without re-running the CUDA-to-HIP translation tool 3720. In at least one embodiment, the CUDA-to-HIP translation tool 3720 translates the CUDA source code 3710 into HIP source code 3730, and the HIP source code 3730 is then stored in memory. In at least one embodiment, the HIP compiler driver 3740 then configures the HCC 3760 to generate host-executable code 3770(2) and HCC device-executable code 3782 based on the HIP source code 3730. In at least one embodiment, the HIP compiler driver 3740 then configures the CUDA compiler 3750 to generate host-executable code 3770(1) and CUDA device-executable code 3784 based on the stored HIP source code 3730.

[0302] FIG. 37B shows a system 3704 configured to compile and execute the CUDA source code 3710 of FIG. 37A using a CPU 3790 and a CUDA-capable GPU 3794, according to at least one embodiment. In at least one embodiment, the system 3704 includes, without limitation, the CUDA source code 3710, the CUDA-to-HIP translation tool 3720, the HIP source code 3730, the HIP compiler driver 3740, the CUDA compiler 3750, the host-executable code 3770(1), the CUDA device-executable code 3784, the CPU 3790, and the CUDA-capable GPU 3794.

[0303] In at least one example, and as previously described herein in conjunction with FIG. 37A, the CUDA source code 3710 includes, without limitation, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one example, the CUDA source code 3710 also includes, without limitation, any number of calls to any number of functions specified in any number of CUDA APIs.

[0304] In at least one example, the CUDA-to-HIP translation tool 3720 translates the CUDA source code 3710 into HIP source code 3730. In at least one example, the CUDA-to-HIP translation tool 3720 converts each kernel call in the CUDA source code 3710 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA source code 3710 to any number of other functionally equivalent HIP calls.

[0305] In at least one embodiment, the HIP compiler driver 3740 determines that the target device 3746 is CUDA - capable and generates a HIP / NVCC compile command 3742. In at least one embodiment, the HIP compiler driver 3740 then configures the CUDA compiler 3750 via the HIP / NVCC compile command 3742 to compile the HIP source code 3730. In at least one embodiment, the HIP compiler driver 3740 provides access to a HIP - to - CUDA translation header 3752 as part of configuring the CUDA compiler 3750. In at least one embodiment, the HIP - to - CUDA translation header 3752 translates any number of constructs (e.g., functions) specified in any number of HIP APIs to any number of constructs specified in any number of CUDA APIs. In at least one embodiment, the CUDA compiler 3750 uses the HIP - to - CUDA translation header 3752 in conjunction with a CUDA runtime library 3754 corresponding to the CUDA runtime API 3702 to generate host - executable code 3770(1) and CUDA device - executable code 3784. In at least one embodiment, the host - executable code 3770(1) and the CUDA device - executable code 3784 can then be executed on a CPU 3790 and a CUDA - capable GPU 3794, respectively. In at least one embodiment, the CUDA device - executable code 3784 includes, without limitation, binary code. In at least one embodiment, the CUDA device - executable code 3784 includes, without limitation, PTX code and is further compiled at runtime to binary code for a particular target device.

[0306] FIG. 37C shows a system 3706 configured to compile and execute the CUDA source code 3710 of FIG. 37A using a CPU 3790 and a CUDA-incompatible GPU 3792, according to at least one embodiment. In at least one embodiment, the system 3706 includes, without limitation, the CUDA source code 3710, a translation tool 3720 from CUDA to HIP, HIP source code 3730, a HIP compiler driver 3740, HCC 3760, host-executable code 3770(2), HCC device-executable code 3782, a CPU 3790, and a GPU 3792.

[0307] In at least one embodiment, and as previously described herein in conjunction with FIG. 37A, the CUDA source code 3710 includes, without limitation, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, the CUDA source code 3710 also includes any number of calls to any number of functions specified in any number of CUDA APIs.

[0308] In at least one embodiment, the translation tool 3720 from CUDA to HIP translates the CUDA source code 3710 into HIP source code 3730. In at least one embodiment, the translation tool 3720 from CUDA to HIP converts each kernel call in the CUDA source code 3710 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the source code 3710 to any number of other functionally equivalent HIP calls.

[0309] In at least one embodiment, the HIP compiler driver 3740 then determines that the target device 3746 is not CUDA - compliant and generates a HIP / HCC compile command 3744. In at least one embodiment, the HIP compiler driver 3740 then configures HCC 3760 to execute the HIP / HCC compile command 3744 to compile the HIP source code 3730. In at least one embodiment, the HIP / HCC compile command 3744 configures HCC 3760 to use the HIP / HCC runtime library 3758 and the HCC headers 3756 to generate, without limitation, host - executable code 3770(2) and HCC device - executable code 3782. In at least one embodiment, the HIP / HCC runtime library 3758 corresponds to the HIP runtime API 3732. In at least one embodiment, the HCC headers 3756 include, without limitation, any number and type of interoperability mechanisms for HIP and HCC. In at least one embodiment, the host - executable code 3770(2) and the HCC device - executable code 3782 can be executed on the CPU 3790 and the GPU 3792, respectively.

[0310] FIG. 38 shows an exemplary kernel translated by the CUDA - to - HIP translation tool 3720 of FIG. 37C, according to at least one embodiment. In at least one embodiment, the CUDA source code 3710 divides the overall problem that a given kernel is designed to solve into relatively coarse sub - problems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads. In at least one embodiment, each sub - problem is further divided into relatively fine - grained pieces that can be solved in parallel and in concert by the threads within the thread block. In at least one embodiment, the threads within a thread block can work in concert by sharing data through shared memory and by synchronizing their execution to coordinate memory accesses.

[0311] In at least one embodiment, the CUDA source code 3710 organizes the thread blocks associated with a given kernel into a one-dimensional grid, two-dimensional grid, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes any number of threads, without limitation, and the grid includes any number of thread blocks, without limitation.

[0312] In at least one embodiment, the kernel is a function in device code defined using the "__global__" declaration specifier. In at least one embodiment, the dimensions of the grid that executes the kernel for a given kernel call and associated stream are specified using the CUDA kernel launch syntax 3810. In at least one embodiment, the CUDA kernel launch syntax 3810 is specified as "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream>>>(KernelArguments);". In at least one embodiment, the execution configuration syntax is the "<<<...>>>" construct inserted between the kernel name ("KernelName") and the list of kernel arguments enclosed in parentheses ("KernelArguments"). In at least one embodiment, the CUDA kernel launch syntax 3810 includes, without limitation, the CUDA launch function syntax instead of the execution configuration syntax.

[0313] In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure that includes, without limitation, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z is defaulted to 1. In at least one embodiment, if y is not specified, y is defaulted to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread that executes the kernel is given a unique thread ID that is accessible within the kernel through an intrinsic variable (e.g., "threadIdx").

[0314] In at least one embodiment, and with respect to CUDA kernel launch syntax 3810, "SharedMemorySize" is an optional argument that specifies the number of bytes in shared memory that is dynamically allocated per thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment, and with respect to CUDA kernel launch syntax 3810, SharedMemorySize is defaulted to 0. In at least one embodiment, and with respect to CUDA kernel launch syntax 3810, "Stream" is an optional argument that specifies the associated stream and is defaulted to 0 to specify the default stream. In at least one embodiment, a stream is a sequence of commands that execute in order (and in some cases, are issued by different host threads). In at least one embodiment, different streams can execute commands out of order with respect to each other or simultaneously.

[0315] In at least one embodiment, the CUDA source code 3710 includes, without limitation, a kernel definition and a main function for an exemplary kernel "MatAdd". In at least one embodiment, the main function is host code that runs on the host and includes, without limitation, a kernel call to cause the kernel MatAdd to execute on the device. In at least one embodiment, and as shown, the kernel MatAdd adds two matrices A and B of size N×N, where N is a positive integer, and stores the result in matrix C. In at least one embodiment, the main function defines the threadsPerBlock variable as 16×16 and the numBlocks variable as N / 16×N / 16. In at least one embodiment, the main function then specifies the kernel call "MatAdd<<<numBlocks,threadsPerBlock>>>(A,B,C);". In at least one embodiment, and as per the CUDA kernel launch syntax 3810, the kernel MatAdd is executed using a grid of thread blocks having dimensions N / 16×N / 16, where each thread block has dimensions 16×16. In at least one embodiment, each thread block includes 256 threads, and the grid is created with enough blocks such that each thread in such a grid has one thread per matrix element, and each thread in such a grid executes the kernel MatAdd to perform one pairwise addition.

[0316] In at least one embodiment, while translating CUDA source code 3710 to HIP source code 3730, the CUDA-to-HIP translation tool 3720 translates each kernel call in the CUDA source code 3710 from CUDA kernel launch syntax 3810 to HIP kernel launch syntax 3820, and converts any number of other CUDA calls in the source code 3710 to any number of other functionally similar HIP calls. In at least one embodiment, the HIP kernel launch syntax 3820 is specified as "hipLaunchKernelGGL(KernelName,GridSize,BlockSize,SharedMemorySize,Stream,KernelArguments);". In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments has the same meaning in the HIP kernel launch syntax 3820 as in the case of the CUDA kernel launch syntax 3810 (previously described herein). In at least one embodiment, the arguments SharedMemorySize and Stream are required in the HIP kernel launch syntax 3820 and are optional in the CUDA kernel launch syntax 3810.

[0317] In at least one embodiment, a portion of the HIP source code 3730 illustrated in FIG. 38 is identical to a portion of the CUDA source code 3710 illustrated in FIG. 38, except for the kernel call to execute on the device in the kernel MatAdd. In at least one embodiment, the kernel MatAdd is defined in the HIP source code 3730 using the same "__global__" declaration specifier as the kernel MatAdd is defined in the CUDA source code 3710. In at least one embodiment, the kernel call in the HIP source code 3730 is "hipLaunchKernelGGL(MatAdd,numBlocks,threadsPerBlock,0,0,A,B,C);", while the corresponding kernel call in the CUDA source code 3710 is "MatAdd<<<numBlocks,threadsPerBlock>>>(A,B,C);".

[0318] FIG. 39 shows the CUDA-incompatible GPU 3792 of FIG. 37C in more detail according to at least one embodiment. In at least one embodiment, the GPU 3792 is developed by AMD corporation of Santa Clara. In at least one embodiment, the GPU 3792 can be configured to perform compute operations in a highly parallel manner. In at least one embodiment, the GPU 3792 is configured to execute graphics pipeline operations, such as rendering commands, pixel operations, geometric calculations, and other operations related to rendering images to a display. In at least one embodiment, the GPU 3792 is configured to execute operations not related to graphics. In at least one embodiment, the GPU 3792 is configured to execute both operations related to graphics and operations not related to graphics. In at least one embodiment, the GPU 3792 can be configured to execute the device code included in the HIP source code 3730.

[0319] In at least one embodiment, GPU 3792 includes, without limitation, any number of programmable processing units 3920, a command processor 3910, an L2 cache 3922, a memory controller 3970, a DMA engine 3980(1), a system memory controller 3982, a DMA engine 3980(2), and a GPU controller 3984. In at least one embodiment, each programmable processing unit 3920 includes, without limitation, a workload manager 3930 and any number of compute units 3940. In at least one embodiment, the command processor 3910 reads commands from one or more command queues (not shown) and distributes the commands to the workload manager 3930. In at least one embodiment, for each programmable processing unit 3920, the associated workload manager 3930 distributes work to the compute units 3940 included within the programmable processing unit 3920. In at least one embodiment, each compute unit 3940 can execute any number of thread blocks, but each thread block executes on a single compute unit 3940. In at least one embodiment, a workgroup is a thread block.

[0320] In at least one embodiment, each compute unit 3940 includes, without limitation, any number of SIMD units 3950 and a shared memory 3960. In at least one embodiment, each SIMD unit 3950 may implement a SIMD architecture and be configured to perform operations in parallel. In at least one embodiment, each SIMD unit 3950 includes, without limitation, a vector ALU 3952 and a vector register file 3954. In at least one embodiment, each SIMD unit 3950 executes different warps. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process different sets of data based on a single set of instructions. In at least one embodiment, predication may be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via the shared memory 3960.

[0321] In at least one embodiment, the programmable processing unit 3920 is referred to as a "shader engine". In at least one embodiment, each programmable processing unit 3920 includes, without limitation, in addition to the compute unit 3940, any amount of dedicated graphics hardware. In at least one embodiment, each programmable processing unit 3920 includes, without limitation, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of render back ends, a workload manager 3930, and any number of compute units 3940.

[0322] In at least one embodiment, compute unit 3940 shares L2 cache 3922. In at least one embodiment, L2 cache 3922 is partitioned. In at least one embodiment, GPU memory 3990 is accessible by all compute units 3940 in GPU 3792. In at least one embodiment, memory controller 3970 and system memory controller 3982 facilitate data transfer between GPU 3792 and a host, and DMA engine 3980(1) enables asynchronous memory transfer between GPU 3792 and such a host. In at least one embodiment, memory controller 3970 and GPU controller 3984 facilitate data transfer between GPU 3792 and other GPUs 3792, and DMA engine 3980(2) enables asynchronous memory transfer between GPU 3792 and other GPUs 3792.

[0323] In at least one embodiment, the GPU 3792 includes any amount and type of system interconnect that facilitates data and control transmissions across any number and type of directly or indirectly linked components, which may be internal or external to the GPU 3792. In at least one embodiment, the GPU 3792 includes any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, the GPU 3792 may include any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, the GPU 3792 implements a memory subsystem that includes any amount and type of memory controllers (e.g., memory controller 3970 and system memory controller 3982) and memory devices (e.g., shared memory 3960) that may be dedicated to one component or shared among multiple components. In at least one embodiment, the GPU 3792 implements a cache subsystem that includes one or more cache memories (e.g., L2 cache 3922), and the one or more cache memories may each be private to any number of components (e.g., SIMD unit 3950, compute unit 3940, and programmable processing unit 3920) or shared among any number of components.

[0324] Figure 40 shows how threads of an exemplary CUDA grid 4020 according to at least one embodiment are mapped to different compute units 3940 of FIG. 39. In at least one embodiment, and for illustrative purposes only, grid 4020 has a GridSize of BX × BY × 1 and a BlockSize of TX × TY × 1. In at least one embodiment, grid 4020 thus includes, without limitation, (BX*BY) thread blocks 4030, each thread block 4030 including, without limitation, (TX*TY) threads 4040. Threads 4040 are illustrated in FIG. 40 as squiggly arrows.

[0325] In at least one embodiment, grid 4020 is mapped to programmable processing unit 3920(1) including, without limitation, compute units 3940(1) to 3940(C). In at least one embodiment, and as shown, (BJ*BY) thread blocks 4030 are mapped to compute unit 3940(1) and the remaining thread blocks 4030 are mapped to compute unit 3940(2). In at least one embodiment, each thread block 4030 may include, without limitation, any number of warps, each warp being mapped to a different SIMD unit 3950 of FIG. 39.

[0326] In at least one embodiment, warps within a given thread block 4030 may synchronize with each other and communicate through shared memory 3960 included within the associated compute unit 3940. For example, and in at least one embodiment, warps within thread block 4030(BJ,1) may synchronize with each other and communicate through shared memory 3960(1). For example, and in at least one embodiment, warps within thread block 4030(BJ+1,1) may synchronize with each other and communicate through shared memory 3960(2).

[0327] Figure 41 shows how to migrate existing CUDA code to Data Parallel C++ code according to at least one embodiment. Data Parallel C++ (DPC++) can refer to an open standard-based alternative to a single architecture proprietary language, which allows developers to reuse code across hardware targets (CPUs as well as accelerators such as GPUs and FPGAs), and also perform custom tuning for a particular accelerator. DPC++ uses similar and / or the same C and C++ constructs that follow ISO C++ with which developers may be familiar. DPC++ incorporates the standard SYCL from the Khronos Group to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer based on the concepts, portability, and efficiency underlying OpenCL, which enables code for heterogeneous processors to be written in a “single source” style using standard C++. SYCL can enable single-source development where C++ template functions can contain both host code and device code, construct complex algorithms using OpenCL acceleration, and then reuse them across their entire source code for different types of data.

[0328] In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code that can be introduced across various hardware targets. In at least one embodiment, a DPC++ compiler is used to generate DPC++ applications that can be introduced across various hardware targets, and a DPC++ compatibility tool can be used to migrate CUDA applications to DPC++ multi-platform programs. In at least one embodiment, a DPC++-based tool kit includes a DPC++ compiler for introducing applications across various hardware targets, a DPC++ library for increasing productivity and performance across CPUs, GPUs, and FPGAs, a DPC++ compatibility tool for migrating CUDA applications to multi-platform applications, and any suitable combination thereof.

[0329] In at least one embodiment, a DPC++ programming model is utilized for one or more aspects related to simply programming CPUs and accelerators by using modern C++ features to express parallelism using a programming language called Data Parallel C++. The DPC++ programming language is utilized for code reuse for hosts (e.g., CPUs) and accelerators (e.g., GPUs or FPGAs), uses a single source language, and can communicate execution and memory dependencies clearly. The mapping within DPC++ code can be used to migrate an application to operate on a set of hardware or hardware devices that best accelerates the workload. A host can be available to simplify the development and debugging of device code even on platforms without available accelerators.

[0330] In at least one embodiment, CUDA source code 4100 is provided as input to a DPC++ compatibility tool 4102 to generate human-readable DPC++ 4104. In at least one embodiment, the human-readable DPC++ 4104 includes inline comments generated by the DPC++ compatibility tool 4102, which guide the developer regarding how and / or where to modify the DPC++ code to complete 4106 the coding and tuning to the desired performance, thereby generating DPC++ source code 4108.

[0331] In at least one embodiment, the CUDA source code 4100 is a set of human-readable source code of the CUDA programming language or includes such a set. In at least one embodiment, the CUDA source code 4100 is human-readable source code of the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, the device code is source code that, after compilation, is executable on a device (e.g., a GPU or FPGA), can be executed on one or more processor cores of the device, or can include a more parallelizable workflow. In at least one embodiment, the device is a processor optimized for parallel instruction processing, such as a CUDA-compatible GPU, a GPU, or another GPGPU. In at least one embodiment, the host code is source code that is executable on the host after compilation. In at least one embodiment, some or all of the host code and device code can be executed in parallel across a CPU and a GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. The CUDA source code 4100 described with respect to FIG. 41 can conform to the CUDA source code described elsewhere in this specification.

[0332] In at least one embodiment, the DPC++ compatibility tool 4102 refers to an executable tool, program, application, or any other suitable type of tool that is used to facilitate the migration of CUDA source code 4100 to DPC++ source code 4108. In at least one embodiment, the DPC++ compatibility tool 4102 is a command-line based code migration tool that is available as part of a DPC++ tool kit used to port existing CUDA sources to DPC++. In at least one embodiment, the DPC++ compatibility tool 4102 converts some or all of the source code of a CUDA application from CUDA to DPC++ and generates a resulting file that is at least partially written in DPC++ and is called human-readable DPC++ 4104. In at least one embodiment, the human-readable DPC++ 4104 includes comments generated by the DPC++ compatibility tool 4102 to indicate where user intervention may be required. In at least one embodiment, user intervention is required when the CUDA source code 4100 calls a CUDA API that does not have a similar DPC++ API, and other examples where user intervention is required will be described in more detail later.

[0333] In at least one embodiment, the workflow for migrating CUDA source code 4100 (e.g., an application or a portion thereof) includes creating one or more compile database files, migrating CUDA to DPC++ using DPC++ compatibility tool 4102, completing the migration and validating it, thereby generating DPC++ source code 4108, and compiling DPC++ source code 4108 using a DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts the commands executed when a Makefile is run and stores them in a compile database file. In at least one embodiment, the file is stored in JSON format. In at least one embodiment, the intercept-built command converts Makefile commands to DPC compatibility commands.

[0334] In at least one embodiment, intercept-build is a utility script that intercepts the build process to capture compile options, macro defs, and include paths and writes this data to a compile database file. In at least one embodiment, the compile database file is a JSON file. In at least one embodiment, DPC++ compatibility tool 4102 parses the compile database and applies options when migrating the input source. In at least one embodiment, the use of intercept-build is optional but highly recommended for Make- or CMake-based environments. In at least one embodiment, the migration database includes commands, directories, and files, where the commands may include the necessary compile flags, the directories may include paths to header files, and the files may include paths to CUDA files.

[0335] In at least one example, the DPC++ compatibility tool 4102 migrates CUDA code (e.g., an application) written in CUDA to DPC++ by generating DPC++ whenever possible. In at least one example, the DPC++ compatibility tool 4102 is available as part of a tool kit. In at least one example, the DPC++ tool kit includes an intercept-build tool. In at least one example, the intercept-built tool creates a compile database that captures compile commands to migrate CUDA files. In at least one example, the compile database generated by the intercept-built tool is used by the DPC++ compatibility tool 4102 to migrate CUDA code to DPC++. In at least one example, non-CUDA C++ code and files are migrated as-is. In at least one example, the DPC++ compatibility tool 4102 generates human-readable DPC++ 4104, which may not be compiled by the DPC++ compiler when generated by the DPC++ compatibility tool 4102 and may require additional plumbing to identify portions of the code that were not migrated correctly and may involve manual intervention, such as by a developer. In at least one example, the DPC++ compatibility tool 4102 provides hints or tools embedded in the code to assist the developer in manually migrating additional code that may not be automatically migrated. In at least one example, the migration is a one-time activity for a source file, project, or application.

[0336] In at least one embodiment, the DPC++ compatibility tool 41002 can successfully migrate all parts of the CUDA code to DPC++, with the possible optional step of manually verifying and tuning the performance of the generated DPC++ source code. In at least one embodiment, the DPC++ compatibility tool 4102 directly generates DPC++ source code 4108 that is compiled by a DPC++ compiler without requiring or utilizing human intervention to modify the DPC++ code generated by the DPC++ compatibility tool 4102. In at least one embodiment, the DPC++ compatibility tool generates compilable DPC++ code, which can optionally be adjusted by the developer for performance, readability, maintainability, various other considerations, or any combination thereof.

[0337] In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files using at least in part the DPC++ compatibility tool 4102. In at least one embodiment, the CUDA source code can include one or more header files that can include CUDA header files. In at least one embodiment, the CUDA source file includes the <cuda.h> header file and the <stdio.h> header file that can be used to print text. In at least one embodiment, a portion of the vector addition kernel CUDA source file can be written as or related to the following.

Number

Number

[0338] In at least one embodiment, and with respect to the CUDA source files presented above, the DPC++ compatibility tool 4102 parses the CUDA source code and replaces header files with appropriate DPC++ header files and SYCL header files. In at least one embodiment, the DPC++ header files include helper declarations. In CUDA, there is a concept of thread IDs, and correspondingly, in DPC++ or SYCL, for each element, there is a local identifier.

[0339] In at least one embodiment, and with respect to the CUDA source files presented above, there are two vectors A and B that are initialized, and the vector addition result is placed into vector C as part of VectorAddKernel(). In at least one embodiment, as part of migrating the CUDA code to DPC++ code, the DPC++ compatibility tool 4102 converts the CUDA thread IDs used to index work elements to SYCL standard addressing for work elements via local IDs. In at least one embodiment, the DPC++ code generated by the DPC++ compatibility tool 4102 can be optimized, for example, by reducing the dimensions of the nd_item, thereby increasing memory and / or processor utilization.

[0340] In at least one embodiment, and with respect to the CUDA source files presented above, memory allocation is migrated. In at least one embodiment, cudaMalloc() is migrated to the unified shared memory SYCL call malloc_device(), which depends on SYCL concepts such as platform, device, context, and queue, and to which the device and context are passed. In at least one embodiment, the SYCL platform can have multiple devices (e.g., a host and a GPU device), the device can have multiple queues to which jobs can be submitted, each device can have a context, the context can have multiple devices, and can manage shared memory objects.

[0341] In at least one embodiment, and with respect to the CUDA source files presented above, the main() function calls or invokes VectorAddKernel() to add two vectors A and B to each other and store the result in vector C. In at least one embodiment, the CUDA code for calling VectorAddKernel() is replaced by DPC++ code for submitting the kernel to a command queue for execution. In at least one embodiment, the command group handler cgh passes data, synchronization, and computation to be submitted to the queue, and parallel_for is called for the number of global elements and the number of work items in the work group in which VectorAddKernel() is called.

[0342] In at least one embodiment, and with respect to the CUDA source files presented above, CUDA calls for copying device memory and then freeing the memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing a vector of floating-point variables) is migrated as-is without being modified by the DPC++ compatibility tool 4102. In at least one embodiment, the DPC++ compatibility tool 4102 modifies the CUDA API for memory setup and / or host calls to execute kernels on the acceleration device. In at least one embodiment, and with respect to the CUDA source files presented above, the corresponding human-readable DPC++ 4104 (which may be compilable) is written as follows or is related to the following.

Number

Number

Number

[0343] In at least one embodiment, the human-readable DPC++ 4104 refers to the output generated by the DPC++ compatibility tool 4102 and can be optimized in one way or another. In at least one embodiment, the human-readable DPC++ 4104 generated by the DPC++ compatibility tool 4102 can be manually edited by the developer after migration for the purpose of making it more sustainable, performance, or other considerations. In at least one embodiment, the DPC++ code generated by a DPC++ compatibility tool 41002 such as the disclosed DPC++ can be optimized by removing repeated calls to get_current_device() and / or get_default_context() for each malloc_device() call. In at least one embodiment, the DPC++ code generated above uses a three-dimensional nd_range, which uses only a single dimension and can be refactored to reduce memory usage. In at least one embodiment, the developer can manually edit the DPC++ code generated by the DPC++ compatibility tool 4102 and replace the use of unified shared memory with accessors. In at least one embodiment, the DPC++ compatibility tool 4102 has options for changing how it migrates CUDA code to DPC++ code. In at least one embodiment, the DPC++ compatibility tool 4102 is redundant because it uses a general template for migrating CUDA code to DPC++ code that works in many cases.

[0344] In at least one embodiment, the CUDA-to-DPC++ migration workflow includes steps to prepare for migration using an intercept-build script, steps to perform the migration of a CUDA project to DPC++ using the DPC++ Compatibility Tool 4102, steps to manually review and edit the migrated source files for completion and sanity, and steps to compile the final DPC++ code to generate a DPC++ application. In at least one embodiment, the manual review of the DPC++ source code may be required in one or more scenarios including, but not limited to, the migrated API not returning an error code (CUDA code can return an error code which can then be consumed by the application, whereas SYCL uses exceptions to report errors and thus does not use error codes to surface errors), CUDA compute-capability dependent logic not being supported by DPC++, and statements possibly being deleted. In at least one embodiment, scenarios where the DPC++ code requires manual intervention may include, but are not limited to, error code logic being replaced with or commented out with (*,0) code, equivalent DPC++ APIs not being available, CUDA compute-capability dependent logic, hardware-dependent APIs (clock()), missing features, unsupported APIs, runtime measurement logic, handling built-in vector type conflicts, migration of the cuBLAS API, etc.

[0345] In at least one embodiment, one or more of the techniques described herein utilize the oneAPI programming model. In at least one embodiment, the oneAPI programming model refers to a programming model for interacting with various compute accelerator architectures. In at least one embodiment, oneAPI refers to an application programming interface (API) designed to interact with various compute accelerator architectures. In at least one embodiment, the oneAPI programming model utilizes the DPC++ programming language. In at least one embodiment, the DPC++ programming language refers to a high-level language for data parallel programming productivity. In at least one embodiment, the DPC++ programming language is at least partially based on the C and / or C++ programming languages. In at least one embodiment, the oneAPI programming model is a programming model developed by Intel Corporation of Santa Clara, California, etc.

[0346] In at least one embodiment, oneAPI and / or the oneAPI programming model are utilized to interact with various accelerator architectures, GPU architectures, processor architectures, and / or variants thereof. In at least one embodiment, oneAPI includes a set of libraries implementing various functionality. In at least one embodiment, oneAPI includes at least the oneAPI DPC++ library, the oneAPI Math Kernel Library, the oneAPI Data Analytics Library, the oneAPI Deep Neural Network Library, the oneAPI Collective Communications Library, the oneAPI Threading Building Blocks Library, the oneAPI Video Processing Library, and / or variants thereof.

[0347] In at least one embodiment, the oneAPI DPC++ Library, also known as oneDPL, is a library that implements algorithms and functions for accelerating DPC++ kernel programming. In at least one embodiment, oneDPL implements one or more standard template library (STL) functions. In at least one embodiment, oneDPL implements one or more parallel STL functions. In at least one embodiment, oneDPL provides a set of library classes and functions such as parallel algorithms, iterators, function object classes, range-based APIs, and / or their variants. In at least one embodiment, oneDPL implements one or more classes and / or functions of the C++ standard library. In at least one embodiment, oneDPL implements one or more random number generator functions.

[0348] In at least one embodiment, the oneAPI Math Kernel Library, also known as oneMKL, is a library that implements various optimizations and parallelized routines for various mathematical functions and / or operations. In at least one embodiment, oneMKL implements one or more basic linear algebra subprograms (BLAS) and / or linear algebra package (LAPACK) high-density linear algebra routines. In at least one embodiment, oneMKL implements one or more sparse BLAS linear algebra routines. In at least one embodiment, oneMKL implements one or more random number generators (RNGs). In at least one embodiment, oneMKL implements one or more vector mathematics (VM) routines for mathematical operations on vectors. In at least one embodiment, oneMKL implements one or more fast Fourier transform (FFT) functions.

[0349] In at least one embodiment, the oneAPI Data Analytics Library, also known as oneDAL, is a library that implements various data analysis applications and distributed computations. In at least one embodiment, oneDAL implements various algorithms for preprocessing, transformation, analysis, modeling, validation, and decision-making for data analysis in batch, online, and distributed processing modes of computation. In at least one embodiment, oneDAL implements various C++ and / or Java APIs and various connectors to one or more data sources. In at least one embodiment, oneDAL implements DPC++ API extensions to legacy C++ interfaces, enabling GPU usage for various algorithms.

[0350] In at least one embodiment, the oneAPI Deep Neural Network Library, also known as oneDNN, is a library that implements various deep learning functions. In at least one embodiment, oneDNN implements various neural network, machine learning, and deep learning functions, algorithms, and / or their variants.

[0351] In at least one embodiment, the oneAPI Collective Communications Library, also known as oneCCL, is a library that implements various applications for deep learning and machine learning workloads. In at least one embodiment, oneCCL is built on lower-level communication middleware such as the Message Passing Interface (MPI) and libfabric. In at least one embodiment, oneCCL enables a set of optimizations specific to deep learning, such as priority, persistent operation, out-of-order execution, and / or their variants. In at least one embodiment, oneCCL implements various CPU and GPU functions.

[0352] In at least one embodiment, the oneAPI threading building block library, also known as oneTBB, is a library that implements various parallelized processes for various applications. In at least one embodiment, oneTBB is utilized for task-based shared parallel programming on the host. In at least one embodiment, oneTBB implements general parallel algorithms. In at least one embodiment, oneTBB implements concurrent containers. In at least one embodiment, oneTBB implements a scalable memory allocator. In at least one embodiment, oneTBB implements a work-stealing task scheduler. In at least one embodiment, oneTBB implements low-level synchronization primitives. In at least one embodiment, oneTBB is compiler-independent and can be used on various processors such as GPUs, PPUs, CPUs, and / or their variants.

[0353] In at least one embodiment, the oneAPI video processing library, also known as oneVPL, is a library that is utilized to accelerate video processing in one or more applications. In at least one embodiment, oneVPL implements various video decoding, encoding, and processing functions. In at least one embodiment, oneVPL implements various functions for media pipelines on CPUs, GPUs, and other accelerators. In at least one embodiment, oneVPL implements device discovery and selection in media-centric and video analysis workloads. In at least one embodiment, oneVPL implements API primitives for zero-copy buffer sharing.

[0354] In at least one embodiment, the oneAPI programming model utilizes the DPC++ programming language. In at least one embodiment, the DPC++ programming language is a programming language that includes a functionally similar version of the CUDA mechanism for, without limitation, defining device code and distinguishing device code from host code. In at least one embodiment, the DPC++ programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, one or more CUDA programming model operations are implemented using the oneAPI programming model that uses the DPC++ programming language.

[0355] Note that the exemplary embodiments described herein may relate to the CUDA programming model, but the techniques described herein may be utilized with any suitable programming model, such as HIP, oneAPI, and / or variations thereof.

[0356] At least one embodiment of the present disclosure may be described in view of the following clauses.

[0357] 1. A processor comprising one or more circuits for performing a memory barrier operation that causes accesses to memory by multiple groups of threads to occur in the order indicated by the memory barrier operation.

[0358] 2. The processor of clause 1, wherein the memory barrier operation stores synchronization information for multiple groups of threads at a single addressable memory location.

[0359] 3. The processor of clause 2, wherein the synchronization information is stored as a bit field having a separate group of bits indicating synchronization for individual groups of threads.

[0360] 4. The processor according to clause 3, wherein individual bits of a bit field represent a subgroup of threads that can be executed in parallel on a symmetric multiprocessor.

[0361] 5. The processor according to any one of clauses 2 to 4, wherein synchronization information is manipulated using atomic logical operations.

[0362] 6. The processor according to any one of clauses 1 to 6, wherein a memory barrier operation causes a plurality of groups of threads to be executed in parallel.

[0363] 7. The processor according to clause 6, wherein individual groups of a plurality of groups of threads are cooperative thread groups.

[0364] 8. The processor according to clause 7, wherein a cooperative thread group spans a plurality of warps.

[0365] 9. A computer-implemented method including the step of performing a memory barrier operation for causing accesses to memory by a plurality of groups of threads to occur in an order indicated by the memory barrier operation.

[0366] 10. The computer-implemented method according to clause 9, wherein the memory barrier operation stores synchronization information for a plurality of groups of threads in a single addressable memory location.

[0367] 11. The computer-implemented method according to clause 10, wherein the synchronization information is stored as a bit field having a separate group of bits indicating synchronization of individual groups of threads.

[0368] 12. The computer-implemented method according to clause 11, wherein individual bits of the bit field represent a subgroup of threads that can be executed in parallel on a symmetric multiprocessor.

[0369] 13. A computer-implemented method according to any one of clauses 10 to 12, wherein the synchronization information is manipulated using atomic logical operations.

[0370] 14. A computer-implemented method according to any one of clauses 9 to 13, wherein the memory barrier operation causes a plurality of groups of threads to be executed in parallel.

[0371] 15. A computer-implemented method according to clause 14, wherein each of the plurality of groups of threads is a cooperative thread group.

[0372] 16. A computer-implemented method according to clause 15, wherein the cooperative thread group spans a plurality of warps.

[0373] 17. A computer system comprising one or more processors and a memory storing executable instructions, the executable instructions causing, as a result of being executed by the one or more processors, the computer system to perform a memory barrier operation that causes accesses to the memory by a plurality of groups of threads to occur in an order specified by the memory barrier operation.

[0374] 18. A computer system according to clause 17, wherein the memory barrier operation stores synchronization information for the plurality of groups of threads in a single addressable memory location.

[0375] 19. A computer system according to clause 18, wherein the synchronization information is stored as a bit field having a separate group of bits indicating synchronization of individual groups of threads.

[0376] 20. A computer system according to clause 19, wherein individual bits of the bit field represent subgroups of threads that can be executed in parallel on a symmetric multiprocessor.

[0377] 21. A computer system according to any one of clauses 18 to 20, wherein the synchronization information is manipulated using atomic logical operations.

[0378] 22. A computer system according to any one of clauses 17 to 21, wherein the memory barrier operation causes a plurality of groups of threads to be executed in parallel.

[0379] 23. A computer system according to clause 22, wherein each of the plurality of groups of threads is a cooperating thread group.

[0380] 24. A computer system according to clause 23, wherein the cooperating thread group spans a plurality of warps.

[0381] 25. A machine-readable medium storing a set of instructions, which, when executed by one or more processors, cause the one or more processors to perform a memory barrier operation that causes accesses to memory by a plurality of groups of threads to occur in the order specified by the memory barrier operation.

[0382] 26. A machine-readable medium according to clause 25, wherein the memory barrier operation stores synchronization information for a plurality of groups of threads in a single addressable memory location.

[0383] 27. A machine-readable medium according to clause 26, wherein the synchronization information is stored as a bit field having a separate group of bits that indicate synchronization for individual groups of threads.

[0384] 28. A machine-readable medium according to clause 27, wherein individual bits of the bit field represent sub-groups of threads that can be executed in parallel on a symmetric multiprocessor.

[0385] 29. A machine-readable medium according to any one of clauses 26 to 28, wherein the synchronization information is manipulated using atomic logical operations.

[0386] 30. A machine-readable medium according to any one of clauses 25 to 29, wherein the memory barrier operation causes a plurality of groups of threads to be executed in parallel.

[0387] 31. A machine-readable medium according to clause 30, wherein each group of the plurality of groups of threads is a cooperating thread group.

[0388] 32. A machine-readable medium according to clause 31, wherein the cooperating thread group spans a plurality of warps.

[0389] Other variations are within the scope of the present disclosure. Accordingly, while the disclosed techniques are capable of various modifications and alternative constructions, some of those exemplary embodiments are shown in the drawings and described in detail above. However, it is to be understood that there is no intention to limit the present disclosure to the particular one or more disclosed forms, and on the contrary, it is intended to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure as defined in the appended claims.

[0390] In the context of describing the disclosed embodiments (in particular, in the context of the following claims), the use of the terms "a", "an", and "the", as well as similar indicators, should be construed to cover both the singular and the plural, unless otherwise stated in this specification or clearly contradicted by the context, and should not be construed as a definition of the terms. The terms "comprising", "having", "including", and "containing" should be construed as open-ended terms (meaning "including, but not limited to") unless otherwise stated. The term "connected" should be construed, when unmodified and referring to a physical connection, to mean something that is either partially or fully enclosed within, attached to, or joined to another thing, even if there is something intervening. The recitation of a range of values herein is merely intended to serve as a concise way of referring individually to each separate value that falls within the range, unless otherwise stated in this specification and unless each separate value is not incorporated herein as if it were individually recited herein. The use of the term "set" (e.g., "a set of items") or "subset" should be construed, unless otherwise stated or contradicted by the context, as a non-empty collection comprising one or more members. Further, unless otherwise stated or contradicted by the context, the term "subset" of a corresponding set does not necessarily refer to a strict subset of the corresponding set, and the subset and the corresponding set may be equal.

[0391] Conjunctive terms such as the phrase "at least one of A, B, and C" or "at least one of A, B, and C" are understood in the context generally used to indicate that, unless otherwise specifically stated or clearly negated by context, items, terms, etc. can be either any one of A or B or C, or any non-empty subset of the set of A, B, and C. For example, in an illustrative example of a set having three members, the conjunctive phrases "at least one of A, B, and C" and "at least one of A, B, and C" refer to any one of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive terms do not generally imply that some embodiments require the presence of at least one of each of at least one of A, at least one of B, and at least one of C. Further, unless otherwise stated or not apparent from the context, the term "plurality" indicates a plural state (e.g., "a plurality of items" indicates multiple items). The number of items that are plural is at least two, but may be more when so indicated either explicitly or by context. Further, unless otherwise stated or not apparent from the context, the phrase "based on" means "based at least in part on" and does not mean "based only on".

[0392] The operations of the processes described in this specification may be performed in any suitable order, unless otherwise stated in this specification or clearly precluded by the context. In at least one embodiment, a process, such as a process described in this specification (or variations and / or combinations thereof), is performed under the control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) executed colle...

Claims

Claim 1 A memory barrier operation, comprising one or more circuits for performing a memory barrier operation to cause access to memory by a plurality of groups of threads to occur in an order indicated by the memory barrier operation, wherein the memory barrier operation stores synchronization information for the plurality of groups of threads in a single addressable memory location, wherein the synchronization information is stored as a bit field having a separate group of bits indicating synchronization of individual groups of threads, wherein individual bits of the bit field represent sub-groups of threads that can be executed in parallel on a symmetric multiprocessor, a processor. Claim 2 The processor according to claim 1, wherein the synchronization information is manipulated using atomic logical operations. Claim 3 The processor according to claim 1, wherein the memory barrier operation causes the plurality of groups of threads to be executed in parallel. Claim 4 The processor according to claim 3, wherein individual groups of the plurality of groups of threads are cooperating thread groups. Claim 5 The processor according to claim 4, wherein the cooperating thread groups span a plurality of warps. Claim 6 A memory barrier operation, comprising the step of performing a memory barrier operation to cause access to memory by a plurality of groups of threads to occur in an order indicated by the memory barrier operation, wherein the memory barrier operation stores synchronization information for the plurality of groups of threads in a single addressable memory location, wherein the synchronization information is stored as a bit field having a separate group of bits indicating synchronization of individual groups of threads, wherein individual bits of the bit field represent sub-groups of threads that can be executed in parallel on a symmetric multiprocessor, a computer implemented method. Claim 7 The computer implemented method according to claim 6, wherein the synchronization information is manipulated using atomic logical operations. Claim 8 The computer implemented method according to claim 6, wherein the memory barrier operation causes the plurality of groups of threads to be executed in parallel. Claim 9 The computer-implemented method of claim 8, wherein each of the plurality of groups of threads is a cooperating thread group.

10. The computer-implemented method of claim 9, wherein the cooperating thread group spans a plurality of warps.

11. A computer system comprising one or more processors and a memory storing executable instructions, wherein the executable instructions, when executed by the one or more processors, cause the computer system to perform a memory barrier operation that causes accesses to the memory by a plurality of groups of threads to occur in an order specified by the memory barrier operation. The memory barrier operation stores synchronization information for the plurality of groups of threads in a single addressable memory location. The synchronization information is stored as a bit field having a separate group of bits indicating synchronization of individual groups of threads. A computer system, wherein individual bits of the bit field represent subgroups of threads that can be executed in parallel on a symmetric multiprocessor.

12. The computer system of claim 11, wherein the synchronization information is manipulated using atomic logical operations.

13. The computer system of claim 11, wherein the memory barrier operation causes the plurality of groups of threads to execute in parallel.

14. The computer system of claim 13, wherein each of the plurality of groups of threads is a cooperating thread group.

15. The computer system of claim 14, wherein the cooperating thread group spans a plurality of warps.

16. A machine-readable medium storing a set of instructions that, when implemented by one or more processors, cause the one or more processors to perform a memory barrier operation that causes accesses to the memory by a plurality of groups of threads to occur in an order specified by the memory barrier operation. The memory barrier operation stores synchronization information for the plurality of groups of threads in a single addressable memory location. The synchronization information is stored as a bit field having a separate group of bits that indicate synchronization of individual groups of threads, wherein individual bits of the bit field represent sub-groups of threads that can be executed in parallel on a symmetric multiprocessor, a machine-readable medium. **Claim 17** The machine-readable medium according to claim 16, wherein the synchronization information is manipulated using atomic logical operations. **Claim 18** The machine-readable medium according to claim 16, wherein the memory barrier operation causes the plurality of groups of threads to be executed in parallel. **Claim 19** The machine-readable medium according to claim 18, wherein individual groups of the plurality of groups of threads are cooperative thread groups. **Claim 20** The machine-readable medium according to claim 19, wherein the cooperative thread groups span a plurality of warps.

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