Fault-protected signal splitter device

Abstract

A system is disclosed herein. The system includes a splitter board. The splitter board includes a microprocessor, a converter, and a bypass relay. The converter includes an analog-to-digital circuit and a digital-to-analog circuit. The bypass relay is configurable between a first state and a second state. In the first state, the bypass relay is configured to direct an input signal to the converter. The converter converts the input signal to a converted input signal and splits the converted input signal into a first portion and a second portion. The first portion is directed to the microprocessor. The second portion is directed to an output port of the splitter board for a downstream process. In the second state, the bypass relay is configured to cause the input signal to bypass the converter. The bypass relay directs the input signal to an output port of the splitter board for a downstream process.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of U.S. Application No. 63 / 261,071, filed Sep. 10, 2021, and U.S. Application No. 17 / 646,247, filed Dec. 28, 2021, which are hereby incorporated by reference in their entirety.

[0002] The present disclosure generally relates to signal splitting systems and methods of operating the same.

Background Art

[0003] Signal splitters are often used in the manufacture for measurement and control applications where a single analog signal needs to be sent to multiple sources. A signal splitter is generally configured to receive a single input and split that single input into a primary output and a secondary output.

Summary of the Invention

Means for Solving the Problems

[0004] In some embodiments, a system is disclosed herein. The system includes a converter including analog-digital and digital-analog circuits, a bypass relay coupled to the converter, the bypass relay being configurable between a first state and a second state, and a microprocessor coupled to the converter and the bypass relay, the microprocessor being configured to switch the bypass relay between the first state and the second state. The splitter board includes: in the first state, the bypass relay directs an input signal to the converter, the converter converts the input signal into a converted input signal, splits the converted input signal into a first portion and a second portion, the microprocessor multiplies the first portion by a calibration factor, returns the first portion to the converter for output at an output port of the splitter board for a downstream process, and outputs the second portion to an external server device; and in the second state, the bypass relay bypasses the converter around the input signal and directs the input signal to the output port of the splitter board for the downstream process.

[0005] In some embodiments, a system is disclosed herein. The system includes a mother board including an input relay configurable between a first position and a second position, an input pad communicating with the input relay, a switch configurable between an open position and a closed position, an output relay configurable between a first position and a second position, and an output pad communicating with the output relay, and a daughter board configured to connect to the mother board. When the daughter board is connected to the mother board, the input relay switches from the open position to the closed position, as a result, power is supplied to the input relay and the output relay, causing the input relay to switch from the first position to the second position and the output relay to switch from the first position to the second position. In the second position, the input pad provides an input signal from the mother board to the daughter board, and the output pad receives an output signal from the daughter board.

[0006] In some embodiments, a method is disclosed herein. The method is for a microprocessor to activate a splitter board, which includes energizing a bypass relay of the splitter board. When energized, the bypass relay directs an input signal to a converter, which is configured to convert the input signal into a converted signal and split the converted signal into a first portion and a second portion; to detect, by the microprocessor, that at least one component of the splitter board has failed; and based on the detection, to de-energize the bypass relay by the microprocessor, which includes bypassing the converter around the input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] As the above features of the present disclosure can be understood in detail, a more detailed description of the present disclosure, briefly summarized above, may be made by referring to the embodiments, some of which are shown in the accompanying drawings. It should be noted that the accompanying drawings show only typical embodiments of the present disclosure, and thus the present disclosure should not be regarded as limited in scope as it may admit other equally effective embodiments.

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[0027] For ease of understanding, where possible, the same reference numerals are used to represent the same elements common to the figures. It is assumed that elements disclosed in one embodiment may be beneficially utilized in other embodiments without specific recitation.

Best Mode for Carrying Out the Invention

[0028] Signal splitters are often used in manufacturing, measurement, and control applications where a single analog or digital signal is sent to multiple sources. Generally, a signal splitter receives a primary input signal and outputs a primary output signal and a secondary output signal. Typically, the primary output signal may be essential for a specific purpose, such as controlling a particular process, while the secondary output signal may not be as essential for a particular purpose. For example, the primary output signal can control the process, while the secondary output signal can be used to monitor the process. The process can continue without the secondary output, but generally cannot continue without the primary output. Due to the indispensability of the primary output, the signal splitter must continue to output the primary signal even if the signal splitter fails.

[0029] Analog splitters are usually used to split a single analog input into multiple analog outputs. An analog-to-digital converter (ADC) is available to output a digital signal from the analog input. Similarly, a digital-to-analog converter (DAC) is available to output an analog signal from the digital input.

[0030] Conventional signal splitters and analog splitters have useful applications, but such devices cannot receive an analog signal and provide multiple analog outputs. Similarly, there is no device or apparatus that can receive an analog input and generate multiple digital outputs.

[0031] One or more of the techniques provided herein provide solutions to limitations of conventional devices. For example, one or more of the techniques described herein include methods and apparatuses for inputting multiple analog signals onto a single board and outputting mirrored analog and digital signals. One or more of the techniques may allow multiple boards to be connected, such that the multiple boards may be connected to combine multiple digital signals into the digital output of the signals. Such an approach can provide fault protection in the event that a board component associated with a particular input, such as an ADC / DAC, fails, in which case a particular input signal can bypass the active signal circuit and be passed directly to the output of that signal while all other input signals continue to be processed through the ADC / DAC circuit.

[0032] In some embodiments, the present disclosure further includes one or more techniques that allow input channels to be calibrated without interrupting the primary output channel. For example, one or more of the techniques provided herein allow an input signal to be disconnected from the ADC and the input signal to the ADC to be replaced with a calibration signal. Since the DAC can continue to output the buffered signal to the analog signal output during calibration, the ADC can be calibrated without interfering with the signal output. The active signal circuit may be re-established through the ADC / DAC after calibration.

[0033] In some embodiments, the input signal may be disconnected from the ADC and sent directly to the analog output. The input to the ADC may be replaced with a calibration signal. Since the analog signal output can continue during calibration, the ADC can be calibrated without interfering with the signal output. The active signal circuit may be re-established through the ADC / DAC after calibration.

[0034] In some embodiments, one or more of the techniques provided herein may allow a calibration signal to be continuously sent to a second channel C2 of the ADC. For example, an input signal may be sent to a first channel C1 of the ADC. The second channel C2 of the ADC may calculate a calibration coefficient. In some embodiments, the second channel C2 may calculate the calibration coefficient frequently, such as every minute, every hour, every day, etc. If the coefficient differs from the previous calibration by a specified amount, the new coefficient may be immediately provided to the first channel C1.

[0035] In some embodiments, the calibration signal may be external and connected when the circuit is being calibrated. In some embodiments, the calibration signal may be internal. In embodiments where the calibration signal is internal, the calibration signal may be pre-identified and selected to enable gain and offset calibration. In some embodiments, the firmware may be programmed to periodically (e.g., daily, weekly, monthly, etc.) check and calibrate the input. In some embodiments, the calibration may be initiated on demand through a server or a dedicated controller. In some embodiments, the internal calibration may include multiple circuits to enable full-range calibration of the signal input. This may include zero (e.g., the lowest expected signal) and span (e.g., the highest expected signal).

[0036] In some embodiments, one or more of the techniques disclosed herein provide software or firmware techniques for calibrating a system. In some embodiments, such as for external calibration, the system may allow selection of the input signal to be calibrated. In some embodiments, the user may be prompted for the selected zero and span inputs. In some embodiments, the calibration data may be automatically stored on a splitter board.

[0037] In some embodiments, such as for internal calibration, the system may allow time intervals at which automatic calibration can be performed. In some embodiments, the system may provide means for recalibrating internal calibration standards. In some embodiments, the system may automatically set zero and span inputs according to selected internal selections.

[0038] In some embodiments, the system may allow the user to encode or encrypt data so that the digital date is obfuscated from unintended users. In some embodiments, data from auxiliary boards and / or host boards may be encoded or encrypted.

[0039] In some embodiments, the system may allow a board or board output to be authenticated. The host board and auxiliary boards may be used in series, and the host board may be connected to a server. The host and auxiliary boards may include authentication information such that they can be permitted and used in a specified configuration. For example, authentication may refer to a process that ensures that a device used with a splitter board is recognized by the splitter board's firmware and the server's software and that the device is permitted to be used with the splitter board. In some embodiments, a further function of the authentication process may include alignment such that either the host or auxiliary board can only be connected to a specified connection board. In some embodiments, the system may provide a method for verifying the integrity of input signals.

[0040] FIG. 1 is a block diagram showing a splitter board 120 according to an exemplary embodiment. The splitter board 120 may include functions associated with a host splitter board and an auxiliary board. As shown, the splitter board 120 may include at least one input signal IS1 and at least one output signal OS1. The splitter board 120 may further include a second input signal IS2 and a second output signal OS2. As will be appreciated by those skilled in the art, the splitter board may include an nth input signal IS n and an nth output signal OS n . For simplicity of explanation and illustration, FIG. 1 includes input signals IS1 and IS2 and output signals OS1 and OS2, but the remaining description may refer to only a single input signal and a single output signal in some cases. In some embodiments, the input signal can be an analog signal (e.g., current / voltage). In some embodiments, the input signal can be a digital state signal (TTL or digital I / O). In some embodiments, the input signal IS1 may represent a plurality of signals. Similarly, the output signal OS1 may represent a plurality of output signals. Generally, each input signal (e.g., IS1, IS2,..., IS n ) may represent n input signals, and each output signal (e.g., OS1, OS2,..., OS n ) may represent m output signals. In some embodiments, n = m. In some embodiments, n > m.

[0041] Annotations for the components of the splitter board 120 distinguish the active circuits for each signal by using the notations "a" and "b". For example, the converter for the first signal may be 160a, and the converter for the second signal may be 160b.

[0042] The splitter board 120 may be configured to perform the functions of both the host board and the auxiliary board. The splitter board 120 may include various electronic devices disposed thereon. For example, the splitter board 120 may include an input relay 136a, a bypass relay 131a, an output relay 132a, and a converter 160a.

[0043] An external analog signal IS1 may be connected to the splitter board 120. In some embodiments, the external analog signal IS1 may represent one or more wires depending on the type of signal. For example, in some embodiments, IS1 may represent a thermocouple signal with a two-wire input. Although FIG. 1 shows a single "line" input for IS1, as those skilled in the art will understand, a particular input may consist of multiple lines or wires. The external analog signal IS1 may be coupled or provided to the input relay 136a. In some embodiments, the external analog signal IS1 may be coupled or provided to the input relay 136a via a trace 133a.

[0044] A trace 138a may connect the input relay 136a to the bypass relay 131a. The bypass relay 131a may be configured to switch the input signal IS1 towards the converter 160a or away from the ADC / DAC 160a. The bypass relay 131a may toggle between an active state and a fault state depending on the state of the converter 160a.

[0045] In some embodiments, the active state may refer to a situation where the splitter board 120 is operating properly. The splitter board 120 is operating properly when there is power to the splitter board 120 and all components of the splitter board 120 are operating. When the splitter board 120 is operating properly, the input analog signal IS1 may be split by the converter 160a and converted into an output analog signal OS1 and a digital output signal.

[0046] In some embodiments, the fault state may refer to a situation in which a failure has occurred. In some embodiments, the failure may be a full board failure. The full board failure may occur when there is no power to the splitter board 120 and all outputs are absent. In some embodiments, the failure may be a single component failure. The single component failure may occur when a component of the splitter board 120 fails. For example, the converter 160a or the converter 160b fails.

[0047] When in the active state, the bypass relay 131a may be in a first state, in which the bypass relay 131a directs the input signal IS1 towards the converter 160a. When in the fault state, the bypass relay 131a may be in a second state, in which the bypass relay 131a directs the input signal IS1 towards the output relay 132a, bypassing the converter 160a.

[0048] The trace 140a may connect the bypass relay 131a to the converter 160a. In some embodiments, although not shown, the splitter board 120 may include an electronic device or other component between the bypass relay 131a and the converter 160a. For example, the splitter board 120 may include an amplifier between the input relay 136a and the converter 160a to amplify the signal before it is received by the converter 160a.

[0049] Converter 160a may be configured to split an incoming signal and convert the incoming signal from one format (e.g., digital or analog) to another format (e.g., digital or analog). For example, converter 160a may consist of two functions, namely, analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC). Converter 160a may convert input signal IS1 from analog to digital or from digital to analog. For example, converter 160a may split input signal IS1 into a first portion and a second portion. Converter 160a may convert both portions of the input signal from an analog signal to a digital signal. In the active state, converter 160a may provide the first portion of the digital signal and the second portion of the digital signal to microprocessor 180. Microprocessor 180 may be configured to multiply a calibration factor by the first portion of the digital signal. After the calibration factor is multiplied by the first portion of the digital signal, microprocessor 180 may return the first portion of the digital signal to converter 160a, and converter 160a may convert the digital signal back to an analog signal (however, the digital signal to be converted back to an analog signal is multiplied by a calibration factor). The analog signal may be provided to relay 132a via trace 145a for output. Although not shown, converter 160a may provide a plurality of output signals OS n In some embodiments, converter 160a may direct a plurality of digital output signals to a plurality of microprocessors 180.

[0050] As shown, trace 170 may connect converter 160a to microprocessor 180. Trace 170 may communicate information with microprocessor 180. Trace 170 may communicate information with converter 160a. In some embodiments, microprocessor 180 may be configured to communicate with and / or control converter 160a. For example, microprocessor 180 may be configured to execute firmware that controls the logic of one or more of converter 160a, input relay 136a, bypass relay 131a, and output relay 132a. In some embodiments, microprocessor 180 may be configured to read and control all signals, and as a result, microprocessor 180 may provide logic and functionality to fault detection module 190a.

[0051] Converter 160a may include a fault detection module 190a. The fault detection module 190a may represent a circuit configured to check whether converter 160a is in an active state. The fault detection module 190a may be read and controlled by the microprocessor 180. The fault detection module 190a may be configured to detect faults in various ways. In some embodiments, the fault detection module 190a may detect faults using general relay logic. For example, the bypass relay 131a may be in an energized switching position (e.g., a first state) when there is power supplied to the splitter board 120. If there is no power, the bypass relay 131a may be de-energized (e.g., a second state), and the output from the bypass relay 131a may switch to a fault signal 135a. In some embodiments, during a power failure, all converters (e.g., converter 160a, converter 160b, converter 160n, etc.) on the splitter board 120 may switch to a fault state. In some embodiments, the built-in code logic of the microprocessor 180 may be used to detect individual converter circuit faults. For example, some converters (e.g., converter 160a) may include registers, which can change during active conversion. The microprocessor 180 may check the registers to ensure that the registers are changing progressively.

[0052] In some embodiments, converter 160a may include digital input / output. In such embodiments, converter 160a may be configured to generate a digital output. When in an active state, the signal can be high. When converter 160a fails, the signal goes low.

[0053] In the fault state, communication from the converter 160a to the microprocessor 180 fails. Instead, the bypass relay 131a may output the fault signal 135a to the output relay 132a. The output relay 132a may be configured to receive the fault signal 135a and output the output signal OS1. In this way, even when the converter 160a is in the fault state, the original input signal IS1 can pass through.

[0054] In some embodiments, the output relay 132a and the input relay 136a may represent logic relays. For example, in some embodiments, the output relay 132a and the input relay 136a may represent a single multi-throw physical relay. In some embodiments, the output relay 132a and the input relay 136a may represent separate relays having a common coil circuit. In some embodiments, the output relay 132a and the input relay 136a may represent separate relays having software control of individual coil circuits.

[0055] As shown in the illustration, when in the active state, the converter 160a outputs a digital signal to the microprocessor 180 via the trace 170. The microprocessor 180 may output one or more digital signals based on the input digital signal. For example, as shown in the illustration, the microprocessor 180 may output a first digital signal to the server 199 via the trace 184 through the port 185. In some embodiments, the microprocessor 180 may encrypt the first digital signal before providing the digital signal to the server 199. In some embodiments, the microprocessor 180 may also output a digital signal to the dedicated controller 101 via the trace 195 through the connector 196. In some embodiments, the microprocessor 180 may also output a digital signal to an auxiliary board via the trace 182 through a port 183 that connects the auxiliary board (not shown) to the splitter board 120. In some embodiments, the port 183 may include one or more wires for connecting the splitter board 120 to the auxiliary board. In some embodiments, the microprocessor 180 may also output a digital signal to an auxiliary board (not shown) through the port 187. In some embodiments, the signal may be encrypted and / or authenticated by the microprocessor 180 before being provided to the auxiliary board. Alignment may be required so that the auxiliary boards can be daisy-chained in a specific order. In this way, the splitter board 120 may include functions associated with both the host splitter board 120 and the auxiliary board.

[0056] As shown in the illustration, the splitter board 120 may include an additional set of components. For example, as shown in the illustration, the splitter board 120 includes two sets of components (distinguished by "a" and "b" following each reference number). As will be understood by those skilled in the art, the splitter board 120 may include a single set of components or n sets of components. For the sake of simplicity of explanation, two sets of components are shown in FIG. 1.

[0057] The splitter board 120 may further include a second set of components. The second set of components includes an input relay 136b, a bypass relay 131b, an output relay 132b, and a converter 160b.

[0058] An external analog signal IS2 may be connected to the splitter board 120. In some embodiments, the external analog signal IS2 may represent one or more wires depending on the type of signal. For example, in some embodiments, IS2 may represent a thermocouple signal that is a two-wire input. Although FIG. 1 shows a single "line" input for IS2, as will be understood by those skilled in the art, a particular input may consist of multiple lines or wires. The external analog signal IS2 may be coupled or provided to the input relay 136b. In some embodiments, the external analog signal IS2 may be coupled or provided to the input relay 136b via a trace 133b.

[0059] A trace 138b may connect the input relay 136b to the bypass relay 131b. The bypass relay 131b may be configured to switch the input signal IS2 towards the converter 160b or away from the ADC / DAC 160b. The bypass relay 131b may toggle between an active state and a fault state depending on the state of the converter 160b.

[0060] In some embodiments, the active state may refer to a situation where the splitter board 120 is operating properly. The splitter board 120 is operating properly when there is power to the splitter board 120 and all components of the splitter board 120 are functioning. When the splitter board 120 is operating properly, the input analog signal IS2 may be split by the converter 160b and converted into an output analog signal OS2 and a digital output signal.

[0061] In some embodiments, the fault state may refer to a situation in which a failure has occurred. In some embodiments, the failure may be a full-board failure. The full-board failure may occur when there is no power supply to the splitter board 120 and all outputs are absent. In some embodiments, the failure may be a single-component failure. The single-component failure may occur when a component of the splitter board 120 fails. For example, the converter 160a or the converter 160b fails.

[0062] When in the active state, the bypass relay 131b may be in a first state, in which the bypass relay 131b directs the input signal IS2 towards the converter 160b. When in the fault state, the bypass relay 131b may be in a second state, in which the bypass relay 131b directs the input signal IS2 towards the output relay 132b, bypassing the converter 160b.

[0063] The trace 140b may connect the bypass relay 131b to the converter 160b. In some embodiments, although not shown, the splitter board 120 may include an electronic device or other component between the bypass relay 131b and the converter 160b. For example, the splitter board 120 may include an amplifier between the input relay 136b and the converter 160b to amplify the signal before it is received by the converter 160b.

[0064] Converter 160b may be configured to split an incoming signal and convert the incoming signal from one format (e.g., digital or analog) to another format (e.g., digital or analog). For example, converter 160b may consist of two functions, namely, analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC). Converter 160b may convert input signal IS2 from analog to digital or from digital to analog. For example, converter 160b may split input signal IS2 into a first portion and a second portion. Converter 160b may convert both portions of the input signal from an analog signal to a digital signal. In an active state, converter 160b may provide the first portion of the digital signal and the second portion of the digital signal to microprocessor 180. Microprocessor 180 may be configured to multiply a calibration factor by the first portion of the digital signal. After the calibration factor is multiplied by the first portion of the digital signal, microprocessor 180 may return the first portion of the digital signal to converter 160b, and converter 160b may convert the digital signal to return it to an analog signal (however, the digital signal to be converted to return it to an analog signal is multiplied by a calibration factor). The analog signal may be provided to relay 132b via trace 145b for output. Although not shown, converter 160b may provide a plurality of output signals OS n . In some embodiments, converter 160b may direct a plurality of digital output signals to a plurality of microprocessors 180.

[0065] As shown, trace 170 may connect converter 160b to microprocessor 180. Trace 170 may communicate information with microprocessor 180. Trace 170 may communicate information with converter 160b. In some embodiments, microprocessor 180 may be configured to communicate with and / or control converter 160b. For example, microprocessor 180 may be configured to execute firmware that controls the logic of one or more of converter 160b, input relay 136b, bypass relay 131b, and output relay 132b. In some embodiments, microprocessor 180 may be configured to read and control all signals, and as a result, microprocessor 180 may provide logic and functionality to fault detection module 190b.

[0066] Converter 160b may include a fault detection module 190b. The fault detection module 190b may represent a circuit configured to check whether the converter 160b is in an active state. The fault detection module 190b may be read and controlled by the microprocessor 180. The fault detection module 190b may be configured to detect faults in various ways. In some embodiments, the fault detection module 190b may use general relay logic to detect faults. For example, the bypass relay 131b may be in an energized switching position (e.g., a first state) when there is power supplied to the splitter board 120. In the absence of power, the bypass relay 131b may be de-energized (e.g., a second state), and the output from the bypass relay 131b may switch to a fault signal 135b. In some embodiments, during a power failure, all converters (e.g., converter 160a, converter 160b, converter 160n, etc.) on the splitter board 120 may switch to a fault state. In some embodiments, the embedded code logic of the microprocessor 180 may be used to detect individual converter circuit faults. For example, some converters (e.g., converter 160b) may include registers, which can change during active conversion. The microprocessor 180 may check the registers to ensure that the registers are changing progressively.

[0067] In some embodiments, the converter 160b may include digital input / output. In such embodiments, the converter 160b may be configured to generate a digital output. When in an active state, the signal can be high. When the converter 160b fails, the signal goes low.

[0068] In a fault state, communication from the converter 160b to the microprocessor 180 fails. Instead, the bypass relay 131b may output the fault signal 135b to the output relay 132b. The output relay 132b may be configured to receive the fault signal 135b and output an output signal OS2.

[0069] In some embodiments, output relay 132b and input relay 136b may represent logic relays. For example, in some embodiments, output relay 132b and input relay 136b may represent a single multi-throw physical relay. In some embodiments, output relay 132b and input relay 136b may represent separate relays having a common coil circuit. In some embodiments, output relay 132b and input relay 136b may represent separate relays having software control of individual coil circuits.

[0070] As shown, when in the active state, converter 160b outputs a digital signal to microprocessor 180 via trace 170. Microprocessor 180 may output one or more digital signals based on the input digital signal. For example, as shown, microprocessor 180 may output a digital signal to server 199 via trace 184 through port 185. In some embodiments, microprocessor 180 may encrypt the digital signal before providing it to server 199. In some embodiments, microprocessor 180 may also output a digital signal to a dedicated controller via trace 195 through connector 196. In some embodiments, microprocessor 180 may also output a digital signal to an auxiliary board via trace 182 through port 183 that connects an auxiliary board (not shown) to splitter board 120. In some embodiments, port 183 may include one or more wires for connecting splitter board 120 to the auxiliary board. In some embodiments, the signal may be encrypted and / or authenticated by microprocessor 180 before being provided to the auxiliary board. Alignment may be required so that auxiliary boards can be daisy chained in a specific order.

[0071] When splitter board 120 includes a plurality of sets of components (e.g., a-components and b-components), microprocessor 180 may receive digital outputs from both transducer 160a and transducer 160b. In some embodiments, microprocessor 180 may still receive a digital output from the transducer that remains active, such as when either transducer 160a or transducer 160b fails. When both transducer 160a and transducer 160b are active, microprocessor 180 may aggregate data from both transducer 160a and transducer 160b. For example, microprocessor 180 may aggregate the digital output from transducer 160a with the digital output from transducer 160b. In such embodiments, microprocessor 180 may provide the aggregated data to server 199 via trace 184 through port 185. Similarly, microprocessor 180 may provide the aggregated data to a dedicated controller via trace 195 through connector 196 and provide a digital signal to an auxiliary board via trace 182 through port 183.

[0072] In some embodiments, splitter board 120 may further include an internal calibration circuit. The internal calibration circuit includes a calibration relay 141, a calibration device 142, and a calibration signal 143. In some situations, it may be necessary or useful to calibrate one or more transducers (e.g., transducer 160a and / or transducer 160b) on splitter board 120. For example, the ADCs of transducer 160a and / or transducer 160b may be calibrated. During the calibration process, input signal IS1 and / or IS2 may be disconnected, and transducer 160a and / or transducer 160b may be placed in a calibration state. For example, as shown, input signal IS1 may be provided to input relay 136a, which may pass the input signal to calibration relay 141 via trace 137a. Similarly, input signal IS2 may be provided to input relay 136b, which may pass the input signal to calibration relay 141 via trace 137b.

[0073] For simplicity of explanation, the following description only explains the calibration for the a-component. As will be understood by those skilled in the art, such a process is also executable for the b-component, or more generally, for the n-components of the splitter board 120.

[0074] The calibration device 142 may be configured to calibrate the transducer 160a. The calibration device 142 may include a plurality of signals that can be used to calibrate the ADC of the calibration device 142. In some embodiments, the calibration signals may include a low reference signal LRS and a high reference signal HRS. The LRS may represent the lowest expected analog signal, and the HRS may represent the highest expected analog signal. The number of reference signals may vary depending on the linearity of the input signal. The calibration device 142 may output a calibration signal 143 to the calibration relay 141. In some embodiments, the microprocessor 180 may include logic for changing the calibration signal 143 from LRS to HRS, or from HRS to LRS. The microprocessor 180 may control the calibration relay 141 so that the output calibration signal is sent to the desired ADC. In this way, the calibration circuit can ensure that the measured signal accurately reflects the correct value.

[0075] FIG. 2 is a block diagram showing a splitter board 200 according to an exemplary embodiment. The splitter board 200 may have an architecture similar to that of the splitter board 120. The same reference numbers are used to easily show the components that the splitter board 200 has in common with the splitter board.

[0076] The splitter board 200 may represent the first, or primary board, in a chain of auxiliary boards. For example, the splitter board 200 may be configured to aggregate data from the auxiliary boards via port 183 and communicate the data to server 199 via port 185. In some embodiments, server 199 may provide inputs and instructions to the splitter board 200. In some embodiments, server 199 may provide inputs and instructions to any of the auxiliary boards via the splitter board 200. The splitter board 200 may be different from the splitter board 120 in that it may be connected to server 199 only through trace 184 and port 185. The splitter board 200 may include only one port 183.

[0077] In other words, the splitter board 200 may be a dedicated host splitter board, whereas the splitter board 120 may include the functions of both a host splitter board and an auxiliary splitter board.

[0078] FIG. 3 is a block diagram showing an auxiliary board 300 according to an exemplary embodiment. The auxiliary board 300 may have an architecture similar to that of the splitter board 120. The same reference numerals are used to easily indicate the components that the auxiliary splitter board 300 has in common with the splitter board 120.

[0079] The auxiliary board 300 may provide a concatenation function to other boards, or a plurality of other auxiliary boards, where applicable. As described above, a plurality of auxiliary boards may be daisy-chain connected together with the first auxiliary board directly connected to the splitter board 200 or the splitter board 120.

[0080] As shown in the figure, the auxiliary board 300 may not be directly connected to the server 199. Instead, the auxiliary board 300 may be configured to connect to two other boards through ports 183 and 187, respectively. For example, if the auxiliary board 300 is the first auxiliary board in a series of auxiliary boards, either port 183 or port 187 is connected to the splitter board 200. The remaining port (port 183 or port 187) may be connected to another auxiliary board. In some embodiments, when connected and used with the splitter board 200 or another auxiliary board, the auxiliary board 300 may be authenticated to permit the use of the board. The auxiliary board 300 may be coupled to the splitter board 200 or another auxiliary board via port 187. The auxiliary board 300 may also be coupled to another auxiliary board via port 183.

[0081] Figure 4 is a block diagram showing a splitter board 120 and an auxiliary board 300 arranged in a daisy chain configuration 400 according to an exemplary embodiment.

[0082] As shown in the figure, port 183 of the splitter board 120 may be connected to port 187 of the auxiliary board 300. In some embodiments, port 183 may be connected to port 187 through any means, including but not limited to, a Universal Serial Bus (USB), serial, Modbus, Ethernet, or other well-known communication means. Accordingly, the output from the auxiliary board 300 may be provided to the splitter board.

[0083] The host splitter board 120 may provide an output from the auxiliary board 300 to the server 199. The splitter board may be connected to the server 199 through port 185. In some embodiments, port 185 may be connected to the server 199 through any means, including but not limited to USB, serial, Modbus, Ethernet, or other well-known communication means. As shown, the input from the auxiliary board 300 may be provided to the microprocessor 180 via trace 182. In some embodiments, the microprocessor 180 may simply pass a signal from the auxiliary board 300 to the server 199. In some embodiments, the microprocessor 180 may aggregate the signal from the auxiliary board 300 with any other input signals from other auxiliary boards or signals generated by the host splitter board 120.

[0084] Figure 5 is a block diagram showing the splitter board 120 when the splitter board 120 is in an active state, according to an exemplary embodiment.

[0085] For simplicity of explanation, the signal path through the splitter board 120 is emphasized. In the active state, the input signal IS1 flows through the relay 136a and via the trace 138a to the bypass relay 131a. The relay 136a is in the power-off position. When commanded by the microprocessor 180, the relay 136a may be energized, such as when the transducer 160a is to be calibrated. When in the power-off position, the signal may pass through the relay 136a and via the trace 138a to the bypass relay 131a. The bypass relay 131a is shown in the energized position. When energized, the signal is passed to the transducer 160a through the active circuit of the relay 136a. In some embodiments, the active circuit of the bypass relay 131a may include signal conditioning such as amplification. The transducer 160a splits the input signal and converts the split input signal into a digital signal. For example, the ADC of the transducer 160a may convert the analog input signal into a digital signal. The split digital input signal is provided to the microprocessor 180 via the trace 170. The microprocessor 180 may interpret the signal and send commands to one or more outputs (such as the server 199, the controller 101, etc.). In some embodiments, the microprocessor 180 may multiply the first digital signal by a calibration factor to ensure the accuracy of the signal. The microprocessor 180 may communicate the calibrated digital signal to the DAC of the transducer 160a. The transducer 160a may convert the calibrated digital signal into an analog signal. The transducer 160a may output the analog signal to the output relay 132a via the trace 145a. The analog signal may be available to an external device via the OS1.

[0086] Similarly, the input signal IS2 flows through relay 136b and via trace 138b to bypass relay 131b. Relay 136b is in the power-off position. Relay 136b may be energized when commanded by microprocessor 180, such as when transducer 160b is to be calibrated. When in the power-off position, the signal may pass through relay 136b and via trace 138b to bypass relay 131b. Bypass relay 131b is shown in the energized position. When energized, the signal is passed through the active circuit of relay 136b to transducer 160b. In some embodiments, the active circuit of bypass relay 131b may include signal conditioning such as amplification. Transducer 160b splits the input signal and converts the split input signal into a digital signal. For example, the ADC of transducer 160b may convert an analog input signal into a digital signal. The split digital input signal is provided to microprocessor 180 via trace 170. Microprocessor 180 may interpret the signal and send commands to one or more outputs (such as server 199, controller 101, etc.). In some embodiments, microprocessor 180 may multiply a calibration factor by the first digital signal to ensure the accuracy of the signal. Microprocessor 180 may communicate the calibrated digital signal to the DAC of transducer 160b. Transducer 160b may convert the calibrated digital signal into an analog signal. Transducer 160b may output the analog signal to output relay 132b via trace 145b. The analog signal may be made available to an external device via OS2.

[0087] In some embodiments, microprocessor 180 may aggregate the digital signals from transducer 160a and transducer 160b for transmission to server 199. In some embodiments, microprocessor 180 may encrypt the output signal before transmission.

[0088] FIG. 6A is a block diagram showing splitter board 120 when splitter board 120 is in a fault condition, according to an exemplary embodiment.

[0089] For simplicity of explanation, the signal path through the splitter board 120 is emphasized.

[0090] In some embodiments, as shown in FIG. 6A, the fault condition can be caused by a board-wide failure due to loss of board power. Some components of the splitter board 120 require power to operate. For example, the microprocessor 180, converters 160a, 160b, and relays 136a, 136b, 131a, 131b, 132a, and 132b typically require power to operate.

[0091] When in a fault condition, the input relay 136a may pass a signal to the bypass relay 131a via the trace 138a. During a power failure, the bypass relay 131a may return to the power-off position. At the power-off position, the input signal may be passed directly to the output relay 132a and then to the output OS1. In other words, during a power failure, all inputs may bypass the active circuit. The original input signal IS1 may be available at the output port OS1. In this way, downstream processes external to the splitter board 120 that require the original input signal may continue without interruption. Meanwhile, the digital outputs that are normally output via ports 183, 185, 187 are not available until power is restored.

[0092] Similarly, the input relay 136b may pass a signal to the bypass relay 131b via the trace 138b. During a power failure, the bypass relay 131b may return to the power-off position. In the power-off position, the input signal may be passed directly to the output relay 132b and then to the output OS2. In other words, during a power failure, all inputs may bypass the active circuitry. The original input signal IS2 may be available at the output port OS2. In this way, downstream processes external to the splitter board 120 that require the original input signal may continue without interruption. Meanwhile, the digital outputs that are normally output via ports 183, 185, 187 are not available until power is restored.

[0093] FIG. 6B is a block diagram showing the splitter board 120 when the splitter board 120 is in a fault state, according to an exemplary embodiment.

[0094] For simplicity of explanation, the signal paths through the splitter board 120 are emphasized.

[0095] In some embodiments, as shown in FIG. 6B, the fault condition may be caused by a single component on the splitter board 120 failing. As shown, a set of a-components may be subject to failure. For example, one of the converters 160a, relays 136a, bypass relays 131a, or relays 132a may have failed. Accordingly, the input signal IS1 may be in a fault state while the input signal IS2 may be in an active state. In such embodiments, the bypass relay 131a and the output relay 132a for the input IS1 may behave as described in FIG. 6A above, bypassing all active circuitry and directing the input to the output port OS1. The bypass relay 131b and the output bypass relay 132b may remain in the active state as described above with reference to FIG. 5.

[0096] In the case of a component failure, only the circuit in which the component has failed is redirected through the bypass circuit. For example, if converter 160a fails, the input signal is passed through the "a" bypass circuit. Component failures may be monitored through failure detection modules 190a and 190b. For example, failure detection module 190a may continuously or periodically check to ensure that converter 160a or other components are in an active state.

[0097] Failure detection module 190a may be read and controlled by microprocessor 180. In some embodiments, microprocessor 180 may use general relay logic to detect failures. For example, when there is power to splitter board 120, bypass relay 131a may be in an energized switched position (such as that shown in FIG. 1). In the absence of power, bypass relay 131a may be de-energized, and the output from bypass relay 131a may be switched to failure signal 135a. During a power failure, all converters 160a - 160n return to a failed state. In some embodiments, microprocessor 180 may utilize embedded code logic to detect individual converter circuit failures. For example, converter 160a may include registers that change during active conversion. Microprocessor 180 may check the registers to ensure that they are changing progressively. In another example, if converter 160a includes digital input / output, a digital signal can be output. When active, the signal can be high, and when the converter has failed, the signal goes low.

[0098] FIG. 7 is a block diagram showing splitter board 120 undergoing a calibration process according to an exemplary embodiment.

[0099] The splitter board 120 can maintain an analog output to the downstream process even during the calibration process. As shown, the converter 160a may undergo a calibration process. During the calibration process, the bypass relay 131a may switch states so that the input signal IS1 is not sent to the converter 160a. In some embodiments, the converter 160a may buffer the input signal IS1 before switching states. Alternatively, a signal to the calibration device 142 may be used to calibrate the ADC of the converter 160a. Further, the DAC of the converter 160a may output a buffered analog output signal during calibration so that the process signal does not drop out. The calibration relay 141 may be activated so that a signal from the calibration device 142 is sent through the bypass relay 131a to the ADC of the converter 160a.

[0100] As shown, the calibration signal may flow through the same components as the input signal IS1 during the calibration process. In some embodiments, the process signal may also flow through the ADC of the converter 160a. After completion of the calibration, the microprocessor 180 may return the DAC of the converter 160a to real-time output. The microprocessor 180 may further return the calibration relay 141 to its original state. The microprocessor 180 may further return the input relay 136a to its previous state and return the input signal to the ADC of the converter 160a.

[0101] In some embodiments, the calibration signal may be directed through the bypass relay 131a so that the calibration signal can follow the same circuitry as the original input signal IS1. For example, if there is amplification of the input signal between the input relay 136a and the bypass relay 131a or between the bypass relay 131a and the converter 160a, the calibration signal may be passed through the same circuitry. Generally, the calibration device 142 may be configured to calibrate any converter of the splitter board 120 via the calibration relay 141, and the calibration relay 141 may direct the calibration signal to the other ADCs of other converters.

[0102] Furthermore, although the calibration device 142 is shown as being a component of the splitter board 120, those skilled in the art will recognize that in some embodiments, the calibration device 142 may be external to the splitter board 120.

[0103] FIG. 8 is a block diagram showing a splitter board 800 undergoing a calibration process according to an exemplary embodiment.

[0104] The splitter board 800 may be configured similarly to the above-described splitter board 120. In the example shown in FIG. 8, the splitter board 800 may further include a calibration bypass 802. The calibration bypass 802 may connect the input signal IS1 to the analog output signal OS1.

[0105] During calibration, the bypass relay 131a may switch states so that the input signal IS1 is sent directly to the output relay 132a via the calibration bypass 802. The output relay 132a may switch states so that the input signal IS1 is directed to the output port OS1. The calibration relay 141 may be activated so that a signal from the calibration device 142 can be sent through the bypass relay 131a to the ADC of the converter 160a. The signal from the calibration device 142 may be used to calibrate the ADC.

[0106] After calibration, the calibration relay 141 may be returned to its previous state. The bypass relay 131a may be returned to its previous state and the input signal IS1 may be returned to the ADC of the converter 160a. In this way, the splitter board 800 can maintain an analog output without interruption.

[0107] FIG. 9 is a block diagram showing a splitter board 900 according to an exemplary embodiment. As shown, the splitter board 900 may be configured similarly to the splitter board 120. The splitter board 900 may include a converter 960a that includes two ADC channels C1 and C2. The calibration device 142 may be connected to the ADC channel C1 of the converter 960a through the trace 146. The calibration device 142 may be connected to the ADC channel C2 of the converter 960b through the trace 151. In some embodiments, the channel C1 may be on the same ADC chip or on different ADC chips.

[0108] The channel C2 may be calibrated periodically. For example, the channel C2 may be calibrated hourly, daily, weekly, or at any desired interval. In some embodiments, the calibration parameters are stored by the microprocessor 180. The microprocessor 180 may compare the current calibration value with a previously stored calibration value. When the current calibration value differs from the stored calibration value by a predetermined amount, the microprocessor 180 may write new calibration parameters for the ADC channel C1. Such a process, i.e., writing new calibration parameters, can be performed without a significant interruption of the output signal OS.

[0109] FIG. 10 is a block diagram showing a splitter board 1000 according to an exemplary embodiment. The splitter board 1000 may include components similar to those of the splitter board 120. The splitter board 1000 differs from the splitter board 120 in that the splitter board 1000 can perform calibration without a separate calibration circuit.

[0110] As shown, the calibration circuit of the splitter board 120 has been removed from the splitter board 1000. To calibrate the splitter board 1000, input signals, such as IS1 and / or IS2, may be disconnected from the splitter board 1000. At the location where the input signal is connected, a calibration device (not shown) may be connected to the splitter board 1000. And the calibration device may calibrate the converter 160a and / or the converter 160b. After calibration, the calibration device may be disconnected from the splitter board 1000, and the input signal may be reconnected.

[0111] Figure 11A is a block diagram showing a motherboard 1100 according to an exemplary embodiment. The motherboard 1100 may represent a circuit board to which other circuit boards and components can be connected. The motherboard 1100 may be configured to input and output signals obtained from a processor board. The processor board may refer to a circuit board or component that processes signals and outputs the processed signals to the motherboard 1100.

[0112] As shown, the motherboard 1100 may include multiple sets of components. For example, the motherboard 1100 may include only one set of components or up to n sets of components. For example, the motherboard 1100 may be configured to receive a plurality of input signals IS1...IS n and may be configured to output a plurality of output signals OS1...OS n .

[0113] The motherboard 1100 may be configured to receive power inputs at V+ and V-. The motherboard 1100 may be configured to provide fault protection, such that, without a daughter board (e.g., shown in FIG. 12), the input signal IS1 may be passed to the output OS1.

[0114] As shown in the figure, the motherboard 1100 may include alignment pins A, B, C, and D, a switch 1120, an input relay 1130, and an output relay 1135. The switch 1120 may be controlled by an electronic circuit. The switch 1120 may be in an open position when the daughter board is not in a predetermined position. The switch 1120 may be in a closed position when the daughter board is in a predetermined position. As shown in FIG. 11A, when the daughter board is not in a predetermined position, the motherboard 1100 may be in a fault state. Therefore, the switch 1120 is shown to be in an open position in FIG. 11A. In the fault position, the input relay 1130 and the output relay 1135 may be powered off. In this way, the input signal IS1 is directly passed to the output signal OS1.

[0115] FIG. 11B is a block diagram showing the motherboard 1100 according to an exemplary embodiment. As shown in the figure, the motherboard 1100 is in an active state. The motherboard 1100 may be in an active state when the daughter board is connected to the motherboard 1100. When the daughter board is detected, the switch 1120 may be moved to the closed position. When the switch 1120 is closed, power may be applied to energize the relay 1130. When energized, the input relay 1130 may pass the input signal IS1 to the transfer pad 1116. The transfer pad 1116 is configured to transfer or pass the input signal IS1 from the motherboard 1100 to the daughter board. Further, in the active state, power may be applied to energize the output relay 1135. The output relay 1135 may communicate with the output pad 1118. The output pad 1118 may be configured to receive an output signal from the daughter board. The output signal received at the output pad 1118 may be passed through the output relay 1135 and output as the output signal OS1.

[0116] Therefore, as shown over FIGS. 11A and 11B, when the daughter board is in a predetermined position, the motherboard 1100 is in an active state and the input signal may be sent through the daughter board. When the daughter board is not in the predetermined position, the motherboard 1100 is in a fault state and the original input signal is sent to the output.

[0117] FIG. 12 is a block diagram showing a daughter board 1200 according to an exemplary embodiment. As shown, the daughter board 1200 may include alignment pins A, B, C, and D configured to interface with the alignment pins A, B, C, and D of the motherboard 1100, respectively. The daughter board 1200 may be configured similarly to the splitter board 120 and may represent a particular use case of the splitter board 120. The daughter board 1200 includes input pads 1215 and output pads 1217. For example, when the daughter board 1200 is in a predetermined position, the input signal IS1 may be passed from the motherboard 1100 to the input pad 1215 at the transfer pad 1116. Similarly, the output signal may be passed from the daughter board 1200 at the output pad 1217 to the motherboard 1100 at the output pad 1118.

[0118] FIG. 13 is a flowchart showing a method 1300 of operating a splitter board according to an exemplary embodiment. The method 1300 may start at step 1302. For simplicity of explanation, the following operations are described with a single set of components. As will be appreciated by those skilled in the art, the process may be repeated for each set of components and for each input signal provided to each respective set of components.

[0119] At step 1302, the microprocessor 180 may initialize the firmware for the splitter board. For example, the microprocessor 180 may execute a boot process, during which the microprocessor 180 may check the state of each component to determine if a fault exists.

[0120] In step 1304, the microprocessor 180 determines whether a fault condition exists. In some embodiments, the microprocessor 180 may determine whether there is a complete board failure or a component failure.

[0121] If in step 1304 the microprocessor 180 determines that there is a fault condition, method 1300 proceeds to step 1306. In step 1306, the microprocessor 180 resolves the fault. On the other hand, if in step 1304 the microprocessor 180 determines that there is no fault condition, method 1300 proceeds to step 1308.

[0122] In step 1308, the microprocessor 180 establishes communication with the server 199. For example, the splitter board may be connected to the server 199 through port 185. In some embodiments, port 185 may be connected to the server 199 through any means, including but not limited to USB, serial, Modbus, Ethernet, or other well-known communication means.

[0123] In step 1310, the microprocessor 180 may calibrate all input channels of each of the converters 160a - 160n. The calibration process will be described in more detail below with reference to FIGS. 14A and 14B.

[0124] In step 1312, the microprocessor 180 may connect all input signals. In some embodiments, each set of components may each include a separate set of input signals associated therewith. For example, the a-components may include a first set of input signal IS1. The microprocessor 180 may connect all input signals to their respective input relays. For example, input signal IS1 may be connected to bypass relay 131a. Similarly, input signal IS2 may be connected to bypass relay 131b. The input signals may represent one or more analog signals.

[0125] In step 1314, the microprocessor 180 may determine whether the splitter board is in a fault state. The fault state may refer to a situation where a failure has occurred. In some embodiments, the failure may be a full board failure. The full board failure may be when there is no power supply to the splitter board and all outputs are absent. In some embodiments, the failure may be a single component failure. The single component failure may be when a component of the splitter board fails. For example, converter 160a or converter 160b fails.

[0126] The microprocessor 180 may determine whether the splitter board is in a fault state by reading the fault detection module of the converter. For example, the microprocessor 180 may read the fault detection module 190a of the converter 160a and the fault detection module 190b of the converter 160b. The fault detection module 190a may detect a fault in various ways. In some embodiments, the fault detection module 190a may use general relay logic to detect a fault. For example, the bypass relay 131a may be in the energized switching position (e.g., the first state) when there is power supplied to the splitter board 120. If there is no power, the bypass relay 131a may be de-energized (e.g., the second state), and the output from the bypass relay 131a may switch to the fault signal 135a. In some embodiments, during a power failure, all converters (e.g., converter 160a, converter 160b, converter 160n, etc.) on the splitter board 120 may switch to a fault state. In some embodiments, the built-in code logic of the microprocessor 180 may be used to detect an individual converter circuit failure. For example, some converters (e.g., converter 160a) may include registers, which can change during active conversion. The microprocessor 180 may check the registers to ensure that the registers are changing progressively.

[0127] In step 1314, if the microprocessor 180 determines that the splitter board is in a fault state, method 1300 proceeds to step 1316. In step 1316, the microprocessor 180 may initiate an alarm protocol. During the alarm protocol, the microprocessor 180 may bypass the active signal circuit for the input signal and pass it directly to the output relay of that signal. For example, the input signal IS1 may go directly to the output signal OS1 as illustrated and described above with FIGS. 6A and 6B.

[0128] On the other hand, in step 1314, if the microprocessor 180 determines that the splitter board is in an active state, method 1300 proceeds to step 1318. In step 1318, the microprocessor 180 may direct the input signal to a converter for conversion. For example, the microprocessor 180 may direct the input signal IS1 to the active circuit, as a result of which the input signal IS1 reaches the ADC / DAC of the converter 160a.

[0129] In step 1320, the converter may perform data conversion on the input signal. For example, the ADC of the converter 160a may convert the input signal IS1 from an analog to a digital signal. Although not shown, the microprocessor 180 may continuously check for faults within the splitter board. The fault checks performed in steps 1304 and 1314 are examples of when the microprocessor 180 can check for a fault state.

[0130] In step 1322, the converter splits the converted signal into two or more output signals. For example, the converter 160a may split the converted input signal into a first signal and a second signal to be sent to the microprocessor 180.

[0131] In step 1324, the microprocessor 180 may multiply the first signal by a calibration factor. The calibration factor may be determined based on, for example, the operations described below with FIGS. 14A and 14B. The microprocessor 180 may transmit the first signal, along with the applied calibration factor, back to the transducer 160a.

[0132] In step 1326, the transducer 160a may convert the first signal back to an analog signal. The analog signal is based on the digital signal and the calibration factor multiplied by the digital signal by the microprocessor 180.

[0133] In step 1328, the splitter board may output a data signal. For example, the analog signal may be output as output signal OS1 from the splitter board via output relay 132a for a downstream process. Similarly, the microprocessor 180 may output the digital signal to the server 199 for analysis.

[0134] FIG. 14A is a flowchart showing a method 1400 for calibrating a splitter board according to an exemplary embodiment. The method 1400 may be particularly applicable to calibrating the splitter board described above with FIGS. 1-3 and 9. For simplicity of explanation, the following operations are described with a single set of components. As will be understood by those skilled in the art, the process may be repeated for each set of components and each input signal provided to each set of components. The method 1400 may begin at step 1402.

[0135] In step 1402, the microprocessor 180 may initialize a calibration routine. In some embodiments, the calibration routine may be initialized through the server 199. In some embodiments, the calibration routine may exist within the firmware or on the microprocessor 180.

[0136] In step 1404, the splitter board may maintain the signal to the output port, e.g., OS1, and may remove the signal from the ADC of the converter 160a. For example, the microprocessor 180 may cause the bypass relay 131a to switch states so that the input signal IS1 is not sent to the converter 160a. Instead, a signal for the calibration device 142 may be used to calibrate the ADC of the converter 160a. Further, the DAC of the converter 160a may output a buffered analog output signal.

[0137] In step 1406, the splitter board may route a calibration signal to the ADC of the converter 160a. For example, the microprocessor 180 may activate the calibration relay 141 so that the signal from the calibration device 142 is sent through the bypass relay 131a to the ADC of the converter 160a.

[0138] In step 1408, the splitter board may calibrate the ADC of the converter 160a. In some embodiments, appropriate signals may be sequentially directed to the ADC of the converter 160a in turn. For example, zero and span signals (LRS and HRS). Calibration constants may be calculated and stored by the microprocessor 180.

[0139] In step 1410, the splitter board may remove the calibration signal from the ADC of the converter 160a. For example, the microprocessor 180 may deactivate the calibration relay 141 so that the signal from the calibration device 142 is no longer passed to the ADC of the converter 160a.

[0140] In step 1412, the splitter board may restore the signal to the ADC of the converter 160a. For example, the microprocessor 180 may cause the bypass relay 131a to switch states so that the input signal IS1 is sent to the converter 160a.

[0141] FIG. 14B is a flowchart showing a method 1450 for calibrating a splitter board according to an exemplary embodiment. Method 1450 may be particularly applicable to calibrating the splitter board described above with FIG. 10. For simplicity of explanation, the following operations are described with a single set of components. As will be appreciated by those skilled in the art, the process may be repeated for each set of components and for each input signal provided to each set of components. Method 1450 may begin at step 1452.

[0142] At step 1452, the splitter board may initialize a calibration routine. For example, the microprocessor 180 may communicate with the server 199 to start the calibration routine.

[0143] At step 1454, the splitter board may connect a calibrator to the C input.

[0144] At step 1456, the splitter board may initialize a calibration program.

[0145] At step 1458, the splitter board may calculate the S output buffer and switch the output to the buffer value. In some embodiments, calibration of the ADC of the transducer 160a may take from 10 microseconds to several seconds, depending on the system. The time required for calibration may be estimated and equivalent time should be used to collect and buffer the input signal.

[0146] At step 1460, the splitter board may calibrate the ADC of the transducer 160a. In some embodiments, when calibration begins, the buffered signal may be sent to the output. When calibration is complete, the live signal may be processed again.

[0147] At step 1462, the splitter board may store the calibration constant. The microprocessor 180 may later apply a calibration input to the input signal, as described above with FIG. 13.

[0148] In step 1464, the splitter board may cut off the calibrator. The splitter board may also be reconnected to the input signal IS1.

[0149] After completion of calibration, the microprocessor 180 may return the DAC of the transducer 160a to the real-time output. The microprocessor 180 may further return the calibration relay 141 to its original state. The microprocessor 180 may further return the input relay 136a to its previous state and return the input signal to the ADC of the transducer 160a.

[0150] In some embodiments, the calibration signal may be directed through the bypass relay 131a so that the calibration signal may follow the same circuit as the original input signal IS1. For example, if there is amplification of the input signal between the input relay 136a and the bypass relay 131a or between the bypass relay 131a and the transducer 160a, the calibration signal may be passed through the same circuit. Generally, the calibration device 142 may be configured to calibrate any transducer of the splitter board via the calibration relay 141, and the calibration relay 141 may direct the calibration signal to the other ADCs of other transducers.

[0151] FIG. 15A shows the system bus architecture of a computing system 1500 according to an exemplary embodiment. The system 1500 may represent at least a portion of a microprocessor 180. One or more components of the system 1500 may communicate electrically with each other using a bus 1505. The system 1500 may include a system bus 1505 that couples various system components, including a processing unit (CPU or processor) 1510, and a system memory 1515 such as a read-only memory (ROM) 1520 and a random access memory (RAM) 1525, to the processor 1510. The system 1500 may include a cache of high-speed memory that is directly or proximally connected to the processor 1510 or integrated as part of the processor 1510. The system 1500 may copy data from the memory 1515 and / or the storage device 1530 to the cache 1512 for rapid access by the processor 1510. In this way, the cache 1512 may provide a performance improvement that avoids the delay of the processor 1510 while waiting for data. These and other modules may control the processor 1510 to perform various actions or may be configured to control. Other system memory 1515 may also be available for use. The memory 1515 may include multiple different types of memory having different performance characteristics. The processor 1510 may include any general-purpose processor and hardware module or software module, such as Service 1 1532, Service 2 1534, and Service 3 1536, stored in the storage device 1530 and configured to control the processor 1510, and a dedicated processor in which software instructions are incorporated into an actual processor design. The processor 1510 may essentially be a fully self-contained computing system including multiple cores or processors, buses, memory controllers, caches, and the like. The multi-core processor may be symmetric or asymmetric.

[0152] To enable user interaction with the computing system 1500, the input device 1545 may represent any number of input mechanisms such as a microphone for voice, a touch-sensitive screen for gesture or graphical input, a keyboard, a mouse, motion input, voice, etc. The output device 1535 may also be one or more of several output mechanisms known to those skilled in the art. In some examples, a multimodal system may allow the user to provide multiple types of input to communicate with the computing system 1500. The communication interface 1540 may generally control and manage user input and system output. Since there is no limitation on operating on any specific hardware configuration, the basic features here can be easily replaced as improved hardware configurations or firmware configurations are developed.

[0153] The memory device 1530 may be a non-volatile memory such as a magnetic cassette, a flash memory card, a solid-state memory device, a digital versatile disk, a cartridge, a random access memory (RAM) 1525, a read-only memory (ROM) 1520, and their hybrids, and may be a hard disk or other type of computer-readable medium capable of storing data and accessible by a computer.

[0154] The memory device 1530 may include services 1532, 1534, and 1536 for controlling the processor 1510. Other hardware or software modules are contemplated. The memory device 1530 may be connected to the system bus 1505. In one aspect, a hardware module that performs a specific function may include software components stored on a computer-readable medium associated with the necessary hardware components such as the processor 1510, the bus 1505, the output device 1535 (e.g., a display), etc. to implement that function.

[0155] FIG. 15B shows a computer system 1550 having a chipset architecture that may represent at least a portion of microprocessor 180. Computer system 1550 may be an example of computer hardware, software, and firmware that may be used to implement the disclosed techniques. System 1550 may include a processor 1555, which represents any number of physical and / or logically distinct resources capable of executing software, firmware, and hardware configured to perform the identified computations. Processor 1555 may communicate with a chipset 1560 that may control inputs to and outputs from processor 1555. In this example, chipset 1560 may output information to an output 1565 such as a display and may read from and write information to a storage device 1570 that may include, for example, a magnetic medium and a solid state medium. Chipset 1560 may also read data from and write data to a storage device 1575 (e.g., RAM). A bridge 1580 may be provided to interface chipset 1560 with various user interface components 1585. Such user interface components 1585 may include a keyboard, a microphone, touch detection / processing circuitry, and a pointing device such as a mouse. In general, inputs to system 1550 may originate from any of a variety of sources, machine-generated and / or human-generated.

[0156] Chipset 1560 may also interface with one or more communication interfaces 1590, which may have different physical interfaces. Such communication interfaces may include interfaces for wired and wireless local area networks, wide area wireless networks, and personal area networks. Some applications of the methods for generating, displaying, and using the GUIs disclosed herein may include receiving an ordered data set through a physical interface, or may be generated by the machine itself by the processor 1555 analyzing data stored in the storage device 1570 or the storage device 1575. Further, the machine may receive inputs from the user through the user interface component 1585 and perform appropriate functions, such as browsing functions, by using the processor 1555 to interpret these inputs.

[0157] As can be appreciated, the exemplary systems 1500 and 1550 may have multiple processors 1510 to provide higher processing capabilities, or may be part of a group or cluster of computing devices networked together.

[0158] While the foregoing is directed to embodiments described herein, other and further embodiments may be devised without departing from the basic scope thereof. For example, aspects of the present disclosure may be implemented in hardware or software or a combination of hardware and software. One embodiment described herein may be implemented as a program product for use with a computer system. The program of the program product defines the functions of the embodiments (including the methods described herein) and can be included on various computer-readable storage media. Exemplary computer-readable storage media include, but are not limited to, (i) non-writable storage media in which information is permanently stored (e.g., CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips, or any type of solid-state non-volatile memory such as a read-only memory (ROM) device in a computer), and (ii) writable storage media in which modifiable information is stored (e.g., floppy disks in a disk drive or hard disk drive or any type of solid-state random access memory). Such computer-readable storage media are embodiments of the present disclosure when executing computer-readable instructions that direct the functions of the disclosed embodiments.

[0159] As will be understood by those skilled in the art, the above examples are illustrative and not limiting. All substitutions, extensions, equivalents, and improvements thereto will be apparent to those skilled in the art upon reading this specification and considering the drawings and are intended to be included within the true spirit and scope of the present disclosure. Accordingly, the appended claims below are intended to include all such modifications, substitutions, and equivalents as falling within the true spirit and scope of these teachings.

Claims

1. A system comprising: a converter having an analog-to-digital circuit and a digital-to-analog circuit; a bypass relay coupled to the converter, the bypass relay being configurable between a first state and a second state; a microprocessor coupled to the converter and the bypass relay, the microprocessor being configured to switch the bypass relay between the first state and the second state; a splitter board comprising and comprising In the first state, the bypass relay directs an input signal to the converter, the converter converts the input signal into a converted input signal, the converter divides the converted input signal into a first portion and a second portion, the microprocessor multiplies the first portion by a calibration factor, returns the first portion to the converter for output at an output port of the splitter board for a downstream process, and outputs the second portion to an external server device; In the second state, the bypass relay bypasses the converter from the input signal and directs the input signal to the output port of the splitter board for the downstream process.

2. a second converter coupled to the microprocessor, the second converter having a second analog-to-digital circuit and a second digital-to-analog circuit; a second bypass relay coupled to the microprocessor and the second converter, the second bypass relay being configurable between the first state and the second state; further comprising The microprocessor is further configured to switch the second bypass relay between the first state and the second state. In the first state, the second bypass relay directs a second input signal to the second transducer, and the second transducer converts the second input signal into a second converted input signal. The second converted input signal is split into a third portion and a fourth portion. The third portion is directed to the microprocessor, and the fourth portion is directed to a second output port of the splitter board for the downstream process. In the second state, the second bypass relay bypasses the second transducer from the second input signal and directs the second input signal to the second output port of the splitter board for the downstream process. The system according to claim 1.

3. The bypass relay is in the first state, and the second bypass relay is in the second state. The system according to claim 2.

4. A calibration circuit coupled to the transducer and the microprocessor, the calibration circuit being configured to calibrate the analog-digital circuit of the transducer. The system according to claim 1, further comprising.

5. The transducer is configured to buffer the input signal. The system according to claim 4.

6. While the calibration circuit calibrates the analog-digital circuit of the transducer, the transducer outputs the buffered input signal. The system according to claim 5.

7. The transducer further comprises a fault detection module configured to detect when at least one component of the splitter board has failed. The system according to claim 1.

8. The microprocessor is configured to read the fault detection module to determine when at least one component of the splitter board has failed. The system according to claim 7.

9. When it is determined that the transducer has failed, the microprocessor is configured to cause the bypass relay to switch from the first state to the second state. The system according to claim 8.

10. A second splitter board that communicates with the splitter board, the second splitter board comprising: A second converter comprising a second analog-to-digital circuit and a second digital-to-analog circuit; A second bypass relay coupled to the second converter, the second bypass relay being configurable between a third state and a fourth state; A second microprocessor coupled to the second converter and the second bypass relay, the second microprocessor being configured to switch the second bypass relay between the third state and the fourth state; The second splitter board comprising Further comprising In the third state, the second bypass relay directs a second input signal to the second converter, the second converter converts the second input signal into a second converted input signal, and the second converted input signal is divided into a third portion and a fourth portion. The microprocessor multiplies the third portion by the calibration factor, returns the first portion to the converter for output at a second output port of the second splitter board for the downstream process, and outputs the fourth portion to the external server device; In the fourth state, the second bypass relay bypasses the second converter around the second input signal and directs the second input signal to a second output port of the splitter board for output to the microprocessor of the splitter board. The system according to claim 1. **Claim 11** The splitter board is a host splitter board, the second splitter board is an auxiliary splitter board, and the splitter board and the second splitter board are arranged in a daisy chain. The system according to claim 10. **Claim 12** A system comprising: An input relay configurable between a first position and a second position; An input pad communicating with the input relay; A switch configurable between an open position and a closed position; An output relay configurable between a first position and a second position; An output pad communicating with the output relay; A motherboard comprising ​ A daughter board configured to be connected to the motherboard, wherein when the daughter board is connected to the motherboard, the input relay switches from the open position to the closed position, as a result, power is supplied to the input relay and the output relay, the input relay is switched from the first position to the second position, and the output relay is switched from the first position to the second position. Daughter board Comprising In the second position, the input pad provides an input signal from the motherboard to the daughter board, and the output pad receives an output signal from the daughter board. System

13. The daughter board is A converter comprising an analog-digital circuit and a digital-analog circuit; A bypass relay coupled to the converter, the bypass relay being configurable between a first state and a second state. Bypass relay A microprocessor coupled to the converter and the bypass relay, the microprocessor being configured to switch the bypass relay between the first state and the second state. Microprocessor Comprising, in the first state, the bypass relay directing an input signal to the converter, the converter converting the input signal into a converted input signal, splitting the converted input signal into a first portion and a second portion, the microprocessor multiplying the first portion by a calibration factor, returning the first portion to the converter for output at an output port for a downstream process, and outputting the second portion to an external server device, and in the second state, the bypass relay bypassing the converter around the input signal and directing the input signal to the output port for the downstream process. The system according to claim 12

14. The daughter board is A second converter comprising a second analog-digital circuit and a second digital-analog circuit; A second bypass relay coupled to the second converter, the second bypass relay being configurable between a third state and a fourth state. Second bypass relay A second microprocessor coupled to the second converter and the second bypass relay, wherein the second microprocessor is configured to switch the second bypass relay between the third state and the fourth state, the second microprocessor and further comprising In the third state, the second bypass relay directs a second input signal to the second converter, the second converter converts the second input signal into a second converted input signal, and the second converted input signal is divided into a third part and a fourth part. The microprocessor multiplies the third part by the calibration factor, returns the first part to the converter for output at a second output port of the daughter board for the downstream process, and outputs the fourth part to the external server device. configured to In the fourth state, the second bypass relay bypasses the second converter from the second input signal and directs the second input signal to the second output port for output to the microprocessor. The system of claim 13, wherein

15. The system of claim 14, wherein the bypass relay is in the first state and the second bypass relay is in the second state.

16. A calibration circuit inside the daughter board and coupled to the microprocessor and the converter, the calibration circuit being configured to calibrate the analog-digital circuit of the converter, the calibration circuit The system of claim 13, further comprising

17. The system of claim 16, wherein the converter is configured to buffer the input signal.

18. The system of claim 17, wherein the converter outputs the buffered input signal while the calibration circuit calibrates the analog-digital circuit of the converter.

19. A calibration circuit external to the daughter board and coupled to the microprocessor and the converter, the calibration circuit being configured to calibrate the analog-digital circuit of the converter, the calibration circuit The system of claim 13, further comprising

20. The converter further comprises a fault detection module configured to detect when at least one component of the daughter board has failed, the system according to claim 13.

21. The microprocessor is configured to read the fault detection module to determine when at least one component of the daughter board has failed, the system according to claim 20.

22. When it is determined that the converter has failed, the microprocessor is configured to cause the bypass relay to switch from the first state to the second state, the system according to claim 20.

23. Activating a splitter board by a microprocessor, wherein activating the splitter board includes energizing a bypass relay of the splitter board, and when energized, the bypass relay directs an input signal to the converter, the converter being configured to convert the input signal into a converted signal and split the converted signal into a first portion and a second portion, activating the splitter board; Detecting by the microprocessor that at least one component of the splitter board has failed; Based on the detecting, de-energizing the bypass relay by the microprocessor, wherein de-energizing the bypass relay bypasses the converter to the input signal, de-energizing the bypass relay; A method comprising.

24. Initiating a calibration process to calibrate the analog-to-digital circuit of the converter; Buffering the input signal by the converter; Inputting a calibration signal to the converter; Calibrating the converter using the calibration signal while the buffered input signal is being output from the converter; The method according to claim 23, further comprising.

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