Method and apparatus for measuring non-local conductance

Abstract

A method is provided for measuring the nonlocal conductance of a semiconductor component of a semiconductor-superconductor hybrid device, the semiconductor component having a first terminal and a second terminal, a first gate electrode for electrostatically gating the first terminal, a second gate electrode for electrostatically gating the second terminal, and a superconductor component configured for energy level hybridization with the semiconductor component. The method includes applying a first gate voltage to the first gate electrode to gate the first terminal to an open regime, applying a second gate voltage to the second gate electrode to gate the second terminal to a tunneling regime, applying a bias voltage to the first terminal, and measuring a current through the second terminal while applying the first gate voltage, the second gate voltage, and the bias voltage, the superconductor component being grounded during the measurement. Also provided is an apparatus used to perform the method, and a computer readable medium having stored thereon code for causing the apparatus to perform the method.

Description

Background Art

[0001] Topological quantum computing is based on the phenomenon that non-abelian anyons can be formed in the form of Majorana zero modes (MZM) in a region where a semiconductor is coupled to a superconductor, i.e., a region where energy level hybridization with the superconductor can be formed. Non-abelian anyons are a type of quasiparticle, meaning an excitation in an electron liquid that behaves at least partially like a particle, rather than the particle itself. MZM is a specific bound state of such quasiparticles.

[0002] Under certain conditions, MZM can be formed in a nanowire formed from the length of a superconductor-coated semiconductor close to the semiconductor-superconductor interface. When MZM is induced in a nanowire, it is said to be in a "topological regime". To induce this, conventionally, an externally applied magnetic field and cooling of the nanowire to a temperature that induces superconducting behavior within the superconductor material are required. Also, it may include gate biasing a part of the nanowire with an electrostatic potential.

[0003] By forming such a network of nanowires and inducing a topological regime in parts of the network, it is possible to create qubits (quantum bits) that can be manipulated for the purpose of quantum computing. A qubit, i.e., a quantum bit, is an element for which a measurement with two possible outcomes can be performed, but in reality, at any time (when not being measured), two states corresponding to different outcomes may be quantum mechanically superposed.

[0004] To induce MZMs, the device is cooled to a temperature at which the superconductor (e.g., aluminum, Al) exhibits superconducting behavior. The superconductor induces a proximity effect in the adjacent semiconductor, causing the regions of the semiconductor near the interface with the superconductor to also exhibit superconducting properties. That is, topological phase behavior is induced not only in the superconductor but also in the adjacent semiconductor. It is in this region of the semiconductor that MZMs are formed.

[0005] Another condition for inducing the topological phase in which MZMs can be formed is to apply a magnetic field to lift the spin degeneracy in the semiconductor. Degeneracy in the context of a quantum system refers to the case where different quantum states have the same energy level. Lifting the degeneracy means causing such states to have different energy levels. Spin degeneracy refers to the case where different spin states have the same energy level. Spin degeneracy can be lifted by a magnetic field, causing a splitting of the energy levels between differently spin-polarized electrons. This is known as the Zeeman effect. Usually, the magnetic field is applied by an external electromagnet. However, U.S. Patent Application No. 16 / 246287 (Patent Document 1) also discloses a heterostructure in which a layer of ferromagnetic insulator is disposed between the superconductor and the semiconductor to apply a magnetic field internally to lift the spin degeneracy without the need for an external magnet. Examples of ferromagnetic insulators include EuS, GdN, Y3Fe5O 12 、Bi3Fe5O 12 、YFeO3, Fe2O3, Fe3O4, GdN, Sr2CrReO6, CrBr3 / CrI3, YTiO3 (the heavy elements are europium, gadolinium, yttrium, iron, strontium, and rhenium).

[0006] Inducing MZMs usually also requires gating of the nanowire by an electrostatic potential. The electrostatic potential is applied using a gate electrode. Applying the electrostatic potential manipulates the number of charge carriers in the conductance band or valence band of the semiconductor component.

[0007] As shown in FIG. 1, to create a high-quality device in which the MZM has a long lifetime, it is desirable that the topological gap E g is large. Materials in the topological phase (which may be a superconductor or a proximitized superconducting region of a semiconductor) exhibit different energy bands, namely, a lower band 101 and an upper band 102. The lower band 101 is a band where the quasiparticle energy E falls within a lower range, and the upper band (or "excitation band") 102 is a band of higher quasiparticle energy. The topological gap E g is an energy window between the upper band 102 and the lower band 101 where quasiparticles cannot exist due to the quantized (discrete) nature of the quasiparticle energy levels. The lower band 101, the upper band 102, and the topological gap E g are similar to the valence band, conduction band, and band gap of electrons in a semiconductor. In the upper excitation band 102, quasiparticles can propagate freely through the superconductor (or proximitized region of a semiconductor), similar to electrons in the valence band of a semiconductor.

[0008] The Majorana that is in the state forming the MZM forms the lower band 101. The Majorana is part of the computational space, i.e., the characteristics of the system utilized in the quantum computing application in question. In other words, the MZM is an operating element of a qubit. On the other hand, particle-like excitations (quasiparticles) in the upper band 102 are not part of the computational space. When these quasiparticles enter the lower band 101 across the topological energy gap E g due to, for example, thermal fluctuations, this destroys at least a part of the MZM. This is sometimes called "poisoning" of the MZM. The gap E g protects the MZM from such poisoning. The probability that quasiparticles present in the upper band cross the gap E g from the upper band to the lower band is e -Eg / kTProportional to, where T is the temperature and k is the Boltzmann constant. Therefore, the larger the topological gap, the more protected the MZM can be against poisoning from harmful quasiparticles in the upper band 102.

[0009] A more detailed treatment of the theory of the operation of semiconductor-superconductor hybrid devices is provided by Stanescu et al (Physical Review B 84, 144522 (2011)) (Non-Patent Document 1) and Winkler et al (Physical Review B 99, 245408 (2019)) (Non-Patent Document 2).

[0010] It is desirable to enable the measurement of the characteristics of semiconductor-superconductor hybrid devices, particularly the measurement of the size of the topological gap. It is also desirable to be able to select appropriate operating parameters for semiconductor-superconductor hybrid devices.

Prior Art Documents

Patent Documents

[0011]

Patent Document 1

Non-Patent Documents

[0012]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

[0013] In one aspect, a method for measuring the nonlocal conductance of a semiconductor component of a semiconductor-superconductor hybrid device is provided. The semiconductor-superconductor hybrid device includes a semiconductor component having a first terminal and a second terminal, a first gate electrode for electrostatically gating the first terminal, a second gate electrode for electrostatically gating the second terminal, and a superconductor component configured to enable energy level hybridization with the semiconductor component. The method includes applying a first gate voltage to the first gate electrode to gate the first terminal into an open regime, applying a second gate voltage to the second gate electrode to gate the second terminal into a tunneling regime, applying a bias voltage to the first terminal, and measuring a current flowing through the second terminal while the first gate voltage, the second gate voltage, and the bias voltage are applied. During the measurement, the superconductor component is grounded.

[0014] In other aspects, an apparatus for measuring the nonlocal conductance of a semiconductor component of a semiconductor-superconductor hybrid device is provided, where the semiconductor-superconductor hybrid device includes a semiconductor component and a superconductor component, and the superconductor component is configured to enable energy level hybridization with the semiconductor component. The apparatus includes a processing unit, a data storage, and a connection circuit operably connected to the semiconductor-superconductor hybrid device. The data storage stores code that, when executed by the processing unit, causes the apparatus to perform operations including applying a first gate voltage to the first gate electrode to gate the first terminal of the semiconductor component into an open regime, applying a second gate voltage to the second gate electrode to gate the second terminal of the semiconductor component into a tunneling regime, applying a bias voltage to the first terminal, and measuring a current flowing through the second terminal while the first gate voltage, the second gate voltage, and the bias voltage are applied.

[0015] Yet another aspect provides a computer-readable storage medium storing code that, when executed by a processing unit of an apparatus having a connection circuit operably connected to a semiconductor-superconductor hybrid device, causes the apparatus to perform an operation having: applying a first gate voltage to a first gate electrode to gate a first terminal of a semiconductor component into a depletion regime; applying a second gate voltage to a second gate electrode to gate a second terminal of the semiconductor component into a tunneling regime; applying a bias voltage to the first terminal; and measuring a current flowing through the second terminal while the first gate voltage, the second gate voltage, and the bias voltage are being applied.

[0016] This summary is provided to introduce, in a simplified form, some concepts that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all of the disadvantages described herein.

[0017] For the purpose of assisting in the understanding of the embodiments of the present disclosure and of showing how such embodiments may be implemented, reference is made, by way of mere example, to the accompanying drawings.

Brief Description of the Drawings

[0018]

Figure 1

Figure 2a

Figure 2b

Figure 3

Figure 4

Figure 5

DETAILED DESCRIPTION OF THE INVENTION

[0019] Figures 2a and 3 are not to scale. In Figure 3, the relative sizes of the semiconductor - superconductor hybrid device are exaggerated for ease of representation.

[0020] The verb "comprising" is used herein as a shorthand for "including" or "consisting of". In other words, while the verb "comprising" is intended to be an open term, substitution of this term by the closed term "consisting of" is explicitly contemplated, particularly when used in connection with chemical components.

[0021] Directional terms such as "above", "below", "left", "right", "above ~", "below ~", "horizontal", and "vertical" are used herein for convenience of description and are related to the orientation shown in the drawings. To avoid misunderstanding, it is added that this term is not intended to limit the orientation in an external reference frame.

[0022] As used herein, the term "superconductor" refers to a substance that becomes superconducting when cooled to a temperature below the critical temperature T C of the substance. The use of this term is not intended to limit the temperature of the device.

[0023] A "nanowire" is an elongated member having a nanoscale width and a length-to-width ratio of at least 100, or at least 500, or at least 1000. Typical examples of nanowires have a width in the range of 10 to 500 nm, optionally 50 to 100 nm or 75 to 125 nm. The length is usually on the order of micrometers, for example, at least 1 μm, or at least 10 μm.

[0024] The term "coupling" in the context of the present disclosure refers to the hybridization of energy levels.

[0025] A "semiconductor-superconductor hybrid structure", also referred to herein as a "hybrid device", has semiconductor and superconductor components that can couple to each other under certain operating conditions. In particular, this term refers to a structure that can exhibit topological behavior such as Majorana zero modes, or other excitations useful for quantum computing applications. Operating conditions generally include cooling the structure to a temperature lower than T of the superconductor component, applying a magnetic field to the structure, and applying electrostatic gating to the structure. Generally, at least a portion of the semiconductor component is in close contact with the superconductor component. For example, the superconductor component may grow epitaxially on the semiconductor component. However, certain device structures having one or more additional components between the semiconductor and superconductor components have been proposed. C Cooling the structure to a temperature lower than that of the superconductor component, applying a magnetic field to the structure, and applying electrostatic gating to the structure. Generally, at least a portion of the semiconductor component is in close contact with the superconductor component. For example, the superconductor component may grow epitaxially on the semiconductor component. However, certain device structures having one or more additional components between the semiconductor and superconductor components have been proposed.

[0026] Characterization of semiconductor-superconductor hybrid devices using local conductance measurements has been reported. In local conductance measurements, the conductance is measured between one terminal of the superconductor component and one terminal of the semiconductor component.

[0027] This specification provides a method for measuring the non-local conductance of a hybrid device. Measuring the non-local conductance can enable better characterization of the properties and behavior of a semiconductor-superconductor hybrid device. For example, the size of the topological gap occurring in the device can be determined based on non-local conductance data. Further, it has been found that by electrostatically gating a semiconductor-superconductor hybrid device in a particular way, an improvement in the signal-to-noise ratio of the measurement can be achieved.

[0028] An example of a semiconductor-superconductor hybrid device will first be described with reference to FIG. 2. FIG. 2 shows a schematic cross-sectional view of the device.

[0029] Device 200 includes a substrate, a semiconductor-superconductor hybrid structure, and a gate stack.

[0030] Substrate 210 provides a base on which the other parts of the device are fabricated. The substrate may have a wafer of a crystalline material. The wafer material is not particularly limited. The wafer may have a material selected from high bandgap semiconductors, such as indium phosphide, gallium arsenide, and gallium antimonide.

[0031] The semiconductor-superconductor hybrid structure has a semiconductor component 212 and a superconductor component 216.

[0032] Semiconductor component 212 is disposed on substrate 210. The semiconductor component typically has a nanowire, or a network of nanowires. The network of nanowires has two or more connected nanowires and may have a branched structure in a plane.

[0033] The semiconductor component may have any suitable semiconductor material. For example, semiconductor component 212 may have a group III-V semiconductor material such as a substance of Formula 1: InAsxSb 1-x (Formula 1) Here, x ranges from 0 to 1. In other words, the semiconductor component 212 may have indium antimonide (x = 0), indium arsenide (x = 1), or a ternary mixture containing 50% indium and variable proportions of arsenic and antimony (0 < x < 1) on a molar basis. The substance of Formula 1 is known to bind particularly well with superconducting materials such as aluminum.

[0034] Another class of materials useful as semiconductor components are II-VI semiconductor materials. Examples of II-VI semiconductor materials include lead telluride and tin telluride.

[0035] During device fabrication, the semiconductor component 212 can be epitaxially grown on the substrate 210, for example, using selective area growth. Selective area growth uses a dielectric mask 214 disposed on the substrate 210 to control where the semiconductor component 212 grows. In an implementation where selective area growth is used to fabricate a device, the dielectric mask 214 may remain in the completed device. Examples of materials useful as dielectric masks include silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (AlO x ), and hafnium oxide (HfO x ). Two or more dielectric layers may be present.

[0036] Other processes, such as, for example, the VLS (Vapour-Liquid-Solid) process, may be used to manufacture the semiconductor component.

[0037] The represented semiconductor component 212 generally has a generally trapezoidal cross-section. The cross-sectional shape, however, is not particularly limited and can vary, for example, depending on the process and conditions selected for manufacturing the semiconductor component.

[0038] The hybrid structure further includes a superconducting component 216. The superconducting component 216 is disposed on the semiconductor component 212. The semiconductor component 212 and the superconducting component 216 are configured to enable coupling between the semiconductor component 212 and the superconducting component 216. Such coupling enables excitations useful for quantum computing to be induced under conditions.

[0039] In the illustrated example, the superconducting component 216 is in direct contact with the semiconductor component 212. For example, the superconducting component 216 may be epitaxially grown on the semiconductor component 212. However, direct contact is not necessarily essential to achieve the coupling. A device structure has been proposed in which additional components such as ferromagnetic insulators can be disposed between the semiconductor component 212 and the superconducting component 216.

[0040] The properties of the superconductor are not particularly limited and may be selected as needed. The superconductor is typically an s-wave superconductor. Any of the various s-wave superconductors known in the art may be used. By way of example, aluminum, indium, tin, and lead may be mentioned, although aluminum may be preferred in some situations. In embodiments where aluminum is used, the superconducting component 216 may have a thickness in the range of, for example, 4 to 10 nm. Aluminum layers having a thickness in this range have been reported to couple particularly well with the semiconductor material of Equation 1 (Winkler et al (Physical Review B 99, 245408 (2019))).

[0041] The device 200 may include regions where the superconducting component is not present on the semiconductor component 212. In other words, the superconducting component 216 does not necessarily extend along the entire length of the semiconductor component 212. In particular, the superconductor may not be present in the terminal regions at the ends of the semiconductor component 212.

[0042] Device 200 includes a gate stack having a gate electrode 220 and a dielectric 218 disposed between the gate electrode and other portions of the device. The example shown is a top-gate type, and the gate stack is disposed on top of other components of device 200.

[0043] Generally, the purpose of the gate electrode is to apply an electrostatic field to the semiconductor component 212 during use in order to manipulate the number of charge carriers available in the conduction band of the semiconductor component 212.

[0044] The dielectric 218 is for blocking or reducing the flow of current from the gate electrode to other components of the device. Any such current is referred to as leakage current. The leakage current in such a device can depend on various factors including the quality of the layer of dielectric material 218, e.g., purity and thickness.

[0045] Gating can be applied to any portion of the semiconductor component 212. A gate electrode that gates a region of the semiconductor component where a superconducting component is present may be referred to as a plunger gate. A gate electrode that gates a region of the semiconductor component where no superconducting component is present may be referred to as a cutter gate. The gate electrode 220 shown in FIG. 2 is an example of a plunger gate.

[0046] The semiconductor-superconductor hybrid device used herein has a cutter gate at the terminal region, i.e., the end of the semiconductor component 212. The device may further include one or more plunger gates.

[0047] FIG. 2 shows only one example of a semiconductor-superconductor hybrid device, but numerous variations are possible.

[0048] The exemplary device is a top-gate type. Other configurations of the gate stack are possible. The device may be a bottom-gate type. In a bottom-gate type device, the gate electrode may be disposed under the semiconductor component, e.g., on the surface of the substrate opposite to the semiconductor component. In such a configuration, the substrate may function as a gate dielectric. A side-gate type device in which the gate electrode is laterally spaced from the semiconductor component is also possible. In the case of a side-gate type device, it is optional to include a layer of dielectric material since there may be a void space left between the gate electrode and the semiconductor device and it can function as a dielectric.

[0049] The exemplary device is horizontally oriented, i.e., the length direction of the nanowire extends parallel to the surface of the substrate. The method provided herein is equally applicable to vertically oriented devices. Examples of vertically oriented devices are described in U.S. Patent Application Publication No. 2020 / 0027030(A1) and U.S. Patent Application Publication No. 2020 / 0027971(A1).

[0050] An example of an apparatus for measuring non-local conductance will now be described with reference to FIG. 3. FIG. 3 is a block diagram showing an apparatus used in connection with a semiconductor-superconductor hybrid device. The apparatus may be detachably connectable to the semiconductor-superconductor hybrid device such that the semiconductor-superconductor hybrid device need not be present when the apparatus is not in use. Alternatively, the apparatus may be permanently connected to the semiconductor-superconductor hybrid device.

[0051] As described above with reference to FIG. 2, the semiconductor-superconductor hybrid device 310 includes a semiconductor component 312 in the form of a nanowire and a superconductor component 314. FIG. 3 further shows that the semiconductor-superconductor hybrid device has first and second terminals each provided with a cutter gate 316, 318.

[0052] When at least the device is in use, the superconducting component is connected to ground.

[0053] The first terminal of the hybrid device 310 is connected to a voltage source 320 that applies a known bias voltage to the semiconductor component 312. The first terminal may be an emitter terminal. The second terminal of the hybrid device 310 is connected to an ammeter that measures the current flowing through the second terminal. The second terminal may be a receiver terminal.

[0054] In the examples given herein, the first and second terminals are also referred to as the left and right terminals, respectively. Of course, this is for convenience of description only and is not intended to limit the relative positions of the terminals in space.

[0055] The device 340 includes a processing unit 342, a data storage 344, and a connection circuit 346. The processing unit 342 is operably linked to the data storage 344 and the connection circuit 346. The data storage 344 stores a computer program, and when the computer program is executed by the processing unit 342, it causes the device to execute the methods described herein.

[0056] The device 340 may further include any user terminal. The user terminal may include a user input device and a display device.

[0057] The user input device may have any one or more suitable input devices known in the art for receiving input from the user. Examples of input devices include pointing devices such as a mouse, a stylus, a touch screen, a track pad, and / or a trackball. Other examples of input devices include a keyboard, a microphone when used with a voice recognition algorithm, and / or a video camera when used with a gesture recognition algorithm.

[0058] As used herein, when referring to receiving input from a user via a user input device, this may mean via any one or more of the user input devices that make up the user input device.

[0059] The user input device may be useful in enabling the user to specify values of parameters to be investigated, such as the bias voltage and gate voltage to be used. The user input device may be omitted if the parameters are determined in some other way, for example, based on a message received in a program or over a network.

[0060] The display device may take any suitable form for outputting an image, such as a light-emitting diode (LED) screen, a liquid crystal display (LCD), a plasma screen, or a cathode ray tube (CRT). The display device may have a touch screen and thus may form at least part of the user input device. The touch screen enables input by being touched by a user's finger and / or using a stylus.

[0061] Including a display device is optional. The display device is useful in cases where it is desirable to display a graph or other output that can be read by a person to the user.

[0062] The processing unit 342 may be implemented in one or more dies, integrated circuit (IC) packages, and / or enclosures at one or more geographical locations. There may be more than one processing unit.

[0063] Each of the one or more processing units may take any suitable form known in the art, such as, for example, a general-purpose central processing unit (CPU), or a dedicated form such as a co-processor or accelerator processor like a graphics processing unit (GPU), a digital signal processor (DSP), etc. Each of the one or more processing units may have one or more cores. The processing unit is typically a classical processing unit, as opposed to a quantum processing unit.

[0064] When a computer program is said to be executed using a processing device, this may mean execution by any one or more of the processing units present within the device.

[0065] The processing unit 342 typically further has a working memory such as random access memory and / or one or more memory caches.

[0066] The data storage 344 has one or more memory units implemented on one or more memory media within one or more enclosures at one or more geographical locations.

[0067] Each of the one or more memory units may use any suitable computer-readable storage medium known in the art, such as, for example, a magnetic storage medium like a hard disk drive, a magnetic tape drive, etc., or an electronic storage medium like a solid state drive (SSD), flash memory or electrically erasable programmable read-only memory (EEPROM), or an optical storage medium like an optical disk drive or memory liquid crystal based storage. As used herein, the term "computer-readable storage medium" specifically refers to a non-transitory computer-readable storage medium.

[0068] When it is said that some item of data is stored in data storage 344 or an area thereof, this may mean that it is stored in any part of any one or more of the memory devices that make up data storage 344.

[0069] Processing unit 342 and data storage 344 are operably linked. The processing unit and data storage are configured such that processing unit 342 can read data from at least a portion of data storage 344 and optionally write data to at least a portion of data storage 344. Processing unit 342 can communicate with data storage 344 via a local connection, e.g., a physical data bus, and / or via a network such as a local area network or the Internet. In the latter case, the network connection may be wired or wireless.

[0070] Apparatus 340 further includes a connection circuit 346 that is operably connected to a semiconductor - superconductor hybrid device. In the example shown, the connection circuit is configured such that apparatus 340 can control the gate voltages applied to first and second cutter gates 316, 318, control or receive the measurement of the bias voltage applied by voltage source 320, and measure the current flowing through the second terminal by ammeter 330.

[0071] When the semiconductor - superconductor hybrid device includes one or more additional gate electrodes, e.g., cutter gates, the connection circuit is further configured to enable the apparatus to control the gate voltages applied to its additional gate electrodes.

[0072] Voltage source 320 and ammeter 330 may be components of apparatus 340 or may be removably connectable to apparatus 340.

[0073] One or more components of the device may be disposed on the same die as the semiconductor-superconductor hybrid device. One or more components of the device may be disposed on the same circuit board as the semiconductor-superconductor hybrid device. Disposing the device on the same die or the same circuit as the hybrid device may be particularly useful in implementations where the device is for controlling the operating parameters of the qubit device.

[0074] The semiconductor-superconductor hybrid device operates in a cryogenic chamber so as to enable superconducting behavior to be induced. Components of device 340 may be disposed outside the cryogenic chamber. In particular, the voltage source and the processing unit may be outside the cryogenic chamber. The cryogenic chamber has a finite refrigeration capacity, also called a thermal budget, and generally it is desirable to minimize the number of heat-generating components present in the chamber.

[0075] The example presented shows a device connected to a single semiconductor-superconductor hybrid device. The device may alternatively be configured to be connected to a plurality of semiconductor-superconductor hybrid devices simultaneously. The plurality of semiconductor-superconductor hybrid devices may be disposed, for example, on a qubit device.

[0076] Alternative devices may be used in the implementation of the methods described herein. The device used is not particularly limited, provided that the gate voltage is controllable, the base station bias voltage is applicable to the first terminal, and the current flowing through the second terminal is measurable. The use of a processing unit and data storage for controlling the applied voltage and recording the measurements is optional.

[0077] FIG. 4 is a flowchart illustrating a method of measuring the nonlocal conductance of a semiconductor-superconductor hybrid device. As described with reference to FIGS. 2 and 3, the hybrid device comprises first and second terminals each provided with a cutter gate. The superconductor component is connected to ground during measurement.

[0078] In block 401, a first gate voltage is applied to the first gate electrode 316 to gate the first terminal into an open regime. In other words, the first gate voltage is selected to increase the number of available charge carriers in the semiconductor at the first terminal. This places the semiconductor of the first terminal in a conductive state.

[0079] A terminal is considered to be "open", i.e., in an open regime, when it has a local conductance of e 2 / h or more. Here, e is the elementary charge (i.e., the absolute value of the charge of a single electron), and h is Planck's constant.

[0080] The local conductance is the conductance measured between the terminal and the superconducting component. The local conductance may be a high-bias local conductance. The high-bias local conductance is the local conductance measured when a bias voltage greater than the size of the superconducting energy gap, e.g., a bias voltage at least twice the size of the superconducting gap, is applied. In particular, the local conductance may be measured at a bias voltage twice the size of the superconducting gap. The local conductance may be measured as described in Anselmetti et al., Phys. Rev. B 100, 205412 (2019).

[0081] Simultaneously, in block 402, a second gate voltage is applied to the second gate electrode 318 to gate the second terminal into a tunneling regime. Typically, the first and second gate voltages are different.

[0082] In the tunneling regime, an energy barrier is created for the flow of charge through the second terminal. The second terminal is adjusted to a classically non-conductive state. Any flow of current through the second terminal is due to the quantum tunneling effect.

[0083] A terminal is considered to be "open", i.e., in an open regime, when it has a local conductance of e 2It is in the tunneling regime when it has a high-bias local conductance of less than e / h. Here, e is the elementary charge (i.e., the absolute value of the charge of a single electron), and h is the Planck constant.

[0084] In particular, the second terminal may be gated into the deep tunneling regime. The terminal in the deep tunneling regime has a high-bias local conductance of 0.1e 2 / h or less. Here, e is the elementary charge (i.e., the absolute value of the charge of a single electron), and h is the Planck constant.

[0085] Similar to the local conductance of the first terminal, the local conductance of the second terminal is the conductance between the second terminal and the superconducting component. The local conductance may be the high-bias local conductance measured when applying a bias voltage greater than the size of the superconducting gap, optionally, a bias voltage at least twice the size of the superconducting gap. In particular, the high-bias local conductance may be measured at a bias voltage twice the size of the superconducting gap.

[0086] In block 403, a bias voltage is applied to the semiconductor component via the first terminal. The magnitude of the applied voltage is known or measured. The bias voltage is applied while simultaneously applying the first and second gate voltages to their respective terminals.

[0087] In block 404, while the operations of block 401, block 402, and block 403 are being performed, the current flowing through the second terminal is measured.

[0088] When the applied voltage exceeds the threshold corresponding to the induced energy gap in the semiconductor component of the hybrid device, a current flows.

[0089] Next, the conductance of the semiconductor component may be calculated based on the bias voltage applied to the first terminal and the value of the current flowing through the second terminal. Since this conductance represents the conductance through the nanowire from the first terminal to the second terminal, it is a "non-local conductance". In contrast, in a "local" conductance measurement, the current between one terminal of the hybrid device and the superconducting component is measured.

[0090] By gate biasing the first terminal into the open regime and the second terminal into the tunneling regime, a detectable signal with a good signal-to-noise ratio can be achieved.

[0091] Another approach to measuring non-local conductance uses symmetric gating where the same gate voltage is applied to both terminals. It has been found that gating both terminals into the open or intermediate regime results in a noisy signal, and gating both terminals closed results in no measurable current flowing through the nanowire.

[0092] Various modifications may be made to the method.

[0093] The bias voltage may be changed, and the current flowing through the second terminal may be measured as a function of the bias voltage. For example, a scan of the bias voltage may be performed. The range to be scanned may be selected as needed depending on the characteristics of the semiconductor-superconductor hybrid device. The scan may cover, for example, bias voltages in the range from -500 to +500 μV, optionally from -300 to +300 μV, optionally from 0 to 500 μV, optionally from 0 to 300 μV.

[0094] Performing such a scan can be useful for determining the minimum bias voltage to drive current from one terminal of the semiconductor component to the other terminal of the semiconductor component. This minimum bias voltage can be an indicator of the size of the induced energy gap in the semiconductor-superconductor hybrid device.

[0095] The size of the topological gap can be obtained from the conductance data by determining a bias voltage at which the measured non-local conductance value exceeds a predetermined threshold. The predetermined threshold is set to be larger than the noise floor of the device. The noise floor is the sum of all noise sources and unwanted signals within the device, and all signals other than the signal representing non-local conductance are considered "unwanted".

[0096] Alternatively, the size of the topological gap can be obtained from the conductance data by calculating the first derivative value of the conductance with respect to the applied bias voltage and finding the lowest applied bias voltage at which the slope of the first derivative value is not zero.

[0097] According to yet another possibility, the size of the topological gap can be determined by fitting a curve to the data and estimating the gap size to be associated with the peak position at the lowest bias voltage.

[0098] Other techniques for determining the size of the induced gap based on non-local conductance measurements may be used.

[0099] In addition to, or as an alternative to, changing the bias voltage, one or both of the first and second gate voltages may be adjusted. In particular, the gate voltage may be adjusted while applying a fixed bias voltage.

[0100] Adjustment of the gate voltage can enable optimization of the signal-to-noise ratio of the measurement.

[0101] Adjusting the gate voltage can also change the behavior of the semiconductor-superconductor hybrid device. For example, by changing one or both of the gate voltages, the magnitude of the energy gap induced in the hybrid device can be changed. The gate voltage may be adjusted to maximize the magnitude of the induced energy gap, such as a topological gap. Alternatively, the gate voltage may be adjusted to obtain an induced energy gap having a size within a predetermined range. The predetermined range may be in the range of 20% to 80% of the superconducting gap of the superconducting component.

[0102] In an example where the hybrid device includes one or more additional gate electrodes, the gate voltage may be applied to the additional electrodes during measurement. The gate voltage applied to the additional electrodes may be changed, for example, to maximize the size of the induced energy gap or to obtain the induced energy gap within a predetermined range.

[0103] The adjustment of the values of the operating parameters of the semiconductor-superconductor hybrid device may be performed based on an optimization algorithm. The nature of the optimization algorithm is not particularly limited and may be selected as needed from various optimization algorithms known in the field of machine learning. The optimization may have iterative adjustments. For example, a gradient descent method or an ascent algorithm such as stochastic gradient descent may be used.

[0104] The optimization algorithm may change the values of one or more parameters selected from the bias voltage, the first gate voltage, and the second gate voltage. When there are one or more additional gate electrodes, the one or more parameters may include the gate voltage for the additional gate electrodes.

[0105] The initial values of the one or more parameters may be based on input received from a user, for example, via a user input device of apparatus 340. Alternatively, the initial values may be determined programmatically, for example, based on stored values from a previous optimization or based on a model or simulation of the semiconductor-superconductor hybrid device.

[0106] The optimization algorithm may be configured to determine an optimized value of one or more parameters, the value corresponding to a target result. The target result may be the maximum signal-to-noise ratio of the measurement of non-local conductance. The target result may be the maximum magnitude and / or visibility of an induced energy gap, such as a topological gap. The target result may be to obtain an induced energy gap having a size within a predetermined range, for example, 20% to 80% of the size of the superconducting gap. The magnitude of the induced energy gap can be determined as described above.

[0107] The output of the optimization algorithm includes an optimized value of one or more parameters. The optimized value is written to a data storage, such as the data storage 344 of the device 340, output in a human-readable format, for example, displayed on a display device of the device 340, communicated to other entities over a network, and / or used, for example, by the device 340 to control the operation of the device.

[0108] In an implementation where the optimized value is written to a data storage, when iterative optimization is performed, the initial value of the iteration may be determined based on the stored optimized value. Since a particular hybrid structure may be damaged over time, it may be useful to repeat the optimization periodically, for example, daily or weekly, for the same device.

[0109] One or more parameters selected from the bias voltage, the first gate voltage, and the second gate voltage may be selected according to a machine learning algorithm, such as an artificial neural network.

[0110] The training data for the machine learning algorithm may include optimized values of the bias voltage, the first gate voltage, and the second gate voltage for a plurality of hybrid devices. The training data may include empirical data obtained experimentally, such as the results of manual optimization, and / or stored optimized values generated using an optimization algorithm as described above. Additionally, or alternatively, the training data may include optimized values generated by simulation.

[0111] The machine learning algorithm may be configured to determine optimized values of one or more parameters, the values corresponding to a target result. The target result may be the maximum signal-to-noise ratio of the measurement of the non-local conductance. The target result may be the maximum magnitude and / or visibility of the induced energy gap. The target result may be to obtain an induced energy gap having a magnitude within a predetermined range.

[0112] The exemplary method has been described with reference to a single semiconductor-superconductor hybrid device, but the method may be performed with a plurality of semiconductor-superconductor hybrid devices. The plurality of semiconductor-superconductor hybrid devices may be arranged, for example, as qubit devices. The non-local conductance of the individual hybrid devices of the plurality of hybrid devices may be measured continuously or simultaneously. This may be useful for selecting the operating parameters of the qubit device, for example, specifying the bias voltage and the gate voltage such that the individual hybrid devices have an induced gap with a magnitude within a desired range.

[0113] It will be understood that the above embodiments are described by way of example only.

[0114] More generally, according to one aspect disclosed herein, a method for measuring the nonlocal conductance of a semiconductor component of a semiconductor-superconductor hybrid device is provided. The semiconductor-superconductor hybrid device has the semiconductor component having a first terminal and a second terminal, a first gate electrode for electrostatically gating the first terminal, a second gate electrode for electrostatically gating the second terminal, and a superconductor component configured to enable energy level hybridization with the semiconductor component. The method includes applying a first gate voltage to the first gate electrode to gate the first terminal to an open regime, applying a second gate voltage to the second gate electrode to gate the second terminal to a tunneling regime, applying a bias voltage to the first terminal, and measuring the current flowing through the second terminal while the first gate voltage, the second gate voltage, and the bias voltage are applied. During the measurement, the superconductor component is grounded. By adjusting the first terminal of the semiconductor component to the open regime, the second terminal to the tunneling regime, applying a bias voltage to the first terminal, and measuring the current flowing through the second terminal, a measurement of the nonlocal conductance through the semiconductor component with a good signal-to-noise ratio can be obtained. The nonlocal conductance may then be used to determine the characteristics of the hybrid device.

[0115] The first and second gate electrodes may each be a cutter gate. In other words, the first and second terminals may be regions of the semiconductor component that do not have superconducting material thereon.

[0116] The semiconductor component may be a nanowire of semiconductor material having first and second ends. The superconductor component may be disposed on a portion of the nanowire. The superconductor component may be spaced apart from the first and second ends of the nanowire so as to define the first and second terminals.

[0117] The tunneling regime may be a deep tunneling regime.

[0118] The method may further include changing one or more of the bias voltage, the first gate voltage, and the second gate voltage. Changing the applied voltage may change the behavior of the semiconductor - superconductor hybrid device.

[0119] The method provided herein may be controlled by a computer. For example, the semiconductor - superconductor hybrid device may be operatively connected to a device having a processing unit and data storage. The processing unit may control one or more of the bias voltage, the first gate voltage, and the second gate voltage, and may receive measurements of current.

[0120] The processing unit may be a classical processing unit.

[0121] The method may further include determining, based on the measurements, the magnitude of the energy gap occurring in the semiconductor - superconductor hybrid device. For example, the determination may include identifying the lowest bias voltage corresponding to a non - local conductance greater than the noise floor of the measurement. The determination may include fitting a model to the measurements.

[0122] The determination may be performed by the processing unit of the device.

[0123] The method may include adjusting one or more of the bias voltage, the first gate voltage, and the second gate voltage. The adjustment may be controlled by the processing unit. For example, the processing unit may execute an optimization algorithm as described above herein. The processing unit may use the optimization algorithm to determine an optimized value of one or more of the bias voltage, the first gate voltage, and the second gate voltage corresponding to a target result.

[0124] The adjustment and / or optimization may alternatively be controlled manually.

[0125] The target result may be to enhance the visibility of the energy gap, for example, by obtaining a non-local conductance greater than a predetermined threshold. The predetermined threshold may be the noise floor of the device used to perform the measurement.

[0126] The target result may include a signal-to-noise ratio of the measurement that is above a predetermined threshold.

[0127] The target result may include the magnitude of the energy gap induced in a semiconductor-superconductor hybrid device that is within a predetermined range.

[0128] The predetermined range may be in the range of 20% to 80% of the superconducting gap of the superconducting component. An induced gap having a magnitude outside this range may not be very useful for quantum computing.

[0129] Alternatively, the predetermined range may be a range above a predetermined threshold.

[0130] The processing unit may select a static value for the bias voltage and change the first and / or second gate voltage.

[0131] The semiconductor-superconductor hybrid device may be present in a device that includes a plurality of semiconductor-superconductor hybrid devices. A device having a plurality of semiconductor-superconductor hybrid devices may be, for example, a qubit device.

[0132] The non-local conductance measurement may be performed simultaneously or sequentially on individual hybrid devices of a plurality of semiconductor-superconductor hybrid devices.

[0133] The induced gap, for example, the topological gap, of individual hybrid devices of a plurality of semiconductor-superconductor hybrid devices can be determined.

[0134] The bias voltage, the first gate voltage, and the second gate of the individual hybrid devices of the plurality of semiconductor - superconductor hybrid devices may each be independently selected. In other words, the voltages applied to the individual devices may be different. The voltages may be adjusted as described above, for example, to induce an energy gap within a predetermined range in the semiconductor - superconductor hybrid device.

[0135] Another aspect is an apparatus for measuring the non - local conductance of a semiconductor component of a semiconductor - superconductor hybrid device, the semiconductor - superconductor hybrid device having a semiconductor component and a superconductor component, the superconductor component being configured such that energy level hybridization with the semiconductor component is possible. In the apparatus, there are a processing unit, a data storage, and a connection circuit operably connected to the semiconductor - superconductor hybrid device. The data storage stores code that, when executed by the processing unit, causes the apparatus to perform operations including applying a first gate voltage to a first gate electrode to gate a first terminal of the semiconductor component into an open regime, applying a second gate voltage to a second gate electrode to gate a second terminal of the semiconductor component into a tunneling regime, applying a bias voltage to the first terminal, and measuring a current flowing through the second terminal while the first gate voltage, the second gate voltage, and the bias voltage are being applied. The apparatus is useful for performing the methods provided herein.

[0136] The apparatus may be configured to perform the operations described above with respect to the method aspects.

[0137] The tunneling regime may be a deep tunneling regime.

[0138] The apparatus may include a semiconductor - superconductor hybrid device. In such an implementation, the connection circuit is connected to the semiconductor - superconductor hybrid device.

[0139] The operation may further comprise connecting a superconducting component to the installation. Alternatively, the semiconductor-superconductor hybrid device may be configured such that the superconducting component is connected to the installation.

[0140] The operation may further comprise determining the magnitude of the energy gap occurring in the semiconductor-superconductor hybrid device based on the measured current. The determination may comprise fitting a model to the measurement. The determination may comprise identifying the lowest bias voltage corresponding to a non-local conductance greater than the noise floor of the measurement.

[0141] The operation may further comprise adjusting one or more of the first gate voltage, the second gate voltage, and the bias voltage. For example, the operation may comprise selecting and applying a static bias voltage and adjusting one or both of the first and second gate voltages.

[0142] The adjustment may comprise determining optimized values of one or more of the bias voltage, the first gate voltage, and the second gate voltage using an optimization algorithm to obtain a target result. The target result includes a signal-to-noise ratio of the measurement that is above a predetermined threshold. The target result may include the magnitude of the energy gap induced in the semiconductor-superconductor hybrid device that is within a predetermined range.

[0143] The apparatus may be configured to perform measurements on and / or control the operation of a plurality of semiconductor-superconductor hybrid devices. For example, the connection circuit may be operably connectable to a plurality of semiconductor-superconductor hybrid devices. The code may be configured to cause the apparatus to perform operations on a plurality of semiconductor-superconductor hybrid devices.

[0144] The operation may include applying a first gate voltage, a second gate voltage, and a bias voltage, which are independently selected, to respective hybrid devices of a plurality of semiconductor-superconductor hybrid devices.

[0145] The apparatus may be configured to perform the operation simultaneously on at least two of the plurality of semiconductor-superconductor hybrid devices. Alternatively, the operation may be performed sequentially on respective hybrid devices of the plurality of semiconductor-superconductor hybrid devices.

[0146] The plurality of semiconductor-superconductor hybrid devices may be disposed in a qubit device.

[0147] Yet another aspect provides a computer-readable medium storing code that, when executed by a processing unit of an apparatus having a connection circuit operably connected to a semiconductor-superconductor hybrid device, causes the apparatus to perform the methods defined herein.

[0148] The operation may include applying a first gate voltage to a first gate electrode to gate a first terminal of a semiconductor component into an open regime, applying a second gate voltage to a second gate electrode to gate a second terminal of the semiconductor component into a tunneling regime, applying a bias voltage to the first terminal, and measuring a current flowing through the second terminal while the first gate voltage, the second gate voltage, and the bias voltage are being applied.

[0149] The computer-readable medium is typically a non-transitory computer-readable medium. The computer-readable medium may be a non-volatile memory such as a hard drive, a solid-state drive, or a ROMANTIC chip.

[0150] [Example 1] The device shown in Fig. 2b was fabricated on hybrid InAs / Al nanowires grown by selective area growth, similar to the process described in Vaitiekenas et al., Phys. Rev. Lett. 121, 147701. The nonlocal conductance of the device as a function of the applied bias voltage at the left terminal was measured using the method described with reference to Fig. 4. The left bias voltage was varied from -500 to 500 μV.

[0151] A plot showing the nonlocal conductance as a function of the applied bias voltage, i.e., the derivative of the current (dI left ) flowing through the second terminal with respect to the bias voltage (dV right ) applied to the first terminal, is shown in Fig. 5.

[0152] The magnitude of the nonlocal conductance coincides with zero in the bias voltage range near zero bias. When a higher bias voltage is applied, a finite nonlocal conductance begins corresponding to the edges of the induced gap. To quantify this gap, a peak fit was performed and the value of the induced gap was obtained from the center of the peak, which in this case is Δ = 186 μV.

[0153] The local conductance (e.g., the derivative dI_left / dV_left of the current flowing through the first terminal with respect to the voltage applied to the first terminal) is usually positive, while the nonlocal conductance (e.g., dI_left / dV_right) can be not only positive but also negative depending on the details of the electron transport mechanism. The nonlocal conductance is approximately asymmetric with respect to the bias voltage, as is usually observed and predicted from theory in a particular scenario.

[0154] Other variations or uses of the disclosed technology will be apparent to those skilled in the art upon reading the disclosure herein. The scope of the present disclosure is not limited by the described embodiments, but only by the appended claims.

Claims

A method for measuring the non-local conductance of a semiconductor component of a semiconductor-superconductor hybrid device operably connected to a device having a processing unit and a data storage, comprising: The semiconductor-superconductor hybrid device comprises: The semiconductor component having a first terminal and a second terminal; A first gate electrode for electrostatically gating the first terminal; A second gate electrode for electrostatically gating the second terminal; A superconductor component configured to be capable of energy level hybridization with the semiconductor component In the method, Applying a first gate voltage to the first gate electrode to gate the first terminal into an open regime; Applying a second gate voltage to the second gate electrode to gate the second terminal into a tunneling regime; Applying a bias voltage to the first terminal; Measuring the current flowing through the second terminal while applying the first gate voltage, the second gate voltage, and the bias voltage; Receiving, by the processing unit, the measurement result of the current, and based on the measurement result, determining the magnitude of the energy gap generated in the semiconductor-superconductor hybrid device, wherein the determination comprises: i) Fitting a model to the measurement; and / or ii) Identifying the lowest bias voltage corresponding to a non-local conductance greater than the noise floor of the measurement Having the step of determining; And During the measurement, the superconductor component is grounded. Method.

2. The tunneling regime is a deep tunneling regime. The method according to claim 1.

3. Further comprising changing one or more of the bias voltage, the first gate voltage, and the second gate voltage. The method according to claim 1 or 2.

4. The processing unit Controls one or more of the bias voltage, the first gate voltage, and the second gate voltage. The method according to any one of claims 1 to 3.

5. The processing unit adjusts one or more of the bias voltage, the first gate voltage, and the second gate voltage to enhance the visibility of the energy gap. The method according to claim 4.

6. The processing unit uses an optimization algorithm to determine an optimal value for one or more of the bias voltage, the first gate voltage, and the second gate voltage to obtain a target result, where the target result is i) the measured signal-to-noise ratio being greater than or equal to a predetermined threshold, and / or ii) the magnitude of the energy gap occurring in the semiconductor-superconductor hybrid device being within a predetermined range including The method according to claim 4 or 5.

7. The processing unit selects a static value for the bias voltage and changes the first gate voltage and / or the second gate voltage. The method according to claim 5 or 6.

8. The semiconductor-superconductor hybrid device is present in a qubit device including a plurality of semiconductor-superconductor hybrid devices. The method according to any one of claims 1 to 7.

9. An apparatus for measuring the non-local conductance of a semiconductor component of a semiconductor-superconductor hybrid device, wherein the semiconductor-superconductor hybrid device has a semiconductor component and a superconductor component, and the superconductor component is configured to be capable of energy level hybridization with the semiconductor component. In the apparatus, a processing unit; a data storage; a connection circuit operably connected to the semiconductor-superconductor hybrid device having When executed by the processing unit, the data storage causes the apparatus to apply a first gate voltage to a first gate electrode to gate a first terminal of the semiconductor component into an open regime; apply a second gate voltage to a second gate electrode to gate a second terminal of the semiconductor component into a tunneling regime; apply a bias voltage to the first terminal; measure a current flowing through the second terminal while applying the first gate voltage, the second gate voltage, and the bias voltage; determine the magnitude of the energy gap occurring in the semiconductor-superconductor hybrid device based on the measured current, and the determination is i) fitting a model to the measured current, and / or ii) identifying the lowest bias voltage corresponding to a non-local conductance greater than the noise floor of the measurement having, said determining storing code for causing an operation having an apparatus. **Claim 10** The operation further comprises connecting the superconducting component to ground, The apparatus according to claim 9. **Claim 11** The operation further comprises adjusting one or more of the first gate voltage, the second gate voltage, and the bias voltage, the operation comprising selecting and applying a static bias voltage and adjusting one or both of the first gate voltage and the second gate voltage, The apparatus according to claim 9 or 10. **Claim 12** The adjustment comprises using an optimization algorithm to determine an optimum value for one or more of the bias voltage, the first gate voltage, and the second gate voltage to obtain a target result, the target result being i) a signal-to-noise ratio of the measurement that is greater than or equal to a predetermined threshold, and / or ii) a magnitude of an energy gap occurring in the semiconductor-superconductor hybrid device that is within a predetermined range including, The apparatus according to claim 11. **Claim 13** The connection circuit is operably connected to a plurality of semiconductor-superconductor hybrid devices, The code configures the apparatus to perform the operation on the plurality of semiconductor-superconductor hybrid devices, i) the operation comprises applying a first gate voltage, a second gate voltage, and a bias voltage, each independently selected, to individual devices of the plurality of semiconductor-superconductor hybrid devices, and / or ii) the operation is performed simultaneously on at least two of the plurality of semiconductor-superconductor hybrid devices, and / or iii) the plurality of semiconductor-superconductor hybrid devices are arranged in a qubit device, The apparatus according to any one of claims 9 to 12.

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