Semiconductor device and electronic device

Abstract

Provided is a semiconductor device having a novel configuration. This semiconductor device comprises a cell array which performs multiply-add operations in a first layer and multiply-add operations in a second layer in an artificial neural network, a first circuit which inputs data into the cell array, and a second circuit which outputs second data from the cell array. The cell array comprises multiple cells. The cell array has a first region and a second region. During a first period, in the first region, by inputting the t^th (t a natural number greater than or equal to 2) first data from the first circuit, the t^th second data corresponding to multiply-add operations in the first layer is outputted to the second circuit. In the second region, by inputting the (t-1)^st first data from the first circuit, the (t-1)^st second data corresponding to the multiply-add operations in the second layer is outputted to the first circuit.

Description

Technical Field

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include semiconductor devices, imaging devices, display devices, light-emitting devices, power storage devices, storage devices, display systems, electronic devices, lighting devices, input devices, input / output devices, their driving methods, or their manufacturing methods.

Background Art

[0003] Currently, the development of integrated circuits that mimic the structure of the human brain is actively underway. The integrated circuit has the structure of the brain incorporated as an electronic circuit and has circuits corresponding to the "neurons" and "synapses" of the human brain. Therefore, such an integrated circuit may also be referred to as "neuromorphic", "brainomorphic", or "brain-inspired". The integrated circuit has a non-Neumann architecture and is expected to perform parallel processing with extremely low power consumption compared to the Neumann architecture in which power consumption increases as the processing speed increases.

[0004] A model of information processing that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). By using an artificial neural network, it is possible to make inferences with human-level or even higher accuracy than humans. In an artificial neural network, the operation of weighted summation of neuron outputs, that is, the multiplication and summation operation, is the main operation.

[0005] Non-Patent Document 1 has proposed a multiplication-accumulation circuit using non-volatile memory elements. In the multiplication-accumulation circuit, in each memory element, by utilizing the operation in the subthreshold region of a transistor having silicon in the channel formation region, a current corresponding to the multiplication of the data corresponding to the multiplier stored in each memory element and the input data corresponding to the multiplicand is output. Further, data corresponding to the multiplication-accumulation operation is obtained by the sum of the currents output from the memory elements in each column. Since the multiplication-accumulation circuit has memory elements inside, it is not necessary to perform data reading and writing from an external memory in multiplication and addition. Therefore, the number of data transfers due to reading and writing can be reduced, and it is expected that the power consumption can be lowered.

Prior Art Documents

Non-Patent Documents

[0006]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] When performing a multiplication-accumulation operation in a multiplication-accumulation circuit, there is a risk that the power consumption increases due to an increase in the leakage current accompanying the miniaturization of transistors. In repeated arithmetic processing such as multiplication-accumulation, it is important to improve not only the arithmetic processing speed but also the arithmetic processing ability per unit power.

[0008] In addition, by applying a display system equipped with a sum-of-products operation circuit to a glasses-type AR (Augmented Reality) device or the like, it is possible to provide an advanced user experience that combines not only a display function but also a sensor function and an AI processing function. However, since it is assumed that a battery is used to drive the device, restrictions on power consumption become severe. Therefore, the arithmetic unit for realizing the function needs to have low power consumption.

[0009] One aspect of the present invention is to provide a semiconductor device or the like having excellent arithmetic processing ability per unit power as one of the problems. One aspect of the present invention is to provide a semiconductor device or the like excellent in power consumption reduction as one of the problems. One aspect of the present invention is to provide a semiconductor device or the like having a novel configuration capable of performing a sum-of-products operation as one of the problems.

[0010] Note that one aspect of the present invention does not necessarily need to solve all of the above problems, and it is sufficient if it can solve at least one problem. Also, the description of the above problems does not prevent the existence of other problems. Other problems will naturally become clear from the description in the specification, claims, drawings, etc., and it is possible to extract these other problems from the description in the specification, claims, drawings, etc.

Means for Solving the Problems

[0011] One aspect of the present invention is a semiconductor device comprising: a cell array that performs a first layer product-sum operation and a second layer product-sum operation in an artificial neural network; a first circuit that inputs first data to the cell array; and a second circuit that outputs second data from the cell array, wherein the cell array has a plurality of cells, and the cell array has a first region and a second region; during a first period, the first region receives t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs t-th second data corresponding to the first layer product-sum operation to the second circuit; and the second region receives (t-1)-th first data from the first circuit and outputs (t-1)-th second data corresponding to the second layer product-sum operation to the second circuit.

[0012] One aspect of the present invention is an artificial neural network comprising a cell array that executes a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit that inputs first data to the cell array, and a second circuit that outputs second data from the cell array, wherein the cell array has a plurality of cells, the cell array having a first region and a second region, and wherein during a first period, the first region receives t-th (t is a natural number equal to or greater than 2) first data from the first circuit and outputs t-th second data corresponding to the product-sum operation of the first layer to the second region. the second region receives the (t-1)th first data from the first circuit and outputs the (t-1)th second data corresponding to the sum-of-products operation of the second layer to the second circuit; during a second period, the first region receives the (t+1)th first data from the first circuit and outputs the (t+1)th second data corresponding to the sum-of-products operation of the first layer to the second circuit; and the second region receives the tth first data from the first circuit and outputs the tth second data corresponding to the sum-of-products operation of the second layer to the second circuit.

[0013] In one aspect of the present invention, the semiconductor device is preferably such that the first data input to the second region is data obtained by performing a nonlinear operation on the second data output from the first region.

[0014] In one aspect of the present invention, a semiconductor device having a third circuit that outputs second data from a cell array is preferable, and the third circuit has a function of performing an operation based on a non-linear function on the second data.

[0015] In one aspect of the present invention, a cell has a first transistor, a second transistor, and a capacitor. The first transistor has a function of holding a first potential corresponding to weight data applied to the gate of the second transistor via the first transistor when in the off state. The capacitor has a function of changing the first potential held at the gate of the second transistor to a second potential in response to a change in potential corresponding to first data applied to one electrode. The second transistor has a function of outputting second data corresponding to the first data as an analog current to the other of the source or drain. A semiconductor device is preferable.

[0016] In one aspect of the present invention, a semiconductor device in which the analog current is a current that flows when the second transistor operates in the subthreshold region is preferable.

[0017] In one aspect of the present invention, a semiconductor device in which the first transistor has a semiconductor layer having a metal oxide in a channel formation region is preferable.

[0018] In one aspect of the present invention, a semiconductor device in which the metal oxide contains In, Ga, and Zn is preferable.

[0019] In one aspect of the present invention, a semiconductor device in which the second transistors each have a semiconductor layer having silicon in a channel formation region is preferable.

[0020] One aspect of the present invention is an electronic device including the semiconductor device, a drive circuit, a pixel circuit, a light-emitting element, and a light-receiving element, where the pixel circuit has a function of controlling the light emission of the light-emitting element, the drive circuit has a function of controlling the pixel circuit, the semiconductor device has transistors in the layer where the pixel circuit is provided and transistors in the layer where the drive circuit is provided, and the semiconductor device has a function of performing arithmetic processing using the current output from the light-receiving element as first data.

[0021] In one aspect of the present invention, the light-receiving element includes an organic photodiode, and the light-emitting element is an organic EL element, and it is an electronic device.

[0022] In one aspect of the present invention, the separation of the light-emitting element and the light-receiving element is performed by a photolithography method, and it is an electronic device.

[0023] Other aspects of the present invention are described and illustrated in the embodiments described below and in the drawings.

Advantages of the Invention

[0024] One aspect of the present invention can provide a semiconductor device and the like with excellent arithmetic processing ability per unit power. One aspect of the present invention can provide a semiconductor device and the like with excellent low power consumption. One aspect of the present invention can provide a semiconductor device and the like with a novel configuration capable of performing multiplication and accumulation operations.

[0025] The description of multiple effects does not prevent the existence of other effects. Also, one embodiment of the present invention does not necessarily have to have all of the illustrated effects. Also, for one embodiment of the present invention, other problems, effects, and novel features will be apparent from the description and drawings of this specification.

Brief Description of the Drawings

[0026] FIG. 1 is a diagram for explaining a configuration example of a semiconductor device. FIGS. 2A and 2B are diagrams for explaining a configuration example of a semiconductor device. FIG. 3A and FIG. 3B are diagrams for explaining a configuration example of a semiconductor device. FIG. 4A and FIG. 4B are diagrams for explaining a configuration example of a semiconductor device. FIG. 5 is a diagram for explaining a configuration example of a semiconductor device. FIG. 6 is a diagram for explaining a configuration example of a semiconductor device. FIG. 7 is a diagram for explaining a configuration example of a semiconductor device. FIG. 8 is a diagram for explaining a configuration example of a semiconductor device. FIG. 9 is a diagram for explaining a configuration example of a semiconductor device. FIG. 10 is a diagram for explaining a configuration example of a semiconductor device. FIG. 11A and FIG. 11B are diagrams for explaining a configuration example of a semiconductor device. FIG. 12 is a diagram for explaining a configuration example of a semiconductor device. FIG. 13A, FIG. 13B, and FIG. 13C are diagrams for explaining a configuration example of a semiconductor device. FIG. 14A, FIG. 14B, FIG. 14C, and FIG. 14D are diagrams for explaining a configuration example of a semiconductor device. FIG. 15A, FIG. 15B, and FIG. 15C are diagrams for explaining a configuration example of a semiconductor device. FIG. 16 is a diagram for explaining a configuration example of a semiconductor device. FIG. 17 is a diagram for explaining a configuration example of a semiconductor device. FIG. 18A and FIG. 18B are diagrams for explaining a configuration example of a display device. FIG. 19A and FIG. 19B are diagrams for explaining a configuration example of a display device. FIG. 20 is a diagram for explaining a configuration example of a display device. FIG. 21A and FIG. 21B are diagrams for explaining a configuration example of a display device. FIG. 22A and FIG. 22B are diagrams for explaining a configuration example of a display device. FIG. 23A, FIG. 23B, FIG. 23C, and FIG. 23D are diagrams for explaining a configuration example of a display device. FIG. 24A and FIG. 24B are diagrams for explaining a configuration example of a display device. FIG. 25A, FIG. 25B, FIG. 25C, and FIG. 25D are diagrams for explaining a configuration example of a display device. FIG. 26A and FIG. 26B are diagrams for explaining a configuration example of a display device. FIGS. 27A to 27G are diagrams for explaining a configuration example of a display device. FIG. 28 is a diagram for explaining a configuration example of a display device. FIGS. 29A and 29B are diagrams for explaining a configuration example of an electronic device. FIGS. 30A and 30B are diagrams for explaining a configuration example of an electronic device.

Mode for Carrying Out the Invention

[0027] Hereinafter, embodiments of the present invention will be described. However, one embodiment of the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention is not construed as being limited to the description of the embodiments shown below.

[0028] In this specification and the like, ordinal numbers such as "first", "second", and "third" are added to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, the component referred to as "first" in one of the embodiments of this specification and the like may be the component referred to as "second" in other embodiments or the claims. Also, for example, the component referred to as "first" in one of the embodiments of this specification and the like may be omitted in other embodiments or the claims.

[0029] In the drawings, the same elements, elements having the same or similar functions, elements of the same material, or elements formed simultaneously may be given the same reference numerals, and repeated explanations may be omitted.

[0030] In this specification, for example, the power supply potential VDD may be described by omitting it as the potential VDD, VDD, etc. The same applies to other components (for example, signals, voltages, circuits, elements, electrodes, wirings, etc.).

[0031] Furthermore, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "_2", "_n", or "_m,n" may be added to the reference numeral. For example, the second wiring GL is written as wiring GL_2.

[0032] (Embodiment 1) A semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention can be used for arithmetic processing of an artificial neural network. As an example of the artificial neural network, a hierarchical neural network can be used.

[0033] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0034] 1 is a block diagram of a semiconductor device that combines a cell array and its peripheral circuits, which can perform the sum-of-products operation performed in the arithmetic processing of an artificial neural network (hereinafter sometimes referred to as a neural network). Note that the semiconductor device having the cell array and its peripheral circuits described in this embodiment is a circuit capable of sum-of-products operation, and may be referred to as an arithmetic circuit.

[0035] The semiconductor device MAC includes a circuit XCS, a circuit WCS, a circuit WSD, a cell array CA, and a circuit ITRZ. The cell array CA includes cells IM (also called memory cells) arranged in a matrix of m rows and n columns (m and n are natural numbers greater than or equal to 2).

[0036] Circuit XCS has digital-to-analog (D / A) conversion circuits corresponding to each row of cell array CA. Circuit XCS can supply analog signals corresponding to input data to cell IMs of each row of cell array CA via signal lines X[1] to X[m]. Circuit XCS may be referred to as an X driver. Also, signal lines X[1] to X[m] may be referred to as wiring XCL[1] to XCL[m].

[0037] Input data XDATA to be supplied to each row of cell array CA is given to circuit XCS. Input data XDATA is supplied to signal lines X[1] to X[m] at a predetermined timing by a clock signal XCLK, a start pulse XSP, and a latch signal XLAT. For example, as shown in FIG. 2A, circuit XCS includes a shift register SR1 and a latch circuit LAT1. Input data XDATA is assigned to each row by the clock signal XCLK and the start pulse XSP input to the shift register SR1 and held in the latch circuit LAT1. Then, input data XDATA is output to signal lines X[1] to X[m] at the timing of the latch signal XLAT.

[0038] Circuit WCS has D / A conversion circuits corresponding to each column of cell array CA, and can supply analog signals corresponding to weight data to cell IMs of each column of cell array CA from signal lines W[1] to W[n]. Circuit WCS may be referred to as a W driver. Also, signal lines W[1] to W[n] may be referred to as wiring WCL[1] to WCL[n].

[0039] Circuit WSD can supply a signal for selecting a row to be written in cell array CA from signal lines G[1] to G[m]. Circuit WSD may be referred to as a G driver. Also, signal lines G[1] to G[m] may be referred to as wiring WSL[1] to WSL[m].

[0040] The circuit ITRZ has an analog-to-digital (A / D) conversion circuit corresponding to each column of the cell array CA, and can acquire digital signals corresponding to the analog signals output from the cells IM of each column of the cell array CA to the signal lines Y[1] to Y[n]. The circuit ITRZ is sometimes called a Y driver. The signal lines Y[1] to Y[n] correspond to the signal lines W[1] to W[n], i.e., the wirings connected to the wirings WCL[1] to WCL[n].

[0041] The circuit ITRZ outputs output data YDATA acquired from each row of the cell array CA. The output data YDATA acquires analog signals from the signal lines Y[1] to Y[n] at predetermined timings based on a clock signal YCLK, a start pulse YSP, and a latch signal YLAT, and outputs the analog signals as digital output data YDATA. For example, as shown in FIG. 2B, the circuit ITRZ includes a shift register SR2, a latch circuit LAT2, and a switch SW_Y. The data on the signal lines Y[1] to Y[n] is held in the latch circuit LAT2. The data on the signal lines Y[1] to Y[n] held in the latch circuit LAT2 is output as output data YDATA when the switch SW_Y assigned to each column is turned on by the clock signal YCLK and start pulse YSP input to the shift register SR2.

[0042] Specific examples of the circuit XCS, the circuit WCS, the circuit WSD, the cell array CA, and the circuit ITRZ, and an example of their operation will be described in detail in the third embodiment.

[0043] Here, we will explain hierarchical neural networks. As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer. Figure 3A shows a network diagram of a three-layer perceptron, which is an example of a hierarchical neural network. In Figure 3A, the first layer corresponds to the input layer, the second layer corresponds to the intermediate layer, and the third layer corresponds to the output layer.

[0044] Each layer of the neural network has one or more neurons NU. In FIG. 3A, the first layer has m neurons, the second layer has n neurons, and the third layer has p neurons (n, m, and p are natural numbers greater than or equal to 2).

[0045] In the first layer, which is the input layer in FIG. 3A, data X1[1] to X1[m] are given to m neurons. The data X1[1] to X1[m] are output from each neuron in the first layer to each neuron in the second layer. Also, in the third layer, which is the output layer in FIG. 3A, data X2[1] to X2[n] are given to p neurons. The neurons in the output layer output data Y2[1] to Y2[p] obtained by performing a fully connected process on the data X2[1] to X2[n] and weight data W2[1] to W2[n] (not shown).

[0046] The signals input and output in the neurons of the second layer, which is the intermediate layer, will be described with reference to FIG. 3B. In FIG. 3B, data X1[1] to X1[m] input from each neuron in the first layer and weight data W1[1] to W1[m] that the neurons in the second layer have are shown. Also, in FIG. 3B, data Y1[1] to Y1[m] obtained by the sum-of-products operation of the input data X1[1] to X1[m] and the weight data W1[1] to W1[m] are shown. The data Y1[1] to Y1[m] are output as data X2[1] on which a non-linear operation based on the activation function f has been performed to each neuron in the third layer.

[0047] For example, for the data X1[1](t) to X1[m](t) of the t-th (t is a natural number greater than or equal to 2), in each layer of the neural network in FIG. 3A, each data is input and output as shown in FIG. 4A. Also, for the data X1[1](t - 1) to X1[m](t - 1) of the (t - 1)-th, in each layer of the neural network in FIG. 3A, each data is input and output as shown in FIG. 4B.

[0048] In this neural network, for the input t-th data X1[1](t) to X1[m](t), in the second layer which is the intermediate layer, a sum-of-products operation Y1[j](t)=ΣW1[i,j]X1[i](t) and a non-linear operation X2[j](t)=f(Y1[j](t)) are performed. In the third layer which is the output layer, a sum-of-products operation Y2[k](t)=ΣW2[j,k]X2[j](t) is executed. Similarly, for the input (t - 1)-th data X1[1](t - 1) to X1[m](t - 1), in the second layer which is the intermediate layer, a sum-of-products operation Y1[j](t - 1)=ΣW1[i,j]X1[i](t - 1) and a non-linear operation X2[j](t - 1)=f(Y1[j](t - 1)) are performed. In the third layer which is the output layer, a sum-of-products operation Y2[k](t)=ΣW2[j,k]X2[j](t - 1) is executed. Note that the layer performing the sum-of-products operation may be referred to as the first layer and the second layer. For example, the second layer which is the intermediate layer may be referred to as the first layer, and the third layer which is the output layer may be referred to as the second layer. Here, i, j, and k in each formula are natural numbers. Also, the non-linear operation is an operation by a non-linear function f(X) with respect to X. Examples of the non-linear function f(X) include the sigmoid function and the ReLU function.

[0049] FIG. 5 is a diagram showing the division of the area of the cell array CA shown in FIG. 1 corresponding to the neural network shown in FIGS. 4A and 4B. The area L1 is assigned to the m×n sum-of-products operation Y1[j](t)=ΣW1[i,j]X1[i](t) in the intermediate layer for the t-th data X1[1](t) to X1[m](t), and the area L2 is assigned to the n×p sum-of-products operation Y2[k](t - 1)=ΣW2[j,k]X2[j](t - 1) in the output layer for the (t - 1)-th data X1[1](t - 1) to X1[m](t - 1).

[0050] With the configuration of FIG. 5, it is possible to execute sum-of-products operations in multiple layers of a neural network using a single cell array CA, and it is possible to provide a low-power consumption arithmetic processing device that can efficiently execute arithmetic processing.

[0051] Fig. 6 is a timing chart when the cell array CA shown in Fig. 1 is divided into regions and operated as shown in Fig. 5. In the following explanation, it is assumed that weight data W1[i,j] is stored in cell IM in the i-th row and j-th column (i = 1 to m, j = 1 to n) of cell array CA. It is also assumed that weight data W2[i,j] is stored in cell IM in the (m+i)-th row and (n+j)-th column (i = 1 to n, j = 1 to p) of cell array CA.

[0052] At time TX0, the t-th data X1[1](t) through X1[m](t) and the hidden layer nonlinear operation data X2[1](t-1) through X2[n](t-1) for the (t-1)th data X1[1](t-1) through X1[m](t-1) are sequentially input to the circuit XCS. The hidden layer nonlinear operation data X2[1](t-1) through X2[n](t-1) for the t-th data X1[1](t) through X1[m](t) and the (t-1)th data X1[1](t-1) through X1[m](t-1) are sequentially captured into the latch circuit of the circuit XCS in synchronization with the clock signal XCLK.

[0053] At time TX1, the t-th analog signal y1[1](t-1) = Σw1[i,1]x1[i](t-1) to y1[n](t-1) = Σw1[i,n]x1[i](t-1) and the (t-2)-th analog signal y2[1](t-2) = Σw2[j,1]x2[j](t-2) to y2[p](t-2) = Σw2[j,p]x1[j](t-2) are determined in each column of the cell array CA and supplied to signal lines Y[1] to Y[n] and Y[n+1] to Y[n+p]. The A / D conversion circuits corresponding to each column of the cell array CA generate the (t-1)th output data Y1[1](t-1) to Y1[n](t-1) and the (t-2)th output data Y2[1](t-2) to Y2[p](t-2) corresponding to the (t-1)th analog signal y1[1](t-1) to y1[n](t-1) and the (t-2)th analog signal y2[1](t-2) to y2[p](t-2).

[0054] At time TX2, by setting the latch signal YLAT to H level, the (t-1)th data Y1[1](t-1) to Y1[n](t-1) and the (t-2)th data Y2[1](t-2) to Y2[l](t-2) are taken into the latch circuit of circuit ITRZ and output sequentially in synchronization with the clock signal YCLK.

[0055] At time TX3, by setting the latch signal XLAT to H level, the D / A conversion circuit corresponding to each row of the cell array CA generates the t-th analog signals x1[1](t) to x1[m](t) corresponding to the t-th data X1[1](t) to X1[m](t), and the (t-1)-th analog signals x2[1](t-1) to x2[n](t-1) corresponding to the intermediate layer nonlinear operation data X2[1](t-1) to X2[n](t-1) for the (t-1)-th data X1[1](t-1) to X1[m](t-1), and these are supplied to the signal lines X[1] to X[m], X[m+1] to X[m+n].

[0056] During the period (first period) from time TX0 to time TX3, the (t-1)th data X1[1](t-1) to X1[m](t-1) are input to area L1 (first region) in Fig. 5, and thereby the (t-1)th data Y1[1](t-1) to Y1[n](t-1) corresponding to the product-sum operation of area L1 can be output. Also, during the period (first period) from time TX0 to time TX3, the (t-2)th data X2[1](t-2) to X2[m](t-2) are input to area L2 (second region) in Fig. 5, and thereby the (t-2)th data Y2[1](t-2) to Y2[n](t-2) corresponding to the product-sum operation of area L2 can be output.

[0057] At time TX4, the (t+1)th data X1[1](t+1) through X1[m](t+1) and the hidden layer nonlinear operation data X2[1](t) through X2[n](t) for the t-th data X1[1](t) through X1[m](t) are sequentially input to the circuit XCS. The (t+1)th data X1[1](t+1) through X1[m](t+1) and the hidden layer nonlinear operation data X2[1](t) through X2[n](t) for the t-th data X1[1](t) through X1[m](t) are sequentially captured into the latch circuit of the circuit XCS in synchronization with the clock signal XCLK.

[0058] At time TX5, the t-th analog signal y1[1](t) = Σw1[i,1]x1[i](t) to y1[n](t) = Σw1[i,n]x1[i](t) and the (t-1)-th analog signal y2[1](t-1) = Σw2[j,1]x2[j](t-1) to y2[p](t-1) = Σw2[j,p]x1[j](t-1) in each column of the cell array CA are determined and supplied to signal lines Y[1] to Y[n] and Y[n+1] to Y[n+p]. The A / D conversion circuits corresponding to each column of the cell array CA generate the tth output data Y1[1](t) to Y1[n](t) and the (t-1)th output data Y2[1](t-1) to Y2[p](t-1) corresponding to the tth analog signal y1[1](t) to y1[n](t) and the (t-1)th analog signal y2[1](t-1) to y2[p](t-1).

[0059] At time TX6, by setting the latch signal YLAT to H level, the t-th data Y1[1](t) to Y1[n](t) and the (t-1)-th data Y2[1](t-1) to Y2[l](t-1) are taken into the latch circuit of the circuit ITRZ and output sequentially in synchronization with the clock signal YCLK.

[0060] At time TX7, by setting the latch signal XLAT to the H level, the D / A conversion circuits corresponding to each row of the cell array CA generate the (t + 1)-th analog signals x1[1](t + 1) to x1[m](t + 1) corresponding to the (t + 1)-th data X1[1](t + 1) to X1[m](t + 1), and the t-th analog signals x2[1](t) to x2[n](t) corresponding to the non-linear operation data X2[1](t) to X2[n](t) of the intermediate layer for the t-th data X1[1](t) to X1[m](t), and supply them to signal lines X[1] to X[m], X[m + 1] to X[m + n] (not shown).

[0061] During the period from time TX4 to time TX7 (the second period), in area L1 (the first region) of FIG. 5, when the t-th data X1[1](t) to X1[m](t) is input, the t-th data Y1[1](t) to Y1[n](t) corresponding to the product-sum operation of area L1 can be output. Also, during the period from time TX4 to time TX7 (the second period), in area L2 (the second region) of FIG. 5, when the (t - 1)-th data X2[1](t - 1) to X2[m](t - 1) is input, the (t - 1)-th data Y2[1](t - 1) to Y2[n](t - 1) corresponding to the product-sum operation of area L2 can be output.

[0062] Here, in accordance with the period of the clock signal YCLK, the t-th data Y1[1](t) to Y1[n](t) is output, and further, the non-linear operation X2[j](t)=f(Y1[j](t)) in the intermediate layer corresponding to the t-th data is executed, and the non-linear operation result is stored in a first-in first-out (FIFO). In accordance with the period of the clock signal XCLK, it is preferable to read out the non-linear operation data X2[1](t) to X2[n](t) from the FIFO. By adopting such a configuration, the operating speeds of the D / A conversion circuit and the A / D conversion circuit can be set to values suitable for each, so that power consumption can be reduced.

[0063] Furthermore, it is preferable to synchronize the period of the clock signal YCLK with the period of the clock signal XCLK, so that the timing of outputting the t-th data Y1[1](t) to Y1[n](t) and the timing of executing the nonlinear operation X2[j](t) = f(Y1[j](t)) in the intermediate layer corresponding to the t-th data are synchronized with the timing of inputting X2[j](t). This configuration eliminates the need for a mechanism such as a first-in-first-out (FIFO) to store the results of the nonlinear operation and read them out in synchronization with the clock signal XCLK, simplifying the configuration of the semiconductor device.

[0064] With the above configuration, a single cell array can perform product-sum operations equivalent to multiple layers of a neural network, providing a low-power processing device that can efficiently perform calculations.

[0065] (Embodiment 2) In this embodiment, a configuration different from that of the semiconductor device described in the above embodiment will be described. Note that the detailed description of the same configuration as in the first embodiment will be omitted, as the description is incorporated herein by reference.

[0066] In this embodiment, a case will be described in which calculations are performed in an example of the hierarchical neural network described in Fig. 3A of Embodiment 1. Fig. 7 shows, as an example, how, for the t-th (t is a natural number equal to or greater than 2) data X1[1](t) to X1[m](t), data X1[1](t) to X1[m](t) are input / output between the first and second layers of the neural network, and data X2[1](t) to X2[n](t) are input / output between the second and third layers of the neural network.

[0067] In this neural network, for the t-th input data X1[1](t) to X1[m](t), in the second layer (also referred to as the first layer) which is the intermediate layer, the product-sum operation Y1[j](t)=ΣW1[i,j]X1[i](t) and the non-linear operation X2[j](t)=f(Y1[j](t)) are performed. In the third layer (also referred to as the second layer) which is the output layer, the product-sum operation Y2[k](t)=ΣW2[j,k]X2[j](t) is executed. Here, i, j, and k in each formula are natural numbers. The non-linear operation is an operation by the non-linear function f(X) on X. Examples of the non-linear function f(X) include the sigmoid function and the ReLU function.

[0068] Figure 8 is a diagram showing the division of the area of the cell array CA corresponding to the neural network shown in Figure 7. The cell array CA shown in Figure 8 has cell IMs arranged in (m + n) rows and (n + p) columns, which are connected to the signal lines X[1] to X[m] and X[m + 1] to X[m + n], and the signal lines Y[1] to X[n] and X[n + 1] to X[n + p]. In the cell array CA shown in Figure 8, the t-th data X1[1](t) to X1[m](t) and the t-th data X2[1](t) to X2[n](t) are input to the signal lines X[1] to X[m + n]. In the cell array CA shown in Figure 8, the t-th data Y1[1](t) to Y1[n](t) and the t-th data Y2[1](t) to Y2[p](t) are output to the signal lines Y[1] to Y[n + p]. That is, the m-by-n product-sum operation Y1[j](t)=ΣW1[i,j]X1[i](t) in the second layer which is the intermediate layer for the t-th data X1[1](t) to X1[m](t) is assigned to area L1, and the n-by-p product-sum operation Y2[k](t)=ΣW2[j,k]X2[j](t) in the third layer which is the output layer for the t-th data X2[1](t) to X2[n](t) is assigned to area L2.

[0069] FIG. 9 is a driving timing chart of a semiconductor device in which the cell array CA is area-divided as shown in FIG. 8. It is assumed that weight data w1[i, j] is stored in the cell IM at the i-th row and j-th column (i = 1 to m, j = 1 to n) of the cell array CA. Also, it is assumed that weight data w2[i, j] is stored in the cell IM at the (m + i)-th row and (n + j)-th column (i = 1 to n, j = 1 to p) of the cell array CA.

[0070] At time TX10, analog signals x1[1](t) to x1[m](t) corresponding to the t-th data are supplied to signal lines X[1] to X[m]. In area L1 of the cell array CA, an operation corresponding to the product-sum operation ΣW1[i, j]X1[i](t) of m rows and n columns is executed.

[0071] At time TX11, the analog signals y1[1](t) = Σw1[i, 1]x1[i](t) to y1[n](t) = Σw1[i, n]x1[i](t) in each column of area L1 of the cell array CA are determined and supplied to signal lines Y[1] to Y[n].

[0072] At time TX12, analog signals x2[1](t) to x2[n](t) obtained by performing a non-linear operation on the analog signals y1[1](t) to y1[n](t) are supplied to signal lines X[m + 1] to X[m + n]. In area L2 of the cell array CA, an operation corresponding to the product-sum operation Σw2[j, k]x2[j](t) of n rows and p columns is executed.

[0073] At time TX13, the analog signals y2[1](t) = Σw2[j, 1]x2[j](t) to y2[l](t) = Σw2[j, n]x2[j](t) in each column of area L2 of the cell array CA are determined and supplied to signal lines Y[n + 1] to Y[n + p]. Here, the analog signals y2[1](t) to y2[p](t) correspond to the result of executing the arithmetic processing of the neural network in FIG. 7 for the t-th data.

[0074] At time TX20, analog signals x1[1](t+1) to x1[m](t+1) corresponding to the (t+1)th data are supplied to signal lines X[1] to X[m]. In area L1 of cell array CA, an operation corresponding to a product-sum operation Σw1[i,j]x1[i](t+1) of m rows and n columns is executed.

[0075] At time TX21, analog signals y1[1](t+1) = Σw1[i,1]x1[i](t+1) to y1[n](t+1) = Σw1[i,n]x1[i](t+1) of each column of area L1 of cell array CA are determined and supplied to signal lines Y[1] to Y[n].

[0076] At time TX22, analog signals x2[1](t+1) through x2[n](t+1) are generated by performing a nonlinear operation on analog signals y1[1](t+1) through y1[n](t+1), and the analog signals x2[1](t+1) through x2[n](t+1) are supplied to signal lines X[m+1] through X[m+n]. In area L2 of cell array CA, an operation equivalent to a product-sum operation Σw2[j,k]x2[j](t+1) of n rows and p columns is executed.

[0077] At time TX23, analog signals y2[1](t+1)=Σw2[j,1]x2[j](t+1) through y2[l](t+1)=Σw2[j,n]x2[j](t+1) for each column of area L2 of cell array CA are determined and supplied to signal lines Y[n+1] through Y[n+p]. Here, analog signals y2[1](t+1) through y2[l](t+1) correspond to the results of performing the neural network calculation process shown in FIG. 7 on the (t+1)th data.

[0078] FIG. 10 shows an example of the peripheral circuit of a semiconductor device MAC2 including a cell array CA enabling the arithmetic processing of the present embodiment. The semiconductor device MAC2 includes a circuit XCS, a circuit WCS, a circuit WSD, a cell array CA, a circuit ITRZ, and a circuit ACT. The cell array CA has cell IMs arranged in a matrix of (m + n) rows and (n + p) columns. As a difference from the semiconductor device MAC of the first embodiment, there is a point that a circuit ACT is provided between signal lines Y[1] to Y[n] and signal lines X[m + 1] to X[m + n].

[0079] The circuit ACT has a circuit having a function of performing a non-linear operation corresponding to each column of the cell array CA. The circuit ACT can obtain an analog signal obtained by performing a non-linear operation on the analog signals output from each column of the cell array CA to the signal lines Y[1] to Y[n]. Further, by outputting the analog signal to the signal lines X[m + 1] to X[m + n], it can be supplied to the cell IMs of each row of the cell array CA.

[0080] Note that it is preferable that the signal lines X[m + 1] to X[m + n] have a configuration in which an analog signal supplied from the circuit ACT and an analog signal supplied from the circuit XCS can be selectively supplied. Further, it is preferable that the signal lines Y[1] to Y[n] have a configuration in which an analog signal can be supplied not only to the circuit ACT but also to the circuit ITRZ. With such a configuration, the number of rows and columns of the areas L1 and L2 can be flexibly changed corresponding to the configuration of the neural network to be the object of the arithmetic processing. In addition to the configuration in which the supply of the analog signal from the circuit XCS or the circuit ACT can be selected for all of the signal lines X[1] to X[m + n], a configuration in which a plurality of lines can be selected as a group is also possible. Further, in addition to the configuration in which the analog signal can be selectively supplied from all of the signal lines Y[1] to Y[n + p] to the circuit ITRZ or the circuit ACT, a configuration in which a plurality of lines can be selected as a group is also possible. Furthermore, the signal lines X[1] to X[m + n] and the signal lines Y[1] to Y[n + p] that do not supply an analog signal can be appropriately electrically cut off by an analog switch or the like.

[0081] 11A shows an example of the configuration of a circuit ACT having a function of performing nonlinear calculations, in which two columns of a cell array CA are used as a pair when the weight data is positive and negative.

[0082] In the configuration shown in FIG. 11A, as shown in FIG. 11B, the paired signal lines Y P [j], Y N Analog current I flowing through [j] + , I - A configuration for performing nonlinear calculations according to the above will be described.

[0083] The analog current I shown in FIGS. 11A and 11B + is the current output from the column corresponding to the positive weight data. Also, the analog current I - is the current output from the column corresponding to the negative weight data. In the configuration shown in FIG. 11A, the circuit ACT + >I - , that is, when the net result of the multiply-and-accumulate operation is positive, (I + -I - ) is the analog current I RELU On the other hand, in the configuration shown in FIG. 11A, the circuit ACT outputs I + - , that is, when the net result of the multiply-and-accumulate operation is negative, the analog current I RELU In other words, an output equivalent to the result of performing a nonlinear operation using the ReLU function on the result of the sum-of-products operation can be obtained.

[0084] With the above configuration, it is possible to provide a low-power semiconductor device that can efficiently perform product-sum operations equivalent to multiple layers of a neural network using a single cell array without performing analog-to-digital conversion or digital-to-analog conversion in between.

[0085] (Embodiment 3) ​In this embodiment, a configuration example of the cell array and its peripheral circuits described in the above embodiment will be described.

[0086] <Configuration Example of Cell Array CA> FIG. 12 shows a configuration example of a semiconductor device that performs a sum-of-products operation on positive or "0" weight data and positive or "0" input data. The semiconductor device MAC1 shown in FIG. 12 performs a sum-of-products operation on weight data corresponding to the potential held in each cell and input input data (first data), and performs an activation function operation using intermediate data (second data) of the sum-of-products operation. Note that the weight data and the input data can be, for example, analog data or multi-valued data (discrete data).

[0087] The semiconductor device MAC1 includes a circuit WCS, a circuit XCS, a circuit WSD, a circuit SWS1, a circuit SWS2, a cell array CA, and circuits ITRZ[1] to ITRZ[n].

[0088] The cell array CA includes cells IM[1,1] to IM[m,n] (where m is an integer of 1 or more and n is an integer of 1 or more here), and cells IMref[1] to IMref[m]. Each of the cells IM[1,1] to IM[m,n] has a function of holding a potential corresponding to an electric current amount according to the weight data, and the cells IMref[1] to IMref[m] have a function of supplying a potential corresponding to the input data required for performing a sum-of-products operation with the held weight data to the wirings XCL[1] to XCL[m].

[0089] Note that in the cell array CA of FIG. 12, the cells are arranged in an (n + 1)×m matrix in the row direction and the column direction. However, the cell array CA may have a configuration in which the cells are arranged in a matrix with 2 or more cells in the row direction and 2 or more cells in the column direction. When applying the semiconductor device MAC and the semiconductor device MAC2 described in the first and second embodiments, a configuration in which cells IM corresponding to each region are provided may be employed.

[0090] Each of cells IM[1,1] to IM[m,n] has, as an example, transistor F1, transistor F2, and capacitor C5, and each of cells IMref[1] to IMref[m] has, as an example, transistor F1m, transistor F2m, and capacitor C5m.

[0091] In particular, it is preferable that the sizes (e.g., channel length, channel width, transistor configuration, etc.) of transistor F1 included in each of cells IM[1,1] to IM[m,n] are equal to each other, and it is preferable that the sizes of transistor F2 included in each of cells IM[1,1] to IM[m,n] are equal to each other. Also, it is preferable that the sizes of transistor F1m included in each of cells IMref[1] to IMref[m] are equal to each other, and it is preferable that the sizes of transistor F2m included in each of cells IMref[1] to IMref[m] are equal to each other. Further, it is preferable that the size of transistor F1 is equal to the size of transistor F1m, and it is preferable that the size of transistor F2 is equal to the size of transistor F2m.

[0092] By making the transistor sizes equal to each other, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the size of the transistor F1 included in each of cells IM[1,1] to IM[m,n] equal and making the size of the transistor F2 included in each of cells IM[1,1] to IM[m,n] equal, each of cells IM[1,1] to IM[m,n] can perform approximately the same operation under the same conditions. Here, the same conditions refer to, for example, the input potentials to the source, drain, gate, etc. of transistor F1, the input potentials to the source, drain, gate, etc. of transistor F2, and the voltages input to each of cells IM[1,1] to IM[m,n]. Furthermore, by making the size of the transistor F1m included in each of cells IMref[1] to IMref[m] equal and making the size of the transistor F2m included in each of cells IMref[1] to IMref[m] equal, for example, the operation and results of the operation of cells IMref[1] to IMref[m] can be made approximately the same. They can perform substantially the same operation under the same conditions, which means, for example, the input potentials to the source, drain, gate, etc. of transistor F1m, the input potentials to the source, drain, gate, etc. of transistor F2m, and the voltages input to each of cells IMref[1] to IMref[m].

[0093] Unless otherwise specified, the transistors F1 and F1m are considered to ultimately operate in a linear region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors are considered to include a voltage range in which they operate in a linear region. However, one embodiment of the present invention is not limited to this. For example, the transistors F1 and F1m may operate in a saturation region when they are on, or may operate in both the linear region and the saturation region.

[0094] Also, unless otherwise specified, the transistors F2 and F2m operate in the subthreshold region (that is, in the transistors F2 or F2m, when the gate-source voltage is lower than the threshold voltage, more preferably, when the drain current increases exponentially with respect to the gate-source voltage). That is, each of the gate voltage, source voltage, and drain voltage of each of the transistors described above includes the case where it is in the voltage range operating in the subthreshold region. Therefore, the transistors F2 and F2m include the case where they operate so that an off-current flows between the source and the drain.

[0095] Also, the transistor F1 and / or the transistor F1m is preferably, as an example, a transistor (also referred to as an OS transistor) having a metal oxide (also referred to as an oxide semiconductor) in the channel formation region. In addition, the channel formation region of the transistor F1 and / or the transistor F1m is more preferably an oxide containing at least one of indium, gallium, and zinc. Further, instead of the oxide, an oxide containing at least one of indium, element M (element M includes, for example, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.), and zinc may be used.

[0096] By using OS transistors as the transistors F1 and / or F1m, leakage current of the transistors F1 and / or F1m can be suppressed, thereby reducing the power consumption of the semiconductor device. Specifically, when the transistors F1 and / or F1m are off, leakage current from the retention node to the wiring XCL or WCL can be significantly reduced, thereby reducing the number of refresh operations for the potential of the retention node. Furthermore, reducing the number of refresh operations can reduce the power consumption of the semiconductor device. Furthermore, by significantly reducing the leakage current from the retention node to the wiring WCL or XCL, the cell can retain the potential of the retention node for a long time, thereby improving the operation accuracy of the semiconductor device.

[0097] Furthermore, by using an OS transistor for the transistor F2 and / or the transistor F2m, the transistors can operate over a wide current range in the subthreshold region, thereby reducing current consumption. Furthermore, by using an OS transistor for the transistor F2 and / or the transistor F2m, the transistors can be manufactured simultaneously with the transistors F1 and F1m, which may shorten the manufacturing process of the semiconductor device. The transistors F2 and / or the transistor F2m can be transistors containing silicon in their channel formation regions (hereinafter referred to as Si transistors) other than OS transistors. Examples of silicon that can be used include amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, and single-crystal silicon.

[0098] Incidentally, when a semiconductor device or the like is highly integrated into a chip or the like, heat may be generated in the chip due to the driving of the circuit. Due to this heat generation, when the temperature of the transistor rises, the characteristics of the transistor may change, and a change in the field-effect mobility or a decrease in the operating frequency may occur. Since the OS transistor has higher heat resistance than the Si transistor, a change in the field-effect mobility due to a temperature change is less likely to occur, and a decrease in the operating frequency is also less likely to occur. Therefore, by using the OS transistor, it is easy to perform operations, processing, etc. even in a high-temperature environment. Therefore, when configuring a semiconductor device that is resistant to heat generation due to driving, it is preferable to apply the OS transistor as the transistor.

[0099] In each of cells IM[1,1] to IM[m,n], the first terminal of transistor F1 is electrically connected to the gate of transistor F2. The first terminal of transistor F2 is electrically connected to wiring VE. The first terminal of capacitor C5 is electrically connected to the gate of transistor F2.

[0100] Also, in each of cells IMref[1] to IMref[m], the first terminal of transistor F1m is electrically connected to the gate of transistor F2m. The first terminal of transistor F2m is electrically connected to wiring VE. The first terminal of capacitor C5m is electrically connected to the gate of transistor F2m.

[0101] In FIG. 12, back gates are shown for transistors F1, F2, F1m, and F2m, and although the connection configuration of the back gates is not shown, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-current of the transistor. That is, for example, the gate and the back gate of transistor F1 may be electrically connected, or the gate and the back gate of transistor F1m may be electrically connected. Also, for example, in a transistor having a back gate, in order to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, a wiring for electrically connecting the back gate of the transistor to an external circuit or the like may be provided, and a configuration may be adopted in which a potential is applied to the back gate of the transistor by the external circuit or the like.

[0102] Also, transistors F1 and F2 shown in FIG. 12 have back gates, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, transistors F1 and F2 shown in FIG. 12 may be configured not to have back gates, that is, may be transistors having a single-gate structure. Also, some transistors may have a configuration with a back gate, and another part of the transistors may have a configuration without a back gate.

[0103] In addition, although the transistors F1 and F2 illustrated in FIG. 12 are n-channel transistors, the semiconductor device according to one aspect of the present invention is not limited thereto. For example, some or all of the transistors F1 and F2 may be replaced with p-channel transistors. When some or all of the transistors F1 and F, are replaced with p-channel transistors, the voltage applied by the wiring, the potential of the node NN, the potential of the node NNref, etc., described in the specification or the like may be changed as necessary so that the transistors F1 and F2 operate as desired.

[0104] Note that the modification examples regarding the structure and polarity of the above transistors are not limited to only the transistors F1 and F2. For example, the same applies to the transistors F1m, F2m, transistors F3[1] to F3[n], transistors F4[1] to F4[n], which will be described later, and also to the transistors described in other parts of the specification or illustrated in other drawings, and their structure or polarity may be changed in the same manner.

[0105] The wiring VE is a wiring for flowing a current between the first terminal and the second terminal of each transistor F2 of the cells IM[1,1], IM[m,1], IM[1,n], and IM[m,n], and also functions as a wiring for flowing a current between the first terminal and the second terminal of each transistor F2m of the cells IMref[1] and IMref[m]. As an example, the wiring VE functions as a wiring for supplying a constant voltage. The constant voltage can be, for example, a low-level potential, a ground potential, or the like.

[0106] In cell IM[1,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1], and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In FIG. 12, in cell IM[1,1], the connection point of the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 is defined as node NN[1,1].

[0107] In cell IM[m,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1], and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In FIG. 12, in cell IM[m,1], the connection point of the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 is defined as node NN[m,1].

[0108] In cell IM[1,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n], and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[n], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In FIG. 12, in cell IM[1,n], the connection point of the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 is defined as node NN[1,n].

[0109] In cell IM[m,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n], and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[n], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In FIG. 12, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[m,n] is designated as node NN[m,n].

[0110] In cell IMref[1], the second terminal of transistor F1m is electrically connected to line XCL[1], and the gate of transistor F1m is electrically connected to line WSL[1]. The second terminal of transistor F2m is electrically connected to line XCL[1], and the second terminal of capacitor C5 is electrically connected to line XCL[1]. In FIG. 12, the connection point between the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5 in cell IMref[1] is referred to as node NNref[1].

[0111] In cell IMref[m], the second terminal of transistor F1m is electrically connected to line XCL[m], and the gate of transistor F1m is electrically connected to line WSL[m]. The second terminal of transistor F2m is electrically connected to line XCL[m], and the second terminal of capacitor C5 is electrically connected to line XCL[m]. In FIG. 12, the connection point between the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5 in cell IMref[m] is referred to as node NNref[m].

[0112] Note that the nodes NN[1,1] to NN[m,n] and the nodes NNref[1] to NNref[m] function as holding nodes for the respective cells.

[0113] In cells IM[1,1] to IM[m,n], for example, when transistor F1 is in the on state, transistor F2 has a diode-connected configuration. With the constant voltage provided by wiring VE set to the ground potential (GND), when transistor F1 is in the on state and a current of current amount I flows from wiring WCL to the second terminal of transistor F2, the potential of the gate (node NN) of transistor F2 is determined according to the current amount I. Note that the potential of the second terminal of transistor F2 is ideally equal to the gate (node NN) of transistor F2 because transistor F1 is in the on state. Here, by turning off transistor F1, the potential of the gate (node NN) of transistor F2 is held. As a result, transistor F2 can cause a current of current amount I corresponding to the ground potential of the first terminal of transistor F2 and the potential of the gate (node NN) of transistor F2 to flow between the source and drain of transistor F2. In this specification and the like, such an operation is referred to as "setting (programming) the current amount flowing between the source and drain of transistor F2 in cell IM to I".

[0114] As an example, circuit SWS1 includes transistors F3[1] to F3[n]. The first terminal of transistor F3[1] is electrically connected to wiring WCL[1], the second terminal of transistor F3[1] is electrically connected to circuit WCS, and the gate of transistor F3[1] is electrically connected to wiring SWL1. The first terminal of transistor F3[n] is electrically connected to wiring WCL[n], the second terminal of transistor F3[n] is electrically connected to circuit WCS, and the gate of transistor F3[n] is electrically connected to wiring SWL1.

[0115] For each of transistors F3[1] to F3[n], for example, a transistor applicable to transistor F1 and / or transistor F2 can be used. In particular, it is preferable to use an OS transistor for each of transistors F3[1] to F3[n].

[0116] The circuit SWS1 functions as a circuit that makes the connection between the circuit WCS and each of the wirings WCL[1] to WCL[n] conductive or non-conductive.

[0117] The circuit SWS2, as an example, has transistors F4[1] to F4[n]. The first terminal of transistor F4[1] is electrically connected to the wiring WCL[1], the second terminal of transistor F4[1] is electrically connected to the input terminal of the circuit ITRZ[1], and the gate of transistor F4[1] is electrically connected to the wiring SWL2. The first terminal of transistor F4[n] is electrically connected to the wiring WCL[n], the second terminal of transistor F4[n] is electrically connected to the input terminal of the circuit ITRZ[n], and the gate of transistor F4[n] is electrically connected to the wiring SWL2.

[0118] As each of the transistors F4[1] to F4[n], for example, a transistor applicable to the transistor F1 and / or the transistor F2 can be used. In particular, it is preferable to use an OS transistor as each of the transistors F4[1] to F4[n].

[0119] The circuit SWS2 has a function of making the connection between the wiring WCL[1] and the circuit ITRZ[1], and between the wiring WCL[n] and the circuit ITRZ[n] conductive or non-conductive.

[0120] The circuit WCS has a function of supplying data for storage in each cell of the cell array CA.

[0121] The circuit XCS is electrically connected to the wirings XCL[1] to XCL[m]. The circuit XCS has a function of passing a current amount corresponding to the reference data described later, or a current amount corresponding to the input data, through each of the cells IMref[1] to IMref[m] of the cell array CA.

[0122] The circuit WSD is electrically connected to the wirings WSL[1] to WSL[m]. When writing weight data to the cells IM[1,1] to IM[m,n], the circuit WSD has a function of selecting a row of the cell array CA to which the weight data is to be written by supplying a predetermined signal to the wirings WSL[1] to WSL[m]. In other words, the wirings WSL[1] to WSL[m] function as write word lines.

[0123] For example, the circuit WSD is electrically connected to the wiring SWL1 and the wiring SWL2. The circuit WSD has a function of bringing the circuit WCS and the cell array CA into a conductive state or a non-conductive state by supplying a predetermined signal to the wiring SWL1, and a function of bringing the circuits ITRZ[1] to ITRZ[n] and the cell array CA into a conductive state or a non-conductive state by supplying a predetermined signal to the wiring SWL2.

[0124] Each of the circuits ITRZ[1] to ITRZ[n] has, for example, an input terminal and an output terminal. For example, the output terminal of the circuit ITRZ[1] is electrically connected to a wiring OL[1], and the output terminal of the circuit ITRZ[n] is electrically connected to a wiring OL[n].

[0125] Each of the circuits ITRZ[1] to ITRZ[n] has a function of receiving a current input to an input terminal, converting the current into a voltage corresponding to the amount of the current, and outputting the voltage from an output terminal. The voltage may be, for example, an analog voltage or a digital voltage. Each of the circuits ITRZ[1] to ITRZ[n] may include a semiconductor device that performs a function operation. In this case, for example, the semiconductor device may perform a function operation using the converted voltage, and the result of the operation may be output to the wirings OL[1] to OL[n].

[0126] In particular, when performing calculations on a hierarchical neural network, the nonlinear functions that can be used include, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, and a threshold function.

[0127] <Configuration example of circuit WCS and circuit XCS> The configuration examples of circuit WCS and circuit XCS will be described.

[0128] First, circuit WCS will be described. FIG. 13A is a block diagram showing an example of circuit WCS. In addition, in FIG. 13A, in order to show the electrical connection with the circuits around circuit WCS, circuit SWS1, transistor F3, wiring SWL1, and wiring WCL are also shown. Further, transistor F3 is any one of transistors F3[1] to F3[n] included in semiconductor device MAC1 in FIG. 12, and wiring WCL is any one of wirings WCL[1] to WCL[n] included in semiconductor device MAC1 in FIG. 12.

[0129] The circuit WCS shown in FIG. 13A has a switch SWW as an example. The first terminal of switch SWW is electrically connected to the second terminal of transistor F3, and the second terminal of switch SWW is electrically connected to wiring VINIL1. Wiring VINIL1 functions as a wiring that gives an initialization potential to wiring WCL, and as the initialization potential, a ground potential (GND), a low-level potential, a high-level potential, etc. can be used. Note that switch SWW is in an on state only when giving an initialization potential to wiring WCL, and is in an off state at other times.

[0130] As switch SWW, for example, an electrical switch such as an analog switch or a transistor can be applied. Note that when applying a transistor as switch SWW, for example, the transistor can be a transistor having the same structure as transistors F1 and F2. Also, other than an electrical switch, a mechanical switch may be applied.

[0131] Also, the circuit WCS in FIG. 13A has a plurality of current sources CS as an example. Specifically, circuit WCS is K bits (2 Khas a function of outputting weight data of values) (K is an integer of 1 or more) as a current amount. In this case, the circuit WCS is 2 K - has one current source CS. The circuit WCS has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and two current sources CS that output information corresponding to the value of the K-bit as a current K-1 has.

[0132] In FIG. 13A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is electrically connected to the second terminal of the transistor F3 included in the circuit SWS1. The terminal T2 of one current source CS is electrically connected to the wiring DW[1], and each of the terminals T2 of the two current sources CS is electrically connected to the wiring DW[2], and 2 K-1 each of the terminals T2 of the current sources CS is electrically connected to the wiring DW[K].

[0133] The plurality of current sources CS included in the circuit WCS each have a function of outputting the same constant current I Wut from the terminal T1. In actuality, in the manufacturing stage of the semiconductor device MAC1, an error may appear due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the error of the constant current I Wut output from each of the terminals T1 of the plurality of current sources CS is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, it is described that there is no error in the constant current I Wut output from the terminals T1 of the plurality of current sources CS included in the circuit WCS.

[0134] The wirings DW[1] to DW[K] function as wirings for transmitting a control signal for outputting the constant current I Wut from the electrically connected current source CS. Specifically, for example, when a high-level potential is applied to the wiring DW[1], the current source CS electrically connected to the wiring DW[1] outputs I as a constant currentWut flows to the second terminal of the transistor F3, and when a low-level potential is applied to the wiring DW[1], the current source CS electrically connected to the wiring DW[1] flows as follows: Wut For example, when a high-level potential is applied to the wiring DW[2], the two current sources CS electrically connected to the wiring DW[2] output a total of 2I Wut When a constant current of 2I flows to the second terminal of the transistor F3 and a low-level potential is applied to the wiring DW[2], the current source CS electrically connected to the wiring DW[2] flows through the second terminal of the transistor F3. Wut For example, when a high-level potential is applied to the wiring DW[K], the 2 K-1 The current sources CS are K-1 I Wut When a constant current of 100 V flows to the second terminal of the transistor F3 and a low-level potential is applied to the wiring DW[K], the current source CS electrically connected to the wiring DW[K] has a total of 2 K-1 I Wut The constant current is not output.

[0135] The current flowing from one current source CS electrically connected to the wiring DW[1] corresponds to the value of the first bit, the current flowing from two current sources CS electrically connected to the wiring DW[2] corresponds to the value of the second bit, and the amount of current flowing from K current sources CS electrically connected to the wiring DW[K] corresponds to the value of the Kth bit. Here, consider the circuit WCS when K is 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", a high-level potential is applied to the wiring DW[1] and a low-level potential is applied to the wiring DW[2]. At this time, a constant current I is supplied from the circuit WCS to the second terminal of the transistor F3 of the circuit SWS1. Wut Also, for example, when the value of the first bit is "0" and the value of the second bit is "1", a low level potential is applied to the wire DW[1] and a high level potential is applied to the wire DW[2]. At this time, a constant current of 2I flows from the circuit WCS to the second terminal of the transistor F3 of the circuit SWS1. WutAlso, for example, when the value of the first bit is "1" and the value of the second bit is "1", a high level potential is applied to the wires DW[1] and DW[2]. At this time, a constant current of 3I flows from the circuit WCS to the second terminal of the transistor F3 of the circuit SWS1. Wut Furthermore, for example, when the value of the first bit is "0" and the value of the second bit is "0", a low-level potential is applied to the wires DW[1] and DW[2]. At this time, no constant current flows from the circuit WCS to the second terminal of the transistor F3 of the circuit SWS1.

[0136] 13A illustrates the circuit WCS when K is an integer equal to or greater than 3, but when K is 1, the circuit WCS in FIG. 13A may be configured without a current source CS electrically connected to the wirings DW[2] to DW[K]. When K is 2, the circuit WCS in FIG. 13A may be configured without a current source CS electrically connected to the wirings DW[3] to DW[K].

[0137] Next, a specific example of the configuration of the current source CS will be described.

[0138] The current source CS1 shown in FIG. 14A is a circuit that can be applied to the current source CS included in the circuit WCS in FIG. 13A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.

[0139] A first terminal of the transistor Tr1 is electrically connected to the wiring VDDL, and a second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. A second terminal of the transistor Tr2 is electrically connected to the terminal T1, and a gate of the transistor Tr2 is electrically connected to the terminal T2. The terminal T2 is also electrically connected to the wiring DW.

[0140] The wiring DW is any one of the wirings DW[1] to DW[K] in FIG. 13A.

[0141] The wiring VDDL functions as a wiring that supplies a constant voltage. As the constant voltage, for example, it can be a high-level potential.

[0142] When the constant voltage supplied by the wiring VDDL is a high-level potential, a high-level potential is input to the first terminal of the transistor Tr1. Also, the potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. At this time, the first terminal of the transistor Tr1 functions as a drain, and the second terminal of the transistor Tr1 functions as a source. Further, since the gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected, the gate-source voltage of the transistor Tr1 becomes 0V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current (drain current) within the current range of the subthreshold region flows between the first terminal and the second terminal of the transistor Tr1. As the amount of this current, when the transistor Tr1 is an OS transistor, for example, it is preferably -8 1.0×1 -12 0^-6 A or less, more preferably -15 1.0×1 Wut 0^-7 A or less, and even more preferably Xut 1.0×1

[0143] 0^-8 A or less. Also, for example, it is more preferably within a range where the current increases exponentially with respect to the gate-source voltage. That is, the transistor Tr1 functions as a current source for flowing a current within the current range when operating in the subthreshold region. Note that the current corresponds to the above-described I Wut or the I Xut to be described later.

[0143] Transistor Tr2 functions as a switching element. When the potential of the first terminal of transistor Tr2 is higher than the potential of the second terminal of transistor Tr2, the first terminal of transistor Tr2 functions as a drain, and the second terminal of transistor Tr2 functions as a source. Because the back gate of transistor Tr2 and the second terminal of transistor Tr2 are electrically connected, the back gate-source voltage is 0 V. Therefore, when the threshold voltage of transistor Tr2 is within an appropriate range, transistor Tr2 is turned on when a high-level potential is input to the gate of transistor Tr2, and turned off when a low-level potential is input to the gate of transistor Tr2. Specifically, when transistor Tr2 is on, a current in the subthreshold region flows from the second terminal of transistor Tr1 to terminal T1. When transistor Tr2 is off, the current does not flow from the second terminal of transistor Tr1 to terminal T1.

[0144] Note that the circuit applicable to the current source CS included in the circuit WCS of FIG. 13A is not limited to the current source CS1 of FIG. 14A. For example, while the current source CS1 is configured such that the back gate of the transistor Tr2 is electrically connected to the second terminal of the transistor Tr2, the back gate of the transistor Tr2 may be electrically connected to a separate wiring. An example of such a configuration is shown in FIG. 14B. The current source CS2 shown in FIG. 14B is configured such that the back gate of the transistor Tr2 is electrically connected to a wiring VTHL. By electrically connecting the wiring VTHL to an external circuit or the like, the current source CS2 can apply a predetermined potential to the wiring VTHL via the external circuit or the like, thereby applying the predetermined potential to the back gate of the transistor Tr2. This allows the threshold voltage of the transistor Tr2 to be varied. In particular, increasing the threshold voltage of the transistor Tr2 can reduce the off-state current of the transistor Tr2.

[0145] Also, for example, the current source CS1 has a configuration in which the back gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected, but the voltage may be held by a capacitor between the back gate and the second terminal of the transistor Tr2. Such a configuration example is shown in FIG. 14C. The current source CS3 shown in FIG. 14C includes a transistor Tr3 and a capacitor C6 in addition to the transistor Tr1 and the transistor Tr2. The current source CS3 is different from the current source CS1 in that the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 are electrically connected via the capacitor C6, and the back gate of the transistor Tr1 and the first terminal of the transistor Tr3 are electrically connected. Also, the current source CS3 has a configuration in which the second terminal of the transistor Tr3 is electrically connected to the wiring VTL and the gate of the transistor Tr3 is electrically connected to the wiring VWL. The current source CS3 can make the connection between the wiring VTL and the back gate of the transistor Tr1 conductive by applying a high-level potential to the wiring VWL to turn on the transistor Tr3. At this time, a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr1. Then, by applying a low-level potential to the wiring VWL to turn off the transistor Tr3, the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 can be held by the capacitor C6. That is, by determining the voltage applied from the wiring VTL to the back gate of the transistor Tr1, the threshold voltage of the transistor Tr1 can be varied, and the threshold voltage of the transistor Tr1 can be fixed by the transistor Tr3 and the capacitor C6.

[0146] Also, for example, as a circuit applicable to the current source CS included in the circuit WCS of FIG. 13A, it may be the current source CS4 shown in FIG. 14D. The current source CS4 has a configuration in which, in the current source CS3 of FIG. 14C, the back gate of the transistor Tr2 is electrically connected not to the second terminal of the transistor Tr2 but to the wiring VTHL. That is, similar to the current source CS2 in FIG. 14B, the current source CS4 can vary the threshold voltage of the transistor Tr2 according to the potential provided by the wiring VTHL.

[0147] In the current source CS4, when a large current flows between the first terminal and the second terminal of the transistor Tr1, in order to flow the current from the terminal T1 to the outside of the current source CS4, it is necessary to increase the on-current of the transistor Tr2. In this case, the current source CS4 applies a high-level potential to the wiring VTHL, lowers the threshold voltage of the transistor Tr2, and increases the on-current of the transistor Tr2, so that the large current flowing between the first terminal and the second terminal of the transistor Tr1 can be flowed from the terminal T1 to the outside of the current source CS4.

[0148] By applying the current sources CS1 to CS4 shown in FIGS. 14A to 14D as the current source CS included in the circuit WCS of FIG. 13A, the circuit WCS can output a current corresponding to the K-bit weight data. Also, the amount of the current can be, for example, the amount of current flowing between the first terminal and the second terminal within the range where the transistor F1 operates in the subthreshold region.

[0149] Also, as the circuit WCS of FIG. 13A, the circuit WCS shown in FIG. 13B may be applied. The circuit WCS of FIG. 13B has a configuration in which one current source CS of FIG. 14A is connected to each of the wirings DW[1] to DW[K]. Also, when the channel width of the transistor Tr1[1] is w[1], the channel width of the transistor Tr1[2] is w[2], and the channel width of the transistor Tr1[K] is w[K], the ratio of the respective channel widths is w[1]:w[2]:w[K]=1:2:2 K-1Since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the circuit WCS shown in Fig. 13B can output a current according to K-bit weight data, just like the circuit WCS in Fig. 13A.

[0150] Note that the transistor Tr1 (including transistors Tr1[1] to Tr2[K]), the transistor Tr2 (including transistors Tr2[1] to Tr2[K]), and the transistor Tr3 can be, for example, a transistor that can be used for the transistor F1 and / or the transistor F2. In particular, it is preferable to use OS transistors as the transistor Tr1 (including transistors Tr1[1] to Tr2[K]), the transistor Tr2 (including transistors Tr2[1] to Tr2[K]), and the transistor Tr3.

[0151] Next, a specific example of the circuit XCS will be described.

[0152] 13C is a block diagram showing an example of the circuit XCS. In addition, in order to show the electrical connection of the circuit WCS with the peripheral circuits, the wiring XCL is also shown in FIG. 13C. The wiring XCL is any one of the wirings XCL[1] to XCL[m] included in the semiconductor device MAC1 of FIG. 12.

[0153] The circuit XCS shown in FIG. 13C includes, as an example, a switch SWX. A first terminal of the switch SWX is electrically connected to the wiring XCL and a plurality of current sources CS, and a second terminal of the switch SWX is electrically connected to the wiring VINIL2. The wiring VINIL2 functions as a wiring that applies an initialization potential to the wiring XCL, and the initialization potential can be a ground potential (GND), a low-level potential, a high-level potential, or the like. The initialization potential applied by the wiring VINIL2 may be equal to the potential applied by the wiring VINIL1. Note that the switch SWX is turned on only when the initialization potential is applied to the wiring XCL, and is turned off otherwise.

[0154] As the switch SWX, for example, it can be a switch applicable to the switch SWW.

[0155] Also, the circuit configuration of the circuit XCS in FIG. 13C can be made substantially the same as that of the circuit WCS in FIG. 14A. Specifically, the circuit XCS has a function of outputting reference data as a current amount, and a function of outputting input data of L bits (2 L values) (L is an integer of 1 or more) as a current amount. In this case, the circuit XCS has 2 L -1 current sources CS. Note that the circuit XCS has 1 current source CS that outputs information corresponding to the value of the first bit as a current, 2 current sources CS that output information corresponding to the value of the second bit as a current, and 2 L-1 current sources CS that output information corresponding to the value of the Lth bit as a current.

[0156] By the way, as the reference data output as a current by the circuit XCS, for example, it can be information where the value of the first bit is "1" and the values of the bits after the second bit are "0".

[0157] In FIG. 13C, the terminal T2 of 1 current source CS is electrically connected to the wiring DX[1], each of the terminals T2 of 2 current sources CS is electrically connected to the wiring DX[2], and 2 L-1 each of the terminals T2 of the current sources CS is electrically connected to the wiring DX[L].

[0158] The plurality of current sources CS included in the circuit XCS each have a function of outputting I Xut as the same constant current from the terminal T1. Also, the wirings DX[1] to DX[L] are electrically connected to the current sources CS from which I XutIt functions as a wiring for transmitting a control signal for output. That is, the circuit XCS has a function of flowing a current amount corresponding to the L-bit information sent from the wirings DX[1] to DX[L] through the wiring XCL. Note that the control signals transmitted to the wirings DX[1] to DX[L] can be transmitted to each row by the shift register, latch circuit, etc. described in the first embodiment.

[0159] Specifically, here, consider the circuit XCS when L is 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", a high-level potential is applied to the wiring DX[1], and a low-level potential is applied to the wiring DX[2]. At this time, a constant current I Xut flows from the circuit XCS through the wiring XCL. Also, for example, when the value of the first bit is "0" and the value of the second bit is "1", a low-level potential is applied to the wiring DX[1], and a high-level potential is applied to the wiring DX[2]. At this time, a constant current 2I Xut flows from the circuit XCS through the wiring XCL. Also, for example, when the value of the first bit is "1" and the value of the second bit is "1", high-level potentials are applied to both the wiring DX[1] and the wiring DX[2]. At this time, a constant current 3I Xut flows from the circuit XCS through the wiring XCL. Also, for example, when the value of the first bit is "0" and the value of the second bit is "0", low-level potentials are applied to both the wiring DX[1] and the wiring DX[2]. At this time, no constant current flows from the circuit XCS through the wiring XCL. Note that in this case, in this specification, etc., it may be rephrased as a current with a current amount of 0 flows from the circuit XCS through the wiring XCL. Also, the current amounts 0, I Xut , 2I Xut , 3I Xut etc. output by the circuit XCS can be used as input data output by the circuit XCS. In particular, the current amount I Xut output by the circuit XCS can be used as reference data output by the circuit XCS.

[0160] In addition, if an error occurs due to variations in the electrical characteristics of the transistors included in each current source CS of the circuit XCS, the constant current I output from each of the terminals T1 of the multiple current sources CS will Xut The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of each of the multiple current sources CS included in the circuit XCS is Xut In the following description, it is assumed that there is no error.

[0161] 14A to 14D can be used as the current source CS of the circuit XCS, similar to the current source CS of the circuit WCS. In this case, the wiring DW shown in FIGS. 14A to 14D can be replaced with the wiring DX. This allows the circuit XCS to pass a current in the subthreshold current range through the wiring XCL as reference data or L-bit input data.

[0162] Furthermore, the circuit XCS in Fig. 13C can have the same circuit configuration as the circuit WCS shown in Fig. 13B. In this case, the circuit WCS shown in Fig. 13B can be replaced with the circuit XCS, the wiring DW[1] with the wiring DX[1], the wiring DW[2] with the wiring DX[2], the wiring DW[K] with the wiring DX[L], the switch SWW with the switch SWX, and the wiring VINIL1 with the wiring VINIL2.

[0163] <Example of circuit ITRZ configuration> Here, a configuration example of a circuit that can be applied to the circuits ITRZ[1] to ITRZ[n] included in the semiconductor device MAC1 in FIG. 12 will be described.

[0164] The circuit ITRZ1 shown in Fig. 15A is an example of a circuit that can be applied to the circuits ITRZ[1] to ITRZ[n] in Fig. 12. Note that Fig. 15A also illustrates a circuit SWS2, wiring WCL, wiring SWL2, and a transistor F4 in order to show the electrical connection of the circuit ITRZ1 with peripheral circuits. The wiring WCL is any one of the wirings WCL[1] to WCL[n] included in the semiconductor device MAC1 in Fig. 12, and the transistor F4 is any one of the transistors F4[1] to F4[n] included in the semiconductor device MAC1 in Fig. 12.

[0165] The circuit ITRZ1 in FIG. 15A is electrically connected to the wiring WCL via a transistor F4. The circuit ITRZ1 is also electrically connected to the wiring OL. The circuit ITRZ1 has a function of converting the amount of current flowing from the circuit ITRZ1 to the wiring WCL or the amount of current flowing from the wiring WCL to the circuit ITRZ1 into an analog voltage and outputting the analog voltage to the wiring OL. In other words, the circuit ITRZ1 has a current-voltage conversion circuit.

[0166] The circuit ITRZ1 in FIG. 15A includes, as an example, a resistor R5 and an operational amplifier OP1.

[0167] The inverting input terminal of the operational amplifier OP1 is electrically connected to the first terminal of the resistor R5 and the second terminal of the transistor F4. The non-inverting input terminal of the operational amplifier OP1 is electrically connected to the wiring VRL. The output terminal of the operational amplifier OP1 is electrically connected to the second terminal of the resistor R5 and the wiring OL.

[0168] The wiring VRL functions as a wiring that applies a constant voltage, which may be, for example, a ground potential (GND) or a low-level potential.

[0169] By configuring the circuit ITRZ1 as shown in Fig. 15A, the amount of current flowing into the circuit ITRZ1 from the wiring WCL via the transistor F4, or the amount of current flowing from the circuit ITRZ1 to the wiring WCL via the transistor F4, can be converted into an analog voltage and output to the wiring OL.

[0170] In particular, by setting the constant voltage provided by the wiring VRL to the ground potential (GND), the inverting input terminal of the operational amplifier OP1 becomes a virtual ground, so that the analog voltage output to the wiring OL can be a voltage referenced to the ground potential (GND).

[0171] Also, although the circuit ITRZ1 in Fig. 15A is configured to output an analog voltage, the circuit configuration applicable to the circuits ITRZ[1] to ITRZ[n] in Fig. 12 is not limited to this. For example, as shown in Fig. 15B, the circuit ITRZ1 may have a configuration including an analog-to-digital conversion circuit ADC. Specifically, in the circuit ITRZ2 of Fig. 15B, the input terminal of the analog-to-digital conversion circuit ADC is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, and the output terminal of the analog-to-digital conversion circuit ADC is electrically connected to the wiring OL. With such a configuration, the circuit ITRZ2 in Fig. 15B can output a digital signal to the wiring OL. The digital signal output to the wiring OL can be converted into a serial signal by a shift register, a latch circuit, a switch, etc. described in Embodiment 1 and output externally.

[0172] Furthermore, in the circuit ITRZ2, when the digital signal output to the line OL is 1 bit (binary), the circuit ITRZ2 may be replaced with the circuit ITRZ3 shown in FIG. 15C. The circuit ITRZ3 in FIG. 15C is configured by adding a comparator CMP1 to the circuit ITRZ1 in FIG. 15A. Specifically, the circuit ITRZ3 is configured such that a first input terminal of the comparator CMP1 is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, a second input terminal of the comparator CMP1 is electrically connected to the line VRL2, and an output terminal of the comparator CMP1 is electrically connected to the line OL. The line VRL2 functions as a line that provides a potential to be compared with the potential of the first terminal of the comparator CMP1. By using such a configuration, the circuit ITRZ3 in FIG. 15C can output a low-level potential or a high-level potential (binary digital signal) to the wiring OL depending on the magnitude of the voltage converted from the amount of current flowing between the source and drain of the transistor F4 by the current-voltage conversion circuit and the voltage applied by the wiring VRL2.

[0173] 12 的电路ITRZ[1]〜电路ITRZ[n]应用于图12的半导体器件MAC1的电路ITRZ1〜电路ITRZ3所示的图15A〜15C。 For example, when the semiconductor device MAC1 is used for the operation of a hierarchical neural network, the circuits ITRZ1~ITRZ3 preferably include semiconductor devices that perform function operations. Furthermore, the semiconductor device that performs function operations may be a semiconductor device that performs a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, or the like.

[0174] Note that one aspect of the present invention is not limited to the circuit configuration of the semiconductor device MAC1 described in this embodiment. The semiconductor device MAC1 can change its circuit configuration according to the situation. For example, the semiconductor device MAC1 may be changed to a configuration without the circuit SWS1 as in the semiconductor device MAC1A shown in FIG. 16. In the case of the semiconductor device MAC1, the circuit SWS1 can stop the current flowing from the circuit WCS to the wirings WCL[1] to WCL[n]. However, in the case of the semiconductor device MAC1A, the current flowing from the circuit WCS to the wirings WCL[1] to WCL[n] may be stopped by the circuit WCS. Specifically, for example, when the circuit WCS included in the semiconductor device MAC1A is the circuit WCS of FIG. 13A and the current source CS is the current source CS1 of FIG. 14A, a low-level potential may be input to each of the wirings DW[1] to DW[K], and the switch SWW may be turned off. By operating the circuit WCS in this way, the current flowing from the circuit WCS to the wirings WCL[1] to WCL[n] can be stopped. By stopping the current flowing from the circuit WCS to the wirings WCL[1] to WCL[n] in this way, calculations can be performed using the semiconductor device MAC1A instead of the semiconductor device MAC1.

[0175] <Operation example of semiconductor device> Next, an operation example of the semiconductor device MAC1 will be described.

[0176] FIG. 17 shows a timing chart of an operation example of the semiconductor device MAC1. The timing chart of FIG. 17 shows the potential fluctuations of the wirings SWL1, SWL2, WSL[i] (where i is an integer from 1 to m - 1), WSL[i + 1], XCL[i], XCL[i + 1], nodes NN[i,j] (where j is an integer from 1 to n - 1), NN[i + 1,j], NNref[i], and NNref[i + 1] between time T11 and time T23 and in the vicinity thereof. Further, the timing chart of FIG. 17 shows the amount of current I flowing between the first terminal and the second terminal of the transistor F2 included in the cell IM[i,j]. F2[i,j] and the current I flowing between the first and second terminals of transistor F2m included in cell IMref[i] F2m [i] and the current I flowing between the first and second terminals of transistor F2 included in cell IM[i+1,j] F2 [i+1,j] and the current I flowing between the first and second terminals of transistor F2m included in cell IMref[i+1] F2m The respective variations of [i+1] and are also shown.

[0177] It is to be noted that the circuit WCS of the semiconductor device MAC1 is the circuit WCS of FIG. 13A, and the circuit XCS of the semiconductor device MAC1 is the circuit XCS of FIG. 13C.

[0178] In this operation example, the potential of the wiring VE is set to the ground potential GND. Also, before time T11, the potentials of the nodes NN[i,j], NN[i+1,j], NNref[i], and NNref[i+1] are set to the ground potential GND as an initial setting. Specifically, for example, by setting the initialization potential of the wiring VINIL1 in FIG. 13A to the ground potential GND and turning on the switch SWW, the transistor F3, and the transistors F1 included in the cells IM[i,j] and IM[i+1,j], the potentials of the nodes NN[i,j] and NN[i+1,j] can be set to the ground potential GND. Furthermore, for example, by setting the initialization potential of the wiring VINIL2 in Figure 13C to the ground potential GND and turning on the switch SWX and the transistors F1m included in the cells IMref[i,j] and IMref[i+1,j], the potentials of the nodes NNref[i,j] and NNref[i+1,j] can be set to the ground potential GND.

[0179] Between time T11 and time T12, a high-level potential (denoted as "High" in FIG. 17) is applied to the wiring SWL1, and a low-level potential (denoted as "Low" in FIG. 17) is applied to the wiring SWL2. As a result, a high-level potential is applied to the gates of the transistors F3[1] to F3[n], turning on the transistors F3[1] to F3[n], and a low-level potential is applied to the gates of the transistors F4[1] to F4[n], turning off the transistors F4[1] to F4[n].

[0180] Furthermore, between time T11 and time T12, a low-level potential is applied to the wiring WSL[i] and the wiring WSL[i+1]. As a result, a low-level potential is applied to the gate of the transistor F1 included in the cells IM[i,1] to IM[i,n] in the i-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i], turning off the respective transistors F1 and F1m. Furthermore, a low-level potential is applied to the gate of the transistor F1 included in the cells IM[i+1,1] to IM[i+1,n] in the i+1-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i+1], turning off the respective transistors F1 and F1m.

[0181] 13C 的电位被设定为电路XCL[i]、XCL[i+1]的电位,通过将电路VINIL2的初始化电位设定为电路XCL[i]、XCL[i+1]的电位被变化。 Specifically, by setting the initializing potential of the line VINIL2 to the ground potential GND and turning on the switch SWX, the potential of the line XCL[i] and XCL[i+1] can be set to the ground potential GND.

[0182] 13A corresponds to the wirings WCL[1] to WCL[K], and no weight data is input to the wirings DW[1] to DW[K]. Also, between time T11 and time T12, when the wiring WCL in FIG. 13A corresponds to the wirings WCL[1] to WCL[K], and no input data is input to the wirings DX[1] to DX[L], and when the wiring XCL in FIG. 13C corresponds to the wirings XCL[1] to XCL[K], and no input data is input to the wirings DX[1] to DX[L], respectively. Here, in the circuit WCS in FIG. 13A, a low-level potential is input to each of the wirings DW[1] to DW[K], and in the circuit XCS in FIG. 13C, a low-level potential is input to each of the wirings DX[1] to DX[L].

[0183] Furthermore, between time T11 and time T12, no current flows through the wiring WCL[j], the wiring XCL[i], and the wiring XCL[i+1]. F2 [i,j], I F2m [i]I F2 [i+1,j], I F2m [i+1] becomes 0.

[0184] Between time T12 and time T13, a high-level potential is applied to the wiring WSL[i]. As a result, a high-level potential is applied to the gate of the transistor F1 included in the cells IM[i,1] to IM[i,n] in the i-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i], turning on the transistor F1 and the transistor F1m. Also, between time T12 and time T13, a low-level potential is applied to the wirings WSL[1] to WSL[m] other than the wiring WSL[i], turning off the transistor F1 included in the cells IM[1,1] to IM[m,n] other than the i-th row of the cell array CA and the transistor F1m included in the cells IMref[1] to IMref[m] other than the i-th row.

[0185] Furthermore, the ground potential GND has been applied to the wirings XCL[1] to XCL[m] continuously since before time T12.

[0186] Between time T13 and time T14, a current of a current amount I0[i,j] flows from the circuit WCS to the cell array CA via the transistor F3[j] as weight data. Specifically, when the wiring WCL shown in FIG. 13A is the wiring WCL[j], signals according to the weight data are input to each of the wirings DW[1] to DW[K], and a current I0[i,j] flows from the circuit WCS to the second terminal of the transistor F3[j]. In other words, the value of the K-bit signal input as weight data is set to α[i,j] (α[i,j] is set to a value between 0 and 2). K -1 or less), then I0[i,j]=α[i,j]×I Wut It becomes.

[0187] Note that when α[i,j] is 0, I0[i,j]=0, so strictly speaking, no current flows from circuit WCS to cell array CA via transistor F3[j]. However, in this specification, it may be stated that "a current of I0[i,j]=0 flows."

[0188] Between time T13 and time T14, there is a conductive state between the first terminal of transistor F1 included in cell IM[i,j] in the i-th row of cell array CA and wiring WCL[j], and there is a non-conductive state between the first terminal of transistor F1 included in cells IM[1,j] to IM[m,j] other than the i-th row of cell array CA and wiring WCL[j], so that a current of an amount I0[i,j] flows from wiring WCL[j] to cell IM[i,j].

[0189] Incidentally, when the transistor F1 included in the cell IM[i,j] is turned on, the transistor F2 included in the cell IM[i,j] has a diode-connected configuration. Therefore, when current flows from the wiring WCL[j] to the cell IM[i,j], the potentials of the gate of the transistor F2 and the second terminal of the transistor F2 become substantially equal. The said potential is determined by the amount of current flowing from the wiring WCL[j] to the cell IM[i,j], the potential of the first terminal of the transistor F2 (here GND), etc. In this operation example, when a current of current amount I0[i,j] flows from the wiring WCL[j] to the cell IM[i,j], the potential of the gate (node NN[i,j]) of the transistor F2 becomes V g [i,j]. That is, in the transistor F2, the gate-source voltage becomes V g [i,j] - GND, and the current amount I0[i,j] is set as the current flowing between the first terminal and the second terminal of the transistor F2.

[0190] Here, when the threshold voltage of the transistor F2 is V th [i,j], the current amount I0[i,j] when the transistor F2 operates in the subthreshold region can be described as in the following formula (1.1).

[0191] [Equation]

[0192] Note that I a is the drain current when V g [i,j] is V th [i,j], and J is a correction coefficient determined by temperature, device structure, etc.

[0193] Also, between time T13 and time T14, from the circuit XCS to the wiring XCL[i], as reference data, a current amount I ref0Specifically, when the wiring XCL shown in FIG. 13C is the wiring XCL[i], a high-level potential is input to the wiring DX[1] and a low-level potential is input to each of the wirings DX[2] to DX[K], and a current I flows from the circuit XCS to the wiring XCL[i]. ref0 In other words, I ref0 =I Xut It becomes.

[0194] Between time T13 and time T14, the first terminal of the transistor F1m included in the cell IMref[i] is in a conductive state with the wiring XCL[i], so that a current I ref0 A current of flows.

[0195] As with cell IM[i,j], when transistor F1m included in cell IMref[i] is turned on, transistor F2m included in cell IMref[i] is configured as a diode connection. Therefore, when current flows from wiring XCL[i] to cell IMref[i], the potentials of the gate of transistor F2m and the second terminal of transistor F2m become approximately equal. This potential is determined by the amount of current flowing from wiring XCL[i] to cell IMref[i] and the potential of the first terminal of transistor F2m (here, GND), etc. In this operation example, the amount of current I flows from wiring XCL[i] to cell IMref[i]. ref0 As a result of this current flowing, the gate of transistor F2 (node NNref[i]) is V gm [i], and the potential of the wiring XCL[i] at this time is also V gm [i]. That is, in transistor F2m, the gate-source voltage is V gm [i]-GND, and the current flowing between the first and second terminals of transistor F2m is I ref0 is set.

[0196] Here, the threshold voltage of transistor F2m is V thm When [i] is set, the amount of current I when transistor F2m operates in the subthreshold region isref0 It can be described by the following formula (1.2). Here, the correction coefficient J is the same as that of the transistor F2 included in the cell IM[i, j]. For example, the device structure and size (channel length, channel width) of the transistors are the same. Also, due to manufacturing variations, the correction coefficient J of each transistor varies, but it is assumed that the variation is suppressed to such an extent that the discussions described later hold with sufficient practical accuracy.

[0197]

Number

[0198] Here, the weight coefficient w[i, j], which is weight data, is defined as in the following formula (1.3).

[0199]

Number

[0200] Therefore, formula (1.1) can be rewritten as the following formula (1.4).

[0201]

Number

[0202] Note that when the current I output by the current source CS of the circuit WCS in FIG. 13A Wut and the current I output by the current source CS of the circuit XCS in FIG. 13C Xut are equal, w[i, j] = α[i, j]. That is, when Wut and Xut are equal, since α[i, j] corresponds to the value of the weight data, it is preferable that Wut and Xut are equal to each other.

[0203] Between time T14 and time T15, a low-level potential is applied to wiring WSL[i]. As a result, a low-level potential is applied to the gates of transistors F1 included in cells IM[i,1] to IM[i,n] in the i-th row of cell array CA and to the gate of transistor F1m included in cell IMref[i], causing each of transistor F1 and transistor F1m to be in an off state.

[0204] When the transistor F1 included in cell IM[i,j] is turned off, the voltage difference V g [i,j] - V gm [i] between the potential of the gate (node NN[i,j]) of transistor F2 and the potential of wiring XCL[i] is held in capacitor C5. Also, when the transistor F1 included in cell IMref[i] is turned off, a voltage difference of 0 between the potential of the gate (node NNref[i]) of transistor F2m and the potential of wiring XCL[i] is held in capacitor C5m. Note that the voltage held in capacitor C5m may be a non-zero voltage (here, for example, V ds assuming this) depending on the transistor characteristics of transistor F1m or transistor F2m in the operation from time T13 to time T14. In this case, the potential of node NNref[i] may be considered as the potential obtained by adding V ds to the potential of wiring XCL[i].

[0205] Between time T15 and time T16, GND is applied to wiring XCL[i]. Specifically, for example, when the wiring XCL shown in FIG. 13C is wiring XCL[i], by setting the initialization potential of wiring VINIL2 to the ground potential GND and turning on switch SWX, the potential of wiring XCL[i] can be set to the ground potential GND.

[0206] Therefore, due to the capacitive coupling by the capacitance C5 included in each of the cells IM[i,1] to IM[i,n] in the i-th row, the potentials of the nodes NN[i,1] to NN[i,n] change, and due to the capacitive coupling by the capacitance C5m included in the cell IMref[i], the potential of the node NNref[i] changes.

[0207] The amount of change in the potentials of the nodes NN[i,1] to NN[i,n] is the potential obtained by multiplying the amount of change in the potential of the wiring XCL[i] by the capacitive coupling coefficient determined by the configuration of each of the cells IM[i,1] to IM[i,n] included in the cell array CA. The capacitive coupling coefficient is calculated based on the capacitance of the capacitance C5, the gate capacitance of the transistor F2, parasitic capacitance, etc. In each of the cells IM[i,1] to IM[i,n], when the capacitive coupling coefficient due to the capacitance C5 is p, the potential of the node NN[i,j] of the cell IM[i,j] decreases by p(V gm [i] - GND) from the potential at a point in time between time T14 and time T15.

[0208] Similarly, when the potential of the wiring XCL[i] changes, the potential of the node NNref[i] also changes due to the capacitive coupling by the capacitance C5m included in the cell IMref[i]. When the capacitive coupling coefficient due to the capacitance C5m is p in the same manner as the capacitance C5, the potential of the node NNref[i] of the cell IMref[i] decreases by p(V gm [i] - GND) from the potential between time T14 and time T15. In the timing chart of FIG. 17, as an example, p = 1 is set. Therefore, the potential of the node NNref[i] between time T15 and time T16 becomes GND.

[0209] As a result, since the potential of the node NN[i,j] of the cell IM[i,j] decreases, the transistor F2 becomes off. Similarly, since the potential of the node NNref[i] of the cell IMref[i] decreases, the transistor F2m also becomes off. Therefore, between time T15 and time T16, I F2 [i,j], I F2mEach of [i] is 0.

[0210] Between time T16 and time T17, a high-level potential is applied to the wiring WSL[i+1]. As a result, a high-level potential is applied to the gate of the transistor F1 included in the cells IM[i+1,1] to IM[i+1,n] in the i+1th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i+1], turning on the transistor F1 and the transistor F1m. Also, between time T16 and time T17, a low-level potential is applied to the wirings WSL[1] to WSL[m] except for the wiring WSL[i+1]. Therefore, the transistor F1 included in the cells IM[1,1] to IM[m,n] other than the i+1th row of the cell array CA and the transistor F1m included in the cells IMref[1] to IMref[m] other than the i+1th row of the cell array CA are turned off.

[0211] Furthermore, the ground potential GND has been applied to the wirings XCL[1] to XCL[m] continuously since before time T16.

[0212] Between time T17 and time T18, a current of a current amount I0[i+1,j] flows from the circuit WCS to the cell array CA via the transistor F3[j] as weight data. Specifically, when the wiring WCL shown in FIG. 13A is the wiring WCL[j+1], signals according to the weight data are input to each of the wirings DW[1] to DW[K], and a current I0[i+1,j] flows from the circuit WCS to the second terminal of the transistor F3[j]. In other words, the value of the K-bit signal input as weight data is set to α[i+1,j] (α[i+1,j] is between 0 and 2). K -1 or less.) I0[i+1,j]=α[i+1,j]×I Wut It becomes.

[0213] Note that when α[i+1,j] is 0, I0[i+1,j]=0, so strictly speaking, no current flows from circuit WCS to cell array CA via transistor F3[j]. However, in this specification, it may be stated that "a current of I0[i+1,j]=0 flows," as in the case of I0[i,j]=0.

[0214] At this time, there is a conductive state between the first terminal of transistor F1 included in cell IM[i+1,j] in the i+1th row of cell array CA and wiring WCL[j], and there is a non-conductive state between the first terminal of transistor F1 included in cells IM[1,j] to IM[m,j] other than the i+1th row of cell array CA and wiring WCL[j], so a current of an amount I0[i+1,j] flows from wiring WCL[j] to cell IM[i+1,j].

[0215] Incidentally, when transistor F1 included in cell IM[i+1,j] is turned on, transistor F2 included in cell IM[i+1,j] is configured as a diode. Therefore, when current flows from wiring WCL[j] to cell IM[i+1,j], the potentials of the gate of transistor F2 and the second terminal of transistor F2 become approximately equal. This potential is determined by the amount of current flowing from wiring WCL[j] to cell IM[i+1,j] and the potential of the first terminal of transistor F2 (here, GND). In this operation example, when a current of a current amount I0[i+1,j] flows from wiring WCL[j] to cell IM[i+1,j], the potential of the gate of transistor F2 (node NN[i+1,j]) becomes V g [i+1,j]. That is, in transistor F2, the gate-source voltage is V g [i+1,j]-GND, and the amount of current I0[i+1,j] is set as the current flowing between the first terminal and the second terminal of the transistor F2.

[0216] Here, the threshold voltage of transistor F2 is V thWhen it is [i + 1, j], the current I0[i + 1, j] when the transistor F2 operates in the subthreshold region can be described as in the following equation (1.5). Note that the correction coefficient is the same J as that of the transistor F2 included in the cell IM[i, j] and the transistor F2m included in the cell IMref[i].

[0217] [Number]

[0218] Also, between time T17 and time T18, from the circuit XCS, a current I ref0 flows through the wiring XCL[i + 1] as reference data. Specifically, similar to the period from time T13 to time T14, when the wiring XCL shown in FIG. 13C is the wiring XCL[i + 1], a high-level potential is input to the wiring DX[1], and low-level potentials are input to each of the wirings DX[2] to DX[K], and a current I ref0 = I Xut flows from the circuit XCS to the wiring XCL[i + 1].

[0219] Between time T17 and time T18, since the connection between the first terminal of the transistor F1m included in the cell IMref[i + 1] and the wiring XCL[i + 1] becomes conductive, a current I ref0 flows from the wiring XCL[i + 1] to the cell IMref[i + 1].

[0220] Similar to cell IM[i+1,j], when the transistor F1m included in cell IMref[i+1] is turned on, the transistor F2m included in cell IMref[i+1,j] is configured in a diode connection. Therefore, when current flows from wiring XCL[i+1] to cell IMref[i+1], the potentials of the gate of transistor F2m and the second terminal of transistor F2m become substantially equal. The said potential is determined by the amount of current flowing from wiring XCL[i+1] to cell IMref[i+1], the potential of the first terminal of transistor F2m (here GND), etc. In this operation example, when a current of amount I ref0 flows from wiring XCL[i+1] to cell IMref[i+1], the gate of transistor F2 (node NNref[i+1]) is assumed to be V gm [i+1], and at this time, the potential of wiring XCL[i+1] is also V gm [i+1]. That is, in transistor F2m, the gate-source voltage becomes V gm [i+1]-GND, and as the current flowing between the first terminal and the second terminal of transistor F2m, a current amount I ref0 is set.

[0221] Here, when the threshold voltage of transistor F2m is V thm [i+1,j], the current amount I ref0 when transistor F2m operates in the subthreshold region can be described as in the following formula (1.6). Note that the correction coefficient J is the same as that of the transistor F2 included in cell IM[i+1,j].

[0222]

Equation

[0223] Here, the weight coefficient w[i+1,j] which is weight data is defined as follows.

[0224]

Equation

[0225] Therefore, Equation (1.5) can be rewritten as the following Equation (1.6).

[0226] [Number]

[0227] Note that the current I output by the current source CS of the circuit WCS in FIG. 13A Wut and the current I output by the current source CS of the circuit XCS in FIG. 13C Xut are equal, then w[i + 1, j]=α[i + 1, j]. That is, when I Wut and I Xut are equal, since α[i + 1, j] corresponds to the value of the weight data, it is preferable that I Wut and I Xut are equal to each other.

[0228] During the time from time T18 to time T19, a low-level potential is applied to the wiring WSL[i + 1]. As a result, a low-level potential is applied to the gates of the transistors F1 included in the cells IM[i + 1, 1] to IM[i + 1, n] in the (i + 1)-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i + 1], and the respective transistors F1 and F1m are turned off.

[0229] When the transistor F1 included in the cell IM[i + 1, j] is turned off, the capacitor C5 has a potential difference V g [i + 1, j]-V gm[i + 1] is retained. Also, when the transistor F1 included in the cell IMref[i + 1] is turned off, 0, which is the difference between the potential of the gate (node NNref[i + 1]) of the transistor F2m and the potential of the wiring XCL[i + 1], is retained in the capacitor C5m. Note that the voltage retained by the capacitor C5m may be a voltage other than 0 (here, for example, V ds as an example) depending on the transistor characteristics of the transistor F1m or the transistor F2m in the operation from time T18 to time T19. In this case, the potential of the node NNref[i + 1] may be considered as the potential obtained by adding V ds to the potential of the wiring XCL[i + 1].

[0230] During the period from time T19 to time T20, the ground potential GND is applied to the wiring XCL[i + 1]. Specifically, for example, when the wiring XCL shown in FIG. 13C is the wiring XCL[i + 1], by setting the initialization potential of the wiring VINIL2 to the ground potential GND and turning on the switch SWX, the potential of the wiring XCL[i + 1] can be set to the ground potential GND.

[0231] Therefore, due to the capacitive coupling by the capacitors C5 included in each of the cells IM[i + 1,1] to IM[i + 1,n] in the (i + 1)-th row, the potentials of the nodes NN[i,1] to NN[i + 1,n] change, and due to the capacitive coupling by the capacitor C5m included in the cell IMref[i + 1], the potential of the node NNref[i + 1] changes.

[0232] The change amount of the potential of Node NN[i+1,1] to Node NN[i+1,n] is the potential obtained by multiplying the change amount of the potential of Wiring XCL[i+1] by the capacitance coupling coefficient determined by the configuration of each cell IM[i+1,1] to cell IM[i+1,n] included in the cell array CA. The capacitance coupling coefficient is calculated based on the capacitance of capacitor C5, the gate capacitance of transistor F2, parasitic capacitance, etc. In each of cells IM[i+1,1] to cell IM[i+1,n], when the capacitance coupling coefficient due to capacitor C5 is set as p, which is the same as the capacitance coupling coefficient due to capacitor C5 in each of cells IM[i,1] to cell IM[i,n], the potential of Node NN[i+1,j] of cell IM[i+1,j] decreases by p(V gm [i+1]-GND) from the potential at the time point between time T18 and time T19.

[0233] Similarly, when the potential of Wiring XCL[i+1] changes, the potential of Node NNref[i+1] also changes due to the capacitance coupling by capacitor C5m included in cell IMref[i+1]. When the capacitance coupling coefficient due to capacitor C5m is set as p, which is the same as that of capacitor C5, the potential of Node NNref[i+1] of cell IMref[i+1] decreases by p(V gm [i+1]-GND) from the potential between time T18 and time T19. In the timing chart of FIG. 17, as an example, p = 1 is set. Therefore, the potential of Node NNref[i+1] between time T20 and time T21 becomes GND.

[0234] As a result, since the potential of Node NN[i+1,j] of cell IM[i+1,j] decreases, transistor F2 turns off. Similarly, since the potential of Node NNref[i+1] of cell IMref[i+1] decreases, transistor F2m also turns off. Therefore, between time T19 and time T20, I F2 [i+1,j], I F2m [i+1] each become 0.

[0235] Between time T20 and time T21, a low-level potential is applied to wiring SWL1. As a result, a low-level potential is applied to the gates of transistors F3[1] to F3[n], respectively, and transistors F3[1] to F3[n] are turned off.

[0236] Between time T21 and time T22, a high-level potential is applied to wiring SWL2. As a result, a high-level potential is applied to the gates of transistors F4[1] to F4[n], respectively, and transistors F4[1] to F4[n] are turned on.

[0237] Between time T22 and time T23, from circuit XCS, a current of x[i]I which is x[i] times the current amount I flows as input data to wiring XCL[i]. ref0 which is x[i] times the current amount I of I ref0 flows. Specifically, for example, when the wiring XCL shown in FIG. 13C is the wiring XCL[i], a high-level potential or a low-level potential is input to each of wirings DX[1] to DX[K] according to the value of x[i], and a current of x[i]I flows from circuit XCS to wiring XCL[i] as the current amount. ref0 =x[i]I Xut flows. In this operation example, x[i] corresponds to the value of the input data. At this time, it is assumed that the potential of wiring XCL[i] changes from 0 to V gm [i]+ΔV[i].

[0238] When the potential of wiring XCL[i] changes, the potentials of nodes NN[i,1] to NN[i,n] also change due to capacitive coupling by the capacitances C5 included in cells IM[i,1] to IM[i,n] in the i-th row of cell array CA. Therefore, the potential of node NN[i,j] of cell IM[i,j] becomes V g [i,j]+pΔV[i].

[0239] Similarly, when the potential of the wiring XCL[i] changes, the potential of the node NNref[i] also changes due to the capacitive coupling of the capacitance C5m included in the cell IMref[i]. Therefore, the potential of the node NNref[i] of the cell IMref[i] is V gm [i]+pΔV[i].

[0240] As a result, between time T22 and time T23, the amount of current I1[i,j] flowing between the first terminal and the second terminal of the transistor F2 and the amount of current I ref1 [i,j] can be written as follows:

[0241]

number

[0242]

number

[0243] From equations (1.9) and (1.10), x[i] can be expressed by the following equation (1.11).

[0244]

number

[0245] Therefore, equation (1.9) can be rewritten as the following equation (1.12).

[0246]

number

[0247] In other words, the amount of current flowing between the first and second terminals of transistor F2 included in cell IM[i,j] is proportional to the product of the weight coefficient w[i,j], which is weight data, and the input data x[i].

[0248] In addition, between time T22 and time T23, the circuit XCS outputs the current amount I ref0 x[i+1] is x[i+1] times I ref0 Specifically, for example, when the wiring XCL shown in FIG. 13C is the wiring XCL[i+1], a high-level potential or a low-level potential is input to each of the wirings DX[1] to DX[K] depending on the value of x[i+1], and a current of x[i+1]I flows from the circuit XCS to the wiring XCL[i+1]. ref0 =x[i+1]I Xut In this example, x[i+1] corresponds to the value of the input data. At this time, the potential of the wiring XCL[i+1] changes from 0 to V gm [i+1]+ΔV[i+1].

[0249] As the potential of the wiring XCL[i+1] changes, the potentials of the nodes NN[i+1,1] to NN[i+1,n] also change due to capacitive coupling by the capacitor C5 included in each of the cells IM[i+1,1] to IM[i+1,n] in the i+1th row of the cell array CA. Therefore, the potential of the node NN[i+1,j] of the cell IM[i+1,j] is V g [i+1,j]+pΔV[i+1].

[0250] Similarly, when the potential of the wiring XCL[i+1] changes, the potential of the node NNref[i+1] also changes due to the capacitive coupling of the capacitance C5m included in the cell IMref[i+1]. Therefore, the potential of the node NNref[i+1] of the cell IMref[i+1] is V gm [i+1]+pΔV[i+1].

[0251] As a result, between time T22 and time T23, the amount of current I1[i+1,j] flowing between the first terminal and the second terminal of the transistor F2 and the amount of current I ref1 [i+1,j] can be written as follows:

[0252]

Number

[0253]

Number

[0254] From Equation (1.13) and Equation (1.14), x[i + 1] can be expressed by the following Equation (1.15).

[0255]

Number

[0256] Therefore, Equation (1.13) can be rewritten as the following Equation (1.16).

[0257]

Number

[0258] That is, the amount of current flowing between the first terminal and the second terminal of the transistor F2 included in the cell IM[i + 1, j] is proportional to the product of the weight data w[i + 1, j] and the input data x[i + 1].

[0259] Here, consider the sum of the amounts of current flowing into the cells IM[i, j] and IM[i + 1, j] from the circuit ITRZ[j] via the transistor F4[j] and the wiring WCL[j]. Let the sum of the amounts of current be I S [j]. Then, I S [j] can be expressed by the following Equation (1.17) from Equation (1.12) and Equation (1.16).

[0260]

Number

[0261] Therefore, the amount of current output from circuit ITRZ[j] is a current amount proportional to the sum of products of weight coefficients w[i,j] and w[i+1,j], which are weight data, and input data x[i] and x[i+1].

[0262] In the above operation example, the total amount of current flowing through cells IM[i,j] and IM[i+1,j] was handled. However, as multiple cells, the total amount of current flowing through each of cells IM[1,j] to IM[m,j] may also be handled. In this case, Equation (1.17) can be rewritten as the following Equation (1.18).

[0263]

Equation

[0264] Therefore, even in the case of semiconductor device MAC1 having a cell array CA of three or more rows and two or more columns, as described above, the sum-of-products operation can be performed. In this case, for semiconductor device MAC1, one column out of multiple columns is a cell that holds current I ref0 and xI ref0 so that the sum-of-products operation process can be executed simultaneously for the number of remaining columns out of multiple columns. That is, by increasing the number of columns of the cell array, a semiconductor device that realizes a high-speed sum-of-products operation process can be provided.

[0265] Note that the above operation example of semiconductor device MAC1 is suitable for the case of calculating the sum of products of positive weight data and positive input data.

[0266] In addition, in the present embodiment, the case where the transistors included in the semiconductor device MAC1 are OS transistors or Si transistors has been described. However, one aspect of the present invention is not limited to this. The transistors included in the semiconductor device MAC1 can be, for example, transistors in which Ge or the like is included in the channel formation region, transistors in which a compound semiconductor such as gallium nitride is included in the channel formation region, transistors in which carbon nanotubes are included in the channel formation region, transistors in which an organic semiconductor is included in the channel formation region, and the like.

[0267] Note that the present embodiment can be appropriately combined with other embodiments shown in this specification.

[0268] (Embodiment 4) In the present embodiment, a display device including the above-described semiconductor device will be described. The display device can be a display device that can perform arithmetic processing with excellent arithmetic efficiency by including a semiconductor device capable of performing arithmetic processing of an artificial neural network. In the present embodiment, a schematic top view and a schematic cross-sectional view of the upper surface of the light-emitting element, a configuration example of the light-emitting element, configuration examples of the light-emitting element and the light-receiving element, and a configuration example of the cross-sectional view of the display device will be described.

[0269] <Configuration Example of Display Device> FIG. 18A is a diagram showing a perspective view of the display device 10. In the display device 10 illustrated in FIG. 18A, the configurations of the layers 20, 50, and 60 provided between the substrate 11 and the substrate 12 are schematically shown. Also in FIG. 18A, in the layer 60, the display unit 13, the light-receiving unit 14, and the input / output terminal 15 are illustrated.

[0270] On the substrate 11, a layer 20 is provided. As an example, the layer 20 is provided with a drive circuit 30 and an arithmetic circuit 40. The layer 20 has a transistor 21 (also referred to as an Si transistor) having silicon in the channel formation region 22. The substrate 11 is, for example, a silicon substrate. A silicon substrate is preferable because it has higher thermal conductivity compared to a glass substrate.

[0271] The transistor 21 can be, for example, a transistor having single-crystalline silicon in its channel formation region. In particular, when a transistor having single-crystalline silicon in its channel formation region is used as the transistor provided in the layer 20, the on-current of the transistor can be increased. Therefore, since the circuit included in the layer 20 can be driven at high speed, it is preferable. Further, since the transistor having single-crystalline silicon in its channel formation region can be formed by microfabrication such that the channel length is 3 nm to 10 nm, in addition to the dedicated arithmetic circuit 40 such as an artificial neural network (hereinafter sometimes referred to as a neural network) and / or the drive circuit 30, it is possible to provide an accelerator such as a CPU or a GPU, an application processor, and the like. The arithmetic circuit 40 can be the semiconductor device described in the first to third embodiments.

[0272] The drive circuit 30 includes, for example, a gate driver circuit, a source driver circuit, and the like. The gate driver circuit, the source driver circuit, and the like can be arranged so as to overlap the display unit 13 and / or the light receiving unit 14. Therefore, compared with the case where the drive circuit 30 and the display unit 13 are arranged side by side, the width of the non-display region (also referred to as a frame) existing on the outer periphery of the display unit 13 of the display device 10 can be made extremely narrow, and a small display device 10 can be realized. Further, when arranged on the outer periphery of the display unit 13 of the display device 10, the gate driver circuit and the source driver circuit are arranged in a concentrated manner on the outer periphery. However, the drive circuit 30 can be arranged in a plurality of divided regions overlapping the display unit 13.

[0273] The arithmetic circuit 40 includes the semiconductor device described in the first to third embodiments. Therefore, it is possible to execute the multiplication and addition operation processing in the artificial neural network, and for example, inference processing based on a hierarchical neural network such as a deep neural network (DNN) or a convolutional neural network (CNN) can be performed. Since the arithmetic circuit 40 can execute a multiplication and addition operation using a minute current corresponding to an analog value voltage, arithmetic processing using the minute current flowing through the light receiving element 62 as input data can be performed. Therefore, it is effective for reducing the area of the circuit, reducing power consumption, and improving arithmetic efficiency. The light receiving element 62 is an element that converts an optical signal into an electrical signal, and is also referred to as a photoelectric conversion element.

[0274] A layer 50 is provided on the layer 20. The layer 50 is provided with a pixel circuit portion 51P including a plurality of pixel circuits 51 and a cell array CA including a plurality of cells IM. The layer 50 has a transistor 52 (also referred to as an OS transistor) having a metal oxide (also referred to as an oxide semiconductor) in a channel formation region 54. Note that the layer 50 can be configured to be laminated on the layer 20. It is also possible to form the layer 50 on a separate substrate and perform bonding.

[0275] As the transistor 52 which is an OS transistor, it is preferable to use a transistor having an oxide containing at least one of indium, element M (element M is aluminum, gallium, yttrium, or tin), and zinc in a channel formation region. Such an OS transistor has a characteristic that the off-current is very low. Therefore, it is particularly preferable to use an OS transistor as the transistor provided in the pixel circuit 51 and the cell IM because the analog data written in the pixel circuit 51 and the cell IM can be held for a long period of time.

[0276] On layer 50, layer 60 is provided. On layer 60, substrate 12 is provided. Substrate 12 is preferably a substrate having translucency or a layer made of a material having translucency. Layer 60 has a display portion 13 provided with a plurality of light-emitting elements 61 and a light-receiving portion 14 provided with a plurality of light-receiving elements 62. Note that layer 60 can be configured to be laminated on layer 50. As the light-emitting element 61, for example, an organic electroluminescence element (also referred to as an organic EL element) can be used. However, the light-emitting element 61 is not limited thereto, and for example, an inorganic EL element made of an inorganic material may be used. Note that the “organic EL element” and the “inorganic EL element” may be collectively referred to as an “EL element”. The light-emitting element 61 may have an inorganic compound such as a quantum dot. For example, by using a quantum dot for a light-emitting layer, it can also function as a light-emitting material. As the light-receiving element 62, for example, an organic photodiode can be used, and some processes can be fabricated in the same process as that for the organic electroluminescence element.

[0277] As shown in FIG. 18A, the display device 10 according to one embodiment of the present invention can be configured by laminating a light-emitting element 61, a pixel circuit 51, and a driving circuit 30. Therefore, the pixel circuit 51 can be arranged with extremely high density, and the pixel fineness can be made extremely high. Since such a display device 10 is extremely high-definition, it can be suitably used for VR devices such as head-mounted displays or glasses-type AR devices. For example, even in the case of a configuration in which the display portion of the display device 10 is visually recognized through an optical member such as a lens, since the display device 10 has an extremely high-definition display portion, pixels are not visually recognized even when the display portion is enlarged by the lens, and a display with a high sense of immersion can be performed.

[0278] 18A , the display device 10 of one embodiment of the present invention can have a stacked configuration of the light-receiving element 62, the cell array CA, and the arithmetic circuit 40. This allows for efficient arithmetic processing using a minute current output from the light-receiving element 62 as input data. Furthermore, the display device 10 can have a configuration in which the light-receiving unit 14 is located close to the display unit 13. This allows images to be viewed by the user's eyes, and images of the user's eyes and / or their surroundings to be captured. Furthermore, the cell IM of the cell array CA can retain analog data written in response to a minute current for a long period of time. Furthermore, the arithmetic circuit 40, which performs product-sum calculations using a minute current, can perform calculations with high arithmetic efficiency.

[0279] 18B shows a block diagram of each component of the layers 20, 50, and 60 in FIG. 18A. The driving circuit 30 in the layer 20 outputs signals GS and DS (for example, GS is a signal for driving a gate line, and DS is a signal corresponding to image data) for controlling the pixel circuit section 51P in the layer 50. The pixel circuit section 51P in the layer 50 supplies a current I corresponding to image data to a light emitting element 61 (not shown) in the display section 13 in the layer 60. EL The light emitting element 61 (not shown) in the display unit 13 on the layer 60 outputs a current I EL The light is emitted in accordance with the image, and the user can visually recognize the image.

[0280] In the block diagram shown in FIG. 18B, a light receiving element 62 (not shown) in the light receiving section 14 in the layer 60 captures an image around the display device 10, and a current I PS It outputs the current I PS is output to the cell array CA in the layer 50 and the arithmetic circuit 40 in the layer 20. The cell array CA in the layer 50 receives the current I PS , and a signal D corresponding to a product-sum operation in response to a control signal from the arithmetic circuit 40 in the layer 20. MAC to the arithmetic circuit 40 in the layer 20. The arithmetic circuit 40 in the layer 20 can perform inference processing based on a neural network ANN.

[0281] Note that the layer 50 provided on the layer 20 can have a structure of two or more layers. For example, as shown in FIG. 19A, the layers 50_1 and 50_2 having transistors which are OS transistors can be used. Further, the layer 20 can have a structure of two or more layers by a bonding process or the like. For example, as shown in FIG. 19B, instead of the layer 50 and the layer 20, the layers 20_1 and 20_2 having Si transistors can be used. The layers 20_1 and 20_2 having Si transistors can be bonded by connecting electrodes (not shown) provided by TSV (Through Silicon Via) with micro bumps 23 or the like.

[0282] <Three-Dimensional Structure of Sensor and Semiconductor Device> Next, the three-dimensional structure when providing a semiconductor device capable of performing an operation using the output of a sensor such as a light receiving element provided in a part of the display device in the display device 10 will be described. The display device 10 shown in FIG. 20 has a layer PDL, a layer ERL, a layer CCL, and a layer PHL. In the layer CCL and the layer PHL, each configuration included in the above-described semiconductor device MAC1 or MAC1A is provided. Note that the circuit PTC provided in the layer CCL has circuits PTR[1] to PTR[m].

[0283] The circuit PTR[1] has a function of making the wiring EIL[1] and the wiring XCL[1] in a conductive state or a non-conductive state. Similarly, the circuit PTR[i] has a function of making the wiring EIL[i] and the wiring XCL[i] in a conductive state or a non-conductive state, and the circuit PTR[m] has a function of making the wiring EIL[m] and the wiring XCL[m] in a conductive state or a non-conductive state. That is, each of the circuits PTR[1] to PTR[m] has a function as a switching element.

[0284] Note that since the display device 10 shown in FIG. 20 is shown in a three-dimensional structure, arrows indicating the x-direction, y-direction, and z-direction are attached to FIG. 20. Here, the x-direction, y-direction, and z-direction are shown as directions orthogonal to each other as an example. Also, in this specification and the like, one of the x-direction, y-direction, or z-direction may be referred to as the "first direction" or "first direction". Also, the other one may be referred to as the "second direction" or "second direction". Also, the remaining one may be referred to as the "third direction" or "third direction".

[0285] The layer CCL is located above the layer PHL, the layer ERL is located above the layer CCL, and the layer PDL is located above the layer ERL. That is, the layer PHL, the layer CCL, the layer ERL, and the layer PDL are stacked in order in the z-direction.

[0286] The layer PDL has, as an example, a sensor array SCA. The sensor array SCA has a plurality of electrodes and a plurality of sensors. In FIG. 20, as an example, electrode DNK[1] to electrode DNK[m] (where m is an integer of 1 or more) are shown as a plurality of electrodes, and sensor SNC[1] to sensor SNC[m] are shown as a plurality of sensors. Also, in the layer PDL, as an example, m electrodes DNK are arranged in a matrix, and sensors SNC[1] to sensors SNC[m] are provided on each of the electrodes DNK[1] to electrode DNK[m].

[0287] Note that in the layer PDL shown in FIG. 20, among the electrodes DNK[1] to electrode DNK[m], the symbols of electrode DNK[1], electrode DNK[i] (where i is an integer of 1 or more and m or less), and electrode DNK[m] are shown in an excerpt. Also, in the layer PDL shown in FIG. 20, among the sensors SNC[1] to sensors SNC[m], the symbols of sensor SNC[1], sensor SNC[i], and sensor SNC[m] are shown in an excerpt.

[0288] Sensors SNC[1] to SNC[m] have the function of converting the sensed information into an electric current and outputting the electric current. Further, each of electrodes DNK[1] to DNK[m] functions as a terminal for outputting the electric current in sensors SNC[1] to SNC[m]. As the sensor SNC, for example, a light receiving element can be applied. By applying a light receiving element as sensors SNC[1] to SNC[m], layer PDL can be made part of an image sensor. In that case, it is desirable that the range of the intensity of light that the light receiving element can sense includes the intensity of light irradiated in the environment where the light receiving element is used. Further, FIG. 20 shows a display device 10 to which a sensor SNC having a photodiode PD is applied as a light receiving element. As the photodiode PD, it is preferable to use an organic light emitting diode that can be provided in the same layer as the light emitting element.

[0289] Further, as the circuit configuration of sensor SNC[i], one of the input terminal or the output terminal of the photodiode PD included in sensor SNC[i] may be electrically connected to wiring EIL[i] via electrode DNK[i]. Also, as the circuit configuration of sensor SNC[i], a configuration may be provided in which a switch or the like for cutting off the power supply to temporarily stop sensor SNC[i] is provided. Note that a light emitting element (not shown) for performing display can be provided in the same layer as sensor SNC[i].

[0290] Layer ERL has wirings EIL[1] to EIL[m]. Note that in layer ERL shown in FIG. 20, among wirings EIL[1] to EIL[m], the reference numerals of wiring EIL[1], wiring EIL[i], and wiring EIL[m] are excerptedly shown.

[0291] Wiring EIL[1] is electrically connected to electrode DNK[1] of layer PDL. Further, wiring EIL[i] is electrically connected to electrode DNK[i] of layer PDL. Also, wiring EIL[m] is electrically connected to electrode DNK[m] of layer PDL.

[0292] Specifically, for example, in a top view of the display device 10 (a line of sight in the direction opposite to the arrow of the z-axis shown in FIG. 20), plugs (sometimes called contact holes, etc.) are provided at the locations where each of the electrodes DNK[1] to DNK[m] intersects with the wirings EIL[1] to EIL[m], etc., to electrically connect each of the electrodes DNK[1] to DNK[m] and each of the wirings EIL[1] to EIL[m].

[0293] Therefore, when information sensing is performed at each of the sensors SNC[1] to SNC[m], the wirings EIL[1] to EIL[m] function as paths through which a current corresponding to the information output from each of the sensors SNC[1] to SNC[m] flows.

[0294] Note that the layer PDL preferably has a configuration in which each of the sensors SNC[1] to SNC[m] can sequentially perform sensing and sequentially flow current to each of the wirings EIL[1] to EIL[m]. In this case, for example, the layer PDL may be configured to provide signal lines for selecting the sensors SNC[1] to SNC[m], and signals, etc. may be sequentially transmitted to the signal lines to sequentially operate the sensors SNC[1] to SNC[m].

[0295] Also, when the sensors SNC[1] to SNC[m] are light receiving elements constituted by a photodiode or the like, the layer PDL of the display device 10 may have a configuration in which, for example, the output terminal (cathode) of the photodiode is electrically connected to the electrode DNK. Alternatively, as another configuration example of the layer PDL of the display device 10, a configuration in which the input terminal (anode) of the photodiode is electrically connected to the electrode DNK may also be used.

[0296] Further, when the sensors SNC[1] to SNC[m] are light-receiving elements composed of, for example, photodiodes, a filter may be provided so that only one of the sensors SNC[1] to SNC[m], for example, only one sensor SNC, is irradiated with light, enabling the sensors SNC[1] to SNC[m] to operate sequentially. Since there are m sensors SNC, there are m types of filters that irradiate only one sensor SNC with light. In addition to these, when a filter that does not irradiate any of the sensors SNC[1] to SNC[m] is prepared, there are m + 1 types of filters. When the layer PDL is irradiated with light, by sequentially switching such filters, the sensors SNC[1] to SNC[m] can perform sensing sequentially.

[0297] Further, when the sensors SNC[1] to SNC[m] are light-receiving elements composed of, for example, photodiodes, for example, the display device 10 may be configured to irradiate each of the sensors SNC[1] to SNC[m] with light individually. By adopting a configuration in which light is irradiated individually, light can be irradiated sequentially to each of the sensors SNC[1] to SNC[m], enabling the sensors SNC[1] to SNC[m] to perform sensing sequentially.

[0298] The layer CCL has, as an example, a circuit PTC and a cell array CA. The layer PHL has, as an example, a circuit XCS, a circuit WCS, a circuit WSD, a circuit ITS, a circuit SWS1, and a circuit SWS2. As shown in FIG. 20, the cell array CA can be configured to be located above the circuit XCS, the circuit WCS, the circuit WSD, the circuit ITS, the circuit SWS1, and the circuit SWS2, which correspond to the peripheral circuits of the cell array CA.

[0299] The cell array CA has a plurality of cells. The plurality of cells included in the cell array CA have functions such as a function of holding weight data for performing a sum-of-products operation and a function of multiplying the weight data and input data.

[0300] The cell array CA is also electrically connected to a plurality of wirings. Specifically, for example, FIG. 20 shows a configuration in which the cell array CA is electrically connected to wirings WCL[1] to WCL[n] (where n is an integer equal to or greater than 1), wirings WSL[1] to WSL[m], and wirings XCL[1] to XCL[m]. In particular, the wirings WCL[1] to WCL[n] electrically connect the circuit SWS1 and the circuit SWS2. That is, the circuit SWS1 can be said to be electrically connected to the circuit SWS2 via the cell array CA by the wirings WCL[1] to WCL[n]. In FIG. 20, the wirings WSL[1] to WSL[m], wirings XCL[1] to XCL[m], and wirings WCL[1] to WCL[n] extend in the z-direction.

[0301] Furthermore, each of the cells in the cell array CA is electrically connected to one of the lines WCL[1] through WCL[n], one of the lines WSL[1] through WSL[m], and one of the lines XCL[1] through XCL[m]. Therefore, the cells included in the cell array CA are arranged in a matrix of at least m rows and n columns.

[0302] The circuit WCS has a function of supplying current to the wirings WCL[1] to WCL[n] in an amount corresponding to the weight data, and therefore is electrically connected to each of the wirings WCL[1] to WCL[n] via the circuit SWS1.

[0303] The circuit SWS1 has a function of bringing the circuit WCS into electrical continuity or non-conduction between it and each of the wirings WCL[1] to WCL[n].

[0304] The circuit WSD is electrically connected to the wirings WSL[1] to WSL[m]. When writing weight data to the cells included in the cell array CA, the circuit WSD has a function of selecting a row of the cell array CA that becomes the write destination of the weight data by supplying a predetermined signal to the wirings WSL[1] to WSL[m]. That is, the wirings WSL[1] to WSL[m] function as write word lines.

[0305] The circuit XCS is electrically connected to the wirings XCL[1] to XCL[m]. The circuit XCS has a function of flowing a current in an amount corresponding to reference data, which will be described later, or a current in an amount corresponding to input data, through the wirings XCL[1] to XCL[m].

[0306] The circuit PTC includes circuits PTR[1] to PTR[m]. The first terminal of the circuit PTR[1] is electrically connected to the wiring XCL[1], the first terminal of the circuit PTR[i] is electrically connected to the wiring XCL[i], and the first terminal of the circuit PTR[m] is electrically connected to the wiring XCL[m].

[0307] Also, the second terminal of the circuit PTR[1] is electrically connected to the wiring EIL[1] of the layer ERL, the second terminal of the circuit PTR[i] is electrically connected to the wiring EIL[i] of the layer ERL, and the second terminal of the circuit PTR[m] is electrically connected to the wiring EIL[m] of the layer ERL.

[0308] Specifically, for example, in a top view of the display device 10, plugs or the like are provided at locations where the respective second terminals of the circuits PTR[1] to PTR[m] intersect with the respective wirings EIL[1] to EIL[m], and the respective second terminals of the circuits PTR[1] to PTR[m] and the respective wirings EIL[1] to EIL[m] are electrically connected.

[0309] Circuit PTR[1] has the function of making the connection between wiring EIL[1] and wiring XCL[1] in a conductive state or a non-conductive state. Similarly, circuit PTR[i] has the function of making the connection between wiring EIL[i] and wiring XCL[i] in a conductive state or a non-conductive state, and circuit PTR[m] has the function of making the connection between wiring EIL[m] and wiring XCL[m] in a conductive state or a non-conductive state. That is, each of circuits PTR[1] to PTR[m] has the function as a switching element.

[0310] Circuit ITS has the function of acquiring the amount of current flowing through wirings WCL[1] to WCL[n] and outputting a result corresponding to the amount of current to wirings OL[1] to OL[n]. Therefore, circuit ITS is electrically connected to each of wirings WCL[1] to WCL[n] via circuit SWS2. Also, circuit ITS is electrically connected to each of wirings OL[1] to OL[n].

[0311] Circuit SWS2 has the function of making the connection between circuit ITS and each of wirings WCL[1] to WCL[n] in a conductive state or a non-conductive state.

[0312] In layer ERL of FIG. 20, as an example, it is preferable that wirings EIL[1] to EIL[m] extend along the x direction. That is, as the direction in which wirings EIL[1] to EIL[m] extend, for example, in the line of sight in the y direction, it is preferable that they are substantially parallel to wirings XCL[1] to XCL[m], and more preferably parallel. Also, for example, in a top view, it is preferable that wirings EIL[1] to EIL[m] are substantially parallel to wirings XCL[1] to XCL[m] included in layer CCL, and more preferably parallel.

[0313] As described above, by applying the display device 10 shown in Fig. 20, the location of the sensor array SCA on the display device including the arithmetic circuit (layer CCL) can be determined almost freely. Therefore, for example, the sensor array SCA can be disposed at or near the center of the display device when viewed from above. Furthermore, the layout of the arithmetic circuit included in the layer CCL does not depend on the location of the sensor array SCA, which increases the degree of freedom in the layout of the arithmetic circuit and its surrounding wiring.

[0314] <Three-dimensional structure of driving circuits, pixel circuits, and light-emitting elements> 21A and 21B show an example of the configuration of pixel circuit 51 and light-emitting element 61 connected to pixel circuit 51, as shown in Fig. 18A. Fig. 21A is a diagram showing the connection of each element, and Fig. 21B is a diagram schematically showing the hierarchical relationship between layer 20 including drive circuit 30, layer 50 including multiple transistors that pixel circuit 51 has, and layer 60 including light-emitting element 61.

[0315] 21A and 21B include a pixel circuit 51 including a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The number of transistors, the number of capacitors, and the electrical connections between elements in the pixel circuit 51 are not limited to those shown in FIGS. 21A and 21B , and other configurations may be used. The transistors 52A, 52B, and 52C may be OS transistors. Each of the OS transistors 52A, 52B, and 52C preferably includes a back gate electrode. In this case, the back gate electrode may be configured to receive the same signal as the gate electrode, or a signal different from that of the gate electrode.

[0316] The transistor 52B includes a gate electrode electrically connected to the transistor 52A, a first electrode electrically connected to the light-emitting element 61, and a second electrode electrically connected to a wiring ANO. The wiring ANO is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0317] Transistor 52A has a first terminal electrically connected to the gate electrode of transistor 52B, a second terminal electrically connected to wiring SL that functions as a source line, and has a gate electrode. Transistor 52A has a function of controlling a conductive state or a non-conductive state based on the potential of wiring GL1 that functions as a gate line.

[0318] Transistor 52C has a first terminal electrically connected to wiring V0, a second terminal electrically connected to light-emitting element 61, and has a gate electrode. Transistor 52C has a function of controlling a conductive state or a non-conductive state based on the potential of wiring GL2 that functions as a gate line. Wiring V0 is wiring for providing a reference potential and for outputting the current flowing through pixel circuit 51 to drive circuit 30 or arithmetic circuit 40.

[0319] Capacitor 53 includes a conductive film electrically connected to the gate electrode of transistor 52B and a conductive film electrically connected to the second electrode of transistor 52C.

[0320] Light-emitting element 61 includes a first electrode electrically connected to the first electrode of transistor 52B and a second electrode electrically connected to wiring VCOM. Wiring VCOM is wiring for providing a potential for supplying current to light-emitting element 61.

[0321] Thereby, the intensity of the light emitted by light-emitting element 61 can be controlled according to the image signal applied to the gate electrode of transistor 52B. Also, variations in the gate-source voltage of transistor 52B can be suppressed by the reference potential of wiring V0 applied through transistor 52C.

[0322] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to the arithmetic circuit 40 or the like.

[0323] Note that the light-emitting element described in one embodiment of the present invention refers to a self-luminous light-emitting element such as an organic light-emitting element (also referred to as an OLED (organic light-emitting diode)). Note that the light-emitting element electrically connected to the pixel circuit can be a self-luminous light-emitting element such as an LED (light-emitting diode), a micro LED, a QLED (quantum-dot light-emitting diode), or a semiconductor laser.

[0324] In the configuration shown in FIG. 21B as an example, the wiring electrically connecting the pixel circuits 51 and the drive circuit 30 can be shortened, thereby reducing the wiring resistance of the wiring. This allows data to be written at high speed, thereby enabling the display device 10 to be driven at high speed. This allows a sufficient frame period to be ensured even if the display device 10 has a large number of pixel circuits 51, thereby increasing the pixel density of the display device 10. Furthermore, increasing the pixel density of the display device 10 increases the resolution of the image displayed by the display device 10. For example, the pixel density of the display device 10 can be set to 1000 ppi or more, 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 10 can be used as a display device for AR or VR, for example, and can be suitably applied to electronic devices in which the display unit is close to the user, such as a head-mounted display.

[0325] 21A and 21B may be provided with the arithmetic circuit 40, the cell array CA, and the photodiode PD, which is a light-receiving element, respectively, as described in the third embodiment. Therefore, the display device 10 may be configured to include an arithmetic circuit and a drive circuit, a pixel circuit and a cell array, a light-emitting element, and a light-receiving element.

[0326] As described above, the display device 10 of one embodiment of the present invention can have a stacked structure including the light-emitting element 61, the pixel circuit 51, and the driver circuit 30, thereby enabling an extremely high pixel aperture ratio (effective display area ratio). Furthermore, the pixel circuits 51 can be arranged at extremely high density, enabling extremely high pixel resolution. Because of its extremely high resolution, the display device 10 can be suitably used for VR devices such as head-mounted displays or glasses-type AR devices. For example, even in a configuration in which the display portion of the display device 10 is viewed through an optical component such as a lens, the display device 10 has an extremely high-resolution display portion, and therefore, pixels are not visible even when the display portion is enlarged with the lens, enabling highly immersive display.

[0327] Furthermore, the display device 10 of one embodiment of the present invention can have a stacked structure including the light-receiving element 62, the cell array CA, and the arithmetic circuit 40. Therefore, the display device 10 can perform arithmetic processing with high arithmetic efficiency using a minute current output from the light-receiving element 62 as input data. Furthermore, the display device 10 can have a structure in which the light-receiving unit 14 is located close to the display unit 13. This allows the user to view an image with their eyes and capture images of the user's eyes and / or their surroundings. Furthermore, the cell IM of the cell array CA can retain analog data written in response to a minute current for a long period of time. Furthermore, the arithmetic circuit 40, which performs a product-sum operation using a minute current, can perform arithmetic processing with high arithmetic efficiency.

[0328] <Top view and cross-sectional view of the light-emitting element> 22A is a schematic top view illustrating a configuration example in which a light-emitting element and a light-receiving element are arranged in one pixel in a display device 10 according to one embodiment of the present invention. The display device 10 includes a plurality of light-emitting elements 61R that emit red light, a plurality of light-emitting elements 61G that emit green light, a plurality of light-emitting elements 61B that emit blue light, and a plurality of light-receiving elements 62. In FIG. 22A, in order to easily distinguish between the light-emitting elements 61, the light-emitting regions of the light-emitting elements 61 are labeled with R, G, and B. Furthermore, the light-receiving regions of the light-receiving elements 62 are labeled with PD.

[0329] The light-emitting elements 61R, 61G, 61B, and the light-receiving elements 62 are arranged in a matrix. FIG. 22A shows an example in which the light-emitting elements 61R, 61G, and 61B are arranged in the X direction, and the light-receiving elements 62 are arranged below them. FIG. 22A also shows an example in which the light-emitting elements 61 emitting light of the same color are arranged in the Y direction intersecting the X direction. In the display device 10 shown in FIG. 22A, a pixel 80 can be configured by, for example, a sub-pixel having the light-emitting element 61R, a sub-pixel having the light-emitting element 61G, and a sub-pixel having the light-emitting element 61B arranged in the X direction, and a sub-pixel having the light-receiving element 62 provided below these sub-pixels.

[0330] The light-emitting elements 61R, 61G, and 61B are preferably EL elements such as organic light-emitting diodes (OLEDs) or quantum-dot light-emitting diodes (QLEDs). Examples of light-emitting materials included in the EL elements include fluorescent materials, phosphorescent materials, inorganic compounds (quantum dot materials, etc.), and thermally activated delayed fluorescence (TADF) materials. The TADF material may be a material that is in thermal equilibrium between a singlet excited state and a triplet excited state. Such TADF materials have a short emission lifetime (excitation lifetime), which can suppress a decrease in the efficiency of the light-emitting elements in the high-brightness range.

[0331] As the light receiving element 62, for example, a pn-type or pin-type photodiode can be used. The light receiving element 62 functions as a photoelectric conversion element that detects light incident on the light receiving element 62 and generates electric charges. The amount of generated electric charges is determined based on the amount of incident light.

[0332] In particular, as the light receiving element 62, it is preferable to use an organic photodiode having a layer containing an organic compound. The organic photodiode is easy to be thinned, lightened, and enlarged in area, and also has a high degree of freedom in shape and design, so it can be applied to various display devices.

[0333] In one aspect of the present invention, an organic EL element is used as the light emitting element 61, and an organic photodiode is used as the light receiving element 62. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be incorporated into a display device using an organic EL element. The separation between the organic EL elements and the organic photodiode is preferably performed by a photolithography method. Thereby, since the intervals between the light emitting elements and between the organic photodiodes can be narrowed, a display device with a high aperture ratio can be realized as compared with the case of using a shadow mask such as a metal mask, for example.

[0334] FIG. 22A shows a common electrode 81 and a connection electrode 82. Here, the connection electrode 82 is electrically connected to the common electrode 81. The connection electrode 82 is provided outside the display portion where the light emitting element 61 and the light receiving element 62 are arranged. Also, FIG. 22A shows, by a broken line, the common electrode 81 having a region overlapping with the light emitting element 61, the light receiving element 62, and the connection electrode 82.

[0335] The connection electrode 82 can be provided along the outer periphery of the display portion. For example, it may be provided along one side of the outer periphery of the display portion, or may be provided over two or more sides of the outer periphery of the display portion. That is, when the upper surface shape of the display portion is rectangular, the upper surface shape of the connection electrode 82 can be strip-shaped, L-shaped, U-shaped (angle bracket-shaped), or square-shaped, etc.

[0336] Fig. 22B is a schematic top view showing an example of the configuration of display device 10, which is a modification of display device 10 shown in Fig. 22A. Display device 10 shown in Fig. 22B differs from display device 10 shown in Fig. 22A in that it includes a light-emitting element 61IR that emits infrared light. Light-emitting element 61IR can emit, for example, near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less).

[0337] 22B, in addition to light-emitting elements 61R, 61G, and 61B, a light-emitting element 61IR is arranged in the X direction, and a light-receiving element 62 is arranged below them. The light-receiving element 62 has a function of detecting infrared light.

[0338] Fig. 23A is a cross-sectional view corresponding to dashed-dotted line A1-A2 in Fig. 22A, and Fig. 23B is a cross-sectional view corresponding to dashed-dotted line B1-B2 in Fig. 22A. Fig. 23C is a cross-sectional view corresponding to dashed-dotted line C1-C2 in Fig. 22A, and Fig. 23D is a cross-sectional view corresponding to dashed-dotted line D1-D2 in Fig. 22A. The light-emitting element 61R, the light-emitting element 61G, the light-emitting element 61B, and the light-receiving element 62 are provided on a substrate 83. Furthermore, when the display device 10 has a light-emitting element 61IR, the light-emitting element 61IR is provided on the substrate 83.

[0339] In this specification and the like, for example, when it is said that "B is on A" or "B is below A," A and B do not necessarily have to have an area where they contact each other.

[0340] 23A shows an example of the cross-sectional configuration of the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B, and FIG.

[0341] The light-emitting element 61R includes a pixel electrode 84R, a hole injection layer 85R, a hole transport layer 86R, a light-emitting layer 87R, an electron transport layer 88R, a common layer 89, and a common electrode 81. The light-emitting element 61G includes a pixel electrode 84G, a hole injection layer 85G, a hole transport layer 86G, a light-emitting layer 87G, an electron transport layer 88G, a common layer 89, and a common electrode 81. The light-emitting element 61B includes a pixel electrode 84B, a hole injection layer 85B, a hole transport layer 86B, a light-emitting layer 87B, an electron transport layer 88B, a common layer 89, and a common electrode 81. The light-receiving element 62 includes a pixel electrode 84PD, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88PD, a common layer 89, and a common electrode 81.

[0342] In the following description, when explaining matters common to the hole injection layer 85R, the hole injection layer 85G, the hole injection layer 85B, etc., it may be referred to as the hole injection layer 85. Also, when explaining matters common to the hole transport layer 86R, the hole transport layer 86G, the hole transport layer 86B, the hole transport layer 86PD, etc., it may be referred to as the hole transport layer 86. Also, when explaining matters common to the light-emitting layer 87R, the light-emitting layer 87G, the light-emitting layer 87B, etc., it may be referred to as the light-emitting layer 87. Also, when explaining matters common to the electron transport layer 88R, the electron transport layer 88G, the electron transport layer 88B, the electron transport layer 88PD, etc., it may be referred to as the electron transport layer 88.

[0343] The common layer 89 functions as an electron injection layer in the light-emitting element 61. On the other hand, the common layer 89 functions as an electron transport layer in the light-receiving element 62. For this reason, the light-receiving element 62 may not have the electron transport layer 88PD.

[0344] The hole injection layer 85, the hole transport layer 86, the electron transport layer 88, and the common layer 89 can also be referred to as functional layers.

[0345] The pixel electrode 84, the hole injection layer 85, the hole transport layer 86, the light-emitting layer 87, and the electron transport layer 88 can be provided separately for each element. The common layer 89 and the common electrode 81 are provided in common to the light-emitting element 61R, the light-emitting element 61G, the light-emitting element 61B, and the light-receiving element 62.

[0346] Note that the light-emitting element 61 and the light-receiving element 62 may have a hole blocking layer and an electron blocking layer in addition to the layers shown in FIG. 23A. Further, the light-emitting element 61 and the light-receiving element 62 may have a layer containing a bipolar substance (a substance having high electron transporting property and hole transporting property) or the like.

[0347] A gap is provided between the common layer 89 and the insulating layer 92 described later. Thereby, it is possible to suppress the common layer 89 from coming into contact with the side surfaces of the light-emitting layer 87, the light-receiving layer 90, the hole transporting layer 86, and the hole injection layer 85. Thereby, a short circuit in the light-emitting element 61 and a short circuit in the light-receiving element 62 can be suppressed.

[0348] The above-described gap is more likely to be formed as the distance between the light-emitting layers 87 is shorter. For example, when the distance is 1 μm or less, preferably 500 nm or less, more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less, the above-described gap can be preferably formed.

[0349] In FIG. 23A, the light-emitting element 61 is shown having a configuration in which a pixel electrode 84, a hole injection layer 85, a hole transporting layer 86, a light-emitting layer 87, an electron transporting layer 88, a common layer 89 (electron injection layer), and a common electrode 81 are provided in this order from the lower layer. Further, in FIG. 23B, the light-receiving element 62 is shown having a configuration in which a pixel electrode 84PD, a hole transporting layer 86PD, a light-receiving layer 90, an electron transporting layer 88PD, a common layer 89, and a common electrode 81 are provided in this order from the lower layer, but one aspect of the present invention is not limited to this. For example, in the light-emitting element 61, a pixel electrode, an electron injection layer, an electron transporting layer, a light-emitting layer, a hole transporting layer, a hole injection layer, and a common electrode may be provided in this order from the lower layer, and in the light-receiving element 62, a pixel electrode, an electron transporting layer, a light-receiving layer, a hole transporting layer, and a common electrode may be provided in this order from the lower layer. In this case, the hole injection layer included in the light-emitting element 61 can be used as the common layer, and the common layer can be provided between the hole transporting layer included in the light-receiving element 62 and the common electrode. Further, in the light-emitting element 61, the electron injection layer can be separated for each element.

[0350] In the following description, the electron transport layer is assumed to be provided above the hole transport layer. However, the following description can also be applied to the case where the electron transport layer is provided below the hole transport layer, for example, by replacing "electrons" with "holes" and "holes" with "electrons."

[0351] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound and a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0352] The hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light emitting layer. The hole transport layer is a layer that contains a hole transporting material. Examples of the hole transporting material include 10 -6 cm 2 A material having a hole mobility of 1 / Vs or more is preferred. Note that other materials can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton), is preferred.

[0353] The electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light emitting layer. The electron transport layer is a layer that contains an electron transporting material. The electron transporting material is a material having a molecular weight of 1×10 -6 cm 2A substance having an electron mobility of 10^-6 cm^2 / Vs or more is preferred. In addition, as long as the substance has higher electron transportability than holes, other substances can also be used. As the electron transport material, in addition to metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, etc., oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and other electron transport materials such as π-electron-deficient heteroaromatic compounds containing nitrogen-containing heteroaromatic compounds can be used.

[0354] The electron injection layer is a layer that injects electrons from the cathode into the electron transport layer and is a layer containing a material with high electron injection properties. As the material with high electron injection properties, an alkali metal, an alkaline earth metal, or a compound thereof can be used. As the material with high electron injection properties, a composite material containing an electron transport material and a donor material (electron-donating material) can also be used.

[0355] As the electron injection layer, for example, lithium, cesium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF2), 8-(quinolinolato)lithium (abbreviation: Liq), 2-(2-pyridyl)phenolato lithium (abbreviation: LiPP), 2-(2-pyridyl)-3-pyridinolato lithium (abbreviation: LiPPy), 4-phenyl-2-(2-pyridyl)phenolato lithium (abbreviation: LiPPP), lithium oxide (LiO x ), cesium carbonate, etc., such as alkali metals, alkaline earth metals, or compounds thereof can be used.

[0356] Alternatively, the electron injection layer may be formed using a material having electron transport properties. For example, a compound having an unshared electron pair and an electron-deficient heteroaromatic ring may be used as the material having electron transport properties. Specifically, a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), and a triazine ring may be used.

[0357] The organic compound having an unshared electron pair preferably has a lowest unoccupied molecular orbital (LUMO) of -3.6 eV to -2.3 eV. Generally, the highest occupied molecular orbital (HOMO) level and the LUMO level of an organic compound can be estimated by cyclic voltammetry (CV), photoelectron spectroscopy, optical absorption spectroscopy, inverse photoelectron spectroscopy, or the like.

[0358] Examples of organic compounds with lone electron pairs include 4,7-diphenyl-1,10-phenanthroline (abbreviated as BPhen), 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviated as NBPhen), diquinoxalino[2,3-a:2',3'-c]phenazine (abbreviated as HATNA), and 2,4,6-tris[3'-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviated as TmPPPyTz). NBPhen has a higher glass transition temperature (Tg) and better heat resistance than BPhen.

[0359] The light-emitting layer is a layer containing a light-emitting substance. The light-emitting layer can contain one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0360] Examples of the light-emitting material include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0361] Examples of the fluorescent material include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, naphthalene derivatives, and the like.

[0362] Examples of the phosphorescent material include organometallic complexes (particularly iridium complexes) having a 4H-triazole skeleton, 1H-triazole skeleton, imidazole skeleton, pyrimidine skeleton, pyrazine skeleton, or pyridine skeleton, organometallic complexes (particularly iridium complexes) having a phenylpyridine derivative having an electron-withdrawing group as a ligand, platinum complexes, rare earth metal complexes, and the like.

[0363] In addition to the light-emitting substance (guest material), the light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.). As the one or more organic compounds, one or both of a hole-transporting material and an electron-transporting material can be used. Further, a bipolar material or a TADF material may be used as the one or more organic compounds.

[0364] The light-emitting layer preferably has, for example, a phosphorescent material, a hole-transporting material, and an electron-transporting material that are a combination likely to form an exciplex. By adopting such a configuration, efficient light emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the exciplex to the light-emitting substance (phosphorescent material), can be obtained. By selecting a combination that forms an exciplex that emits light having a wavelength overlapping with the absorption band on the lowest energy side of the light-emitting substance, energy transfer becomes smooth and efficient light emission can be obtained. With this configuration, high efficiency, low-voltage driving, and long life of the light-emitting element can be achieved simultaneously.

[0365] The light-emitting layer 87R of the light-emitting element 61R has a light-emitting organic compound that emits light having intensity at least in the red wavelength range. The light-emitting layer 87G of the light-emitting element 61G has a light-emitting organic compound that emits light having intensity at least in the green wavelength range. The light-emitting layer 87B of the light-emitting element 61B has a light-emitting organic compound that emits light having intensity at least in the blue wavelength range. The light-receiving layer 90 of the light-receiving element 62 has, for example, an organic compound having detection sensitivity in the wavelength range of visible light.

[0366] A conductive film having light transmittance with respect to visible light is used for either one of the pixel electrode 84 and the common electrode 81, and a conductive film having reflectivity is used for the other. By making the pixel electrode 84 light-transmissive and the common electrode 81 reflective, the display device 10 can be made a bottom emission type display device. On the other hand, by making the pixel electrode 84 reflective and the common electrode 81 light-transmissive, the display device 10 can be made a top emission type display device. Note that by making both the pixel electrode 84 and the common electrode 81 light-transmissive, the display device 10 can also be made a dual emission type display device.

[0367] In addition, the light-emitting element 61 preferably has a microcavity structure. Thereby, the light emitted from the light-emitting layer 87 can be resonated between the pixel electrode 84 and the common electrode 81, and the light emitted from the light-emitting element 61 can be enhanced.

[0368] When the light-emitting element 61 has a microcavity structure, one of the common electrode 81 or the pixel electrode 84 is preferably an electrode having both light transmittance and reflectivity (semi-transmissive and semi-reflective electrode), and the other of the common electrode 81 or the pixel electrode 84 is an electrode having reflectivity (reflective electrode). Here, the semi-transmissive and semi-reflective electrode can have a laminated structure of a reflective electrode and an electrode having light transmittance with respect to visible light (also referred to as a transparent electrode). Note that the transparent electrode can be referred to as an optical adjustment layer.

[0369] The light transmittance of the transparent electrode shall be 40% or more. For example, for the light-emitting element 61, it is preferable to use an electrode with a light transmittance of 40% or more for visible light (light with a wavelength of 400 nm or more and less than 750 nm). Also, the reflectance of visible light of the semi-transmissive / semi-reflective electrode shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectance of visible light of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. Also, the resistivity of these electrodes is preferably -2 1×10

[0370] An insulating layer 92 is provided to cover the ends of the pixel electrode 84R, the pixel electrode 84G, the pixel electrode 84B, and the pixel electrode 84PD. The end of the insulating layer 92 is preferably in a tapered shape. Note that the insulating layer 92 may not be provided if it is not necessary.

[0371] For example, the hole injection layer 85R, the hole injection layer 85G, the hole injection layer 85B, and the hole transport layer 86PD each have a region in contact with the upper surface of the pixel electrode 84 and a region in contact with the surface of the insulating layer 92. Also, the ends of the hole injection layer 85R, the ends of the hole injection layer 85G, the ends of the hole injection layer 85B, and the ends of the hole transport layer 86PD are located on the insulating layer 92.

[0372] As shown in Fig. 23A, a gap is provided, for example, between two light-emitting layers 87 between light-emitting elements 61 that emit different colors of light. Thus, for example, it is preferable that the light-emitting layer 87R, the light-emitting layer 87G, and the light-emitting layer 87B are provided so as not to be in contact with each other. Thereby, it is possible to suitably prevent current from flowing through two adjacent light-emitting layers 87 and causing unintended light emission. Therefore, the contrast of the display device 10 can be increased, and thus the display quality of the display device 10 can be improved.

[0373] A protective layer 91 is provided on the common electrode 81. The protective layer 91 has the function of preventing impurities such as water from diffusing from above into each light-emitting element.

[0374] The protective layer 91 may have, for example, a single-layer structure or a multilayer structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, the protective layer 91 may be made of a semiconductor material such as indium gallium oxide or indium gallium zinc oxide.

[0375] In this specification and the like, a silicon oxynitride film refers to a film whose composition contains more oxygen than nitrogen, and a silicon nitride oxide film refers to a film whose composition contains more nitrogen than oxygen.

[0376] Alternatively, a laminated film of an inorganic insulating film and an organic insulating film may be used as the protective layer 91. For example, a configuration in which an organic insulating film is sandwiched between a pair of inorganic insulating films is preferable. Furthermore, it is preferable that the organic insulating film functions as a planarizing film. This allows the upper surface of the organic insulating film to be flat, improving the coverage of the inorganic insulating film thereon and enhancing the barrier properties. Furthermore, since the upper surface of the protective layer 91 is flat, when a structure (e.g., a color filter, a touch sensor electrode, a lens array, etc.) is provided above the protective layer 91, the influence of uneven shapes caused by the structure below can be reduced, which is preferable.

[0377] In FIGS. 23A and 23B, when the insulating layer 92 is not provided, the distance between the light-emitting elements can be narrowed. For example, FIGS. 24A and 24B show diagrams in which the insulating layer 92 is omitted. Note that the region 92R between the light-emitting elements in FIGS. 24A and 24B may have an insulating layer containing an organic material or the like. For example, the region 92R may be filled with an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimide amide resin, a silicone resin, a siloxane resin, a benzocyclobutene-based resin, a phenol resin, or a precursor of these resins. Further, the region 92R may be filled with a photosensitive resin. As the photosensitive resin, a photoresist may be used. The photosensitive resin can be a positive-type material or a negative-type material.

[0378] FIG. 23C shows a cross-sectional configuration example of the display device 10 in the Y direction, specifically, a cross-sectional configuration example of the light-emitting element 61R and the light-receiving element 62. Note that the light-emitting elements 61G and 61B can also be arranged in the Y direction in the same manner as the light-emitting element 61R.

[0379] FIG. 23D shows a connection portion 93 where the connection electrode 82 and the common electrode 81 are electrically connected. In the connection portion 93, the common electrode 81 is provided in contact with the connection electrode 82, and the protective layer 91 is provided to cover the common electrode 81. Further, the insulating layer 92 is provided to cover the end portion of the connection electrode 82.

[0380] <Configuration example of light-emitting element> As shown in FIG. 25A, the light-emitting element has an EL layer 686 between a pair of electrodes (electrode 672 and electrode 688). The EL layer 686 can be composed of a plurality of layers such as layer 4420, light-emitting layer 4411, and layer 4430. The layer 4420 can have, for example, a layer containing a material with high electron injection property (electron injection layer) and a layer containing a material with high electron transport property (electron transport layer). The light-emitting layer 4411 has, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a material with high hole injection property (hole injection layer) and a layer containing a material with high hole transport property (hole transport layer).

[0381] A structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 25A is referred to as a single structure in this specification.

[0382] 25B shows a modification of the EL layer 686 included in the light-emitting element shown in Fig. 25A. Specifically, the light-emitting element shown in Fig. 25B includes a layer 4430-1 on an electrode 672, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and an electrode 688 on the layer 4420-2. For example, when the electrode 672 is an anode and the electrode 688 is a cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. 25B , it is possible to efficiently inject carriers into light-emitting layer 4411 and increase the efficiency of carrier recombination in light-emitting layer 4411.

[0383] As shown in FIG. 25C, a configuration in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between layer 4420 and layer 4430 is also a variation of the single structure.

[0384] Furthermore, as shown in Figure 25D, a configuration in which multiple light-emitting units (EL layer 686a, EL layer 686b) are connected in series via an intermediate layer (charge generation layer) 4440 is referred to as a tandem structure in this specification. Note that, although the configuration shown in Figure 25D is referred to as a tandem structure in this specification, the present invention is not limited to this, and for example, the tandem structure may also be referred to as a stack structure. Note that by using a tandem structure, a light-emitting element capable of emitting light with high brightness can be obtained.

[0385] Note that in FIGS. 25C and 25D as well, as shown in FIG. 25B, the layer 4420 and the layer 4430 may be a laminated structure composed of two or more layers.

[0386] Also, for each light-emitting element, a structure that creates different emission colors (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure.

[0387] Also, when comparing the above-mentioned single structure, tandem structure, and SBS structure, the power consumption can be lowered in the order of the SBS structure, tandem structure, and single structure. When it is desired to keep the power consumption low, it is preferable to use the SBS structure. On the other hand, the single structure and tandem structure are suitable because the manufacturing process is simpler than that of the SBS structure, so the manufacturing cost can be reduced or the manufacturing yield can be increased.

[0388] The emission color of the light-emitting element can be red, green, blue, cyan, magenta, yellow, white, etc. depending on the material constituting the EL layer 686. Also, by providing a microcavity structure to the light-emitting element, the color purity can be further enhanced.

[0389] A light-emitting element that emits white light preferably has a configuration in which the light-emitting layer contains two or more types of light-emitting substances. To obtain white light emission, light-emitting substances can be selected such that the emissions of two or more light-emitting substances are in a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer be in a complementary color relationship, a light-emitting element that emits white light as a whole can be obtained. The same applies to the case of a light-emitting element having three or more light-emitting layers.

[0390] The light-emitting layer preferably contains two or more light-emitting substances that exhibit emissions such as R (red), G (green), B (blue), Y (yellow), O (orange), etc. Or, there are two or more light-emitting substances, and the emission of each light-emitting substance preferably contains spectral components of two or more colors among R, G, and B.

[0391] <Configuration Examples of Light-Emitting Elements and Light-Receiving Elements> The display device according to one aspect of the present invention is of a top emission type that emits light in a direction opposite to the substrate on which the light-emitting element is formed. In the present embodiment, a display device including a top emission type light-emitting element and a light-receiving element will be described as an example.

[0392] In this specification and the like, unless otherwise specified, even when describing a configuration having a plurality of elements (such as a light-emitting element and a light-emitting layer), when describing matters common to each element, the alphabet will be omitted. For example, when describing matters common to the light-emitting layer 383R and the light-emitting layer 383G, etc., it may be described as the light-emitting layer 383.

[0393] The display device 380A shown in FIG. 26A includes a light-receiving element 370PD, a light-emitting element 370R that emits red (R) light, a light-emitting element 370G that emits green (G) light, and a light-emitting element 370B that emits blue (B) light.

[0394] Each light-emitting element has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, a light-emitting layer, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 laminated in this order. The light-emitting element 370R has a light-emitting layer 383R, the light-emitting element 370G has a light-emitting layer 383G, and the light-emitting element 370B has a light-emitting layer 383B. The light-emitting layer 383R has a light-emitting substance that emits red light, the light-emitting layer 383G has a light-emitting substance that emits green light, and the light-emitting layer 383B has a light-emitting substance that emits blue light.

[0395] The light-emitting element is an electroluminescent element that emits light toward the common electrode 375 by applying a voltage between the pixel electrode 371 and the common electrode 375.

[0396] The light-receiving element 370PD has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, an active layer 373, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 laminated in this order.

[0397] The light receiving element 370PD is a photoelectric conversion element that receives light incident from outside the display device 380A and converts it into an electrical signal.

[0398] In this embodiment, in both the light-emitting element and the light-receiving element, the pixel electrode 371 functions as an anode and the common electrode 375 functions as a cathode. In other words, by applying a reverse bias between the pixel electrode 371 and the common electrode 375 and driving the light-receiving element, the light-receiving element can detect light incident on the light-receiving element, generate electric charges, and extract the electric charges as a current.

[0399] In the display device of this embodiment, an organic compound is used for the active layer 373 of the light-receiving element 370PD. The layers of the light-receiving element 370PD other than the active layer 373 can be configured in common with the light-emitting element. Therefore, by simply adding a step of forming the active layer 373 to the manufacturing process of the light-emitting element, the light-receiving element 370PD can be formed in parallel with the formation of the light-emitting element. Furthermore, the light-emitting element and the light-receiving element 370PD can be formed on the same substrate. Therefore, the light-receiving element 370PD can be built into the display device without significantly increasing the number of manufacturing steps.

[0400] In the display device 380A, the light receiving element 370PD and the light emitting element have a common configuration, except that the active layer 373 of the light receiving element 370PD and the light emitting layer 383 of the light emitting element are fabricated separately. However, the configuration of the light receiving element 370PD and the light emitting element is not limited to this. The light receiving element 370PD and the light emitting element may have layers fabricated separately from each other, in addition to the active layer 373 and the light emitting layer 383. It is preferable that the light receiving element 370PD and the light emitting element have one or more layers used in common (common layers). This allows the light receiving element 370PD to be incorporated into the display device without significantly increasing the number of manufacturing steps.

[0401] A conductive film that transmits visible light is used for the electrode from which light is extracted, between the pixel electrode 371 and the common electrode 375. It is preferable to use a conductive film that reflects visible light for the electrode from which light is not extracted.

[0402] It is preferable that a microcavity structure is applied to the light-emitting element included in the display device of the present embodiment. Therefore, it is preferable that one of the pair of electrodes included in the light-emitting element has an electrode (semi-transmissive / semi-reflective electrode) having transmissivity and reflectivity with respect to visible light, and the other has an electrode (reflective electrode) having reflectivity with respect to visible light. By having a microcavity structure in the light-emitting element, the light emitted from the light-emitting layer can be resonated between both electrodes, and the light emitted from the light-emitting element can be enhanced.

[0403] Note that the semi-transmissive / semi-reflective electrode can have a laminated structure of a reflective electrode and an electrode having transmissivity with respect to visible light (also referred to as a transparent electrode).

[0404] The light transmittance of the transparent electrode is set to 40% or more. For example, it is preferable to use an electrode having a transmittance of 40% or more for visible light (light having a wavelength of 400 nm or more and less than 750 nm) for the light-emitting element. The reflectivity of visible light of the semi-transmissive / semi-reflective electrode is set to 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectivity of visible light of the reflective electrode is set to 40% or more and 100% or less, preferably 70% or more and 100% or less. Further, the resistivity of these electrodes is preferably 1×10 -2 Ωcm or less. Note that when the light-emitting element emits near-infrared light (light having a wavelength of 750 nm or more and 1300 nm or less), it is preferable that the transmittance or reflectivity of near-infrared light of these electrodes satisfies the above numerical range in the same manner as the transmittance or reflectivity of visible light.

[0405] The light-emitting element has at least a light-emitting layer 383. The light-emitting element may further include, as layers other than the light-emitting layer 383, a layer containing a substance with high hole-injecting property, a substance with high hole-transporting property, a hole-blocking material, a substance with high electron-transporting property, a substance with high electron-injecting property, an electron-blocking material, or a bipolar substance (a substance with high electron-transporting property and high hole-transporting property).

[0406] For example, the light-emitting element and the light-receiving element may have one or more layers of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer in common, or the light-emitting element and the light-receiving element may have one or more layers of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer formed differently from each other.

[0407] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound or a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0408] In a light-emitting element, the hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light-emitting layer. In a light-receiving element, the hole transport layer is a layer that transports holes generated in the active layer based on incident light to the anode. The hole transport layer is a layer that contains a hole transport material. The hole transport material is a material having a concentration of 1×10 -6 cm 2 A material having a hole mobility of 1 / Vs or more is preferred. Note that other materials can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton), is preferred.

[0409] In a light-emitting element, the electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light-emitting layer. In a light-receiving element, the electron transport layer is a layer that transports electrons generated in the active layer based on incident light to the cathode. The electron transport layer is a layer that contains an electron transporting material. The electron transporting material is a material having a concentration of 1×10 -6 cm 2A substance having an electron mobility of / Vs or higher is preferred. In addition, any other substance can be used as long as it has a higher electron transport property than holes. As the electron transport material, in addition to metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, etc., oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and other highly electron-transporting materials such as π-electron-deficient heteroaromatic compounds containing nitrogen-containing heteroaromatic compounds can be used.

[0410] The electron injection layer is a layer that injects electrons from the cathode into the electron transport layer and is a layer containing a material with high electron injection properties. As the material with high electron injection properties, an alkali metal, an alkaline earth metal, or a compound thereof can be used. As the material with high electron injection properties, a composite material containing an electron transport material and a donor material (electron-donating material) can also be used.

[0411] The light-emitting layer 383 is a layer containing a light-emitting substance. The light-emitting layer 383 can have one or more light-emitting substances. As the light-emitting substance, substances exhibiting light-emitting colors such as blue, purple, blue-violet, green, yellow-green, yellow, orange, and red can be appropriately used. In addition, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0412] Examples of the light-emitting substance include fluorescent materials, phosphorescent materials, TADF materials, quantum dot materials, etc.

[0413] Examples of the fluorescent material include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, naphthalene derivatives, etc.

[0414] Examples of the phosphorescent material include organometallic complexes (especially iridium complexes) having a 4H-triazole skeleton, 1H-triazole skeleton, imidazole skeleton, pyrimidine skeleton, pyrazine skeleton, or pyridine skeleton, organometallic complexes (especially iridium complexes) having a phenylpyridine derivative having an electron-withdrawing group as a ligand, platinum complexes, rare earth metal complexes, and the like.

[0415] In addition to the light-emitting substance (guest material), the light-emitting layer 383 may contain one or more organic compounds (host materials, assist materials, etc.). As the one or more organic compounds, one or both of a hole-transporting material and an electron-transporting material can be used. Further, a bipolar material or a TADF material may be used as the one or more organic compounds.

[0416] The light-emitting layer 383 preferably has, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination likely to form an exciplex. By adopting such a configuration, efficient light emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from an exciplex to a light-emitting substance (phosphorescent material), can be obtained. By selecting a combination that forms an exciplex that exhibits light emission overlapping the wavelength of the absorption band on the lowest energy side of the light-emitting substance, energy transfer becomes smooth and efficient light emission can be obtained. With this configuration, high efficiency, low-voltage driving, and long life of the light-emitting element can be achieved simultaneously.

[0417] As the combination of materials that form an exciplex, it is preferable that the HOMO level (highest occupied orbital level) of the hole-transporting material is a value equal to or higher than the HOMO level of the electron-transporting material. It is preferable that the LUMO level (lowest unoccupied orbital level) of the hole-transporting material is a value equal to or higher than the LUMO level of the electron-transporting material. The LUMO level and HOMO level of the material can be derived from the electrochemical characteristics (reduction potential and oxidation potential) of the material measured by cyclic voltammetry (CV) measurement.

[0418] The formation of an exciplex can be confirmed, for example, by comparing the emission spectra of a hole transporting material, the emission spectra of an electron transporting material, and the emission spectra of a mixed film obtained by mixing these materials, and observing the phenomenon that the emission spectrum of the mixed film is shifted to a longer wavelength (or has a new peak on the longer wavelength side) than the emission spectra of the respective materials. Alternatively, the transient photoluminescence (PL) of a hole transporting material, the transient PL of an electron transporting material, and the transient PL of a mixed film obtained by mixing these materials are compared, and the formation of an exciplex can be confirmed by observing differences in transient responses such as the transient PL lifetime of the mixed film having a longer lifetime component or a larger ratio of a delayed component than the transient PL lifetimes of the respective materials. Further, the above-mentioned transient PL may be read as transient electroluminescence (EL). That is, the formation of an exciplex can also be confirmed by comparing the transient EL of a hole transporting material, the transient EL of a material having electron transporting properties, and the transient EL of a mixed film of these, and observing differences in transient responses.

[0419] The active layer 373 contains a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors containing organic compounds. In the present embodiment, an example in which an organic semiconductor is used as the semiconductor included in the active layer 373 is shown. By using an organic semiconductor, the light emitting layer 383 and the active layer 373 can be formed by the same method (for example, vacuum evaporation method), and it is preferable because the manufacturing apparatus can be shared.

[0420] Examples of the material of the n-type semiconductor included in the active layer 373 include fullerenes (for example, C 60 、C 70Examples of electron-accepting organic semiconductor materials include fullerene derivatives and other fullerenes. Fullerenes have a soccer ball-like shape, which is energetically stable. Fullerenes have deep (low) HOMO and LUMO levels. Because fullerenes have a deep LUMO level, they have extremely high electron-accepting (acceptor) properties. Normally, when the π-electron conjugation (resonance) spreads on a plane, as in benzene, the electron-donating (donor) properties increase, but fullerenes have a spherical shape, so they have high electron-accepting properties despite the large spread of π-electrons. High electron-accepting properties allow charge separation to occur quickly and efficiently, making them useful as light-receiving elements. C 60 , C 70 Both have a wide absorption band in the visible light region, especially C 70 is C 60 It is preferable because it has a larger π-electron conjugated system and a broad absorption band in the long wavelength region compared to [6,6]-Phenyl-C71-butyric acid methyl ester (abbreviation: PC70BM), [6,6]-Phenyl-C61-butyric acid methyl ester (abbreviation: PC60BM), and 1',1'',4',4''-Tetrahydro-di[1,4]methanonaphthaleno[1,2:2',3',56,60:2'',3''][5,6]fullerene-C60 (abbreviation: ICBA).

[0421] Furthermore, examples of n-type semiconductor materials include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, naphthalene derivatives, anthracene derivatives, coumarin derivatives, rhodamine derivatives, triazine derivatives, and quinone derivatives.

[0422] Examples of the p-type semiconductor materials included in the active layer 373 include electron-donating organic semiconductor materials such as copper(II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), zinc phthalocyanine (ZnPc), tin phthalocyanine (SnPc), and quinacridone.

[0423] In addition, examples of the p-type semiconductor materials include carbazole derivatives, thiophene derivatives, furan derivatives, and compounds having an aromatic amine skeleton. Further, examples of the p-type semiconductor materials include naphthalene derivatives, anthracene derivatives, pyrene derivatives, triphenylene derivatives, fluorene derivatives, pyrrole derivatives, benzofuran derivatives, benzothiophene derivatives, indole derivatives, dibenzofuran derivatives, dibenzothiophene derivatives, indolocarbazole derivatives, porphyrin derivatives, phthalocyanine derivatives, naphthalocyanine derivatives, quinacridone derivatives, polyphenylene vinylene derivatives, polyparaphenylene derivatives, polyfluorene derivatives, polyvinylcarbazole derivatives, and polythiophene derivatives.

[0424] The HOMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the HOMO level of the electron-accepting organic semiconductor material. The LUMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the LUMO level of the electron-accepting organic semiconductor material.

[0425] It is preferable to use spherical fullerenes as the electron-accepting organic semiconductor material and an organic semiconductor material with a shape close to planar as the electron-donating organic semiconductor material. Molecules with similar shapes tend to aggregate easily. When the same type of molecules aggregate, the energy levels of the molecular orbitals are close, so the carrier transport property can be enhanced.

[0426] For example, the active layer 373 is preferably formed by co-evaporating an n-type semiconductor and a p-type semiconductor. Alternatively, the active layer 373 may be formed by laminating an n-type semiconductor and a p-type semiconductor.

[0427] Either a low molecular weight compound or a high molecular weight compound can be used for the light-emitting element and the light-receiving element, and an inorganic compound may be included. The layers constituting the light-emitting element and the light-receiving element can be formed by methods such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, and a coating method, respectively.

[0428] For example, as a hole transporting material, a high molecular weight compound such as poly(3,4-ethylenedioxythiophene) / poly(styrenesulfonic acid) (PEDOT / PSS), and inorganic compounds such as molybdenum oxide and copper iodide (CuI) can be used. Further, as an electron transporting material, an inorganic compound such as zinc oxide (ZnO) can be used.

[0429] In addition, a high molecular weight compound such as Poly[[4,8-bis[5-(2-ethylhexyl)-2-thienyl]benzo[1,2-b:4,5-b’]dithiophene-2,6-diyl]-2,5-thiophenediyl[5,7-bis(2-ethylhexyl)-4,8-dioxo-4H,8H-benzo[1,2-c:4,5-c’]dithiophene-1,3-diyl]]polymer (abbreviation: PBDB-T), which functions as a donor, or a PBDB-T derivative can be used for the active layer 373. For example, a method of dispersing an acceptor material in PBTB-T or a PBDB-T derivative can be used.

[0430] Also, three or more types of materials may be mixed in the active layer 373. For example, for the purpose of expanding the wavelength range, in addition to an n-type semiconductor material and a p-type semiconductor material, a third material may be mixed. At this time, the third material may be a low molecular weight compound or a high molecular weight compound.

[0431] The display device 380B shown in FIG. 26B is different from the display device 380A in that the light receiving element 370PD and the light emitting element 370R have the same configuration.

[0432] The light receiving element 370PD and the light emitting element 370R commonly have the active layer 373 and the light emitting layer 383R.

[0433] Here, it is preferable that the light receiving element 370PD has the same configuration as a light emitting element that emits light with a longer wavelength than the light to be detected. For example, the light receiving element 370PD configured to detect blue light can have the same configuration as one or both of the light emitting element 370R and the light emitting element 370G. For example, the light receiving element 370PD configured to detect green light can have the same configuration as the light emitting element 370R.

[0434] By making the light receiving element 370PD and the light emitting element 370R have the same configuration, the number of film formation steps and the number of masks can be reduced compared to a configuration in which the light receiving element 370PD and the light emitting element 370R have layers that are made separately from each other. Therefore, the manufacturing process and manufacturing cost of the display device can be reduced.

[0435] Also, by making the light receiving element 370PD and the light emitting element 370R have the same configuration, the margin for misalignment can be narrowed compared to a configuration in which the light receiving element 370PD and the light emitting element 370R have layers that are made separately from each other. As a result, the aperture ratio of the pixel can be increased, and the light extraction efficiency of the display device can be increased. Thereby, the lifespan of the light emitting element can be extended. Also, the display device can exhibit high brightness. Also, high definition of the display device is possible.

[0436] The light-emitting layer 383R has a light-emitting material that emits red light. The active layer 373 has an organic compound that absorbs light with a shorter wavelength than red light (for example, one or both of green light and blue light). The active layer 373 preferably has an organic compound that hardly absorbs red light and absorbs light with a shorter wavelength than red light. Thereby, red light is efficiently extracted from the light-emitting element 370R, and the light-receiving element 370PD can detect light with a shorter wavelength than red light with high accuracy.

[0437] In addition, in the display device 380B, an example in which the light-emitting element 370R and the light-receiving element 370PD have the same configuration is shown, but the light-emitting element 370R and the light-receiving element 370PD may each have an optical adjustment layer with a different thickness.

[0438] The display device 380C shown in FIGS. 27A and 27B has a light-emitting and light-receiving element 370SR that emits red (R) light and has a light-receiving function, a light-emitting element 370G, and a light-emitting element 370B. The configurations of the light-emitting element 370G and the light-emitting element 370B can be applied to the display device 380A and the like.

[0439] The light-emitting and light-receiving element 370SR has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, an active layer 373, a light-emitting layer 383R, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 laminated in this order. The light-emitting and light-receiving element 370SR has the same configuration as the light-emitting element 370R and the light-receiving element 370PD illustrated in the display device 380B.

[0440] In FIG. 27A, a case where the light-emitting and light-receiving element 370SR functions as a light-emitting element is shown. In FIG. 27A, an example is shown in which the light-emitting element 370B emits blue light, the light-emitting element 370G emits green light, and the light-emitting and light-receiving element 370SR emits red light.

[0441] In FIG. 27B, a case where the light-emitting and light-receiving element 370SR functions as a light-receiving element is shown. In FIG. 27B, an example is shown in which the light-emitting and light-receiving element 370SR receives blue light emitted by the light-emitting element 370B and green light emitted by the light-emitting element 370G.

[0442] The light-emitting element 370B, the light-emitting element 370G, and the light-receiving and emitting element 370SR each have a pixel electrode 371 and a common electrode 375. In the present embodiment, a case where the pixel electrode 371 functions as an anode and the common electrode 375 functions as a cathode will be described as an example. The light-receiving and emitting element 370SR can detect light incident on the light-receiving and emitting element 370SR, generate charges, and extract them as a current by driving with a reverse bias applied between the pixel electrode 371 and the common electrode 375.

[0443] The light-receiving and emitting element 370SR can be said to have a configuration in which an active layer 373 is added to the light-emitting element. That is, the light-receiving and emitting element 370SR can be formed in parallel with the formation of the light-emitting element only by adding a step of forming the active layer 373 to the manufacturing process of the light-emitting element. Further, the light-emitting element and the light-receiving and emitting element can be formed on the same substrate. Therefore, one or both of the imaging function and the sensing function can be imparted to the display unit without significantly increasing the manufacturing process.

[0444] The stacking order of the light-emitting layer 383R and the active layer 373 is not limited. FIGS. 27A and 27B show an example in which the active layer 373 is provided on the hole transport layer 382 and the light-emitting layer 383R is provided on the active layer 373. The stacking order of the light-emitting layer 383R and the active layer 373 may be interchanged.

[0445] Further, the light-receiving and emitting element may not have at least one of the hole injection layer 381, the hole transport layer 382, the electron transport layer 384, and the electron injection layer 385. Further, the light-receiving and emitting element may have other functional layers such as a hole blocking layer and an electron blocking layer.

[0446] In the light-receiving and emitting element, a conductive film that transmits visible light is used for the electrode on the side where light is extracted. Further, it is preferable to use a conductive film that reflects visible light for the electrode on the side where light is not extracted.

[0447] Since the functions and materials of the respective layers constituting the light-receiving and emitting element are the same as those of the respective layers constituting the light-emitting element and the light-receiving element, detailed description thereof will be omitted.

[0448] FIGS. 27C to 27G show examples of the stacked structure of the light-emitting and light-receiving elements.

[0449] The light-emitting and light-receiving element shown in FIG. 27C has a first electrode 377, a hole injection layer 381, a hole transport layer 382, a light-emitting layer 383R, an active layer 373, an electron transport layer 384, an electron injection layer 385, and a second electrode 378.

[0450] FIG. 27C shows an example in which the light-emitting layer 383R is provided on the hole transport layer 382 and the active layer 373 is stacked on the light-emitting layer 383R.

[0451] As shown in FIGS. 27A to 27C, the active layer 373 and the light-emitting layer 383R may be in contact with each other.

[0452] Further, it is preferable that a buffer layer is provided between the active layer 373 and the light-emitting layer 383R. At this time, the buffer layer preferably has hole transportability and electron transportability. For example, it is preferable to use a bipolar substance for the buffer layer. Alternatively, at least one layer of a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, a hole blocking layer, an electron blocking layer, etc. can be used as the buffer layer. FIG. 27D shows an example in which the hole transport layer 382 is used as the buffer layer.

[0453] By providing a buffer layer between the active layer 373 and the light-emitting layer 383R, it is possible to suppress the transfer of excitation energy from the light-emitting layer 383R to the active layer 373. Also, the optical path length (cavity length) of the microcavity structure can be adjusted using the buffer layer. Therefore, a high luminous efficiency can be obtained from the light-emitting and light-receiving element having a buffer layer between the active layer 373 and the light-emitting layer 383R.

[0454] FIG. 27E shows an example of a laminated structure in which a hole transport layer 382-1, an active layer 373, a hole transport layer 382-2, and an emitting layer 383R are laminated in this order on a hole injection layer 381. The hole transport layer 382-2 functions as a buffer layer. The hole transport layer 382-1 and the hole transport layer 382-2 may contain the same material or different materials. Alternatively, a layer that can be used as the buffer layer described above may be used instead of the hole transport layer 382-2. Alternatively, the positions of the active layer 373 and the emitting layer 383R may be interchanged.

[0455] 27F differs from the light emitting / receiving element shown in Fig. 27A in that it does not have the hole transport layer 382. In this way, the light emitting / receiving element may not have at least one layer among the hole injection layer 381, the hole transport layer 382, the electron transport layer 384, and the electron injection layer 385. The light emitting / receiving element may also have other functional layers such as a hole blocking layer or an electron blocking layer.

[0456] The light emitting / receiving device shown in FIG. 27G differs from the light emitting / receiving device shown in FIG. 27A in that it does not have an active layer 373 and a light emitting layer 383R, but has a layer 389 that serves as both a light emitting layer and an active layer.

[0457] The layer that serves as both the light-emitting layer and the active layer can be, for example, a layer containing three materials: an n-type semiconductor that can be used for the active layer 373, a p-type semiconductor that can be used for the active layer 373, and a light-emitting substance that can be used for the light-emitting layer 383R.

[0458] It is preferable that the lowest energy absorption band in the absorption spectrum of the mixed material of n-type and p-type semiconductors does not overlap with the maximum peak in the emission spectrum (PL spectrum) of the luminescent substance, and it is more preferable that they are sufficiently separated from each other.

[0459] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0460] <Example of cross-sectional view configuration> FIG. 28 is a cross-sectional view showing a configuration example of the display device 10. The display device 10 has a configuration in which a transistor 310 having a channel formed on a substrate 301 and a transistor 320 containing a metal oxide in a semiconductor layer in which a channel is formed are stacked.

[0461] An insulating layer 261 is provided to cover the transistor 310, and a conductive layer 251 is provided on the insulating layer 261. Further, an insulating layer 262 is provided to cover the conductive layer 251, and a conductive layer 252 is provided on the insulating layer 262. The conductive layer 251 and the conductive layer 252 each function as a wiring. Further, an insulating layer 263 and an insulating layer 332 are provided to cover the conductive layer 252, and a transistor 320 is provided on the insulating layer 332. Further, an insulating layer 265 is provided to cover the transistor 320, and a capacitor 240 is provided on the insulating layer 265. The capacitor 240 and the transistor 320 are electrically connected by a plug 274.

[0462] The transistor 320 can be used as a transistor constituting a pixel circuit or a transistor constituting a memory cell. Further, the transistor 310 can be used as a transistor constituting a memory cell, a transistor constituting a drive circuit for driving the pixel circuit, or a transistor constituting an arithmetic circuit. Further, the transistor 310 and the transistor 320 can be used as transistors constituting various circuits such as an arithmetic circuit or a storage circuit.

[0463] The transistor 310 is a transistor having a channel formation region on the substrate 301. As the substrate 301, for example, a semiconductor substrate such as a single crystal silicon substrate can be used. The transistor 310 has a part of the substrate 301, a conductive layer 311, a low resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as one of a source or a drain. The insulating layer 314 is provided to cover the side surface of the conductive layer 311 and functions as an insulating layer.

[0464] Also, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301.

[0465] The transistor 320 is a transistor in which a metal oxide (also referred to as an oxide semiconductor) is applied to a semiconductor layer in which a channel is formed.

[0466] The transistor 320 includes a semiconductor layer 321, an insulating layer 323, a conductive layer 324, a pair of conductive layers 325, an insulating layer 326, and a conductive layer 327.

[0467] The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 301 into the transistor 320 and prevents oxygen from desorbing from the semiconductor layer 321 toward the insulating layer 332 side. As the insulating layer 332, for example, a film such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, in which hydrogen or oxygen diffuses less easily than a silicon oxide film, can be used.

[0468] The conductive layer 327 is provided on the insulating layer 332, and the insulating layer 326 is provided so as to cover the conductive layer 327. The conductive layer 327 functions as a first gate electrode of the transistor 320, and a part of the insulating layer 326 functions as a first gate insulating layer. It is preferable to use an oxide insulating film such as a silicon oxide film for at least a portion of the insulating layer 326 that contacts the semiconductor layer 321. The upper surface of the insulating layer 326 is preferably planarized.

[0469] The semiconductor layer 321 is provided on the insulating layer 326. The semiconductor layer 321 preferably has a metal oxide (also referred to as an oxide semiconductor) film having semiconductor characteristics. For the semiconductor layer 321, it is preferable to use a metal oxide containing at least one of indium, element M (element M is aluminum, gallium, yttrium, or tin), and zinc. An OS transistor using such a metal oxide in the channel formation region has the characteristic that the off-current is very low. Therefore, it is preferable to use an OS transistor as the transistor provided in the pixel circuit because analog data written in the pixel circuit can be held for a long time. Similarly, it is preferable to use an OS transistor as the transistor used in the memory cell because analog data written in the memory cell can be held for a long time.

[0470] A pair of conductive layers 325 are provided in contact with the semiconductor layer 321 and function as a source electrode and a drain electrode.

[0471] An insulating layer 328 is provided to cover the upper surface and side surfaces of the pair of conductive layers 325 and the side surface of the semiconductor layer 321, etc., and an insulating layer 264 is provided on the insulating layer 328. The insulating layer 328 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 264 or the like into the semiconductor layer 321 and prevents oxygen from desorbing from the semiconductor layer 321. As the insulating layer 328, the same insulating film as the above-mentioned insulating layer 332 can be used.

[0472] An opening reaching the semiconductor layer 321 is provided in the insulating layer 328 and the insulating layer 264. Inside the opening, an insulating layer 323 in contact with the upper surface of the semiconductor layer 321, the side surfaces of the insulating layer 264, the insulating layer 328, and the conductive layer 325, and a conductive layer 324 are embedded. The conductive layer 324 functions as a second gate electrode, and the insulating layer 323 functions as a second gate insulating layer.

[0473] The upper surfaces of the conductive layer 324, the insulating layer 323, and the insulating layer 264 are planarized so that their heights are substantially the same, and an insulating layer 329 and an insulating layer 265 are provided to cover them.

[0474] The insulating layers 264 and 265 function as an interlayer insulating layer. The insulating layer 329 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 265 or the like into the transistor 320. As the insulating layer 329, an insulating film similar to the above-described insulating layer 328 and insulating layer 332 can be used.

[0475] The plug 274 that is electrically connected to one of the pair of conductive layers 325 is provided so as to be embedded in the insulating layer 265, the insulating layer 329, and the insulating layer 264.

[0476] The capacitor 240 has a conductive layer 241, a conductive layer 245, and an insulating layer 243 positioned therebetween. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 245 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as a dielectric of the capacitor 240.

[0477] The conductive layer 241 is provided on the insulating layer 261 and is embedded in the insulating layer 254. The conductive layer 241 is electrically connected to one of the source or drain of the transistor 310 by a plug 271 embedded in the insulating layer 261. The insulating layer 243 is provided so as to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping the conductive layer 241 via the insulating layer 243.

[0478] An insulating layer 255 is provided so as to cover the capacitor 240, and a light-emitting element 61, a light-receiving element 62, and the like are provided on the insulating layer 255. A protective layer 91 is provided on the light-emitting element 61 and the light-receiving element 62, and a substrate 420 is bonded to the upper surface of the protective layer 91 by a resin layer 419. As the substrate 420, a substrate having translucency can be used.

[0479] The pixel electrode 84 of the light-emitting element 61 and the pixel electrode 84PD of the light-receiving element 62 are electrically connected to one of the source or drain of the transistor 310 by a plug 256 embedded in the insulating layer 255, a conductive layer 241 embedded in the insulating layer 254, and a plug 271 embedded in the insulating layer 261.

[0480] By using this configuration, it is possible to arrange the OS transistors that make up the pixel circuits and cells directly below the light-receiving elements and light-emitting elements, and it is also possible to arrange driving circuits, arithmetic circuits, etc., making it possible to miniaturize a display device with high performance.

[0481] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0482] (Embodiment 5) In one embodiment of the present invention, an electronic device to which the display device of one embodiment of the present invention can be applied is described. The electronic device according to one embodiment of the present invention can also be suitably used as a wearable electronic device for VR and AR applications.

[0483] Fig. 29A is a perspective view of a goggle-type electronic device 100, which is an example of a wearable electronic device. The electronic device 100 shown in Fig. 29A illustrates a state in which a pair of display devices 10_L and 10_R are provided in a housing 101. The housing 101 is equipped with an acceleration sensor such as a gyro sensor, which can detect the orientation of the user's head and display an image according to that orientation.

[0484] In this specification and the like, when describing matters common to the display devices 10_L and 10_R, or when there is no need to distinguish between them, the display device 10 may simply be referred to as "display device 10." The display device 10 described in the above embodiment is applicable to the display devices 10_L and 10_R illustrated in FIG. 29A.

[0485] As described in the above Embodiment 4, the display device 10 according to one aspect of the present invention can have a structure in which a light-emitting element, a pixel circuit, and a driving circuit are stacked. Therefore, the aperture ratio (effective display area ratio) of the pixel can be made extremely high. Also, the pixel circuits can be arranged at an extremely high density, and the fineness of the pixels can be made extremely high. Since such a display device 10 is extremely high-definition, it can be suitably used for VR devices such as head-mounted displays or glasses-type AR devices. For example, even in the case of a configuration in which the display unit of the display device 10 is viewed through an optical member such as a lens, since the display device 10 has an extremely high-definition display unit, pixels cannot be viewed even when the display unit is magnified by the lens, and a display with a high sense of immersion can be performed.

[0486] As described in the above Embodiment 4, the display device 10 according to one aspect of the present invention can have a structure in which a light-receiving element, a cell array, and an arithmetic circuit are stacked. Therefore, arithmetic processing with excellent arithmetic efficiency can be executed using the minute current output from the light-receiving element as input data. Also, in the display device 10, since a light-receiving unit can be arranged at a position close to the display unit, an image can be viewed with the user's eyes, and imaging of the user's eyes and / or the periphery thereof can be performed. Therefore, a configuration can be adopted in which inference processing based on a neural network using imaging data as input data is performed. Also, in the cells of the cell array, analog data written according to the minute current can be held for a long time. Also, in the arithmetic circuit that performs sum-of-products arithmetic processing using the minute current, arithmetic with excellent arithmetic efficiency can be performed.

[0487] FIG. 29B is a perspective view showing the back surface, bottom surface, and right side surface of the electronic device 100 described in FIG. 29A.

[0488] In FIG. 29B, the housing 101 of the electronic device 100 includes, as an example, a mounting portion 106, a buffer member 107, a pair of lenses 108, etc., in addition to the pair of display devices 10_L and 10_R. The display units 13 in the pair of display devices 10_L and 10_R are respectively provided at positions where they can be viewed through the lenses 108 inside the housing 101.

[0489] In addition, the light receiving units 14 in the pair of display devices 10_L and 10_R are respectively provided at positions where information on the user's eyes and the surroundings thereof can be acquired. Note that the acquisition of information on the user's eyes and the surroundings thereof by the light receiving unit 14 may be performed via the lens 108 inside the housing 101, or may be performed without passing through the lens 108.

[0490] In addition, the housing 101 shown in FIG. 29B is provided with an input terminal 109 and an output terminal 110. An image signal (image data) from a video output device or the like, or a cable for supplying power or the like for charging a battery provided inside the housing 101 can be connected to the input terminal 109. As the output terminal 110, for example, it functions as an audio output terminal, and earphones, headphones, etc. can be connected thereto.

[0491] In addition, the housing 101 preferably has a mechanism capable of adjusting the left and right positions of the lens 108 and the display devices 10_L and 10_R so that they are in optimal positions according to the position of the user's eyes. Further, it preferably has a mechanism for adjusting focus by changing the distance between the lens 108 and the display devices 10_L and 10_R.

[0492] The buffer member 107 is a portion that contacts the user's face (forehead, cheeks, etc.). When the buffer member 107 is in close contact with the user's face, light leakage can be prevented and the sense of immersion can be enhanced. As the buffer member 107, it is preferable to use a soft material so that it is in close contact with the user's face when the user wears the electronic device 100. Using such a material is preferable because in addition to a good touch feeling, it does not make the user feel cold when worn in cold seasons. Members such as the buffer member 107 or the mounting portion 106 that come into contact with the user's skin are preferably configured to be removable, as this facilitates cleaning or replacement.

[0493] An electronic device according to one aspect of the present invention may further include earphone 106A. Earphone 106A has a communication unit (not shown) and has a wireless communication function. Earphone 106A can output audio data by means of the wireless communication function. Note that earphone 106A may have a vibration mechanism in order to function as a bone conduction earphone. Earphone 106A can also be directly connected or wired to attachment part 106.

[0494] Also, FIG. 30A is a perspective view of glasses-type electronic device 100A shown as another example of a wearable electronic device. Electronic device 100A shown in FIG. 30A illustrates a state in which a pair of display devices 10_L and 10_R are provided within housing 101.

[0495] Electronic device 100A can project the images displayed on display units 13 of display devices 10_L and 10_R onto display area 104 of optical member 103. Also, since optical member 103 has translucency, the user can view the images displayed in display area 104 superimposed on the transmitted images viewed through optical member 103. Therefore, electronic device 100A is an electronic device capable of AR display.

[0496] Also, although not shown, housing 101 is provided with a wireless receiver or a connector to which a cable can be connected, and video signals and the like can be supplied to housing 101. Further, by providing housing 101 with an acceleration sensor such as a gyro sensor, the orientation of the user's head can be detected, and an image corresponding to the orientation can be displayed in display area 104.

[0497] Subsequently, with reference to FIG. 30B, a method for projecting an image onto display area 104 of electronic device 100A will be described. Inside housing 101, display device 10, lens 111, and reflector 112 are provided. Also, a reflecting surface 113 that functions as a half mirror is provided at a portion corresponding to display area 104 of optical member 103.

[0498] The light 115 emitted from the display device 10 passes through the lens 111 and is reflected by the reflector 112 toward the optical member 103. Inside the optical member 103, the light 115 repeatedly undergoes total internal reflection at the end face of the optical member 103 and reaches the reflection surface 113, where an image is projected onto the reflection surface 113. As a result, the user can visually recognize both the light 115 reflected by the reflection surface 113 and the transmitted light 116 that has passed through the optical member 103 (including the reflection surface 113).

[0499] FIG. 30B shows an example in which the reflector 112 and the reflection surface 113 each have a curved surface. This can increase the degree of freedom in optical design and reduce the thickness of the optical member 103 compared to the case where they are flat surfaces. Note that the reflector 112 and the reflection surface 113 may be flat surfaces.

[0500] As the reflector 112, a member having a mirror surface can be used, and it is preferably highly reflective. As the reflection surface 113, a half mirror using the reflection of a metal film may be used, but using a prism or the like that utilizes total internal reflection can increase the transmittance of the transmitted light 116.

[0501] Here, the housing 101 preferably has a mechanism for adjusting the distance between the lens 111 and the display device 10 or their angles. This enables focusing adjustment, image enlargement, reduction, etc. For example, one or both of the lens 111 or the display device 10 may be configured to be movable in the optical axis direction.

[0502] Also, the housing 101 preferably has a mechanism for adjusting the angle of the reflector 112. By changing the angle of the reflector 112, it is possible to change the position of the display area 104 where the image is displayed. This makes it possible to arrange the display area 104 at an optimal position according to the position of the user's eyes.

[0503] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc. can be appropriately combined with at least a part of other configuration examples, or drawings, etc.

[0504] <Supplementary Note Regarding the Descriptions in this Specification, etc.> Regarding the above embodiments and the descriptions of each configuration in the embodiments, the following supplementary notes are provided.

[0505] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form an aspect of the present invention. Also, when multiple configuration examples are shown within one embodiment, it is possible to appropriately combine the configuration examples.

[0506] Note that the content described in one embodiment (even a part of the content) can be applied, combined, or replaced with respect to the content described in another part of the same embodiment (even a part of the content), and / or the content described in one or more other embodiments (even a part of the content).

[0507] Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the text described in the specification.

[0508] Note that the figure (even a part of it) described in one embodiment can be combined with another part of the figure, another figure (even a part of it) described in the same embodiment, and / or the figure (even a part of it) described in one or more other embodiments to form more figures.

[0509] Also, in this specification, etc., in the block diagram, the components are classified by function and shown as independent blocks. However, in an actual circuit, etc., it is difficult to separate the components by function, and there may be cases where a single circuit is related to multiple functions or a single function is related to multiple circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification and can be appropriately rephrased according to the situation.

[0510] In the drawings, the size, layer thickness, or area are shown in arbitrary sizes for convenience of explanation. Therefore, they are not necessarily limited to that scale. The drawings are schematically shown for clarity and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0511] In this specification and the like, when explaining the connection relationship of transistors, the notations "one of the source or drain" (or the first electrode, or the first terminal), "the other of the source or drain" (or the second electrode, or the second terminal) are used. This is because the source and drain of a transistor change depending on the structure or operating conditions of the transistor. Regarding the naming of the source and drain of a transistor, it can be appropriately rephrased according to the situation, such as the source (drain) terminal or the source (drain) electrode.

[0512] Also, in this specification and the like, terms such as "electrode" or "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, terms such as "electrode" or "wiring" also include cases where a plurality of "electrodes" or "wirings" are integrally formed.

[0513] Also, in this specification and the like, voltage and potential can be appropriately rephrased. Voltage is the potential difference from a reference potential. For example, if the reference potential is the ground voltage (earthing voltage), the voltage can be rephrased as potential. The ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, the potential applied to a wiring or the like may be changed.

[0514] In this specification and the like, terms such as "film" and "layer" can be interchanged with each other in some cases or according to the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer".

[0515] In this specification and the like, a switch refers to something that can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether current flows or not. Or, a switch refers to something that has a function of selecting and switching the path through which current flows.

[0516] In this specification and the like, the channel length refers to, for example, in the top view of a transistor, the distance between the source and the drain in the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate overlap, or in the region where the channel is formed.

[0517] In this specification and the like, the channel width refers to, for example, the length of the portion where the source and the drain face each other in the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or in the region where the channel is formed.

[0518] In this specification and the like, "A and B are connected" shall include not only the case where A and B are directly connected but also the case where they are electrically connected. Here, "A and B are electrically connected" means that when there is an object having some electrical action between A and B, it enables the exchange of electrical signals between A and B.

[0519] In this specification and the like, a device manufactured using a metal mask or an FMM (fine metal mask, high-definition metal mask) may be referred to as a device having an MM (metal mask) structure. Also, in this specification and the like, a device manufactured without using a metal mask or an FMM may be referred to as a device having an MML (metal maskless) structure.

[0520] In this specification and the like, a structure in which light-emitting elements of different colors (here, blue (B), green (G), and red (R)) form separate light-emitting layers or are separately coated may be referred to as an SBS (Side By Side) structure. Also, in this specification and the like, a light-emitting element capable of emitting white light may be referred to as a white light-emitting element. Note that a white light-emitting element can be made into a light-emitting element for full-color display by combining it with a coloring layer (for example, a color filter).

[0521] Also, light-emitting elements can be broadly classified into a single structure and a tandem structure. An element with a single structure has one light-emitting unit between a pair of electrodes, and it is preferable that the light-emitting unit includes one or more light-emitting layers. To obtain white light emission, light-emitting layers can be selected such that the light emission of each of two or more light-emitting layers is in a complementary color relationship. For example, by making the light emission color of the first light-emitting layer and the light emission color of the second light-emitting layer be in a complementary color relationship, a configuration in which the entire light-emitting element emits white light can be obtained. The same applies to the case of a light-emitting element having three or more light-emitting layers.

[0522] An element with a tandem structure has two or more light-emitting units between a pair of electrodes, and it is preferable that each light-emitting unit includes one or more light-emitting layers. To obtain white light emission, a configuration can be adopted such that the light from the light-emitting layers of the plurality of light-emitting units is combined to obtain white light emission. Note that the configuration for obtaining white light emission is the same as that of the single structure. In the case of an element with a tandem structure, it is preferable to provide an intermediate layer such as a charge generation layer between the plurality of light-emitting units.

[0523] Further, when comparing the above-mentioned white light-emitting element (single structure or tandem structure) with the light-emitting element having an SBS structure, the light-emitting element having an SBS structure can achieve lower power consumption than the white light-emitting element. When it is desired to keep the power consumption low, it is preferable to use the light-emitting element having an SBS structure. On the other hand, the white light-emitting element is preferable because its manufacturing process is simpler than that of the light-emitting element having an SBS structure, so that the manufacturing cost can be reduced or the manufacturing yield can be increased.

Explanation of Signs

[0524] CA: Cell array, IM: Cell, ITRZ: Circuit, MAC: Semiconductor device, WCS: Circuit, WSD: Circuit, XCLK: Clock signal, XCS: Circuit, XDATA: Input data, XLAT: Latch signal, XSP: Start pulse, YCLK: Clock signal, YDATA: Output data, YLAT: Latch signal, YSP: Start pulse

Claims

1. A semiconductor device, a drive circuit, a pixel circuit, a light-emitting element, and a light-receiving element, wherein the semiconductor device includes a cell array that performs a multiplication-accumulation operation of a first layer and a multiplication-accumulation operation of a second layer in an artificial neural network, a first circuit that inputs first data to the cell array, and a second circuit that outputs second data from the cell array, the cell array includes a plurality of cells, the cell array includes a first region and a second region, in a first period, in the first region, the t-th (t is a natural number of 2 or more) first data is input from the first circuit, and the t-th second data corresponding to the multiplication-accumulation operation of the first layer is output to the second circuit, and in the second region, the (t−1)-th first data is input from the first circuit, and the (t−1)-th second data corresponding to the multiplication-accumulation operation of the second layer is output to the second circuit, the pixel circuit has a function of controlling the light emission of the light-emitting element, the drive circuit has a function of controlling the pixel circuit, the semiconductor device includes transistors included in a layer where the pixel circuit is provided and transistors included in a layer where the drive circuit is provided, the semiconductor device has a function of performing arithmetic processing using the current output from the light-receiving element as the first data, an electronic device.

2. A semiconductor device, a drive circuit, a pixel circuit, a light-emitting element, and a light-receiving element, wherein the semiconductor device includes a cell array that performs a multiplication-accumulation operation of a first layer and a multiplication-accumulation operation of a second layer in an artificial neural network, a first circuit that inputs first data to the cell array, and a second circuit that outputs second data from the cell array, the cell array includes a plurality of cells, the cell array includes a first region and a second region, in a first period, in the first region, the t-th (t is a natural number of 2 or more) first data is input from the first circuit, and the t-th second data corresponding to the multiplication-accumulation operation of the first layer is output to the second circuit, and in the second region, the (t−1)-th first data is input from the first circuit, and the (t−1)-th second data corresponding to the multiplication-accumulation operation of the second layer is output to the second circuit, In the second period, the first region outputs the (t + 1)-th second data corresponding to the sum-of-products operation of the first layer to the second circuit when the (t + 1)-th first data is input from the first circuit, and the second region outputs the t-th second data corresponding to the sum-of-products operation of the second layer to the second circuit when the t-th first data is input from the first circuit. The pixel circuit has a function of controlling the light emission of the light-emitting element. The driving circuit has a function of controlling the pixel circuit. The semiconductor device has a transistor included in the layer provided with the pixel circuit and a transistor included in the layer provided with the driving circuit. The semiconductor device has a function of performing arithmetic processing using the current output from the light-receiving element as the first data. An electronic device.

3. In Claim 1 or Claim 2, the first data input to the second region is data obtained by non-linearly operating the second data output from the first region. An electronic device.

4. In any one of Claims 1 to 3, it has a third circuit that outputs the second data from the cell array, and the third circuit has a function of performing an operation based on a non-linear function on the second data. An electronic device.

5. In any one of Claims 1 to 4, the cell has a first transistor, a second transistor, and a capacitor, the first transistor has a function of holding a first potential corresponding to weight data applied to the gate of the second transistor via the first transistor when in an off state, the capacitor has a function of changing the first potential held at the gate of the second transistor to a second potential in response to a change in potential corresponding to the first data applied to one electrode, and the second transistor has a function of outputting the second data corresponding to the first data as an analog current to the other of the source or drain. An electronic device.

6. In Claim 5, the analog current is a current that flows when the second transistor operates in the subthreshold region. An electronic device.

7. In Claim 5 or Claim 6, the first transistor has a semiconductor layer having a metal oxide in a channel formation region. An electronic device.

8. In Claim 7, the metal oxide contains In, Ga, and Zn. An electronic device.

9. In any one of Claims 5 to 8, the second transistor has a semiconductor layer having silicon in a channel formation region, an electronic device.

10. In Claim 9, the light receiving element has an organic photodiode, the light emitting element is an organic EL element, an electronic device.

11. In Claim 10, the separation of the light emitting element and the light receiving element is performed by a photolithography method, an electronic device.

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