Solid-state imaging device and imaging apparatus

Abstract

A solid-state imaging element provided with a comparator for each column, wherein the responsiveness of the comparator is improved.　An input transistor outputs, from a drain, a potential in a range from one to the other of a pair of output potentials on the basis of whether an input potential inputted to a source and a prescribed reference potential inputted to a gate approximately match each other. A first current source supplies a uniform current. A capacitance is inserted between the source of the input transistor and the first current source. A cutoff switch cuts off the drain of the input transistor from a connection node for the capacitance and the first current source within a prescribed period for initializing the connection node to the lower of the pair of output potentials, and connects the connection node and the drain of the input transistor outside of the prescribed period.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging device. More specifically, it relates to a solid-state imaging device provided with a comparator and a counter, and an imaging apparatus.

Background Art

[0002] Conventionally, in solid-state imaging devices and the like, since the structure is simple, a single-slope type ADC (Analog to Digital Converter) is often used for AD (Analog to Digital) conversion. This single-slope type ADC generally consists of a comparator and a counter that performs counting based on the comparison result of the comparator. In this comparator, for example, a solid-state imaging device in which a pMOS (p-channel Metal-Oxide-Semiconductor) transistor, a current source, and a logic gate (such as an inverter) are arranged has been proposed (see, for example, Patent Document 1). This pMOS transistor compares the pixel signal from the pixel circuit with a reference signal and outputs the comparison result from the drain via an inverter. This comparison result is initialized to a low level by the input of a high-level reference voltage immediately before the start of counting by the counter.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the above solid-state imaging device, the comparator shares the current of the pixel circuit, thereby reducing power consumption compared to a configuration in which a current source is also provided for the comparator separately from the pixel circuit. However, in the above solid-state imaging device, it is difficult to increase the speed at which the output transitions from a high level to a low level during initialization (in other words, to improve the responsiveness of the comparator). If the value of the reference voltage is made sufficiently high to improve the responsiveness, although the leakage current of the pMOS transistor in the off state decreases, the power consumption increases.

[0005] The present technology has been created in view of such a situation, and an object thereof is to improve the responsiveness of a comparator in a solid-state imaging device provided with a comparator for each column.

Means for Solving the Problem

[0006] The present technology has been made to solve the above problems, and a first aspect thereof is an input transistor that outputs a potential within a range from one of a pair of output potentials to the other based on whether an input potential input to the source substantially matches a predetermined reference potential input to the gate, a first current source that supplies a constant current, a capacitor inserted between the source of the input transistor and the first current source, and a first cutoff switch that disconnects the drain of the input transistor from the connection node during a predetermined period for initializing the connection node of the capacitor and the first current source to the lower one of the pair of output potentials and connects the connection node and the drain of the input transistor outside the predetermined period. This brings about an effect of improving the responsiveness.

[0007] Also, in this first aspect, the first cutoff switch may include an N-type transistor and a P-type transistor connected in parallel between the drain of the input transistor and the first current source. This enables the comparison operation to be performed without being affected by the cutoff switch.

[0008] Also, in this first aspect, the first cutoff switch may include an N-type transistor. This brings about the effect of reducing the number of transistors.

[0009] Also, in this first aspect, a first output transistor that outputs a potential within a range from a predetermined potential lower than the input potential to the input potential based on whether a difference between the input potential input to the source and the potential of the connection node input to the gate exceeds a predetermined threshold voltage, and an output-side short-circuit switch that short-circuits the source and the drain of the first output transistor within the predetermined period may be further provided. This brings about the effect of improving responsiveness.

[0010] Also, in this first aspect, an auto-zero transistor that connects the gate and the drain of the input transistor within an auto-zero period before the predetermined period may be further provided, and the output-side short-circuit switch may short-circuit the source and the drain of the first output transistor within the auto-zero period and within the predetermined period. This brings about the effect of suppressing oscillation during the auto-zero period.

[0011] Also, in this first aspect, the output-side short-circuit switch may include an N-type transistor and a P-type transistor connected in parallel between the source and the drain of the first output transistor. This brings about the effect that the source and the drain of the first output transistor are short-circuited when the level of the comparison result is around the middle of the power supply potential.

[0012] Also, in this first aspect, the output-side short-circuit switch may include an N-type transistor. This brings about the effect of reducing the number of transistors.

[0013] Also, in this first aspect, the output-side short-circuit switch may include a P-type transistor. This brings about the effect of reducing the number of transistors.

[0014] Also, in this first aspect, a second output transistor may be further provided that outputs a voltage within the range from the predetermined potential to the input potential based on whether or not the difference between the input potential input to the source and the drain of the first output transistor input to the gate exceeds a predetermined threshold voltage. As a result, since the gain of the comparator increases, the linearity improves.

[0015] Also, in this first aspect, an input-side short-circuit switch that short-circuits the drain and source of the input transistor within the predetermined period may be further provided. This brings about the effect of suppressing characteristic degradation.

[0016] Also, in this first aspect, a level shift circuit that outputs an output signal of a pair of shift potentials having a larger potential difference than the predetermined potential and the input potential based on the potential of the drain of the first output transistor, and a logic gate that determines whether the output signal is higher than a predetermined threshold between the pair of shift potentials and outputs a determination result may be further provided. This brings about the effect of improving the design freedom.

[0017] Also, in this first aspect, one of the pair of shift potentials is a power supply potential higher than the input potential, and the other is a reference potential lower than the predetermined potential. The level shift circuit includes an N-type transistor whose gate is connected to the vertical signal line of the input potential and whose source is connected to the drain of the first output transistor, a power supply-side precharge transistor that initializes the potential of the drain of the N-type transistor to the power supply potential, a P-type transistor whose gate is connected to the drain of the N-type transistor and whose drain is connected to the logic gate, and a reference-side precharge transistor that initializes the potential of the drain of the P-type transistor to the reference potential. This brings about the effect of expanding the voltage circuit by four transistors.

[0018] Also, in this first aspect, a first output transistor that outputs a potential within a range from a predetermined potential lower than the input potential to the input potential based on whether a difference between the input potential input to the source and the potential of the connection node input to the gate exceeds a predetermined threshold voltage; a second current source that supplies a constant current; a second cutoff switch that disconnects the drain of the first output transistor from the second current source before the start timing of setting the reference potential and connects the drain of the first output transistor and the second current source for a certain period from the start timing; a clamp transistor having its drain connected to the second current source; and a control switch that connects the source of the first output transistor and the source of the clamp transistor before the start timing and disconnects the source of the first output transistor from the source of the clamp transistor for a certain period from the start timing may be further provided. Thereby, an effect of suppressing kickback is brought about.

[0019] Also, in this first aspect, a level shift circuit that outputs output signals of a pair of shift potentials having a larger potential difference than the predetermined potential and the input potential based on the potential of the connection node of the control switch and the clamp transistor may be further provided. Thereby, an effect of improving the design freedom is brought about.

[0020] Also, in this first aspect, an input capacitance switching circuit that switches the number of input capacitances connected in parallel to the gate of the input transistor may be further provided. Thereby, an effect of reducing noise is brought about.

[0021] Further, a second aspect of the present technology is an input transistor that outputs a drain potential corresponding to the input potential from the drain when the input potential input to the source and a predetermined reference potential input to the gate are substantially the same, and a first output transistor that outputs a potential within a range from the predetermined potential to the input potential from the drain based on whether a difference between the input potential input to the source and the drain potential input to the gate exceeds a predetermined threshold voltage, and an output-side short-circuit switch that shorts the source and drain of the first output transistor within a predetermined period for initializing the drain of the first output transistor to the input potential. This brings about an effect of improving responsiveness.

[0022] Further, a third aspect of the present technology is an input transistor that outputs a predetermined clamp potential from the drain when the input potential input to the source and a predetermined reference potential input to the gate are substantially the same, and an input-side short-circuit switch that shorts the source and drain of the input transistor within a predetermined period for initializing the potential of the drain to a high level higher than the clamp potential. This brings about an effect of improving responsiveness.

[0023] Further, a fourth aspect of the present technology is an input transistor that outputs a potential within a range from one of a pair of output potentials to the other from the drain based on whether the input potential input to the source and a predetermined reference potential input to the gate are substantially the same, a current source that supplies a predetermined constant current, a capacitor inserted between the source of the input transistor and the current source, a cutoff switch that disconnects the drain of the input transistor from the connection node during a predetermined period for initializing the connection node of the capacitor and the current source to the lower of the pair of output potentials and connects the connection node and the drain of the input transistor outside the predetermined period, and a counter that counts a count value over a period until the potential of the connection node is inverted. This brings about an effect of improving responsiveness.

[0024] Also, a fifth aspect of the present technology is a solid-state imaging device including a transistor having a vertical signal line connected to a pixel, a source connected to the vertical signal line, and a gate receiving a signal based on a predetermined reference potential, a current source supplying a constant current, a capacitor inserted between the source of the transistor and the current source, and a switch connected to a connection node of the capacitor and the current source and a drain of the transistor.

[0025] Also, a sixth aspect of the present technology is a solid-state imaging device including a first transistor having a vertical signal line connected to a pixel, a source connected to the vertical signal line, and a gate receiving a signal based on a predetermined reference potential, a current source supplying a constant current, a second transistor having a source connected to the vertical signal line and a gate connected to the current source, and a switch connected to a source and a drain of the second transistor.

Brief Description of the Drawings

[0026]

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Embodiments for Carrying Out the Invention

[0027] Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First Embodiment (Example of accelerating the response speed by a cutoff switch) 2. Second Embodiment (Example of accelerating the response speed by a short-circuit switch) 3. Third Embodiment (Example of accelerating the response speed by a cutoff switch and an output-side short-circuit switch) 4. Fourth Embodiment (Example of adding a third-stage transistor and accelerating the response speed by a cutoff switch and an output-side short-circuit switch) 5. Fifth Embodiment (Example of adding an input-side short-circuit switch and accelerating the response speed by a cutoff switch and an output-side short-circuit switch) 6. Sixth Embodiment (Example of Providing a Level Shift Circuit and Accelerating Response Speed with a Cutoff Switch and an Output-Side Short-Circuit Switch) 7. Seventh Embodiment (Example of Corresponding to Lamp Signals of Different Waveforms and Accelerating Response Speed with a Short-Circuit Switch) 8. Eighth Embodiment (Example of Suppressing Kickback with a Cutoff Switch, a Clamp Transistor, and a Control Switch) 9. Application Example to a Moving Body

[0028] <1. First Embodiment> [Configuration Example of Imaging Device] FIG. 1 is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment of the present technology. This imaging device 100 is a device for imaging image data, and includes an optical unit 110, a solid-state imaging device 200, and a DSP (Digital Signal Processing) circuit 120. Further, the imaging device 100 includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. As the imaging device 100, a camera mounted on a smartphone, an in-vehicle camera, etc. are assumed.

[0029] The optical unit 110 collects light from a subject and guides it to the solid-state imaging device 200. The solid-state imaging device 200 generates image data by photoelectric conversion. This solid-state imaging device 200 supplies the generated image data to the DSP circuit 120 via a signal line 209.

[0030] The DSP circuit 120 executes predetermined signal processing on the image data. This DSP circuit 120 outputs the processed image data to the frame memory 160 etc. via the bus 150.

[0031] The display unit 130 displays image data. As the display unit 130, for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed. The operation unit 140 generates an operation signal according to a user's operation.

[0032] The bus 150 is a common path for the optical unit 110, the solid-state imaging device 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 to exchange data with each other.

[0033] The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the solid-state imaging device 200, the DSP circuit 120, the display unit 130, and the like.

[0034] FIG. 2 is a diagram showing an example of the stacked structure of the solid-state imaging device 200 in the first embodiment of the present technology. This solid-state imaging device 200 includes a circuit chip 202 and a light-receiving chip 201 stacked on the circuit chip 202. These chips are electrically connected via connection parts such as vias. In addition to vias, they can also be connected by Cu-Cu bonding or bumps.

[0035] [Configuration Example of Solid-State Imaging Device] FIG. 3 is a block diagram showing a configuration example of the solid-state imaging device 200 in the first embodiment of the present technology. This solid-state imaging device 200 includes a vertical scanning circuit 210, a timing control unit 220, a DAC (Digital to Analog Converter) 230, a pixel array unit 240, a column signal processing unit 260, and a horizontal scanning circuit 270. A plurality of pixel circuits 250 are arranged in a two-dimensional lattice in the pixel array unit 240.

[0036] The pixel array unit 240 is arranged, for example, on the light-receiving chip 201, and the remaining circuits are arranged on the circuit chip 202. Note that the circuits arranged on each chip are not limited to those illustrated in the figure.

[0037] The vertical scanning circuit 210 sequentially selects and drives rows in the pixel array unit 240.

[0038] The timing control unit 220 controls the operation timings of the vertical scanning circuit 210, the DAC 230, the column signal processing unit 260, and the horizontal scanning circuit 270 in synchronization with the vertical synchronization signal VSYNC.

[0039] The DAC 230 generates a sawtooth-shaped ramp signal and supplies it to the column signal processing unit 260 as a reference signal.

[0040] The pixel circuit 250 generates an analog pixel signal by photoelectric conversion according to the control of the vertical scanning circuit 210. The pixel circuits 250 in each column output pixel signals to the column signal processing unit 260 via vertical signal lines (not shown).

[0041] An ADC (not shown) is arranged in the column signal processing unit 260 for each column of the pixel circuits 250. Each of the ADCs converts the pixel signal of the corresponding column into a digital signal and outputs it to the DSP circuit 120 according to the control of the horizontal scanning circuit 270.

[0042] The horizontal scanning circuit 270 controls the column signal processing unit 260 to sequentially output digital signals.

[0043] [Configuration Example of Pixel Circuit] FIG. 4 is a circuit diagram showing a configuration example of the pixel circuit 250 in the first embodiment of the present technology. This pixel circuit 250 includes a photoelectric conversion element 251, a transfer transistor 252, a reset transistor 253, a floating diffusion layer 254, an amplification transistor 255, and a selection transistor 256. Also, in the pixel array unit 240, vertical signal lines 259 are wired for each column along the vertical direction.

[0044] The photoelectric conversion element 251 photoelectrically converts incident light to generate charges. The transfer transistor 252 transfers charges from the photoelectric conversion element 251 to the floating diffusion layer 254 according to the drive signal TRG from the vertical scanning circuit 210.

[0045] The reset transistor 253 extracts charges from the floating diffusion layer 254 and initializes them according to the drive signal RST from the vertical scanning circuit 210.

[0046] The floating diffusion layer 254 accumulates charges and generates a voltage according to the amount of charge. The amplification transistor 255 amplifies the voltage of the floating diffusion layer 254.

[0047] The selection transistor 256 outputs the amplified voltage signal as a pixel signal to the column signal processing unit 260 via the vertical signal line 259 according to the drive signal SEL from the vertical scanning circuit 210.

[0048] [Configuration example of column signal processing unit] FIG. 5 is a block diagram showing a configuration example of the column signal processing unit 260 in the first embodiment of the present technology. In this column signal processing unit 260, a comparator 300, a counter 261, and a latch 262 are arranged for each column. When the number of columns is N (N is an integer), N comparators 300, N counters 261, and N latches 262 are arranged.

[0049] The comparator 300 compares the reference signal from the DAC 230 with the pixel signal from the corresponding column. Hereinafter, the potential of the reference signal is referred to as the reference potential V RMP and the potential of the vertical signal line 259 that transmits the pixel signal is hereinafter referred to as the input potential V VSL . This comparator 300 supplies an output signal VCO indicating the comparison result to the counter 261 of the corresponding column.

[0050] Also, the level of the pixel signal when the pixel circuit 250 is initialized (that is, the input potential V VSL ) is hereinafter referred to as the "reset level", and the level of the pixel signal when charges are transferred to the floating diffusion layer 254 is hereinafter referred to as the "signal level".

[0051] Counter 261 counts the count value over the period until the output signal VCO is inverted. This counter 261, for example, counts down over the period until the output signal VCO corresponding to the reset level is inverted, and counts up over the period until the output signal VCO corresponding to the signal level is inverted. Thereby, correlated double sampling (CDS) processing for obtaining the difference between the reset level and the signal level is realized.

[0052] Then, counter 261 causes latch 262 to hold the digital signal indicating the count value. The comparator 300 and the counter 261 realize analog-to-digital (AD) conversion processing for converting an analog pixel signal into a digital signal. That is, the comparator 300 and the counter 261 function as an ADC. An ADC using a comparator and a counter in this way is generally called a single-slope type ADC.

[0053] Although the CDS processing is realized by up-counting and down-counting, the configuration is not limited to this. The counter 261 may perform only either up-counting or down-counting, and a configuration may be adopted in which a subsequent-stage circuit executes the CDS processing for obtaining the difference.

[0054] Latch 262 holds a digital signal. This latch 262 outputs the held digital signal in accordance with the control of the horizontal scanning circuit 270.

[0055] [Configuration Example of Comparator] FIG. 6 is a circuit diagram showing a configuration example of the comparator 300 in the first embodiment of the present technology. This comparator 300 includes an input capacitor 311, an input transistor 312, an auto-zero transistor 313, a cutoff switch 330, a current source 314, a band-limiting capacitor 315, and a clamp transistor 316. Further, the comparator 300 includes an output transistor 317, a current source 318, a clamp transistor 319, and inverters 340 and 350.

[0056] The input capacitance 311 is inserted between the DAC 230 and the gate of the input transistor 312 .

[0057] The source of the input transistor 312 is connected to the vertical signal line 259, and the source of the input transistor 312 is supplied with an input potential V VSL The gate of the input transistor 312 is connected to a reference potential V RMP The input transistor 312 receives the input potential V VSL and the reference potential V RMP When the input voltage V VSL and the reference potential V RMP The drain outputs a drain voltage corresponding to the voltage. Here, "substantially the same" means that the potentials of the compared transistors are completely the same, or that the difference is within a predetermined tolerance. This tolerance is set to the threshold voltage Vt of the input transistor 312. For example, a pMOS (p-channel Metal-Oxide-Semiconductor) transistor is used as this input transistor 312.

[0058] The auto-zero transistor 313 shorts the gate and drain of the input transistor 312 in accordance with a control signal AZSW from the timing control section 220. The auto-zero transistor 313 is, for example, a pMOS transistor.

[0059] This current source 314 supplies a constant current and is realized by an nMOS (n-channel MOS) transistor or the like.

[0060] The band-limiting capacitance 315 is inserted between the vertical signal line 259 (i.e., the source of the input transistor) and the current source 314. The placement of the band-limiting capacitance 315 makes it possible to limit a predetermined band, such as a low frequency band below the cutoff frequency. Note that the band-limiting capacitance 315 is an example of a capacitance as defined in the claims.

[0061] The cutoff switch 330 opens and closes the path between the connection node 329 of the band-limiting capacitor 315 and the current source 314 and the drain of the input transistor 312 according to the control signals XPAC1 and PAC1 from the timing control unit 220. When the cutoff switch 330 is in the closed state, the drain voltage of the input transistor 312 is output as the comparison result CMP1 from the connection node 329.

[0062] The clamp transistor 316 is inserted between the source of the input transistor 312 and the connection node 329. As the clamp transistor 316, a pMOS (n-channel MOS) transistor is used, and its gate is short-circuited to the drain. Also, it is desirable that the back gate and the source of the clamp transistor 316 be short-circuited. With this clamp transistor 316, it is possible to suppress a decrease in the drain voltage of the input transistor 312 when the input transistor 312 is in the off state. The potential lower than the input potential V VSL by the drain-source voltage of the clamp transistor 316 is hereinafter referred to as the "clamp potential V CLP ".

[0063] The source of the output transistor 317 is connected to the vertical signal line 259, and the input potential V VSL is input to the source. Also, the gate of the output transistor 317 is connected to the drain of the input transistor 312, and the comparison result CMP1 is input. As this output transistor 317, for example, a pMOS transistor is used. Also, it is desirable that the back gate and the source of the output transistor 317 be short-circuited.

[0064] The output transistor 317 outputs, as the comparison result CMP2, a signal indicating whether or not the difference between the input potential V VSL input to the source and the comparison result CMP1 input to the gate exceeds a predetermined threshold voltage from the drain. This comparison result CMP2 is input to the inverter 340. Note that the output transistor 317 is an example of the second output transistor described in the claims.

[0065] Here, when the pixel signal and the reference signal are substantially the same, the drain voltage of the input transistor 312 (i.e., the comparison result CMP1) varies according to the level of the pixel signal. Therefore, when the comparison result CMP1 is input to a subsequent circuit having a fixed threshold with respect to the ground potential, for example, the timing at which the drain voltage is inverted may deviate from the ideal timing at which the pixel signal and the reference signal are substantially the same.

[0066] With the connection shown in the figure, the drain-source voltage of the input transistor 312 is input as the gate-source voltage of the output transistor 317. Since the amount of variation in the drain voltage of the input transistor 312 is equivalent to the amount of variation in the voltage of the pixel signal, the comparison result CMP2 from the output transistor 317 is inverted at the ideal timing at which the pixel signal and the reference signal are substantially the same. When this comparison result CMP2 is connected to a subsequent circuit having a fixed threshold with respect to the ground potential, for example, the comparison result CMP2 varies according to the pixel signal level in the same manner as the comparison result CMP1, but the gain is higher than that of the comparison result CMP1, so the error becomes less visible. In this way, by adding the output transistor 317, the error in the inversion timing can be suppressed.

[0067] The current source 318 is inserted between the drain of the output transistor 317 and the reference potential VSSB, and supplies a constant current. The current source 318 is realized by an nMOS transistor or the like.

[0068] The clamp transistor 319 is inserted between the source and the drain of the output transistor 317. As the clamp transistor 319, a pMOS (n-channel MOS) transistor is used, and its gate is short-circuited to the drain. Also, it is desirable that the back gate and the source of the clamp transistor 319 are short-circuited. With this clamp transistor 319, a decrease in the drain voltage when the output transistor 317 is in the off state can be suppressed. The clamp potential corresponding to the clamp transistor 319 shall be substantially the same as the clamp potential corresponding to the clamp transistor 316.

[0069] Note that although the clamp transistor 316, the output transistor 317, and the clamp transistor 319 are arranged in the comparator 300, it is also possible to adopt a configuration in which at least one of them is not provided. When the output transistor 317 is not provided, the current source 318 and the clamp transistor 319 become unnecessary.

[0070] Reference potential V RMP is set higher than the auto-zero level at the start of the AD conversion and decreases with the passage of time during the AD conversion period. Here, the AD conversion period is the period for the counter 261 to perform counting. At the start of the AD conversion period, the first-stage input transistor 312 is in the off state, current flows through the clamp transistor 316, and from the connection node 329 via the cutoff switch 330, a clamp potential V VSL lower than the input potential V CLP is output as the comparison result CMP1. The second-stage output transistor 317 is in the on state and outputs the input potential V VSL as the comparison result CMP2.

[0071] Then, as the reference potential V RMP drops and the gate potential of the input transistor 312, which is in the substantially matching state, becomes lower than the value obtained by subtracting the threshold Vt of the input transistor 312 from the input potential V VSL , the first-stage input transistor 312 transitions to the on state, and the comparison result CMP1 is inverted to the input potential V VSL . The second-stage output transistor 317 transitions to the off state, and the comparison result CMP2 is inverted to the clamp potential V CLP .

[0072] Thus, the potential of the comparison result CMP1 is a value within the range from the clamp potential V CLP to the input potential V VSL . Also, within the counting period of the counter 261 (i.e., the AD conversion period), the comparison result CMP1 output from the connection node 329 changes from the low level (clamp potential V CLP ) to the high level (input potential V VSL) It transitions to this state. Therefore, it is necessary to initialize the potential of the connection node 329 to a low level immediately before the AD conversion period. The timing control unit 220 controls the cutoff switch 330 to be in the open state for a predetermined pulse period at the timing of initializing it to the low level. As a result, the connection node 329 is disconnected from the drain of the input transistor 312. Also, outside the pulse period, the cutoff switch 330 is controlled to be in the closed state, and the connection node 329 is connected to the drain of the input transistor 312.

[0073] Note that the clamp potential V output from the input transistor 312 CLP and the input potential V VSL are examples of a pair of output potentials described in the claims.

[0074] The inverter 340 inverts the comparison result CMP2 and supplies the inverted signal to the inverter 350. The inverter 350 inverts the inverted signal from the inverter 340 and supplies it to the counter 261 as the output signal VCO.

[0075] Note that instead of the inverters 340 and 350, other logic gates such as buffers and NOR (negative OR) gates can also be provided. The inverters 340 and 350 are examples of the logic gates described in the claims.

[0076] [Configuration Example of Cutoff Switch and Inverter] FIG. 7 is a circuit diagram showing a configuration example of the cutoff switch 330, the inverters 340 and 350 in the first embodiment of the present technology. In the figure, a is a circuit diagram showing a configuration example of the cutoff switch 330. In the figure, b is a circuit diagram showing a configuration example of the inverters 340 and 350.

[0077] As illustrated by a in the same figure, the cutoff switch 330 includes an nMOS transistor 331 and a pMOS transistor 332 connected in parallel between the drain of the input transistor 312 and the current source 314. A control signal XPAC1 is input to the gate of the nMOS transistor 331, and a control signal PAC1 is input to the gate of the pMOS transistor 332. The control signal XPAC1 is a signal with a phase different from PAC1 by 180 degrees.

[0078] Note that the nMOS transistor 331 is an example of the N-type transistor described in the claims, and the pMOS transistor 332 is an example of the P-type transistor described in the claims.

[0079] Also, as illustrated by b in the same figure, the inverter 340 includes a pMOS transistor 341 and an nMOS transistor 342. The inverter 350 includes a pMOS transistor 351 and an nMOS transistor 352.

[0080] The pMOS transistor 341 and the nMOS transistor 342 in the inverter 340 are connected in series between the power supply potential VDDC and the reference potential VSSC. The comparison result CMP2 is input to the gates of these transistors. An inverted signal INV is output from the connection node of the pMOS transistor 341 and the nMOS transistor 342 to the inverter 350. Here, the power supply potential VDDB is a power supply potential different from the power supply potential VDDA of the pixel circuit 250. Also, the reference potential VSSC is a potential different from the reference potential VSSB of the comparator 300.

[0081] The pMOS transistor 351 and the nMOS transistor 352 in the inverter 350 are connected in series between the power supply potential VDDC and the reference potential VSSC. The inverted signal INV is input to the gates of these transistors. An output signal VCO is output from the connection node of the pMOS transistor 351 and the nMOS transistor 352 to the counter 261.

[0082] The inverters 340 and 350 can convert the power supply potential VDDB at their previous stage into a lower power supply potential VDDC.

[0083] FIG. 8 is a diagram for explaining the effect of improving responsiveness in the first embodiment of the present technology. In FIG. 8, a is a circuit diagram showing a configuration example of a comparator 300 of a comparative example in which the cutoff switch 330 is not provided. In FIG. 8, b is a circuit diagram showing a configuration example of the comparator 300 in the first embodiment of the present technology.

[0084] As illustrated in a of the figure, assume a comparative example in which the cutoff switch 330 is not provided and the drain of the input transistor 312 is connected to the connection node 329. In this comparative example, assume that the potential of the connection node 329 transitions from a high level (input potential V VSL ) to a low level (clamp potential V CLP ), and a reference potential V VSL equal to or higher than the input potential V RMP is input to the input transistor 312.

[0085] When the high-level reference potential V RMP is input, the input transistor 312 transitions to an off state, and the comparison result CMP1 transitions from a high level to a low level. However, since the difference between the reference potential V RMP and the input potential V VSL is relatively small, the input transistor 312 does not turn off completely and weakly turns off, causing a leakage current to flow between the drain and source of the input transistor 312.

[0086] Also, since the current source 314 supplies a constant current, the differential current between the leakage current of the input transistor 312 and the constant current supplied by the current source 314 discharges the bandwidth limiting capacitor 315. The thin arrows in a of the figure indicate the differential current and the leakage current. The thick arrow indicates the constant current.

[0087] The speed at which the comparison result CMP1 transitions to the low level in response to the input (i.e., the response speed) is determined by the throughput rate and the settling time. The throughput rate of the first stage means the rate of decrease in the potential of the connection node 329 when discharging the band-limiting capacitance 315 with the discharge current. The settling time of the first stage means the time until the potential of the connection node 329 transitions to the low level when assuming an RC circuit including the output impedance of the input transistor 312 and the band-limiting capacitance 315. The higher the discharge current, the better the throughput rate and the higher the response speed. Also, the larger the capacitance value of the band-limiting capacitance 315, the longer the settling time and the lower the response speed.

[0088] In particular, since the input transistor 312 has its source grounded, if the drain conductance is g ds then its output impedance is 1 / g ds which is relatively high. Also, in a of the same figure, since it is discharged by the leakage current and the current of the difference between the constant currents (thin arrow), the discharge current becomes smaller than when there is no leakage current, and the response speed decreases. Also, since the parasitic capacitance between the drain and source of the input transistor 312 appears as part of the band-limiting capacitance 315, the capacitance value becomes larger than when there is no parasitic capacitance, and the response speed decreases. The dotted capacitance in the same figure indicates the parasitic capacitance.

[0089] On the other hand, as illustrated in b of the same figure, when the cutoff switch 330 is provided and opened, the leakage current is cut off, so the discharge current becomes larger than in the comparative example. Also, since the input transistor 312 is disconnected, the capacitance value becomes smaller by the amount of the parasitic capacitance between its drain and source. As a result, the response speed increases and the responsiveness is improved compared to the comparative example.

[0090] [Operation example of solid-state imaging device] FIG. 9 is a timing chart showing an example of the operation of the solid-state imaging device 200 in the first embodiment of the present technology. The alternate long and short dash line in the same figure indicates the potential of the vertical signal line 259 (input potential V VSL ).

[0091] During the auto-zero period from timing T0 to timing T1, DAC230 sets the reference potential V RMP to the auto-zero potential V AZ . Also, the timing control unit 220 sets the control signal AZSW to the low level. As a result, the comparison results CMP1 and CMP2 become the auto-zero potential V AZ . Also, the control signal PAC1 is controlled to the low level, and the control signal XPAC1 is controlled to the high level. Thereby, the cutoff switch 330 is in the closed state.

[0092] At timings T1 to T8, the timing control unit 220 sets the control signal AZSW to the high level. Also, at timing T1, the timing control unit 220 sets the control signal PAC1 to the high level and the control signal XPAC1 to the low level over a predetermined pulse period. Thereby, the cutoff switch 330 is in the open state.

[0093] During the period from timing T1 to T2, DAC230 makes the reference potential V RMP higher than that at the time of auto-zero. As a result, the input transistor 312 turns off, and the comparison result CMP1 of the clamp potential V CLP is output. The clamp potential at this time is higher than the clamp potential corresponding to the signal level, and this potential is denoted as V CLPH . During this period, the output transistor 317 turns on, and the comparison result CMP2 of the reset level V VSLL is output. Also, the inverter 350 outputs a high-level output signal VCO.

[0094] Here, the comparison results CMP1, CMP2, and the output signal VCO do not actually instantaneously transition from one of the high level and the low level to the other, and it takes a predetermined time according to a time constant or the like until the transition is completed. However, in the figure, for the sake of convenience of explanation, the waveforms are depicted as instantaneously transitioning.

[0095] Then, during the period from timing T2 to T4, DAC230 sets the reference potential V RMPis decreased over time. This period corresponds to the AD conversion period of the reset level. At timing T3 within this period, it is assumed that the difference between the reference potential V RMP and the input potential V VSL becomes less than the threshold voltage Vt of the input transistor 312. At this time, the input transistor 312 transitions to the on state, and the comparison result CMP1 is inverted to the reset level V VSLL . The output transistor 317 transitions to the off state, and the comparison result CMP2 is inverted to the clamp potential V CLPH . The output signal VCO is inverted to the low level.

[0096] At timing T5, the timing control unit 220 sets the control signal PAC1 to the high level and the control signal XPAC1 to the low level over a predetermined pulse period. Thereby, the cutoff switch 330 becomes open.

[0097] Also, within the period from timing T5 to T6, the DAC 230 makes the reference potential V RMP higher than that at the time of auto-zero. Thereby, the input transistor 312 becomes off, and outputs the comparison result CMP1 of the clamp potential V CLP . The clamp potential at this time is lower than the clamp potential corresponding to the black level, and this potential is denoted as V CLPL . Within this period, the output transistor 317 becomes on and outputs the comparison result CMP2 of the signal level V VSLL . Also, the inverter 350 outputs a high-level output signal VCO.

[0098] Then, within the period from timing T6 to T8, the DAC 230 decreases the reference potential V RMP over time. This period corresponds to the AD conversion period of the signal level. At timing T7 within this period, it is assumed that the difference between the reference potential V RMP and the input potential V VSL becomes less than the threshold voltage Vt. At this time, the comparison result CMP1 is inverted to the signal level V VSLL , and the comparison result CMP2 is inverted to the clamp potential V CLPLIt is inverted. The output signal VCO is inverted to a low level.

[0099] As illustrated in the figure, the timing control unit 220 controls the cutoff switch 330 to be in an open state for a predetermined pulse period at timings T1 and T5 immediately before the AD conversion period.

[0100] FIG. 10 is an example of a timing chart when a black level is input during the signal level conversion period in the first embodiment of the present technology. In FIG. 10, a shows an example of the waveform of the potential (input potential V VSL ) of the vertical signal line 259 and the reference potential V RMP . b in the figure is a diagram showing an example of the waveform of the comparison result CMP1 in a comparative example without the cutoff switch 330. c in the figure is a diagram showing an example of the waveform of the comparison result CMP1 in the first embodiment provided with the cutoff switch 330.

[0101] As illustrated by the dashed-dotted line in a of the figure, a black level substantially the same as the reset level is input as the signal level.

[0102] As illustrated in b of the figure, in a comparative example without the cutoff switch 330, the slope when the comparison result CMP1 transitions from a high level to a low level is gentle and the time until it transitions to the low level becomes long. The thick line in the figure shows the locus when transitioning from a high level to a low level. Also, immediately after timings T2 and T6, before it drops to the clamp potential, the transition to the high level is started, so the amplitude from the low level to the high level is different between the reset level conversion and the signal level conversion. The line segment with arrows at both ends in the figure shows the magnitude of the amplitude. As a result, the characteristics of the comparator 300 may deteriorate.

[0103] On the other hand, as illustrated by c in the figure, when the cutoff switch 330 is provided, due to the cutoff of leakage current and parasitic capacitance, the slope when transitioning from a high level to a low level becomes steep, and the time until transitioning to the low level becomes short. Also, since the transition to the high level is started after the potential has dropped to the clamp potential, the amplitude from the low level to the high level is the same during the conversion of the reset level and during the conversion of the signal level. Thereby, deterioration of the characteristics of the comparator 300 can be suppressed.

[0104] FIG. 11 is an example of a timing chart when a white level is input during the signal level conversion period in the first embodiment of the present technology. a in the figure is a diagram showing an example of the waveforms of the potential (input potential V VSL ) of the vertical signal line 259 and the reference potential V RMP . b in the figure is a diagram showing an example of the waveform of the comparison result CMP1 in a comparative example without the cutoff switch 330. c in the figure is a diagram showing an example of the waveform of the comparison result CMP1 in the first embodiment provided with the cutoff switch 330.

[0105] As illustrated by the dashed-dotted line of a in the figure, a white level lower than the reset level is input as the signal level.

[0106] As illustrated by b in the figure, in the comparative example without the cutoff switch 330, the time until the comparison result CMP1 transitions to the low level becomes long. Also, the amplitude from the low level to the high level is different during the conversion of the reset level and during the conversion of the signal level.

[0107] On the other hand, as illustrated by c in the figure, when the cutoff switch 330 is provided, due to the cutoff of leakage current and parasitic capacitance, the time until transitioning to the low level becomes short. Also, the amplitude from the low level to the high level is the same during the conversion of the reset level and during the conversion of the signal level.

[0108] FIG. 12 is a flowchart showing an example of the operation of the solid-state imaging device 200 in the first embodiment of the present technology. This operation is started, for example, when a predetermined application for imaging image data is executed.

[0109] The vertical scanning circuit 210 selects a readout row and exposes it (step S911). The cutoff switch 330 disconnects the input transistor 312 from the connection node 329 within the pulse period (step S912). The column signal processing unit 260 AD-converts the reset level for each column (step S913). The cutoff switch 330 disconnects the input transistor 312 from the connection node 329 within the pulse period (step S914). The column signal processing unit 260 AD-converts the signal level for each column (step S915). Then, the vertical scanning circuit 210 determines whether the readout row is the last row (step S916).

[0110] If the readout row is not the last row (step S916: No), the solid-state imaging device 200 repeats steps S911 and subsequent steps. On the other hand, if the readout row is the last row (step S916: Yes), the solid-state imaging device 200 ends the operation for imaging.

[0111] Note that the operations of the timing chart illustrated in FIG. 9 correspond to steps S912 to S915 in FIG. 12.

[0112] When continuously imaging a plurality of pieces of image data, steps S911 to S916 are repeatedly executed in synchronization with the vertical synchronization signal.

[0113] As described above, according to the first embodiment of the present technology, since the cutoff switch 330 disconnects the input transistor 312 from the connection node 329, the leakage current of the input transistor 312 can be blocked, and the parasitic capacitance can be disconnected from the connection node 329. Thereby, the responsiveness of the comparator 300 can be improved.

[0114] [First Modification Example] In the above-described first embodiment, the cutoff switch 330 composed of the nMOS transistor 331 and the pMOS transistor 332 was arranged for each column. However, in this configuration, the number of transistors increases compared to the case where the cutoff switch 330 is realized by one transistor. The solid-state imaging device 200 according to the first modification of the first embodiment is different from the first embodiment in that the cutoff switch 330 composed only of the nMOS transistor 331 is used.

[0115] FIG. 13 is a circuit diagram showing a configuration example of the comparator 300 in the first modification of the first embodiment of the present technology. The comparator 300 according to the first modification of the first embodiment is different from the first embodiment in that the cutoff switch 330 composed only of the nMOS transistor 331 is arranged. The waveform of the control signal XPAC1 for controlling the nMOS transistor 331 is the same as that in the first embodiment.

[0116] By realizing the cutoff switch 330 with only the nMOS transistor 331, the number of transistors can be reduced compared to the case of using a pair of transistors (the nMOS transistor 331 and the pMOS transistor 332).

[0117] As described above, according to the first modification of the first embodiment of the present technology, since the cutoff switch 330 composed only of the nMOS transistor 331 is used, the number of transistors can be reduced compared to the case of using a pair of transistors.

[0118] [Second Modification] In the above-described first embodiment, the cutoff switch 330 composed of the nMOS transistor 331 and the pMOS transistor 332 was arranged for each column. However, in this configuration, the number of transistors increases compared to the case where the cutoff switch 330 is realized by one transistor. The solid-state imaging device 200 according to the second modification of the first embodiment is different from the first embodiment in that the cutoff switch 330 composed only of the pMOS transistor 332 is used.

[0119] FIG. 14 is a circuit diagram showing a configuration example of the comparator 300 in the second modification of the first embodiment of the present technology. The comparator 300 of the second modification of the first embodiment is different from the first embodiment in that a cutoff switch 330 composed only of a pMOS transistor 332 is arranged. The waveform of the control signal PAC1 for controlling the pMOS transistor 332 is the same as that of the first embodiment.

[0120] By realizing the cutoff switch 330 only with the pMOS transistor 332, the number of transistors can be reduced as compared with the case of using a pair of transistors (nMOS transistor 331 and pMOS transistor 332).

[0121] As illustrated in FIGS. 14 and 15, the cutoff switch 330 can be realized by either only the nMOS transistor 331 or only the pMOS transistor 332. When the level of the first-stage comparison result CMP1 is relatively low, the nMOS transistor 331 is used. On the other hand, when the level of the first-stage comparison result CMP1 is relatively high, the pMOS transistor 332 is used. Also, when the level of the comparison result CMP2 is about the middle of the power supply potential VDDB, both the nMOS transistor 331 and the pMOS transistor 332 are used as in the first embodiment.

[0122] Thus, according to the second modification of the first embodiment of the present technology, since the cutoff switch 330 composed only of the pMOS transistor 332 is used, the number of transistors can be reduced as compared with the case of using a pair of transistors.

[0123] <2. Second Embodiment> In the above-described first embodiment, the time until the comparison result CMP1 transitions to the low level is shortened by the cutoff switch 330. However, with the cutoff switch 330, there may be cases where the response speed until the second-stage comparison result CMP2 becomes high level cannot be made sufficiently fast. The solid-state imaging device 200 of this second embodiment differs from the first embodiment in that the responsiveness is improved by short-circuiting the source and drain of the output transistor 317.

[0124] FIG. 15 is a circuit diagram showing a configuration example of the comparator 300 in the second embodiment of the present technology. The comparator 300 of this second embodiment differs from the first embodiment in that it includes an output-side short-circuit switch 360 instead of the cutoff switch 330. Also, the drain of the input transistor 312 in the second embodiment is connected to the connection node 329.

[0125] The output-side short-circuit switch 360 opens and closes the path between the source (in other words, the vertical signal line 259) and the drain of the output transistor 317 according to the control signals XPAC2 and PAC2 from the timing control unit 220.

[0126] The output-side short-circuit switch 360 includes, for example, an nMOS transistor 361 and a pMOS transistor 362 connected in parallel between the source and drain of the output transistor 317. The control signal PAC2 is input to the gate of the nMOS transistor 361, and the control signal XPAC2 is input to the gate of the pMOS transistor 362. The control signal XPAC2 is a signal with a phase 180 degrees different from PAC2.

[0127] Note that the nMOS transistor 361 is an example of the N-type transistor described in the claims, and the pMOS transistor 362 is an example of the P-type transistor described in the claims.

[0128] The potential of the second-stage comparison result CMP2 is from the clamp potential V CLP to the input potential V VSLis a value within the range up to. Also, during the counting period (AD conversion period) of the counter 261, the comparison result CMP2 from the drain of the output transistor 317 is at a high level (input potential V VSL ) and transitions to a low level (clamp potential V CLP ). Therefore, it is necessary to initialize the drain of the output transistor 317 to a high level immediately before the AD conversion period.

[0129] Here, the speed at which the comparison result CMP2 transitions to a high level in response to the input (i.e., the response speed) is determined by the slew rate and the settling time. The second-stage slew rate means the rising speed of the drain when charging the parasitic capacitance on the drain side of the output transistor 317 with the charging current from the output transistor 317. The second-stage settling time means the time until the potential of the drain transitions to a high level when assuming an RC circuit including the output impedance of the output transistor 317 and the parasitic capacitance. The dotted capacitance in the figure indicates the parasitic capacitance.

[0130] Also, the second-stage comparison result CMP2 is linked to the first-stage comparison result CMP1, and when the response speed of the first stage decreases, the response speed of the second stage also decreases.

[0131] The timing control unit 220 controls the output-side short-circuit switch 360 to be in a closed state for a predetermined pulse period at the timing of initializing to a high level. As a result, the source (vertical signal line 259) and the drain of the output transistor 317 are short-circuited. Since the potential of the vertical signal line 259 is at a high level (input potential V VSL ), the short circuit can increase the speed at which the comparison result CMP2 transitions to a high level. Also, during the auto-zero period, the output-side short-circuit switch 360 is controlled to be in a closed state.

[0132] FIG. 16 is a timing chart showing an example of the operation of the solid-state imaging device 200 in the second embodiment of the present technology.

[0133] During the auto-zero period from timing T0 to timing T1, the timing control unit 220 sets the control signal PAC2 to a high level and the control signal XPAC2 to a low level. As a result, the cutoff switch 330 is in a closed state.

[0134] Then, from timing T1 until the pulse period elapses, the timing control unit 220 keeps the control signal PAC2 at a high level and the control signal XPAC2 at a low level. After the pulse period has elapsed, the control signal PAC2 is controlled to a low level and the control signal XPAC2 is controlled to a high level. As a result, the cutoff switch 330 is in an open state.

[0135] At timing T5 when the reset level conversion period has elapsed, the timing control unit 220 sets the control signal PAC2 to a high level and the control signal XPAC1 to a low level for a predetermined pulse period. As a result, the output-side short-circuit switch 360 is in a closed state. After the pulse period has elapsed, the control signal PAC2 is controlled to a low level and the control signal XPAC2 is controlled to a high level. As a result, the cutoff switch 330 is in an open state.

[0136] As illustrated in the figure, the timing control unit 220 controls the output-side short-circuit switch 360 to be in a closed state for a predetermined pulse period at timings T1 and T5 immediately before the AD conversion period. Thereby, the speed (response speed) at which the comparison result CMP2 transitions to a high level can be increased.

[0137] Also, the timing control unit 220 controls the output-side short-circuit switch 360 to be in a closed state even within the auto-zero period from timing T0 to timing T1. A loop circuit is formed by the first-stage input transistor 312, the second-stage output transistor 317, and the vertical signal line 259, and there is a possibility that the loop circuit oscillates during the auto-zero period. However, by controlling the output-side short-circuit switch 360 to be in a closed state even within the auto-zero period, oscillation during the auto-zero period can be suppressed.

[0138] FIG. 17 is an example of a timing chart when a black level is input during a signal level conversion period in the second embodiment of the present technology. In FIG. 17, a shows an example of waveforms of the potential (input potential V VSL ) of the vertical signal line 259 and the reference potential V RMP . In FIG. 17, b shows an example of the waveform of the comparison result CMP2 in a comparative example without the output-side short-circuit switch 360. In FIG. 17, c shows an example of the waveform of the comparison result CMP2 in the second embodiment provided with the output-side short-circuit switch 360.

[0139] As illustrated in a in the figure, a black level substantially the same as the reset level is input as the signal level.

[0140] As illustrated in b in the figure, in the comparative example without the output-side short-circuit switch 360, the slope when the comparison result CMP2 transitions from the low level to the high level is gentle and the time until it transitions to the high level becomes long. The thick line in the figure indicates the locus when transitioning from the low level to the high level.

[0141] Also, immediately after timing T6, before reaching the reset level, a transition to the low level is started, so the amplitude from the high level to the low level is different between when the reset level is converted and when the signal level is converted. As a result, the characteristics of the comparator 300 may deteriorate.

[0142] On the other hand, as illustrated in c in the figure, when the output-side short-circuit switch 360 is provided, the short circuit between the source (vertical signal line 259) and the drain of the output transistor 317 shortens the time until transitioning to the high level. Also, since the transition to the low level is started after reaching the reset level, the amplitude from the high level to the low level is the same between when the reset level is converted and when the signal level is converted. As a result, deterioration of the characteristics of the comparator 300 can be suppressed.

[0143] FIG. 18 is an example of a timing chart when a white level is input during the signal level conversion period in the second embodiment of the present technology. In FIG. 18, a shows an example of waveforms of the potential (input potential V VSL ) of the vertical signal line 259 and the reference potential V RMP . In FIG. 18, b shows an example of the waveform of the comparison result CMP2 in a comparative example without the output-side short-circuit switch 360. In FIG. 18, c shows an example of the waveform of the comparison result CMP2 in the second embodiment provided with the output-side short-circuit switch 360.

[0144] As illustrated in a in the figure, as the signal level, a white level lower than the reset level is input.

[0145] As illustrated in b in the figure, in the comparative example without the output-side short-circuit switch 360, the time until the comparison result CMP2 transitions to the high level becomes long. Also, the amplitude from the high level to the low level is different between when the reset level is converted and when the signal level is converted.

[0146] On the other hand, as illustrated in c in the figure, when the output-side short-circuit switch 360 is provided, due to the short circuit, the time until it transitions to the high level becomes short. Also, the amplitude from the high level to the low level is the same between when the reset level is converted and when the signal level is converted.

[0147] Thus, according to the second embodiment of the present technology, since the output-side short-circuit switch 360 short-circuits the source and drain of the output transistor 317, the speed at which the comparison result CMP2 transitions to the potential (high level) of the source can be increased. Thereby, the responsiveness can be improved.

[0148] [First Modification Example] In the above-described second embodiment, the output-side short-circuit switch 360 composed of the nMOS transistor 361 and the pMOS transistor 362 was arranged for each column. However, in this configuration, the number of transistors increases compared to the case where the output-side short-circuit switch 360 is realized by one transistor. The solid-state imaging device 200 according to the first modification of the second embodiment is different from the first embodiment in that the output-side short-circuit switch 360 composed only of the nMOS transistor 361 is used.

[0149] FIG. 19 is a circuit diagram showing a configuration example of the comparator 300 in the first modification of the second embodiment of the present technology. The comparator 300 according to the first modification of the second embodiment is different from the second embodiment in that the output-side short-circuit switch 360 composed only of the nMOS transistor 361 is arranged. The waveform of the control signal PAC2 for controlling the nMOS transistor 361 is the same as that in the second embodiment.

[0150] By realizing the output-side short-circuit switch 360 with only the nMOS transistor 361, the number of transistors can be reduced compared to the case of using a pair of transistors (the nMOS transistor 361 and the pMOS transistor 362).

[0151] Thus, according to the first modification of the second embodiment of the present technology, since the output-side short-circuit switch 360 composed only of the nMOS transistor 361 is used, the number of transistors can be reduced compared to the case of using a pair of transistors.

[0152] [Second Modification Example] In the above-described second embodiment, the output-side short-circuit switch 360 composed of the nMOS transistor 361 and the pMOS transistor 362 was arranged for each column. However, in this configuration, the number of transistors increases compared to the case where the output-side short-circuit switch 360 is realized by one transistor. The solid-state imaging device 200 according to the second modification of the second embodiment is different from the first embodiment in that the output-side short-circuit switch 360 composed only of the pMOS transistor 362 is used.

[0153] FIG. 20 is a circuit diagram showing a configuration example of the comparator 300 in the second modification of the second embodiment of the present technology. The comparator 300 according to the second modification of the second embodiment is different from the second embodiment in that the output-side short-circuit switch 360 composed only of the pMOS transistor 362 is arranged. The waveform of the control signal XPAC2 for controlling the pMOS transistor 362 is the same as that in the second embodiment.

[0154] By realizing the output-side short-circuit switch 360 with only the pMOS transistor 362, the number of transistors can be reduced compared to the case of using a pair of transistors (the nMOS transistor 361 and the pMOS transistor 362).

[0155] As illustrated in FIGS. 19 and 20, the output-side short-circuit switch 360 can be realized by either only the nMOS transistor 361 or only the pMOS transistor 362. When the level of the second-stage comparison result CMP2 is relatively low, the nMOS transistor 361 is used. On the other hand, when the level of the second-stage comparison result CMP2 is relatively high, the pMOS transistor 362 is used. Also, when the level of the comparison result CMP2 is around the middle of the power supply potential VDDB, both the nMOS transistor 361 and the pMOS transistor 362 are used as in the second embodiment.

[0156] Thus, according to the second modification of the second embodiment of the present technology, since the output-side short-circuit switch 360 is composed only of the pMOS transistor 362, the number of transistors can be reduced as compared with the case of using a pair of transistors.

[0157] <3. Third Embodiment> In the above-described first embodiment, the time until the comparison result CMP1 transitions to the low level by the cutoff switch 330 was shortened. However, with only the cutoff switch 330, the response speed until the second-stage comparison result CMP2 becomes high level may not be sufficiently increased. The solid-state imaging device 200 of this third embodiment is different from the first embodiment in that the responsiveness is further improved by adding a switch that short-circuits the source and drain of the output transistor 317.

[0158] FIG. 21 is a circuit diagram showing a configuration example of the comparator 300 in the third embodiment of the present technology. The comparator 300 of this third embodiment is different from the first embodiment in that it further includes an output-side short-circuit switch 360. This output-side short-circuit switch 360 is realized only by the pMOS transistor 362, similar to the second modification of the second embodiment. The third embodiment is obtained by applying the second modification of the second embodiment to the first embodiment.

[0159] By adding the output-side short-circuit switch 360, the speed at which the second-stage output transitions to the high level can be increased, and the responsiveness of the comparator 300 can be further improved.

[0160] Note that both the nMOS transistor 331 and the pMOS transistor 332 are provided in the cutoff switch 330, but only one of them may be provided.

[0161] Also, although the output-side short-circuit switch 360 is realized only by the pMOS transistor 362, the present invention is not limited to this configuration. Both the nMOS transistor 361 and the pMOS transistor 362 may be provided in the output-side short-circuit switch 360, or only the nMOS transistor 361 may be provided.

[0162] FIG. 22 is a timing chart showing an example of the operation of the solid-state imaging device 200 according to the third embodiment of the present technology. The timing control unit 220 further supplies a control signal XPAC2 to control the output-side short-circuit switch 360. The waveform of the control signal XPAC2 is the same as that of the second modification of the second embodiment.

[0163] As described above, according to the third embodiment of the present technology, since the output-side short-circuit switch 360 short-circuits the source and the drain of the output transistor 317, the speed at which the comparison result CMP2 transitions to the potential (high level) of the source can be increased. Thereby, the responsiveness can be further improved.

[0164] <4. Fourth Embodiment> In the above-described third embodiment, the two-stage transistors of the input transistor 312 and the output transistor 317 are arranged, but a third-stage transistor having the same configuration as the output transistor 317 can also be added. The solid-state imaging device 200 of this fourth embodiment is different from the third embodiment in that a third-stage transistor is added.

[0165] FIG. 23 is a circuit diagram showing a configuration example of the comparator 300 according to the fourth embodiment of the present technology. The comparator 300 of this fourth embodiment is different from the third embodiment in that the inverter 340 is not arranged and includes an output transistor 320, a current source 321, and a clamp transistor 322.

[0166] The source of the output transistor 320 is connected to the vertical signal line 259, and the input potential V is applied to the source. VSLis input. Also, the gate of the output transistor 320 is connected to the drain of the second-stage output transistor 317, and the comparison result CMP2 is input. As the third-stage output transistor 320, for example, a pMOS transistor is used. Also, it is desirable that the back gate and the source of the output transistor 320 be short-circuited.

[0167] The output transistor 320 outputs, as the comparison result CMP3, a signal indicating whether the difference between the input potential V input to the source and the comparison result CMP2 input to the gate exceeds a predetermined threshold voltage, from the drain. This comparison result CMP3 is input to the inverter 350. Note that the output transistor 320 is an example of the second output transistor described in the claims. VSL

[0168] The current source 321 is inserted between the drain of the output transistor 320 and the reference potential VSSB and supplies a constant current. The current source 321 is realized by an nMOS transistor or the like.

[0169] The clamp transistor 322 is inserted between the source and the drain of the output transistor 320. As the clamp transistor 322, a pMOS transistor is used, and its gate is short-circuited to the drain. Also, it is desirable that the back gate and the source of the clamp transistor 322 be short-circuited.

[0170] When the second-stage output-side short-circuit switch 360 transitions to the on state immediately before the AD conversion period, the gate-source voltage of the third stage becomes close to zero, the output transistor 320 is forcibly turned off, and the comparison result CMP3 transitions to the clamp potential. Therefore, unlike the first stage, the cutoff switch 330 is not required in the third stage.

[0171] As illustrated in the figure, since the output transistor 320 is added to the third stage, the inverter 340 is reduced.

[0172] ​Note that both the cutoff switch 330 and the output-side short-circuit switch 360 are arranged, but only one of them can also be arranged. Further, for each of the cutoff switch 330 and the output-side short-circuit switch 360, both an nMOS transistor and a pMOS transistor may be provided, or only one of them may be provided.

[0173] Further, a transistor equivalent to the output transistor 320 can be further added to make it four or more stages. In this case, it is better to provide a switch equivalent to the output-side short-circuit switch 360 in even-numbered stages after the fourth stage, but it may not be provided in odd-numbered stages.

[0174] Thus, in the fourth embodiment of the present technology, since the output transistor 320 that determines whether the difference between the input potential V VSL and the comparison result CMP2 exceeds a predetermined threshold voltage is added to the third stage, the gain of the comparator 300 increases and the linearity improves.

[0175] <5. Fifth Embodiment> In the above-described third embodiment, the cutoff switch 330 disconnected the drain of the input transistor 312 from the connection node 329 immediately before AD conversion, and the input transistor 312 transitioned to the off state. However, in this configuration, the drain of the off-state input transistor 312 becomes a high-impedance node. Since the potential of the high-impedance node easily fluctuates due to capacitive coupling, the potential of the gate of the input transistor 312 fluctuates due to the fluctuation, and the characteristics of the comparator 300 may deteriorate. The solid-state imaging device 200 of this fifth embodiment is different from the third embodiment in that characteristic deterioration is suppressed by short-circuiting the source and drain of the input transistor 312.

[0176] FIG. 24 is a circuit diagram showing a configuration example of the comparator 300 in the fifth embodiment of the present technology. The comparator 300 of this fifth embodiment further includes an input-side short-circuit switch 370.

[0177] The input-side short-circuit switch 370 opens and closes the path between the source (vertical signal line 259) and the drain of the input transistor 312 according to the control signals PAC1 and XPAC1.

[0178] Also, the input-side short-circuit switch 370 includes, for example, an nMOS transistor 371 and a pMOS transistor 372 connected in parallel between the source and the drain of the input transistor 312. The control signal PAC1 is input to the gate of the nMOS transistor 371, and the control signal XPAC1 is input to the gate of the pMOS transistor 372.

[0179] According to the control signals PAC1 and XPAC1, the input-side short-circuit switch 370 becomes closed when the cutoff switch 330 is in the open state, short-circuiting the source and the drain of the input transistor 312. Thereby, it is possible to prevent the drain of the input transistor 312 from becoming a high-impedance node and suppress characteristic degradation.

[0180] Although both the cutoff switch 330 and the output-side short-circuit switch 360 are arranged, only one of them can be arranged. Also, for each of the cutoff switch 330, the output-side short-circuit switch 360, and the input-side short-circuit switch 370, both an nMOS transistor and a pMOS transistor may be provided, or only one of them may be provided. Also, the fourth embodiment can be applied to the fifth embodiment.

[0181] Thus, according to the fifth embodiment of the present technology, since the input-side short-circuit switch 370 short-circuits the source and the drain of the input transistor 312, it is possible to prevent the drain from becoming a high-impedance state. Thereby, characteristic degradation of the comparator 300 can be suppressed.

[0182] <6. Sixth Embodiment> In the above-described third embodiment, the output transistor 317 input the comparison result CMP2 to the inverter 340. However, if the voltage range is narrow, there is a risk of malfunction or leakage current in the inverter 340. The solid-state imaging device 200 of this sixth embodiment is different from the third embodiment in that a level shift circuit for expanding the voltage range is added.

[0183] FIG. 25 is a circuit diagram showing a configuration example of the comparator 300 in the sixth embodiment of the present technology. The comparator 300 of this sixth embodiment is different from the third embodiment in that it does not include the inverter 340 and further includes a level shift circuit 380.

[0184] The level shift circuit 380 outputs, as an output signal, either one of a pair of potentials (in other words, a high level and a low level) having a larger potential difference than the input potential V VSL and the clamp potential V CLP to the inverter 350. The high level is set to, for example, a power supply potential higher than the input potential V VSL . The low level is set to, for example, a reference potential lower than the clamp potential V CLP . Note that the input potential V VSL and the clamp potential V CLP are an example of a pair of output potentials described in the claims. The power supply potential and the reference potential are an example of a pair of shift potentials described in the claims.

[0185] By providing the level shift circuit 380, the voltage range on the input side of the inverter 350 can be expanded compared to the third embodiment. By expanding the voltage range, the difference between the lower limit or upper limit of the range and the threshold value of the inverter 350 becomes sufficiently large, preventing malfunction or leakage current in the inverter 350. As a result, design constraints for preventing malfunction or leakage current in the inverter 350 are relaxed, improving the design freedom. Note that the level shift circuit 380 expands both the power supply side and the ground side, but only one of them may be expanded.

[0186] Note that both the cutoff switch 330 and the output-side short-circuit switch 360 are arranged, but only one of them can also be arranged. Further, for each of the cutoff switch 330, the output-side short-circuit switch 360, and the input-side short-circuit switch 370, both an nMOS transistor and a pMOS transistor may be provided, or only one of them may be provided. Further, the fourth embodiment and the fifth embodiment can also be applied to the sixth embodiment.

[0187] FIG. 26 is a circuit diagram showing a configuration example of the level shift circuit 380 in the sixth embodiment of the present technology.

[0188] The level shift circuit 380 includes a precharge transistor 381, an nMOS transistor 382, a pMOS transistor 384, and a precharge transistor 385. As the precharge transistor 381, for example, a pMOS transistor is used. As the precharge transistor 385, for example, an nMOS transistor is used.

[0189] The source of the precharge transistor 381 is connected to the power supply potential VDDB, and the control signal PreChg1 from the timing control unit 220 is input to the gate. The drain of the precharge transistor 381 is connected to the drain of the nMOS transistor 382. Here, the power supply potential VDDB is a potential different from the power supply potential VDDA of the pixel circuit 250 and the power supply potential VDDC of the inverter.

[0190] The gate of the nMOS transistor 382 is connected to the vertical signal line 259, and the comparison result CMP2 from the output transistor 317 is input to the source. Further, the connection node of the precharge transistor 381 and the nMOS transistor 382 is connected to the gate of the pMOS transistor 384, and the output signal nOUT is output from the connection node. The back gate and the source of the nMOS transistor 382 are short-circuited.

[0191] The source of the pMOS transistor 384 is connected to the power supply potential VDDB, and the gate is connected to the connection node of the precharge transistor 381 and the nMOS transistor 382. The output signal pOUT is output from the connection node of the pMOS transistor 384 and the precharge transistor 381. The drain of the pMOS transistor 384 is connected to the drain of the precharge transistor 385.

[0192] The source of the precharge transistor 385 is connected to the reference potential VSSB, and the control signal PreChg2 is input to the gate. Also, the connection node of the pMOS transistor 384 and the precharge transistor 385 is connected to the inverter 350, and the output signal pOUT is output from the connection node.

[0193] Note that the precharge transistor 381 is an example of the power supply side precharge transistor described in the claims. The nMOS transistor 382 is an example of the N-type transistor described in the claims. The pMOS transistor 384 is an example of the P-type transistor described in the claims. The precharge transistor 385 is an example of the reference side precharge transistor described in the claims.

[0194] The timing control unit 220 turns on the precharge transistors 381 and 385 by the control signals PreChg1 and PreChg2 immediately before the AD conversion period. The on-state precharge transistor 381 precharges the parasitic capacitance 383 and initializes the drain of the nMOS transistor 382 to the power supply potential VDDB. Also, the on-state precharge transistor 385 precharges the parasitic capacitance 386 and initializes the drain of the nMOS transistor 382 to the reference potential VSSB. Also, during the AD conversion period, the precharge transistors 381 and 385 are controlled to be in the off state.

[0195] At the start of the AD conversion, the comparison result CMP2 is the input potential V VSL(It becomes (high level). At this time, the nMOS transistor 382 is turned off, and the power supply potential VDDB of the pre-charged parasitic capacitance 383 is output as the output signal nOUT. In response to this output signal nOUT, the pMOS transistor 384 is turned off, and the reference potential VSSB of the pre-charged parasitic capacitance 386 is output as the output signal pOUT.)

[0196] And when the comparison result CMP2 is inverted to the clamp potential V CLP (low level), the nMOS transistor 382 transitions to the on state, and the potential of the output signal nOUT is inverted to the clamp potential V CLP . Then, in response to this output signal nOUT, the pMOS transistor 384 transitions to the on state, and the potential of the output signal pOUT is inverted to the power supply potential VDDB.)

[0197] Note that the configuration may be such that the pMOS transistor 384 and the pre-charge transistor 385 are not provided. In this case, an inverter 340 is added, and the output signal nOUT is output to the inverter 340. Also, the back gate of the nMOS transistor 382 can be grounded.)

[0198] FIG. 27 is a timing chart showing an example of the operation of the solid-state imaging device 200 in the sixth embodiment of the present technology.)

[0199] The timing control unit 220 sets the control signal PreChg1 to the low level and the control signal PreChg2 to the high level from the timing T0 until immediately after the timing T1 (when the pulse period has elapsed from the timing T1). Thereby, the pre-charge transistors 381 and 385 perform pre-charge. Until the subsequent timing T5, the control signal PreChg1 is controlled to the high level and the control signal PreChg2 is controlled to the low level.)

[0200] Also, the timing control unit 220 sets the control signal PreChg1 to the low level and the control signal PreChg2 to the high level over the pulse period from timing T5 to precharge the precharge transistors 381 and 385. Until the subsequent timing T8, the control signal PreChg1 is controlled to the high level and the control signal PreChg2 is controlled to the low level.

[0201] In the figure, the auto-zero period from timing T0 to timing T1 is such that the second-stage output (comparison result CMP2) is at the auto-zero potential V AZ Therefore, if the output-side short-circuit switch 360 is opened during that period, a potential difference is generated between the gate and source of the nMOS transistor 382. Due to this potential difference, the nMOS transistor 382 turns on, and there is a risk of leakage current flowing from the power supply potential VDDB through the precharge transistor 381, the nMOS transistor 382, and the current source 318. However, as illustrated in the figure, during the auto-zero period, the output-side short-circuit switch 360 is controlled to the closed state by the control signal XPAC2, so that the nMOS transistor 382 is turned off. Thus, by closing the output-side short-circuit switch 360 during the auto-zero period, in addition to suppressing oscillation, leakage current can be prevented.

[0202] Thus, according to the sixth embodiment of the present technology, since the level shift circuit ********** outputs either one of a pair of potentials having a larger potential difference than the input potential V VSL and the clamp potential V CLP the voltage range on the input side of the inverter 350 can be expanded. By expanding the voltage range, the difference between the lower or upper limit of that range and the threshold value of the inverter 350 becomes sufficiently large, preventing malfunction and leakage current of the inverter 350. As a result, design constraints regarding the power supply voltage and threshold value for preventing malfunction and leakage current are relaxed, and the design freedom can be improved.

[0203] <7. Seventh Embodiment> In the above-described first embodiment, a ramp signal in which the level (reference potential V RMP ) gradually decreases during the AD conversion period is used, but a ramp signal in which the level gradually increases can also be used. The solid-state imaging device 200 of this seventh embodiment is different from the first embodiment in that a ramp signal in which the level gradually increases is used.

[0204] FIG. 28 is a circuit diagram showing a configuration example of the comparator 300 in the seventh embodiment of the present technology. The comparator 300 of this seventh embodiment is different from the first embodiment in that it does not include the cutoff switch 330 and the inverter 350, and further includes an input-side short-circuit switch 370.

[0205] The input-side short-circuit switch 370 opens and closes the path between the source (vertical signal line 259) and the drain of the input transistor 312 according to the control signals PAC1 and XPAC1.

[0206] Further, the input-side short-circuit switch 370 includes, for example, an nMOS transistor 371 and a pMOS transistor 372 connected in parallel between the source and the drain of the input transistor 312. The control signal PAC1 is input to the gate of the nMOS transistor 371, and the control signal XPAC1 is input to the gate of the pMOS transistor 372.

[0207] FIG. 29 is a timing chart showing an example of the operation of the solid-state imaging device 200 in the seventh embodiment of the present technology.

[0208] During the auto-zero period from timing T0 to timing T1, the DAC 230 sets the reference potential V RMP to the auto-zero potential V AZ . Further, the timing control unit 220 sets the control signal AZSW to a low level. As a result, the comparison results CMP1 and CMP2 become the auto-zero potential V AZ . Also, the control signal PAC1 is controlled to a low level, and the control signal XPAC1 is controlled to a high level. As a result, the input-side short-circuit switch 370 is in an open state.

[0209] At timings T1 to T8, the timing control unit 220 sets the control signal AZSW to a high level. Also, at timing T1, the timing control unit 220 sets the control signal PAC1 to a high level and the control signal XPAC1 to a low level over a predetermined pulse period. As a result, the input-side short-circuit switch 370 is in a closed state.

[0210] Within the period from timing T1 to T2, the DAC 230 makes the reference potential V RMP lower than that at auto-zero time. As a result, the input transistor 312 turns on and outputs the comparison result CMP1 of the reset level V VSLH . During this period, the output transistor 317 turns off and outputs the comparison result CMP2 of the clamp potential V CLPH . Also, the inverter 350 outputs a high-level output signal VCO.

[0211] Then, within the period from timing T2 to T4, the DAC 230 raises the reference potential V RMP with the passage of time. This period corresponds to the AD conversion period of the reset level. At timing T3 within this period, it is assumed that the difference between the reference potential V RMP and the input potential V VSL becomes less than the threshold voltage Vt of the input transistor 312. At this time, the input transistor 312 transitions to an off state, and the comparison result CMP1 is inverted to the clamp potential V CLPH . The output transistor 317 transitions to an on state, and the comparison result CMP2 is inverted to the reset level V VSLH . The output signal VCO is inverted to a low level.

[0212] At timing T5, the timing control unit 220 sets the control signal PAC1 to a high level and the control signal XPAC1 to a low level over a predetermined pulse period. As a result, the input-side short-circuit switch 370 is in a closed state.

[0213] Also, within the period from timing T5 to T6, DAC230 makes the reference potential V RMP lower than that during auto-zeroing. As a result, the input transistor 312 turns on and outputs the comparison result CMP1 of the signal level V VSLL . During this period, the output transistor 317 turns off and outputs the comparison result CMP2 of the clamp potential V CLPL . Also, the inverter 350 outputs a high-level output signal VCO.

[0214] Then, within the period from timing T6 to T8, DAC230 raises the reference potential V RMP over time. This period corresponds to the AD conversion period of the signal level. At timing T7 within this period, assume that the difference between the reference potential V RMP and the input potential V VSL becomes less than the threshold voltage Vt. At this time, the comparison result CMP1 reverses to the clamp potential V CLPL , and the comparison result CMP2 reverses to the signal level V VSLL . The output signal VCO reverses to the low level.

[0215] As illustrated in the figure, when using a ramp signal whose level gradually rises, since it is necessary to increase the speed at which the output of the first stage transitions to the high level, an input-side short-circuit switch 370 is provided in the first stage. In this case, the cutoff switch 330 for increasing the speed of transitioning to the low level becomes unnecessary.

[0216] Thus, according to the seventh embodiment of the present technology, since a ramp signal whose level gradually rises is used, the responsiveness can be improved by the input-side short-circuit switch 370.

[0217] [First Modification Example] In the above-described seventh embodiment, the input-side short-circuit switch 370 composed of the nMOS transistor 371 and the pMOS transistor 372 was arranged for each column. However, in this configuration, the number of transistors increases compared to the case where the input-side short-circuit switch 370 is realized by one transistor. The solid-state imaging device 200 according to the first modification of the seventh embodiment is different from the seventh embodiment in that the input-side short-circuit switch 370 is composed only of the nMOS transistor 371.

[0218] FIG. 30 is a circuit diagram showing a configuration example of the comparator 300 in the first modification of the seventh embodiment of the present technology. The comparator 300 according to the first modification of the seventh embodiment is different from the first embodiment in that the input-side short-circuit switch 370 composed only of the nMOS transistor 371 is arranged. The waveform of the control signal PAC1 for controlling the nMOS transistor 371 is the same as that in the seventh embodiment.

[0219] As described above, according to the first modification of the seventh embodiment of the present technology, since the input-side short-circuit switch 370 composed only of the nMOS transistor 371 is used, the number of transistors can be reduced compared to the case where a pair of transistors is used.

[0220] [Second Modification Example] In the above-described seventh embodiment, the input-side short-circuit switch 370 composed of the nMOS transistor 371 and the pMOS transistor 372 was arranged for each column. However, in this configuration, the number of transistors increases compared to the case where the input-side short-circuit switch 370 is realized by one transistor. The solid-state imaging device 200 according to the second modification of the seventh embodiment is different from the first embodiment in that the input-side short-circuit switch 370 is composed only of the pMOS transistor 372.

[0221] FIG. 31 is a circuit diagram showing a configuration example of a comparator 300 in a second modification of the seventh embodiment of the present technology. The comparator 300 in the second modification of the seventh embodiment is different from the seventh embodiment in that an input-side short-circuit switch 370 composed only of a pMOS transistor 372 is arranged. The waveform of the control signal XPAC1 for controlling the pMOS transistor 372 is the same as that in the seventh embodiment.

[0222] As described above, according to the second modification of the seventh embodiment of the present technology, since the input-side short-circuit switch 370 composed only of the pMOS transistor 372 is used, the number of transistors can be reduced as compared with the case of using a pair of transistors.

[0223] [Third Modification] In the above-described seventh embodiment, two-stage transistors of the input transistor 312 and the output transistor 317 are arranged, but a third-stage transistor having the same configuration as the output transistor 317 can also be added. The solid-state imaging device 200 in the third modification of the seventh embodiment is different from the seventh embodiment in that a third-stage transistor is added.

[0224] FIG. 32 is a block diagram showing a configuration example of a comparator 300 in a third modification of the seventh embodiment of the present technology. The comparator 300 in the third modification of the seventh embodiment includes a comparison circuit 310, and inverters 340 and 350.

[0225] FIG. 33 is a circuit diagram showing a configuration example of a comparison circuit 310 in a third modification of the seventh embodiment of the present technology. This comparison circuit 310 includes, in the first stage, an input capacitor 311, an input transistor 312, an auto-zero transistor 313, an input-side short-circuit switch 370, a current source 314, a band-limiting capacitor 315, and a clamp transistor 316. The comparison circuit 310 further includes, in the second stage, an output transistor 317, a current source 318, and a clamp transistor 319. The comparison circuit 310 includes, in the third stage, an output transistor 320, a current source 321, a clamp transistor 322, and an output-side short-circuit switch 360.

[0226] The circuit configurations of the first and second stages in FIG. 33 are the same as those illustrated in FIG. 31. The circuit configuration of the third stage in FIG. 33 is the same as that obtained by adding an output-side short-circuit switch 360 to the third stage in FIG. 23. The output-side short-circuit switch 360 opens and closes the path between the source (vertical signal line 259) and the drain of the output transistor 320 according to the control signal XPAC3. The waveform of the control signal XPAC3 is the same as that of the control signal XPAC1. Note that the output-side short-circuit switch 360 can be realized by only nMOS transistors, only pMOS transistors, or both of them.

[0227] Although the comparison circuit 310 has three stages, it can have four or more stages. In this case, short-circuit switches can be provided in odd-numbered stages.

[0228] As described above, according to the third modification of the seventh embodiment of the present technology, since the output-side short-circuit switch 360 short-circuits the source and the drain of the output transistor 317, the speed at which the comparison result CMP3 transitions to the potential (high level) of the source can be increased. Thereby, the responsiveness can be further improved.

[0229] [Fourth Modification] In the above-described seventh embodiment, the comparison result CMP2 was input to the inverter 340. However, if the voltage range is narrow, there is a risk of malfunction or leakage current in the inverter 340. The solid-state imaging device 200 according to the fourth modification of the seventh embodiment is different from the seventh embodiment in that a level shift circuit for expanding the voltage range is added.

[0230] FIG. 34 is a block diagram showing a configuration example of the comparator 300 in the fourth modification of the seventh embodiment of the present technology. The comparator 300 according to the third modification of the seventh embodiment includes a comparison circuit 310, a level shift circuit 380, and an inverter 340. The configuration of the comparison circuit 310 is the same as that illustrated in FIG. 33. The circuit configuration of the level shift circuit 380 is the same as that illustrated in FIG. 26.

[0231] FIG. 35 is a timing chart showing an example of the operation of the solid-state imaging device 200 in the fourth modification of the seventh embodiment of the present technology.

[0232] The waveforms of the control signals AZSW and XPAC1 are the same as those illustrated in FIG. 29. The timing control unit 220 sets the control signal XPAC3 to the low level for a period until the control signal XPAC1 becomes high level immediately after the timing T1. As a result, the output-side short-circuit switch 360 is in the closed state.

[0233] The timing control unit 220 sets the control signal XPAC3 to the high level at the timing when the control signal XPAC1 becomes high level immediately after the timing T1. As a result, the output-side short-circuit switch 360 is in the open state. Also, at the timing T5, the timing control unit 220 sets the control signal XPAC1 to the low level for a predetermined pulse period.

[0234] The waveform of the first-stage comparison result CMP1 is the same as that illustrated in FIG. 29. The second-stage comparison result CMP2 is at the auto-zero potential V until the period up to the timing T3. AZ The waveform of the comparison result CMP2 after the timing T3 is the same as that illustrated in FIG. 29.

[0235] The waveforms of the control signals PreChg1 and PreChg2 are the same as those illustrated in FIG. 27. The waveform of the output signal VCO is the same as that illustrated in FIG. 29.

[0236] Thus, according to the fourth modification of the seventh embodiment of the present technology, since the level shift circuit 380 outputs either one of a pair of potentials having a larger potential difference than the input potential V VSL and the clamp potential V CLP the voltage range on the input side of the inverter 340 can be expanded.

[0237] <8. Eighth Embodiment> In the above-described third embodiment, the source and the drain of the output transistor 317 are short-circuited by the output-side short-circuit switch 360. However, in this configuration, there is a possibility that the input potential V VSL varies during setting. A configuration in which the clamp transistor 319, the inverters 340 and 350 are reduced from the circuit of the third embodiment illustrated in FIG. 21 is used as a comparative example.

[0238] FIG. 36 is a circuit diagram showing a configuration example of the comparator 300 in the comparative example. The parasitic capacitance of the output node of the comparison result CMP1 in the first stage is 402, and the parasitic capacitance of the output node of the comparison result CMP2 in the second stage is 403.

[0239] FIG. 37 is a timing chart showing an example of the operation of the solid-state imaging device 200 in the comparative example. First, during the auto-zero period from timing T0 to T1, the DAC 230 sets the reference potential V RMP to the neutral auto-zero potential V AZ . After that, after the reference potential V RMP rises once at the POF edge of timing T1, the reference potential V RMPIt becomes a P-phase slope period that gradually decreases. Raising it once at the POF edge is to ensure that the inversion operation occurs reliably in the slope part by swinging it in the reverse direction. The count value is counted over the period until the output signal VCO when the pixel circuit 250 is reset within this P-phase slope period is inverted.

[0240] After that, according to the signal charge amount transferred by the transfer transistor 252, the input potential V VSL decreases, and then the reference potential V RMP rises once at the timing T5 of the POF edge and then becomes a D-phase slope period that gradually decreases. The count value is counted over the period until the output signal VCO when the signal charge is transferred within this D-phase slope period is inverted. By the CDS process, subtracting the count value of the P-phase slope period from the count value of the D-phase slope period, the net amount of signal charge can be obtained as a digital value. In the figure, the amount of signal charge is 0 and the input potential V VSL is in a state where it has not decreased.

[0241] In this circuit operation, when the reference potential V RMP rises at the POF edge or the DOF edge, the first-stage comparison result CMP1 starts to fall and stops falling when the clamp transistor 316 transitions to the on state. To accelerate the fall of this first-stage comparison result CMP1, the timing control unit 220 turns off (opens) the cutoff switch 330 from the timings T1 and T5 for a short period by the control signal XPAC1.

[0242] On the other hand, the second-stage output-side short-circuit switch 360 becomes on when the reference potential V RMP is at the potential during auto-zero and fixes the second-stage comparison result CMP2 to the input potential V VSL This is because if the second-stage amplifier is enabled in the neutral state, the circuit may oscillate depending on the conditions.

[0243] In the circuit of this comparative example, starting from the POF edge and the DOF edge, the potential of the vertical signal line 259 (input potential V VSL) A problem occurs when a potential fluctuation (kickback) occurs. In order for the deviation of the input potential V due to kickback to settle and then transition to the slope period, it is necessary to lengthen the settling periods (timings T1 to T2 and timings T5 to T6) immediately before the slope periods of the P phase and D phase. This results in an increase in the AD conversion time, leading to a decrease in the frame rate and an increase in the average power consumption. Also, if the settling of the kickback is insufficient, the count values within the slope periods of the P phase and D phase will deviate due to the settling error, but due to mismatches between the P phase and D phase and between columns, a settling error beyond a certain level cannot be completely removed by CDS. As a result, image quality degradation such as offset and vertical streaks occurs. VSL Since the deviation of the input potential V due to kickback settles and then transitions to the slope period, it is necessary to lengthen the settling periods (timings T1 to T2 and timings T5 to T6) immediately before the slope periods of the P phase and D phase. This results in an increase in the AD conversion time, leading to a decrease in the frame rate and an increase in the average power consumption. Also, if the settling of the kickback is insufficient, the count values within the slope periods of the P phase and D phase will deviate due to the settling error, but due to mismatches between the P phase and D phase and between columns, a settling error beyond a certain level cannot be completely removed by CDS. As a result, image quality degradation such as offset and vertical streaks occurs.

[0244] The cause of the above-mentioned kickback is as follows. First, when the potential of the first-stage comparison result CMP1 drops due to a POF edge or a DOF edge, the parasitic capacitance (401 in FIG. 36) of the first stage is discharged. Since a part of the current drawn by the first-stage current source 314 is used for this discharge, the current drawn from the vertical signal line 259 decreases for a short period. At this time, since a part of the charge that continues to flow from the pixel side loses its path and charges the parasitic capacitance of the vertical signal line 259, the potential (V VSL ) of the vertical signal line 259 temporarily rises (that is, kickback occurs).

[0245] FIG. 38 is a circuit diagram showing a configuration example of the comparator 300 in the eighth embodiment of the present technology. In order to suppress kickback, in the eighth embodiment, a cutoff switch 410, a control switch 420, and a clamp transistor 430 are added.

[0246] The cutoff switch 410 is inserted between the output transistor 317 and the current source 318. This cutoff switch 410 shifts between an open state and a closed state according to the control signals XPAC2A and PAC2A from the timing control unit 220. The cutoff switch 410 includes, for example, an nMOS transistor 411 and a pMOS transistor 412 connected in parallel between the output transistor 317 and the current source 318. The control signal XPAC2A is input to the gate of the nMOS transistor 411, and the control signal PAC2A is input to the gate of the pMOS transistor 412. Note that the cutoff switch 410 may include only one of the nMOS transistor 411 and the pMOS transistor 412.

[0247] The clamp transistor 430 is of P type, with its gate and drain connected to the current source 318 and its source connected to the control switch 420. The control switch 420 is inserted between the source of the output transistor 317 and the source of the clamp transistor 430. This control switch 420 shifts between an open state and a closed state according to the control signal XPAC2. Also, the control switch 420 includes, for example, a pMOS transistor 422. Note that the control switch 420 may include an nMOS transistor instead of the pMOS transistor 422, or may include both the nMOS transistor 422 and the pMOS transistor.

[0248] Note that the cutoff switch 330 is an example of the first cutoff switch described in the claims, and the cutoff switch 410 is an example of the second cutoff switch described in the claims. The current source 314 is an example of the first current source described in the claims, and the current source 318 is an example of the second current source described in the claims.

[0249] FIG. 39 is a timing chart showing an example of the operation of the solid-state imaging device 200 in the eighth embodiment of the present technology. In order to suppress kickback, in the eighth embodiment, the reference potential V RMPBefore the settling period, the second comparison result CMP2 is lowered. Further, when the first comparison result CMP1 drops at the POF edge and the DOF edge, the second comparison result CMP2 rises simultaneously.

[0250] The cutoff switch 410 and the control switch 420 operate exclusively so that either one of them is in the on state. Before the settling period (such as timing T1 to T2), when the control switch 420 side is in the on state, the current of the second current source 318 flows to the second clamp transistor 430. Then, the potential of the second comparison result CMP2 settles at a level that has dropped by the gate-source voltage of the clamp transistor 430 from the input potential V VSL During the settling period and the subsequent slope period, when the cutoff switch 410 side is in the on state, the current of the second current source 318 flows to the second input side, and the potential of the second comparison result CMP2 becomes the output of the inverting amplifier according to the first comparison result CMP1. Since the potential of the first comparison result CMP1 drops during the settling period, the second comparison result CMP1 will rise.

[0251] As a result, at the POF edge and the DOF edge, the first parasitic capacitance 401 is discharged and the second parasitic capacitance 402 is charged simultaneously, and the change in the current drawn from the vertical signal line 259 is suppressed by the cancellation of these charging and discharging currents. As a result, the occurrence of kickback can be suppressed. At this time, by adjusting the size of the second clamp transistor 430, the potential when lowering the potential of the second comparison result CMP2 can be adjusted, so it can be designed so that the cancellation effect is maximized.

[0252] By suppressing the kickback, the settling period of the ramp signals of the P phase and the D phase can be shortened. As a result, an increase in the AD conversion time can be avoided, and a decrease in the frame rate and an increase in the average power consumption can be suppressed.

[0253] In addition, as illustrated in FIG. 40, N-type clamp transistors 441 and 442 can be further added. Clamp transistor 441 is connected in parallel with P-type clamp transistor 316. Clamp transistor 442 is connected in parallel with control switch 420 and clamp transistor 430.

[0254] The first-stage clamp transistor 441 is provided to prevent the drain potential of the first-stage current source 314 from dropping too much and changing the current value when the input potential V drops below the dynamic range due to an excessive input. Similarly, the second-stage clamp transistor 442 serves to protect the second-stage current source 318. This is provided because after the second-stage comparison result CMP2 is inverted, the potential drops and the transistor of the current source 318 does not shift to the linear region. VSL As described above, according to the eighth embodiment of the present technology, since the cutoff switch 410, the control switch 420, and the clamp transistor 430 are added, kickback can be suppressed.

[0255] In the above eighth embodiment, the output transistor 317 outputs the comparison result CMP2. However, if the voltage range is narrow, there is a risk of malfunction or leakage current in the subsequent logic gate (such as an inverter). The solid-state imaging device 200 according to the first modification of the eighth embodiment is different from the third embodiment in that a level shift circuit for expanding the voltage range is added.

[0256] [First Modification Example] In the above-described eighth embodiment, the output transistor 317 outputs the comparison result CMP2. However, if the voltage range is narrow, there is a risk of malfunction or leakage current in the subsequent logic gate (such as an inverter). The solid-state imaging device 200 according to the first modification of the eighth embodiment is different from the third embodiment in that a level shift circuit for expanding the voltage range is added.

[0257] FIG. 41 is a circuit diagram showing a configuration example of a comparator 300 in a first modification of the eighth embodiment of the present technology. The comparator 300 in the first modification of the eighth embodiment differs from the eighth embodiment in that it further includes a level shift circuit 380 and a NAND gate 450. The circuit configuration of the level shift circuit 380 is the same as the circuit illustrated in FIG. 26. The NAND gate 450 outputs the negative logical product of the output signal pOUT of the level shift circuit 380 and the enable signal EN as the output signal VCO. Note that the NAND gate 450 is an example of the logic gate described in the claims.

[0258] However, in FIG. 41, the node connected to the source of the third-stage nMOS transistor 382 is not the node of the second-stage comparison result CMP2, but the connection node of the control switch 420 and the clamp transistor 430. The output of this connection node is designated as CMP2'. Connecting in this way is because if the source is connected to the node of the comparison result CMP2, the potential difference between the gate and source of the nMOS transistor 382 in FIG. 26 will open and turn on due to the potential of the comparison result CMP2 being lowered before the setting period of the lamp signal.

[0259] This setting period is the period during which the third-stage precharge transistor 381 illustrated in FIG. 26 is in the on state. Therefore, a through current flows in the third stage, resulting in malfunction. By connecting the connection node of the control switch 420 and the clamp transistor 430 to the source of the nMOS transistor 382, the third-stage nMOS transistor 382 can be correctly turned off before the setting period.

[0260] Note that N-type clamp transistors 441 and 442 can also be further added.

[0261] FIG. 42 is a timing chart showing an example of the operation of the solid-state imaging device in the first modification of the eighth embodiment of the present technology. The thick dashed line in the figure indicates the variation of the output CMP2' of the connection node of the control switch 420 and the clamp transistor 430. The enable signal EN is controlled to a low level (disabled) until the end of the setting period (timings T2 and T6), and is controlled to a high level (enabled) from the end of the setting period to the end of the slope period. As illustrated in the figure, kickback is suppressed.

[0262] Thus, according to the first modification of the eighth embodiment of the present technology, since the level shift circuit 380 outputs either one of a pair of potentials having a larger potential difference than the input potential V VSL and the clamp potential V CLP , the voltage range on the input side can be expanded.

[0263] [Second Modification] In the first modification of the above-described eighth embodiment, one input capacitor 311 was inserted between the DAC 230 and the gate of the input transistor 312. However, in this configuration, noise may not be sufficiently attenuated. The comparator 300 of the second modification of the eighth embodiment is different from the first modification of the eighth embodiment in that an input capacitor switching circuit 470 is added.

[0264] FIG. 43 is a circuit diagram showing a configuration example of the comparator 300 in the second modification of the eighth embodiment of the present technology. The comparator 300 of the second modification of the eighth embodiment is different from the first modification of the eighth embodiment in that it further includes a buffer 460 and an input capacitor switching circuit 470. The buffer 460 is inserted between the DAC 230 and the input capacitor switching circuit 470.

[0265] FIG. 44 is a circuit diagram showing a configuration example of the input capacitor switching circuit 470 in the second modification of the eighth embodiment of the present technology. This input capacitor switching circuit 470 includes input capacitors 471 to 474 and switches 475 to 478.

[0266] One end of each of the input capacitances 471 to 474 is commonly connected to the gate of the input transistor 312. The other end of the input capacitance 471 is connected to the output terminal of the buffer 460. The switch 475 opens and closes the path between the other end of the input capacitance 471 and the other end of the input capacitance 474 according to the control of the timing control unit 220. The switch 476 opens and closes the path between the other end of the input capacitance 472 and the other end of the input capacitance 473 according to the control of the timing control unit 220. The switch 477 opens and closes the path between the other end of the input capacitance 473 and the other end of the input capacitance 474 according to the control of the timing control unit 220. The switch 478 opens and closes the path between the other end of the input capacitance 474 and the ground potential according to the control of the timing control unit 220.

[0267] With the circuit illustrated in the figure, the input capacitance switching circuit 470 can switch the number of input capacitances connected in parallel to the gate of the input transistor 312 to any one of 1 to 4. Thereby, the noise of the buffer 460 of the lamp signal and the noise riding on the column common lamp signal can be reduced. In this case, it is desirable to make the slope of the lamp signal larger by the amount attenuated by the capacitive voltage division.

[0268] Note that the number of input capacitances is not limited to four. When the number of input capacitances is M (M is an integer), M - 1 switches are provided. Also, the input capacitance switching circuit 470 can be added to the circuit of FIG. 38 in which the level shift circuit 380 is not provided. Also, N-type clamp transistors 441 and 442 can be further added.

[0269] As described above, according to the second modification of the eighth embodiment of the present technology, since the input capacitance switching circuit 470 is added, noise can be further reduced.

[0270] <9. Application Example to a Moving Body> The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0271] FIG. 45 is a block diagram showing a schematic configuration example of a vehicle control system which is an example of a movement control system to which the technology according to the present disclosure can be applied.

[0272] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 45, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

[0273] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device such as a driving force generation device for generating a driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0274] The body control unit 12020 controls the operations of various devices equipped on the vehicle according to various programs. For example, the body control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as a headlamp, a backlamp, a brake lamp, a turn signal, or a fog lamp. In this case, radio waves transmitted from a portable device that substitutes for a key or signals from various switches can be input to the body control unit 12020. The body control unit 12020 receives these inputs of radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0275] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing on objects such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.

[0276] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. Also, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared light.

[0277] The vehicle interior information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the vehicle interior information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the vehicle interior information detection unit 12040 may calculate the degree of driver fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0278] Based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate the control target values of the driving force generation device, the steering mechanism, or the braking device, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of the vehicle, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, collision warning of the vehicle, or lane departure warning of the vehicle, etc.

[0279] In addition, based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can perform cooperative control aimed at autonomous driving, etc., which runs autonomously without relying on the driver's operation, by controlling the driving force generation device, the steering mechanism, or the braking device, etc.

[0280] Also, based on the exterior information of the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control aimed at anti-glare, such as controlling the headlamp according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030 and switching the high beam to the low beam.

[0281] The audio-visual output unit 12052 transmits at least one output signal of audio and image to an output device capable of notifying information visually or auditorily to the vehicle occupants or outside the vehicle. In the example of FIG. 45, the output devices are exemplified by the audio speaker 12061, the display unit 12062, and the instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0282] FIG. 46 is a diagram showing an example of the installation position of the imaging unit 12031.

[0283] In FIG. 46, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0284] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirror, rear bumper, back door, and the upper part of the windshield inside the vehicle compartment of the vehicle 12100, for example. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle compartment mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images on the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or the back door mainly acquires images behind the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle compartment is mainly used for detecting a preceding vehicle or detecting pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0285] Note that FIG. 46 shows an example of the imaging ranges of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose, the imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the back door. For example, by overlapping the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 seen from above can be obtained.

[0286] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0287] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100). In particular, it can extract, as the leading vehicle, the three-dimensional object that is closest to the traveling path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more). Further, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the leading vehicle and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Thus, cooperative control for the purpose of autonomous driving, etc., which runs autonomously without relying on the driver's operation, can be performed.

[0288] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into motorcycles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and can use it for automatic avoidance of obstacles. For example, the microcomputer 12051 discriminates between obstacles around the vehicle 12100 as obstacles visible to the driver of the vehicle 12100 and obstacles difficult to visually recognize. Then, the microcomputer 12051 determines the collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, it outputs an alarm to the driver via the audio speaker 12061 or the display unit 12062, or performs forced deceleration or avoidance steering via the drive system control unit 12010, thereby providing driving assistance for collision avoidance.

[0289] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. Such recognition of a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 to superimpose and display a rectangular outline for emphasizing the recognized pedestrian. Further, the audio-visual output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0290] As described above, an example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. Specifically, the imaging device 100 in FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, the responsiveness of the comparator 300 can be improved, the frame rate can be increased, and a more viewable video can be obtained, so that the driver's fatigue can be reduced.

[0291] Note that the above-described embodiments show examples for embodying the present technology, and there is a corresponding relationship between the matters in the embodiments and the invention-specific matters in the claims. Similarly, there is a corresponding relationship between the invention-specific matters in the claims and the matters in the embodiments of the present technology having the same name. However, the present technology is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from the gist thereof.

[0292] Note that the effects described in this specification are merely illustrative and not limiting, and there may be other effects.

[0293] Note that the present technology can also be configured as follows. (1) An input transistor that outputs a potential within a range from one of a pair of output potentials to the other based on whether an input potential input to the source substantially matches a predetermined reference potential input to the gate, from the drain; A first current source that supplies a constant current; A capacitor inserted between the source of the input transistor and the first current source; A first cutoff switch that disconnects the drain of the input transistor from the connection node during a predetermined period for initializing the connection node of the capacitor and the first current source to the lower of the pair of output potentials, and connects the connection node and the drain of the input transistor outside the predetermined period A solid-state imaging device comprising the same. (2) The first cutoff switch includes an N-type transistor and a P-type transistor connected in parallel between the drain of the input transistor and the first current source. The solid-state imaging device according to (1) above. (3) The first cutoff switch includes an N-type transistor. The solid-state imaging device according to (1) above. (4) The first cutoff switch includes a P-type transistor. The solid-state imaging device according to (1) above. (5) A first output transistor that outputs a potential within a range from a predetermined potential lower than the input potential to the input potential based on whether a difference between the input potential input to the source and the potential of the connection node input to the gate exceeds a predetermined threshold voltage, from the drain; An output-side short-circuit switch that short-circuits the source and the drain of the first output transistor during the predetermined period The solid-state imaging device according to any one of (1) to (4) above, further comprising the same. (6) Further comprising an auto-zero transistor that connects the gate and drain of the input transistor during an auto-zero period before the predetermined period. The output-side short-circuit switch shorts the source and drain of the first output transistor during the auto-zero period and during the predetermined period. The solid-state imaging device according to (5) above. (7) The output-side short-circuit switch includes an N-type transistor and a P-type transistor connected in parallel between the source and drain of the first output transistor. The solid-state imaging device according to (5) above. (8) The output-side short-circuit switch includes an N-type transistor. The solid-state imaging device according to (5) above. (9) Further comprising a second output transistor that outputs a voltage within the range from the predetermined potential to the input potential from the drain based on whether the difference between the input potential input to the source and the drain of the first output transistor input to the gate exceeds a predetermined threshold voltage. The solid-state imaging device according to any one of (5) to (8) above. (10) Further comprising an input-side short-circuit switch that shorts the drain and source of the input transistor during the predetermined period. The solid-state imaging device according to any one of (5) to (9) above. (11) A level shift circuit that outputs output signals of a pair of shift potentials having a larger potential difference than the predetermined potential and the input potential based on the potential of the drain of the first output transistor, A logic gate that determines whether the output signal is higher than a predetermined threshold between the pair of shift potentials and outputs a determination result. And further comprising The solid-state imaging device according to any one of (5) to (10) above. (12) One of the pair of shift potentials is a power supply potential higher than the input potential, and the other is a reference potential lower than the predetermined potential. The level shift circuit is an N-type transistor having a gate connected to the vertical signal line of the input potential and a source connected to the drain of the first output transistor; a power-side precharge transistor for initializing the potential of the drain of the N-type transistor to the power supply potential; a P-type transistor having a gate connected to the drain of the N-type transistor and a drain connected to the logic gate; a reference-side precharge transistor for initializing the potential of the drain of the P-type transistor to the reference potential; The solid-state imaging device according to (11) above, comprising: (13) a first output transistor that outputs a potential within a range from a predetermined potential lower than the input potential to the input potential based on whether a difference between the input potential input to the source and the potential of the connection node input to the gate exceeds a predetermined threshold voltage; a second current source that supplies a constant current; a second cutoff switch that disconnects the drain of the first output transistor from the second current source before the start timing of setting the reference potential and connects the drain of the first output transistor and the second current source for a certain period from the start timing; a clamp transistor having a drain connected to the second current source; a control switch that connects the source of the first output transistor and the source of the clamp transistor before the start timing and disconnects the source of the first output transistor from the source of the clamp transistor for a certain period from the start timing; The solid-state imaging device according to (1) above, further comprising: (14) The solid-state imaging device according to (13) above, further comprising a level shift circuit that outputs an output signal of a pair of shift potentials having a larger potential difference than the predetermined potential and the input potential based on the potential of the connection node of the control switch and the clamp transistor. The solid-state imaging device according to (13) or (14) above, further comprising an input capacitance switching circuit that switches the number of input capacitances connected in parallel to the gate of the input transistor. (16) An input transistor that outputs a drain potential corresponding to the input potential from the drain when the input potential input to the source and a predetermined reference potential input to the gate substantially match, A first output transistor that outputs a potential within a range from a predetermined potential to the input potential from the drain based on whether or not a difference between the input potential input to the source and the drain potential input to the gate exceeds a predetermined threshold voltage, An output-side short-circuit switch that short-circuits the source and the drain of the first output transistor within a predetermined period for initializing the drain to the input potential, A solid-state imaging device comprising the same. (17) An input transistor that outputs a predetermined clamp potential from the drain when the input potential input to the source and a predetermined reference potential input to the gate substantially match, An input-side short-circuit switch that short-circuits the source and the drain of the input transistor within a predetermined period for initializing the potential of the drain to the input potential, A solid-state imaging device comprising the same. (18) An input transistor that outputs a potential within a range from one of a pair of output potentials to the other from the drain based on whether or not the input potential input to the source and a predetermined reference potential input to the gate substantially match, A current source that supplies a predetermined constant current, A capacitance inserted between the source of the input transistor and the current source, A cutoff switch that disconnects the drain of the input transistor from the connection node within a predetermined period for initializing the connection node of the capacitance and the current source to the lower of the pair of output potentials, and connects the connection node and the drain of the input transistor outside the predetermined period, A counter that counts a count value over a period until the potential of the connection node is inverted, An imaging device comprising the same. (19) A vertical signal line connected to a pixel, a transistor including a source connected to the vertical signal line and a gate receiving a signal based on a predetermined reference potential, a current source supplying a constant current, a capacitor inserted between the source of the transistor and the current source, and a switch connected between a connection node of the capacitor and the current source and the drain of the transistor A solid-state imaging device comprising the same. (20) A vertical signal line connected to a pixel, a first transistor including a source connected to the vertical signal line and a gate receiving a signal based on a predetermined reference potential, a current source supplying a constant current, a second transistor including a source connected to the vertical signal line and a gate connected to the current source, and a switch connected between the source and the drain of the second transistor A solid-state imaging device comprising the same. [Description of Reference Numerals]

[0294] 100 Imaging device 110 Optical unit 120 DSP circuit 130 Display unit 140 Operation unit 150 Bus 160 Frame memory 170 Storage unit 180 Power supply unit 200 Solid-state imaging device 201 Light-receiving chip 202 Circuit chip 210 Vertical scanning circuit 220 Timing control unit 230 DAC 240 Pixel array unit 250 Pixel circuit 251 Photoelectric conversion element 252 Transfer transistor 253 Reset transistor 254 Floating diffusion layer 255 Amplification transistor 256 Selection transistor 260 Column signal processing unit 261 Counter 262 Latch 270 Horizontal scanning circuit 300 Comparator 310 Comparison circuit 311, 471~474 Input capacitance 312 Input transistor 313 Auto-zero transistor 314, 318, 321 Current source 315 Band-limiting capacitance 316, 319, 322, 430, 441, 442 Clamp transistor 317, 320 Output transistor 330, 410 Cutoff switch 331, 342, 352, 361, 371, 382, 411 nMOS transistor 332, 341, 351, 362, 372, 384, 412, 422 pMOS transistor 340, �50 Inverter 360 Output-side short-circuit switch 370 Input-side short-circuit switch 380 Level shift circuit 381, 385 Precharge transistor 383, 386, 401, 402 Parasitic capacitance 420 Control switch 450 NAND gate 460 Buffer 470 Input capacitance switching circuit 475~478 Switch 12031 Imaging unit

Claims

1. An input transistor that outputs a potential within a range from one of a pair of output potentials to the other from a drain based on whether an input potential input to a source substantially matches a predetermined reference potential input to a gate; A first current source that supplies a constant current; A capacitor inserted between the source of the input transistor and the first current source; A first cutoff switch that disconnects the drain of the input transistor from the connection node during a predetermined period for initializing the connection node of the capacitor and the first current source to the lower one of the pair of output potentials, and connects the connection node and the drain of the input transistor outside the predetermined period; A first clamp transistor inserted between the source of the input transistor and the connection node of the capacitor and the first current source Comprising; One of the pair of output potentials is the input potential, and the other of the pair of output potentials is a clamp potential that is lower than the input potential by the drain-source voltage of the first clamp transistor. Solid-state imaging device.

2. The first cutoff switch includes an N-type transistor and a P-type transistor connected in parallel between the drain of the input transistor and the first current source. The solid-state imaging device according to Claim 1.

3. The first cutoff switch includes an N-type transistor. The solid-state imaging device according to Claim 1.

4. The first cutoff switch includes a P-type transistor. The solid-state imaging device according to Claim 1.

5. A first output transistor that outputs a potential within a range from a predetermined potential lower than the input potential to the input potential from a drain based on whether a difference between the input potential input to the source and the potential of the connection node input to the gate exceeds a predetermined threshold voltage; An output-side short-circuit switch that short-circuits the source and the drain of the first output transistor during the predetermined period. The solid-state imaging device according to Claim 1, further comprising.

6. Further comprising an auto-zero transistor that connects the gate and the drain of the input transistor during an auto-zero period before the predetermined period; The output-side short-circuit switch short-circuits the source and the drain of the first output transistor during the auto-zero period and the predetermined period. The solid-state imaging device according to Claim 5.

7. The output-side short-circuit switch includes an N-type transistor and a P-type transistor connected in parallel between the source and the drain of the first output transistor. The solid-state imaging device according to claim 5.

8. The output-side short-circuit switch includes an N-type transistor. The solid-state imaging device according to claim 5.

9. Further comprising a second output transistor that outputs a voltage within a range from the predetermined potential to the input potential from the drain based on whether a difference between the input potential input to the source and the drain of the first output transistor input to the gate exceeds a predetermined threshold voltage. The solid-state imaging device according to claim 5.

10. Further comprising an input-side short-circuit switch that short-circuits the drain and the source of the input transistor within the predetermined period. The solid-state imaging device according to claim 5.

11. A level shift circuit that outputs output signals of a pair of shift potentials having a larger potential difference than the predetermined potential and the input potential based on the potential of the drain of the first output transistor; A logic gate that determines whether the output signal is higher than a predetermined threshold between the pair of shift potentials and outputs a determination result; Further comprising: One of the pair of shift potentials is a power supply potential higher than the input potential, and the other of the pair of shift potentials is a reference potential lower than the predetermined potential. The solid-state imaging device according to claim 5.

12. The level shift circuit includes: An N-type transistor having a gate connected to the vertical signal line of the input potential and a source connected to the drain of the first output transistor; A power supply-side precharge transistor that initializes the potential of the drain of the N-type transistor to the power supply potential; A P-type transistor having a gate connected to the drain of the N-type transistor and a drain connected to the logic gate; A reference-side precharge transistor that initializes the potential of the drain of the P-type transistor to the reference potential. The solid-state imaging device according to claim 11, comprising:

13. A first output transistor that outputs a potential within a range from a predetermined potential lower than the input potential to the input potential from the drain based on whether a difference between the input potential input to the source and the potential of the connection node input to the gate exceeds a predetermined threshold voltage; A second current source that supplies a constant current. Before the start timing of setting the reference potential, disconnect the drain of the first output transistor from the second current source, and a second cutoff switch that connects the drain of the first output transistor and the second current source for a certain period from the start timing. A second clamp transistor having its drain connected to the second current source. A control switch that connects the source of the first output transistor and the source of the second clamp transistor before the start timing, and disconnects the source of the first output transistor from the source of the second clamp transistor for a certain period from the start timing. The solid-state imaging device according to claim 1, further comprising the above.

14. The solid-state imaging device further comprises a level shift circuit that outputs an output signal of a pair of shift potentials having a larger potential difference than the predetermined potential and the input potential based on the potential of the connection node between the control switch and the second clamp transistor. One of the pair of shift potentials is a power supply potential higher than the input potential, and the other of the pair of shift potentials is a reference potential lower than the predetermined potential. The solid-state imaging device according to claim 13.

15. The solid-state imaging device according to claim 13, further comprising an input capacitance switching circuit that switches the number of input capacitances connected in parallel to the gate of the input transistor.

16. An input transistor that outputs a drain potential corresponding to the input potential when the input potential input to the source and the predetermined reference potential input to the gate substantially coincide, A first output transistor that outputs a potential within the range from the predetermined potential to the input potential based on whether or not the difference between the input potential input to the source and the drain potential input to the gate exceeds a predetermined threshold voltage. An output-side short-circuit switch that short-circuits the source and the drain of the first output transistor within a predetermined period for initializing the drain of the first output transistor to the input potential. A solid-state imaging device comprising the above.

17. An input transistor that outputs a predetermined clamp potential from the drain when the input potential input to the source and the predetermined reference potential input to the gate substantially coincide, An input-side short-circuit switch that short-circuits the source and the drain of the input transistor within a predetermined period for initializing the potential of the drain to a high level higher than the clamp potential. A clamp transistor inserted between the drain and source of the input transistor and comprising the solid-state imaging device, wherein the clamp potential is a potential lower than the input potential by the drain-source voltage of the clamp transistor solid-state imaging device.

18. An input transistor that outputs a potential within a range from one of a pair of output potentials to the other based on whether an input potential input to the source substantially matches a predetermined reference potential input to the gate, from the drain; a current source that supplies a predetermined constant current; a capacitor inserted between the source of the input transistor and the current source; a cutoff switch that disconnects the drain of the input transistor from the connection node for a predetermined period to initialize the connection node of the capacitor and the current source to the lower of the pair of output potentials, and connects the connection node and the drain of the input transistor outside the predetermined period; a first clamp transistor inserted between the source of the input transistor and the connection node of the capacitor and the current source; a counter that counts a count value over a period until the potential of the connection node reverses comprising wherein one of the pair of output potentials is the same potential as the input potential, and the other of the pair of output potentials is a clamp potential lower than the input potential by the drain-source voltage of the first clamp transistor imaging device.

19. a vertical signal line connected to a pixel; a transistor comprising a source connected to the vertical signal line and a gate that receives a signal based on a predetermined reference potential; a current source that supplies a constant current; a capacitor inserted between the source of the transistor and the current source; a solid-state imaging device comprising a switch connected to the connection node of the capacitor and the current source and the drain of the transistor

20. a vertical signal line connected to a pixel; a first transistor comprising a source connected to the vertical signal line and a gate that receives a signal based on a predetermined reference potential; a current source that supplies a constant current; a second transistor comprising a source connected to the vertical signal line and a gate connected to the current source; a solid-state imaging device comprising a switch connected between the source and drain of the second transistor

27. ​

Images