Signal processing apparatus and signal processing method

Abstract

This signal processing device comprises: a control unit that divides buffer data into a plurality of pieces of divided buffer data; a plurality of filter coefficient updating units that execute, in parallel on the plurality of pieces of divided buffer data, a filter coefficient updating process for each piece of the divided buffer data included in the plurality of pieces of divided buffer data; and a plurality of filter processing units that execute a filter process on sample data of the divided buffer data on the basis of the filter coefficient for each piece of the divided buffer data. The plurality of filter coefficient updating units may execute, in parallel, the filter coefficient updating process on a portion of the divided buffer data.

Description

Technical Field

[0001] The present invention relates to a signal processing apparatus and a signal processing method.

Background Art

[0002] When a functional unit for transmitting a main signal of an optical access system is software-defined, an adaptive filter that performs polarization separation may be implemented in software in a communication device. FIG. 13 is a diagram showing a configuration example of an adaptive filter. The adaptive filter includes a filter processing unit and a filter coefficient update unit in parallel.

[0003] The filter processing unit performs filter processing on the main signal. The filter in the filter processing is, for example, a finite impulse response (FIR) filter. The filter in the filter processing may be, for example, an infinite impulse response (IIR) filter.

[0004] The filter coefficient update unit updates the filter coefficient “W” to the filter coefficient “W'” based on the result of the filter processing, for example, using a constant modulus algorithm (CMA). The filter coefficient update unit may update the filter coefficient “W” to the filter coefficient “W'” based on the result of the filter processing, for example, using least mean squares (LMS). In the next filter processing to be executed, the filter processing unit performs a convolution operation on the main signal using the filter coefficient “W'”. The filter processing unit outputs the result of the convolution operation to the subsequent stage as the result of the filter processing.

[0005] FIG. 14 is a diagram showing an example of an adaptive filter implemented by software. Filter processing and filter coefficient update are executed offline. That is, the filter coefficient update is not parallelized with respect to the filter processing, and the filter processing and the filter coefficient update are sequentially processed by software in order from the head to the end of the buffered signal data (hereinafter referred to as "buffer data") (see Non-Patent Document 1).

Prior Art Documents

Non-Patent Documents

[0006]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] Even when the characteristics of the input main signal change over time, the adaptive filter can execute filter processing using filter coefficients updated according to the changed characteristics. However, the execution time of filter processing by an adaptive filter implemented by software in a communication device is longer than the execution time of filter processing by an adaptive filter implemented by dedicated hardware in the communication device because the processor sequentially executes the filter processing synchronized with the clock. For this reason, in the filter processing by the adaptive filter implemented by software, a long processing time is required, and there is a problem that the processing throughput cannot be improved.

[0008] In view of the above circumstances, an object of the present invention is to provide a signal processing apparatus and a signal processing method capable of improving processing throughput.

Means for Solving the Problems

[0009] One aspect of the present invention is a signal processing apparatus including a control unit that divides buffer data into a plurality of divided buffer data, a plurality of filter coefficient update units that execute in parallel an update process of a filter coefficient for each of the divided buffer data included in the plurality of divided buffer data, and a plurality of filter processing units that execute a filter process on sample data of the divided buffer data based on the filter coefficient for each of the divided buffer data.

[0010] One aspect of the present invention is a signal processing apparatus including a control unit that divides buffer data into a plurality of first divided buffer data and further divides the first divided buffer data included in the plurality of first divided buffer data into a plurality of second divided buffer data, a plurality of filter coefficient update units that execute in parallel an update process of a filter coefficient for each of the second divided buffer data included in the plurality of second divided buffer data, a representative filter coefficient derivation unit that derives a representative value of the filter coefficient for each of the second divided buffer data, and a plurality of filter processing units that execute a filter process on sample data of the first divided buffer data based on the representative value.

[0011] One aspect of the present invention is a signal processing method executed by the above signal processing apparatus, the method including steps of dividing buffer data into a plurality of divided buffer data, executing in parallel an update process of a filter coefficient for each of the divided buffer data included in the plurality of divided buffer data, and executing a filter process on sample data of the divided buffer data based on the filter coefficient for each of the divided buffer data.

[0012] One aspect of the present invention is a signal processing method executed by the above signal processing apparatus, the method including: dividing buffer data into a plurality of first divided buffer data, and further dividing the first divided buffer data included in the plurality of first divided buffer data into a plurality of second divided buffer data; performing, in parallel for the plurality of second divided buffer data, an update process of filter coefficients for each of the second divided buffer data included in the plurality of second divided buffer data; deriving a representative value of the filter coefficients for each of the second divided buffer data; and performing a filter process on sample data of the first divided buffer data based on the representative value.

Advantages of the Invention

[0013] According to the present invention, it is possible to improve the processing throughput.

Brief Description of the Drawings

[0014]

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Embodiments for Carrying Out the Invention

[0015] Embodiments of the present invention will be described in detail with reference to the drawings. (First Embodiment) FIG. 1 is a diagram showing a configuration example of a signal processing system 1a in the embodiment. The signal processing system 1a is a system that executes predetermined signal processing on a signal subjected to adaptive filter processing. Here, the signal processing system 1a executes adaptive filter processing on a signal. At least a part of the adaptive filter processing may be executed by software.

[0016] The signal processing system 1a is provided, for example, in an optical access system (optical communication system). The signal processing system 1a executes communication processing using, for example, optical phase modulation by a coherent method. The signal processing system 1a may execute communication processing by, for example, an amplitude modulation method.

[0017] The signal processing system 1a includes a signal generation device 2 (opposite communication device) and a signal processing device 3a. In the first embodiment, as an example, the configuration of the network connecting the signal generation device 2 and the signal processing device 3a is a point-to-point configuration. The signal generation device 2 includes a signal generation unit 4. The signal processing device 3a includes a communication unit 5, a memory 6, a control unit 7, a signal processing unit 8a, and a MAC processing unit 9.

[0018] The signal generation unit 4 generates a predetermined signal (for example, an optical signal). The generated signal includes the data of the main signal. The generated signal may further include the data of a sub-signal (for example, a control signal). The signal generation unit 4 transmits the generated signal to the communication unit 5.

[0019] The communication unit 5 acquires the signal transmitted from the signal generation unit 4 from the signal generation unit 4. The communication unit 5 performs communication processing of the optical signal, for example, using optical phase modulation by a coherent method. The communication unit 5 records the acquired signal in the memory 6.

[0020] The memory 6 stores the signal acquired by the communication unit 5 as buffer data. The memory 6 may store a program. The program may be a multi-thread program. The memory 6 may store a plurality of filter coefficients.

[0021] When the length of the buffer data (buffer data length) stored in the memory 6 becomes equal to or greater than a threshold value, the control unit 7 controls the signal processing unit 8a so that the signal processing unit 8a acquires the buffer data.

[0022] The signal processing unit 8a acquires the buffer data from the memory 6. The signal processing unit 8a performs adaptive filter processing on the buffer data. The signal processing unit 8a performs predetermined signal processing on the buffer data on which the adaptive filter processing has been performed. The predetermined signal processing is, for example, data decoding processing.

[0023] The MAC processing unit 9 executes Media Access Control processing on the execution result of predetermined signal processing. For example, the MAC processing unit 9 executes the definition and allocation of an address (MAC address) for identifying the signal processing device 3a. The MAC processing unit 9 may record the result of the executed Media Access Control processing in the memory 6.

[0024] FIG. 2 is a diagram showing a configuration example of the signal processing unit 8a in the first embodiment. The signal processing unit 8a includes an adaptive filter processing unit 80a, a frequency offset compensation unit 81, a phase compensation unit 82, a symbol determination unit 83, and a decoding unit 84.

[0025] The adaptive filter processing unit 80a acquires buffer data from the memory 6 according to the control by the control unit 7. The signal processing unit 8a executes adaptive filter processing on the acquired buffer data using the updated filter coefficients. At least a part of this adaptive filter processing is executed by software. The adaptive filter processing unit 80a outputs the buffer data on which the adaptive filter processing has been executed to the frequency offset compensation unit 81.

[0026] The frequency offset compensation unit 81 executes frequency offset processing on the buffer data on which the adaptive filter processing has been executed. The phase compensation unit 82 executes phase compensation processing on the buffer data on which the frequency offset processing has been executed. The symbol determination unit 83 executes processing for determining symbol points on the buffer data on which the phase compensation processing has been executed. The decoding unit 84 executes data decoding processing on the buffer data on which the phase compensation processing has been executed using the determination result of the symbol points.

[0027] FIG. 3 is a diagram showing an example of updating filter coefficients in the first embodiment. The buffer data 100 is divided into N (= buffer data length / L) regions (divided buffer data). The length (data length) of each region is L. Each region contains one or more sample data.

[0028] Also, a filter coefficient is associated with the region. In FIG. 3, the filter coefficient "W1" is associated with the sample data on the head side of the buffer data 100. The filter coefficient "W N " is associated with the sample data on the tail side of the buffer data 100. In the first embodiment, the filter coefficient is updated for all the sample data in the region of length "L". Therefore, the filter coefficient is updated for all of the buffer data 100.

[0029] FIG. 4 is a diagram showing a configuration example of the adaptive filter processing unit 80a in the first embodiment. The adaptive filter processing unit 80a includes N first filter coefficient update units 800. Hereinafter, the unit length of the sample data in the buffer data is referred to as the "unit sample data length". The adaptive filter processing unit 80a includes P (= L / unit sample data length) filter processing units 801 for each first filter coefficient update unit 800.

[0030] The adaptive filter processing unit 80a divides the buffer data 100 stored in the memory 6 into N first divided buffer data 101 (a plurality of divided buffer data). The length (data length) of the first divided buffer data 101 is L.

[0031] The filter coefficient "W n " is associated with the first divided buffer data 101-n (n is an integer from 1 to N). For example, when the control unit 7 starts N threads, N first filter coefficient update units 800 are generated in the signal processing unit la. The N first filter coefficient update units 800 execute in parallel the process of updating the N filter coefficients.

[0032] For each first filter coefficient update unit 800, the P filter processing units 801 execute in parallel the filter processing on the first divided buffer data 101. The filter processing unit 801-n-p (p is an integer from 1 to P) performs the filter processing on the first divided buffer data 101 of the first filter coefficient update unit 800-n with the filter coefficient "Wn It is executed for each sample data in the buffer data 100 using "". The filter processing unit 801 outputs the first divided buffer data 101 for which the filter processing has been executed to the frequency offset compensation unit 81.

[0033] The first filter coefficient update unit 800 initializes the filter coefficients of all the sample data in the N first divided buffer data 101 of the buffer data 100 to be stored in the memory 6 next time to "W N ". The filter coefficient "W N " that has converged in the current update (the most recent input signal) is used as the initial value of the filter coefficient in the next update. As a result, in the next update, the filter coefficient can be converged in a short time.

[0034] Next, an operation example of the signal processing system 1a will be described. FIG. 5 is a flowchart showing an operation example of the signal processing system 1a in the first embodiment. The control unit 7 acquires the buffer data 100 from the memory 6 (step S101). The control unit 7 divides the buffer data 100 into a plurality of first divided buffer data 101 (step S102). The plurality of first filter coefficient update units 800 execute the update process of the filter coefficient "W n " in parallel for the plurality of first divided buffer data 101 (step S103). The plurality of filter processing units 801 execute filter processing for the sample data of the first divided buffer data 101 for each unit sample data length based on the filter coefficient "W n " (step S104).

[0035] As described above, the control unit 7 divides the buffer data 100 into a plurality of first divided buffer data 101. The plurality of first filter coefficient update units 800 execute the update process of the filter coefficient "W n " for each first divided buffer data 101 included in the plurality of first divided buffer data 101 in parallel for the plurality of first divided buffer data 101. The plurality of filter processing units 801 use the filter coefficient "W" for each first divided buffer data 101.n Based on this, filter processing is performed on the sample data of the first divided buffer data 101.

[0036] This makes it possible to improve the processing throughput. Also, it is possible to reduce the processing delay.

[0037] (Modification Example of the First Embodiment) In the modification example of the first embodiment, the difference from the first embodiment is that the filter coefficient is updated only for some of the sample data in the region of length "L". In the modification example of the first embodiment, the description will focus on the difference from the first embodiment.

[0038] FIG. 6 is a diagram showing an example of updating the filter coefficient in the modification example of the first embodiment. The buffer data 100 is divided into N (= buffer data length / L) regions. The length (data length) of each region is L. Each region contains one or more sample data.

[0039] Also, a filter coefficient is associated with each region. In FIG. 6, the filter coefficient "W1" is associated with the sample data on the head side of the buffer data 100. The filter coefficient "W N " is associated with the sample data on the tail side of the buffer data 100. In the modification example of the first embodiment, the filter coefficient is updated only for some of the sample data in the region of length "L". Therefore, the filter coefficient is updated only for a part of the buffer data 100.

[0040] The first filter coefficient update unit 800 initializes the filter coefficients of all the sample data in the N first divided buffer data 101 of the buffer data 100 to be stored in the memory 6 next time as "W N ". The filter coefficient "W N " that converged in the current update (the most recent input signal) is used as the initial value of the filter coefficient in the next update. This makes it possible to converge the filter coefficient in a short time in the next update.

[0041] As described above, the plurality of first filter coefficient update units 800 update the filter coefficients “W n The update processes for " may be executed in parallel. This makes it possible to improve the processing throughput. It is also possible to reduce the processing delay.

[0042] (Second embodiment) The second embodiment differs from the first embodiment in that a representative value of the filter coefficients is derived for each of a plurality of filter coefficients. The second embodiment will be described focusing on the differences from the first embodiment.

[0043] 7 is a diagram showing an example of the configuration of a signal processing system 1b in the second embodiment. The signal processing system 1b includes a signal generating device 2 and a signal processing device 3b. The signal generating device 2 includes a signal generating unit 4. The signal processing device 3b includes a communication unit 5, a memory 6, a control unit 7, a signal processing unit 8b, and a MAC processing unit 9.

[0044] 8 is a diagram showing an example of updating filter coefficients in the second embodiment. The buffer data 100 is divided into N (=buffer data length / L) first regions. The length (data length) of each first region is L. Each first region includes one or more sample data. The first region is divided into M second regions. The length (data length) of each second region is L'.

[0045] In addition, a filter coefficient is associated with the second region. In FIG. 8, the sample data in the second region at the beginning of the buffer data 100 is associated with a filter coefficient "W 1,m (m is an integer between 1 and M) is associated with the sample data in the second area at the end of the buffer data 100. N,m In the second embodiment, for all sample data in the first region of length "L", the filter coefficients are updated for each second region of length "L'". Therefore, the filter coefficients are updated for all of the buffer data 100.

[0046] In the second embodiment, a representative value of the filter coefficients (hereinafter referred to as "representative filter coefficient") is derived for each of the M filter coefficients. As a result, N representative filter coefficients are derived.

[0047] The first filter coefficient update unit 800 initializes the filter coefficients of all the sample data in the N first divided buffer data 101 of the buffer data 100 to be stored next time in the memory 6 as "W N ". The filter coefficient "W N " that has converged in the current update (the most recent input signal) is used as the initial value of the filter coefficient in the next update. As a result, in the next update, the filter coefficient can be converged in a short time.

[0048] FIG. 9 is a diagram showing a configuration example of the adaptive filter processing unit 80b in the second embodiment. The adaptive filter processing unit 80b includes "N×M" (= buffer data length / L') second filter coefficient update units 802 and N representative filter coefficient derivation units 803. The adaptive filter processing unit 80b includes P filter processing units 801 for each representative filter coefficient derivation unit 803.

[0049] The filter coefficient "W n " is associated with the first divided buffer data 101-n. For example, when the control unit 7 starts "N×M" threads, "N×M" second filter coefficient update units 802 are generated in the signal processing unit 8b. The "N×M" second filter coefficient update units 802 execute in parallel the process of updating the "N×M" filter coefficients.

[0050] The representative filter coefficient derivation unit 803 derives a representative filter coefficient "W n,1 " for each of the M filter coefficients from "W n,M " to "W n ". For example, the representative filter coefficient derivation unit 803 uses the average value of the M filter coefficients as the representative filter coefficient "W nis derived as "」. As a result, the representative filter coefficient derivation unit 803 derives N representative filter coefficients "W n ". The representative filter coefficient derivation unit 803 outputs the representative filter coefficient "W n " to the filter processing unit 801-n-p.

[0051] For each representative filter coefficient derivation unit 803, the P filter processing units 801 execute filter processing on the first divided buffer data 101 in parallel. The filter processing unit 801-n-p executes filter processing on the first divided buffer data 101 of the first filter coefficient update unit 800-n for each sample data in the buffer data 100 using the representative filter coefficient "W n ". The filter processing unit 801 outputs the first divided buffer data 101 on which the filter processing has been executed to the frequency offset compensation unit 81.

[0052] Next, an operation example of the signal processing system 1b will be described. FIG. 10 is a flowchart showing an operation example of the signal processing system 1b in the second embodiment. The control unit 7 acquires the buffer data 100 from the memory 6 (step S201). The control unit 7 divides the buffer data 100 into a plurality of first divided buffer data 101 (step S202). The control unit 7 divides the first divided buffer data 101 into a plurality of second divided buffer data 102 (a plurality of divided buffer data) (step S203). A plurality of second filter coefficient update units 802 execute update processing of the filter coefficient "W n,m " for each of the plurality of second divided buffer data 102 in parallel (step S204). The representative filter coefficient derivation unit 803 derives a representative value of the filter coefficient "W n,m " for each of the second divided buffer data 102 for each of the first divided buffer data 101 (step S205). A plurality of filter processing units 801 execute filter processing for each unit sample data length on the sample data of the first divided buffer data 101 based on the representative filter coefficient derived for each of the first divided buffer data 101 (step S206).

[0053] As described above, the control unit 7 divides the buffer data 100 into a plurality of first divided buffer data 101. The control unit 7 divides the first divided buffer data 101 included in the plurality of first divided buffer data 101 into a plurality of second divided buffer data 102. The plurality of second filter coefficient update units 802 update the filter coefficients "W" for each of the second divided buffer data 102 included in the plurality of second divided buffer data 102. n,m The representative filter coefficient derivation unit 803 executes the update process of the filter coefficient "W" for each of the second divided buffer data 102 in parallel. n,m The plurality of filter processing units 801 executes filter processing on the sample data of the first divided buffer data 101 based on the representative value.

[0054] This makes it possible to improve processing throughput, reduce processing delays, and make it possible to converge the filter coefficients within a predetermined time.

[0055] (Third embodiment) The third embodiment differs from the first and second embodiments in that the configuration of the network connecting the signal generating device and the signal processing device is a point-to-multipoint configuration. The third embodiment will be described focusing on the differences from the first and second embodiments.

[0056] FIG. 11 is a diagram showing a configuration example of the signal processing system 1c in the third embodiment. The signal processing system 1c includes R (R is an integer of 2 or more) signal generation devices 2 (opposite communication devices), a signal processing device 3c, and a splitter 20. In the third embodiment, as an example, the configuration of the network connecting the signal generation device 2 and the signal processing device 3c is a point-to-multipoint configuration. The signal generation device 2 includes a signal generation unit 4. The signal processing device 3a includes a communication unit 5, a memory 6, a control unit 7, a signal processing unit 8c, and a MAC processing unit 9.

[0057] The signal generation unit 4-r (r is an integer from 1 to R) generates a predetermined signal. The generated signal includes the data of the main signal. The generated signal may further include the data of the sub-signal. The signal generation unit 4-r transmits the generated signal to the communication unit 5.

[0058] The operation of the signal processing unit 8c is the same as the operation of the signal processing unit 8a in the first embodiment or the signal processing unit 8b in the second embodiment. The operation of the signal processing unit 8c may also be the same as the operation of the signal processing unit 8a in the modification of the first embodiment.

[0059] As described above, the configuration of the network connecting the signal generation device and the signal processing device may be a point-to-multipoint configuration.

[0060] As a result, it is possible to improve the processing throughput. It is possible to reduce the processing delay. Also, it is possible to converge the filter coefficients within a predetermined time.

[0061] (Hardware Configuration Example) FIG. 12 is a diagram showing a hardware configuration example of the signal processing apparatus 3 in each embodiment. The signal processing apparatus 3 includes a processor 30. The signal processing apparatus 3 may include a plurality of processors 30. The processor 30 may be a multi-core processor. The processor 30 such as a CPU (Central Processing Unit) executes a program stored in a storage device 32 having a non-volatile recording medium (non-transitory recording medium) and a memory 31, thereby being realized as software. The program may be recorded on a computer-readable non-transitory recording medium. The program may be a multi-thread program. The computer-readable non-transitory recording medium is, for example, a non-transitory recording medium such as a flexible disk, a magneto-optical disk, a ROM (Read Only Memory), a portable medium such as a CD-ROM (Compact Disc Read Only Memory), or a storage device such as a hard disk built in a computer system. The communication unit 33 executes predetermined communication processing.

[0062] At least a part of each functional unit of the signal processing apparatus 3 may be an analog circuit or a digital circuit. The signal processing apparatus may be realized using hardware including an electronic circuit (electronic circuit or circuitry) using, for example, an LSI (Large Scale Integrated circuit), an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), or an FPGA (Field Programmable Gate Array).

[0063] As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and designs and the like within the scope not departing from the gist of the present invention are also included.

Industrial Applicability

[0064] The present invention is applicable to a communication system.

Explanation of Reference Numerals

[0065] 1a, 1b, 1c... signal processing systems, 2... signal generation device, 3, 3a, 3b, 3c... signal processing devices, 4... signal generation unit, 5... communication unit, 6... memory, 7... control unit, 8a, 8b, 8c... signal processing units, 9... MAC processing unit, 10... burst corresponding unit, 11... PON-MAC processing unit, 20... splitter, 30... processor, 31... memory, 32... storage device, 33... communication unit, 80a, 80b... adaptive filter processing units, 81... frequency offset compensation unit, 82... phase compensation unit, 83... symbol determination unit, 84... decoding unit, 100... buffer data, 101... first divided buffer data, 102... second divided buffer data, 800... first filter coefficient update unit, 801... filter processing unit, 802... second filter coefficient update unit, 803... representative filter coefficient derivation unit

Claims

1. A control unit that divides buffer data into a plurality of divided buffer data, a plurality of filter coefficient update units that execute in parallel, for each divided buffer data included in the plurality of divided buffer data, an update process of a filter coefficient, and a plurality of filter processing units that execute a filter process on sample data of the divided buffer data based on the filter coefficient for each divided buffer data are provided, wherein the filter coefficient includes a plurality of sample data, a signal processing device.

2. The signal processing device according to claim 1, wherein the plurality of filter coefficient update units execute in parallel the update process of the filter coefficient for a part of the divided buffer data.

3. A control unit that divides buffer data into a plurality of first divided buffer data and divides the first divided buffer data included in the plurality of first divided buffer data into a plurality of second divided buffer data, a plurality of filter coefficient update units that execute in parallel, for each second divided buffer data included in the plurality of second divided buffer data, an update process of a filter coefficient, a representative filter coefficient derivation unit that derives a representative value of the filter coefficient for each second divided buffer data, and a plurality of filter processing units that execute a filter process on sample data of the first divided buffer data based on the representative value are provided in a signal processing device.

4. A signal processing method executed by a signal processing device, comprising: a step of dividing buffer data into a plurality of divided buffer data; a step of executing in parallel, for each divided buffer data included in the plurality of divided buffer data, an update process of a filter coefficient; and a step of executing a filter process on sample data of the divided buffer data based on the filter coefficient for each divided buffer data wherein the filter coefficient includes a plurality of sample data, a signal processing method.

5. A signal processing method executed by a signal processing device, comprising: a step of dividing buffer data into a plurality of first divided buffer data and dividing the first divided buffer data included in the plurality of first divided buffer data into a plurality of second divided buffer data, ​ performing, in parallel for the plurality of second divided buffer data, an update process of a filter coefficient for each of the second divided buffer data included in the plurality of second divided buffer data; deriving a representative value of the filter coefficient for each of the second divided buffer data; performing a filtering process on the sample data of the first divided buffer data based on the representative value; and A signal processing method including the above steps.

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