Hybrid CMOS Micro LED Display Layout

Abstract

At least two long sides of the μLED display area have alternating V led A CMOS power plane is described that includes a V contact area and a Vcat contact area. Thus, V is provided along the four sides of the μLED display panel. led and the cathode current is injected uniformly. V led and V cat A large cathode current distribution ring on the circuit is used to distribute the current along the four sides of the panel. The current distribution ring surrounds the pixel die area. An insulating area may be included on the cathode current distribution ring adjacent to one of the μ-bumps.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to light emitting diode (LED) devices. More specifically, embodiments are directed to a layout structure for CMOS driver electronics for individual control of pixel brightness of micro LEDs. [Background technology]

[0002] A light-emitting diode (LED) is a semiconductor light source that emits visible light when an electric current passes through it. LEDs combine a P-type semiconductor with an N-type semiconductor. LEDs typically use Group III compound semiconductors. Group III compound semiconductors provide stable operation at higher temperatures than devices using other semiconductors. Group III compounds are typically formed on substrates made of sapphire or silicon carbide (SiC).

[0003] LEDs have emerged as attractive light sources for numerous applications. From road signs and traffic signals, LEDs are now dominant in general lighting, automotive, mobile electronics, camera flashes, display backlighting, horticulture, and disinfection applications. Typical advantages of LEDs over competing light sources are increased efficacy, longer lifetime, and adaptability to a wide variety of form factors.

[0004] Highly compact pixelated light-emitting diode (LED) devices, such as arrays of microLEDs for advanced automotive forward lighting, may have monolithic large-area, high-power LED dies hybridized with CMOS driver electronics for individual control of pixel brightness. Linear drive schemes are among the most practical solutions for such control electronics, especially in large pixel array configurations.

[0005] A difficulty associated with this system relates to CMOS routing for interconnecting all pixel contacts to power supplies and integrated circuit drivers. A cost-effective solution must minimize the number of metal layers for the power planes. However, minimizing the number of metal layers for the power planes can compromise the layout's ability to distribute current evenly, leading to undesirable current crowding effects with excessive current density levels, which can negatively impact reliability and heat dissipation associated with electromigration at the contact interfaces.

[0006] Therefore, a layout architecture that optimizes current distribution in a hybrid LED die / CMOS monolithic architecture is desirable. Summary of the Invention

[0007] The techniques and embodiments of the present disclosure relate to a CMOS power plane. In one or more embodiments, the CMOS power plane is a cathode redistribution ring having an inner portion and an outer portion, the inner portion surrounding a periphery of a die pixel area, and the outer portion providing a common supply voltage V interleaved with cathode current distribution areas. led and a plurality of cathode μ-bumps contacting the inner portion of the cathode redistribution ring along the periphery of the die pixel area.

[0008] Another embodiment of the present disclosure relates to a CMOS layout. In one or more embodiments, the CMOS layout is a power plane on a substrate with multiple alternating Vs evenly distributed along at least two sides of the power plane. led a power plane having a contact region and a cathode contact region; a cathode current redistribution ring extending along four sides of the power plane; and a plurality of alternating V ledThe device includes a plurality of cathode μ-bumps that connect each of the contact areas and cathode contact areas to corresponding p-contacts of a plurality of pixels, and a common cathode grid that electrically connects the plurality of pixels to the plurality of cathode μ-bumps.

[0009] Further embodiments relate to a CMOS power plane. In one or more embodiments, the CMOS power plane is a cathode redistribution ring having an inner portion and an outer portion, the inner portion surrounding a periphery of a die pixel area, and the outer portion providing a common supply voltage V interleaved with cathode current distribution areas along a first edge, a second edge, a third edge, and a fourth edge of the CMOS power plane. led and a plurality of cathode μ-bumps contacting the inner portion of the cathode redistribution ring along the periphery of the die pixel area.

[0010] Additional embodiments relate to a CMOS layout. In one or more embodiments, the CMOS layout includes a power plane on a substrate and a plurality of alternating Vs distributed along a first side, a second side, a third side, and a fourth side of the power plane. led a power plane having a contact region and a cathode contact region; a cathode current redistribution ring extending along the first side, the second side, the third side, and the fourth side of the power plane; and a plurality of alternating V led The device includes a plurality of cathode μ-bumps that connect each of the contact areas and cathode contact areas to corresponding p-contacts of a plurality of pixels, and a common cathode grid that electrically connects the plurality of pixels to the plurality of cathode μ-bumps.

[0011] Another embodiment relates to a CMOS power plane. In one or more embodiments, the CMOS power plane is a cathode redistribution ring having an inner portion and an outer portion, the inner portion surrounding a periphery of a die pixel area, and the outer portion providing a common supply voltage V interleaved with cathode current distribution areas. leda plurality of cathode μ-bumps contacting the inner portion of the cathode redistribution ring along the periphery of the die pixel area; and an insulating region on the cathode redistribution ring adjacent one of the plurality of cathode μ-bumps.

[0012] Additional embodiments relate to a CMOS layout. In one or more embodiments, the CMOS layout is a power plane on a substrate with multiple alternating Vs evenly distributed along at least two sides of the power plane. led a power plane having a contact region and a cathode contact region; a cathode current redistribution ring extending along four sides of the power plane; and a plurality of alternating V led The cathode current redistribution ring includes a plurality of cathode μ-bumps connecting each of the contact regions and cathode contact regions to a corresponding p-contact of a plurality of pixels, an insulating region on the cathode current redistribution ring adjacent to one of the plurality of cathode μ-bumps, and a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode μ-bumps. [Brief explanation of the drawings]

[0013] In order that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, will be rendered with reference to embodiments, some of which are illustrated in the accompanying drawings. It is to be mentioned, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered as limiting its scope, as the present disclosure may admit of other embodiments that are equally effective. The embodiments described herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which like reference numerals refer to similar elements.

[0014] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee. [Figure 1A]1 illustrates a top view of a CMOS top layer of a CMOS power plane according to one or more embodiments. [Figure 1B] FIG. 1B is a cross-sectional view taken along line A of FIG. 1A according to one or more embodiments. [Figure 1C] FIG. 1B is a cross-sectional view taken along line B of FIG. 1A according to one or more embodiments. [Figure 1D] FIG. 1B illustrates a top view of a CMOS second current distribution layer of the CMOS power plane of FIG. 1A according to one or more embodiments. [Figure 1E] 1B illustrates a top view of the common cathode of the CMOS power plane of FIG. 1A according to one or more embodiments. [Figure 2A] 1 illustrates a top view of a CMOS top layer of a CMOS power plane according to one or more embodiments. [Figure 2B] FIG. 2B illustrates a top view of a CMOS second current distribution layer of the CMOS power plane of FIG. 2A according to one or more embodiments. [Figure 2C] 2B illustrates a top view of the common cathode of the CMOS power plane of FIG. 2A according to one or more embodiments. [Figure 3A] 1 illustrates a top view of a CMOS top layer with isolation regions of a CMOS power plane according to one or more embodiments. [Figure 3B] FIG. 3B is an expanded view of a region 370 of the CMOS power plane of FIG. 3A according to one or more embodiments. [Figure 4A] 1 is a current density plot of a CMOS power plane in accordance with one or more embodiments. [Figure 4B] 1 is a current density plot of a CMOS power plane in accordance with one or more embodiments. [Figure 5A] 1 is a current density plot of a μ-bump according to one or more embodiments. [Figure 5B] 1 is a current density plot of a μ-bump according to one or more embodiments. [Figure 6] FIG. 1 shows a block diagram of an example of a visualization system using a μLED array of one or more embodiments.

[0015] For ease of understanding, the same reference numerals have been used, where possible, to designate like elements common to the figures. The figures are not drawn to scale; for example, the height and width of the mesas are not drawn to scale. DETAILED DESCRIPTION OF THE INVENTION

[0016] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0017] The term "substrate," as used herein, according to one or more embodiments, refers to an intermediate or final structure having a surface or surface portion on which a process acts. Furthermore, reference to a substrate in some embodiments may refer to only a portion of a substrate, unless the context clearly indicates otherwise. Also, reference to depositing on a substrate, according to some embodiments, includes depositing on a bare substrate or depositing on a substrate having one or more layers, films, features, or materials deposited or formed thereon.

[0018] In one or more embodiments, the term "substrate" refers to any substrate or material surface formed on a substrate on which film processing occurs during a manufacturing process. In exemplary embodiments, the substrate surface on which processing occurs includes materials such as silicon, silicon oxide, silicon-on-insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and any other suitable material, such as metals, metal nitrides, Group III nitrides (e.g., GaN, AlN, InN, and other alloys), metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, light-emitting diode (LED) devices. In some embodiments, the substrate is subjected to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in some embodiments, any of the disclosed film processing steps are also performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include the underlying layer as the context indicates. Thus, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0019] The terms "wafer" and "substrate" are used interchangeably in this disclosure. Thus, as used herein, a wafer serves as a substrate for the formation of the LED devices described herein.

[0020] To deploy LEDs in high-density display applications or large-area medium-density applications, it is desirable for LED units to have characteristic dimensions of 100 micrometers or less, with typical values ranging from 8 to 25 micrometers. This class of LEDs is commonly referred to as microLEDs (μLEDs). MicroLED-based microdisplay technology is still in the early stages of commercial deployment, but it is expected to gradually replace existing display technologies, such as liquid crystal on silicon (LCDoS) or organic light-emitting diode on silicon (OLEDoS), in certain applications. One of the biggest hurdles to commercializing microLED displays is the transfer technology required to attach pixelated LEDs to a backplane.

[0021] The embodiments described herein describe CMOS driver electronics for individual control of pixel brightness of a micro LED. The CMOS power plane layout of one or more embodiments includes a V led Contact area and V cat The CMOS power plan layout of one or more embodiments advantageously uses small, interleaved contact areas along the four sides of the panel. led and cathode current is injected uniformly. led and V cat A large ring on the circuit is used to distribute the current along the four sides of the panel.

[0022] Complementary metal-oxide-semiconductor (CMOS), also known as complementary-symmetric metal-oxide-semiconductor (COS-MOS), is a type of metal-oxide-semiconductor field-effect transistor (MOSFET) manufacturing process that uses complementary, symmetric pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used to build integrated circuit (IC) chips. CMOS refers to both a specific style of digital circuit design and the family of processes used to implement that circuit on an integrated circuit (chip). CMOS circuits dissipate less power than logic families with resistive loads.

[0023] The CMOS power circuit layout provides a positive V LED The LED pixel common cathode has two functions: to apply a ground potential to the common cathode of the LED pixel and to apply a ground potential to the common cathode of the pixel. For these purposes, (1) a V cat circuit and (2) positive potential (V LED ) to each CMOS driver cell. LED Two different circuits are required: a voltage circuit and a voltage circuit.

[0024] A CMOS layout may typically be divided into multiple layers designated for digital circuitry, small signal analog circuitry, and powertrain. The latter is preferentially reduced to one or two layers, particularly the top or bottom layers, to facilitate current distribution and interconnection to external components such as LED dies. For the latter, a peripheral ring around the die is usually used to connect the pixel common cathode grid to V catThe ring connection is as close as possible to the die area to reduce ohmic losses. The interconnect between the common cathode and ground circuitry cannot be located within the die area because even the minimum area required to interconnect the two layers would not fit into the currently limited space between pixels. The interconnection of the common cathode grid with the power plane is performed with a μ-bump, which has a size similar to the pixel size (~40 × 40 μm). Because the current flowing through the entire device is very high and the length of the first μ-bump row is limited, the current density in the μ-bump becomes very high, increasing the risk of reliability failure of the metal interconnect. Therefore, limiting the current density in the μ-bump is an important design requirement.

[0025] Additionally, the thickness of the CMOS power plane layer is limited by process constraints. For example, using sputtering or plating, the process thickness of CMOS power lines is limited to a few micrometers. As a result, the sheet resistance of the spreading layer is limited, and electrical losses in the spreading layer become significant. To solve this problem, additional current distribution layers connected in parallel by through vias are commonly used.

[0026] Traditionally, CMOS power plane layouts have been led Uses part of the CMOS backplane for voltage, V cat Use a separate part of the backplane for the power supply voltage. In a traditional CMOS power plane layout, cat The U-shaped cathode electrical circuit (having ledThe U-shaped cathode circuitry surrounds the electrical circuit. The U-shaped cathode circuitry serves as the current distribution region for the cathode circuitry. The problem with this configuration is that the cathode current is injected at three edges of the panel. The current in the second current distribution layer is forced to flow to the lateral edges. Because it is not wide enough, it has high resistance. This is the main problem that leads to uneven current distribution in the common cathode μ-bump. In this type of CMOS layout, current is not injected uniformly along the four edges of the die area. As a result, one or more current distribution layers connected in parallel are needed to distribute the cathode current uniformly to the four edges of the LED pixel area and reduce μ-bump current density.

[0027] Therefore, additional layers connected in parallel are required to redistribute the current along the remaining edges of the die area. Therefore, the additional layers are primarily used to distribute the current rather than to reduce ohmic losses. LED For ,current is injected only on one side of the panel, causing a significant voltage drop between the top and bottom sides of the die area.,As a result, the current distribution in the die area is not uniform and the current density at the μ-bump is very high.

[0028] 1A-1C, one or more embodiments provide a CMOS power plane layout 100 in which small, interleaved cathode distribution regions alternating with Vcat and Vled contact regions 102, 104 and a large cathode redistribution ring 112 are used to distribute current around the four sides of the die area. With this layout, current is uniformly distributed across the four sides of the die area, and additional current distribution layers connected in parallel can be used primarily to reduce ohmic losses. As a result, current density and ohmic power losses in the μ-bumps are significantly reduced. Furthermore, only one type of cathode microbump (u-bump or μ-bump) 106 is required, simplifying the CMOS panel manufacturing process.

[0029] Those skilled in the art will understand that for ease of illustration, the multiple μbumps 106 are not drawn to scale, and the illustrated μbumps 106 appear larger than they would be. Furthermore, those skilled in the art will understand that multiple rows of μbumps 106 may be used for common cathode interconnection with CMOS (not shown in the drawings). In practice, the minimum size of the μbumps is limited by process constraints. In one or more embodiment hybrid CMOS μLED displays, the radius of the anode μbumps is smaller than the pixel size, and the cathode μbumps 106 have the same or similar size as the anode μbumps 114.

[0030] A schematic of a CMOS power plane 100 having interleaved regions 102, 104 and a cathode redistribution ring 112 according to the present invention is shown in Figures 1A-1E. Figures 1B and 1C are cross-sectional views 100A and 100B, respectively, of the μLED display region 100 shown in Figure 1A along lines A and B. Figure 1A is a top view 100 of the CMOS top layer. Figure 1D is a view 150 of the CMOS second current distribution layer. Figure 1E is a view 155 of the common cathode.

[0031] 1A-1C, in one or more embodiments, the CMOS power plane 120 is connected to at least two long sides 108 of the μLED display area 100 via a V led 104 contact area and V cat 102 contact areas. As used herein, "interleaved" refers to a V led 104 contact area adjacent to two cathode 102 contact areas. led This refers to the interspersed alternating 104 contact areas and cathode 102 contact areas. led The current in the cathode 104 and cathode 102 is injected uniformly along the four sides 108, 110 of the panel.

[0032] In one or more embodiments, V cat Large cathode redistribution ring 112 and V on the circuitLED Common supply voltage V on the circuit led 154 are used to distribute current along the four sides 108, 110 of the panel. Note that the cathode redistribution ring 112 in one or more embodiments is a full ring, not a U-shaped ring. As shown, only the top and bottom sides of the display 100 are used for current injection. In one or more embodiments, the cathode redistribution ring 112 surrounds the pixel die area, the common cathode grid 130. Note that for ease of illustration, the common cathode grid 130 in FIG. 1A is depicted without any grid covering the cathode μ-bumps 106 so that the cathode μ-bumps 106 can be seen. Those skilled in the art will understand that the common cathode grid 130 can extend over the cathode μ-bumps 106, as shown in FIGS. 1B and 1C.

[0033] The pixel die area, common cathode grid 130, has a plurality of pixels 116, as shown in Figures 1B and 1C. While only two pixels 116 are shown, one skilled in the art will understand that there may be any number of pixels, depending on the size of the pixels 116 and the size of the die. In some embodiments, there may be 86 pixels. In other embodiments, there may be 170 pixels or more. The pixels 116 may have any suitable size known to one skilled in the art. In some embodiments, the pixels 116 may be 40 μm pixels, 30 μm pixels, or 20 μm pixels.

[0034] In one or more embodiments, the alternating region is V cat 102 Contact area and V led 1A, the alternating regions consist of ten cathode contacts 102 and eight V contacts 104 periodically distributed along the two long sides 108 of the CMOS panel 100. led In one or more embodiments, the alternating V ledThe more cathode 104 and cathode 102 contact areas there are, the better the current distribution. Therefore, in one or more embodiments, more than three or more than five contact areas are used. In some embodiments, at least 10 cathode 102 contact areas and at least 8 V led 104 contact region.

[0035] In one or more embodiments, alternating V led The cathode 104 and cathode 102 contact areas are located on the two long sides 108 of the CMOS panel 100 but not on the two short sides 110 of the panel 100 .

[0036] 1B and 1C, an architecture is used that has a common cathode grid 130 and a CMOS panel 120 that is bump-connected (μ-bumps 114) to the p or anode contacts 124 of each pixel 116. One advantage of this configuration is that the CMOS layout is symmetrical, with the path lengths between the die areas and the cathode contacts being the same, providing good current injection uniformity. In one or more embodiments, a driver circuit 140 is used to control the current provided to each pixel individually.

[0037] In one or more embodiments, the length of the interleaved regions can vary between hundreds of micrometers and several millimeters. In one or more embodiments, the interleaved regions can be symmetric. In other embodiments, the interleaved regions can be asymmetric. Each interleaved region of a different polarity is electrically isolated by a region a few microns wide. In one or more embodiments, V cat The top CMOS current distribution layer is used for routing because it simplifies interconnection with the common cathode contact. In some embodiments, a second current distribution layer (or more current distribution layers) is used to route V led Used for routes. V ledThe current passes through electrical vias located above the contact area to a second current distribution layer connected to the p-contact 124 of each driver cell. In one or more embodiments, a large cathode redistribution ring 112 surrounding the four sides of the die area is used to distribute the current evenly around the die.

[0038] 1D, a top view of the CMOS second current distribution layer 150 is shown. In one or more embodiments, the common supply voltage V led 154 is V led Surrounding grid 136, V led 104 contact area. Common supply voltage V led 154 has interleaved cathode current distribution regions 102. In one or more embodiments, the cathode current does not travel through the cathode current distribution regions 102. Thus, in some non-illustrated embodiments, the cathode current distribution regions 102 may not be present, and therefore the common supply voltage V led 154 is enlarged.

[0039] 1E shows a common cathode 155 according to one or more embodiments. The outer region of the cathode redistribution ring 112 overlaps the cathode μ-bumps 106. The cathode redistribution ring 112 surrounds the common cathode grid 130. The common cathode grid 130 contacts each pixel 116 on the pixel side.

[0040] In one or more non-illustrated embodiments, an inverted structure may alternatively be used with a common anode (instead of a common cathode) and a CMOS panel bumped to the n-contact of each pixel, in which case NMOS transistors are used instead of PMOS transistors in driver 140.

[0041] 2A-2C show an alternative embodiment in which a CMOS power plane layout 200 has interleaved small cathode distribution regions 202, 204, alternating Vcat and Vled contact regions 202, 204, and a large cathode redistribution ring 212 for current distribution around the four sides of the die area. With this layout, current is evenly distributed across the four sides of the die area, and additional current distribution layers connected in parallel can be used primarily to reduce ohmic losses. As a result, current density and ohmic power losses in the μ-bumps are significantly reduced. Furthermore, only one type of cathode microbump (u-bump or μ-bump) 206 is required, simplifying the CMOS panel manufacturing process.

[0042] Figure 2A is a diagram of the CMOS top layer 200. Figure 2B is a diagram of the CMOS second current distribution layer 250. Figure 2C is a diagram of the common cathode 255.

[0043] Referring to FIG. 2A, all four sides of the panel 200 can be used to place interleaved contact areas. In one or more embodiments, the open space on the short side 210 of the panel is used to place addressing circuitry, driver components, sense, etc. led The contact areas 204 and cathode 202 contact areas are arranged around the four sides 208 , 210 of the panel 200 .

[0044] In one or more embodiments, V led and V cat A large cathode redistribution ring 112 on the circuit is used to distribute current along the four sides 208, 210 of the panel. Note that in one or more embodiments, the cathode redistribution ring 212 is a full ring, not a U-shaped ring. As shown, only the top and bottom sides of the display 200 are used for current injection. In one or more embodiments, the cathode redistribution ring 212 surrounds a pixel die area, a common cathode grid 230. The pixel die area 230 has a plurality of pixels (not shown).

[0045] In one or more embodiments, the alternating region is V cat 202 contact area and V led 2A, the alternating regions consist of ten cathode contacts 202 and eight V contacts 204 periodically distributed along the four sides 208, 210 of the CMOS panel 200. led In one or more embodiments, the alternating V led The more V 204 and cathode 202 contact areas there are, the better the current distribution. Therefore, in one or more embodiments, more than three or more than five contact areas are used. In some embodiments, at least 10 V 204 and at least 8 V 202 contact areas are used. led 204 contact region.

[0046] In one or more embodiments, alternating V led The cathode 204 and cathode 202 contact areas are located on the long sides 108 of the CMOS panel 200 and along the two short sides 210 of the panel 200 .

[0047] In one or more embodiments, the length of the interleaved regions can vary between hundreds of micrometers and several millimeters. In one or more embodiments, the interleaved regions can be symmetric. In other embodiments, the interleaved regions can be asymmetric. Each interleaved region of a different polarity is electrically isolated by a region a few microns wide. In one or more embodiments, V cat The top CMOS current distribution layer is used for routing because it simplifies interconnection with the common cathode contact. In some embodiments, a second current distribution layer (or more current distribution layers) is used to route V led Used for routes. V ledThe current passes through electrical vias located above the contact area to a second current distribution layer connected to the p-contact of each driver cell. In one or more embodiments, a large cathode redistribution ring 212 surrounding the four sides of the die area is used to distribute the current evenly around the die.

[0048] 2B, a CMOS second current distribution layer 250 is shown. In one or more embodiments, a common supply voltage V led 254 surrounds the die area 230, and V led 204 contact area. Common supply voltage V led 254 has interleaved cathode current distribution regions 202. In one or more embodiments, the cathode current does not travel through the cathode current distribution regions 202. Thus, in some non-illustrated embodiments, the cathode current distribution regions 202 may not be present, and therefore the common supply voltage V led 254 is enlarged.

[0049] 2C shows a common cathode 255 according to one or more embodiments. The outer region of the cathode redistribution ring 212 overlaps the cathode μ-bumps 206. The cathode redistribution ring 212 surrounds the common cathode grid 230. The common cathode grid 230 contacts each pixel on the pixel side.

[0050] Traditionally, CMOS power plane V cat The layout has very high current densities in the outermost cathode μ-bumps. This can be caused by the outer contact pads supplying current primarily to the outermost corner cathode μ-bumps. Over time, high current densities and temperatures can accelerate metal-to-metal connection failure mechanisms. If one cathode μ-bump cracks or delamination, current will not flow through that μ-bump, and the maximum current density of neighboring μ-bumps will also increase.

[0051] 3A and 3B, in one or more embodiments, a solution to reduce current density in the μ-bump 306 is to reduce the outer V cat The inclusion of an insulating region 360 between the pad and the outermost μ-bump 306x. Figure 3B is an expanded view of region 370 of Figure 3A.

[0052] In one or more embodiments, the outer V cat This can reduce the DC current between the pad and the outermost corner μ-bump 306x, thereby reducing the current density in the cathode μ-bump 306. In one or more embodiments, the insulating region 360 reduces the risk of failure of the outermost corner μ-bump 306x due to high current density. The insulating region 360 does not completely block current from reaching the outermost corner μ-bump 306x. To this end, a gap 345 of at least 10 μm exists between the insulating region 360 and the outermost corner cathode μ-bump 306x. The length of the insulating region 360 is at least 80 μm to suppress current injection on at least two μ-bumps 306. In one or more embodiments, the insulating region 360 includes two vertical etched lines to suppress current injection from both sides.

[0053] In some embodiments, insulating region 360 comprises an etched opening. In other embodiments, insulating region 360 comprises a dielectric material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), aluminum nitride (AlN), and combinations thereof. Those skilled in the art will recognize that the use of a formula such as SiO to represent silicon oxide does not imply a specific stoichiometric relationship between elements; the formula merely identifies the major elements of the film.

[0054] Visualization systems, such as virtual reality and augmented reality systems, are becoming increasingly common in fields such as entertainment, education, medicine, and business.

[0055] In a virtual reality system, a display can present a user with a view of a scene, such as a three-dimensional scene. The user can move within the scene, for example, by changing the user's head position or walking. The virtual reality system can detect the user's movements and change the view of the scene to match the movements. For example, as the user rotates their head, the system can present a view of the scene whose viewing direction changes to match the user's gaze. In this way, the virtual reality system can simulate the user's presence within the three-dimensional scene. The virtual reality system can also receive haptic input, for example from a wearable position sensor, and optionally provide haptic feedback to the user.

[0056] In an augmented reality system, a display can incorporate elements from a user's surroundings into a view of a scene. For example, an augmented reality system can add text captions and / or visual elements to a view of a user's surroundings. For example, a retailer can use an augmented reality system to show a user how furniture will look in a room in the user's home by incorporating a visualization of the furniture over a captured image of the user's surroundings. As the user moves around the user's room, the visualization takes the user's movements into account and changes the visualization of the furniture to match the movements. For example, an augmented reality system can position a virtual chair in a room. The user can stand in front of the virtual chair's location in the room and see the front side of the chair. The user can move to an area behind the virtual chair's location in the room and see the back side of the chair. In this way, the augmented reality system can add elements to a dynamic view of the user's surroundings.

[0057] FIG. 6 shows a block diagram of an example visualization system 10 utilizing a μLED array of one or more embodiments. The visualization system 10 can include a wearable housing 12, such as a headset or goggles. The housing 12 can mechanically support and house the elements described in detail below. In some examples, one or more of the elements described in detail below can be included in one or more additional housings that are separate from the wearable housing 12 and can be coupled to the wearable housing 12 wirelessly and / or via a wired connection. For example, the separate housing can reduce the weight of the wearable goggles, such as by including a battery, radio, and other elements. The housing 12 can include one or more batteries 14 that can power any or all of the elements described in detail below. The housing 12 can include circuitry that can be electrically coupled to an external power source, such as a wall outlet, to recharge the battery 14. The housing 12 can include one or more radios 16 for wireless communication with a server or network via a suitable protocol, such as WiFi.

[0058] The visualization system 10 may include one or more sensors 18, such as, for example, optical sensors, audio sensors, tactile sensors, thermal sensors, gyro sensors, time-of-flight sensors, triangulation-based sensors, and others. In some examples, one or more of the sensors may sense a user's location, position, and / or orientation. In some examples, one or more of the sensors 18 may generate a sensor signal in response to the sensed location, position, and / or orientation. The sensor signal may include sensor data corresponding to the sensed location, position, and / or orientation. For example, the sensor data may include a depth map of the surroundings. In some examples, such as for an augmented reality system, one or more of the sensors 18 may capture real-time video images of the surroundings proximate to the user.

[0059] The visualization system 10 may include one or more image generation processors 20. The one or more image generation processors 20 may receive scene data representing a three-dimensional scene, such as a set of position coordinates for objects in the scene or a depth map of the scene, from a server and / or storage medium. The one or more image generation processors 20 may receive one or more sensor signals from the one or more sensors 18. In response to the scene data representing the surroundings and at least one sensor signal representing the user's location and / or orientation relative to the surroundings, the one or more image generation processors 20 may generate at least one video signal corresponding to a view of the scene. In some examples, the one or more image generation processors 20 may generate two video signals, one for each eye of the user, representing views of the scene from the perspectives of the user's left and right eyes, respectively. In some examples, the one or more image generation processors 20 may generate three or more video signals and combine the video signals to provide one video signal for both eyes, two video signals for both eyes, or other combinations.

[0060] Visualization system 10 may include one or more light sources 22 capable of providing light to a display of visualization system 10. Suitable light sources 22 may include light emitting diodes, monolithic light emitting diodes, multiple light emitting diodes, arrays of light emitting diodes, arrays of light emitting diodes disposed on a common substrate, segmented light emitting diodes having individually addressable and controllable (and / or controllable in groups and / or subsets) light emitting diode elements disposed on a single substrate, arrays of micro light emitting diodes (microLEDs), and others.

[0061] The light emitting diode may be a white light emitting diode. For example, the white light emitting diode may emit excitation light, such as blue light or violet light. The white light emitting diode may include one or more phosphors that can absorb some or all of the excitation light and, in response, emit phosphor light, such as yellow light, having a wavelength longer than the wavelength of the excitation light.

[0062] One or more light sources 22 may include light-generating elements having different colors or wavelengths. For example, a light source may include a red light-emitting diode capable of emitting red light, a green light-emitting diode capable of emitting green light, and a blue light-emitting diode capable of emitting blue light. The red, green, and blue light combine in specific ratios to produce a suitable visually perceptible color within the visible portion of the electromagnetic spectrum.

[0063] The visualization system 10 may include one or more modulators 24. The modulators 24 may be implemented in one of at least two configurations.

[0064] In a first configuration, modulator 24 may include circuitry capable of directly modulating light source 22. For example, light source 22 may include an array of light emitting diodes, and modulator 24 may directly modulate the power, voltage, and / or current directed to each light emitting diode in the array to form modulated light. Modulation may be performed in an analog and / or digital manner. In some examples, light source 22 may include an array of red light emitting diodes, an array of green light emitting diodes, and an array of blue light emitting diodes, and modulator 24 may directly modulate the red light emitting diodes, the green light emitting diodes, and the blue light emitting diodes to form modulated light to generate a specified image.

[0065] In a second configuration, the modulator 24 may include a modulation panel, such as a liquid crystal panel. The light source 22 may generate uniform or nearly uniform illumination to illuminate the modulation panel. The modulation panel may include pixels. Each pixel may selectively attenuate a respective portion of the modulation panel area in response to an electrical modulation signal to form the modulated light. In some examples, the modulator 24 may include multiple modulation panels capable of modulating light of different colors. For example, the modulator 24 may include a red modulation panel capable of attenuating red light from a red light source, such as a red light emitting diode; a green modulation panel capable of attenuating green light from a green light source, such as a green light emitting diode; and a blue modulation panel capable of attenuating blue light from a blue light source, such as a blue light emitting diode.

[0066] In some examples of the second configuration, the modulator 24 can receive uniform or nearly uniform white light from a white light source, such as a white light emitting diode. The modulation panel can include a wavelength-selective filter on each pixel of the modulation panel. The panel pixels can be arranged in groups (e.g., groups of three or four), with each group forming a pixel of a color image. For example, each group can include panel pixels with red color filters, panel pixels with green color filters, and panel pixels with blue color filters. Other suitable configurations can also be used.

[0067] The visualization system 10 may include one or more modulation processors 26 that may receive video signals, such as from one or more image generation processors 20, and in response generate electrical modulation signals. In configurations where the modulators 24 directly modulate the light sources 22, the electrical modulation signals may drive the light sources 22. In configurations where the modulators 24 include a modulation panel, the electrical modulation signals may drive the modulation panel.

[0068] The visualization system 10 may include one or more beam combiners 28 (also known as beam splitters 28) that can combine light beams of different colors to form a single multicolor beam. In configurations where the light source 22 may include multiple light emitting diodes of different colors, the visualization system 10 may include one or more wavelength-sensitive (e.g., dichroic) beam splitters 28 that can combine light of the different colors to form a single multicolor beam.

[0069] The visualization system 10 can direct the modulated light toward a viewer's eyes in one of at least two configurations. In a first configuration, the visualization system 10 can function as a projector and can include suitable projection optics 30 capable of projecting the modulated light onto one or more screens 32. The screens 32 can be placed at a suitable distance from the user's eyes. The visualization system 10 can optionally include one or more lenses 34 capable of positioning the virtual image on the screen 32 at a suitable distance from the eyes, such as a near focus distance of 500 mm, 750 mm, or another suitable distance. In some examples, the visualization system 10 can include a single screen 32 such that the modulated light is directed toward both of the user's eyes. In some examples, the visualization system 10 can include two screens 32 such that the modulated light from each screen 32 is directed toward a respective eye of the user. In some examples, the visualization system 10 can include three or more screens 32. In a second configuration, the visualization system 10 can direct the modulated light directly toward one or both of the viewer's eyes. For example, the projection optical system 30 may form an image on the retina of the user's eye, or may form an image on each of the retinas of both of the user's eyes.

[0070] In some configurations of an augmented reality system, the visualization system 10 may include an at least partially transparent display, allowing a user to see their surroundings through the display. In such configurations, the augmented reality system may generate modulated light that corresponds to an augmentation of the surroundings, rather than the surroundings themselves. For example, in the example of a retailer showing a chair, the augmented reality system may direct modulated light that corresponds to the chair, but not the rest of the room, toward a screen or toward the user's eyes.

[0071] The present disclosure will now be described with reference to the following examples. Before describing certain exemplary embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0072] example Comparative Example 1 A CMOS layout with two current distribution layers was fabricated. The CMOS layout had a U-shaped cathode ring. The current density of the CMOS layout was calculated. As shown in Figure 4A, the current density was not uniform.

[0073] Example 2 A CMOS layout with eight interleaved current distribution regions was fabricated. The current density of the CMOS layout with eight interleaved current distribution regions was calculated. As shown in Figure 4B, the current density was uniform.

[0074] Table 1 shows a comparison of power losses between a CMOS layout of Comparative Example 1 with two current distribution layers and a CMOS layout of Example 2 with a continuous current distribution ring with interleaved regions on the top and bottom panel edges. The power plane layout of one or more embodiments reduces ohmic losses by more than 40%. The average current density through the cathode μ-bump is also much lower. [Table 1]

[0075] Example 3 A CMOS layout was created with eight interleaved current distribution regions. The layout consisted of an outer V cat There was no insulating region between the pad and the outermost μ-bump via. The current density was measured and is shown in Figure 5A.

[0076] Example 4 A CMOS layout was created with eight interleaved current distribution regions. The layout consisted of an outer V cat There was an insulating area between the pad and the outermost μ-bump via. The current density was measured. Figures 5A and 5B show the outer V cat The current density at the cathode μ-bump is compared between a layout with an insulating region between the contact area and the outermost corner μ-bump (Example 4) and a layout without an insulating region (Example 3). The current density at the outermost corner cathode μ-bump in the layout with the insulating region is reduced by more than 30%.

[0077] Embodiment Various embodiments are listed below, and it will be understood that the embodiments listed below can be combined with all aspects and other embodiments in accordance with the scope of the present invention.

[0078] Embodiment (a) A cathode redistribution ring having an inner portion and an outer portion, the inner portion surrounding a die pixel area, and the outer portion supplying a common supply voltage V interleaved with the cathode current distribution area. led and a plurality of cathode μ-bumps contacting the inner portion of the cathode redistribution ring along the periphery of the die pixel area.

[0079] Embodiment (b). The common supply voltage V ledand the cathode current distribution regions are interleaved.

[0080] Embodiment (c) The common supply voltage V led and the cathode current distribution regions are interleaved.

[0081] Embodiment (d). At least three common supply voltages V led is interleaved with at least three cathode current distribution regions.

[0082] Embodiment (e). The CMOS power plane of any one of embodiments (a)-(b), further comprising an insulating region on the cathode redistribution ring adjacent one of the plurality of cathode μ-bumps.

[0083] Embodiment (f). The CMOS power plane of any one of embodiments (a) through (e), wherein the isolation regions have etched lines.

[0084] Embodiment (g). The CMOS power plane of any one of embodiments (a) through (f), wherein the insulating region comprises a dielectric material.

[0085] Embodiment (h). The CMOS power plane of any one of embodiments (a) to (g), further comprising a plurality of PMOS transistors connected to the die pixel regions.

[0086] Embodiment (i). The CMOS power plane of any of embodiments (a) through (h), wherein the plurality of cathode μ-bumps are electrically connected to a common cathode grid.

[0087] Embodiment (j). The CMOS power plane of any one of embodiments (a) to (i), wherein the die pixel region comprises a plurality of pixels.

[0088] Embodiment (k). The CMOS power plane of any one of embodiments (a) to (j), wherein the insulating region has a size greater than 80 μm.

[0089] Embodiment (l). A power plane on a substrate, comprising a plurality of alternating Vs uniformly distributed along at least two sides of the power plane. led a power plane having a contact region and a cathode contact region; a cathode current redistribution ring extending along four sides of the power plane; and a plurality of alternating V led 1. A CMOS layout comprising: a plurality of cathode μ-bumps connecting each of the contact regions and cathode contact regions to corresponding p-contacts of a plurality of pixels; and a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode μ-bumps.

[0090] Embodiment (m). The V on two sides led The CMOS layout of embodiment (l), wherein the contact regions and the cathode contact regions are interleaved.

[0091] Embodiment (n). The V on four sides led The CMOS layout of embodiments (l) through (m), wherein the contact regions and the cathode contact regions are interleaved.

[0092] Embodiment (o). At least three V led The CMOS layout of embodiments (l) through (n), wherein the contact regions alternate with at least three cathode contact regions.

[0093] Embodiment (p). The CMOS layout of any of embodiments (l) through (o), further comprising an insulating region on the cathode current redistribution ring adjacent one of the plurality of cathode μ-bumps.

[0094] Embodiment (q). The CMOS layout of embodiments (l) through (p), wherein the insulating regions have etched lines.

[0095] Embodiment (r). The CMOS layout of any one of embodiments (l) through (q), wherein the insulating region comprises a dielectric material.

[0096] Embodiment (s). The CMOS layout of any one of embodiments (l) to (r), further comprising a plurality of PMOS transistors connected in parallel to at least one of the plurality of pixels.

[0097] Embodiment (t). The CMOS layout of embodiments (l) through (s), wherein the insulating regions have a size greater than 80 μm.

[0098] Embodiment (u). A CMOS power plane, comprising a cathode redistribution ring having an inner portion and an outer portion, the inner portion surrounding a periphery of a die pixel area, the outer portion providing a common supply voltage V V interleaved with cathode current distribution areas along a first edge, a second edge, a third edge, and a fourth edge of the CMOS power plane. led and a plurality of cathode μ-bumps contacting the inner portion of the cathode redistribution ring along the periphery of the die pixel area.

[0099] Embodiment (v). At least three common supply voltages V led The CMOS power plane of embodiment (u), wherein the region is interleaved with at least three cathode current distribution regions.

[0100] Embodiment (w). The CMOS power plane of any one of embodiments (u) to (v), further comprising an insulating region on the cathode redistribution ring adjacent one of the plurality of cathode μ-bumps.

[0101] Embodiment (x). The CMOS power plane of any one of embodiments (u) to (w), wherein the isolation regions have etched lines.

[0102] Embodiment (y). The CMOS power plane of any one of embodiments (u) through (x), wherein the insulating region comprises a dielectric material.

[0103] Embodiment (z). The CMOS power plane of any one of embodiments (u) to (y), further comprising a plurality of PMOS transistors connected to the die pixel regions.

[0104] Embodiment (aa). The CMOS power plane of any one of embodiments (u) to (z), wherein the plurality of cathode μ-bumps are electrically connected to a common cathode grid.

[0105] Embodiment (bb). The CMOS power plane of any one of embodiments (u) to (aa), wherein the die pixel region comprises a plurality of pixels.

[0106] Embodiment (cc). The CMOS power plane of any one of embodiments (u) to (bb), wherein the insulating region has a size greater than 80 μm.

[0107] Embodiment (dd). The CMOS power plane of any one of embodiments (u) through (cc), wherein the insulating region is at least 10 μm away from one of the plurality of cathode μ-bumps.

[0108] Embodiment (ee). A power plane on a substrate, comprising a plurality of alternating Vs distributed along a first side, a second side, a third side, and a fourth side of the power plane. led a power plane having a contact region and a cathode contact region; a cathode current redistribution ring extending along the first side, the second side, the third side, and the fourth side of the power plane; and a plurality of alternating V led 1. A CMOS layout comprising: a plurality of cathode μ-bumps connecting each of the contact regions and cathode contact regions to corresponding p-contacts of a plurality of pixels; and a common cathode grid electrically connecting the plurality of pixels to the plurality of cathode μ-bumps.

[0109] Embodiment (ff). At least three V led The CMOS layout of embodiment (ee), wherein the contact regions alternate with at least three cathode contact regions.

[0110] Embodiment (gg). The CMOS layout of embodiments (ee) through (ff), further comprising an insulating region on the cathode current redistribution ring adjacent one of the plurality of cathode μ-bumps.

[0111] Embodiment (hh). The CMOS layout of embodiments (ee) through (gg), wherein the isolation regions have etched lines.

[0112] Embodiment (ii). The CMOS layout of any one of embodiments (ee) to (hh), further comprising a plurality of PMOS transistors connected in parallel to at least one of the plurality of pixels.

[0113] Embodiment (jj). The CMOS layout of embodiments (ee) through (ii), wherein the insulating regions have a size greater than 80 μm.

[0114] Embodiment (kk). The CMOS layout of embodiments (ee) through (jj), wherein the insulating region is at least 10 μm away from one of the plurality of cathode μ-bumps.

[0115] Embodiment (ll). The CMOS layout of embodiments (ee) through (kk), wherein the insulating region comprises a dielectric material.

[0116] Embodiment (mm) The alternating V led The CMOS layout of embodiments (ee) through (ll), wherein contact regions and cathode contact regions are uniformly distributed along the first side, the second side, the third side, and the fourth side of the power plane.

[0117] Embodiment (nn) A cathode redistribution ring having an inner portion and an outer portion, the inner portion surrounding a die pixel area, and the outer portion supplying a common supply voltage V interleaved with a cathode current distribution area. led a plurality of cathode μ-bumps contacting the inner portion of the cathode redistribution ring along the periphery of the die pixel area; and an insulating region on the cathode redistribution ring adjacent one of the plurality of cathode μ-bumps.

[0118] Embodiment (oo) The common supply voltage V led and the cathode current distribution regions are interleaved.

[0119] Embodiment (pp). The common supply voltage V led and the cathode current distribution regions are interleaved.

[0120] Embodiment (qq). At least three common supply voltages V led The CMOS power plane of any one of embodiments (nn) to (pp), wherein the cathode current distribution regions are interleaved with at least three cathode current distribution regions.

[0121] Embodiment (rr). The CMOS power plane of any one of embodiments (nn) through (qq), wherein the isolation region comprises an etched line.

[0122] Embodiment (ss). The CMOS power plane of any one of embodiments (nn) through (rr), wherein the insulating region comprises a dielectric material.

[0123] Embodiment (tt). The CMOS power plane of embodiments (nn) through (ss), wherein the plurality of cathode μ-bumps are electrically connected to a common cathode grid.

[0124] Embodiment (uu). The CMOS power plane of any one of embodiments (nn) to (tt), wherein the die pixel region comprises a plurality of pixels.

[0125] Embodiment (vv). The CMOS power plane of any one of embodiments (nn) to (uu), wherein the insulating region has a size greater than 80 μm.

[0126] Embodiment (ww). The CMOS power plane of any one of embodiments (nn) through (vv), wherein the insulating region is at least 10 μm away from one of the plurality of cathode μ-bumps.

[0127] Embodiment (xx). 8 common supply voltages V led The CMOS power plane of embodiments (nn) through (ww), wherein the CMOS power plane is interleaved with ten cathode current distribution regions.

[0128] Embodiment (yy): A power plane on a substrate, comprising a plurality of alternating Vs uniformly distributed along at least two sides of the power plane. led a power plane having a contact region and a cathode contact region; a cathode current redistribution ring extending along four sides of the power plane; and a plurality of alternating V led 1. A CMOS layout comprising: a plurality of cathode μ-bumps connecting each of the contact regions and cathode contact regions to a corresponding p-contact of a plurality of pixels; an insulating region on the cathode current redistribution ring adjacent one of the plurality of cathode μ-bumps; and a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode μ-bumps.

[0129] Embodiment (zz). The V on two sides led The CMOS layout of embodiment (yy), wherein the contact regions and the cathode contact regions are interleaved.

[0130] Embodiment (aaa). The V on four sides ledThe CMOS layout of embodiments (yy) through (zz), wherein the contact regions and the cathode contact regions are interleaved.

[0131] Embodiment (bbb). At least three V led The CMOS layout of embodiments (yy) through (aaa), wherein the contact regions alternate with at least three cathode contact regions.

[0132] Embodiment (ccc). The CMOS layout of embodiments (yy) through (bbb), wherein the isolation regions have etched lines.

[0133] Embodiment (ddd). The CMOS layout of embodiments (yy) through (ccc), wherein the insulating region comprises a dielectric material.

[0134] Embodiment (eee). The CMOS layout of embodiments (yy) through (ddd), further comprising a plurality of PMOS transistors connected in parallel to at least one of the plurality of pixels.

[0135] Embodiment (fff). The CMOS layout of embodiments (yy) through (eee), wherein the insulating regions have a size greater than 80 μm.

[0136] Embodiment (ggg). The CMOS layout of embodiments (yy) through (fff), wherein the insulating region is at least 10 μm away from one of the plurality of cathode μ-bumps.

[0137] The use of the terms "a," "an," and "the" and similar designations in the context of describing the materials and methods described herein (particularly in the context of the claims below) should be construed to cover both the singular and the plural, unless otherwise stated herein or clearly contradicted by context. The recitation of ranges of values herein is merely intended to serve as a shorthand method for referring individually to each separate value falling within the range, unless otherwise stated herein, and each separate value is incorporated herein as if it were individually stated herein. All methods described herein can be performed in any suitable order, unless otherwise stated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "for example, etc.") provided herein is intended only to further clarify the materials and methods and does not impose a limitation on the scope unless otherwise asserted. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0138] Although references to terms such as first, second, third, etc. may be used throughout this specification to describe various elements, the elements should not be limited by these terms. These terms may be used to distinguish one element from another.

[0139] Throughout this specification, referring to a layer, region, or substrate as being "on" or extending "onto" another element means that it may be directly on or extending directly onto the other element, or that intervening elements may also be present. When an element is referred to as being "directly on" or extending "directly onto" another element, there may be no intervening elements present. Also, when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element and / or connected or coupled to the other element via one or more intervening elements. When an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements between the element and the other element. It is understood that these terms are intended to encompass the element in different orientations in addition to the orientation depicted in the figures.

[0140] Relative terms such as "below," "above," "upper," "lower," "horizontal," or "vertical" may be used herein to describe the relationship of one element, section, or region to another element, section, or region, as shown in the figures. It is understood that these terms are intended to encompass the device in different orientations in addition to the orientation shown in the figures.

[0141] Throughout this specification, references to "one embodiment," "particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the present disclosure. In one or more embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0142] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made in the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, it is intended that the present disclosure cover such modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. a cathode redistribution ring having an inner portion and an outer portion, the inner portion surrounding a die pixel area, the outer portion being connected to a common supply voltage V interleaved with cathode current distribution areas; ｌｅｄ a cathode redistribution ring having an area; a plurality of cathode μ-bumps contacting the inner portion of the cathode redistribution ring along the periphery of the die pixel area; A CMOS power plane having

2. 10. The CMOS power plane of claim 1, further comprising an insulating region on said cathode redistribution ring adjacent one of said plurality of cathode μ-bumps.

3. The common supply voltage V ｌｅｄ 2. The CMOS power plane of claim 1, wherein regions and said cathode current distribution regions are interleaved.

4. The common supply voltage V ｌｅｄ 2. The CMOS power plane of claim 1, wherein regions and said cathode current distribution regions are interleaved.

5. At least three common supply voltages V ｌｅｄ 10. The CMOS power plane of claim 1, wherein the regions are interleaved with at least three cathode current distribution regions.

6. 2. The CMOS power plane of claim 1, wherein the cathode current distribution regions are along a first edge, a second edge, a third edge, and a fourth edge of the CMOS power plane.

7. 7. The CMOS power plane of claim 6, further comprising an insulating region on said cathode redistribution ring adjacent one of said plurality of cathode μ-bumps.

8. The CMOS power plane of claim 7 wherein the isolation region comprises a line.

9. 8. The CMOS power plane of claim 7, wherein the insulating region comprises a dielectric material.

10. 10. The CMOS power plane of claim 1, further comprising a plurality of PMOS transistors connected to the die pixel regions.

11. 10. The CMOS power plane of claim 1, wherein the plurality of cathode μ-bumps are electrically connected to a common cathode grid.

12. 8. The CMOS power plane of claim 7, wherein the insulating regions have a size greater than 80 [mu]m.

13. a power plane on a substrate, the power plane having a plurality of alternating Vs uniformly distributed along at least two sides of the power plane; ｌｅｄ a power plane having a contact area and a cathode contact area; a cathode current redistribution ring extending along four sides of the power plane; The plurality of alternating V ｌｅｄ a plurality of cathode μ-bumps connecting each of the contact areas and the cathode contact areas to corresponding p-contacts of a plurality of pixels; a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode μ-bumps; A CMOS layout having:

14. 14. The CMOS layout of claim 13, further comprising an insulating region on the cathode current redistribution ring adjacent one of the plurality of cathode μ-bumps.

15. 14. The CMOS layout of claim 13, wherein the cathode contact regions are along a first side, a second side, a third side, and a fourth side of the power plane.

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