Photoelectric conversion device, electronic device and substrate

Abstract

To provide a technology advantageous for improving image quality in a photoelectric conversion device using a delta-sigma AD converter.SOLUTION: A photoelectric conversion device includes a pixel unit in which a plurality of pixels each including a photoelectric conversion element are arranged in a matrix, and a plurality of delta-sigma AD converters that convert signals output from the pixel unit into digital signals, and when the plurality of delta-sigma AD converters convert signals output from pixels selected by a common pixel control line among the plurality of pixels into digital signals, the plurality of delta-sigma AD converters divide the signals into two groups having at least different AD conversion start timings.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device, an electronic device, and a substrate. [Background technology]

[0002] Patent Document 1 discloses a solid-state imaging device that uses a delta-sigma (ΔΣ) analog-to-digital (AD) converter in its analog-to-digital conversion section. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 069614 Summary of the Invention [Problem to be solved by the invention]

[0004] In the solid-state imaging device disclosed in Patent Document 1, multiple ΔΣ AD converters are arranged corresponding to each vertical signal line. When a signal output from a quantizer in a ΔΣ AD converter is inverted, a transient fluctuation may occur in the potential of the power supply or ground connected to the ΔΣ AD converter. Consider a case where the outputs of the quantizers of multiple ΔΣ AD converters change at close timing, such as when signals of similar magnitude are input from pixels to multiple ΔΣ AD converters. In this case, potential fluctuations associated with the operation of the ΔΣ AD converter whose quantizer output is inverted first may cause variations in the timing at which the quantizer outputs of the other ΔΣ AD converters are inverted. Variations in operation among multiple ΔΣ AD converters can reduce the accuracy of AD conversion and result in degradation of the quality of the resulting image.

[0005] An object of the present invention is to provide a technique that is advantageous for improving image quality in a photoelectric conversion device using a ΔΣ AD converter. [Means for solving the problem]

[0006] In view of the above-described problems, a photoelectric conversion device according to an embodiment of the present invention is a photoelectric conversion device including a pixel section in which a plurality of pixels each including a photoelectric conversion element are arranged in a matrix, and a plurality of ΔΣ AD converters that convert signals output from the pixel section into digital signals, wherein the plurality of ΔΣ AD converters are divided into at least two groups that start AD conversion at different timings when converting signals output from pixels selected by a common pixel control line from among the plurality of pixels into digital signals. Each of the plurality of ΔΣ AD converters includes an integrator, a quantizer that compares an output of the integrator with a predetermined voltage, and a decimation filter that generates the digital signal based on a comparison result output from the quantizer, and the plurality of ΔΣ AD converters have different timings for completing the reset operation of the decimation filter between the at least two groups. It is characterized by: [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a technique that is advantageous for improving image quality in a photoelectric conversion device using a ΔΣ AD converter. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing an outline of the configuration of a photoelectric conversion device according to an embodiment of the present invention. [Figure 2] 2 is a block diagram showing an outline of the configuration of a ΔΣ AD converter of the photoelectric conversion device of FIG. 1; [Figure 3] FIG. 2 is a circuit diagram showing an example of the configuration of a pixel of the photoelectric conversion device of FIG. 1. [Figure 4] 2 is a diagram showing an example of the configuration of a ΔΣ AD converter of the photoelectric conversion device of FIG. 1; [Figure 5] 2 is a diagram showing the operation timing of a ΔΣ AD converter of the photoelectric conversion device of FIG. 1. [Figure 6] 2 is a diagram showing the operation timing of a ΔΣ AD converter of the photoelectric conversion device of FIG. 1. [Figure 7] 2 is a diagram showing an example of the configuration of a ΔΣ AD converter of the photoelectric conversion device of FIG. 1; [Figure 8] 2 is a diagram showing the operation timing of a ΔΣ AD converter of the photoelectric conversion device of FIG. 1. [Figure 9] 2 is a diagram showing an example of a supply path of a control signal for the photoelectric conversion device of FIG. 1; [Figure 10] 2 is a diagram showing an example of a supply path of a control signal for the photoelectric conversion device of FIG. 1; [Figure 11] 2 is a diagram showing an example of a supply path of a control signal for the photoelectric conversion device of FIG. 1; [Figure 12] 1. FIG. 4 is a diagram showing the operation timing of a comparative example of the ΔΣ AD converter of the photoelectric conversion device of FIG. [Figure 13] FIG. 1 is a diagram showing an example of the configuration of a camera incorporating a photoelectric conversion device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0010] A photoelectric conversion device according to an embodiment of the present disclosure will be described with reference to Figures 1(a), 1(b) to 12, and 13. Figure 1(a) is a block diagram showing an example configuration of a photoelectric conversion device 100 according to this embodiment. The photoelectric conversion device 100 includes a pixel unit 1, a vertical scanning unit 5, a load transistor unit 6, a sample and hold unit 7, an AD conversion unit 8, a horizontal transfer unit 9, a timing control unit 10, a processing unit 11, and an output unit 12. The photoelectric conversion device 100 may be a so-called CMOS image sensor.

[0011] The pixel section 1 has a plurality of pixels 2, each including a photoelectric conversion element, arranged, for example, in a matrix. Here, the row direction refers to the left-right direction in FIG. 1(a), and the column direction refers to the up-down direction in FIG. 1(a). The pixels 2 generate signal charges in response to incident light. The pixel section 1 has vertical signal lines 4 arranged along the column direction, corresponding to the pixel columns in which the pixels 2 are arranged. The vertical signal lines 4 may be arranged, for example, so that one vertical signal line corresponds to one pixel column, or multiple vertical signal lines may be arranged for one pixel column. The vertical signal lines 4 transfer pixel signals corresponding to the signal charges generated by the photoelectric conversion elements of the pixels 2 from the pixels 2 to the sample-and-hold section 7.

[0012] The vertical scanning unit 5 selects pixels 2 that output signals from among the plurality of pixels 2 arranged in the pixel unit 1 via pixel control lines 3. For example, among the plurality of pixels 2 arranged in a matrix in the pixel unit 1, pixels 2 that are aligned in the row direction can be selected at the same time via a common pixel control line 3. The signals of the pixels 2 selected by the common pixel control line 3 from among the plurality of pixels 2 are transferred to the sample and hold unit 7 at the same time.

[0013] The load transistor section 6 includes current sources arranged corresponding to the respective vertical signal lines 4. The current sources of the load transistor section 6 supply bias currents via the vertical signal lines 4 to the pixels 2 selected to read out signals.

[0014] The sample and hold unit 7 samples and holds the signal generated by the photoelectric conversion element of each pixel 2 from the pixel unit 1 via the vertical signal line 4. For example, in the sample and hold unit 7, two circuits may be connected to one vertical signal line 4: one circuit for sampling the signal when the photoelectric conversion element is reset, and the other circuit for sampling the signal when the photoelectric conversion element performs a photoelectric conversion operation. Using such a configuration makes it easy to perform correlated double sampling (CDS).

[0015] The AD conversion unit 8 performs analog-to-digital conversion on the signal input from the sample-and-hold unit 7. In this embodiment, the AD conversion unit 8 is provided with a plurality of delta-sigma (ΔΣ) analog-to-digital (AD) converters that convert signals output from the pixel unit 1 into digital signals so as to correspond to the respective vertical signal lines 4. The ΔΣ AD converters will be described later.

[0016] The horizontal transfer unit 9 is arranged to sequentially transfer signals output from the AD conversion unit 8 corresponding to each vertical signal line 4 to the processing unit 11. The processing unit 11 processes the digital signals output from the AD conversion unit 8 via the horizontal transfer unit 9. For example, the processing unit 11 may perform correction processing or interpolation processing on the digital signals output from the AD conversion unit 8. The output unit 12 outputs the signals processed by the processing unit 11 from the photoelectric conversion device 100 to the outside.

[0017] The timing control unit 10 controls the driving of each of the above-mentioned components arranged in the photoelectric conversion device 100. By the timing control unit 10 controlling the operation timing of each component arranged in the photoelectric conversion device 100, for example, an imaging operation in the photoelectric conversion device 100 can be performed, and an image can be obtained.

[0018] Here, the photoelectric conversion device 100 may have a configuration in which multiple substrates are stacked. FIG. 1(a) is drawn in a planar manner to show each component of the photoelectric conversion device 100, but, for example, the photoelectric conversion device 100 may include a substrate 13 and a substrate 14 stacked on top of each other, as shown in FIG. 1(b). The substrates 13 and 14 may be arranged so that the two substrates entirely overlap, as shown in FIG. 1(b), or so that they partially overlap. When the substrates 13 and 14 are stacked, for example, as shown in FIGS. 1(a) and 1(b), a plurality of pixels 2 (pixel section 1) arranged in multiple rows and multiple columns are provided on the upper substrate 13, onto which light is incident. The substrate 14 stacked below this substrate 13 is provided with circuits other than the plurality of pixels 2 of the pixel section 1 shown in FIG. 1(a). That is, the substrate 14 is provided with the vertical scanning unit 5, the load transistor unit 6, the sample and hold unit 7, the AD conversion unit 8, the horizontal transfer unit 9, the timing control unit 10, the processing unit 11, and the output unit 12. However, without being limited to this example, a substrate other than the substrates 13 and 14 may be stacked. Also, for example, some of the circuits such as the vertical scanning unit 5 and the timing control unit 10 may be provided on the substrate 13.

[0019] Next, the following description will focus on the pixel 2, sample and hold unit 7, and AD conversion unit 8 of the photoelectric conversion device 100, with reference to Fig. 2. Fig. 2 shows the pixel 2 corresponding to one vertical signal line 4 of the photoelectric conversion device 100, the sample and hold circuit 207 of the sample and hold unit 7, and the ΔΣ AD converter 208 of the AD conversion unit 8. The pixel 2 corresponding to one vertical signal line 4 may be, for example, a plurality of pixels 2 arranged side by side along the column direction of the pixel unit 1 and connected to the same vertical signal line 4 via a switch element.

[0020] The ΔΣ AD converter 208 includes a subtractor 215, an integrator 216, a quantizer 217, a digital-to-analog (DA) converter 218, and a decimation filter 214. The subtractor 215 has an input (+) to which a signal is input from the sample-and-hold circuit 207 of the sample-and-hold unit 7, and an input (−) to which a subtraction signal is input. The integrator 216 receives the output of the subtractor 215, integrates it, and outputs the integrated value to the quantizer 217. The quantizer 217 compares the output of the integrator 216 with a predetermined voltage. If the output of the comparison result signal of the quantizer 217 is 1 bit, the predetermined voltage may be one type. If the output of the quantizer 217 is 2 bits or more, the quantizer 217 compares the output of the integrator 216 with multiple types of voltages and outputs a comparison result. The decimation filter 214 generates a digital signal based on the comparison result output from the quantizer 217 and outputs the digital signal to the processing unit 11 via the horizontal transfer unit 9. The DA converter 218 converts the output of the quantizer 217 into an analog signal and generates a subtraction signal to be output to the input (-) of the subtractor 215. The subtractor 215 calculates the difference between the signal output from the pixel unit 1 (more precisely, the sample and hold circuit 207) and supplied to the input (+) and the subtraction signal supplied to the input (-). By providing the subtractor 215 in the ΔΣ AD converter 208, a previously sampled data value is fed back to the signal output from the pixel unit 1, thereby reducing quantization noise during AD conversion in the ΔΣ AD converter 208.

[0021] 2, the AD conversion unit 8 is also provided with a reset unit 219. The reset unit 219 is provided to reset the integrator 216 and decimation filter 214 of the ΔΣ AD converter 208. One reset unit 219 may be provided for multiple ΔΣ AD converters 208, or a reset unit 219 may be provided in each ΔΣ AD converter 208. Any configuration may be used as long as it is capable of resetting the integrator 216 and decimation filter 214 of the ΔΣ AD converter 208 in the AD conversion unit 8, as will be described later. The operation of the reset unit 219 will be described later.

[0022] FIG. 3 is a circuit diagram showing an example configuration of a pixel 2. The pixel 2 includes a photoelectric conversion element 30, a transfer transistor 31, a reset transistor 32, an amplification transistor 33, and a selection transistor 34. The photoelectric conversion element 30 may be, for example, a photodiode. One of the main electrodes of the photoelectric conversion element 30 is connected to the ground potential GND, and the photoelectric conversion element 30 photoelectrically converts received light into signal charges (e.g., photoelectrons) of an amount corresponding to the amount of light, and stores the signal charges. The other main electrode of the photoelectric conversion element 30 is electrically connected to the gate electrode of the amplification transistor 33 via the transfer transistor 31. A node 35 electrically connected to the gate electrode of the amplification transistor 33 functions as a floating diffusion. The node 35, which functions as a floating diffusion, is a charge-voltage converter that converts the signal charges generated by the photoelectric conversion element 30 into a signal voltage.

[0023] A transfer signal TX is supplied to the gate electrode of the transfer transistor 31 from the vertical scanning unit 5 via the pixel control line 3. When the transfer transistor 31 becomes conductive (ON operation) in response to the transfer signal TX, photoelectric conversion is performed in the photoelectric conversion element 30, and the signal charge accumulated in the photoelectric conversion element 30 is transferred to a node 35 that functions as a floating diffusion.

[0024] The reset transistor 32 is connected between a power supply potential VDD and a node 35. Here, when a transistor is said to be connected between A and B, it means that one of the main electrodes of the transistor is connected to A and the other of the main electrodes is connected to B. Also, when a transistor is said to be connected between A and B, it means that the gate electrode of the transistor is not connected to A or B.

[0025] A reset signal RES is supplied to the gate electrode of the reset transistor 32 from the vertical scanning unit 5 via the pixel control line 3. When the reset transistor 32 becomes conductive in response to the reset signal RES, the potential of the node 35 (floating diffusion) is reset to the power supply potential VDD, and the charge accumulated in the floating diffusion is swept away.

[0026] The amplifier transistor 33 is connected between a power supply potential VDD and the selection transistor 34, and the gate electrode of the amplifier transistor 33 is connected to a node 35. The amplifier transistor 33 serves as an input section of a source follower that reads out a signal obtained by photoelectric conversion of the photoelectric conversion element 30. That is, the other main electrode of the amplifier transistor 33 is connected to the vertical signal line 4 via the selection transistor 34. The amplifier transistor 33 and the current source of the load transistor section 6 connected to the vertical signal line 4 constitute a source follower that converts the voltage of the node 35 into the potential of the vertical signal line 4.

[0027] The selection transistor 34 is connected between the amplification transistor 33 and the vertical signal line 4. A selection signal SEL is supplied to the gate electrode of the selection transistor 34 from the vertical scanning unit 5 via the pixel control line 3. When the selection transistor 34 becomes conductive in response to the selection signal SEL, the pixel 2 is placed in a selected state, and the signal output from the amplification transistor 33 is transmitted to the vertical signal line 4.

[0028] The circuit configuration of the pixel 2 is not limited to the configuration shown in FIG. 3. For example, the selection transistor 34 may be connected between the power supply potential VDD and the amplification transistor 33. In addition, in the configuration shown in FIG. 3, the pixel 2 has a so-called four-transistor (4Tr.) configuration including the transfer transistor 31, the reset transistor 32, the amplification transistor 33, and the selection transistor 34, but the configuration is not limited to this. For example, the pixel 2 may have a three-transistor configuration in which the selection transistor 34 is omitted and the amplification transistor 33 also functions as the selection transistor. Furthermore, depending on the specifications required for the photoelectric conversion device 100, the pixel 2 may have a five-transistor or more configuration in which the number of transistors is increased.

[0029] Next, the circuit configuration of the photoelectric conversion device 100 of this embodiment will be described with reference to Fig. 4. Fig. 4 shows an example of circuits including the pixel 2 connected to one vertical signal line 4, the sample and hold circuit 207 of the sample and hold unit 7, and the ΔΣ AD converter 208 of the AD conversion unit 8.

[0030] The sample and hold circuit 207 shown in FIG. 4 includes a holding circuit 301, an amplifier 302, and a current source 303 and a transistor 304 that constitute a source follower circuit. The sample and hold circuit 207 also includes a holding circuit 305, an amplifier 306, and a current source 307 and a transistor 308 that constitute a source follower circuit. In this embodiment, the sample and hold circuit 207 is configured such that the holding circuit 301 that samples and holds a reset signal and the holding circuit 305 that samples and holds a data signal are connected to one vertical signal line 4. The sample and hold circuit 207 also includes a resistive element 309 that functions as a voltage-to-current converter. With this configuration, the sample and hold circuit 207 supplies the signal output from the pixel 2 of the pixel unit 1 as a current signal to the ΔΣ AD converter 208 of the AD conversion unit 8.

[0031] FIG. 4 shows the configuration of the delta-sigma AD converter 208 that performs second-order delta-sigma modulation. Node 318 corresponds to the subtractor 215 in FIG. 2. The configuration 310 enclosed by the dashed-dotted line corresponds to the integrator 216 and the DA converter 218 in FIG. 2. The operation of the integrator 216 is realized by capacitive elements 312 and 314. The operation of the DA converter 218 is realized by current sources 311 and 313 and switches 316 and 317 that turn on and off the outputs of the current sources 311 and 313 according to the output of the quantizer 217. The Gm amplifier 315 converts a signal input as a voltage value into a current signal. By performing second-order delta-sigma modulation in the delta-sigma AD converter 208, the accuracy of the AD conversion by the delta-sigma AD converter 208 is improved. Furthermore, a delta-sigma AD converter configured to perform even higher-order delta-sigma modulation, such as third-order or higher, may be provided in the AD conversion unit 8.

[0032] 4, the AD conversion unit 8 is provided with the reset unit 219 as described above. The reset unit 219 includes a reset control unit 319 for controlling the reset operation of the decimation filter 214. The reset control unit 319 also resets the capacitive elements 312 and 314 functioning as the integrator 216 via switches 320 and 321. The capacitive elements 312 and 314 are connected to reset potentials 322 and 323 via switches 320 and 321. The reset potentials 322 and 323 may be, for example, the ground potential GND.

[0033] Here, each of the multiple ΔΣ AD converters 208 may have a configuration in which at least one of the number of comparisons in the quantizer 217 and the filter constant of the decimation filter 214 is variable. By changing the number of comparisons in the quantizer 217 and the filter constant of the decimation filter 214, the ΔΣ AD converter 208 is configured to be able to change the resolution of AD conversion. By changing the resolution of AD conversion in accordance with the magnitude of the signal output from the pixel 2, the quality of the resulting image can be improved.

[0034] Next, the effect of the operation of the reset unit 219 of this embodiment will be described. Fig. 5 is a diagram showing the operation timing of the ΔΣ AD converter 208 of the photoelectric conversion device 100 using the reset unit 219 of this embodiment. Before describing the operation of the photoelectric conversion device 100 of this embodiment using Fig. 5, the operation of the photoelectric conversion device 100 of the comparative example will be described using Fig. 12. Fig. 12 shows the operation when the reset operation by the reset unit 219 is performed at approximately the same timing in multiple ΔΣ AD converters 208 included in the AD conversion unit 8 of the photoelectric conversion device 100.

[0035] In FIG. 12, "transfer" indicates a period during which a signal is transferred from the pixel 2 to the sample-and-hold circuit 207. "AD reset" indicates a reset period for the integrator 216 and decimation filter 214 of the ΔΣ AD converter 208 using the reset unit 219. "Subtractor potential" indicates the potential of the subtractor 215. "Quantizer output" indicates a signal output from the quantizer 217. The same applies to other timing diagrams.

[0036] The AD conversion unit 8 is provided with a plurality of ΔΣ AD converters 208 corresponding to a plurality of vertical signal lines 4 for outputting signals from the pixel unit 1. When a signal output from a quantizer 217 in a ΔΣ AD converter 208 is inverted, a transient fluctuation may occur in the power supply potential VDD or the ground potential GND connected to the ΔΣ AD converter 208. Consider a case where the outputs of the quantizers 217 of the many ΔΣ AD converters 208 change at close timing, such as when signals of similar magnitude are input from the pixel 2 to a plurality of ΔΣ AD converters 208. In this case, the timing at which the outputs of the quantizers 217 of the ΔΣ AD converters 208 are inverted may vary due to potential fluctuations caused by the operation of the ΔΣ AD converter 208 whose output is inverted first.

[0037] Variations in the inversion time of the quantizer 217 can cause variations in the output when the ΔΣ AD converter 208 performs AD conversion, which can result in a decrease in the accuracy of the AD conversion in the ΔΣ AD converter 208. Furthermore, fluctuations in the power supply potential VDD and ground potential GND can affect changes in the current output from the DA converter 218 and the sink capacity of the ground potential GND. Variations in the inversion time of the quantizer 217 and the current output from the DA converter 218 can cause variations in the time when the capacitors 312 and 314 functioning as the integrator 216 start charging and the time required to charge to a predetermined potential. Furthermore, changes in the sink capacity of the ground potential GND affect the amount of charge remaining when the capacitors 312 and 314 are reset. As a result, the accuracy of the AD conversion in each ΔΣ AD converter 208 in the AD conversion unit 8 can vary, potentially reducing the quality of the resulting image.

[0038] Furthermore, for example, if the outputs of the quantizers 217 of multiple delta-sigma AD converters 208 are inverted at approximately the same time, the range of transient fluctuations occurring in the ground potential, etc., may become large. If the sample-and-hold circuit 207 is provided with a holding circuit 305 for image data signals, large potential fluctuations may be input to the data signals held in the holding circuit 305 via the common ground potential GND, potentially affecting the data signals. Furthermore, in the delta-sigma AD converter 208, inversion of the quantizer 217 causes charges held in the capacitive elements 312 and 314, which function as the integrator 216, to flow. This makes it easy for potential fluctuations in the ground potential GND to occur, potentially exacerbating the impact of simultaneous operation of multiple delta-sigma AD converters 208, such as multiple quantizers 217 inverting at similar times in multiple delta-sigma AD converters 208.

[0039] To mitigate these effects, the photoelectric conversion device 100 of this embodiment operates as shown in FIG. 5 . Specifically, when converting signals output from pixels 2 selected by a common pixel control line 3 among the multiple pixels 2 into digital signals, the multiple delta-sigma AD converters 208 are divided into at least two groups that start AD conversion at different times. FIG. 5 shows an example in which AD conversion is started by dividing the multiple delta-sigma AD converters 208 into two groups: one that operates in response to an AD reset 1 signal from the reset unit 219, and the other that operates in response to an AD reset 2 signal from the reset unit 219. The multiple delta-sigma AD converters 208 arranged in the AD conversion unit 8 are divided into two or more groups that start AD conversion at different times. This prevents the outputs of the quantizers 217 of the multiple delta-sigma AD converters 208 from being inverted at closely spaced times, for example, when signals of similar magnitude are input from the pixels 2 to the multiple delta-sigma AD converters 208, as shown in FIG. 5 .

[0040] The timings at which the reset operation of the decimation filter 214 is completed may differ between at least two groups of the multiple delta-sigma AD converters 208. That is, as shown in Fig. 5, the AD conversion unit 8 may include a delta-sigma AD converter 208 in which the decimation filter 214 performs a reset operation in accordance with AD reset 1 output from the reset unit 219, and a delta-sigma AD converter 208 in which the decimation filter 214 performs a reset operation in accordance with AD reset 2 output from the reset unit 219. In this case, the reset operations of the capacitive elements 312 and 314 functioning as the integrator 216 may be performed simultaneously regardless of the group, or may be performed at the same timing as the decimation filters 214 arranged in the same delta-sigma AD converter 208.

[0041] Furthermore, the timings at which the reset operations of the capacitive elements 312 and 314 functioning as the integrators 216 are completed may differ between at least two groups of the multiple delta-sigma AD converters 208. That is, the AD converter 208 may include a delta-sigma AD converter 208 in which the capacitive elements 312 and 314 functioning as the integrators 216 perform a reset operation in accordance with AD reset 1 output from the reset unit 219, and a delta-sigma AD converter 208 in which the capacitive elements 312 and 314 functioning as the integrators 216 perform a reset operation in accordance with AD reset 2 output from the reset unit 219. In this case, the reset operations of the decimation filters 214 may be performed simultaneously regardless of the group.

[0042] Furthermore, not only may the timing of starting AD conversion be divided for each group by adjusting the timing of the reset operation of the decimation filter 214 and the integrator 216 of the ΔΣ AD converter 208, but also the timing of transferring signals may be divided for each group. In other words, the timing at which signals output from pixels 2 selected by a common pixel control line 3 among the plurality of pixels 2 and sampled by the sample-and-hold unit 7 are supplied from the sample-and-hold unit 7 to each of the plurality of ΔΣ AD converters 208 may differ from each other between at least two of the above-mentioned groups.

[0043] 6 illustrates a case where the timing at which the current sources 303 and 307 arranged in the sample and hold circuit 207 operate is changed. The sample and hold unit 7 may include a sample and hold circuit 2071 and a sample and hold circuit 2072 arranged corresponding to the delta-sigma AD converters 208 belonging to different groups among the plurality of delta-sigma AD converters 208. The sample and hold circuit 2071 and the sample and hold circuit 2072 each include the above-described current sources 303 and 307 for outputting a signal to the corresponding delta-sigma AD converter 208 among the plurality of delta-sigma AD converters 208. In this case, the timing at which the current sources 303 and 307 of the sample and hold circuit 2071 operate may be different from the timing at which the current sources 303 and 307 of the sample and hold circuit 2072 operate. In the operation shown in Figure 6, for example, a signal may be transferred from the sample and hold circuit 2071 to the ΔΣ AD converter 208 operating in accordance with AD reset 1 shown in Figure 5, and a signal may be transferred from the sample and hold circuit 2072 to the ΔΣ AD converter 208 operating in accordance with AD reset 2.

[0044] The method of dividing the timing of transferring signals from the sample-and-hold circuit 207 to the delta-sigma AD converter 208 into groups is not limited to controlling the current sources 303 and 307. Fig. 7 shows a circuit configuration of the photoelectric conversion device 100 that further includes a plurality of switches 324, 325 (here, a combination of the switch 324 and the switch 325 can also be considered as one switch) arranged between the sample-and-hold unit 7 and the plurality of delta-sigma AD converters 208 so as to correspond to each of the plurality of delta-sigma AD converters 208. When the switch 324 is conductive, the signal is transferred from the sample-and-hold circuit 207 to the delta-sigma AD converter 208. Furthermore, while the switch 324 is non-conductive, the switch 325 is conductive. In other words, the switches 324 and 325 can operate complementarily. The multiple switches 324, 325 are divided into at least two switch groups corresponding to the at least two groups to which the multiple ΔΣ AD converters 208 belong, and the timing at which the multiple switches 324, 325 conduct may differ from each other between the at least two switch groups.

[0045] 8 shows the operation timing of the photoelectric conversion device 100 having the configuration shown in FIG. 7. The sample and hold unit 7 may include a sample and hold circuit 2071 and a sample and hold circuit 2072 arranged corresponding to the delta sigma AD converters 208 belonging to different groups among the plurality of delta sigma AD converters 208. The sample and hold circuit 2071 and the sample and hold circuit 2072 each include the above-mentioned switches 324 and 325. In this case, the operation timing of the switches 324 and 325 of the sample and hold circuit 2071 may be different from the operation timing of the switches 324 and 325 of the sample and hold circuit 2072. In the operation shown in FIG. 8, for example, a signal may be transferred from the sample and hold circuit 2071 to the delta sigma AD converter 208 operating in accordance with AD reset 1 shown in FIG. 5, and a signal may be transferred from the sample and hold circuit 2072 to the delta sigma AD converter 208 operating in accordance with AD reset 2.

[0046] Next, control from the timing control unit 10 that controls the operation timing of the reset unit 219 of the AD conversion unit 8 in which multiple ΔΣ AD converters 208 are arranged will be described. As described above, in order to operate the multiple ΔΣ AD converters 208 by dividing them into at least two groups having different AD conversion start timings, the phases of clocks that control the driving of each of the multiple ΔΣ AD converters 208 may be different depending on which of the at least two groups the converter belongs to. In other words, the timing control unit 10 may supply clocks with different phases to the multiple ΔΣ AD converters 208 arranged in the AD conversion unit 8. Furthermore, for example, the timing control unit 10 may be configured to supply control signals that control the reset operations of the decimation filter 214 and the integrator 216 via the reset unit 219 at different timings between the at least two groups. 9, supply lines 903 and 904 for supplying control signals from the timing control unit 10 to the plurality of delta-sigma AD converters 208 may be provided for each of groups 901 and 902 of the plurality of delta-sigma AD converters 208. With the configuration shown in FIG. 9, the timing control unit 10 can supply clocks and control signals to the delta-sigma AD converters 208 for differentiating the timing of AD conversion for each of groups 901 and 902.

[0047] 10 , a buffer circuit 1001 may be provided on a supply line 903, which supplies control signals from the timing control unit 10 to the plurality of delta-sigma AD converters 208, between nodes connected to the delta-sigma AD converters 208 belonging to different groups 901 and 902 among the plurality of delta-sigma AD converters 208. The buffer circuit 1001 delays the signal supplied from the timing control unit 10 to the delta-sigma AD converters 208 for each of the groups 901 and 902, thereby changing the timing at which AD conversion starts. Furthermore, as shown in FIG. 11 , a buffer circuit 1101 may be provided between the buffer circuit 1001 and the delta-sigma AD converters 208 belonging to the same group 901 or 902. The buffer circuit 1101 suppresses attenuation of the clock and control signals supplied from the timing control unit 10, thereby more reliably operating each of the delta-sigma AD converters 208, thereby improving the accuracy of AD conversion.

[0048] The delta-sigma AD converters belonging to different groups among the multiple delta-sigma AD converters 208 may be arranged adjacent to each other. By having adjacent delta-sigma AD converters 208 belong to different groups, it becomes possible to distribute large noise that occurs when many quantizers 217 invert at close timings.

[0049] Alternatively, for example, among the plurality of ΔΣ AD converters 208, ΔΣ AD converters belonging to different groups may be selected by a common pixel control line 3 from among the plurality of pixels 2 and convert signals output from pixels having color filters of the same color into digital signals. When pixels 2 are adjacent to each other, signals output from color filters of the same color are likely to have similar signal values. Therefore, by making these ΔΣ AD converters 208 belong to different groups, it is possible to distribute the large noise caused by multiple quantizers 217 inverting at close timing. In this case, these ΔΣ AD converters 208 may be arranged adjacent to each other.

[0050] Here, the difference in timing at which the delta-sigma AD converters 208 belonging to different groups start AD conversion may be 0.1 msec or more, 0.2 msec or more, or 0.3 msec or more. For example, the difference in timing at which the delta-sigma AD converters 208 belonging to different groups start AD conversion may be 0.1 msec or more. In other words, one delta-sigma AD converter 208 among the multiple delta-sigma AD converters 208 may start AD conversion 0.1 msec or more after another delta-sigma AD converter 208 starts AD conversion.

[0051] Furthermore, for example, the time it takes for each of the multiple delta-sigma AD converters 208 to convert one analog signal into a digital signal is defined as the first time. In this case, the difference in timing at which the delta-sigma AD converters 208 belonging to different groups among the multiple delta-sigma AD converters 208 start AD conversion may be 10% or more, 20% or more, or 30% or more of the first time. In this way, the difference in timing at which the delta-sigma AD converters 208 belonging to different groups among the multiple delta-sigma AD converters 208 start AD conversion may be longer than the delay time of the circuits in the readout of signals from the pixel unit 1, the sample-and-hold unit 7, and the AD conversion unit 8.

[0052] As described above, when converting signals output from pixels 2 selected from among a plurality of pixels 2 via a common pixel control line 3 into digital signals, the photoelectric conversion device 100 of this embodiment operates the ΔΣ AD converters 208 by dividing the pixels into at least two groups with different AD conversion start timings. This reduces the effects of potential fluctuations and other factors that occur during the operation of the ΔΣ AD converters 208, improving the accuracy of the AD conversion. As a result, the photoelectric conversion device 100 using the ΔΣ AD converters 208 can improve the quality of images obtained. Furthermore, although the above description has mainly focused on dividing the ΔΣ AD converters 208 arranged in the AD conversion unit 8 into two groups with different operation timings, this is not limiting. The plurality of ΔΣ AD converters 208 arranged in the AD conversion unit 8 may also be divided into three or more groups, with operations such as resetting controlled separately.

[0053] Here, an application example of the photoelectric conversion device 100 according to the above-described embodiment will be described below. FIG. 13 is a schematic diagram of an electronic device EQP equipped with the photoelectric conversion device 100. FIG. 13 shows a camera as an example of the electronic device EQP. Here, the concept of a camera includes not only a device whose main purpose is to take pictures, but also a device that has an auxiliary photography function (for example, a personal computer or a mobile terminal such as a smartphone).

[0054] The photoelectric conversion device 100 may be a semiconductor chip with a stacked structure in which a pixel unit 1 is provided. As shown in FIG. 13 , the photoelectric conversion device 100 is housed in a semiconductor package PKG. The package PKG may include a base on which the photoelectric conversion device 100 is fixed, a cover such as glass facing the photoelectric conversion device 100, and conductive connecting members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the photoelectric conversion device 100. The equipment EQP may further include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, and a memory device MMRY.

[0055] The optical system OPT is a component for forming an image on the photoelectric conversion device 100 and may be, for example, a lens, a shutter, or a mirror. The control device CTRL controls the operation of the photoelectric conversion device 100 and may be, for example, a semiconductor device such as an ASIC. The processing device PRCS processes signals output from the photoelectric conversion device 100 and may be, for example, a semiconductor device such as a CPU or an ASIC. The display device DSPL may be an EL display device or a liquid crystal display device that displays image data obtained by the photoelectric conversion device 100. The memory device MMRY is a magnetic device or a semiconductor device that stores image data obtained by the photoelectric conversion device 100. The memory device MMRY may be a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving or propulsive part such as a motor or an engine. The mechanical device MCHN in a camera can drive components of the optical system OPT for zooming, focusing, and shutter operation. The device EQP displays the image data output from the photoelectric conversion device 100 on the display device DSPL, or transmits it to the outside via a communication device (not shown) included in the device EQP. For this reason, the device EQP may include a memory device MMRY and a processing device PRCS.

[0056] A camera incorporating the photoelectric conversion device 100 can be used as a surveillance camera or an on-board camera mounted on transportation equipment such as automobiles, railroad cars, ships, aircraft, or industrial robots. In addition, a camera incorporating the photoelectric conversion device 100 can be used not only in transportation equipment but also in a wide range of equipment that uses object recognition, such as intelligent transport systems (ITS).

[0057] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0058] 1: pixel section, 2: pixel, 3: pixel control line, 208: ΔΣ type AD converter

Claims

1. a pixel section in which a plurality of pixels, each including a photoelectric conversion element, are arranged in a matrix; a plurality of ΔΣ type AD converters for converting signals output from the pixel units into digital signals, the plurality of ΔΣ AD converters are divided into at least two groups having different timings for starting AD conversion when converting signals output from pixels selected by a common pixel control line among the plurality of pixels into digital signals; each of the plurality of ΔΣ AD converters includes an integrator, a quantizer that compares an output of the integrator with a predetermined voltage, and a decimation filter that generates the digital signal based on a comparison result output from the quantizer; The photoelectric conversion device according to the present invention, wherein the plurality of ΔΣ AD converters have different timings for completing the reset operation of the decimation filters between the at least two groups.

2. 2. The photoelectric conversion device according to claim 1, wherein the plurality of ΔΣ AD converters further differ from each other in timing at which the reset operation of the integrator is completed between the at least two groups.

3. A pixel section in which a plurality of pixels each including a photoelectric conversion element are arranged in a matrix; a plurality of ΔΣ type AD converters for converting signals output from the pixel units into digital signals, the plurality of ΔΣ AD converters are divided into at least two groups having different timings for starting AD conversion when converting signals output from pixels selected by a common pixel control line among the plurality of pixels into digital signals; each of the plurality of ΔΣ AD converters includes an integrator, a quantizer that compares an output of the integrator with a predetermined voltage, and a decimation filter that generates the digital signal based on a comparison result output from the quantizer; The photoelectric conversion device according to the present invention, wherein the timings at which the reset operations of the integrators of the plurality of ΔΣ AD converters are completed differ between the at least two groups.

4. Each of the plurality of ΔΣ type AD converters further includes a subtractor having a first input to which a signal output from the pixel unit is input and a second input to which a subtraction signal is input, and a DA converter that converts the output of the quantizer into an analog signal and generates the subtraction signal, 4. The photoelectric conversion device according to claim 1, wherein the integrator receives an output from the subtractor.

5. A photoelectric conversion device as described in any one of claims 1 to 4, characterized in that each of the multiple ΔΣ type AD converters is configured to be able to change the AD conversion resolution by changing at least one of the number of comparisons in the quantizer and the filter constant of the decimation filter.

6. 6. A photoelectric conversion device according to claim 1, wherein the phases of clocks controlling the driving of each of the plurality of ΔΣ AD converters are different between the at least two groups.

7. a timing control unit that controls driving of the plurality of ΔΣ AD converters; and a supply line that supplies control signals from the timing control unit to the plurality of ΔΣ AD converters, A photoelectric conversion device as described in any one of claims 1 to 6, characterized in that a buffer circuit is arranged between nodes on the supply line to which ΔΣ type AD converters belonging to different groups among the plurality of ΔΣ type AD converters are connected.

8. further including a timing control unit that controls driving of the plurality of ΔΣ AD converters; 6. The photoelectric conversion device according to claim 1, wherein the timing control section supplies a control signal for controlling the reset operation to the at least two groups at different timings.

9. a sample and hold unit between the pixel unit and the plurality of ΔΣ type AD converters; A photoelectric conversion device as described in any one of claims 1 to 8, characterized in that the timing at which a signal output from a pixel selected from the plurality of pixels by the common pixel control line and sampled in the sample-and-hold unit is supplied from the sample-and-hold unit to each of the plurality of ΔΣ type AD converters is different between the at least two groups.

10. further comprising a plurality of switches disposed between the sample hold unit and the plurality of ΔΣ AD converters so as to correspond to the plurality of ΔΣ AD converters, the plurality of switches are divided into at least two switch groups corresponding to the at least two groups to which the plurality of ΔΣ AD converters belong; 10. The photoelectric conversion device according to claim 9, wherein the timings at which the plurality of switches are turned on are different between the at least two switch groups.

11. the sample-and-hold unit includes a first sample-and-hold circuit and a second sample-and-hold circuit arranged corresponding to the ΔΣ AD converters belonging to different groups among the plurality of ΔΣ AD converters; the first sample-and-hold circuit and the second sample-and-hold circuit each include a current source for outputting a signal to a corresponding one of the plurality of ΔΣ AD converters; 11. The photoelectric conversion device according to claim 9, wherein the timing at which the current source of the first sample-and-hold circuit operates is different from the timing at which the current source of the second sample-and-hold circuit operates.

12. A photoelectric conversion device as described in any one of claims 1 to 11, characterized in that a first ΔΣ type AD converter and a second ΔΣ type AD converter belonging to different groups among the plurality of ΔΣ type AD converters are arranged adjacent to each other.

13. The photoelectric conversion device described in claim 12, characterized in that the first ΔΣ type AD converter and the second ΔΣ type AD converter convert signals output from pixels selected by a common pixel control line among the plurality of pixels and having color filters of the same color into digital signals.

14. A photoelectric conversion device described in any one of claims 1 to 13, characterized in that a third ΔΣ type AD converter and a fourth ΔΣ type AD converter belonging to different groups among the plurality of ΔΣ type AD converters are selected by a common pixel control line among the plurality of pixels, and convert signals output from pixels having color filters of the same color into digital signals.

15. A photoelectric conversion device according to any one of claims 1 to 14, characterized in that the timing at which the ΔΣ type AD converters belonging to different groups among the plurality of ΔΣ type AD converters start AD conversion differs by 0.1 msec or more.

16. a first time is defined as a time required for each of the plurality of ΔΣ AD converters to convert one analog signal into the digital signal, A photoelectric conversion device described in any one of claims 1 to 15, characterized in that the timing at which ΔΣ type AD converters belonging to different groups among the plurality of ΔΣ type AD converters start AD conversion differs by more than 10% of the first time.

17. The photoelectric conversion device according to any one of claims 1 to 16, a control device that controls the operation of the photoelectric conversion device; An electronic device comprising:

18. A substrate laminated on a substrate provided with a pixel portion in which a plurality of pixels each including a photoelectric conversion element are arranged in a matrix, a plurality of ΔΣ AD converters that convert signals output from the pixel units into digital signals; the plurality of ΔΣ AD converters are divided into at least two groups having different timings for starting AD conversion when converting signals output from pixels selected by a common pixel control line among the plurality of pixels into digital signals; each of the plurality of ΔΣ AD converters includes an integrator, a quantizer that compares an output of the integrator with a predetermined voltage, and a decimation filter that generates the digital signal based on a comparison result output from the quantizer; The substrate is characterized in that the timings at which the reset operation of the decimation filters of the plurality of ΔΣ AD converters ends are different between the at least two groups.

19. A substrate laminated on a substrate having a pixel portion in which a plurality of pixels, each including a photoelectric conversion element, are arranged in a matrix, comprising: a plurality of ΔΣ AD converters that convert signals output from the pixel units into digital signals; the plurality of ΔΣ AD converters are divided into at least two groups having different timings for starting AD conversion when converting signals output from pixels selected by a common pixel control line among the plurality of pixels into digital signals; each of the plurality of ΔΣ AD converters includes an integrator, a quantizer that compares an output of the integrator with a predetermined voltage, and a decimation filter that generates the digital signal based on a comparison result output from the quantizer; The substrate is characterized in that the timings at which the reset operations of the integrators of the plurality of ΔΣ AD converters end are different between the at least two groups.

20. Each of the plurality of ΔΣ type AD converters further includes a subtractor having a first input to which a signal output from the pixel unit is input and a second input to which a subtraction signal is input, and a DA converter that converts the output of the quantizer into an analog signal to generate the subtraction signal, 20. The substrate of claim 18 or 19, wherein the integrator receives the output of the subtractor.

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