Accelerator state control device, accelerator state control system, accelerator state control method and program

Abstract

An accelerator state control device (100) comprises: an input amount acquisition / prediction unit (110) that predicts a processing amount to be offloaded to an accelerator (12) and outputs the prediction result as a traffic amount and the fluctuation range thereof; a processing capacity setting recording unit (150) that holds information regarding accelerator types and models and setting information corresponding to processing capacity as list information and, in response to an inquiry, extracts information from the list information and responds; an ACC processing capacity / power consumption setting determination unit (120) that uses the traffic amount, the fluctuation range, and the list information as a basis to determine setting information regarding the processing capacity and fluctuation time of the accelerator; and an ACC processing capacity / power consumption setting introduction unit (130) that causes the setting information to be reflected in the accelerator (12) on the basis of the setting information destined for the accelerator (12) determined by the ACC processing capacity / power consumption setting determination unit (120).

Description

[Technical Field]

[0001] The present invention relates to an accelerator state control device, an accelerator state control system, an accelerator state control method, and a program. [Background technology]

[0002] Different types of processors excel at different workloads (high processing power). While general-purpose central processing units (CPUs) are capable of handling highly parallel workloads that CPUs struggle with (low processing power), accelerators such as field programmable gate arrays (FPGAs), graphics processing units (GPUs), and application-specific integrated circuits (ASICs) (hereafter referred to as ACCs) can handle these workloads with high speed and efficiency. By combining these heterogeneous processors and offloading workloads that CPUs struggle with to the ACCs, offloading these workloads is becoming increasingly common, improving overall computing time and efficiency.

[0003] In vRAN (virtual Radio Access Network), when the CPU alone does not have enough performance to meet the requirements, some processing is offloaded to accelerators capable of high-speed calculations such as FPGAs and GPUs. Typical examples of workloads that are subject to ACC offloading include encoding / decoding processing (FEC: Forward Error Correction processing) in vRAN, audio and video media processing, and encryption / decryption processing.

[0004] In computer systems, a computer (hereafter referred to as an accelerator-equipped server) may be configured to have hardware (CPU) capable of general-purpose processing and hardware (accelerator) specialized for specific calculations, with some calculation processing offloaded from the general-purpose processor running the software to the accelerator.

[0005] Furthermore, with the advancement of cloud computing, it is becoming common to simplify the configuration of client machines by offloading some of the computationally intensive processing from client machines deployed at user sites to servers at remote sites (such as data centers located near the users) via a network (NW).

[0006] FIG. 17 is a diagram illustrating a computer system. 17, a server 50 is equipped with a CPU 11, an accelerator 12 having an accelerator arithmetic circuit / program 12a, an input / output unit 13, and a cooling mechanism (such as a fan) 14 on hardware 10, and is provided with an application (hereinafter, referred to as APL as appropriate) 1 of software 20 that runs on the CPU 11 on the server 50. Note that although an example in which the cooling mechanism (such as a fan) 14 is equipped on the hardware 10 in FIG. 17 is shown, it may be equipped on hardware separate from the hardware 10.

[0007] The server 50 receives input data from the outside, performs calculation processing within the server, and then outputs the data to the outside.

[0008] The application 1 calls a set of functions (API) defined as a standard and offloads part of the processing to the accelerator 12.

[0009] The accelerator 12 is a calculation accelerator device such as an FPGA / GPU, etc. The accelerator 12 has an accelerator arithmetic circuit program 12a and performs calculations using the accelerator arithmetic circuit program 12a. It should be noted that there is a certain probability that the accelerator 12 will fail due to a cooling fan failure or the like. The input / output unit 13 receives and outputs input data.

[0010] FIG. 18 is a diagram illustrating fluctuations in the traffic volume of input data to the input / output unit 13 of the server 50. In FIG. The traffic volume of input data varies over time as shown in Fig. 18. For example, traffic in urban areas in a Radio Access Network (RAN) is high during the day and low at night.

[0011] In the server 50, the requirements for minimizing the power consumption of the accelerator 12 and its cooling while maintaining responsiveness to input data within a certain time are as follows. Requirement 1: [Power efficiency] The power consumption required for the calculation and cooling of the accelerator 12 for the input data of the server 50 is minimized.

[0012] Requirement 2: [Responsiveness] Processing of input data by the server 50 is completed within a certain period of time after input.

[0013] Requirement 3: [Support for various accelerators] Support for various accelerators such as FPGA, ASIC, and GPU.

[0014] FIG. 19 shows the server processing capacity and surplus when the amount of input data traffic fluctuates. The solid line in FIG. 19 indicates the amount of input data traffic, and the dashed line in FIG. 19 indicates the server processing capacity (≒ power consumption). As shown by the dashed lines in FIG. 19, the server processing capacity and power consumption are constant. Therefore, as shown by the solid line in FIG. 19, surplus occurs with respect to the server processing capacity due to traffic fluctuations. In particular, at night, when the amount of traffic is low, the server processing capacity (≒ power consumption) becomes excessive, resulting in power inefficiency.

[0015] In accelerator-equipped servers, there are conventional technologies that achieve high responsiveness and power efficiency for each accelerator type, with a certain amount of processing capacity as the target.

[0016] Existing technology 1: Power-saving circuit design technology tailored to specific traffic volumes Non-Patent Document 1 describes a technology for minimizing ACC power consumption by optimizing and minimizing the minimum circuit scale required for each specific processing amount and model in FPGA / ASIC circuit design.

[0017] Existing technology 2: Changing the clock frequency to change the balance between processing power and power consumption Non-Patent Document 2 describes a technology that changes the balance between processing performance and power consumption by changing the operating frequency (which remains constant after being set).

[0018] Existing technology 3: Setting the output power of the cooling mechanism required for stable accelerator operation Non-Patent Document 3 describes a configuration in which the fan is always operated at maximum output in order to ensure stable operation regardless of the operating circuit information. [Prior art documents] [Non-patent literature]

[0019] [Non-Patent Document 1] “Power-aware FPGA Design White Paper”, [online], [Retrieved July 6, 2022], Internet〈URL: https: / / www.microsemi.com / document-portal / doc_download / 131579-power-aware-fpga-design-white-paper〉 [Non-patent document 2] "FPGA Frequency Setting Change Command Guide (Intel OPAE Tool Kit)", [online], [Retrieved July 6, 2022], Internet〈URL: https: / / opae.github.io / latest / docs / fpga_tools / userclk / userclk.html〉 [Non-patent document 3] “Intel N3000 Server Configuration Guide”, [online], [Retrieved July 6, 2022], Internet〈URL: https: / / jp.fujitsu.com / platform / server / primergy / products / note / svsdvd / dvd / pdf / intelpac_n3000-qsg-1.1-jp.pdf〉 Summary of the Invention [Problem to be solved by the invention]

[0020] The existing technologies described in Non-Patent Documents 1 to 3 can achieve a configuration that maintains responsiveness and is highly power-efficient by preparing and configuring settings corresponding to a certain amount of processing volume for each accelerator. However, when the input volume fluctuates over time, excess processing capacity and power consumption arise, and there is a problem that requirement 1: [power efficiency], requirement 2: [responsiveness], and requirement 3: [support for various accelerators] cannot be simultaneously met for fluctuating traffic.

[0021] The present invention was made in light of this background, and its objective is to achieve high power efficiency for various accelerators while ensuring responsiveness in response to fluctuating amounts of input data. [Means for solving the problem]

[0022] In order to solve the above-mentioned problems, the present invention provides an accelerator state control device that controls the state of an accelerator when specific processing of an application is offloaded to an accelerator for computational processing, the accelerator state control device comprising: a prediction unit that predicts fluctuations in the amount of input data based on the amount of input data acquired and outputs the prediction result as a traffic volume and its fluctuation range; a processing capacity setting recording unit that holds information on the accelerator type and model and setting information according to processing performance as list information and extracts it from the list information in response to an inquiry; a determination unit that determines setting information for the accelerator's processing capacity and fluctuation time based on the traffic volume and its fluctuation range output from the prediction unit and the list information read from the processing capacity setting recording unit; and a setting input unit that reflects the setting information for the accelerator determined by the determination unit in the accelerator. [Effects of the Invention]

[0023] According to the present invention, it is possible to achieve high power efficiency for various accelerators while ensuring responsiveness in response to fluctuating amounts of input data. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a schematic configuration diagram of an accelerator state control system according to an embodiment of the present invention; [Figure 2] 1 is a schematic configuration diagram showing variations in the arrangement of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention. FIG. [Figure 3] FIG. 2 is a diagram illustrating a list of power reduction techniques for an accelerator state control device in the accelerator state control system according to the embodiment of the present invention. [Figure 4] 1 is a diagram showing an example of processing capacity-based circuit information held by a processing capacity-based ACC circuit information recording unit of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention; [Figure 5]1 is a diagram showing a processing performance calculation table based on traffic volume held in a processing capacity-specific ACC circuit information recording unit of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention. FIG. [Figure 6] 1 is a diagram showing an accelerator mounting relationship management table held by a processing capacity-based ACC circuit information recording unit of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention. FIG. [Figure 7] 1 is a diagram showing an accelerator list management table held by a processing capacity-based ACC circuit information recording unit of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention. FIG. [Figure 8] 1 is a diagram showing an accelerator type management table held by a processing capacity-based ACC circuit information recording unit of an accelerator state control device of an accelerator state control system according to an embodiment of the present invention. FIG. [Figure 9] 10 is a flowchart showing an <operation sequence 1> when power saving control of the accelerator state control device of the accelerator state control system according to the embodiment of the present invention starts with prediction of the input amount of function 1. [Figure 10] 10 is a flowchart showing an <operation sequence 2> when power saving control of the accelerator state control device of the accelerator state control system according to the embodiment of the present invention starts with periodic execution. [Figure 11] FIG. 10 is a diagram showing details of a list of power reduction techniques for an accelerator state control device of the accelerator state control system according to the embodiment of the present invention. [Figure 12A] 10 is a flowchart showing an example of a setting sequence of a power reduction method for an accelerator state control device of the accelerator state control system according to the embodiment of the present invention. [Figure 12B] 10 is a flowchart showing an example of a setting sequence of a power reduction method for an accelerator state control device of the accelerator state control system according to the embodiment of the present invention. [Figure 12C]10 is a flowchart showing an example of a setting sequence of a power reduction method for an accelerator state control device of the accelerator state control system according to the embodiment of the present invention. [Figure 13] 3 is a flowchart showing an operation sequence 1 of the Look-Aside type accelerator state control device of the accelerator state control system according to the embodiment of the present invention. [Figure 14] 1 is a flowchart showing an operation sequence 1 of the inline type accelerator state control device of the accelerator state control system according to the embodiment of the present invention. [Figure 15] 1 is a diagram illustrating the processing capacity, power consumption, and surplus realized by an accelerator state control device of an accelerator state control system according to an embodiment of the present invention. FIG. [Figure 16] FIG. 2 is a hardware configuration diagram illustrating an example of a computer that realizes the functions of an accelerator state control device of the accelerator state control system according to the embodiment of the present invention. [Figure 17] FIG. 1 is a diagram illustrating a computer system. [Figure 18] 10A and 10B are diagrams illustrating fluctuations in the traffic volume of input data to an input / output unit of a server. [Figure 19] FIG. 10 is a diagram showing the processing capacity and surplus of a server in response to fluctuations in the traffic volume of input data. DETAILED DESCRIPTION OF THE INVENTION

[0025] An accelerator state control system and the like in an embodiment of the present invention (hereinafter referred to as "the present embodiment") will be described below with reference to the drawings. (Embodiment) [overview] FIG. 1 is a schematic configuration diagram of an accelerator state control system according to an embodiment of the present invention. As shown in FIG. 1, the accelerator state control system 1000 includes a server 200, an antenna device 210, and a post-processing device 220. The accelerator state control system 1000 also includes an accelerator state control device 100 that controls the state of the accelerator 12 when specific processing of the application 1 is offloaded to the accelerator 12 for computational processing, and a cooling mechanism 14 that cools the computational device including the accelerator 12.

[0026] [Server 200] Server 200 is a distributed unit in 5G signal processing. The server 200 includes hardware (HW) 10 and software 20.

[0027] Hardware 10 The hardware 10 includes a CPU (Central Processing Unit) 11, an accelerator 12, an input / output unit 13, and a cooling mechanism (such as a fan) 14.

[0028] <cpu11> The CPU 11 executes the processing of the application 1 and also executes the software of each functional unit in the server 200 .

[0029] <Accelerator 12> The accelerator 12 is a calculation accelerator device such as an FPGA / GPU. The accelerator 12 is a computing device specialized for a specific process, installed in the server 200. The accelerator 12 may be connected to the CPU 11 via a bus in the form of an ASIC-equipped accelerator, an FPGA-equipped accelerator, a GPU, or the like.

[0030] The data processed by the accelerator 12 may be input from the CPU 11 in a look-aside format (sequence 2-1: FIG. 13) or may be input directly from an input / output unit 13 such as a NIC in an in-line format (sequence 2-2: FIG. 14). The signal line indicated by the arrow from the CPU 11 to the accelerator 12 in FIG. 1 exists in the case of the look-aside type ACC offload format shown in (sequence 2-1: FIG. 13). Also, the bidirectional signal line connecting the input / output unit 13 and the accelerator 12 in FIG. 1 exists in the case of the in-line type ACC offload format shown in (sequence 2-2: FIG. 14).

[0031] The accelerator 12 has an accelerator arithmetic circuit program 12a. The accelerator arithmetic circuit program 12a is a circuit or program loaded into the accelerator 12. The accelerator arithmetic circuit program 12a refers to FPGA circuit information if the accelerator 12 is an FPGA, or refers to a program for the GPU if the accelerator 12 is a GPU. The accelerator 12 may fail at a certain probability due to a malfunction of the cooling mechanism (fan, etc.) 14 or the like.

[0032] <I / O section 13> The input / output unit 13 is an input / output mechanism such as a NIC (Network Interface Card), and performs data input / output with external devices (the antenna device 210 and the post-processing device 220). The input / output unit 13 also has an interface that notifies the application 1 of the current amount of data input.

[0033] <Cooling mechanism 14> The cooling mechanism 14 is a mechanism that cools the entirety of each computing device (CPU 11 and accelerator 12) of the server 200. The cooling performance of the cooling mechanism 14 can be changed, and the power consumption changes accordingly. The cooling mechanism 14 receives the setting of the cooling performance as an input.

[0034] The cooling mechanism 14 is a mechanism that cools the entire server, including the CPU and accelerators, all at once, but may also be an independent cooling mechanism that cools only the CPU or only the accelerators.

[0035] "Software 20" The software 20 includes an application 1 and an accelerator state control device 100 that controls the state of the accelerator.

[0036] <Application 1> The application 1 is a program that performs signal processing and runs on the CPU 11. Dedicated processing that is not suitable for the CPU, such as some parallel calculation processing, is offloaded to the accelerator 12. For example, the application 1 calls a set of functions (API) defined as a standard and offloads some of the processing to the accelerator 12. Here, when the accelerator setting is changed, if the accelerator becomes temporarily unavailable, offloading is performed to the ACC switching time processing continuation unit 160.

[0037] The application 1 receives, as input, data to be processed from the input / output unit 13. As output, the application 1 passes calculated data to the input / output unit 13.

[0038] [Accelerator state control device 100] The accelerator state control device 100 includes an input amount acquisition and prediction unit 110 (prediction unit, prediction procedure), an ACC processing capacity and power consumption setting judgment unit 120 (judgment unit, judgment procedure), an ACC processing capacity and power consumption setting input unit 130 (setting input unit, setting input procedure), an ACC circuit information recording unit by processing capacity 140, an ACC information and processing capacity setting recording unit 150 (processing capacity setting recording unit, processing capacity setting recording procedure), and an ACC switching processing continuation unit 160 (processing continuation unit).

[0039] <Input Amount Acquisition / Prediction Unit 110> The input amount acquisition / prediction unit 110 predicts the processing amount to be offloaded to the accelerator and outputs the prediction result as the traffic amount and its fluctuation range. In this embodiment, the input amount acquisition / prediction unit 110 predicts fluctuations in the input data amount as one mode for predicting (estimating) the processing amount to be offloaded to the accelerator. Any method can be used as long as it can predict (estimate) the processing amount to be offloaded to the accelerator.

[0040] The input amount acquisition and prediction unit 110 predicts fluctuations in the input data amount based on the acquired input data amount, and outputs the prediction result as traffic amount and its fluctuation range. Specifically, the input amount acquisition and prediction unit 110 acquires the input data amount of the server and predicts future fluctuations in the input data amount. The input amount acquisition and prediction unit 110 accepts the input data amount of the server as input, and outputs the traffic amount after a certain time has passed and the unit of fluctuation time as the prediction result of future data amount.

[0041] Prediction function example 1 It is possible to predict future changes based on past changes in traffic volume. For example, based on the past five traffic volumes acquired at regular intervals, it is determined whether traffic volume is on an increasing trend. The five traffic volumes are linearly approximated, and if the obtained slope is above a certain level, it is considered to be an increase, and if it is below a certain level, it is considered to be a decrease, and the traffic volume after a certain time is predicted. Furthermore, based on the variance of each traffic volume, the unit of fluctuation time is output. Specifically, if the variance is large, traffic fluctuations are expected in a short period of time, so it outputs that it is on the order of seconds, and if the variance is small, it outputs that it is on the order of minutes.

[0042] Prediction function example 2 It is also possible to record the traffic volume for the relevant device by day of the week and time period, and perform traffic predictions based on this. For example, in the case of traffic volume in a mobile phone wireless access network, the time transition of traffic volume varies from location to location. For example, in urban areas, traffic volume is high during the daytime but low at night. Also, in areas along railway lines, traffic volume is extremely low outside of train operating hours. Such results can be used to predict traffic volume by hour. Note that when using the method in Example 2 of this prediction function, the time unit for fluctuations in traffic volume is long, such as minutes or hours.

[0043] When predicting traffic volume, other factors that determine the traffic volume of the corresponding server device may be used. For example, in a mobile phone wireless access network, traffic volume fluctuates depending on the weather for a device connected to an antenna device near a crowded outdoor area. In such a use case, traffic volume fluctuations may be predicted based on weather forecast results. Note that when this method is used, the time unit for traffic volume fluctuations is long, such as minutes or hours.

[0044] Input data size prediction function In addition to the form of estimating from the time zone, the input data size prediction function may also be configured to estimate from other factors. For example, fluctuations in traffic volume due to weather or events provided by the RIC (RAN Intelligent Controller) in the RAN (Radio Access Network) may be used as an information source.

[0045] · Example of fluctuations in the input data volume over time In vRAN, the amount of input data to the server depends on the number of mobile phone terminals and the traffic volume in the area served by that server. The number of mobile phone terminals and the traffic volume depend on human movement. The time zones and areas where people gather have an increase in traffic volume, and conversely, the traffic volume decreases in time zones and areas where people do not gather. For example, the office streets in the city center have a large traffic volume during weekdays and daytime, while the traffic volume at night and on holidays is small. Also, the residential streets in the suburbs have a larger traffic volume on holidays compared to the traffic volume during weekdays and daytime.

[0046] <ACC processing capacity and power consumption setting determination unit 120> Based on the traffic volume and the fluctuation range output from the input amount acquisition and prediction unit 110 and the list information (Figure 3) read from the ACC information and processing capacity setting record unit 150, the ACC processing capacity and power consumption setting determination unit 120 determines the setting of the accelerator's processing capacity and the fluctuation time.

[0047] Specifically, the ACC processing capacity and power consumption setting determination unit 120 determines the setting of the accelerator's processing capacity and the fluctuation time according to the prediction result of the traffic volume output from the input amount acquisition and prediction unit 110 and the assumed fluctuation range. The ACC processing capacity and power consumption setting determination unit 120 inputs the traffic volume into the ACC information and processing capacity setting record unit 150 and obtains the list information (Figure 3) of applicable accelerators and settings. From these list information of settings, it selects the settings of the accelerator that matches the processing capacity and the fluctuation time and the settings of the cooling mechanism 14, and notifies the ACC processing capacity and power consumption setting input unit 130. The ACC processing capacity and power consumption setting determination unit 120 receives, as input, the prediction and fluctuation range of the traffic volume from the input amount acquisition and prediction unit 110. The ACC processing capacity and power consumption setting determination unit 120 passes the ACC setting information to the ACC processing capacity and power consumption setting input unit 130 as output.

[0048] <ACC processing capacity and power consumption setting input unit 130> The ACC processing capacity and power consumption setting input unit 130 reflects the setting information on the accelerator 12 based on the setting information on the accelerator 12 determined by the ACC processing capacity and power consumption setting determination unit 120. Specifically, the ACC processing capacity and power consumption setting input unit 130 reflects the input setting to the accelerator 12 and the setting to the cooling mechanism 14 on the accelerator 12 and the cooling mechanism 14, respectively. The ACC processing capacity and power consumption setting input unit 130 receives, as input, the setting to the accelerator 12 and the setting information to the cooling mechanism 14 from the ACC processing capacity and power consumption setting determination unit 120. The ACC processing capacity and power consumption setting input unit 130 reflects the setting information on the accelerator 12 and the cooling mechanism 14 as output, respectively.

[0049] Also, the ACC processing capacity and power consumption setting input unit 130 reflects the setting information in a common manner for the accelerators by changing the frequency and / or turning off the power, and in the case of FPGA, reflects the setting information by circuit rewriting, and in the case of GPU, reflects the setting information by sleep.

[0050] <ACC circuit information recording unit 140 by processing capacity> The ACC circuit information recording unit 140 by processing capacity holds the FPGA circuit information and the information on the FPGA type according to the processing performance for each FPGA type, and responds with the FPGA circuit information and the information on the FPGA type in response to an inquiry. In this case, the ACC circuit information recording unit 140 by processing capacity responds to the ACC processing capacity and power consumption setting determination unit 120 via the ACC information and processing capacity setting recording unit 150 or directly.

[0051] The ACC circuit information recording unit 140 by processing capacity holds a plurality of FPGA circuit information corresponding to the processing performance for each FPGA type, and pays out the FPGA circuit information in response to an inquiry. This inquiry includes information on the FPGA type (Fig. 4). The ACC circuit information recording unit 140 by processing capacity receives information on the FPGA model from the ACC information and processing capacity setting recording unit 150 as an input. The ACC circuit information recording unit 140 by processing capacity responds with a plurality of FPGA circuit information to the ACC information and processing capacity setting recording unit 150 as an output.

[0052] The ACC circuit information recording unit 140 by processing capacity may also be configured to include "required processing performance" in the above inquiry and respond with only one optimal FPGA circuit information based on this information. Regarding the response of the FPGA circuit information, instead of the actual data of the FPGA circuit information itself, circuit information such as a file path pointer necessary for access may be used as an identifier that can uniquely identify it.

[0053] <ACC information and processing capacity setting recording unit 150> The ACC information and processing capacity setting recording unit 150 holds information on the accelerator type and model and setting information corresponding to the processing performance as list information 170 (Fig. 3), and extracts and responds from the list information 170 in response to an inquiry. Here, the above accelerator type and model information is information on the accelerator held by the host on which the accelerator can be mounted for use.

[0054] The ACC information and processing capacity setting recording unit 150 receives the accelerator type, model, and application name from the ACC processing capacity and power consumption setting determination unit 120 as an input. The ACC information and processing capacity setting recording unit 150 responds with a list of applicable setting means for the corresponding accelerator to the ACC processing capacity and power consumption setting determination unit 120 as an output. Also, when the input accelerator type is FPGA, the ACC information and processing capacity setting recording unit 150 makes an inquiry to the ACC circuit information recording unit 140 by processing capacity based on the model information and obtains a list of the corresponding compatible FPGA circuit information.

[0055] <ACC Switching Time Processing Continuity Unit 160> When the ACC switching time processing continuity unit 160 enables the service while the arithmetic function of the accelerator 12 is temporarily stopped due to the input of the setting information by the ACC processing ability and power consumption setting input unit 130, the CPU 11 or another accelerator temporarily continues the processing. It is activated when the operation in the corresponding accelerator 12 temporarily stops when the setting of the accelerator 12 is changed. When the ACC switching time processing continuity unit 160 is activated, the arithmetic offloading from the application 1 is received by this functional unit and calculated using the arithmetic resources other than the setting change target.

[0056] In addition to continuing the operation on the CPU, it may also be possible to temporarily use another accelerator and continue the operation.

[0057] [Antenna Device 210] The antenna device 210 is an antenna and a transceiver for wireless communication with a terminal (UE: User Equipment) (hereinafter, the "antenna device" generically refers to the antenna, the transceiver, and its power supply unit). The transmitted and received data is connected to the signal processing device (server 200) of the base station (BBU: Base Band Unit) by, for example, a dedicated cable.

[0058] The antenna device 210 includes an antenna device data input / output unit 211. The antenna device data input / output unit 211 is a functional unit that sends the signal generated by the antenna device 210 to the server 200 and is realized in the form of a NIC or the like.

[0059] [Subsequent Processing Device 220] The subsequent processing device 220 is a Centralized Unit in 5G signal processing. The subsequent processing device 220 includes a subsequent processing device data input / output unit 221. The subsequent processing device data input / output unit 221 is a functional unit that receives the signal processing result processed by the server 200 and is realized in the form of a NIC or the like.

[0060] <Other embodiments> In this embodiment, the input / output unit 13, the CPU 11, and the accelerator 12 are configured as separate hardware components, but the CPU 11, the accelerator 12, and the accelerator arithmetic circuit program 12a may be integrated into dedicated hardware. In other words, as shown in Figure 1, in addition to the so-called Look-Aside type accelerator application form in which "data obtained via an input / output unit 13 such as a NIC is explicitly offloaded from the CPU 11 to the accelerator 12," it is also possible to use a so-called In-line type accelerator application form in which "NIC, accelerator, and CPU" are integrated into hardware, and processing is completed within the same hardware after data is received by the NIC." Furthermore, the CPU 11 and the accelerator 12 may be mounted on a single chip, such as in the form of an SoC (System on Chip).

[0061] [Placement of accelerator state control device] Variations in the arrangement of the accelerator state control device in the accelerator state control system will be described. The accelerator state control system 1000 in Fig. 1 is an example in which the accelerator state control device 100 is arranged in software 20 of a server 200. Some of the functions of the accelerator state control device 100 can also be installed in a separate housing outside the server 200, as exemplified below.

[0062] 2 is a schematic diagram showing variations in the arrangement of the accelerator state control device of the accelerator state control system. In the following figures, the same components as those in FIG. 1 are designated by the same reference numerals, and explanations of overlapping parts will be omitted. The variation shown in Figure 2 is an example in which the controller function unit consisting of the input amount acquisition and prediction unit 110, the ACC processing capacity and power consumption setting judgment unit 120, the ACC circuit information recording unit by processing capacity 140, and the ACC information and processing capacity setting recording unit 150 is housed in a separate housing. As shown in FIG. 2, the accelerator state control system 1000A includes an accelerator state control device 100A installed outside the server 200 in a separate housing. The software 20 of the server 200 includes an application 1, an ACC processing capacity and power consumption setting input unit 130, and an ACC switching time processing continuation unit 160. The accelerator state control device 100A has the controller function unit installed outside the server 200 and has the same functions as the accelerator state control device 100 of FIG.

[0063] As shown in FIG. 2, by independently deploying some or all of the functions of the accelerator state control device in a separate housing outside the server 200, it is possible to accommodate the deployment of functions to a RAN Intelligent Controller (RIC) in a RAN (Radio Access Network).

[0064] Furthermore, by placing the controller function unit externally, the input volume can be predicted based on the input volume obtained from multiple server machines (function 1), which has the advantage of improving the accuracy of traffic prediction for function 1. For example, in a mobile phone wireless system, if the traffic volume in the processing area handled by a certain server machine increases, it is expected that the input volume in nearby processing areas will also fluctuate with a delay.

[0065] Furthermore, it becomes possible to operate a single accelerator state control device for multiple servers 200. This reduces costs and improves maintainability of the accelerator state control device. Furthermore, modifications to the server side are unnecessary or can be reduced, making it possible to apply it in a general-purpose manner.

[0066] [Accelerator data structure] This section explains the list and characteristics of power reduction techniques. FIG. 3 is a diagram illustrating a list of power reduction techniques. As shown in Figure 3, power reduction techniques are classified into 1. circuit scale change, 2. clock control, 3. power supply control, and 4. others. For each of these four categories, the power reduction technique, ACC processing capacity, power consumption reduction range (difference from maximum configuration), transition and recovery time, applicability by ACC, and remarks are set. Applicability by ACC is divided into FPGA, GPU, and ASIC.

[0067] There are four categories of methods for controlling accelerator processing capacity and power consumption. Each of the four categories of power reduction methods differs in the range of fluctuation in ACC processing capacity, the amount of power consumption reduction, the time required for transition and recovery, and applicability to each ACC. The accelerator state control method uses these methods appropriately based on the load prediction results and the accelerator to be controlled.

[0068] For example, in the "Partial Reconfiguration" section of the "Power Reduction Method" for "Classification" 1. Circuit Scale Change, the ACC processing capacity is "Small to Large (Degeneration)", the power consumption reduction range (difference from the maximum configuration) is "Up to 60W", the transition and recovery time is "on the order of seconds", and the applicability for each ACC is "FPGA". Furthermore, it has the characteristic that "optimal circuit information for each performance is prepared and rewritten as appropriate according to the load amount."

[0069] In addition, in "Classification" 4. Other "Power Reduction Methods" 4-2. "ACC Switching," the ACC processing capacity is "Small to Large (Degenerated)," the power consumption reduction (difference from maximum configuration) is "up to 60W," the transition and recovery time is "on the order of seconds," and the applicability of each ACC is "FPGA, GPU, ASIC." Furthermore, it is characterized by "preparing multiple optimal circuits and ACCs for each performance and switching appropriately depending on the load."

[0070] [Circuit information by processing capacity] The processing capacity-based circuit information of the processing capacity-based ACC circuit information recording unit 140 will be described. FIG. 4 is a diagram showing an example of a database of circuit information classified by processing capacity held by the processing capacity-classified ACC circuit information recording unit 140. As shown in FIG. As shown in FIG. 4, the circuit information by processing capacity includes an FPGA function type, an application name, performance, and a circuit information file name. The processing capacity-based ACC circuit information recording unit 140 holds multiple pieces of FPGA circuit information (circuit information by processing capacity shown in Figure 4) according to processing performance for each FPGA type, and issues FPGA circuit information in response to an inquiry (hereinafter, "issue" means to retrieve information and respond).

[0071] [Processing volume estimation table] A processing performance calculation table (a processing amount estimation table) based on the traffic amount held by the processing capacity-specific ACC circuit information recording unit 140 will be described. FIG. 5 is a diagram showing a processing performance calculation table (a processing amount estimation table) based on the traffic amount held by the processing capacity-specific ACC circuit information recording unit 140. As shown in FIG. As shown in Figure 5, the processing amount estimation table specifies the required processing performance based on the traffic volume. For example, if the traffic volume is "0 bps or more but less than 10 Mbps," the required processing performance is "small."

[0072] [Accelerator installation relationship management table] The accelerator installation relationship management table held by the processing capacity-based ACC circuit information recording unit 140 will be described. FIG. 6 is a diagram showing an accelerator installation relationship management table held by the processing capacity-based ACC circuit information recording unit 140. As shown in FIG. As shown in Fig. 6, the accelerator installation relationship management table stores the correspondence between the installed host ID and the installed accelerator ID. In the example of Fig. 6, the installed host Host-1 is equipped with installed accelerator IDs "1", "2", and "3".

[0073] [Accelerator list management table] The accelerator list management table held by the processing capacity-based ACC circuit information recording unit 140 will be described. FIG. 7 is a diagram showing an accelerator list management table held by the processing capacity-based ACC circuit information recording unit 140. As shown in FIG. As shown in Fig. 7, the accelerator list management table stores the correspondence between accelerator IDs and accelerator type IDs. In the example of Fig. 7, accelerator ID "1" specifies accelerator type ID "A," accelerator ID "2" specifies accelerator type ID "B," accelerator ID "3" specifies accelerator type ID "C," and accelerator ID "4" specifies accelerator type ID "D." Accelerator type IDs "A" to "D" are specifically shown in the accelerator type management table of Fig. 8 below.

[0074] [Accelerator type management table] The accelerator type management table held by the processing capacity-based ACC circuit information recording unit 140 will be described. FIG. 8 is a diagram showing an accelerator type management table held by the processing capacity-based ACC circuit information recording unit 140. As shown in FIG. As shown in FIG. 8, the accelerator type management table stores the accelerator type (notes), performance, and power consumption for each accelerator type ID. For example, accelerator type ID "A" corresponds to accelerator type "FPGA-low performance," performance "low to high," and power consumption "75W." Accelerator type ID "B" corresponds to accelerator type "FPGA-high performance," performance "low to high," and power consumption "200W." Therefore, if the accelerator type is "FPGA" and performance is prioritized, accelerator type ID "B" is selected. Also, if the required performance is "medium to high," accelerator type ID "C" (GPU) or accelerator type ID "D" (ASIC) can be selected in addition to accelerator type "FPGA." Note that items other than performance and power consumption (e.g., application type) may also be managed. For example, if an application executes parallel processing, accelerator type "GPU" may be selected even if the power consumption is the same.

[0075] The operation of the accelerator state control system 1000 configured as described above will now be described. The operation sequence of this embodiment is a power saving control sequence, and there are two types of operation sequence: <operation sequence 1>, in which the power saving control starts with predicting the input amount of function 1, and <operation sequence 2>, in which the power saving control starts with periodic execution. These will be explained in order below. [Operation sequence 1] FIG. 9 is a flowchart showing the <operation sequence 1> in the case where power saving control starts with prediction of the input amount of function 1.

[0076] In step S11, the input volume acquisition and prediction unit 110 receives as input the input data volume of the server, and outputs as output the traffic volume after a certain time has elapsed and the unit of fluctuation time as the prediction result of the future data volume.

[0077] In step S12, the ACC processing capacity and power consumption setting determination unit 120 determines the accelerator processing capacity and fluctuation time settings based on the traffic volume and fluctuation range output from the input volume acquisition and prediction unit 110 and the list information read from the ACC information and processing capacity setting recording unit 150 (Figure 3).

[0078] In step S13, the installed ACC information and processing capacity setting recording unit 150 holds information on the accelerator type and model installed in each host and a list of setting information corresponding to processing performance, and dispenses it in response to an inquiry. The ACC information and processing capacity setting recording unit 150 receives as input the accelerator type, model, and application name from the ACC processing capacity and power consumption setting determination unit 120. The ACC information and processing capacity setting recording unit 150 responds as output to the ACC processing capacity and power consumption setting determination unit with a list of setting methods applicable to the corresponding accelerator 12. Furthermore, if the input accelerator type is FPGA, the ACC information and processing capacity setting recording unit 150 queries the processing capacity-specific ACC circuit information recording unit 140 based on the model information and obtains a list of corresponding compatible FPGA circuit information.

[0079] In step S14, the ACC processing capacity / power consumption setting determination unit 120 determines whether or not the installed accelerator 12 is an FPGA. If the installed accelerator 12 is not an FPGA (S14: No), the process proceeds to step S16.

[0080] If the installed accelerator 12 is an FPGA (S14: Yes), in step S15, the processing-capability-based ACC circuit information recording unit 140 stores FPGA circuit information and FPGA type information according to processing performance for each FPGA type, and responds with the FPGA circuit information and FPGA type information in response to an inquiry. In this case, the processing-capability-based ACC circuit information recording unit 140 responds to the ACC processing capacity and power consumption setting determination unit 120 via the ACC information and processing capacity setting recording unit 150 or directly.

[0081] In step S16, the ACC processing capacity / power consumption setting input unit 130 reflects the input settings for the accelerator 12 and the cooling mechanism 14 in the accelerator 12 and the cooling mechanism 14, respectively. The ACC processing capacity / power consumption setting input unit 130 receives, as input, the settings for the accelerator 12 and the setting information for the cooling mechanism 14 from the ACC processing capacity / power consumption setting determination unit 120. The ACC processing capacity / power consumption setting input unit 130 reflects, as output, the setting information in the accelerator 12 and the cooling mechanism 14, respectively.

[0082] In step S17, the accelerator 12 executes an operation specialized for a particular process. In step S18, the accelerator arithmetic circuit / program 12a loads the accelerator circuit or program, and ends the processing of this flowchart. If the accelerator 12 is an FPGA, FPGA circuit information is loaded, and if the accelerator 12 is a GPU, GPU information is loaded.

[0083] On the other hand, in step S19, the cooling mechanism 14 cools down all of the computing devices (CPU 11 and accelerator 12) of the server, and the process of this flowchart ends.

[0084] [Operation sequence 2] 10 is a flowchart showing the operation sequence 2 when power saving control starts with periodic execution. Steps that perform the same processes as those in the operation sequence 1 in FIG. 9 are assigned the same reference numerals and their explanations are omitted. In step S21, the ACC processing capacity / power consumption setting determination unit 120 is activated at regular intervals and determines the accelerator settings according to the processing capacity of the accelerator 12 and the fluctuation time, based on the predicted traffic volume input from the input volume acquisition / prediction unit 110 and the expected fluctuation range.

[0085] After step S15, in step S22, the ACC switching process continuation unit 160 temporarily continues the process in the CPU 11 or another accelerator to continue the service if the calculation function of the accelerator 12 is temporarily stopped due to the input of the setting information. This is enabled when the calculation in the accelerator 12 is temporarily stopped when the setting of the accelerator 12 is changed.

[0086] After step S18, in step S23, the ACC switching process continuation unit 160 suspends the calculation of the accelerator when the accelerator setting is changed, and ends the process of this flowchart. The above has described the <operation sequence 1> in which power saving control starts with prediction of the input amount of function 1, and the <operation sequence 2> in which power saving control starts with periodic execution.

[0087] [Power reduction method setting sequence] The accelerator state control device 100 selects a power reduction method to apply depending on the amount of traffic and the duration of fluctuation. Examples of power reduction methods and examples of load patterns suitable for these power reduction methods will be described below.

[0088] FIG. 11 is a diagram showing details of the list information of power reduction methods. As shown in Figure 11, the power consumption reduction method, ACC processing capacity, power consumption reduction amount (difference from maximum configuration), transition / recovery time, and suitable load pattern are divided into four categories. The four categories are: 1. Circuit scale change, 2. Clock control, 3. Power supply control, and 4. Other. The power consumption reduction amount is a calculated value assuming a specific configuration (e.g., Dell R740 2-socket + FPGA N3000). For example, if the classification is "1. Changing the circuit scale" and the power reduction method is "1-1. Writing an empty design," the appropriate load pattern is "a case where load fluctuations on the order of minutes occur under a small load." In other words, if "a small load with load fluctuations on the order of minutes" is acceptable, then it is appropriate to adopt "1-1. Writing an empty design." In particular, if the classification is "4. Other" and the power reduction method is "4-2. ACC switching," the appropriate load pattern is "set according to the ACC processing capacity in all cases."

[0089] [Example of power reduction method setting sequence] An example of the settings and decision logic for the accelerator 12 and the cooling mechanism 14 (fan, etc.) will be described with reference to a flowchart. Each setting amount is an example, and changes depending on each setting item.

[0090] 12A-12C are flowcharts showing an example of a power reduction method setting sequence. Although each of FIGS. 12A-12C is a single flow, for convenience of illustration, they are connected using connectors [A], [B], and [C]. The dashed lines surrounding each step in the flow represent the functional units that execute that step.

[0091] As shown in FIG. 12A, in step S31, the ACC processing capacity and power consumption setting determination unit 120 acquires the traffic volume. In step S32, the ACC processing capability and power consumption setting determination unit 120 determines whether the traffic volume has increased or decreased a certain number of times in succession. If the traffic volume has not increased or decreased a certain number of times in succession (S32: No), the process returns to step S31.

[0092] If the traffic volume has increased or decreased a certain number of times in succession (S32: Yes), the ACC processing capacity / power consumption setting determination unit 120 is skipped and the process proceeds to step S33. In step S33, the ACC information and processing capacity setting recording unit 150 refers to the processing capacity calculation table shown in FIG. 5 and calculates the processing capacity from the traffic volume. In step S34, the ACC information and processing capacity setting recording unit 150 refers to the accelerator mounting relationship management table shown in FIG. 6 to obtain a list of mounted ACCs and their performance.

[0093] The steps enclosed by dashed lines in FIG. 12B are processes performed by the ACC processing capability and power consumption setting determination unit 120. In step S35, the ACC processing capacity / power consumption setting determination unit 120 determines which type of ACC satisfies the processing capacity. If the ACC that satisfies the processing performance is an FPGA, it is determined in step S36 which of the following the processing performance matches.

[0094] If the processing performance is "minimum," select "3. Power Control 3-1. ACC Card Power OFF" (Figure 11) in step S37, and select "4. Other 4-1. Fan Control Fan Setting [Minimum]" (Figure 11) in step S38, and proceed to step S48.

[0095] If the processing performance is "small," select "1. Circuit size change 1-2. Select small-scale circuit by partial reconfiguration" (Figure 11) in step S39, select "2. Clock control 2-1. Frequency [small] by calculation unit clock control" (Figure 11) in step S40, and select "4. Other 4-1. Fan control Fan setting [small]" (Figure 11) in step S41, and proceed to step S48.

[0096] If the processing performance is "medium," select "1. Circuit size change 1-2. Select medium-scale circuit in partial reconfiguration" (Figure 3) in step S42, select "2. Clock control 2-1. Frequency [medium] in calculation unit clock control" (Figure 11) in step S43, and select "4. Other 4-1. Fan control Fan setting [medium]" (Figure 11) in step S44, and proceed to step S48.

[0097] If the processing performance is "large," select "1. Circuit size change 1-2. Select large-scale circuit by partial reconfiguration" (Figure 3) in step S45, select "2. Clock control 2-1. Frequency [large] by calculation unit clock control" (Figure 11) in step S46, and select "4. Other 4-1. Fan control Fan setting [large]" (Figure 11) in step S47, and proceed to step S48.

[0098] In step S48, if the calculation function of the accelerator 12 is temporarily stopped due to the input of the setting information, the ACC switching process continuation unit 160 temporarily continues (enables) the process in the CPU 11 or another accelerator to continue the service, and proceeds to step S58. As a result, when the setting of the accelerator is changed, the accelerator is enabled when the calculation in the accelerator is temporarily stopped.

[0099] If the ACC processing capability / power consumption setting determination unit 120 determines in step S35 that the ACC that satisfies the processing performance is a GPU or ASIC, it determines in step S49 which of the following the processing performance matches.

[0100] If the processing performance is "minimum," select "3. Power Control 3-1. ACC Card Power OFF" (Figure 11) in step S50, and select "4. Other 4-1. Fan Control Fan Setting [Minimum]" (Figure 11) in step S51, and proceed to step S58.

[0101] If the processing performance is "Small," select "2. Clock Control 2-1. Calculation Unit Clock Control Frequency [Small]" (Figure 11) in step S52, and select "4. Other 4-1. Fan Control Fan Setting [Small]" (Figure 11) in step S53, and proceed to step S58.

[0102] If the processing performance is "medium," select "2. Clock Control 2-1. Calculation Unit Clock Control Frequency [medium]" (Figure 11) in step S54, and select "4. Other 4-1. Fan Control Fan Setting [medium]" (Figure 3) in step S55, and proceed to step S58.

[0103] If the processing performance is "large," select "2. Clock Control 2-1. Calculation Unit Clock Control Frequency [large]" (Figure 3) in step S56, and select "4. Other 4-1. Fan Control Fan Setting [large]" (Figure 3) in step S57, and proceed to step S58.

[0104] In step S58 shown in FIG. 12C, the ACC processing capacity / power consumption setting input unit 130 inputs the setting to the ACC / Fan.

[0105] In step S59, the ACC switching process continuation unit 160 determines whether the ACC switching process continuation function is being executed. If the ACC switching process continuation function is not being executed (S59: No), the process of this flow ends. If the ACC switching processing continuation function is being executed (S59: Yes), in step S60, the ACC switching processing continuation unit 160 disables the accelerator by temporarily suspending its calculations when the accelerator settings are changed, and ends the processing of this flow. The power reduction method setting sequence has been described above with reference to FIG. 11 and FIGS. 12A to 12C.

[0106] [Data processing sequence for operation sequence 1] The data processing sequence for operation sequence 1 will be described below. The data processing sequence for operation sequence 2 is similar. The data processing sequence for operation sequence 1 can be either a "Look-Aside type (the CPU actively offloads data processed by the ACC to the ACC)" or an "In-line type (the CPU actively offloads data processed by the ACC to the ACC)." These will be explained in order below.

[0107] FIG. 13 is a flowchart showing a data processing sequence of the Look-Aside type operation sequence 1. In step S61, the antenna device data input / output unit 211 sends the signal generated by the antenna device 210 to the server 200.

[0108] In step S62, the input / output unit 13 inputs and outputs data to and from the external device (antenna device 210 and post-processing device 220).

[0109] In step S63, the application 1 runs and performs signal processing on the CPU 11. The application 1 offloads to the accelerator 12 specialized processing that is not suitable for the CPU 11, such as some parallel arithmetic processing.

[0110] In step S64, the accelerator 12 executes an operation specialized for a particular process. In step S65, the application 1 accepts the data to be processed from the input / output unit 13 and passes the calculated data to the input / output unit 13. If the accelerator 12 becomes temporarily unavailable when the settings of the accelerator 12 are changed, the application 1 offloads the data to the ACC switching time processing continuation unit 160.

[0111] In step S66, the input / output unit 13 inputs and outputs data to and from the external device (antenna device 210 and post-processing device 220).

[0112] In step S67, the post-processing device data input / output unit 221 receives the signal processing result processed by the server 200, and the processing of this flowchart ends.

[0113] FIG. 14 is a flowchart showing a data processing sequence of the in-line type operation sequence 1. In step S71, the antenna device data input / output unit 211 sends the signal generated by the antenna device 210 to the server 200.

[0114] In step S72, the input / output unit 13 inputs and outputs data to and from the external device (antenna device 210 and post-processing device 220).

[0115] In step S73, the accelerator 12 executes an operation specialized for a particular process. In step S74, the application 1 accepts the data to be processed from the input / output unit 13 and passes the calculated data to the input / output unit 13. If the accelerator 12 becomes temporarily unavailable when the settings of the accelerator 12 are changed, the application 1 offloads the data to the ACC switching time processing continuation unit 160.

[0116] In step S75, the input / output unit 13 inputs and outputs data to and from the external device (antenna device 210 and post-processing device 220).

[0117] In step S76, the post-processing device data input / output unit 221 receives the signal processing result processed by the server 200, and the processing of this flowchart ends.

[0118] [Processing capacity, power consumption and surplus] The processing capacity, power consumption, and surplus realized by the accelerator state control device 100 will be described. The ACC processing capacity and power consumption setting determination unit 120 determines accelerator settings according to the accelerator processing capacity and fluctuation time, based on the traffic volume prediction results input from the input volume acquisition and prediction unit 110 and the expected fluctuation range. The ACC processing capacity and power consumption setting input unit 130 receives settings for the accelerator 12 and setting information for the cooling mechanism 14 from the ACC processing capacity and power consumption setting determination unit 120, and reflects the setting information in each of the accelerator 12 and the cooling mechanism 14. The ACC processing capacity and power consumption setting input unit 130 automatically sets accelerator settings (circuit information, frequency, fan output, etc.) appropriate for each input data volume, thereby dynamically changing the processing capacity and power consumption.

[0119] Fig. 15 is a diagram illustrating the processing capacity, power consumption, and surplus realized by the accelerator state control device 100. The solid line in Fig. 15 indicates the amount of input data, and the dashed line in Fig. 15 indicates the server processing capacity (≈power consumption). The ACC processing capacity / power consumption setting determination unit 120 and the ACC processing capacity / power consumption setting input unit 130 perform accelerator settings appropriate for each input data amount, and the processing capacity and power consumption are dynamically changed. As shown by the arrows in Figure 15, the setting change changes the amount that server 200 can process, improving power efficiency.

[0120] [Hardware configuration] The accelerator state control device 100 (FIG. 1) of the accelerator state control systems 1000, 1000A (FIGS. 1 and 2) according to the above embodiments is realized by a computer 900 configured as shown in FIG. 16, for example. FIG. 16 is a hardware configuration diagram showing an example of a computer 900 that realizes the functions of the accelerator state control device 100. The accelerator state control device 100 includes a CPU 901, a RAM 902, a ROM 903, a HDD 904, an accelerator 905, an input / output interface (I / F) 906, a media interface (I / F) 907, and a communication interface (I / F) 908. The accelerator 905 corresponds to the accelerator 12 in FIGS.

[0121] The accelerator 905 is an accelerator (device) 12 (FIGS. 1 and 2) that processes at least one of data from the communication I / F 908 and data from the RAM 902 at high speed. Note that the accelerator 905 may be of a type that returns the execution results to the CPU 901 or RAM 902 after executing processing from the CPU 901 or RAM 902 (look-aside type). On the other hand, the accelerator 905 may be of a type that performs processing between the communication I / F 908 and the CPU 901 or RAM 902 (in-line type).

[0122] The accelerator 905 is connected to an external device 915 via a communication I / F 908. The input / output I / F 906 is connected to an input / output device 916. The media I / F 907 reads and writes data from and to a recording medium 917.

[0123] The CPU 901 operates based on a program stored in the ROM 903 or the HDD 904, and controls each part of the accelerator state control device 100, 100A shown in Figures 1 and 2 by executing a program (also called an application or an app for short) loaded into the RAM 902. This program can also be distributed via a communication line or recorded on a recording medium 917 such as a CD-ROM. The ROM 903 stores a boot program executed by the CPU 901 when the computer 900 is started, programs that depend on the hardware of the computer 900, and the like.

[0124] The CPU 901 controls an input / output device 916, which is made up of input units such as a mouse and a keyboard, and output units such as a display and a printer, via an input / output I / F 906. The CPU 901 acquires data from the input / output device 916 via the input / output I / F 906, and outputs generated data to the input / output device 916. Note that a GPU (Graphics Processing Unit) or the like may be used as a processor together with the CPU 901.

[0125] The HDD 904 stores programs executed by the CPU 901 and data used by the programs. The communication I / F 908 receives data from other devices via a communication network (e.g., a network) and outputs the data to the CPU 901, and also transmits data generated by the CPU 901 to other devices via the communication network.

[0126] The media I / F 907 reads a program or data stored in the recording medium 917 and outputs it to the CPU 901 via the RAM 902. The CPU 901 loads a program related to a target process from the recording medium 917 onto the RAM 902 via the media I / F 907, and executes the loaded program. The recording medium 917 is an optical recording medium such as a DVD (Digital Versatile Disc) or a PD (Phase Change Rewritable Disc), a magneto-optical recording medium such as an MO (Magneto Optical disc), a magnetic recording medium, a conductive memory tape medium, a semiconductor memory, or the like.

[0127] For example, when the computer 900 functions as the accelerator state control device 100 (FIG. 1) configured as one device according to this embodiment, the CPU 901 of the computer 900 executes a program loaded onto the RAM 902 to realize the functions of the accelerator state control device 100. The HDD 904 also stores data in the RAM 902. The CPU 901 reads and executes a program related to a target process from the recording medium 917. Alternatively, the CPU 901 may read a program related to a target process from another device via a communication network. 2 is installed outside the server 200, this accelerator state control device 100A is also realized by a computer 900 having a configuration as shown in FIG.

[0128] [effect] As described above, the accelerator state control device 100 controls the state of the accelerator 12 when a specific process of the application 1 is offloaded to the accelerator 12 for computational processing. The accelerator state control device 100 includes: an input amount acquisition and prediction unit 110 that predicts the amount of processing to be offloaded to the accelerator 12 and outputs the prediction result as a traffic amount and its fluctuation range; a processing capacity setting recording unit 150 that holds information on the accelerator type and model and setting information according to the processing performance as list information and extracts it from the list information in response to an inquiry; an ACC processing capacity and power consumption setting determination unit 120 that determines setting information for the accelerator processing capacity and fluctuation time based on the traffic amount and fluctuation range output from the input amount acquisition and prediction unit 110 and the list information read from the processing capacity setting recording unit 150; and an ACC processing capacity and power consumption setting input unit 130 that reflects the setting information for the accelerator 12 based on the setting information for the accelerator 12 determined by the ACC processing capacity and power consumption setting determination unit 120.

[0129] By doing this, the accelerator settings (circuit information, frequency, fan output, etc.) appropriate for each input data volume are automatically configured, dynamically changing the processing capacity and power consumption, ensuring responsiveness in response to fluctuating input data volumes while achieving high power efficiency for each accelerator. This makes it possible to achieve both <Requirement 1: Power efficiency> and <Requirement 2: Responsiveness>.

[0130] The accelerator state control device 100, 100A (Figures 1 and 2) includes an ACC switching processing continuation unit 160 that temporarily continues processing in the CPU 11 or another accelerator when the calculation function of the accelerator 12 is temporarily stopped due to the input of setting information by the ACC processing capacity / power consumption setting input unit 130.

[0131] By doing so, if the calculation stops when the accelerator is turned on, the calculation can be continued by the CPU 11 or another accelerator, thereby maintaining availability.

[0132] In the accelerator state control device 100, 100A (Figures 1 and 2), the accelerator 12 has an FPGA and is equipped with a processing-capability-specific ACC circuit information recording unit 140 that stores, for each FPGA type, FPGA circuit information and FPGA type information corresponding to processing performance and responds to inquiries with FPGA circuit information and FPGA type information. The processing-capability-specific ACC circuit information recording unit 140 responds to the ACC processing capacity and power consumption setting determination unit 120 via the ACC information and processing capacity setting recording unit 150 or directly. The ACC processing capacity and power consumption setting determination unit 120 determines accelerator setting information corresponding to the accelerator's processing capacity and fluctuation time based on the FPGA circuit information and FPGA type information from the processing-capability-specific ACC circuit information recording unit 140.

[0133] In this way, the processing capacity-based ACC circuit information recording unit 140 records and manages the power saving settings for each accelerator type. The ACC processing capacity / power consumption setting determination unit 120 selects a processing means for each installed ACC information, thereby realizing support for multiple accelerators (<Requirement 3: Support for multiple accelerators>). For example, in the case of FPGA, this is circuit selection + frequency setting, and in the case of ASIC, frequency setting, etc.

[0134] In the accelerator state control devices 100, 100A (Figs. 1 and 2), the accelerator 12 has an FPGA and a GPU, and the ACC processing capacity / power consumption setting input unit 130 is common to all accelerators and reflects the setting information by changing the frequency and / or turning off the power, and also reflects the setting information by rewriting the circuit in the case of an FPGA and by putting the GPU into sleep mode.

[0135] By doing this, when determining the power saving settings, it is possible to determine the parameters that can be set for each installed accelerator, thereby realizing support for various accelerators (<Requirement 3: Support for various accelerators>). For example, in the case of FPGA, this is circuit rewriting, in the case of GPU, this is sleep, and common methods include frequency change and power off.

[0136] The accelerator state control system 1000, 1000A (FIGS. 1 and 2) includes an accelerator state control device 100, 100A (FIGS. 1 and 2) that controls the state of the accelerator when a specific process of an application 1 is offloaded to the accelerator 12 for arithmetic processing, and a cooling mechanism 14 that cools the arithmetic device including the accelerator. The accelerator state control system 1000, 1000A (FIGS. 1 and 2) includes an input amount acquisition and prediction unit 110 that predicts the amount of processing to be offloaded to the accelerator 12 and outputs the prediction result as traffic amount and its fluctuation range, and a list information that stores information on the accelerator type and model and setting information according to processing performance. The processing capacity setting recording unit 150 retrieves the information from the list in response to an inquiry and responds accordingly; an ACC processing capacity and power consumption setting determination unit 120 determines setting information for the accelerator's processing capacity and fluctuation time based on the traffic volume and fluctuation range output from the input volume acquisition and prediction unit 110 and the list information read from the processing capacity setting recording unit 150; and an ACC processing capacity and power consumption setting input unit 130 reflects the setting information for the accelerator 12 and the cooling mechanism 14 based on the setting information for the accelerator 12 and the cooling mechanism 14 determined by the ACC processing capacity and power consumption setting determination unit 120.

[0137] This ensures responsiveness (<Requirement 2: responsiveness>) in response to fluctuating input data volumes while achieving high power efficiency for various accelerators (<Requirement 1: power efficiency>). Furthermore, by determining the parameters that can be set for each installed accelerator when determining power-saving settings, support for multiple accelerators can be achieved (<Requirement 3: Support for multiple accelerators>). For example, circuit rewriting is possible for FPGAs, sleep is possible for GPUs, and common methods include frequency change and power-off. Furthermore, the cooling mechanism 14 sets its output according to each accelerator and traffic volume.

[0138] Furthermore, among the processes described in the above embodiments and modifications, all or part of the processes described as being performed automatically can be performed manually, or all or part of the processes described as being performed manually can be performed automatically using a known method.In addition, the information including the processing procedures, control procedures, specific names, various data, and parameters shown in the above documents and drawings can be changed as desired unless otherwise specified. Furthermore, the components of each device shown in the figure are conceptual functional components and do not necessarily have to be physically configured as shown in the figure. In other words, the specific form of distribution and integration of each device is not limited to that shown in the figure, and all or part of them can be functionally or physically distributed and integrated in any unit depending on various loads, usage conditions, etc.

[0139] Furthermore, the above-described configurations, functions, processing units, processing means, etc. may be partially or entirely implemented in hardware, for example, by designing them as integrated circuits. The above-described configurations, functions, etc. may also be implemented by software that causes a processor to interpret and execute programs that implement the respective functions. Information on the programs, tables, files, etc. that implement the respective functions may be stored in a memory, a recording device such as a hard disk or a solid-state drive (SSD), or a recording medium such as an integrated circuit (IC) card, a secure digital (SD) card, or an optical disc. [Explanation of symbols]

[0140] 1 Application (APL) 10. Hardware 11 CPU 12. Accelerators 12a Accelerator arithmetic circuit program 13 Input / output section 14 Cooling mechanism 20 Software 100,100A Accelerator State Control Device 110 Input quantity acquisition and prediction unit (prediction unit, prediction procedure) 120 ACC processing capacity / power consumption setting judgment unit (judgment unit, judgment procedure) 130 ACC processing capacity / power consumption setting input section (setting input section, setting input procedure) 140 ACC circuit information recording unit by processing capacity 150 ACC information / processing capacity setting recording unit (processing capacity setting recording unit, processing capacity setting recording procedure) 160 ACC switching processing continuation part (processing continuation part) 170 List Information 200 servers (accelerator-equipped servers) 210 Antenna equipment 220 Post-processing device 1000,1000A Accelerator State Control System

Claims

1. An accelerator state control device that controls a state of an accelerator when a specific process of an application is offloaded to the accelerator for calculation processing, a prediction unit that predicts a processing amount to be offloaded to the accelerator and outputs the prediction result as a traffic amount and a fluctuation range thereof; a processing capacity setting recording unit that stores information on accelerator types and models and setting information according to processing performance as list information, and retrieves information from the list information in response to an inquiry; a determination unit that determines setting information for the accelerator's processing capacity and fluctuation time based on the traffic volume and its fluctuation range output from the prediction unit and the list information read from the processing capacity setting recording unit; a setting input unit that reflects the setting information for the accelerator determined by the determination unit in the accelerator. An accelerator state control device comprising:

2. a processing continuation unit that temporarily continues processing in a CPU (Central Processing Unit) or another accelerator when the calculation function of the accelerator is temporarily stopped due to input of the setting information by the setting input unit; 2. The accelerator state control device according to claim 1.

3. the accelerator has an FPGA (Field Programmable Gate Array), a circuit information recording unit that stores, for each FPGA type, FPGA circuit information and FPGA type information corresponding to processing performance, and responds to an inquiry with the FPGA circuit information and FPGA type information; the circuit information recording unit responds to the determining unit directly or via the processing capacity setting recording unit; The determining unit determines the processing capacity and variable time setting information of the accelerator based on the FPGA circuit information and FPGA type information from the circuit information recording unit.

2. The accelerator state control device according to claim 1.

4. the accelerator has an FPGA (Field Programmable Gate Array) and a GPU (Graphics Processing Unit); The setting input unit The setting information is reflected by changing the frequency and / or turning off the power, in common with the accelerators; The setting information is reflected by circuit rewriting in the case of the FPGA, and by sleep in the case of the GPU.

2. The accelerator state control device according to claim 1.

5. An accelerator state control system comprising: an accelerator state control device that controls a state of an accelerator when a specific process of an application is offloaded to the accelerator for arithmetic processing; and a cooling mechanism that cools a arithmetic unit including the accelerator, a prediction unit that predicts a processing amount to be offloaded to the accelerator and outputs the prediction result as a traffic amount and a fluctuation range thereof; a processing capacity setting recording unit that stores information on the accelerator type and model, setting information according to processing performance, and setting information of the cooling mechanism as list information, and retrieves information from the list information in response to an inquiry; a determination unit that determines setting information for the accelerator's processing capacity and fluctuation time based on the traffic volume and fluctuation range output from the prediction unit and the list information read from the processing capacity setting recording unit; a setting input unit that reflects the setting information for the accelerator and the cooling mechanism based on the setting information determined by the determination unit, in the accelerator and the cooling mechanism. An accelerator state control system comprising:

6. 1. An accelerator state control method for an accelerator state control device that controls a state of an accelerator when a specific process of an application is offloaded to the accelerator for computation, comprising: The accelerator state control device predicting a processing amount to be offloaded to the accelerator and outputting the prediction result as a traffic amount and its fluctuation range; a step of storing information on the accelerator type and model and setting information according to processing performance as list information, and extracting information from the list information in response to an inquiry; determining setting information for the processing capacity and fluctuation time of the accelerator based on the traffic volume, fluctuation range, and list information; and reflecting the setting information in the accelerator based on the setting information for the accelerator.

1. A method for controlling an accelerator state, comprising:

7. An accelerator state control method for an accelerator state control system including an accelerator state control device that controls a state of an accelerator when a specific process of an application is offloaded to the accelerator for arithmetic processing, and a cooling mechanism that cools a arithmetic unit including the accelerator, comprising: The accelerator state control device predicting a processing amount to be offloaded to the accelerator and outputting the prediction result as a traffic amount and its fluctuation range; storing information on the accelerator type and model, setting information according to processing performance, and setting information on the cooling mechanism as list information, and extracting information from the list information in response to an inquiry; determining setting information for the processing capacity and fluctuation time of the accelerator based on the traffic volume, fluctuation range, and list information; reflecting the setting information to the accelerator and the cooling mechanism based on the setting information; 1. A method for controlling an accelerator state, comprising:

8. When a specific process of an application is offloaded to an accelerator for calculation processing, the computer functions as an accelerator state control device that controls the state of the accelerator, a prediction step of predicting a processing amount to be offloaded to the accelerator and outputting the prediction result as a traffic amount and its fluctuation range; a processing capacity setting recording procedure for storing information on the accelerator type and model and setting information according to processing performance as list information, and extracting information from the list information in response to an inquiry; a determination step for determining setting information of the accelerator's processing capacity and fluctuation time based on the traffic volume and fluctuation range output from the prediction step and the list information read from the processing capacity setting recording step; a setting input step of reflecting the setting information to the accelerator based on the setting information for the accelerator determined in the determination step; A program to execute.

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