Bus Synchronous System

Abstract

To provide a bus synchronization system which is split into multiple parts executing different test flows in parallel by use of multiple MEPs.SOLUTION: An example test system includes instruments for controlling testing. Each instrument is controlled by one processing unit. Each processing unit includes: an instrument which is configured to operate on portions of a test program relevant to one instrument that the processing unit controls; and a synchronization mechanism which operates with at least some processing units to produce a synchronized sequence of actions, measurements, or measurements and actions at one test instrument interface absent intervention from a centralized controller.SELECTED DRAWING: None

Description

[Technical Field]

[0001] This specification relates generally to bus synchronization systems. [Background technology]

[0002] Semiconductor test equipment (ATE: automatic test equipment) Sends signals to the device under test (DUT) and It contains electronic components for testing the operation of the DUT by receiving signals therefrom. In some instances, testing a DUT involves multiple tests. The ATE may have multiple instrument modules. The test system may include a plurality of test modules, each of which is configured to perform one or more of the tests. In some examples, the instrument module may include one or more resources. Therefore, each test may need to use different resources to test the same DUT. Different studies may require different combinations of resources. DUTs may be tested simultaneously. In some instances, multiple resources may be used to test a particular DUT. In some instances, multiple resources may be dedicated to testing multiple DUTs. may be shared to carry out Summary of the Invention

[0003] An exemplary bus synchronization system includes a computer bus and a host bus for executing test flows. The instrument module includes a resource and a processing device. The resources operated by a test flow define a domain. The computer issues commands to the instrument module, including the sync command during the test flow. The sync command is configured to send the instrument module its state to the computer buffer. The purpose is to have the instrument module in the domain provide the service and pause the processing device. The status from the modules is aggregated on the computer bus. The information is distributed to the instrument modules. The processing device then executes the command based on the information. An exemplary system may have one or more of the following features: They may be included singly or in combination.

[0004] The information is distributed after all instrument modules in the domain encounter the sync command. The host computer sends commands via a communication bus different from the computer bus. The aggregation of status and distribution of information may be programmed to send to the instrument module. At least some of the commands may be performed independently of the host computer. It may instruct resources within the main to perform actions.

[0005] The instrument module has a first type of endpoint for providing status to the computer bus. A first type of endpoint device may include a contributing endpoint device. Contributing endpoint devices may include computer based receive information from the resource and, based on the information, trigger an action on one or more of the resources. The device may be configured to generate a signal.

[0006] The instrument module may include a second type of endpoint device. An endpoint device receives information from a computer bus and performs a non-contributing endpoint that generates a signal that triggers the operation of one or more of the resources; The device may include a

[0007] The host computer is configured to execute a test program that contains multiple separate instruction flows. The multiple separate instruction flows may include a test flow. An endpoint device may be subscribed to one or more of multiple distinct flows. The endpoint device may be configured to provide access to resources within the domain. The signal may be configured to generate a signal indicating that the resource is ready for that purpose. It is used to trigger the execution of actions that are pre-configured (armed) for An offset may be added to the signal to control the timing of the signal relative to the reception of information. An endpoint device may have an additional port for output to the computer bus. and a receiver for receiving from the computer bus. .

[0008] The status may include a pass or fail status of a test performed by the processor. The mode is a time division multiple access (TDMA) system that transmits periodic frames of multiple bits on a computer bus. A periodic frame may contain bits coded using a header, trailer, , cyclic redundancy check, or 8b / 10b coding. good.

[0009] At least some of the bits of information are used to calculate the system clock counter on the instrument. At least one of the specified values or specified times in the payload on the The computer bus may represent a system time alignment signal for setting Wired-OR bus, point-to-point connections and logic gates, contactless, wireless, or or optical signaling medium, or wired-OR bus, point-to-point connections and logic A combination of one or more of gates, contacts, and wireless or optical signaling media It may include at least one of:

[0010] The information may be received on a computer bus. The information may be received on a different The sync command during the test flow may be received on the communication bus. Immediately before a command that requests an action or measurement from the device under test by the flow. At least a portion of the test flows may be controllable to be asynchronous.

[0011] An exemplary bus synchronization system includes a computer bus and an instrument module. A queue contains resources and processing devices for executing commands from the queue. The management device initiates a scheduled to have the processor module provide status to the computer bus and pause the processing device. The status from the instrument modules is aggregated on the computer bus. The aggregated state is distributed to the instrument module. The processing device performs the information-based The exemplary system is configured to resume execution of the command by the host computer. The host computer may include a controller and a communication bus. It may be configured to output a command.

[0012] An exemplary test system includes instruments for controlling the tests. Each instrument includes a processing unit Each processing unit may be controlled by a test system associated with the instrument it controls. The synchronization mechanism may be configured to operate on at least one part of the test program. Both operate using several processing units and operate the test equipment without intervention from a central controller. Synchronized sequence of actions, measurements, or measurements and actions at the instrument interface This exemplary system is configured to generate a signal using the following features, either alone or in combination: It may contain a combination of these.

[0013] The synchronization mechanism ensures that each processing unit completes its part of the test program. transmitting status data indicating whether the processing has been completed or not, aggregating the status data across all processing units; and configured to transmit one or more aggregated status bits back to all processing units. The processing unit may be configured to perform operations including: When the processing unit completes its part of the test program, it sends a synchronous bus indicate that you have completed that portion of the test program before proceeding to the next portion of the test program. The processing unit receives one or more aggregated status bits, which are used to generate a test system indicates that all other processing units in have completed their part of the test program.

[0014] The synchronization mechanism may have a predetermined timing relative to the system clock, This allows multiple instruments to receive one or more aggregated status bits and take action, measure, or both actions and measurements with predictable and repeatable timing across multiple instruments. The synchronization mechanism is triggered to run in alignment with each processing unit. and can be aggregated to generate one or more aggregated state bits. The device may be configured to support status data containing multiple status bits that can be one or One or more aggregated status bits may be transmitted to all of the processing units. A number of aggregated status bits synchronize all instruments in the test system to take action. To synchronize a sequence of actions, a sequence of measurements, or a sequence of actions and measurements It may be possible to use it for

[0015] The status data includes at least one parameter for conveying the pass or fail status of the test program. The status data may include bits of the following: It may include one or more state bits that are encoded using periodic frames. A target frame is one of the following: a header, a trailer, a cyclic redundancy check, or 8b / 10b encoding. A periodic frame may be characterized by one or more status bits. It may also be configured to transmit external information.

[0016] The bit or bits transmitted to the processing unit are the system clock counter on the instrument. This may represent a system time alignment signal for setting the timer to a specified value. One or more aggregated status bits synchronize all instruments in a test system to take action. To synchronize a sequence of actions, a sequence of measurements, or a sequence of actions and measurements It may contain one status bit for

[0017] Synchronization mechanisms include wired-OR buses, point-to-point connections, and logic gates. , contactless, wireless, or optical signaling media, or wired-OR bus, point-to-point -point connections and logic gates, contacts, and wireless or optical signaling media or a combination of at least one of the synchronization mechanisms. Some may be controllable to be disabled either automatically or manually. At least some of the mechanisms are controlled to operate only on a portion of the test program. It may be possible.

[0018] Advantages of this exemplary system may include one or more of the following: It offers one or more processors (e.g., one processor) for fewer resources. By providing resources, they can operate independently and in parallel with all other resources. In addition, it is possible to use one or more processors (e.g. , one processor) to reduce communication latency between the processor and the resource. The synchronization system may include one or more processors as described. The synchronization system also addresses the synchronization issues that may arise with providing One resource per processor that will be synchronized with any other resource in The granularity can be finer than groups. In some cases, there may be no need for a central controller to perform the synchronization.

[0019] Any two or more of the features described herein, including in this Summary section may also be combined to form embodiments not specifically described herein. Cut.

[0020] The systems, techniques and processes described herein, or portions thereof, may be implemented using one or more non-uniform The method may be stored on a temporary machine-readable storage medium and executed on one or more processing devices. A computer program containing instructions that can control (e.g., regulate) the operations described in the document. The systems and techniques described herein can be implemented as and / or controlled by a system product. and processes, or portions thereof, may involve one or more processing devices to perform various operations. and a memory storing executable instructions for It can be implemented as a system.

[0021] The details of one or more embodiments are set forth in the accompanying drawings and the description below. The features, objects, and advantages of the present invention will be apparent from the description and drawings, and from the claims. It would be. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 2 is a block diagram illustrating an exemplary command sequence. [Figure 2] 2 is a block diagram illustrating an exemplary order in which the command sequence of FIG. 1 may be executed. [Figure 3] FIG. 2 is a block diagram illustrating an exemplary order in which commands are encountered, including a "sync barrier" applied by a bus synchronization system. [Figure 4] FIG. 4 is a block diagram illustrating an exemplary order in which the command sequence of FIG. 3 may be executed. [Figure 5] FIG. 1 is a block diagram of components that may be included in an exemplary bus synchronization system. DETAILED DESCRIPTION OF THE INVENTION

[0023] Like reference numbers in different drawings indicate like elements.

[0024] Described herein are exemplary embodiments of a bus synchronization system and its components. In some embodiments, the bus synchronization system is incorporated into a test system such as an ATE. Although included in the NI PXIe-4111, bus synchronization systems are not limited to use with test systems or for testing in general. stomach.

[0025] An exemplary test system may comprise multiple instrument modules (or a single module) that perform tests on the DUT. Each instrument module contains one or more resources, such as radio frequency (RF) F) Includes signal generators, microwave signal generators, processors, power supplies, memory, etc. In general, an instrument module resource (or simply "resource") is a resource that stores digital data, analog data, and Receive, transmit, process, store, or otherwise process log signals or both digital and analog signals. or any other suitable type of electronic hardware device or software operating thereon. Each resource may be or may include an instrument module. One or more of the above module embedded processors (MEPs) controlled by multiple MEPs (or "processing units"). By using the , an exemplary test system can be divided into multiple parts that run different test flows in parallel. Can be divided.

[0026] The use of multiple MEPs can create synchronization problems. Executes commands for the test flow from the command queue. Commands across multiple queues and across multiple resources are Consider the command sequence 100 shown in FIG. is executed by different system resources A, B, and C, which may be on different instrument modules. In Figures 1 and 2, each block represents a time slot in which execution occurs. In this example, no synchronization is performed and the commands shown in Figure 1 are executed by the resource in order 10 of Figure 2. The exemplary synchronization process described herein may be performed in the order shown. The system addresses this issue by ensuring that commands in the same test flow are executed in the correct order (e.g. , then line 1, then line 2, then line 3, then line 4).

[0027] As an overview, in an exemplary synchronization process, a host computer on a test system synchronizes with a DU. Execute the test flow for T. The test flow may be, for example, It may include commands or other instructions for performing the test. A DUT, such as a semiconductor device, may consist of multiple components, such as digital components, analog components, and It may include analog components, wireless components, etc. The experimental flow runs simultaneously on different components. The component uses different instrument module resources for testing, e.g. analog test resources, Digital test resources, wireless test resources, etc. may be required. These more needed resources constitute the test domain, which requires synchronization. For example, synchronization can be used to ensure that different tests performed on different components of the DUT are performed at the same time. The processes may be implemented to occur at the same time or simultaneously.

[0028] The instrument module resources containing the test domain may be on the same instrument module or on different instrument modules. may be on the same instrument module or on a combination of the same and different instrument modules. The resources that contain the test domain are the resources of all test modules in the test system. In any test system, for example, one or more DUTs Multiple test flows used to test different components, and therefore multiple Each of these multiple test domains may be a different combination of The instrument module resources may include different instrument modules corresponding to different test domains. Module resources may be independently synchronized using the processes described herein.

[0029] A test domain with synchronized instrument module resources is a "sync" domain. For the examples described herein, As previously mentioned, each instrument module includes at least It contains one MEP, which is configured to execute commands to perform the tests. Each instrument module may be connected to a sync bus. One endpoint that constitutes a hardware interface, for example, and Interface with the sync bus, e.g., sync, which configures the software interface and a resource driver (SRD).

[0030] In some embodiments, the sync bus may include one or more time division multiplexed (TDM) time-division multiplexed computer bus or other It may be implemented using any suitable transmission medium. In some embodiments, the sync bus is separated from the communication medium used to transmit commands for the experimental flow, and then The sync bus has a tree topology, with the sync bus at the root of the tree. The distributed hardware may include logic gates built into the distributed hardware with the master. As stated in the specification, a sync bus master is a bus master that controls instruments within the same sync domain. The sync bus is configured to synchronize module resources. The host computer is not directly involved in the synchronization. The role of the test computer is to manage the commands executed by the instrument modules in the test domain. By identifying the sequence of events and applying the appropriate synchronization command, called a sync barrier, This involves placing it in the correct position within each command series for the c domain. In some examples, the location of the synchronization command can be specified by the user of the test system. In this case, the host computer also synchronizes the instrument module with the endpoint. Insert commands to subscribe to and from domains. In this example, all instruments are automatically subscribed to all or some of the sync domains. The host computer is configured to Commands that command instrument modules to subscribe to and from the sync domain. There is no need to insert a command.

[0031] In one example, the host computer sends a series of commands for the test flow to Each instrument module that has resources required by the test flow on a communication medium other than the SYNC bus For each instrument module, its MEP communicates the queued commands Stores the series in computer memory. Queues are dedicated to a specific sync domain. Therefore, no commands are received from the host computer. , including the sync barrier command.

[0032] In some embodiments, only commands that request an action or measurement on the DUT Therefore, in some instances, the instruction stream of the test flow and only these commands are preceded by a sync barrier command. An example is Device Interface Board (DIB)-visible commands. The interface between the experimental system and the DUT, e.g., the DUT is connected to it, This is the board through which signals are exchanged between the DUT and the test system. - Visible has an observable effect on the DUT, or more precisely on the DIB, or vice versa This is a generic name given to any command that can be executed, and the measurement result is what happens on the DIB. Some setup commands may not require synchronization. For example, specific measurement parameters such as sample rate or number of samples captured, or pattern balance Various parameters of the beam are not observable from the DIB and do not require synchronization. In an embodiment, synchronization is limited to commands that require an action or measurement on the DUT. do not have.

[0033] In some embodiments, the host computer may include a sync variable in the command series. A sync command (or simply a "sync barrier") must be placed before the DIB-visible command or after the sync precedes any other command that requires sy. The nc barrier command is used to start a test program in the test flow of the instrument module. To execute the command, the MEP must It reads these from the queue and executes the command or performs any other necessary operations related to the command. When a MEP encounters a sync barrier in its queue, it P sends a "sync barrier reached" command (or simply " The sync barrier reached command is output to the sync bus. At this point, the MEP has Therefore, once the MEP has completed its part of the test program, it will c) indicates via a barrier-reached command that it has completed that part of the test program. Before proceeding to the next part of the test program, the MEP must ensure that all other processing units are Aggregated status information (e.g., aggregated status) indicating the completion of each part of the program. Waits to receive a byte (bit).

[0034] On the sync bus, independent of the host computer, the sync bus master is "sync barrier reached" from each of the instrument module endpoints in the nc domain Combine commands. For example, a sync bus master receives a "sync barrier reached" command. A logical "AND" may be performed on all of the commands, or other suitable processing may be performed. The sync bus master is responsible for each of the instrument module's endpoints in the same sync domain. When it determines that each has issued a "sync barrier reached" command, it issues a "sync "nc barrier pass" command (or simply "sync barrier pass"). The "pass barrier" command may involve one state bit or multiple state bits. It may be possible to configure an aggregated state of received "sync barrier reached" commands. stomach.

[0035] Each sync bus endpoint within that sync domain is a "sync barrier crossing" A trigger that receives commands and triggers the operation of instrument module resources within its domain The trigger signal synchronizes the actions of instrument module resources. The actual actions taken by each of the instrument module resources may vary. The MEP also waits for frames in the queue after receiving a "pass sync barrier" command. Resume execution of the command.

[0036] Therefore, in this example, the exemplary bus synchronization system allows All instrument module resources within the system can operate simultaneously. The system can be used by multiple instrument module resources that operate independently of each other. Therefore, in some instances, synchronization may require multiple operations, e.g., by a host computer. No central coordination between a disparate number of resources is required.

[0037] In the above example, each instrument module may contain multiple endpoints. The endpoints in the module include contributing endpoints. Receives a synchronization status, e.g., "sync barrier reached" command, from the MEP of the instrument module and hardware configured to provide its synchronization state to the sync bus. In some embodiments, the state output on the sync bus is determined using the MEP in the test system. may be one or more bits representing the pass or fail status of a test performed by In some instances, it may include a pass or fail status or other type. The output of data representing the state of the sync barrier can be triggered at any time, regardless of the sync barrier command. A contributing endpoint also represents the total number of instrument module resources in a sync domain. Information indicating "ready" status, e.g., "pass sync barrier" command received , configured to provide this information to instrument module resources within the same sync domain. An instrument module may also contain zero, one, or more non-contributing endpoints. A non-contributing endpoint may share all instrument module resources within a sync domain. is "ready", for example, "passing the sync barrier" and includes hardware configured to provide information to instrument module resources; However, non-contributing endpoints do not transmit on the sync bus and do not provide information to the MEP. stomach.

[0038] In some embodiments, the state provided by the contributing endpoints is time division multiplexed. A connection method that consists of multiple bits on a serial data bus, such as a sync bus. In some embodiments, the bits are coded using a periodic frame. The system may optionally include a header, trailer, cyclic redundancy check, and 8b / 10b Any suitable media encoding may be used and may be associated with serial data transmission. In some embodiments, the frame may be any type of Frame type indicator in the frame header to indicate whether information is being transmitted data to transmit or receive other types of information on the same physical wire. May be used.

[0039] 1 and 2, FIG. 3 is a block diagram of a bus synchronization system according to the present invention. 1 shows an exemplary sequence 102 in which commands are encountered that includes a "sync barrier" used In Figures 3 and 4, as with Figures 1 and 2, each block is represented by a time at which execution occurs. Using the system described herein, a "sync barrier" is encountered. This synchronizes the instrument module resources within the same sync domain. The commands are executed in the order shown in Figure 4 (e.g., row 1, then row 2, then row 3, then row 4, then row 5). , then the command on line 6, then the command on line 7). As shown, the "sync barrier" prevents It is used to control when a task runs on different resources A, B, and C, thereby This allows commands in the same sync domain to be executed in the appropriate order across multiple independent resources. The examples in Figures 3 and 4 show that all resources are available within the respective test domains. waits for all other resources in the to finish executing their commands and reach the sync barrier before , and indicates that another command should be executed.

[0040] FIG. 5 illustrates the I / O (input / output) engine 106 and the The MEP 105 includes a command queue 107, an SRD 108, and a shared memory 109. The instrument module includes a sync bus endpoint 110 (e.g., a contributing endpoint). It also includes a transmitter (TX) 111 and a receiver (RX) 112. FIG. 5 also shows the sync bus 114, which is the TDM bus and the sync bus master. Includes Sta. 115.

[0041] In the example in Figure 5, the endpoint operates with commands for several different domains. In this example, the I / O engine of the MEP receives commands from the host computer. The MEP 105 queues host commands transmitted on the communication bus. This communication bus receives test flow commands from the computer. Ethernet bus or any other suitable communication medium, including wired and wireless media. In some instances, commands on the instrument module may be transmitted via a command are pre-stored in a command queue and are not received from the host computer. In the example, the MEP 105 may be configured to control, for example, one instrument module of a test system. The processing device may include one or more processing devices configured, e.g., programmed, to: Examples of such devices are described herein. In one example, each of the test domains of the MEP There is a separate command queue for one or more SRDs running on a MEP. Reads commands for the sync domain from the command queue and processes them. Manage / execute.

[0042] In an exemplary operation, the next command in the queue to be executed is "sync valid" If the state is "a", SRD sets the state of the shared memory to "sync barrier not passed", This means that the state remains set to "passing the sync barrier" from the previous pass. Then, the SRD sends a "sync" to the sync bus endpoint. indicates that the "sync barrier" has been reached and waits for the shared memory to indicate that the "sync barrier" has been crossed. The sync bus endpoint will not start in this state if it is not ready. The transmission may be delayed 116, otherwise the sync bus endpoint is in sync Set the bus endpoint transmission state to "sync barrier reached" and issue this command The nc bus transmits commands to the s Transmit to the ync bus master.

[0043] The sync bus master receives signals from multiple resources in the sync domain, e.g., all resources. Aggregates received sync barrier states (e.g., "sync barrier reached" commands). Once all resources in the sync domain have reported that they have reached the sync barrier, The nc bus master issues a "pass sync barrier" command to the As mentioned above, the sync bus master provides the sync domain with Aggregate (e.g., OR) the state from all endpoints in the It produces one result per nc domain. In this example, as mentioned above, the result is The resulting "passing the sync barrier" state is when all of the sync bus endpoints are "s If the sync barrier has been reached, the result is TRUE. The "Barrier Crossing" command is sent from the sync bus master to the sync bus endpoint receiver. This command is transmitted on the sync bus to each of them, and all of them receive it.

[0044] Sync bus endpoint receiver with instrument module "passes the sync barrier" When it detects the command, the sync bus endpoint receiver sends two The sync bus endpoint receiver operates in the sync bus endpoint Set the transmitter state to "sync barrier not reached" and share "sync barrier passed" The SRD waits for this state change, which causes the MEP to Subsequent commands in the queue can be processed, resulting in different instrument module M The EPs are all in the same sync domain and can synchronize their operations.

[0045] In some embodiments, the sync bus endpoint transmitter is After reaching the sync bus, the sync bus endpoint transmitter The "sync barrier crossing" command is then confirmed by the sync bus master. It may be held until

[0046] Each sync bus endpoint also accepts sync bus commands, e.g., "sync valid" Receives triggers for resources on the instrument module, such as "data state transition" from the sync bus. For example, each resource may be configured to generate a trigger signal in response to a trigger signal. In some examples, The trigger signals trigger resources on different modules, which then The trigger signal is used to ensure that the resource is not only in the correct order, but also simultaneously. It is used to trigger the device to take the action that it has been previously configured to take. good.

[0047] In some embodiments, the sync domain produces only one trigger signal at a time. However, one trigger signal can be applied to multiple receiver outputs with different time delays. Each of the trigger signals is applied to one of a number (e.g., 32) instrument module resources. For example, a trigger signal for the sync domain can be added to multiple instrument modules. A trigger signal for the sync domain can be applied to one instrument module. Each endpoint receiver output can also be applied to a unique trace resource. The trigger signal offset delay may be introduced. Even though they are associated with the nc domain, their offsets are not included in the instrument module resource can be programmed differently to compensate for different paths in

[0048] In some embodiments, such a sync bus frame is a start of frame and a frame It contains a header that indicates the type of message represented by the payload. Data may follow, which may include the sy for each of one or more available test domains. In some examples, the timing of the sync frame may be: The payload size may be adjusted based on the available test domain. The more test domains, the larger the payload and the faster the signal is tested. It takes longer to propagate through the system.

[0049] In some examples, the sync bus is used to For example, a sync bus master can send a sync bus Commands the endpoint to update its time-of-day (TOD) clock. The sync bus endpoint can send a message to update the sync bus master. The TOD clock is the system clock on each instrument. System time alignment signal used to set counters to specified values so that all instruments can set their clocks relative to the system clock. Set it to the same specified value with exactly repeatable timing.

[0050] Therefore, at any appropriate time, the sync bus endpoint transmitter Instead of sending the state of the sync, you can send a message and at any convenient time Bus masters can send messages rather than sending "sync barrier crossings" In some embodiments, when the sync bus master receives a frame without state, The sync bus master responds with a frame type that also does not contain state. In the example, when the sync bus endpoint receives a frame without state, s The sync bus endpoint retains its state from the previous frame. The frame state is saved.

[0051] In some embodiments, the test system may include multiple MEPs, i.e., instrument modules. Each MEP may have one for each instrument module, or one MEP may serve multiple instrument modules. In the latter case, the MEP assigns the sync bus endpoint of one instrument module to a contributing may be configured as a stop point and used to provide a sync barrier state. The MEP may assign sync bus endpoints on other modules to non-contributing endpoints. In some embodiments, the MEP may be configured to be a sync bus end. Configure all of the points to be contributing, and set the sync barrier state for each sync bus element. The synchronization system is therefore configurable. This allows the same module to be used in a cheaper system with slightly reduced functionality. It becomes possible to do this.

[0052] The exemplary test system exhibits two related features: simultaneous test flow and flow performance. In some instances, a concurrent test flow may support multiple test sites of a DUT. The sections must be sufficiently independent to be tested simultaneously. The user may specify which tester resources to associate with each section of the DUT. A test program may be written in separate flows, each for one section of the DUT. The host computer processes these flows sequentially, using only the resources associated with them. Even if you run multiple flows at the same time, MEP will execute commands for multiple flows in parallel.

[0053] Flow per site is the same as the concurrent test flow, but the user can write different flows. Instead of running multiple tests, the execution of one flow depends on the test results of the DUT. groups sites with similar results, and the test flow is repeated once for each group of sites. The commands executed during the flow can be different for each group. As the test program continues, the flows will split and merge again. Resources that execute the code are considered members of a test domain. Resources in different test domains operate with little or no interaction with each other. The difference between the two features is that in the simultaneous test flow, the test domains are tested simultaneously. These are known prior to the execution of the experimental program, whereas in flow-per-site these are known downtime. It is to be made dynamically.

[0054] In some embodiments, the bus synchronization system allows a test engineer to synchronize some of the test programs. In some embodiments, the automatic synchronization may be disabled for at least some of the devices. In this case, the bus synchronization system is used to synchronize all the test programs that require synchronization. For example, the identification may be performed based on the input of a test engineer. may be performed without

[0055] In some embodiments, the sync bus uses a wired-OR bus to connect the points Using two-point connections and logic gates, suitable contactless, wireless, or optical signaling It may be implemented using a sig- nal, a sigma, or any suitable combination of these transmission media. In some embodiments, the sync bus communicates status to hardware or software. , aggregate state and distribute the aggregated state or other information over the same or different paths. Any suitable data communication path configured to transmit to all MEPs via the It may be implemented using

[0056] In some embodiments, the bus synchronization may not be symmetric. In this case, a "passing sync barrier" signal or other appropriate synchronization or other signal is As mentioned above, it can also be transmitted over the Ethernet bus rather than over the sync bus.

[0057] As described herein, the exemplary bus synchronization system therefore includes multiple distributed This allows for synchronized operation across multiple distributed MEPs, eliminating the need for central control. The time it takes the selected MEP to perform each part of the test program varies. Typically, it is not known in advance how long such a process will actually take. Therefore, each MEP must be able to determine whether it is part of a separate testing program. flexibility in the time it takes to execute a task, and this time must be known in advance Bus synchronous systems also have relatively low latency, which means For example, some test programs may contain thousands of synchronization events per second. , which may be advantageous.

[0058] In some embodiments, each of the MEPs runs its own copy of the test program. , identify where in the command queue the sync barrier should be placed, and To identify the sync domain to which the instrument module containing the MEP should subscribe In this distributed system, a host computer executes the test program and Place the sync barrier command at the appropriate position in the command series for the sync domain. It can be implemented instead of or in combination with the above methods.

[0059] The exemplary test systems described herein may be hardware or hardware-based. Implemented by one or more computer systems, including a combination of software, and and / or may be controlled using, for example, a system such as that described herein. The system consists of various control units at various points in the system that control the operation of the automatic elements. The central computer may include various controllers and / or processing devices. The central computer, controller, and processor may coordinate operations among the processors or processing devices. The control device runs various software routines to control and coordinate various automatic elements. That's fine.

[0060] The exemplary systems described herein may be implemented, at least in part, by one or more computers. a data program product, e.g., one or more information media, such as one or more non-transitory machine-readable media; tangibly embodied in an information carrier, e.g. one or more data processing devices, e.g. A programmable processor, a computer, a plurality of computers, and / or a programmer one or more logic components for execution by or for controlling the operation of a It can be controlled using multiple computer programs.

[0061] Computer programs may be in any form, including compiled or interpreted languages. It can be written in any programming language and can be used as a standalone program or Modules, components, subroutines, or uses within a computing environment It can be deployed in any form, such as a computer program, a computer program, or any other unit suitable for use. The program can be distributed on one computer, at one site, or across multiple sites. It is distributed and deployed to run on multiple computers interconnected by a network. It can be opened.

[0062] The actions associated with conducting all or part of a test are described herein. One or more computers executing one or more computer programs to perform the functions described in The tests can be performed by multiple programmable processors. All or part of the tests can be application specific. Logic circuit configuration, such as FPGA (field programmable gate array) rray) and / or ASIC (application-specific inte This can be done using a grated circuit.

[0063] Processors suitable for executing a computer program include, for example, general purpose and special purpose processors. any one of a variety of microprocessors and digital computers Typically, a processor includes a read-only storage area. It stores instructions and data from the hard disk or random access storage area, or both. An element of a computer (including a server) receives one or more instructions. a processor and one or more storage area devices for storing instructions and data Generally, a computer also includes one or more machine-readable storage media, e.g., Mass storage devices for storing data, such as magnetic, magneto-optical disks, or The optical disc drive may include or be operatively coupled to receive data therefrom, or or transmit data thereto, or both. Suitable machine-readable storage media for embodying the data include, for example, semiconductor storage area drives. devices, such as EPROM, EEPROM, and flash storage area devices; Magnetic disks, such as internal hard disks or removable disks, magneto-optical media, and Includes CD-ROM and DVD-ROM discs.

[0064] Any "electrical connection" as used herein may refer to a direct physical connection or to a connection through intervening components. electrical current between connected components, which may or may not contain electrical components Any wired or wireless connection that allows the flow of signals may be implied unless otherwise specified. Any "connection" that includes electrical circuitry that allows a signal to flow is also a qualifying "connection." Regardless of whether the word "electrical" is used, it is an electrical connection and not necessarily This does not necessarily mean a direct physical connection.

[0065] Specifically, by combining elements of different embodiments described herein, Other embodiments not described above may be formed. Elements may be constructed in accordance with the structures described herein. may be omitted from the structure if it does not adversely affect their operation. Various separate elements may be combined with one or more individual elements to perform the functions described. You can also combine them.

Claims

1. 1. A system comprising: a computer bus; a host computer that executes multiple test flows; Multiple instrument modules and Including, an instrument module including a plurality of resources and a processing device; A plurality of resources operated by a single test flow define a single domain; the host computer is configured to output commands, including a sync command, to the plurality of instrument modules within the test flow; the sync command causes the one instrument module to put a state on the computer bus to pause the processing device; states from the instrument modules in the domain are aggregated on the computer bus; Distributing information to the plurality of instrument modules based on the aggregated state; the processing device is configured to resume execution of a command based on the information; The sync command in the test flow immediately precedes a command in the test flow that requires an action or measurement on a device under test by the test flow.

2. The system of claim 1 , wherein the information is distributed after all instrument modules in the domain encounter a sync command.

3. 2. The system of claim 1, wherein the host computer is programmed to send the commands to the plurality of instrument modules over a communications bus that is different from the computer bus.

4. The system of claim 1 , wherein the aggregating of state and the distributing of information are performed independently of the host computer.

5. The system of claim 1 , wherein at least some of the commands instruct multiple resources in the domain to perform an action.

6. the one instrument module includes an endpoint device that provides status to the computer bus; the endpoint devices include one contributing endpoint device; The system of claim 1 , wherein the contributing endpoint device is configured to receive the information from the computer bus and, based on the information, generate a signal that triggers operation of one or more of the resources.

7. the one instrument module includes an endpoint device; 2. The system of claim 1, wherein the endpoint devices include a non-contributing endpoint device that receives the information from the computer bus and generates a signal that triggers operation of one or more of the resources based on the information.

8. the host computer is programmed to execute a test program including a plurality of separate instruction flows; The system of claim 1 , wherein the plurality of separate instruction flows includes the test flow.

9. the one instrument module includes an endpoint device; The system of claim 8 , wherein the endpoint device is configured to be subscribed to one or more of the plurality of separate flows.

10. the one instrument module includes an endpoint device; The system of claim 1 , wherein the endpoint device is configured to generate a signal to provide to a resource within the domain.

11. The system of claim 10 , wherein the signal triggers the resource to perform a pre-configured action.

12. The system of claim 10 , wherein an offset may be added to the signal to control the timing of the signal relative to the reception of the information.

13. the one instrument module includes an endpoint device; 2. The system of claim 1, wherein the one endpoint device includes a transmitter that outputs to the computer bus and a receiver that receives from the computer bus.

14. The system of claim 1 , wherein the status comprises a pass or fail status of a test performed by the one processing device.

15. 2. The system of claim 1, wherein said state comprises bits encoded onto said computer bus in a time division multiple access fashion using periodic frames of bits.

16. 16. The system of claim 15, wherein the periodic frames are characterized by one or more of a header, a trailer, a cyclic redundancy check, or 8b / 10b encoding.

17. 16. The system of claim 15, wherein at least some of the plurality of bits represent a system time alignment signal for setting a system clock counter on the one instrument module to at least one of an explicit value or an explicit time within a payload on the computer bus.

18. 10. The system of claim 1, wherein the computer bus comprises at least one of: a wired-OR bus; point-to-point connections and logic gates; contactless, wireless, or optical signaling; or a combination of one or more of: a wired-OR bus; point-to-point connections and logic gates; contactless, and wireless or optical signaling.

19. The system of claim 1 , wherein at least some of the test flows are controllable to be asynchronous.

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