Sensor device, sensing module

Abstract

This sensor device comprises a semiconductor substrate and a wiring layer section including a plurality of wiring layers formed on the semiconductor substrate. Pixels are formed in a layered structure consisting of the semiconductor substrate and the wiring layer section, and said pixels include a photoelectric conversion element for performing photoelectric conversion, a first charge holding section and a second charge holding section for holding a charge accumulated in the photoelectric conversion element, a first transfer transistor for transferring a charge to the first charge holding section, and a second transfer transistor for transferring a charge to the second charge holding section. Sheet sections are formed surrounding the gate wiring of each of the first and second transfer transistors extending in the thickness direction in the wiring layer section.

Description

[Technical Field]

[0001] The present technology relates to a sensor device and a sensing module having pixels that transfer charges accumulated in a photoelectric conversion element to separate charge storage sections using two transfer transistors, and in particular to a technical field related to reducing power consumption. [Background technology]

[0002] As a ranging technology, a distance measurement technique using a ToF (Time Of Flight) method has been proposed. The ToF method is classified into a direct ToF method and an indirect ToF method.

[0003] In the indirect ToF method, light emitted from a light source is reflected by an object, and the reflected light from the object is photoelectrically converted by a photoelectric conversion element such as a photodiode.The signal charge obtained by this photoelectric conversion is then distributed to two FDs (floating diffusion regions) by a pair of transfer transistors that are alternately driven.

[0004] It should be noted that Patent Document 1 below discloses a technology for a distance measurement module that performs distance measurement using an indirect ToF method. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2020-13909 Summary of the Invention [Problem to be solved by the invention]

[0006] Here, in the indirect ToF method, the pair of transfer transistors described above are driven at high speed so as to repeatedly turn on and off in a short cycle of, for example, 10 MHz (megahertz) to 200 MHz, which poses a problem of increased power consumption.

[0007] This technology was developed in consideration of the above circumstances, and aims to reduce power consumption in sensor devices that are configured to transfer charges accumulated in a photoelectric conversion element to separate charge storage units using two transfer transistors, such as indirect ToF sensor devices. [Means for solving the problem]

[0008] The sensor device according to the present technology includes a semiconductor substrate and a wiring layer portion formed on the semiconductor substrate and having a plurality of wiring layers, and pixels each having a photoelectric conversion element that performs photoelectric conversion, a first charge holding portion and a second charge holding portion that hold charges accumulated in the photoelectric conversion element, a first transfer transistor that transfers the charges to the first charge holding portion, and a second transfer transistor that transfers the charges to the second charge holding portion are formed in a stacked structure of the semiconductor substrate and the wiring layer portion, and a shield portion is formed to surround each of the gate wirings of the first and second transfer transistors that extend in the thickness direction in the wiring layer portion. The shielding portion makes it possible to reduce the capacitive load on the gate wiring from the surrounding wiring.

[0009] In the sensor device according to the present technology described above, the shield portion may be formed across a plurality of the wiring layers. This increases the area in which the shield portion covers the gate wiring in the stacking direction of the wiring layer portion.

[0010] In the sensor device according to the present technology described above, the gate wiring may have a wiring that extends in an in-plane direction inside the shield portion. This makes it possible to apply the same process for forming gate wiring in the area inside the shield part as for the wiring formation process in the area outside the shield part, which is to form (dummy) wiring in each wiring layer and then form one layer's worth of vias.

[0011] In the sensor device according to the present technology described above, it is conceivable that the gate wiring is formed by a through via that penetrates the plurality of wiring layers. By using a through via, it becomes unnecessary to form wiring in the in-plane direction in the gate wiring, and therefore it becomes possible to form the gate wiring thin.

[0012] In the sensor device according to the present technology described above, it is conceivable that inter-pixel wiring to which the gate wiring is connected is formed in the farthest wiring layer, which is the wiring layer in the wiring layer portion that is farthest from the semiconductor substrate, and the shield portion extends from an adjacent wiring layer of the farthest wiring layer in the wiring layer portion toward the semiconductor substrate side. This makes it possible to maximize the area in which the shield portion covers the gate wiring in the stacking direction of the wiring layer portion when the shield portion is formed by digging a trench in the wiring layer portion.

[0013] In the sensor device according to the present technology described above, the shield portion may have a ring-shaped cross section in an in-plane direction. This makes it easier to make the depth of the shield portion uniform when the shield portion is formed by digging a trench in the wiring layer portion.

[0014] In the sensor device according to the present technology described above, it is conceivable that the shield portion may be configured to be formed of an insulating material different from an interlayer insulating material in the wiring layer portion. This allows the shield portion to be made of a material that has higher insulating properties than the interlayer insulating material.

[0015] In the sensor device according to the present technology described above, it is conceivable that the shield portion is formed from a low-k material. This improves the insulating properties of the shielding portion.

[0016] In the sensor device according to the present technology described above, it is conceivable that the shield portion is configured as a hollow portion. This makes it possible to eliminate the need for a step of filling the trench with an insulating material when forming the shielding portion by digging a trench in the wiring layer portion.

[0017] The sensor device according to the present technology described above may be configured as a sensor device for distance measurement using an indirect ToF method. In indirect ToF, the first and second transfer transistors are driven at high speed, which tends to increase power consumption.

[0018] The sensing module according to the present technology comprises a light-emitting unit that emits light for distance measurement, and a sensor unit that receives light emitted from the light-emitting unit and reflected by an object, the sensor unit comprising a semiconductor substrate and a wiring layer unit formed on the semiconductor substrate and having a plurality of wiring layers, and pixels each having a photoelectric conversion element that performs photoelectric conversion, a first charge holding unit and a second charge holding unit that hold charges accumulated in the photoelectric conversion element, a first transfer transistor that transfers the charges to the first charge holding unit, and a second transfer transistor that transfers the charges to the second charge holding unit are formed in a stacked structure made of the semiconductor substrate and the wiring layer unit, and a shield unit is formed to surround each of the gate wirings of the first and second transfer transistors that extend in the thickness direction in the wiring layer unit. Such a sensing module according to the present technology also provides the same effects as the sensor device according to the present technology described above. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a block diagram for explaining a configuration example of a distance measuring device including a sensor device according to a first embodiment of the present technology; [Figure 2] FIG. 2 is a block diagram illustrating an example of an internal circuit configuration of a sensor device according to an embodiment. [Figure 3] 2 is an equivalent circuit diagram of a pixel included in the sensor device according to the embodiment. FIG. [Figure 4]FIG. 2 is a plan view for explaining a schematic structure of a pixel according to the first embodiment. [Figure 5] FIG. 2 is a cross-sectional view for explaining a schematic structure of a pixel according to the first embodiment. [Figure 6] FIG. 2 is a plan view illustrating the structure of a shielding section according to the first embodiment. [Figure 7] FIG. 10 is a cross-sectional view of a pixel for explaining inter-pixel wiring to which a gate wiring is connected. [Figure 8] FIG. 10 is a cross-sectional view for explaining a schematic structure of a pixel according to a second embodiment. [Figure 9] FIG. 10 is a cross-sectional view of a pixel for explaining inter-pixel wiring to which a gate wiring is connected in the second embodiment. [Figure 10] 10 is a cross-sectional view of a pixel for explaining an example in which a shield portion is a cavity portion. FIG. [Figure 11] 10 is a cross-sectional view of a pixel for explaining an example of a shield portion having a layer made of an insulating material and a layer made of a gas. FIG. [Figure 12] 10A and 10B are plan views illustrating modified examples relating to the shape of the shield portion. [Figure 13] FIG. 10 is a plan view illustrating another modified example relating to the shape of the shield portion. [Figure 14] FIG. 10 is a plan view illustrating yet another modified example relating to the shape of the shield portion. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments of the present technology will be described in the following order with reference to the accompanying drawings. <1. First embodiment> (1-1. Configuration of distance measuring device) (1-2. Circuit configuration of the sensor unit) (1-3. Pixel circuit configuration) (1-4. Example of pixel structure) (1-5. About the shielding part) 2. Second Embodiment <3. Modifications> <4. Summary of embodiments> <5. This technology>

[0021] <1. First embodiment> (1-1. Configuration of distance measuring device) FIG. 1 is a block diagram illustrating an example of the configuration of a distance measuring device 10 including a sensor device according to a first embodiment of the present technology. The distance measuring device 10 includes a sensor unit 1 corresponding to the sensor device of the first embodiment, a light emitting unit 2, a control unit 3, a distance image processing unit 4, and a memory 5. In this example, the sensor unit 1, the light emitting unit 2, and the control unit 3 are formed on the same substrate and configured as a sensing module 6.

[0022] The distance measuring device 10 is a device that performs distance measurement using a ToF (Time of Flight) method. Specifically, the distance measuring device 10 in this example performs distance measurement using an indirect ToF method. The indirect ToF method is a distance measuring method that calculates the distance to an object Ob based on the phase difference between light Li irradiated onto the object Ob and reflected light Lr obtained when the irradiated light Li is reflected by the object Ob.

[0023] The light emitting unit 2 has one or more light emitting elements as a light source, and emits irradiation light Li to the object Ob. In this example, the light emitting unit 2 emits infrared light having a wavelength in the range of 780 nm to 1000 nm as the irradiation light Li.

[0024] The control unit 3 controls the light emission operation of the light emitter 2 to emit the illumination light Li. In the case of the indirect ToF method, the illumination light Li is intensity-modulated light whose intensity changes at a predetermined cycle. Specifically, in this example, pulsed light is repeatedly emitted at a predetermined cycle as the illumination light Li. Hereinafter, the emission cycle of such pulsed light is referred to as an "emission cycle Cl." Furthermore, the period between the emission start timings of pulsed light when pulsed light is repeatedly emitted at the emission cycle Cl is referred to as "one modulation period Pm" or simply as a "modulation period Pm." The control unit 3 controls the light emitting operation of the light emitting unit 2 so that the irradiation light Li is emitted only for a predetermined light emitting period in each modulation period Pm. Here, in the indirect ToF method, the light emission cycle Cl is set to a relatively high speed, for example, from several tens of MHz (megahertz) to several hundreds of MHz.

[0025] The sensor unit 1 receives the reflected light Lr and outputs distance measurement information by the indirect ToF method based on the phase difference between the reflected light Lr and the irradiated light Li. As will be described later, the sensor unit 1 in this example has a pixel array unit 11 in which multiple pixels Px are arranged two-dimensionally, each pixel Px comprising a photoelectric conversion element (in this example, a photodiode PD) and a first transfer transistor (e.g., transfer transistor TG1) and a second transfer transistor (e.g., transfer transistor TG2) for transferring the accumulated charge of the photoelectric conversion element, and distance measurement information is obtained for each pixel Px using the indirect ToF method. Hereinafter, information representing distance measurement information (distance information) for each pixel Px will be referred to as a "distance image."

[0026] As is well known, in the indirect ToF method, signal charges accumulated in a photoelectric conversion element in a pixel Px are distributed to two floating diffusions (FD: floating diffusion regions) by a first transfer transistor and a second transfer transistor that are alternately turned on. At this time, the cycle in which the first transfer transistor and the second transfer transistor are alternately turned on is the same as the light emission cycle Cl of the light-emitting unit 2. In other words, the first transfer transistor and the second transfer transistor are each turned on once every modulation period Pm, and the distribution of signal charges to the two floating diffusions as described above is repeated every modulation period Pm. In this example, the first transfer transistor (transfer transistor TG1) is turned on during the emission period of the irradiated light Li in the modulation period Pm, and the second transfer transistor (transfer transistor TG2) is turned on during the non-emission period of the irradiated light Li in the modulation period Pm.

[0027] As mentioned above, the light emission cycle Cl is relatively fast, and therefore the amount of signal charge accumulated in each floating diffusion by one allocation using the first and second transfer transistors as described above is relatively small. For this reason, in the indirect ToF method, the emission of the illumination light Li is repeated several thousand to several tens of thousands of times per distance measurement (i.e., per acquisition of one distance image), and the sensor unit 1 repeatedly allocates the signal charge to each floating diffusion using the first and second transfer transistors as described above while the illumination light Li is repeatedly emitted in this manner.

[0028] As can be understood from the above description, in the sensor unit 1, the first transfer transistor and the second transfer transistor for each pixel Px are driven at timing synchronized with the light emission cycle of the irradiation light Li. To achieve this synchronization, the control unit 3 controls the light receiving operation by the sensor unit 1 and the light emitting operation by the light emitting unit 2 based on a common clock CLK.

[0029] The distance image processing unit 4 receives the distance image obtained by the sensor unit 1 , performs predetermined signal processing such as compression encoding, and outputs the processed image to the memory 5 . Memory 5 is a storage device such as a flash memory, SSD (Solid State Drive), or HDD (Hard Disk Drive), and stores the distance image processed by distance image processor 4.

[0030] (1-2. Circuit configuration of the sensor unit) FIG. 2 is a block diagram showing an example of the internal circuit configuration of the sensor unit 1. As shown in the figure, the sensor unit 1 includes a pixel array unit 11, a transfer gate driver unit 12, a vertical driver unit 13, a system controller unit 14, a column processor unit 15, a horizontal driver unit 16, a signal processor unit 17, and a data storage unit 18.

[0031] The pixel array unit 11 has a configuration in which a plurality of pixels Px are two-dimensionally arranged in a matrix in the row and column directions. Each pixel Px has a photodiode PD (described later) as a photoelectric conversion element. Details of the circuit configuration of the pixel Px will be described later with reference to FIG. 3. Here, the row direction refers to the horizontal arrangement direction of the pixels Px, and the column direction refers to the vertical arrangement direction of the pixels Px. In the drawing, the row direction is the horizontal direction and the column direction is the vertical direction. In the following, the row direction may be referred to as the "X direction," the column direction as the "Y direction," and the direction perpendicular to the XY plane (i.e., the thickness direction of the sensor unit 1) as the "Z direction."

[0032] In the pixel array unit 11, a row drive line 20 is wired in the row direction for each pixel row in the matrix-like pixel arrangement, and two gate drive lines 21 and two vertical signal lines 22 are wired in the column direction for each pixel column. For example, the row drive line 20 transmits a drive signal for driving the pixel Px when reading out a signal. Note that although FIG. 2 shows the row drive line 20 as a single line, the number of lines is not limited to one. One end of the row drive line 20 is connected to an output terminal of the vertical drive unit 13 corresponding to each row.

[0033] The system control unit 14 is composed of a timing generator that generates various timing signals, and controls the driving of the transfer gate driving unit 12, vertical driving unit 13, column processing unit 15, horizontal driving unit 16, etc. based on the various timing signals generated by the timing generator.

[0034] The transfer gate driving unit 12 drives the two transfer transistors provided for each pixel Px through the gate driving lines 21, two of which are provided for each pixel column as described above, under the control of the system control unit 14. As described above, the two transfer transistors are alternately turned on for each modulation period Pm. To this end, the system control unit 14 supplies the clock CLK input from the control unit 3 shown in Fig. 1 to the transfer gate driving unit 12, and the transfer gate driving unit 12 drives the two transfer transistors based on this clock CLK.

[0035] The vertical drive unit 13 is configured with a shift register, an address decoder, etc., and drives the pixels Px of the pixel array unit 11 simultaneously for all pixels or in row units, etc. In other words, the vertical drive unit 13, together with the system control unit 14 that controls the vertical drive unit 13, configures a drive control unit that controls the operation of each pixel Px of the pixel array unit 11.

[0036] The detection signals output (read) from each pixel Px in the pixel row in response to drive control by the vertical drive unit 13, specifically, signals corresponding to the signal charges accumulated in each of the two floating diffusions provided for each pixel Px, are input to the column processing unit 15 through the corresponding vertical signal line 22. The column processing unit 15 performs predetermined signal processing on the detection signals read from each pixel Px through the vertical signal line 22, and temporarily stores the processed detection signals. Specifically, the column processing unit 15 performs signal processing such as noise removal and A / D (Analog to Digital) conversion.

[0037] Here, the reading of two detection signals from each pixel Px (detection signals for each floating diffusion) is performed once for a predetermined number of repeated emissions of the irradiation light Li (for every several thousand to tens of thousands of repeated emissions as mentioned above). Therefore, the system control unit 14 controls the vertical drive unit 13 based on the clock CLK so that the timing for reading out the detection signal from each pixel Px coincides with the timing for each predetermined number of repeated emissions of the illumination light Li.

[0038] The horizontal driving unit 16 is configured with a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns in the column processing unit 15. Through selective scanning by this horizontal driving unit 16, detection signals that have been signal-processed for each unit circuit in the column processing unit 15 are sequentially output.

[0039] The signal processing unit 17 has at least an arithmetic processing function, and performs various signal processing such as distance calculation processing corresponding to the indirect ToF method based on the detection signals output from the column processing unit 15. Note that a known method can be used to calculate distance information by the indirect ToF method based on two types of detection signals (detection signals for each floating diffusion) for each pixel Px, and a description thereof will be omitted here.

[0040] The data storage unit 18 temporarily stores data necessary for signal processing in the signal processing unit 17 .

[0041] The sensor unit 1 configured as described above outputs a distance image that indicates the distance to an object Ob for each pixel Px. A distance measuring device 10 having such a sensor unit 1 can be applied to, for example, an in-vehicle system that is mounted on a vehicle and measures the distance to an object Ob outside the vehicle, or a gesture recognition device that measures the distance to an object such as a user's hand and recognizes the user's gesture based on the measurement result.

[0042] (1-3. Pixel circuit configuration) FIG. 3 shows an equivalent circuit of the pixels Px arranged two-dimensionally in the pixel array section 11. Each pixel Px has one photodiode PD as a photoelectric conversion element and one charge discharging transistor OFG, and also has two transfer transistors TG as transfer gate elements, two floating diffusions FD, two reset transistors RST, two switching transistors FDG, two additional capacitances FDL, two amplification transistors AMP, and two selection transistors SEL.

[0043] Here, when distinguishing between the transfer transistors TG, floating diffusions FD, reset transistors RST, switching transistors FDG, additional capacitances FDL, amplification transistors AMP, and selection transistors SEL, which are provided in pairs in each pixel Px, they will be referred to as transfer transistors TG1 and TG2, floating diffusions FD1 and FD2, switching transistors FDG1 and FDG2, additional capacitances FDL1 and FDL2, reset transistors RST1 and RST2, amplification transistors AMP1 and AMP2, and selection transistors SEL1 and SEL2, as shown in Figure 3. The charge discharging transistor OFG, the transfer transistor TG, the reset transistor RST, the switching transistor FDG, the amplification transistor AMP, and the selection transistor SEL are configured by, for example, N-type MOS transistors.

[0044] The charge discharging transistor OFG is turned on when a charge discharging signal SOFG supplied to its gate is turned on. When the charge discharging transistor OFG is turned on, the photodiode PD is clamped to a predetermined reference potential VDD and the accumulated charge is reset. The charge discharging signal SOFG is supplied from the vertical driving unit 13, for example.

[0045] When a transfer drive signal STG1 supplied to its gate is turned on, the transfer transistor TG1 becomes conductive and transfers the signal charge accumulated in the photodiode PD to the floating diffusion FD1. When a transfer drive signal STG2 supplied to its gate is turned on, the transfer transistor TG2 becomes conductive and transfers the charge accumulated in the photodiode PD to the floating diffusion FD2. The transfer drive signals STG1 and STG2 are supplied from the transfer gate driver 12 via gate drive lines 21-1 and 21-2, which are provided as one of the gate drive lines 21 shown in FIG.

[0046] The floating diffusions FD1 and FD2 are charge holding portions that temporarily hold the charges transferred from the photodiode PD.

[0047] When an FD drive signal SFDG1 supplied to its gate electrode is turned on, the switching transistor FDG1 becomes conductive in response, thereby connecting the additional capacitance FDL1 to the floating diffusion FD1. When an FD drive signal SFDG2 supplied to its gate electrode is turned on, the switching transistor FDG2 becomes conductive in response, thereby connecting the additional capacitance FDL2 to the floating diffusion FD2. In this example, the additional capacitances FDL1 and FDL2 are formed by a capacitance generating section 52 shown in FIG. 5, which will be described later.

[0048] When the reset signal SRST supplied to the gate of the reset transistor RST1 is turned on, the reset transistor RST1 becomes conductive and resets the potential of the floating diffusion FD1 to the reference potential VDD. Similarly, when the reset signal SRST supplied to the gate of the reset transistor RST2 is turned on, the reset transistor RST2 becomes conductive and resets the potential of the floating diffusion FD2 to the reference potential VDD. When the reset transistors RST1 and RST2 are turned on, the switching transistors FDG1 and FDG2 are also turned on at the same time, and the additional capacitances FDL1 and FDL2 are also reset. The reset signal SRST is supplied from the vertical drive unit 13, for example.

[0049] Here, for example, when the illuminance is high and the amount of incident light is large, the vertical drive unit 13 turns on the switching transistors FDG1 and FDG2 to connect the floating diffusion FD1 to the additional capacitance FDL1 and also connect the floating diffusion FD2 to the additional capacitance FDL2, thereby allowing more charge transferred from the photodiode PD to be stored under high illuminance conditions. On the other hand, when the illuminance is low and the amount of incident light is small, the vertical drive unit 13 turns off the switching transistors FDG1 and FDG2 to disconnect the additional capacitances FDL1 and FDL2 from the floating diffusions FD1 and FD2, respectively, thereby increasing the conversion efficiency.

[0050] In addition, in pixel Px, the additional capacitances FDL1 and FDL2 and the switching transistors FDG1 and FDG2 that control their connection may be omitted, but by providing an additional capacitance FDL and using it depending on the amount of incident light, a high dynamic range can be achieved.

[0051] The amplifier transistor AMP1 has a source connected to the vertical signal line 22-1 via the selection transistor SEL1 and a drain connected to the reference potential VDD (constant current source) to form a source follower circuit. The amplifier transistor AMP2 has a source connected to the vertical signal line 22-2 via the selection transistor SEL2 and a drain connected to the reference potential VDD (constant current source) to form a source follower circuit. Here, the vertical signal lines 22-1 and 22-2 are each provided as one of the vertical signal lines 22 shown in FIG.

[0052] The selection transistor SEL1 is connected between the source of the amplification transistor AMP1 and the vertical signal line 22-1, and when the selection signal SSEL supplied to the gate is turned on, the selection transistor SEL1 becomes conductive and outputs the charge held in the floating diffusion FD1 to the vertical signal line 22-1 via the amplification transistor AMP1. The selection transistor SEL2 is connected between the source of the amplification transistor AMP2 and the vertical signal line 22-2, and when the selection signal SSEL supplied to the gate is turned on, it becomes conductive and outputs the charge held in the floating diffusion FD2 to the vertical signal line 22-2 via the amplification transistor AMP1. The selection signal SSEL is supplied from the vertical drive unit 13 via the row drive line 20.

[0053] The operation of the pixel Px will now be briefly described. First, before light reception begins, a reset operation is performed on all pixels Px to reset the charges in the pixels Px. That is, for example, the charge discharge transistor OFG, each reset transistor RST, each switching transistor FDG, and each transfer transistor TG are turned on (conductive state), and the accumulated charges in the photodiode PD, each floating diffusion FD, and each additional capacitance FDL are reset.

[0054] After the accumulated charge is reset, the light receiving operation for distance measurement is started in all pixels. The light receiving operation here means the light receiving operation performed for one distance measurement. In other words, during the light receiving operation, the operation of alternately turning on the transfer transistors TG1 and TG2 is repeated a predetermined number of times (several thousand to several tens of thousands of times in this example). Hereinafter, the period of the light receiving operation performed for one distance measurement will be referred to as the "light receiving period Pr."

[0055] During the light-receiving period Pr, within one modulation period Pm of the light-emitting unit 2, for example, the period during which the transfer transistor TG1 is on (i.e., the period during which the transfer transistor TG2 is off) continues for the light-emitting period of the irradiated light Li, and then the transfer transistor TG2 is on (i.e., the period during which the transfer transistor TG1 is off) for the remaining period, i.e., the non-emitting period of the irradiated light Li. That is, during the light-receiving period Pr, the operation of distributing the charge of the photodiode PD to the floating diffusions FD1 and FD2 is repeated a predetermined number of times within one modulation period Pm.

[0056] Then, when the light-receiving period Pr ends, each pixel Px of the pixel array unit 11 is selected line-sequentially. In the selected pixel Px, the selection transistors SEL1 and SEL2 are turned on. As a result, the charge accumulated in the floating diffusion FD1 is output to the column processing unit 15 via the vertical signal line 22-1. Also, the charge accumulated in the floating diffusion FD2 is output to the column processing unit 15 via the vertical signal line 22-2.

[0057] This completes one light receiving operation, and the next light receiving operation begins with a reset operation.

[0058] Here, the reflected light received by pixel Px is delayed according to the distance to object Ob from the timing when illumination light Li is emitted by light-emitting unit 2. The distribution ratio of the charges accumulated in the two floating diffusions FD1 and FD2 changes depending on the delay time according to the distance to object Ob, and therefore the distance to object Ob can be calculated from the distribution ratio of the charges accumulated in these two floating diffusions FD1 and FD2.

[0059] (1-4. Example of pixel structure) FIG. 4 is a plan view for explaining the schematic structure of the pixel Px. 4 corresponds to the row direction (X direction) in FIG. 1, and the vertical direction corresponds to the column direction (Y direction) in FIG.

[0060] The pixel Px has a rectangular shape in plan view as shown in FIG. The photodiode PD is disposed approximately in the center of the pixel Px in a semiconductor substrate (a semiconductor substrate 31 described later). The photodiode PD is formed of an N-type semiconductor region 42. In plan view, a P-type semiconductor region 41 is formed around the photodiode PD as the N-type semiconductor region 42.

[0061] Outside the photodiode PD, along a predetermined one of the four sides of the pixel Px, the transfer transistor TG1, the switching transistor FDG1, the reset transistor RST1, the amplification transistor AMP1, and the selection transistor SEL1 are arranged in a linear line, and along another one of the four sides of the pixel Px, the transfer transistor TG2, the switching transistor FDG2, the reset transistor RST2, the amplification transistor AMP2, and the selection transistor SEL2 are arranged in a linear line.

[0062] Furthermore, a charge discharging transistor OFG is disposed near a side other than the two sides of the pixel Px on which the transfer transistor TG, the switching transistor FDG, the reset transistor RST, the amplifying transistor AMP, and the selection transistor SEL are formed.

[0063] The arrangement of the components of the pixel Px shown in FIG. 4 is not limited to this example, and other arrangements are also possible.

[0064] FIG. 5 is a cross-sectional view for explaining the schematic structure of the pixel Px. First, as a premise, the sensor unit 1 of this example is configured as a so-called back-illuminated sensor device that receives incident light from the back surface Sb side (upper side in the figure) of the semiconductor substrate 31 on which the photodiode PD is formed in pixel units. The sensor unit 1 includes a semiconductor substrate 31 and a wiring layer unit 32 formed on the surface Ss side of the semiconductor substrate 31.

[0065] The semiconductor substrate 31 is made of, for example, silicon (Si) and is formed to have a thickness of, for example, about 1 μm to 6 μm. In the semiconductor substrate 31, for example, an N-type (second conductivity type) semiconductor region 42 is formed in a P-type (first conductivity type) semiconductor region 41 in a pixel unit, thereby forming a photodiode PD in a pixel unit. The P-type semiconductor regions 41 provided on both the front and back sides of the semiconductor substrate 31 also serve as hole charge accumulation regions for suppressing dark current.

[0066] 5, the back surface Sb of the semiconductor substrate 31 is a light incident surface onto which light is incident. An anti-reflection film 33 is formed on the back surface Sb of the semiconductor substrate 31. The anti-reflection film 33 has a laminated structure in which, for example, a fixed charge film and an oxide film are laminated, and for example, a high-dielectric-constant (High-k) insulating thin film formed by ALD (Atomic Layer Deposition) can be used. Specifically, hafnium oxide (HfO2), aluminum oxide (Al2O3), titanium oxide (TiO2), STO (Strontium Titan Oxide), etc. can be used. In the example of FIG. 5, the anti-reflection film 33 is configured by laminating a hafnium oxide film 43, an aluminum oxide film 44, and a silicon oxide film 45.

[0067] An inter-pixel light-shielding film 35 that prevents incident light from entering an adjacent pixel is formed on the anti-reflection film 33 at a boundary 34 between adjacent pixels Px (hereinafter also referred to as a "pixel boundary 34") The inter-pixel light-shielding film 35 is formed in a lattice pattern so as to open the photodiode PD of each pixel Px. The material of the inter-pixel light-shielding film 35 may be any material that blocks light, and may be, for example, a metal material such as tungsten (W), aluminum (Al), or copper (Cu). The inter-pixel light-shielding film 35 prevents light that should be incident only on one pixel Px from leaking into the other pixel Px between adjacent pixels Px.

[0068] The planarization film 36 is formed on the inter-pixel light-shielding film 35 and on portions of the anti-reflection film 33 where the inter-pixel light-shielding film 35 is not formed, thereby flattening the surface on the back surface Sb side of the semiconductor substrate 31. The planarization film 36 can be formed from, for example, an insulating film such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON), or an organic material such as a resin.

[0069] An on-chip lens (microlens) 37 is formed for each pixel on the upper surface of the planarization film 36. The on-chip lens 37 is made of a resin material such as a styrene-based resin, an acrylic-based resin, a styrene-acrylic copolymer resin, or a siloxane-based resin. Light collected by the on-chip lens 37 is efficiently incident on the photodiode PD.

[0070] Furthermore, in the pixel boundary portion 34 on the back surface Sb side of the semiconductor substrate 31, an inter-pixel isolation portion 40 is formed extending from the back surface Sb side of the semiconductor substrate 31 to a predetermined depth in the substrate thickness direction, electrically isolating adjacent pixels Px. The outer periphery of the inter-pixel isolation portion 40, including its bottom surface and sidewalls, is covered with a hafnium oxide film 43, which is part of the anti-reflection film 33. The inter-pixel isolation portion 40 has the function of electrically isolating the pixels Px so as to prevent leakage of signal charges between the pixels Px.

[0071] Here, the inter-pixel isolation 40 can be formed by filling an insulating material (in this example, a silicon oxide film 45) in a trench (groove) formed in the semiconductor substrate 31 so as to surround the formation region of the photodiode PD (so-called trench isolation). Specifically, the inter-pixel isolation 40 can be configured as, for example, reversed deep trench isolation (RDTI), reversed full trench isolation (RFTI), front deep trench isolation (FDTI), front full trench isolation (FFTI), or the like. Here, "front" and "reversed" refer to whether cutting to form the trench is performed from the front surface Ss side or the back surface Sb side of the semiconductor substrate 31. Additionally, "deep" and "full" refer to the depth of the trench (groove depth), with "full" meaning that the trench penetrates the semiconductor substrate 31, and "deep" meaning that the trench is formed deep enough not to penetrate the semiconductor substrate 31. FIG. 5 illustrates a structure corresponding to RDTI or RFTI in which a trench is formed from the rear surface Sb side.

[0072] When forming a trench in the semiconductor substrate 31, the width of the trench tends to gradually narrow as it moves in the cutting direction. Therefore, when forming a trench from the front surface Ss side, as in FDTI or FFTI, the inter-pixel isolation portion 40 has a characteristic that its width is narrower on the back surface Sb side than on the front surface Ss side. Conversely, when forming a trench from the back surface Sb side, as in RDTI or RFTI, the inter-pixel isolation portion 40 has a characteristic that its width is narrower on the front surface Ss side than on the back surface Sb side.

[0073] Two transfer transistors TG1 and TG2 are formed for one photodiode PD formed in each pixel Px on the surface Ss of the semiconductor substrate 31 on which the wiring layer portion 32 is formed. Furthermore, on the surface Ss side of the semiconductor substrate 31, floating diffusions FD1 and FD2 are formed of high-concentration N-type semiconductor regions (N-type diffusion regions) as charge storage portions that temporarily store the charges transferred from the photodiode PD.

[0074] The wiring layer section 32 is composed of a plurality of wiring layers 32a and interlayer insulating films 32b therebetween. Fig. 5 shows an example in which the wiring layer section 32 has four wiring layers 32a: a first wiring layer 32a-1, a second wiring layer 32a-2, a third wiring layer 32a-3, and a fourth wiring layer 32a-4. In the wiring layer section 32, the wiring layer 32a closest to the surface Ss of the semiconductor substrate 31 is the first wiring layer 32a-1. In this first wiring layer 32a-1 (i.e., the layer in contact with the surface Ss of the semiconductor substrate 31), electrodes of each pixel transistor (such as the reset transistor RST and select transistor SEL) including the transfer transistors TG1 and TG2 described above are formed. In this sense, the first wiring layer 32a-1 can be said to be an electrode formation layer for the pixel transistors. The second wiring layer 32a-2 is a wiring layer 32a stacked on the first wiring layer 32a-1 via an interlayer insulating film 32b, the third wiring layer 32a-3 is a wiring layer 32a stacked on the second wiring layer 32a-2 via an interlayer insulating film 32b, and the fourth wiring layer 32a-4 is a wiring layer 32a stacked on the third wiring layer 32a-3 via an interlayer insulating film 32b.

[0075] In the wiring layer section 32, the electrodes (gate electrodes) of the transfer transistors TG formed in the first wiring layer 32a-1 are connected to inter-pixel wiring (not shown in FIG. 5) for gate driving formed in the fourth wiring layer 32a-4 via gate wiring 50 extending in the thickness direction (Z direction). This inter-pixel wiring corresponds to the gate driving lines 21 (21-1, 21-2) shown in FIGS. 2 and 3, and in this example, is formed in the fourth wiring layer 32a-4, which is farthest from the semiconductor substrate 31. As described above, each transfer transistor TG is driven based on a transfer drive signal STG supplied via an inter-pixel wiring serving as a gate drive line 21.

[0076] In this example, the gate wiring 50 is formed by wirings formed in the second wiring layer 32a-2 and the third wiring layer 32a-3, and vias connecting the wiring layers 32a. In the gate wiring 50, the wirings formed in the second wiring layer 32a-2 and the third wiring layer 32a-3 are wirings that extend in an in-plane direction inside a shield part 60, which will be described later. For clarity, the in-plane direction here means an in-plane direction that is perpendicular to the thickness direction.

[0077] In addition, in the wiring layer portion 32, the second wiring layer 32a-2 has metal wiring such as copper or aluminum formed as a light-shielding / reflecting member 51 in a region located below the formation region of the photodiode PD, in other words, in a region that at least partially overlaps with the formation region of the photodiode PD in a planar view. This light-shielding / reflecting member 51 blocks light that enters the semiconductor substrate 31 from the light incident surface via the on-chip lens 37 and passes through the semiconductor substrate 31 without being photoelectrically converted within the semiconductor substrate 31, preventing the light from passing through to the third wiring layer 32a-3 or the fourth wiring layer 32a-4 below. This light-shielding function prevents light (infrared light in this example) that passes through the semiconductor substrate 31 without being photoelectrically converted within the semiconductor substrate 31 from being scattered by the wiring layer 32a below the second wiring layer 32a-2 and entering nearby pixels. This makes it possible to prevent nearby pixels from erroneously detecting light.

[0078] The light-shielding / reflecting member 51 also has the function of reflecting light that has entered the semiconductor substrate 31 from the light incident surface via the on-chip lens 37 and that has passed through the semiconductor substrate 31 without being photoelectrically converted within the semiconductor substrate 31, thereby allowing the light to enter the semiconductor substrate 31 again. Therefore, the light-shielding / reflecting member 51 can also be said to function as a reflective member. This reflective function increases the amount of light that is photoelectrically converted within the semiconductor substrate 31, thereby improving the quantum efficiency (QE), that is, the sensitivity of the pixel Px to light.

[0079] The light-shielding / reflecting member 51 may be made of a metal material, or may have a reflecting or light-shielding structure made of polysilicon, an oxide film, or the like. Furthermore, the light-shielding / reflecting member 51 may not be formed by one wiring layer 32a, but may be formed by a plurality of wiring layers 32a, such as by forming the second wiring layer 32a-2 and the third wiring layer 32a-3 in a grid pattern.

[0080] A capacitance generating portion 52 is formed by, for example, patterning in a comb shape on a predetermined wiring layer 32a, specifically the third wiring layer 32a-3 in this example, of the multiple wiring layers 32a of the wiring layer portion 32. The capacitance generating portion 52 functions as the aforementioned additional capacitance FDL. The light-shielding / reflecting member 51 and the capacitance generating portion 52 may be formed in the same wiring layer 32a, but when they are formed in different wiring layers 32a, the capacitance generating portion 52 is formed in a layer farther from the semiconductor substrate 31 than the light-shielding / reflecting member 51. In other words, the light-shielding / reflecting member 51 is formed closer to the semiconductor substrate 31 than the capacitance generating portion 52.

[0081] In this example, the wiring layer 32 has a shield portion 60 formed for each gate wiring 50, and the shield portion 60 will be described later.

[0082] As described above, the sensor unit 1 of this example has a back-illuminated structure in which the semiconductor substrate 31, which is a semiconductor layer, is disposed between the on-chip lens 37 and the wiring layer unit 32, and incident light is made incident on the photodiode PD from the back surface Sb side on which the on-chip lens 37 is formed.

[0083] (1-5. About the shielding part) As mentioned above, in the indirect ToF sensor unit 1, the pair of transfer transistors TG1 and TG2 are driven at high speed, repeatedly turning on and off in a short cycle of several tens to several hundreds of MHz (for example, about 10 MHz to 200 MHz), which poses the problem of increased power consumption.

[0084] To reduce power consumption, it is effective to reduce either the gate capacitance Cg of the transfer transistor TG or the wiring capacitance Cw of the wiring connected to the gate electrode (i.e., the gate wiring 50). Specifically, when the capacitance is C (gate capacitance Cg + wiring capacitance Cw) and the drive voltage (swing width of the transfer transistor) is V, the power consumption W is expressed as follows: W=1 / 2*·(C·V) 2 It is expressed as: Therefore, the power consumption W can be reduced by reducing the wiring capacitance Cw.

[0085] In order to reduce the wiring capacitance Cw of the gate wiring 50, the sensor unit 1 of this embodiment is formed with the shield unit 60 shown in FIG.

[0086] FIG. 6 is a plan view for explaining the structure of the shield portion 60, illustrating the positional relationship between the transfer transistor TG1, the gate wiring 50, and the shield portion 60 when the wiring layer portion 32 is viewed in plan from the semiconductor substrate 31 side. Here, the shield part 60 is also formed on the transfer transistor TG2 side, but in that case too, the structure of the shield part 60 is the same, so it is not shown in the drawings.

[0087] As shown in the figure, the shield portion 60 is formed so as to surround the gate wiring 50 in a plan view. Specifically, the shield portion 60 in this example is formed in a ring shape in a plan view as shown in the figure, and surrounds the gate wiring 50. Here, being ring-shaped in a plan view can be rephrased as having a ring-shaped cross section in the in-plane direction.

[0088] In this example, the shield part 60 is made of an insulating material different from the material of the interlayer insulating film 32b. Specifically, the shield part 60 in this case is made of a low-k material (low dielectric constant material). Here, examples of low-k materials include SiOF, which is SiO2 doped with fluorine, SiOCH-based materials, which are SiO2 doped with hydrocarbons, organic polymer-based materials, and porous silica-based materials.

[0089] By providing the gate wiring 50 with the shield portion 60 as described above, it is possible to reduce the capacitive load on the gate wiring 50 from the surrounding wiring, and it is possible to reduce the wiring capacitance Cw of the gate wiring 50.

[0090] Here, the shield section 60 in this example is formed by digging a trench in the wiring layer section 32 . Specifically, the wiring layer section 32 is formed by stacking a second wiring layer 32a-2, a third wiring layer 32a-3, and a fourth wiring layer 32a-4 with an interlayer insulating film 32b interposed between the layers on the surface Ss of the semiconductor substrate 31 on which the electrodes of the pixel transistors are formed, and the shield section 60 is formed by digging a trench from the predetermined wiring layer 32a toward the semiconductor substrate 31 at the stage when a predetermined wiring layer 32a is stacked during the process of forming the wiring layer section 32. At this time, the trench is formed by, for example, dry etching or the like. The formed trench is filled with an insulating material (low-k material in this example) as a shielding material, thereby forming the shield portion 60.

[0091] In this example, the shield part 60 is formed across multiple wiring layers 32a. Specifically, the shield part 60 in this case is formed across from the third wiring layer 32a-3 to the first wiring layer 32a-1. By forming the shield portion 60 across multiple wiring layers 32a in this manner, the area over which the shield portion 60 covers the gate wiring 50 in the stacking direction of the wiring layer portion 32 is increased, thereby enhancing the effect of reducing the wiring capacitance of the gate wiring.

[0092] As mentioned above, in this example, the gate driving line 21 (inter-pixel wiring) to which the gate wiring 50 is connected is formed in the fourth wiring layer 32a-4 (furthest wiring layer) which is the farthest from the semiconductor substrate 31.

[0093] Fig. 7 is a cross-sectional view of a pixel Px for explaining the gate drive line 21 as an inter-pixel wiring. Note that the cross-sectional view of Fig. 7 shows a cross-section of the pixel Px taken in a direction different from that of the cross-sectional view of Fig. 5. Here, the relationship between the transfer transistor TG1, its gate wiring 50, and the gate drive line 21-1 is illustrated, but the relationship between the transfer transistor TG2, its gate wiring 50, and the gate drive line 21-2 is similar to that shown in this figure, and therefore is not shown.

[0094] When the gate driving line 21-1 serving as an inter-pixel wiring is formed in the fourth wiring layer 32a-4, it is not possible to dig a trench from the fourth wiring layer 32a-4 to form the shield section 60. If a trench were to be formed from the fourth wiring layer 32a-4, the gate wiring 50 and the gate driving line 21-1 would be blocked by the shield section 60 in the fourth wiring layer 32a-4, making it impossible to electrically connect them.

[0095] Therefore, in this example, in which the shield portion 60 is formed by digging a trench from the third wiring layer 32a-3 adjacent to the fourth wiring layer 32a-4, it is possible to maximize the area over which the shield portion 60 covers the gate wiring 50 in the stacking direction of the wiring layer portion 32, thereby enhancing the effect of reducing the wiring capacitance Cw.

[0096] 2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, instead of the gate wiring 50, a gate wiring 50A using a through via is provided.

[0097] FIG. 8 is a cross-sectional view for explaining a schematic structure of a pixel PxA according to the second embodiment. In the following description, parts that are similar to parts that have already been described will be given the same reference numerals and description thereof will be omitted.

[0098] As shown in the figure, in the pixel PxA of the second embodiment, a gate wiring 50A formed by a through via that penetrates between the first wiring layer 32a-1 and the fourth wiring layer 32a-4 is provided as the gate wiring of each of the transfer transistors TG1 and TG2.

[0099] By forming the gate wiring 50A using such through vias, it is no longer necessary to form wiring in the in-plane direction as in the gate wiring 50 in the first embodiment, and therefore it is possible to form the gate wiring thin. Therefore, the effect of reducing the wiring capacitance of the gate wiring can be enhanced.

[0100] Here, in the first embodiment, the gate wiring 50 is formed by wiring in the in-plane direction in the second wiring layer 32a-2 and the third wiring layer 32a-3. Therefore, when forming the gate wiring in the region inside the shield section 60 in the process of forming the wiring layer section 32, it is possible to apply the same process as the wiring formation process in the region outside the shield section 60, in which (dummy) wiring is formed in each wiring layer 32a of the second wiring layer 32a-2 and the third wiring layer 32a-3 and then one layer of vias is formed. This has the advantage of improving the manufacturing efficiency of the sensor device when reducing the wiring capacitance of the gate wiring.

[0101] Fig. 9 is a cross-sectional view of pixel PxA for explaining the gate drive line 21 serving as an inter-pixel wiring. Similar to the relationship between Fig. 5 and Fig. 7, the cross-sectional view of Fig. 9 shows a cross-section of pixel PxA taken in a direction different from that of the cross-sectional view of Fig. 8. As illustrated in FIG. 9, the gate wiring 50A using a through via may have a configuration in which the gate electrode of the transfer transistor TG is directly connected to the gate drive line 21 formed in the fourth wiring layer 32a-4.

[0102] <3. Modifications> Here, the embodiment is not limited to the specific example given above, and various modified configurations can be adopted. For example, as shown in the cross-sectional view of pixel PxB in FIG. 10, a configuration can be adopted in which a shield portion 60B is provided as a hollow portion (that is, filled with a gas such as air). This makes it possible to eliminate the need for a step of filling the trench with an insulating material when forming the shielding portion by digging a trench in the wiring layer portion 32 .

[0103] Alternatively, a configuration may be adopted in which a shield section 60C is provided that has a layer of insulating material such as a low-k material and a layer of gas such as air, as shown in the cross-sectional view of pixel PxC in Fig. 11. Specifically, the example shown in Fig. 11 illustrates a configuration in which the outer edge of shield section 60C is a layer of low-k material and the inner part is an air layer.

[0104] Furthermore, in the explanation so far, an example has been given in which the shield portion 60 is formed in a ring shape, but the shape of the shield portion 60, specifically, the cross-sectional shape in the in-plane direction, can also be other shapes such as a square shape as exemplified in FIG. 12, a polygonal shape as exemplified in FIG. 13, or a grid shape as exemplified in FIG. 14. Among these examples, when a rectangular or grid-like shape is used, gas can easily enter the corners and intersections during dry etching during trench formation, allowing the trench to be dug deeper at these corners and intersections. The deeper trenches can improve the shielding effect (the effect of reducing the capacitive load from other wiring), and can further reduce the wiring capacitance Cw.

[0105] Here, when the shield portion 60 is formed in a ring shape as in the example of Figure 6, there is an advantage in that it is easier to make the depth of the shield portion 60 uniform when the shield portion 60 is formed by digging a trench in the wiring layer portion 32.

[0106] The shield part 60B and 60C are not limited to an annular shape.

[0107] In addition, in the explanation so far, a configuration has been exemplified in which the charge of the photodiode PD is transferred to the floating diffusion FD via the transfer transistor TG, but as a configuration corresponding to global readout, for example, a configuration can be adopted in which the charge of the photodiode PD is transferred to a memory element via the transfer transistor TG, and then the charge accumulated in the memory element is transferred to the floating diffusion FD via a separate transfer transistor. In this case, the memory element can be said to be a charge holding unit that holds the charge accumulated in the photoelectric conversion element.

[0108] In addition, in the explanation so far, an example has been given in which the sensor unit 1 performs sensing for distance measurement using an indirect ToF method, but the present technology can be widely and suitably applied to a sensor device having a pixel having a photoelectric conversion element that performs photoelectric conversion, a first charge holding unit that holds the charge accumulated in the photoelectric conversion element, a second charge holding unit, a first transfer transistor that transfers the charge to the first charge holding unit, and a second transfer transistor that transfers the charge to the second charge holding unit.

[0109] <4. Summary of embodiments> As described above, the sensor device (sensor unit 1) as an embodiment comprises a semiconductor substrate (same as 31) and a wiring layer unit (same as 32) formed on the semiconductor substrate and having multiple wiring layers, and pixels (Px, PxA, PxB, PxC) each having a photoelectric conversion element (photodiode PD) that performs photoelectric conversion, a first charge holding unit that holds charges accumulated in the photoelectric conversion element, a second charge holding unit (e.g., floating diffusions FD1 and FD2), a first transfer transistor (e.g., transfer transistor TG1) that transfers charges to the first charge holding unit, and a second transfer transistor (e.g., transfer transistor TG2) that transfers charges to the second charge holding unit are formed in a stacked structure made of the semiconductor substrate and the wiring layer unit, and shield units (60, 60B, 60C) are formed to surround each of the gate wirings (50, 50A) of the first and second transfer transistors that extend in the thickness direction in the wiring layer unit. The shielding portion makes it possible to reduce the capacitive load on the gate wiring from the surrounding wiring. Therefore, the wiring capacitance of the gate wiring can be reduced, and the power consumption of the sensor device can be reduced.

[0110] In the sensor device according to the embodiment, the shield portion is formed across a plurality of wiring layers. This increases the area in which the shield portion covers the gate wiring in the stacking direction of the wiring layer portion. Therefore, the effect of reducing the wiring capacitance of the gate wiring can be enhanced.

[0111] Furthermore, in the sensor device according to the embodiment, the gate wiring (50) has wiring that extends in the in-plane direction inside the shield portion. This makes it possible to apply the same process for forming gate wiring in the area inside the shield part as for the wiring formation process in the area outside the shield part, which is to form (dummy) wiring in each wiring layer and then form one layer's worth of vias. Therefore, the manufacturing efficiency of the sensor device can be improved when the wiring capacitance of the gate wiring is reduced.

[0112] Furthermore, in the sensor device according to the embodiment, the gate wiring (50A) is formed by a through via that penetrates a plurality of wiring layers. By using a through via, it becomes unnecessary to form wiring in the in-plane direction in the gate wiring, and therefore it becomes possible to form the gate wiring thin. Therefore, the effect of reducing the wiring capacitance of the gate wiring can be enhanced.

[0113] In addition, in the sensor device according to the embodiment, the inter-pixel wiring (gate driving line 21) to which the gate wiring is connected is formed in the farthest wiring layer (e.g., the fourth wiring layer 32a-4), which is the wiring layer farthest from the semiconductor substrate in the wiring layer section, and the shield section extends from an adjacent layer (e.g., the third wiring layer 32a-3) of the farthest wiring layer in the wiring layer section toward the semiconductor substrate side. This makes it possible to maximize the area in which the shield portion covers the gate wiring in the stacking direction of the wiring layer portion when the shield portion is formed by digging a trench in the wiring layer portion. Therefore, the effect of reducing the wiring capacitance of the gate wiring can be enhanced.

[0114] Furthermore, in the sensor device according to the embodiment, the shield portion has an annular cross section in the in-plane direction (see FIG. 6). This makes it easier to make the depth of the shield portion uniform when the shield portion is formed by digging a trench in the wiring layer portion. Therefore, the accuracy of forming the shielding portion can be improved.

[0115] Furthermore, in the sensor device according to the embodiment, the shield portion is formed of an insulating material different from the interlayer insulating material in the wiring layer portion. This allows the shield portion to be made of a material that has higher insulating properties than the interlayer insulating material. Therefore, the effect of reducing the wiring capacitance of the gate wiring can be enhanced, and power consumption can be further reduced.

[0116] In the sensor device according to the embodiment, the shielding portion is made of a low-k material. This improves the insulating properties of the shielding portion. Therefore, the effect of reducing the wiring capacitance of the gate wiring can be enhanced, and power consumption can be further reduced.

[0117] Furthermore, in the sensor device according to the embodiment, the shield portion (60B) is a hollow portion (see FIG. 10). This makes it possible to eliminate the need for a step of filling the trench with an insulating material when forming the shielding portion by digging a trench in the wiring layer portion. Therefore, the manufacturing efficiency of the sensor device can be improved when the wiring capacitance of the gate wiring is reduced.

[0118] Furthermore, the sensor device according to the embodiment is a sensor device for distance measurement using an indirect ToF method. In indirect ToF, the first and second transfer transistors are driven at high speed, which tends to increase power consumption. Therefore, it is preferable to apply the technology of the embodiment.

[0119] Further, a sensing module (same as the sixth embodiment) includes a light emitting unit (same as the second embodiment) that emits light for distance measurement, and a sensor unit (same as the first embodiment) that receives light emitted from the light emitting unit and reflected by an object. The sensor unit includes a semiconductor substrate (same as the first embodiment) and a wiring layer unit (same as the second embodiment) that is formed on the semiconductor substrate and has a plurality of wiring layers. The sensor unit includes a photoelectric conversion element (photodiode PD) that performs photoelectric conversion, a first charge holding unit and a second charge holding unit (for example, floating diffusions FD1 and FD2) that hold charges accumulated in the photoelectric conversion element, and a charge Pixels (Px, PxA, PxB, PxC) each having a first transfer transistor (e.g., transfer transistor TG1) that transfers the charge to a first charge holding section and a second transfer transistor (e.g., transfer transistor TG2) that transfers the charge to a second charge holding section are formed in a stacked structure made of a semiconductor substrate and a wiring layer section, and shield sections (60, 60B, 60C) are formed to surround each of the gate wirings (50, 50A) of the first and second transfer transistors that extend in the thickness direction in the wiring layer section. The sensing module according to this embodiment also provides the same functions and effects as the sensor device according to the above-described embodiment.

[0120] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0121] <5. This technology> The present technology can also be configured as follows. (1) a semiconductor substrate; and a wiring layer section formed on the semiconductor substrate and having a plurality of wiring layers; a photoelectric conversion element that performs photoelectric conversion; a first charge holding unit and a second charge holding unit that hold charges accumulated in the photoelectric conversion element; a first transfer transistor that transfers the charges to the first charge holding unit; a pixel including a second transfer transistor that transfers the charge to the second charge holding unit is formed in a stacked structure of the semiconductor substrate and the wiring layer unit, A shield portion is formed to surround each of the gate wirings of the first and second transfer transistors extending in the thickness direction in the wiring layer portion. Sensor device. (2) The shielding portion is formed across the plurality of wiring layers. The sensor device according to (1) above. (3) The gate wiring has wiring extending in an in-plane direction inside the shield part. The sensor device according to (1) or (2). (4) The gate wiring is formed by a through via that penetrates the plurality of wiring layers. The sensor device according to any one of (1) to (3). (5) an inter-pixel wiring to which the gate wiring is connected is formed in an outermost wiring layer which is the wiring layer farthest from the semiconductor substrate in the wiring layer portion; The shield portion extends from an adjacent wiring layer of the farthest wiring layer in the wiring layer portion toward the semiconductor substrate. The sensor device according to any one of (1) to (4). (6) The shielding portion has an annular cross-sectional shape in the in-plane direction. The sensor device according to any one of (1) to (5). (7) The shield portion is formed of an insulating material different from the interlayer insulating material in the wiring layer portion. The sensor device according to any one of (1) to (6). (8) The shielding portion is made of a low-k material. The sensor device according to (7) above. (9) The shielding portion is a hollow portion. The sensor device according to any one of (1) to (6). (10) It is a sensor device for distance measurement using the indirect ToF method. The sensor device according to any one of (1) to (9). (11) a light emitting unit that emits light for distance measurement; a sensor unit that receives light emitted from the light emitting unit and reflected by an object, The sensor unit a semiconductor substrate; and a wiring layer section formed on the semiconductor substrate and having a plurality of wiring layers; a photoelectric conversion element that performs photoelectric conversion; a first charge holding unit and a second charge holding unit that hold charges accumulated in the photoelectric conversion element; a first transfer transistor that transfers the charges to the first charge holding unit; a pixel including a second transfer transistor that transfers the charge to the second charge holding portion is formed in a stacked structure of the semiconductor substrate and the wiring layer portion, A shield portion is formed to surround each of the gate wirings of the first and second transfer transistors extending in the thickness direction in the wiring layer portion. Sensing module. [Explanation of symbols]

[0122] 1. Sensor unit (sensor device) 2 Light-emitting part 6 Sensing Module 10 Ranging device Ob Object Li irradiation light Lr reflected light 11 Pixel array section 12 Transfer gate driver 21, 21-1, 21-2 Gate drive lines 22, 22-1, 22-2 vertical signal lines Px, PxA, PxB, PxC pixels PD photodiode FD, FD1, FD2 Floating Diffusion TG, TG1, TG2 transfer transistors STG, STG1, STG2 transfer drive signals Ss surface Sb back side 31 Semiconductor substrate 32 Wiring layer section 32a wiring layer 32a-1 First wiring layer 32a-2 Second wiring layer 32a-3 Third wiring layer 32a-4 Fourth wiring layer 32b Interlayer insulating film 34 Boundary (pixel boundary) 50, 50A gate wiring 60, 60B, 60C shield part

Claims

1. a semiconductor substrate; and a wiring layer section formed on the semiconductor substrate and having a plurality of wiring layers; a photoelectric conversion element that performs photoelectric conversion; a first charge holding unit and a second charge holding unit that hold charges accumulated in the photoelectric conversion element; a first transfer transistor that transfers the charges to the first charge holding unit; a pixel including a second transfer transistor that transfers the charge to the second charge holding portion is formed in a stacked structure of the semiconductor substrate and the wiring layer portion, Insulating shield portions are formed to surround the gate wirings of the first and second transfer transistors extending in the thickness direction in the wiring layer portion. Sensor device.

2. The shielding portion is formed across the plurality of wiring layers. The sensor device according to claim 1 .

3. The gate wiring has wiring extending in an in-plane direction inside the shield part. The sensor device according to claim 1 .

4. The gate wiring is formed by a through via that penetrates the plurality of wiring layers. The sensor device according to claim 1 .

5. an inter-pixel wiring to which the gate wiring is connected is formed in an outermost wiring layer which is the wiring layer farthest from the semiconductor substrate in the wiring layer portion; The shield portion extends from an adjacent wiring layer of the farthest wiring layer in the wiring layer portion toward the semiconductor substrate. The sensor device according to claim 1 .

6. The shielding portion has an annular cross-sectional shape in the in-plane direction. The sensor device according to claim 1 .

7. The shield portion is formed of an insulating material different from the interlayer insulating material in the wiring layer portion. The sensor device according to claim 1 .

8. The shielding portion is made of a low-k material. The sensor device according to claim 7 .

9. The shielding portion is a hollow portion. The sensor device according to claim 1 .

10. It is a sensor device for distance measurement using the indirect ToF method. The sensor device according to claim 1 .

11. a light emitting unit that emits light for distance measurement; a sensor unit that receives light emitted from the light emitting unit and reflected by an object, The sensor unit a semiconductor substrate; and a wiring layer section formed on the semiconductor substrate and having a plurality of wiring layers; a photoelectric conversion element that performs photoelectric conversion; a first charge holding unit and a second charge holding unit that hold charges accumulated in the photoelectric conversion element; a first transfer transistor that transfers the charges to the first charge holding unit; a pixel including a second transfer transistor that transfers the charge to the second charge holding unit is formed in a stacked structure of the semiconductor substrate and the wiring layer unit, Insulating shield portions are formed to surround the gate wirings of the first and second transfer transistors extending in the thickness direction in the wiring layer portion. Sensing module.

Images