Method, computer program, and computer-readable storage medium (Horizontal and vertical assertions for verification of neuromorphic hardware)

Abstract

To provide a method for simulating and validating a neural network system, and a computer program.SOLUTION: Simulation and validation of neural network systems is provided. In various embodiments, a description of an artificial neural network is read. A directed graph is constructed comprising a plurality of edges and a plurality of nodes, each of the plurality of edges corresponding to a queue and each of the plurality of nodes corresponding to a computing function of the neural network system. A graph state is updated over a plurality of time steps according to the description of the neural network, the graph state being defined by the contents of each of the plurality of queues. Each of a plurality of assertions is tested at each of the plurality of time steps, each of the plurality of assertions being a function of a subset of the graph state. Invalidity of the neural network system is indicated for each violation of one of the plurality of assertions.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] FIELD Embodiments of the present disclosure relate to neural network processing, and more particularly to horizontal and vertical assertions for verification of neuromorphic hardware. Summary of the Invention [Problem to be solved by the invention]

[0002] A method and computer program for simulating and validating a neural network system are provided. [Means for solving the problem]

[0003] According to embodiments of the present disclosure, a method and computer program product for simulating and verifying a neural network system is provided. In various embodiments, a description of an artificial neural network is read. A directed graph is constructed including a plurality of edges and a plurality of nodes, where each of the plurality of edges corresponds to a cue and each of the plurality of nodes corresponds to a computational function of the neural network system. A graph state is updated over a plurality of time steps according to the description of the neural network, where the graph state is determined by the contents of each of the plurality of cues. At each of the plurality of time steps, each of a plurality of assertions is tested, where each of the plurality of assertions is a function of a subset of the graph state. Invalidity of the neural network system is indicated for each violation of one of the plurality of assertions. [Brief explanation of the drawings]

[0004] [Figure 1] 1 illustrates a neural core according to an embodiment of the present disclosure. [Figure 2] 1 illustrates an exemplary inference processing unit (IPU) according to an embodiment of the present disclosure. [Figure 3]1 illustrates a multi-core inference processing unit (IPU) according to an embodiment of the present disclosure. [Figure 4] 1 illustrates a neural core and associated network according to an embodiment of the present disclosure. [Figure 5] FIG. 2 is an exemplary schematic diagram of horizontal and vertical assertions according to an embodiment of the present disclosure. [Figure 6] FIG. 10 is an exemplary schematic diagram of a vertical assertion, according to an embodiment of the present disclosure. [Figure 7] FIG. 10 is an exemplary schematic diagram of assertion logic during two cycles, according to an embodiment of the present disclosure. [Figure 8] FIG. 10 is an exemplary schematic diagram of assertion logic during three cycles, according to an embodiment of the present disclosure. [Figure 9] FIG. 2 is an exemplary schematic diagram of a trace of a particular activity pixel in a layer, according to an embodiment of the present disclosure. [Figure 10] 1 illustrates a method for simulating and validating a neural network system according to an embodiment of the present disclosure. [Figure 11] 1 illustrates a computing node according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0005] An artificial neuron is a mathematical function whose output is a nonlinear function of a linear combination of its inputs. Two neurons are connected where the output of one is an input to the other. A weight is a scalar value that encodes the strength of the connection between the output of one neuron and the input of another.

[0006] A neuron calculates an output, called an activation value, by applying a nonlinear activation function to a weighted sum of its inputs. A weighted sum is an intermediate result calculated by multiplying each input by its corresponding weight and accumulating the products. A partial sum is a weighted sum of a subset of the inputs. The weighted sum of all inputs can be calculated incrementally by accumulating one or more partial sums.

[0007] A neural network is a collection of one or more neurons. Neural networks are often divided into groups of neurons called layers. A layer is a collection of one or more neurons that all receive input from the same layer and all send output to the same layer, typically performing a similar function. An input layer is a layer that receives input from sources outside the neural network. An output layer is a layer that sends output to targets outside the neural network. All other layers are intermediate processing layers. A multilayer neural network is a neural network with more than one layer. A deep neural network is a multilayer neural network with many layers.

[0008] A tensor is a multidimensional array of numbers. A tensor block is a contiguous subarray of the elements of a tensor.

[0009] Each neural network layer is associated with a parameter tensor V, a weight tensor W, an input data tensor X, an output data tensor Y, and an intermediate data tensor Z. The parameter tensor contains all of the parameters that control the neuron activation function σ in the layer. The weight tensor contains all of the weights that connect inputs to the layer. The input data tensor contains all of the data that the layer consumes as input. The output data tensor contains all of the data that the layer computes as output. The intermediate data tensor contains any data that the layer generates as intermediate computations, such as partial sums.

[0010] The data tensors for a layer (input, output, and intermediate) can be three-dimensional, with the first two dimensions interpreted as encoding spatial location and the third dimension interpreted as encoding a different feature. For example, if the data tensor represents a color image, the first two dimensions encode the vertical and horizontal coordinates within the image, and the third dimension encodes the color at each location. Because every element of the input data tensor X can be connected to every neuron by a separate weight, the weight tensor W generally has six dimensions, concatenating the three dimensions of the input data tensor (input row a, input column b, input feature c) and the three dimensions of the output data tensor (output row i, output column j, output feature k). The intermediate data tensor Z has the same shape as the output data tensor Y. The parameter tensor V concatenates the three output data tensor dimensions with an additional dimension o that indexes the parameters of the activation function σ. In some embodiments, the activation function σ does not require any additional parameters, in which case no additional dimensions are required. However, in some embodiments, the activation function σ requires at least one additional parameter that appears in the additional dimension o.

[0011] The elements of the output data tensor Y of a layer can be calculated as in Equation 1, where the neuron activation function σ is composed of a vector of activation function parameters V[i,j,k,:], and the weighted sum Z[i,j,k] can be calculated as in Equation 2.

number

number

[0012] For simplicity of notation, we can refer to the weighted sum in Equation 2 as the output, which is equivalent to using a linear activation function Y[i,j,k]=σ(Z[i,j,k])=Z[i,j,k], with the understanding that the same description applies without loss of generality when different activation functions are used.

[0013] In various embodiments, the computation of the output data tensor as described above is decomposed into smaller problems, each of which can then be solved in parallel on one or more neural cores, or on one or more cores of a conventional multi-core system.

[0014] It will be understood from the above that neural networks are parallel structures. Neurons in a given layer receive elements x from one or more layers or other inputs. i Each neuron receives an input X with an element w i and a weight W with a weight b. In various embodiments, the weighted sum of the inputs is adjusted by a bias b, and the result is then passed to the nonlinear F(·). For example, the activation value of a single neuron can be calculated as y=F(b+Σx i w i ) can be expressed as

[0015] Because all neurons in a given layer receive input from the same layer and calculate their output independently, neuron activations can be calculated in parallel. This aspect of the neural network as a whole accelerates the overall computation by performing the computation on parallel distributed cores. Furthermore, vector operations can be calculated in parallel within each core. Even in the case of recurrent inputs, such as when a layer projects back onto itself, all neurons are still updated simultaneously. In effect, the recurrent connections are delayed to match subsequent inputs to the layer.

[0016] Referring now to FIG. 1, a neural core according to an embodiment of the present disclosure is shown. Neural core 100 is a tileable computational unit that computes one block of output tensors. Neural core 100 has M inputs and N outputs. In various embodiments, M=N. To compute an output tensor block, the neural core multiplies an M×1 input data tensor block 101 by an M×N weight tensor block 102 and accumulates the products into a weighted sum stored in an 1×N intermediate tensor block 103. An O×N parameter tensor block contains O parameters that specify each of the N neuron activation functions that are applied to the intermediate tensor blocks 103, producing a 1×N output tensor block 105.

[0017] Multiple neural cores can be tiled into a neural core array, which in some embodiments is two-dimensional.

[0018] A neural network model is a set of constants that collectively specify the entire computation performed by a neural network, including the graph of connections between neurons and the weight and activation function parameters for every neuron. Training is the process of modifying a neural network model to perform a desired function. Inference is the process of applying a neural network to inputs to generate outputs without modifying the neural network model.

[0019] An inference processing unit is a category of processor that performs neural network inference. A neural inference chip is a specific physical instance of an inference processing unit.

[0020] Referring now to FIG. 2, an exemplary inference processing unit (IPU) according to an embodiment of the present disclosure is shown. The IPU 200 includes a memory 201 for a neural network model. As described above, the neural network model may include synaptic weights for the neural network to be computed. The IPU 200 includes an activity memory 202, which may be temporary. The activity memory 202 may be divided into an input domain and an output domain and stores neuron activity values for processing. The IPU 200 includes a neural computation unit 203 that loads the neural network model from the model memory 201. Input activity values are provided from the activity memory 202 prior to each computation step. Output from the neural computation unit 203 is written back to the activity memory 202 for processing in the same or another neural computation unit.

[0021] In various embodiments, the micro-engines 204 are included in the IPU 200. In such embodiments, all operations within the IPU are directed by the micro-engines. As described below, various embodiments may provide a central micro-engine, distributed micro-engines, or both. A global micro-engine may be referred to as a chip micro-engine, while a local micro-engine may be referred to as a core micro-engine or local controller. In various embodiments, a micro-engine includes one or more micro-engines, microcontrollers, state machines, CPUs, or other controllers.

[0022] Referring to FIG. 3, a multi-core inference processing unit (IPU) according to an embodiment of the present disclosure is shown. The IPU 300 includes memory 301 for neural network models and instructions. In some embodiments, memory 301 is divided into a weight portion 311 and an instruction portion 312. As described above, the neural network model may include synaptic weights for the neural network to be calculated. The IPU 300 includes an activity value memory 302, which may be temporary. The activity value memory 302 may be divided into an input domain and an output domain and stores neuron activity values for processing.

[0023] The IPU 300 includes an array 306 of neural cores 303. Each core 303 includes a computation unit 333 that operates to load a neural network model from the model memory 301 and perform vector computations. Each core also includes a local activation memory 332. Input activation values are provided from the local activation memory 332 prior to each computation step. Output from the computation unit 333 is written back to the activity memory 332 for processing by the same or another computation unit.

[0024] IPU 300 includes one or more networks-on-chip (NoCs) 305. In some embodiments, partial sum NoC 351 interconnects cores 303 and transmits partial sums between them. In some embodiments, a separate parameter distribution NoC 352 connects cores 303 to memory 301 for distributing weights and instructions to cores 303. It will be appreciated that various configurations of NoCs 351 and 352 are suitable for use with the present disclosure. For example, broadcast networks, row broadcast networks, tree networks, and switched networks may be used.

[0025] In various embodiments, a global micro-engine 304 is included in the IPU 300. In various embodiments, a local core controller 334 is included in each core 303. In these embodiments, the global micro-engine (chip micro-engine) and the local core controller (core micro-engine) cooperate to support operations. Specifically, at 361, the global micro-engine 304 loads computational instructions from the instruction portion 312 of the model memory 301 into the core controller 334 on each core 303. At 362, the global micro-engine 304 loads parameters (e.g., neural network / synaptic weights) from the weight portion 311 of the model memory 301 into the neural computation unit 333 on each core 303. At 363, the local core controller 334 loads neural network activity data from the local activity memory 332 into the neural computation unit 333 on each core 303. As described above, activation values are provided to neurons of a particular neural network defined by the model, and may come from the same or another neural computation unit, or may come from outside the system. At 364, the neural computation unit 333 performs a calculation when instructed by the local core controller 334 to generate an activation value for the output neuron. Specifically, the calculation involves applying input synaptic weights to the input activity value. It will be appreciated that various methods are available for performing such a calculation, including in silico dendrites and vector multiplication units. At 365, when instructed by the local core controller 334, the results of the calculation are stored in the local activity memory 332. As described above, these stages can be pipelined to provide efficient use of the neural computation units on each core. It will also be appreciated that inputs and outputs may be transferred from the local activity memory 332 to the global activity memory 302 depending on the requirements of a given neural network.

[0026] Thus, the present disclosure provides runtime control of operations in an inference processing unit (IPU). In some embodiments, the micro-engine is centralized (a single micro-engine). In some embodiments, the IPU computation is distributed (performed by an array of cores). In some embodiments, the runtime control of operations is hierarchical, involving both centralized and distributed micro-engines.

[0027] One or more microengines direct the execution of all operations in the IPU. Each microengine instruction corresponds to several sub-operations (e.g., address generation, load, calculation, store, etc.). Core microcode executes on the core microengines (e.g., 334). For local computation, the core microcode contains instructions to perform a complete single tensor operation, such as a convolution between a weight tensor and a data tensor. For distributed computation, the core microcode contains instructions to perform a single tensor operation on a subset (and partial sum) of the locally stored data tensors. Chip microcode executes on the chip microengines (e.g., 304). The microcode contains instructions to perform all of the tensor operations in the neural network.

[0028] Referring now to FIG. 4, an exemplary neural core and associated network is illustrated, according to an embodiment of the present disclosure. Core 401, which may be implemented as described with reference to FIG. 1, is interconnected with additional cores by networks 402...404. In this embodiment, network 402 is responsible for distributing weights and / or instructions, network 403 is responsible for distributing partial sums, and network 404 is responsible for distributing activation values. However, it will be understood that various embodiments of the present disclosure may combine these networks or further separate them into multiple additional networks.

[0029] Input activation values (X) are distributed from off-core to core 401 via activation network 404 and into activation memory 405. Layer instructions are distributed from off-core to core 401 via weight / instruction network 402 and into instruction memory 406. Layer weights (W) and / or parameters are distributed from off-core to core 401 via weight / instruction network 402 and into weight memory 407 and / or parameter memory 408.

[0030] The weight matrix (W) is read from the weight memory 407 by a vector matrix multiply (VMM) unit 409. The activation vector (V) is read from the activation memory 405 by the vector matrix multiply (VMM) unit 409. The vector matrix multiply (VMM) unit 409 then performs a vector-matrix multiplication Z=X T The vector-vector unit 410 computes W and provides the result to the vector-vector unit 410. The vector-vector unit 410 reads additional partial sums from the partial sum memory 411 and receives additional partial sums from off-core via the partial sum network 403. The vector-vector unit 410 computes vector-vector operations from these source partial sums. For example, various partial sums may be summed in sequence. The resulting target partial sums may be written to the partial sum memory 411, sent off-core via the partial sum network 403, or fed back for further processing by the vector-vector unit 410, or a combination thereof.

[0031] After all calculations for a given layer's inputs are completed, the partial sum results from the vector-vector unit 410 are provided to the activation unit 412 for calculation of the output activation values. The activation vector (Y) is written to the activation memory 405. The layer's activation values (including the results written to the activation memory) are redistributed among the cores from the activation memory 405 via the activation network 404. As each core receives the activation value, it writes it to its local activation memory. Once processing for a given frame is complete, the output activation values are read from the activation memory 405 and sent out of the core via the network 404.

[0032] Thus, in operation, a core control micro-engine (e.g., 413) coordinates the data movement and computation of the core. The micro-engine issues an activity memory address read operation to load an input activity block into the vector-matrix multiplication unit. The micro-engine issues a weight memory address read operation to load a weight block into the vector-matrix multiplication unit. The micro-engine issues a calculation operation to the vector-matrix multiplication unit to cause the vector-matrix multiplication unit to calculate a partial sum block.

[0033] The microengine issues one or more of a partial sum read / write memory address operation, a vector calculation operation, or a partial sum communication operation to read partial sum data from a partial sum source, calculate using a partial sum arithmetic unit, or write the partial sum data to a partial sum target. Writing the partial sum data to a partial sum target can include communicating external to the core via a partial sum network interface or sending the partial sum data to an activated arithmetic unit.

[0034] The micro-engine issues an activation function calculation operation to the activation value block, causing the activation function arithmetic unit to calculate the output activation value block, and issues an activation value memory address write operation, causing the output activation value block to be written to the activation value memory through the activation value memory interface.

[0035] Thus, for a given core, various source, target, address type, computation type, and control components are defined.

[0036] The sources for the vector-vector unit 410 include the vector-matrix multiplication (VMM) unit 409, constants from the parameter memory 408, the partial sum memory 411, the partial sum result from the previous cycle (TGT partial sum), and the partial sum network 403.

[0037] The targets of the vector-vector unit 410 include a partial sum memory 411, the partial sum result for the subsequent cycle (SRC partial sum), an activation unit 412, and a partial sum network 403.

[0038] Thus, a given instruction may be a read or write from activation memory 405, a read from weight memory 407, or a read or write from partial sum memory 411. Computational operations performed by the core include vector matrix multiplication by VMM unit 409, vector (partial sum) operations by vector-vector unit 410, and activation functions by activation unit 412.

[0039] Control operations include updating the program counter and the loop counter and / or sequence counter.

[0040] Thus, memory operations are issued to read weights from weight memory addresses, read parameters from parameter memory addresses, read activations from activation memory addresses, read partial sums from partial sum memory addresses, and write partial sums to partial sum memory addresses. Computation operations are issued to perform vector-matrix multiplication, vector-vector operations, and activation functions. Communication operations are issued to select vector-vector operands, route messages on the partial sum network, and select partial sum targets. Loops over layer outputs and loops over layer inputs are controlled by control operations that specify the micro-engine's program counter, loop counter, and sequence counter.

[0041] According to an embodiment of the present disclosure, data distribution can be provided from a global memory array. The global memory array includes multiple elements, each with a memory element and a buffer. Weights and instructions are provided from the global memory to the memory elements over a network. An exemplary configuration of a core is described above with respect to FIG. 3. Memory 303 of FIG. 3 can be implemented as described with respect to the global memory array.

[0042] As discussed above, many core architectures for neural inference offer significant advantages in computational power. If neural network weights and parameters are not provided to the computational cores in a timely manner, the cores cannot perform useful computations. As a result, the performance of a neural chip is limited by the ability to communicate neural network weights and parameters to the computational cores on the chip. On-chip memory significantly improves memory bandwidth compared to typical off-chip memory, such as dynamic random access memory (DRAM) or high-bandwidth memory (HBM). Furthermore, on-chip memory is more energy-efficient than off-chip memory, resulting in a more power-efficient neural inference system. In various embodiments, on-chip memory can include static random access memory (SRAM) or other embedded memory. However, communicating neural network weights to the cores at a rate comparable to the processing speed remains a challenge.

[0043] Convolutional neural networks (CNNs) can achieve certain efficiencies. In CNNs, the same weight matrix (sometimes called a convolution filter) is used repeatedly. To minimize the amount of on-chip memory used, it is preferable to store a given weight matrix in a single location without duplication. To store large neural networks, some on-chip memory embodiments consist of a collection of many memory elements. It will also be appreciated that many cores are targets for memory weights. This creates a many-to-many communication problem (between many cores and many memory elements). Broadcasting weights can cause network-on-chip (NoC) congestion, resulting in numerous collisions and pipeline stalls, leading to broadcast bandwidth degradation.

[0044] As described above, various embodiments of a neural inference chip provide a grid of neural inference cores to accelerate neural network inference. In various embodiments, instruction pre-scheduling is provided. Because neural network evaluations require computation of a regular pattern, instructions can be pre-scheduled without any stalls to achieve high performance. However, it is preferable that all neural network weights are delivered to the cores just in time as pre-scheduled. If the weight delivery network becomes congested and stalls, pre-scheduling of neural network evaluations will not work.

[0045] This disclosure provides a stall-free weight propagation network-on-chip that propagates weight parameters from a grid of memory elements to a grid of compute cores. A one-dimensional scheme is first presented below, then extended to a two-dimensional grid scheme. These techniques are further extended to support different weight distributions, such as striping (where different rows of cores have different weights).

[0046] The techniques described herein work consistently even when there are different times for transmitting instructions to memory elements and data from memory elements to compute cores. These techniques accommodate instruction flows that can access any column in any order. The new scheme does not constrain all columns to start at the same time.

[0047] According to aspects of the present disclosure, deep learning and deep inference neural networks are widely used in a variety of applications and for workloads that are difficult to solve with conventional microprocessors. These networks can be significantly accelerated using specialized hardware called neural network accelerators or neural inference accelerators. In some cases, these accelerators do not have a traditional sequentially executing instruction stream. Instead, neural inference accelerators often contain many components that move in parallel, and each moving component can be pipelined, creating a queue structure. In other words, the input to a unit becomes clear after many cycles are repeated and post-processed. The output of one object can be the input to another object. This effectively creates a graph structure and queue of objects. Because there is no traditional model of sequential execution instructions, verifying accelerators with many parallel moving objects is complex and error-prone. Therefore, the present disclosure provides a unique approach to designing and verifying networks of objects by defining vertical and horizontal assertions in the time and space dimensions. These assertions define how the machine behaves, effectively replacing the traditional view of sequential instructions.

[0048] According to aspects of the present disclosure, a combination of horizontal and vertical assertions is provided. Horizontal assertions include a set of concepts whose Boolean output depends solely on the current observable state of the validator. Vertical assertions include a set of concepts whose Boolean output depends on the past (and possibly current) observed states of the validator. When an assertion fails, it indicates an invalid / abnormal condition in the validator, requiring further investigation.

[0049] An example horizontal assertion includes a vector-by-matrix multiplication (VMM) unit. To perform a matrix multiplication, the VMM unit must receive a VMM operation (Op), an activity packet from the unified memory, and a weight packet from the weight buffer in the same cycle. Each cycle, the VMM unit's three corresponding input queues can be interrogated to verify that either all three queues contain valid values or none of the three queues contain valid values in the current cycle. The latter case typically occurs near the beginning of a simulation, when the first few ops / packets have not yet arrived. This configuration is useful for detecting timing issues / errors in the network due to queue delays. An example vertical assertion includes a VMM unit, as described above, that receives a VMM operation, an activity packet, and a weight packet during execution.

[0050] The present disclosure provides a method for verifying that there was no packet confusion or improper ordering / delivery when such a large number of packets, e.g., three times as many, arrived. For example, the present disclosure verifies that the system is not attempting to use a VMM operation intended for use with a liveness value packet intended for use with a different VMM operation. In some embodiments, this verification involves attaching metadata information to each queue element X, and then the metadata information is passed / appended to the metadata of all new queue outputs that depend on X.

[0051] In this exemplary embodiment, when the VMM operation, liveness read address, and weight buffer read address are generated, the VMM thread can include a counter value N indicating the number of matrix multiplications in the VMM unit that are intended for this triplet of data. By the time the VMM operation, liveness packet, and weight packet arrive at the VMM unit, the metadata is interpreted and the counter values in these three packets are verified to match. Thus, the process can be thought of as an MD5 hash-like technique for ensuring that nothing is corrupted in the pipeline; instead of passing a simple integer value N, a large hash value (e.g., 128 bits) can be passed and checked for a match. For example, in a simulator, this can help detect race conditions that could result in the incorrect use of a queue output. This is also beneficial in detecting memory corruption issues early in the pipeline, which can include ensuring that every new hash is a function of all previous hashes it depends on. Because vertical assertions can require significant memory resources and slow down processing, some embodiments include the option to disable vertical assertions on a per-component basis (e.g., via a specification in the simulation.json file).

[0052] FIG. 5 is an illustration of horizontal and vertical assertions according to the present disclosure. As shown, three queues 501-503, each with a different delay, are given, and their sums are all fed into a fourth queue 504. The contents of each queue are shown at two time instances, "t" and later "t+1." As shown, the heads of each queue advance and are aggregated into the fourth queue 504, after which the contents of the queues are shifted from t to t+1. For example, the heads of the three queues 501-503 at time "t" (indicated by oval 510) are combined to become 1+6+2=9, which is shown as the tail of the fourth queue 504 at time t+1. Once the heads of each queue 501-503 are combined into queue 504, new data is written to the tail of each queue 501-503.

[0053] According to this disclosure, horizontal assertions can compare data at a single instant in time and evaluate whether that data meets a predetermined condition. In the exemplary embodiment of Figure 5, horizontal assertion 510 is shown checking that at time t, the sum of the heads of all queues is less than 30. In this case, 1 + 6 + 2 = 9, which is less than 30, so the assertion functions.

[0054] According to the present disclosure, vertical assertions compare data in chronological order. In the exemplary embodiment shown in FIG. 5, a vertical assertion (denoted by an oval 520) is shown both at time t and at a later time t+1, comparing data elements in three queues after the queues have advanced one cycle. This assertion checks whether queues 501-503 are functioning properly and whether data has been propagated properly in queues 501-503. In this case, in the next cycle, the values (1, 9, 2) are propagated properly, so the assertion works. Furthermore, verifying that the value of any given vertical assertion 520 (denoted as a row across three queues) is propagated correctly is, by extension, verifying that the previous row, the following row, or both rows are also propagated correctly. For example, if it is determined that at time t+1 the values 1, 9, and 2 of vertical assertion 520 have advanced by one increment, then it can be inferred that at time t+1 the previous row (with values 7, 4, and 11) has also advanced by one increment.

[0055] This disclosure provides cycle-by-cycle simulation of neuromorphic (e.g., NorthPole) hardware. Each time the advance_cycle() function is called, the state of the simulation for the next cycle can be calculated. A configuration of components (similar to the TrueNorth corelet) can be included, where each component outputs a set of queues and receives as input pointers corresponding to the output queues of other components. In some embodiments, queues can be implemented in C++ as circular buffers with specific delays. An operation (Op) queue delay can encode the delay until the Op is executed, and a data queue delay encodes the delay until output data is delivered to its destination. In each cycle, each component reads the head of its input queue, processes the data, and writes the results to the tail of its output queue.

[0056] For example, an N delay queue has N+1 elements (reads / writes can occur at different queue elements), so for parallelization purposes, any two components, even if nested within each other, can compute in parallel during each cycle because they operate on different data elements. Thus, the resulting NorthPole simulator can have thousands of queues. Therefore, adding assertions to code, such as those provided in this disclosure, is beneficial for verifying the correctness of the code.

[0057] According to aspects of the present disclosure, a simulation can model the evolution of the hardware state on a cycle-by-cycle basis. For example, by exploring queues at each cycle and comparing the C++ implementation with the Verilog code, verification of the hardware implementation can be provided. Additionally, the simulator described herein provides upstream software verification by verifying the correctness of numerous components, including, but not limited to, the NP-PyTorch framework, hand-coded assembly code implementing various layers, compilers, and actual ELF files.

[0058] Overall, the simulator is designed to be as close as possible to a "Golden Truth" that the hardware and software teams can use to verify the correctness of their code. As checks / assertions become more sophisticated, more certainty can be achieved about the correctness of the validator. Additionally, the hardware is modeled using a network of queues to save state and restart the simulator / validator. In some embodiments that employ this queue format, it is trivial to model variables as zero-delay queues, making it practically possible to represent (using the queue format) the internal state of a node that may change multiple times in a given cycle.

[0059] This disclosure provides techniques for applying intuitive targeted assertions to test the most common use cases of a chip. Given a ground truth state s(t) at time t and a simulator / validator state V(t) at time t, let P(V(t+1) ≠ s(t+1) | V(t) = s(t)) be the probability of a bug in the simulator's output state appearing at time t+1. If P(S'(t+1) | S'(t) = s(t)) is the probability of observing state S'(t+1) in the hardware implementation under test, then the probability that there is a bug in the hardware implementation that is not picked up by the validator at time t+1 (because both the validator and the HW give the same incorrect result) is

number

[0060] There is statistical independence in the development of the hardware implementation of the software validator (i.e., errors in the HW implementation do not affect the occurrence of errors in the validator implementation, i.e.

number

number

[0061] Therefore, the present disclosure carefully implements validators to minimize the number of bugs at the source. In one aspect, this is incorporated into the above-mentioned network of queue simulation methods for comparing states over time. This can be achieved, for example, by adding metadata associated with all upstream queues that feed into each new queue element X, thereby building assertions (e.g., vertical assertions) that depend on current and past states. The simulator's hierarchical structure also enables the creation of horizontal assertions that compare the states of physically distant components (e.g., comparing the state of a vector-matrix multiplier (VMM) unit with the contents of a partial sum memory). Thus, the present disclosure provides a mechanism for "tagging" data in any single cycle and tracing this tagged data over time to track how the tagged data propagates. This is applicable not only to the NorthPole architecture but to any complex AI chip development effort as well.

[0062] Figure 6 shows an exemplary embodiment of vertical assertions that adds each queue element with user-defined metadata useful for defining assertions. This can include, for example, the cycle number when the queue element was first pushed into the queue. Also, as shown to the right, the metadata for each component's input queue is added to the metadata for the component's output queue. The component's metadata can be used within each component 601-608 to define assertions and check past behavior / states, as encoded in the metadata, against the current expected state within the component 601-608. Thus, as the metadata is processed over time, the user can selectively choose to compare and retain only a select subset of the metadata, as desired.

[0063] FIG. 7 illustrates another exemplary embodiment of the present disclosure implementing a floating-point FP16 bypass mode, in which a vector-vector unit 701 (VV unit) sends an FP16 value to an activation function unit 703 (ActFX unit). Over a two-cycle period, the first and second halves of the FP16 are written to unified memory by the activation function unit 703. In this exemplary embodiment, to ensure that the same value is pushed to the activation function unit 703 over the two cycles, it is a specification invariant that the FP16 register in the vector-vector unit 701 that holds this value is not updated during the two cycles. Also, in the first cycle, the activation function thread 702 (ActFX) must send an operation, but in the second cycle, it is not supposed to send an operation. Therefore, assertion logic is required in the activation function unit 703 to check these conditions. Now, the activation function unit 703 cannot simply check that the two values sent by the vector-vector unit 701 are identical, since the vector-vector unit 701 could have simply updated its FP16 register with the same value. A check is therefore needed to ensure that no update occurred. Thus, the vector-vector unit 701 can send metadata about when the FP16 it sent was last updated. This allows a vertical assertion to be defined in the activation function unit 703 to check, during the second cycle, that the received FP16 value comes from a vector-vector unit 701 register that was not updated in the previous cycle.

[0064] FIG. 8 shows another exemplary embodiment in which a vector matrix multiplier unit crossbar (VMM crossbar) 801 sets an address and initiates an operation in the same cycle, so that three cycles later, the matching triplet of information arrives at the vector matrix multiplier unit (VMM unit) 804. A set of read addresses arrives at the weight buffer 802 and activity memory 803, and data retrieved from memory arrives at the vector matrix multiplier unit (VMM unit) 804. The vector matrix multiplier unit crossbar (VMM crossbar) 801 also sends operations directly to the matrix multiplier unit (VMM unit) 804. From the perspective of the vector matrix multiplier unit (VMM unit) 804, it can be difficult to ensure that all three input data received are uncorrupted and correct (e.g., corruption may be the result of a race condition or a pointer accessing an improper memory area, corrupting the weight buffer).

[0065] Thus, by queueing metadata containing the cycle number when each piece of attached metadata was pushed onto the queue, the vector matrix multiplier unit (VMM unit) 804 can ensure that all three inputs it receives correspond to the same three outputs (two addresses and one operation) generated by the vector matrix multiplier unit crossbar (VMM crossbar) 801 three cycles earlier. Furthermore, by attaching a hash string (such as an MD5 hash of the weight matrix or activation data) as metadata and regenerating a new string at each component based on its input hash string, the final output data generated can be verified as a result of the composition of all hash strings. Thus, the present disclosure provides tracing and verification of the processing pipeline. Similarly, before a read or write is performed in memory, an assertion can be used to check for data corruption by checking that the MD5 hash string remains unchanged since the last memory update.

[0066] Figure 9 illustrates another aspect of the present disclosure that provides a visualization of the trace for a particular activity pixel within a layer, showing which pixels influence it upstream, or which pixels in previous layers influenced the pixel of interest. This visualization feature of the present disclosure has applications that may be useful for creating visualizations of deep networks or helping algorithm developers understand why they are observing a particular result. Advantageously, this can be done in a validator by tagging the queue element corresponding to the original pixel with metadata and then propagating that metadata to other queues to trace which activity pixels in other layers it influences. This therefore extends the capabilities of the hardware, as it is not straightforward to see how such tracing can be done directly in hardware.

[0067] In the exemplary embodiment shown in Figure 9, three layers 901-903 are shown with a pixel of interest 910 identified in the first / top layer 901. The propagation of that first pixel 910 to the second / middle / subsequent layer 902 is indicated by an enlarged pixel 920 (the enlargement in size relative to pixel 910 indicating the acquisition of additional metadata). Furthermore, pixel 920 can be mapped or traced to the next layer 903 to reveal the influence of layers 901 and 902 on the enlarged pixel 930. This tracing can be done forward or backward in time and / or upward or downward relative to the layered layers shown in Figure 9.

[0068] Thus, this disclosure employs assertions in software code to debug neuromorphic hardware using a co-designed network of hardware queue simulations, tagging a single spike / packet at any point in the pipeline and tracing how it affects every single other module upstream or downstream, cycle by cycle, providing a wealth of checks / assertions to verify hardware correctness as well as other algorithm development objectives as described herein.

[0069] Referring to FIG. 10, a method for simulating and validating a neural network system according to an embodiment of the present disclosure is illustrated. At 1001, a description of an artificial neural network is read. At 1002, a directed graph is constructed including a plurality of edges, each corresponding to a cue, and a plurality of nodes, each corresponding to a computational function of the neural network system. At 1003, a graph state defined by the contents of each of the plurality of cues is updated over a plurality of time steps according to the description of the neural network. At 1004, at each of the plurality of time steps, each of a plurality of assertions that is a function of a subset of the graph state is tested. At 1005, a violation of one of the plurality of assertions indicates invalidity of the neural network system.

[0070] 11, a schematic of an example computing node is shown. Computing node 10 is merely one example of a suitable computing node and is not intended to suggest any limitation regarding the scope of use or functionality of the embodiments described herein. Nevertheless, computing node 10 may implement and / or perform any of the functions described above.

[0071] In computing node 10, computer system / server 12 is operable in numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with computer system / server 12 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices.

[0072] Computer system / server 12 may be described in the general context of computer system-executable instructions, such as program modules, executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. Computer system / server 12 may be practiced in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media, including memory storage devices.

[0073] 11, computer system / server 12 in computing node 10 is shown in the form of a general-purpose computing device. Components of computer system / server 12 may include, but are not limited to, one or more processors or processing units 16, system memory 28, and a bus 18 coupling various system components, including system memory 28, to processor 16.

[0074] Bus 18 represents any one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures, including, by way of example and not limitation, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, a Peripheral Component Interconnect (PCI) bus, a Peripheral Component Interconnect Express (PCIe), and an Advanced Microcontroller Bus Architecture (AMBA).

[0075] In various embodiments, one or more inference processing units (not shown) are coupled to bus 18. In such embodiments, the IPU may receive data from or write data to memory 28 via bus 18. Similarly, the IPU may interact with other components via bus 18, as described herein.

[0076] Computer system / server 12 typically includes a variety of computer system-readable media, which can be any available media that can be accessed by computer system / server 12 and includes both volatile and nonvolatile media, removable and non-removable media.

[0077] System memory 28 may include computer system-readable media in the form of volatile memory, such as random access memory (RAM) 30 or cache memory 32, or both. Computer system / server 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 34 may be provided for reading from and writing to a non-removable, non-volatile magnetic medium (not shown, typically referred to as a "hard drive"). Although not shown, a magnetic disk drive may be provided for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive may be provided for reading from and writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM, or other optical medium. In such cases, each may be connected to bus 18 by one or more data media interfaces. As further shown and described below, memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of embodiments of the present disclosure.

[0078] By way of example and not limitation, memory 28 may store a program / utility 40 having a set (at least one) of program modules 42, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or any combination thereof, may include an implementation of a networking environment. Program modules 42 generally perform the functions and / or methods of embodiments of the present invention described herein.

[0079] The computer system / server 12 may also communicate with one or more external devices 14, such as a keyboard, pointing device, display 24, etc., one or more devices that allow a user to interact with the computer system / server 12, or any device that allows the computer system / server 12 to communicate with one or more other computing devices (e.g., a network card, modem, etc.), or combinations thereof. Such communication may occur via an input / output (I / O) interface 22. Furthermore, the computer system / server 12 may also communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or combinations thereof, via a network adapter 20. As shown, the network adapter 20 communicates with other components of the computer system / server 12 via a bus 18. Although not shown, it is understood that other hardware and / or software components may be used with the computer system / server 12. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0080] The present disclosure may be a system, a method, or a computer program product, or a combination thereof, which may include a computer-readable storage medium or media having computer-readable program instructions thereon for causing a processor to perform aspects of the present invention.

[0081] A computer-readable storage medium may be any tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, a mechanically encoded device having instructions recorded thereon, and any suitable combination of the above. As used herein, computer-readable storage media is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses through fiber optic cable), or electrical signals sent through wires.

[0082] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network can include copper cables, optical fibers, wireless networks, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device.

[0083] The computer-readable program instructions for carrying out the operations of the present disclosure may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microprocessors, firmware instructions, state-setting data, or source or object cores written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, and traditional procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer readable program instructions to individualize the electronic circuitry by utilizing state information of the computer readable program instructions to implement aspects of the present disclosure.

[0084] Aspects of the present disclosure will be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0085] These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, whereby the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer program instructions can also be stored in a computer-readable medium that can direct a computer, other programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, whereby the instructions stored in the computer-readable medium include an article of manufacture containing instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0086] The computer program instructions may be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to generate a computer-implemented process, whereby the instructions executing on the computer, other programmable apparatus, or other device provide a process for performing the functions / operations specified in one or more blocks of the flowchart and / or block diagram.

[0087] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, tensorlet, block, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions shown in the blocks may occur in a different order than that shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or a combination of dedicated hardware and computer instructions.

[0088] The descriptions of various embodiments of the present disclosure have been presented for illustrative purposes, but they are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method for simulating and validating a neural network system, the method comprising: reading a description of the artificial neural network; constructing a directed graph including a plurality of edges and a plurality of nodes, each of the plurality of edges corresponding to a queue and each of the plurality of nodes corresponding to a computational function of the neural network system; updating a graph state over a plurality of time steps according to said description of said artificial neural network, said graph state being defined by the contents of each of said plurality of cues; testing each of a plurality of assertions at each of the plurality of time steps, each of the plurality of assertions being a function that evaluates whether a predetermined condition is met based on a subset of the graph state that includes the contents of the plurality of cues, and the testing is to determine whether the plurality of assertions function; indicating invalidity of the neural network system for each violation of one of the plurality of assertions; A method comprising:

2. The method of claim 1 , wherein each of the plurality of queues corresponds to a delay in a pipeline.

3. 3. The method of claim 1, wherein updating the graph state comprises calculating, for each node, its associated function based on current or past graph states transmitted via the plurality of queues.

4. outputting a result of each of the plurality of computational functions at each of the plurality of time steps; The method of any one of claims 1 to 3, further comprising:

5. The method of claim 1 , wherein the directed graph provides a cycle-accurate model of the neural network system.

6. adding cue metadata to each cue at each of the plurality of time steps; The method of any one of claims 1 to 5, further comprising:

7. testing a plurality of assertions against the queue metadata; The method of claim 6 further comprising:

8. The method of claim 6, wherein the neural network system is free of data-dependent branching.

9. 7. The method of claim 6, wherein the queue metadata is a function of the data provided by the head of each incoming queue to each of the nodes.

10. 1. A computer program for verifying a neural network system, the computer program comprising program instructions executable by a processor, the program instructions causing the processor to: reading a description of the artificial neural network; constructing a directed graph including a plurality of edges and a plurality of nodes, each of the plurality of edges corresponding to a queue and each of the plurality of nodes corresponding to a computational function of the neural network system; updating a graph state over a plurality of time steps according to said description of said artificial neural network, said graph state being defined by the contents of each of said plurality of cues; testing each of a plurality of assertions at each of the plurality of time steps, each of the plurality of assertions being a function that evaluates whether a predetermined condition is met based on a subset of the graph state that includes the contents of the plurality of cues, and the testing is to determine whether the plurality of assertions function; indicating invalidity of the neural network system for each violation of one of the plurality of assertions; A computer program for causing a computer to carry out a method comprising:

11. 11. The computer program product of claim 10, wherein each of the plurality of queues corresponds to a delay in a pipeline.

12. 12. The computer program product of claim 10 or 11, wherein updating the graph state comprises calculating, for each node, its associated function based on current or past graph states transmitted via the plurality of queues.

13. outputting a result of each of the plurality of computational functions at each of the plurality of time steps; 13. The computer program of claim 10, further comprising:

14. 14. A computer program product according to any one of claims 10 to 13, wherein the directed graph provides a cycle-accurate model of the neural network system.

15. adding cue metadata to each cue at each of the plurality of time steps; 15. The computer program of claim 10, further comprising:

16. testing a plurality of assertions against the queue metadata; 16. The computer program of claim 15, further comprising:

17. 17. The computer program product of claim 10, wherein the plurality of assertions are specified prior to runtime.

18. 15. The computer program product of claim 14, wherein the neural network system is free of data-dependent branching.

19. 20. The computer program product of claim 18, wherein the queue metadata is a function of the data provided by the head of each incoming queue to each of the nodes.

20. A computer readable storage medium having stored thereon a computer program according to any one of claims 10 to 19.

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