Systems, computer implementation methods, and computer programs (evaluation of quantum circuit optimization routines and knowledge base generation)

Abstract

To provide a system, a computer mounting method, and a computer program product for facilitating the evaluation of a quantum circuit optimization routine and the generation of a knowledge base.SOLUTION: According to one embodiment, the system may include a processor that executes a computer executable component stored in a memory. The computer executable component may include a compilation component that simultaneously performs different quantum circuit optimization sequences for multiple copies of the quantum circuit. The computer executable component may further include an identification component that identifies at least one of the different quantum circuit optimization sequences that produce an output quantum circuit containing defined criteria.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to quantum circuit optimization routines, and more particularly to evaluation and knowledge base generation of quantum circuit optimization routines. Summary of the Invention [Problem to be solved by the invention]

[0002] When running algorithms on short-term quantum devices, limitations arising from gate errors and environmental interactions place strict limits on the depth and gate count of quantum circuits from which quantum algorithms are constructed. Creating efficient quantum circuit optimization methods that globally reduce the gate count and depth of quantum circuits is a key component of the quantum computing toolkit. However, currently, it is not well understood which optimizations are most beneficial given an arbitrary input circuit. Furthermore, the order in which specific optimizations are applied can mean the difference between an optimized circuit and one that cannot be successfully executed on hardware. As quantum device sizes increase, this problem is exacerbated by the fact that blindly applying many optimization passes quickly becomes a performance bottleneck. [Means for solving the problem]

[0003] The following presents a summary in order to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or critical elements of particular embodiments or the claims, or to delineate any scope thereof. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a system, device, computer-implemented method, or computer program product, or combination thereof, that can facilitate evaluation of quantum circuit optimization routines and knowledge base generation is described.

[0004] According to one embodiment, a system may include a processor executing computer-executable components stored in a memory. The computer-executable components may include a compilation component that simultaneously executes different quantum circuit optimization sequences on multiple copies of the quantum circuit. The computer-executable components may further include an identification component that identifies at least one of the different quantum circuit optimization sequences that produces an output quantum circuit that includes the defined criteria.

[0005] According to another embodiment, a computer-implemented method may include simultaneously executing, by a system operatively coupled to a processor, different quantum circuit optimization sequences on multiple copies of the quantum circuit, and may further include identifying, by the system, at least one of the different quantum circuit optimization sequences that produces an output quantum circuit that includes the defined criteria.

[0006] According to another embodiment, a computer program product comprises a computer-readable storage medium having program instructions embodied thereon, the program instructions being executable by a processor to cause the processor to simultaneously perform different quantum circuit optimization sequences on multiple copies of a quantum circuit, the program instructions being further executable by the processor to cause the processor to identify at least one of the different quantum circuit optimization sequences that produces an output quantum circuit that includes defined criteria.

[0007] According to another embodiment, a system may include a processor that executes computer-executable components stored in a memory. The computer-executable components may include a knowledge base component that generates a knowledge base that includes multiple output quantum circuits generated from simultaneously executing different quantum circuit optimization sequences on multiple copies of the quantum circuit. The computer-executable components may further include a recommendation component that utilizes the trained model to recommend at least one of the different quantum circuit optimization sequences to generate an output quantum circuit that includes defined criteria.

[0008] According to another embodiment, a computer-implemented method may include generating, by a system operatively coupled to a processor, a knowledge base including multiple output quantum circuits generated from simultaneously executing different quantum circuit optimization sequences on multiple copies of the quantum circuit. The computer-implemented method may further include utilizing, by the system, a trained model that recommends at least one of the different quantum circuit optimization sequences to generate an output quantum circuit that includes defined criteria. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 shows a block diagram of an exemplary, non-limiting system, each of which can facilitate evaluation and knowledge base generation of quantum circuit optimization routines according to one or more embodiments described herein. [Figure 2] FIG. 1 shows a block diagram of an exemplary, non-limiting system, each of which can facilitate evaluation and knowledge base generation of quantum circuit optimization routines according to one or more embodiments described herein. [Figure 3] FIG. 1 shows a block diagram of an exemplary, non-limiting system, each of which can facilitate evaluation and knowledge base generation of quantum circuit optimization routines according to one or more embodiments described herein. [Figure 4]FIG. 1 shows a block diagram of an exemplary, non-limiting system, each of which can facilitate evaluation and knowledge base generation of quantum circuit optimization routines according to one or more embodiments described herein. [Figure 5] FIG. 1 shows a block diagram of an exemplary, non-limiting system, each of which can facilitate evaluation and knowledge base generation of quantum circuit optimization routines according to one or more embodiments described herein. [Figure 6] FIG. 1 shows a flow diagram of an exemplary, non-limiting computer-implemented method that may facilitate evaluation and knowledge base generation of quantum circuit optimization routines in accordance with one or more embodiments described herein. [Figure 7] FIG. 1 shows a flow diagram of an exemplary, non-limiting computer-implemented method that may facilitate evaluation and knowledge base generation of quantum circuit optimization routines in accordance with one or more embodiments described herein.

[0010] [Figure 8] 1 illustrates a block diagram of an exemplary non-limiting operating environment in which one or more embodiments described herein may be facilitated.

[0011] [Figure 9] FIG. 1 illustrates a block diagram of an exemplary, non-limiting cloud computing environment in accordance with one or more embodiments of the present disclosure.

[0012] [Figure 10] FIG. 1 illustrates a block diagram of exemplary, non-limiting abstraction model layers in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] The following detailed description is merely exemplary and is not intended to limit the embodiments, or the application or uses of embodiments, or combinations thereof. Furthermore, there is no intention to be bound by any express or implied information presented in the preceding Background or Overview sections or in the Detailed Description section.

[0014] One or more embodiments will now be described with reference to the drawings. Like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It will be apparent, however, that in various instances one or more embodiments may be practiced without these specific details.

[0015] As referred to herein, an "entity" may comprise a human being, a client, a user, a computing device, a software application, an agent, a machine learning (ML) model, an artificial intelligence (AI), or another entity, or a combination thereof. It will be understood that as referred to herein as an element being "coupled" to another element, this may describe one or more different types of coupling, including, but not limited to, a chemical coupling, a communicative coupling, an electrical coupling, an electromagnetic coupling, an operative coupling, an optical coupling, a physical coupling, a thermal coupling, or another type of coupling, or a combination thereof.

[0016] Quantum computing generally uses quantum mechanical phenomena for the purposes of performing computing and information processing functions. Quantum computing can be viewed in contrast to classical computing, which generally uses transistors and operates on binary values. That is, while classical computers can operate on bit values of either 0 or 1, quantum computers operate on quantum bits (qubits) with superpositions of both 0 and 1, and may entangle multiple qubits and use interference.

[0017] When running algorithms on short-term quantum devices, limitations arising from gate errors and environmental interactions place strict limits on the depth and gate count of quantum circuits from which quantum algorithms are constructed. Creating efficient quantum circuit optimization methods that globally reduce the gate count and depth of quantum circuits is a key component of the quantum computing toolkit. However, currently, it is not well understood which optimizations are most beneficial given an arbitrary input circuit. Furthermore, the order in which specific optimizations are applied can mean the difference between an optimized circuit and one that cannot be successfully executed on hardware. As quantum device sizes increase, this problem is exacerbated by the fact that blindly applying many optimization passes quickly becomes a performance bottleneck.

[0018] 1, 2, 3, and 4 illustrate block diagrams of exemplary, non-limiting systems 100, 200, 300, and 400, respectively, each of which may facilitate evaluation of quantum circuit optimization routines and knowledge base generation in accordance with one or more embodiments described herein. Each of the systems 100, 200, 300, and 400 may include a routine evaluation system 102. The routine evaluation system 102 of the system 100 illustrated in FIG. 1 may include a memory 104, a processor 106, a compilation component 108, an identification component 110, or a bus 112, or any combination thereof. The routine evaluation system 102 of the system 200 illustrated in FIG. 2 may further include a storage component 202. The routine evaluation system 102 of the system 300 illustrated in FIG. 3 may further include a knowledge base component 302. The routine evaluation system 102 of the system 400 illustrated in FIG. 4 may further include a recommendation component 402.

[0019] It should be understood that the embodiments of the present disclosure illustrated in the various figures disclosed herein are for illustrative purposes only, and thus the architecture of such embodiments is not limited to the illustrated systems, devices, or components, or combinations thereof. For example, in some embodiments, system 100, system 200, system 300, system 400, or routine evaluation system 102, or combinations thereof, may further comprise various computers or computing-based elements, or both, described herein with reference to operating environment 800 and FIG. 8. In embodiments, such computers or computing-based elements, or both, may be used in connection with implementing one or more of the systems, devices, components, or computer-implemented operations, or combinations thereof, illustrated and described in connection with FIG. 1, FIG. 2, FIG. 3, FIG. 4, or other figures, or combinations thereof, disclosed herein.

[0020] Memory 104 may store one or more computer- and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processor 106 (e.g., a classical processor, a quantum processor, or another type of processor, or a combination thereof), may facilitate performance of operations defined by the executable components and / or instructions. For example, memory 104 may store computer- and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processor 106, may facilitate performance of various functions described herein with respect to routine evaluation system 102, compilation component 108, identification component 110, storage component 202, knowledge base component 302, recommendation component 402, or another component associated with routine evaluation system 102, or a combination thereof, as described herein with or without reference to the various figures of this disclosure.

[0021] The memory 104 may comprise volatile memory (e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), or another type of volatile memory, or a combination thereof), or non-volatile memory (e.g., read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or another type of non-volatile memory, or both), which may utilize one or more memory architectures. Further examples of memory 104 are described below with reference to system memory 816 and FIG. 8. Such examples of memory 104 may be utilized to implement any embodiment of the present disclosure.

[0022] Processor 106 may comprise one or more types of processors or electronic circuitry (e.g., classical processors, quantum processors, or other types of processors or electronic circuitry, or both, or a combination thereof) that may implement one or more computer- and / or machine-readable, writable, or executable, or combination thereof, components or instructions that may be stored in memory 104. For example, processor 106 may perform various operations that may be specified by such computer- and / or machine-readable, writable, or executable, or combination thereof, components or instructions, or both, including, but not limited to, logic, control, input / output (I / O), arithmetic, or the like, or a combination thereof. In some embodiments, processor 106 may comprise one or more central processing units, multi-core processors, microprocessors, dual microprocessors, microcontrollers, system-on-chip (SOC), array processors, vector processors, quantum processors, or other types of processors, or a combination thereof. Further examples of processor 106 are described below with reference to processing unit 814 and FIG. 8. Such an example of the processor 106 may be utilized to implement any embodiment of the present disclosure.

[0023] The routine evaluation system 102, memory 104, processor 106, compilation component 108, identification component 110, storage component 202, knowledge base component 302, recommendation component 402, or other components of the routine evaluation system 102 described herein, or combinations thereof, may be communicatively, electrically, operatively, or optically coupled to one another, or combinations thereof, via a bus 112, and may perform the functions of the system 100, system 200, system 300, system 400, routine evaluation system 102, or any component or combination thereof coupled thereto. The bus 112 may comprise one or more memory buses, memory controllers, peripheral buses, external buses, local buses, quantum buses, or other types of buses, or combinations thereof, which may utilize a variety of bus architectures. Further examples of the bus 112 are described below with reference to the system bus 818 and FIG. 8. Such examples of the bus 112 may be utilized to implement any embodiment of the present disclosure.

[0024] The routine evaluation system 102 may comprise any type of component, machine, device, facility, equipment, or appliance, or combination thereof, having a processor and / or capable of effective or operable communication using a wired or wireless network or both. All such embodiments are contemplated. For example, the routine evaluation system 102 may comprise a server device, a computing device, a general-purpose computer, a special-purpose computer, a quantum computing device (e.g., a quantum computer), a tablet computing device, a handheld device, a server-class computing machine or database or both, a laptop computer, a notebook computer, a desktop computer, a mobile phone, a smartphone, a consumer electronic device or equipment or both, an industrial or commercial device or both, a digital assistant, a multimedia Internet-enabled phone, a multimedia player, or another type of device or combination thereof.

[0025] The routine evaluation system 102 may be coupled (e.g., communicatively, electrically, operatively, optically, or via another type of coupling, or a combination thereof) to one or more external systems, sources, or devices (e.g., classical or quantum computing devices, or both, communications devices, or other types of external system sources and / or devices, or a combination thereof) using wires or cables, or both. For example, the routine evaluation system 102 may be coupled (e.g., communicatively, electrically, operatively, optically, or via another type of coupling, or a combination thereof) to one or more external systems, sources, or devices (e.g., classical or quantum computing devices, or both, communications devices, or other types of external system sources and / or devices, or a combination thereof) using data cables, including, but not limited to, High-Definition Multimedia Interface (HDMI) cables, Recommendation Standard (RS) 232 cables, Ethernet cables, or other data cables, or a combination thereof.

[0026] In some embodiments, the routine evaluation system 102 may be coupled (e.g., communicatively, electrically, operatively, optically, or via another type of coupling, or a combination thereof) to one or more external systems, sources, or devices (e.g., classical or quantum computing devices, or both, communications devices, or other types of external system sources and / or devices, or a combination thereof) via a network. For example, such a network may comprise a wired or wireless network, or both, including, but not limited to, a cellular network, a wide area network (WAN) (e.g., the Internet), a local area network (LAN), or another network, or a combination thereof. The routine evaluation system 102 may be configured to support a wide variety of wireless technologies, including, but not limited to, Wireless Fidelity (Wi-Fi), Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX), Enhanced General Packet Radio Service (Enhanced GPRS), Third Generation Partnership Project (3GPP) Long Term Evolution (LTE), Third Generation Partnership Project 2 (3GPP2) Ultra Mobile Broadband (UMB), High Speed Packet Access (HSPA), Zigbee, and other 80 It may communicate with one or more external systems, sources, or devices (e.g., computing devices), or combinations thereof, using virtually any desired wired or wireless technology, or both, including 2.XX wireless technologies or legacy telecommunications technologies, or combinations thereof, BLUETOOTH®, Session Initiation Protocol (SIP), ZIGBEE®, RF4CE protocol, WirelessHART protocol, 6LoWPAN (IPv6 over Low Power Wireless Area Network), Z-Wave, ANT, Ultra-Wideband (UWB) standard protocols, or other proprietary and non-proprietary communication protocols, or combinations thereof.Thus, in some embodiments, the routine evaluation system 102 may include hardware (e.g., a central processing unit (CPU), a transceiver, a decoder, quantum hardware, a quantum processor, or other hardware, or a combination thereof), software (e.g., a set of threads, a set of processes, running software, a quantum pulse schedule, a quantum circuit, a quantum gate, or other software, or a combination thereof), or a combination of hardware and software that may facilitate communication of information between the routine evaluation system 102 and an external system, source, or device (e.g., a computing device, a communication device, and / or another type of external system, source, or device, or a combination thereof), or a combination thereof.

[0027] Routine evaluation system 102 may include one or more computer- and / or machine-readable, writable, or executable, or combinations thereof, components and / or instructions that, when executed by processor 106 (e.g., a classical processor, a quantum processor, or another type of processor, or combinations thereof), may facilitate performance of operations defined by such components and / or instructions. Furthermore, in many embodiments, any component associated with routine evaluation system 102 described herein, with or without reference to the various figures of this disclosure, may include one or more computer- and / or machine-readable, writable, or executable, or combinations thereof, components and / or instructions that, when executed by processor 106, may facilitate performance of operations defined by such components and / or instructions. For example, the compilation component 108, the identification component 110, the storage component 202, the knowledge base component 302, the recommendation component 402, or any other component associated with (e.g., communicatively, electronically, operatively, or optically, or a combination thereof, coupled to or utilized by) the routine evaluation system 102 disclosed herein, or a combination thereof, may include such computer- and / or machine-readable, writable, or executable, or a combination thereof, components and / or instructions. As a result, according to many embodiments, the routine evaluation system 102, or any component associated therewith, as disclosed herein, may utilize the processor 106 to execute such computer- and / or machine-readable, writable, or executable, or a combination thereof, components and / or instructions to facilitate performance of one or more operations described herein with reference to the routine evaluation system 102, or any such component associated therewith, or both.

[0028] Routine evaluation system 102 may facilitate (e.g., via processor 106) performance of operations performed by and / or associated with compilation component 108, identification component 110, storage component 202, knowledge base component 302, recommendation component 402, or another component associated with routine evaluation system 102 disclosed herein, or a combination thereof. For example, as described in detail below, routine evaluation system 102 may facilitate (e.g., via processor 106) simultaneously running different quantum circuit optimization sequences on multiple copies of a quantum circuit, or identifying at least one of the different quantum circuit optimization sequences that produces an output quantum circuit that includes defined criteria, or both.

[0029] In the above examples, as described in more detail below, the routine evaluation system 102 may further facilitate (e.g., via the processor 106) simultaneously running different quantum circuit optimization sequences on multiple copies of the quantum circuit based on one or more properties of the quantum circuit or a quantum device capable of executing at least one of the output quantum circuits, simultaneously running different quantum circuit optimization sequences on multiple copies of the quantum circuit to generate multiple output quantum circuits each including a different defined criterion, and reducing the processing workload associated with identifying at least one of the different quantum circuit optimization sequences that generate the output quantum circuit including the defined criterion, or storing multiple output quantum circuits generated from simultaneously running different quantum circuit optimization sequences on multiple copies of the quantum circuit, wherein each of the multiple output quantum circuits includes a different defined criterion, or a combination thereof. In the above examples, the defined criterion may include a defined quantum circuit-based metric, a defined pulse-based metric, or another defined criterion, or a combination thereof.

[0030] In another example, as described in detail below, the routine evaluation system 102 may facilitate (e.g., via the processor 106) generating a knowledge base including multiple output quantum circuits generated from simultaneously running different quantum circuit optimization sequences on multiple copies of the quantum circuit, or utilizing a trained model that recommends at least one of the different quantum circuit optimization sequences to generate an output quantum circuit that includes defined criteria, or both. In this example, as described in detail below, the routine evaluation system 102 may further facilitate (e.g., via the processor 106) simultaneously running different quantum circuit optimization sequences on multiple copies of the quantum circuit based on one or more properties of the quantum circuit or a quantum device capable of executing at least one of the output quantum circuits, or simultaneously utilizing a trained model that ranks at least one of the different quantum circuit optimization sequences based on defined entity criteria, or a combination thereof. In this example, the defined criteria may include a defined quantum circuit-based metric, a defined pulse-based metric, or another defined criterion, or a combination thereof.

[0031] The compilation component 108 may perform different quantum circuit optimization sequences on multiple copies of the quantum circuit, for example, the compilation component 108 may perform different quantum circuit optimization sequences on multiple copies of the quantum circuit simultaneously.

[0032] To simultaneously run different quantum circuit optimization sequences on multiple copies of a quantum circuit, compilation component 108 may use, for example, an application or software hook process, or both. For example, compilation component 108 may use such an application or software hook process, or both, that enables compilation component 108 to send a raw quantum circuit (e.g., a pre-generated quantum circuit) to an external computing resource (e.g., a remote server) that can generate and / or run identical copies (e.g., instances) of the raw quantum circuit through respective different optimization sequences (e.g., through respective different quantum circuit optimization routines or compilers, or both). In this example, such an external computing resource may include a cloud computing node 910 (e.g., a remote server) of a cloud computing environment 950 described below with reference to FIG. 9 that can generate identical copies (e.g., instances) of the raw quantum circuit and further simultaneously (e.g., run in parallel) the identical copies through respective different optimization sequences (e.g., through respective different quantum circuit optimization routines or compilers, or both). In some embodiments, the above-mentioned raw quantum circuit may comprise an entire raw quantum circuit (e.g., an entire, complete, pre-generated quantum circuit). In some embodiments, the above-mentioned raw quantum circuit may comprise a subset quantum circuit of the entire raw quantum circuit (e.g., a subset quantum circuit of the entire, complete, pre-generated quantum circuit).

[0033] Compilation component 108 may simultaneously run different quantum circuit optimization sequences on multiple copies of a quantum circuit (e.g., the raw quantum circuit described above) based on one or more properties of a quantum device capable of executing the quantum circuit, the output quantum circuit, or both, that may be generated by compilation component 108 (e.g., via the application or software hooking process described above, or both, and an external computing resource (e.g., a remote server)). For example, using the application or software hooking process described above, compilation component 108 may send the raw quantum circuit (e.g., a fully complete or partially pre-generated quantum circuit) to the external computing resource (e.g., a remote server) described above that can generate and / or execute (e.g., simultaneously, in parallel) identical copies (e.g., instances) of the raw quantum circuit through respective different optimization sequences (e.g., through respective different quantum circuit optimization routines or compilers, or both) based on (e.g., using) one or more properties of a quantum device capable of executing at least one of the quantum circuit or the output quantum circuit that may be generated by compilation component 108. In this example, the quantum device may comprise, for example, a quantum computer, and one or more properties of such a quantum device may include, but are not limited to, specifications, configuration properties, operational properties, or other properties, or a combination thereof.

[0034] In some embodiments, one or more of such different optimized sequences may be obtained by the routine evaluation system 102, for example, from a vendor (e.g., via a purchase or license agreement, or both). In these embodiments, the routine evaluation system 102 or the compilation component 108, or both, may provide such different optimized sequences to the external computing resource (e.g., a remote server) described above. In some embodiments, one or more of such different optimized sequences may be provided by an entity as defined herein. For example, an entity as defined herein may provide one or more of such different optimized sequences using an interface component (not shown) of the routine evaluation system 102 (e.g., an application programming interface (API), a representational state transfer (REST) API, a graphical user interface (GUI), etc.). In this example, the routine evaluation system 102 or the compilation component 108, or both, may provide such different optimized sequences to the computing resource (e.g., a remote server) provided by the entity. In some embodiments, such an entity may request (e.g., via an API, GUI, or REST API of the routine evaluation system 102, or a combination thereof) that the compilation component 108 or the external computing resource described above (e.g., a remote server), or both, run one or more identical copies of the raw quantum circuit (e.g., simultaneously) using one or more particular optimization sequences.

[0035] The compilation component 108 may generate multiple output quantum circuits, each including a different defined criterion, by simultaneously running different quantum circuit optimization sequences on multiple copies of the quantum circuit. For example, using the application and / or software hook processes described above, the compilation component 108 may send the raw quantum circuit (e.g., a fully complete or partially pre-generated quantum circuit) to an external computing resource (e.g., a remote server) described above that can generate and / or run (e.g., simultaneously, in parallel) identical copies (e.g., instances) of the raw quantum circuit through different optimization sequences (e.g., through different quantum circuit optimization routines or compilers, or both) to generate multiple such output quantum circuits, each including a different defined criterion.

[0036] In some embodiments, each of the plurality of output quantum circuits may comprise an entire quantum circuit (e.g., an entire complete quantum circuit). For example, in embodiments in which the raw quantum circuit that may be input to compilation component 108 comprises an entire quantum circuit, then each of the plurality of output quantum circuits may comprise an entire quantum circuit. In some embodiments, each of the plurality of quantum circuits may comprise a subset quantum circuit of the entire raw quantum circuit (e.g., a subset quantum circuit of the entire complete quantum circuit). For example, in embodiments in which the raw quantum circuit that may be input to compilation component 108 comprises a subset quantum circuit of the entire quantum circuit, then each of the plurality of output quantum circuits may comprise a subset quantum circuit of the entire quantum circuit.

[0037] In some embodiments, such different defined criteria may have defined quantum-circuit-based metrics, which may include, but are not limited to, depth (e.g., circuit depth), gate type (e.g., two-qubit gates), number of gates, two-qubit gate count, duration (e.g., gate duration or circuit execution duration, or both), fidelity in noisy simulation (e.g., if small enough to be simulated, i.e., less than about 40 qubits), number of swap gates inserted during compilation, number of measurements, number of gates or state teleportations involved, or another defined quantum-circuit-based metric, or a combination thereof. In some embodiments, such different defined criteria may have defined pulse-based metrics, which may include, but are not limited to, duration (e.g., pulse duration or pulse schedule duration, or both), frequency component optimization metrics (e.g., if the pulse sequence has frequency components in a selected (e.g., defined) range of frequencies), waveform preservation criteria (e.g., defining the number of bits (e.g., qubits) used to preserve the waveform), or another defined pulse-based metric, or a combination thereof.

[0038] It should be appreciated that by utilizing the above-described application and / or software hook process to generate (e.g., via a server) such multiple output quantum circuits, each including a different defined criteria, routine evaluation system 102 and / or compilation component 108 may thereby reduce the processing workload associated with identifying quantum circuit optimization sequences that generate output quantum circuits that include the defined criteria. For example, rather than utilizing processor 106 to simultaneously or sequentially run a raw quantum circuit through each different optimization sequence, routine evaluation system 102 and / or compilation component 108 may utilize the above-described external computing resource (e.g., a remote server) to simultaneously run different quantum circuit optimization sequences on multiple copies of the raw quantum circuit to generate such multiple output quantum circuits, each including a different defined criteria. In this example, by utilizing such external computing resources to simultaneously run different quantum circuit optimization sequences on multiple copies of a raw quantum circuit to generate multiple such output quantum circuits, each including different defined criteria, the routine evaluation system 102 or compilation component 108, or both, may thereby reduce at least one of the processing workloads of the processor 106, or the time it takes to identify a quantum circuit optimization sequence that produces an output quantum circuit that includes the particular defined criteria, or both.

[0039] The identification component 110 may identify at least one of the different quantum circuit optimization sequences described above that produces an output quantum circuit that includes defined criteria (e.g., a complete or partial output quantum circuit that includes the desired or target criteria, or both). For example, the identification component 110 may identify at least one of the different quantum circuit optimization sequences described above (e.g., different quantum circuit optimization routines or compilers, or both) that produces an output quantum circuit that includes particular defined criteria, which may be defined, for example, by the entities described above. For example, the identification component 110 may identify at least one of the different quantum circuit optimization sequences described above (e.g., different quantum circuit optimization routines or compilers, or both) that produces an output quantum circuit that has one or more defined quantum circuit-based metrics, or one or more defined pulse-based metrics, or both, which may be defined by the entities described above. In various embodiments, such an entity may define such defined criteria using, for example, an API, a GUI, a REST API, or another interface component of the routine evaluation system 102, or a combination thereof.

[0040] In some embodiments, based on identifying at least one of the above-described different quantum circuit optimization sequences that produces an output quantum circuit that includes particular defined criteria (e.g., a complete or partial output quantum circuit that includes desired or target criteria, or both), identification component 110 may further notify an entity implementing routine evaluation system 102 of the quantum circuit optimization sequence that produced the output quantum circuit that includes the defined criteria, or provide such output quantum circuit to the entity, or both. For example, identification component 110 may use an API, a GUI, a REST API, or another interface component of routine evaluation system 102, or a combination thereof, to notify such entity of the quantum circuit optimization sequence that produced the output quantum circuit that includes the defined criteria, or provide such output quantum circuit to the entity, or both.

[0041] Storage component 202 may store multiple output quantum circuits generated from simultaneously running different quantum circuit optimization sequences on multiple copies of a quantum circuit, where each of the multiple output quantum circuits includes a different defined criterion. For example, storage component 202 may include a database or memory (e.g., memory having the same configuration or functionality as memory 104, or both) that may store multiple output quantum circuits that may be simultaneously generated by compilation component 108 (e.g., via an application or software hook process, or both, as well as a remote server) as described above, and each of which may have a different defined criterion (e.g., metric). In this example, storage component 202 may also store such different defined criteria, each corresponding to multiple quantum circuits. In this example, storage component 202 may further store various unprocessed quantum circuits that may be input to routine evaluation system 102 by different entities implementing routine evaluation system 102.

[0042] The knowledge base component 302 may generate a knowledge base that includes multiple output quantum circuits generated from simultaneously executing different quantum circuit optimization sequences on multiple copies of a quantum circuit. For example, the knowledge base component 302 may utilize a knowledge base generation process, application, or software, or a combination thereof, to generate a knowledge base having, for example, various raw quantum circuits that may be input to the routine evaluation system 102 by different entities implementing the routine evaluation system 102, different quantum circuit optimization sequences that may be used to simultaneously execute multiple copies of such various raw quantum circuits (e.g., by the above-mentioned compilation component 108 or a remote server, or both), multiple output quantum circuits that may be simultaneously generated by such different quantum circuit optimization sequences, or different defined criteria (e.g., metrics) or combinations thereof for such multiple output quantum circuits. In this example, the knowledge base component 302 may retrieve from the storage component 202 the various raw quantum circuits, the multiple output quantum circuits, or different defined criteria (e.g., metrics) or combinations thereof corresponding to the multiple output quantum circuits. In this example, knowledge base component 302 may obtain the different quantum circuit optimization sequences (e.g., knowledge base component 302 may obtain identification data identifying each such different quantum circuit optimization sequence), for example, from compilation component 108, or from an external computing resource (e.g., a remote server) that may be utilized by compilation component 108, as described above, or both.

[0043] The recommendation component 402 may utilize the trained model to recommend (e.g., to an entity implementing the routine evaluation system 102) at least one of different quantum circuit optimization sequences to generate an output quantum circuit that includes defined criteria. For example, the recommendation component 402 may utilize a trained machine learning (ML) or trained artificial intelligence (AI) model, or both, to recommend (e.g., to an entity implementing the routine evaluation system 102) at least one of different quantum circuit optimization sequences that may be utilized by the compilation component 108 (e.g., via the above-described application or software hooking process, or both, as well as a remote server) to generate an output quantum circuit that has defined criteria (e.g., metrics). In this example, such trained models may include, but are not limited to, a trained neural network, a trained deep neural network, a trained classifier model, a trained predictive model, a trained support vector machine, or another trained model, or a combination thereof. In this example, such trained models may be trained using a learning process that includes, but is not limited to, a supervised learning process, an unsupervised learning process, an active learning process, or another learning process, or a combination thereof. In this example, such a trained model may be trained using the above-mentioned knowledge base, which may be generated by knowledge base component 302 as training data, for example.

[0044] In some embodiments, once sufficient statistics (e.g., many multiple output quantum circuits, each with a different defined criterion (e.g., metric)) have been obtained, the particular quantum circuit optimization sequence that performs relatively best on the raw quantum circuit input by the entity implementing the routine evaluation system 102 may be identified (e.g., via the identification component 110) and / or recommended (e.g., via the recommendation component 402) to the entity (e.g., via the API, GUI, or REST API of the routine evaluation system 102, or a combination thereof) as a potential option for performing further quantum circuit optimization. In some embodiments, the knowledge base component 302 may generate a knowledge base having various quantum circuit optimization data aggregated from multiple entities implementing the routine evaluation system 102 using the various input raw quantum circuits. In some embodiments, such a knowledge base may serve as a database that can be used as training data to train an ML model or an AI model or both (e.g., an ML algorithm or an AI algorithm or both) to determine which quantum circuit optimization routine performs relatively best for a given input raw quantum circuit prior to running the actual optimization sequence.

[0045] It will be appreciated that routine evaluation system 102 solves the short-term problem of identifying which quantum circuit optimization routine works relatively best for a given input raw quantum circuit, for example, by transparently running a collection of different quantum circuit optimization sequences on a remote server, thereby not degrading the performance of routine evaluation system 102, and storing output quantum circuits, each of which includes defined criteria for recommending the relatively best quantum circuit optimization procedure to the entity implementing routine evaluation system 102. It will also be appreciated that routine evaluation system 102 provides a long-term solution to this problem, for example, by providing a knowledge base having various raw quantum circuits that can be input to routine evaluation system 102 by different entities implementing routine evaluation system 102, different quantum circuit optimization sequences that can be used to simultaneously run multiple copies of such various raw quantum circuits (e.g., by the above-mentioned compilation component 108 or a remote server, or both), multiple output quantum circuits that can be simultaneously produced by such different quantum circuit optimization sequences, or different defined criteria (e.g., metrics) for such multiple output quantum circuits, or a combination thereof. That is, for example, it should be understood that the routine evaluation system 102 also provides a long-term solution to this problem by providing such a knowledge base that can be used to train ML models and / or AI models (e.g., ML algorithms and / or AI algorithms) to identify which quantum circuit optimization sequences perform relatively best for a given input raw quantum circuit.

[0046] 5 illustrates a block diagram of an exemplary, non-limiting system that can facilitate evaluation and knowledge base generation of quantum circuit optimization routines according to one or more embodiments described herein. Repeated descriptions of similar elements and / or processes utilized in each embodiment are omitted for the sake of brevity.

[0047] As shown in the exemplary embodiment illustrated in FIG. 5, compilation component 108 may receive raw quantum circuit 502 or pre-compiled quantum circuit 504, or both, as input (e.g., via an API, GUI, REST API, or another interface component, or a combination thereof, of routine evaluation system 102). Raw quantum circuit 502 may have the same configuration and / or functionality as that of the raw quantum circuit described above with reference to the exemplary embodiments illustrated in FIGS. 1, 2, 3, and 4. In some embodiments, raw quantum circuit 502 may comprise an entire raw quantum circuit (e.g., an entire, complete, pre-generated quantum circuit). In some embodiments, raw quantum circuit 502 may comprise a subset quantum circuit of an entire raw quantum circuit (e.g., a subset quantum circuit of an entire, complete, pre-generated quantum circuit).

[0048] 5, compilation component 108 may send raw quantum circuit 502 to requested compiler 506, which may be requested by an entity defined herein (e.g., via an API, GUI, REST API, or another interface component, or a combination thereof, of routine evaluation system 102), to generate compiled quantum circuit 508. In this exemplary embodiment, compilation component 108 and requested compiler 506 may send pre-compiled quantum circuit 504 and compiled quantum circuit 508, respectively, to quantum computer 510, where quantum computer 510 may execute pre-compiled quantum circuit 504 or compiled quantum circuit 508, or both.

[0049] 5, compilation component 108 may facilitate the generation of multiple copies of raw quantum circuit 502, and may further facilitate the concurrent execution of different quantum circuit optimization sequences on such multiple copies of raw quantum circuit 502. For example, compilation component 108 may use the above-described application and / or software hook process to enable compilation component 108 to transmit raw quantum circuit 502 to an external computing resource (e.g., a remote server not shown in FIG. 5) that can generate and / or execute identical copies (e.g., instances) of raw quantum circuit 502 through respective different optimization sequences (e.g., through respective different quantum circuit optimization routines or compilers, or both) (e.g., simultaneously, in parallel).

[0050] 5, compilation component 108 may use the above-described applications and / or software hook processes to generate, for example, a first copy of raw quantum circuit 502a, a second copy of raw quantum circuit 502b, or an Nth copy of raw quantum circuit 502N, or a combination thereof (e.g., where N indicates the total number of copies of raw quantum circuit 502), which may be transmitted to a remote server (not shown in FIG. 5). In this exemplary embodiment, the first copy of raw quantum circuit 502a, the second copy of raw quantum circuit 502b, or the Nth copy of raw quantum circuit 502N, or a combination thereof, may each have an identical copy of raw quantum circuit 502. In this exemplary embodiment, compilation component 108 may further use such applications or software hook processes, or both, as well as a remote server, to simultaneously (e.g., in parallel) execute a first copy of raw quantum circuit 502a through compiler runtime "A" 506a, a second copy of raw quantum circuit 502b through compiler runtime "B" 506b, and an Nth copy of raw quantum circuit 502N through compiler runtime "N" 506N. In this exemplary embodiment, compiler runtime "A" 506a, compiler runtime "B" 506b, and compiler runtime "N" 506N may each have a different quantum circuit optimization sequence (e.g., different quantum circuit optimization routine) that may be executed on the first copy of raw quantum circuit 502a, the second copy of raw quantum circuit 502b, and the Nth copy of raw quantum circuit 502N, respectively.

[0051] In the exemplary embodiment shown in FIG. 5 , based on the above-described concurrent execution of respective copies of raw quantum circuit 502 by compiler runtime “A” 506 a, compiler runtime “B” 506 b, and compiler runtime “N” 506 N, multiple output quantum circuits, each including a different defined criterion, may be generated and / or stored in storage component 202. For example, as shown in the exemplary embodiment illustrated in FIG. 5 , based on the above-described concurrent execution of respective copies of raw quantum circuit 502 by compiler runtime “A” 506 a, compiler runtime “B” 506 b, and compiler runtime “N” 506 N, multiple output quantum circuits, each having a compilation metric 512, may be generated and / or stored in storage component 202. In some embodiments, each of the above-described multiple output quantum circuits may comprise an entire quantum circuit (e.g., an entire complete quantum circuit). For example, in an embodiment in which raw quantum circuit 502 comprises an entire quantum circuit, then each of the above-described multiple output quantum circuits may comprise an entire quantum circuit. In some embodiments, each of the plurality of quantum circuits may comprise a subset of the entire raw quantum circuit (e.g., a subset of the entire complete quantum circuit). For example, in an embodiment in which raw quantum circuit 502 comprises a subset of the entire quantum circuit, then each of the plurality of output quantum circuits may comprise a subset of the entire quantum circuit.

[0052] Compilation metrics 512 may have the same data as the defined criteria, or different defined criteria, or both, described above with reference to the exemplary embodiments shown in Figures 1, 2, 3, and 4. For example, compilation metrics 512 may have defined quantum-circuit-based metrics, which may include, but are not limited to, depth (e.g., circuit depth), gate type (e.g., two-qubit gate), number of gates, two-qubit gate count, duration (e.g., gate duration or circuit execution duration, or both), fidelity in noisy simulation (e.g., if small enough to be simulated, i.e., less than about 40 qubits), number of swap gates inserted during compilation, number of measurements, number of gates or state teleportations involved, or another defined quantum-circuit-based metric or a combination thereof. In another example, the compilation metrics 512 may have defined pulse-based metrics, which may include, but are not limited to, duration (e.g., pulse duration or pulse schedule duration, or both), frequency component optimization metrics (e.g., if the pulse sequence has frequency components in a selected (e.g., defined) range of frequencies), waveform storage criteria (e.g., defining the number of bits (e.g., qubits) used to store the waveform), or another defined pulse-based metric or combination thereof.

[0053] In some embodiments, requested compiler 506 may obtain the above-mentioned multiple output quantum circuits, each having a compilation metric 512, or the compilation metrics 512 themselves, or both, from storage component 202. For example, requested compiler 506 may obtain the above-mentioned multiple output quantum circuits (e.g., complete or partial output quantum circuits), each having a compilation metric 512, or the compilation metrics 512 themselves, or both, from storage component 202 to facilitate processing raw quantum circuit 502, or generating compiled quantum circuit 508, or both.

[0054] 5, based on the generation of the above-described plurality of output quantum circuits, each having a compilation metric 512, identification component 110 may determine whether compiler runtime “A” 506a, compiler runtime “B” 506b, or compiler runtime “N” 506N, or a combination thereof, generated an output quantum circuit having a defined criteria (e.g., a complete or partial output quantum circuit that includes desired or target criteria, or both, that may be defined by an entity implementing routine evaluation system 102). For example, based on the generation of the above-described plurality of output quantum circuits, each having a compilation metric 512, identification component 110 may determine whether compiler runtime “A” 506a, compiler runtime “B” 506b, or compiler runtime “N” 506N, or a combination thereof, generated an output quantum circuit having one or more of the above-described defined quantum circuit-based metrics, or one or more of the defined pulse-based metrics, or a combination thereof, that may be defined by a local and / or cloud-based entity 516 illustrated in FIG. The local and / or cloud-based entities 516 may include entities defined herein that may implement the routine evaluation system 102 .

[0055] In embodiments in which identification component 110 determines that compiler runtime "A" 506a, compiler runtime "B" 506b, or compiler runtime "N" 506N, or a combination thereof, has generated an output quantum circuit that includes the above-defined criteria, identification component 110 may further notify a local and / or cloud-based entity 516 of such determination by identification component 110 (e.g., via an API, GUI, REST API, or another interface component, or combination thereof, of routine evaluation system 102). Additionally or alternatively, in these embodiments, identification component 110 may further provide such output quantum circuit to a local and / or cloud-based entity 516 (e.g., via an API, GUI, REST API, or another interface component, or combination thereof, of routine evaluation system 102).

[0056] 5, based on the generation and storage of the above-described multiple output quantum circuits, each having a compilation metric 512, knowledge base component 302 may generate a knowledge base (e.g., as described above with reference to the exemplary embodiments shown in FIGS. 1, 2, 3, and 4) having such multiple output quantum circuits, compilation metrics 512, or both. For example, knowledge base component 302 may utilize a knowledge base generation process, application, or software, or a combination thereof, to generate a knowledge base having, for example, various raw quantum circuits 502 that may be input to compilation component 108 by different local and / or cloud-based entities 516 implementing system 500, various quantum circuit optimization sequences that may use compiler runtime "A" 506a, compiler runtime "B" 506b, or compiler runtime "N" 506N, or a combination thereof, to respectively execute copies of such various raw quantum circuits 502 simultaneously, various output quantum circuits having various compilation metrics 512, or various compilation metrics 512, or a combination thereof.

[0057] In the above example, knowledge base component 302 may obtain various raw quantum circuits 502, various output quantum circuits with various compilation metrics 512, or various compilation metrics 512, or a combination thereof, from storage component 202. In this example, knowledge base component 302 may obtain various quantum circuit optimization sequences from, for example, compilation component 108, the remote server described above that may be utilized by compilation component 108, compiler runtime "A" 506a, compiler runtime "B" 506b, or compiler runtime "N" 506N, or a combination thereof.

[0058] 5, based on the generation of the above-described knowledge base, recommendation component 402 may utilize the trained model to recommend compilation strategy recommendations 514 to a local and / or cloud-based entity 516 (e.g., via an API, GUI, REST API, or another interface component, or a combination thereof, of routine evaluation system 102). For example, recommendation component 402 may utilize the trained ML or AI model, or both, trained (e.g., using the above-described knowledge base, which may be generated by knowledge base component 302) to recommend compilation strategy recommendations 514. In this example, compilation strategy recommendations 514, utilized by compiler runtime “A” 506a, compiler runtime “B” 506b, or compiler runtime “N” 506N, or a combination thereof, may include at least one of different quantum circuit optimization sequences that may produce an output quantum circuit having compilation metrics 512. In this example, such a trained model may include, but is not limited to, a trained neural network, a trained deep neural network, a trained classifier model, a trained predictive model, a trained support vector machine, or another trained model, or a combination thereof. In this example, such a trained model may be trained using a learning process, including, but not limited to, a supervised learning process, an unsupervised learning process, an active learning process, or another learning process, or a combination thereof. In this example, such a trained model may be trained using, for example, the knowledge base described above, which may be generated by knowledge base component 302 as training data.

[0059] 6 illustrates a flow diagram of an exemplary, non-limiting computer-implemented method 600 that can facilitate evaluation and knowledge base generation of quantum circuit optimization routines according to one or more embodiments described herein. Repeated descriptions of similar elements and / or processes utilized in each embodiment are omitted for the sake of brevity.

[0060] At 602, computer-implemented method 600 may include running, by a system operatively coupled to a processor (e.g., processor 106) (e.g., via routine evaluation system 102 or compilation component 108, or both), different quantum circuit optimization sequences on multiple copies of a quantum circuit simultaneously. For example, as described above with reference to the exemplary embodiment illustrated in FIG. 5, compilation component 108 may use a remote server that may utilize applications or software hook processes, or both, to run different quantum circuit optimization sequences simultaneously using compiler runtime "A" 506a, compiler runtime "B" 506b, or compiler runtime "N" 506N, or a combination thereof, on multiple copies of raw quantum circuit 502 (e.g., for a first copy of raw quantum circuit 502a, a second copy of raw quantum circuit 502b, and an Nth copy of raw quantum circuit 502N).

[0061] At 604, the computer-implemented method 600 may include identifying, by the system (e.g., via the routine evaluation system 102 or the identification component 110, or both), at least one of the different quantum circuit optimization sequences that produces an output quantum circuit that includes the defined criteria. For example, as described above with reference to the exemplary embodiment illustrated in FIG. 5, based on the generation of the above-described multiple output quantum circuits, each having a compilation metric 512, the identification component 110 may determine whether compiler runtime “A” 506a, compiler runtime “B” 506b, or compiler runtime “N” 506N, or a combination thereof, produced an output quantum circuit having one or more of the above-described defined quantum circuit-based metrics, or one or more of the defined pulse-based metrics, or a combination thereof.

[0062] 7 illustrates a flow diagram of an exemplary, non-limiting computer-implemented method 700 that can facilitate evaluation and knowledge base generation of quantum circuit optimization routines according to one or more embodiments described herein. Repeated descriptions of similar elements and / or processes utilized in each embodiment are omitted for the sake of brevity.

[0063] At 702, the computer-implemented method 700 may include generating, by a system operably coupled to a processor (e.g., processor 106) (e.g., via the routine evaluation system 102 or the knowledge base component 302, or both), a knowledge base having multiple output quantum circuits generated from simultaneously running different quantum circuit optimization sequences on multiple copies of the quantum circuit. For example, as described above with reference to the exemplary embodiment shown in FIG. 5, the knowledge base component 302 may generate (e.g., as described above with reference to the exemplary embodiments shown in FIGS. 1, 2, 3, and 4) various raw quantum circuits 502 that may be input to the compilation component 108 by different local and / or cloud-based entities 516 implementing the system 500, various quantum circuit optimization sequences that may use compiler runtime "A" 506a, compiler runtime "B" 506b, or compiler runtime "N" 506N, or combinations thereof, to respectively execute copies of such various raw quantum circuits 502 simultaneously, various output quantum circuits with various compilation metrics 512, or a knowledge base with various compilation metrics 512, or combinations thereof.

[0064] At 704, the computer-implemented method 700 may include utilizing, by the system (e.g., via the routine evaluation system 102 or the recommendation component 402, or both), the trained model to recommend at least one of different quantum circuit optimization sequences to generate an output quantum circuit that includes the defined criteria. For example, as described above with reference to the exemplary embodiment illustrated in FIG. 5, the recommendation component 402 may utilize the trained ML or AI model, or both, trained (e.g., using the above-described knowledge base that may be generated by the knowledge base component 302) to recommend a compilation strategy recommendation 514. In this example, the compilation strategy recommendation 514, utilized by compiler runtime “A” 506 a, compiler runtime “B” 506 b, or compiler runtime “N” 506 N, or a combination thereof, may include at least one of different quantum circuit optimization sequences that may generate an output quantum circuit having compilation metrics 512.

[0065] The routine evaluation system 102 may be associated with various technologies, for example, the routine evaluation system 102 may be associated with quantum computing technology, quantum circuit technology, quantum circuit optimization technology, quantum hardware and / or software technology, quantum algorithm technology, machine learning technology, artificial intelligence technology, cloud computing technology, knowledge-based technology, or other technologies, or a combination thereof.

[0066] The routine evaluation system 102 may provide technical improvements to systems, devices, components, operational steps, or process steps, or combinations thereof, associated with the various techniques identified above. For example, the routine evaluation system 102 may simultaneously run different quantum circuit optimization sequences on multiple copies of a quantum circuit, or identify at least one of the different quantum circuit optimization sequences that produces an output quantum circuit that includes defined criteria, or both. In this example, to simultaneously run different quantum circuit optimization sequences on multiple copies of a quantum circuit, the routine evaluation system 102 may use the above-mentioned application and / or software hook process that enables the routine evaluation system 102 (e.g., via the compilation component 108) to send the raw quantum circuit to the above-mentioned external computing resource (e.g., a remote server) that can generate and / or execute identical copies (e.g., instances) of the raw quantum circuit through each different optimization sequence (e.g., through each different quantum circuit optimization routine or compiler, or both) (e.g., simultaneously, in parallel). In this example, by utilizing such external computing resources to simultaneously run different quantum circuit optimization sequences on multiple copies of a raw quantum circuit to generate multiple output quantum circuits, each including different defined criteria, routine evaluation system 102 may thereby reduce at least one of the processing workloads of a processor (e.g., processor 106), or the time it takes to identify a quantum circuit optimization sequence that produces an output quantum circuit that includes the particular defined criteria, or both. In another example, routine evaluation system 102 may further provide (e.g., via knowledge base component 302) a knowledge base that can be used to train an ML model or an AI model or both (e.g., an ML algorithm or an AI algorithm or both) to identify which quantum circuit optimization sequence performs relatively best for a given input raw quantum circuit.

[0067] Routine evaluation system 102 may provide technical improvements to a processing unit (e.g., processor 106, a quantum processor, or another processor, or a combination thereof) associated with routine evaluation system 102. For example, as described above, by utilizing such external computing resources to simultaneously run different quantum circuit optimization sequences on multiple copies of an unprocessed quantum circuit to generate multiple output quantum circuits, each including a different defined criterion, routine evaluation system 102 may thereby reduce the processing workload of a processor (e.g., processor 106) it takes to identify quantum circuit optimization sequences that produce output quantum circuits that include particular defined criteria. In this example, by reducing the processing workload of such a processor (e.g., processor 106), routine evaluation system 102 may thereby facilitate improvements in the performance or efficiency, or both, of such processor, as well as a reduction in the computational cost of such processor.

[0068] A practical application of the routine evaluation system 102 is that it may be implemented using a classical computing device (e.g., a classical processor or a classical computer, or both) to identify quantum circuit optimization sequences (e.g., routines or compilers, or both) that can produce quantum circuits that include desired or target criteria, or both. Such quantum circuits may then be executed on the quantum computing device (e.g., a quantum processor or a quantum computer, or both) to compute one or more solutions (e.g., heuristics) to various problems ranging in complexity (e.g., estimation problems, optimization problems, or other problems, or combinations thereof) in various domains (e.g., finance, chemistry, medicine, or other domains, or combinations thereof). For example, a practical application of the routine evaluation system 102 is that it may be implemented using a classical computing device (e.g., a classical processor or a classical computer, or both) to identify quantum circuit optimization sequences (e.g., routines or compilers, or both) that can produce quantum circuits that include desired or target criteria, or both. Here, such quantum circuits may be executed on a quantum computing device (e.g., a quantum processor or a quantum computer, or both) to compute one or more solutions (e.g., heuristics) to estimation and / or optimization problems in the areas of chemistry, medicine, or finance, or a combination thereof, where such solutions may be used by engineers to, for example, develop new chemical compounds, new drugs, or new option premiums, or a combination thereof.

[0069] It should be appreciated that the routine evaluation system 102 provides a novel approach driven by relatively new quantum computing technology. For example, the routine evaluation system 102 provides a novel approach to identifying quantum circuit optimization sequences (e.g., routines and / or compilers) that can generate quantum circuits that include desired and / or target criteria.

[0070] The routine evaluation system 102 may utilize hardware or software to solve problems that are highly technical in nature, not abstract, and cannot be performed by a human as a set of mental activities. In some embodiments, one or more of the processes described herein may be executed by one or more specialized computers (e.g., specialized processing units, specialized classical computers, specialized quantum computers, or other types of specialized computers, or combinations thereof) to perform defined tasks related to the various technologies identified above. The routine evaluation system 102, or components thereof, or both, may be utilized to solve new problems that arise through the use of the above-described technological advancements, quantum computing systems, cloud computing systems, computer architectures, or other technologies, or combinations thereof.

[0071] It should be appreciated that the routine evaluation system 102 can utilize various combinations of electrical components, mechanical components, and circuitry that cannot be replicated in or performed by the human mind, because various operations that may be performed by the routine evaluation system 102, or its components, or both, described herein are operations beyond the capabilities of the human mind. For example, the amount of data processed, the speed at which such data is processed, or the types of data processed by the routine evaluation system 102 over a particular period of time may be greater, faster, or different from the amount, speed, or types of data that can be processed by the human mind over the same period of time.

[0072] According to various embodiments, the routine evaluation system 102 may also be fully operational to perform one or more other functions (e.g., fully powered on, fully running, or another function, or a combination thereof) while also performing the various operations described herein. It should be understood that performing such multiple simultaneous operations exceeds the capabilities of the human mind. It should also be understood that the routine evaluation system 102 may include information that is impossible to manually obtain by an entity such as a human user. For example, the type, amount, or variety of information, or combinations thereof, included in the routine evaluation system 102, compilation component 108, identification component 110, storage component 202, knowledge base component 302, or recommendation component 402, or combinations thereof, may be more complex than information manually obtained by a human user.

[0073] In some embodiments, the routine evaluation system 102 may be associated with a cloud computing environment. For example, the routine evaluation system 102 may be associated with the cloud computing environment 950 described below with reference to Figure 9, or with one or more functional abstraction layers (e.g., hardware and software layer 1060, virtualization layer 1070, management layer 1080, or workload layer 1090, or a combination thereof) described below with reference to Figure 10, or both.

[0074] The routine evaluation system 102 or its components (e.g., the compilation component 108, the identification component 110, the storage component 202, the knowledge base component 302, the recommendation component 402, or another component or combination thereof) or both may utilize one or more computing resources of a cloud computing environment 950 described below with reference to FIG. 9, or one or more functional abstraction layers (e.g., quantum software) described below with reference to FIG. 10, or both to perform one or more operations according to one or more embodiments of the present disclosure described herein. For example, cloud computing environment 950, or such one or more functional abstraction layers, or both, may include one or more classical computing devices (e.g., a classical computer, a classical processor, a virtual machine, a server, or another classical computing device, or a combination thereof), quantum hardware, or quantum software (e.g., a quantum computing device, a quantum computer, a quantum processor, a quantum circuit simulation software, a superconducting circuit, and / or other quantum hardware, and / or quantum software), or a combination thereof, that may be utilized by routine evaluation system 102, or components thereof, to perform one or more operations according to one or more embodiments of the present disclosure described herein. For example, the routine evaluation system 102 or components thereof, or both, may utilize such one or more classical and / or quantum computing resources to perform one or more classical and / or quantum: arithmetic functions, operations, or equations, or combinations thereof; computing or processing or both scripts; routines, or instructions, or both; algorithms; models (e.g., artificial intelligence (AI) models, machine learning (ML) models, or other types of models, or combinations thereof); or other operations or combinations thereof, according to one or more embodiments of the present disclosure described herein.

[0075] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the teachings described herein is not limited to cloud computing environments. Rather, embodiments of the present invention may be implemented in conjunction with any other type of computing environment now known or later developed.

[0076] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a service provider. The cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0077] The characteristics are as follows:

[0078] On-Demand Self-Service: Cloud consumers can unilaterally provision computing capacity, such as server time and network storage, automatically as needed, without requiring human interaction with the service provider.

[0079] Wide network access: Functionality is available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin- or thick-client platforms (eg, cell phones, laptops, and PDAs).

[0080] Resource Pool: A provider's computing resources are pooled and serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically allocated and reallocated according to demand. Although consumers generally have no control or knowledge of the exact location of the resources provided, there is an implication of location independence in that they may be able to specify location at a higher level of abstraction (e.g., country, state, or data center).

[0081] Rapid Elasticity: Capabilities can be provisioned quickly and elastically, in some cases automatically, to quickly scale out, quickly release, and quickly scale in. To the consumer, the capabilities available for provisioning often appear infinite, and any quantity can be purchased at any time.

[0082] Measured Services: Cloud systems automatically control and optimize resource usage by utilizing metering capabilities at a specific level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services used.

[0083] The service model is as follows:

[0084] Software as a Service (SaaS): The consumer is offered the ability to use a provider's applications running on a cloud infrastructure. The applications are accessible from a variety of client devices through a thin-client interface such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or individual application functions, with the possible exception of limited user-specific application configuration settings.

[0085] Platform as a Service (PaaS): The ability offered to consumers is to deploy applications they create or acquire using programming languages and tools supported by the provider onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but does have control over the deployed applications and potentially the application hosting environment configuration.

[0086] Infrastructure as a Service (IaaS): The ability provided to consumers is to provision processing, storage, network, and other basic computing resources, on which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but does have control over the operating system, storage, deployed applications, and possibly limited control over the selection of network components (e.g., host firewalls).

[0087] The deployment model is as follows:

[0088] Private Cloud: Cloud infrastructure operated solely for an organization. A private cloud may be managed by the organization or a third party and may exist on-premise or off-premise.

[0089] Community Cloud: Cloud infrastructure is shared by multiple organizations to support a specific community with shared interests (e.g., mission, security requirements, policy and compliance considerations). A community cloud may be managed by the organizations or a third party and may exist on-premises or off-premises.

[0090] Public Cloud: Cloud infrastructure is made available to the general public or large industry groups and is owned by organizations that sell cloud services.

[0091] Hybrid Cloud: A cloud infrastructure is a composite of two or more clouds (private, community, or public) that remain distinct entities but are joined by standard or proprietary technologies that allow for data portability and application portability (e.g., cloud bursting for load balancing between clouds).

[0092] Cloud computing environments are service-oriented, focusing on statelessness, low coupling, modularity, and semantic interoperability. At the core of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0093] For simplicity of explanation, computer-implemented methods are illustrated and described as a series of actions. It is to be understood and appreciated that the subject innovation is not limited by the actions shown, or the order or combination of actions. For example, actions may occur in various orders and / or simultaneously, along with other actions not shown and described herein. Moreover, not all actions shown may be required to implement a computer-implemented method in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that a computer-implemented method can alternatively be represented as a series of interrelated states via a state diagram or events. Additionally, it should be further appreciated that the computer-implemented methods disclosed hereinafter and throughout this specification can be stored on an article of manufacture to facilitate transporting and transferring such computer-implemented methods to a computer. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0094] To provide a context for various aspects of the disclosed subject matter, Figure 8 and the following discussion are intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented. Figure 8 illustrates a block diagram of an exemplary, non-limiting operating environment in which one or more embodiments described herein may be facilitated. Repeated descriptions of similar elements utilized in other embodiments described herein are omitted for the sake of brevity.

[0095] 8, a suitable operating environment 800 for implementing various aspects of the present disclosure may also include a computer 812. The computer 812 may also include a processing unit 814, a system memory 816, and a system bus 818. The system bus 818 couples system components including, but not limited to, the system memory 816 to the processing unit 814. The processing unit 814 may be any of a variety of available processors. Dual microprocessors and other multi-processor architectures may also be utilized as the processing unit 814. The system bus 818 can be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus or external bus, or a local bus, or combinations thereof, using any of a variety of available bus architectures, including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Enhanced ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (registered trademark) (IEEE 1394), Small Computer System Interface (SCSI).

[0096] The system memory 816 may also include volatile memory 820 and nonvolatile memory 822. A basic input / output system (BIOS), containing the basic routines for transferring information between elements within the computer 812, such as during start-up, is stored in the nonvolatile memory 822. The computer 812 may also include removable and non-removable, volatile and non-volatile computer storage media. FIG. 8 illustrates, for example, disk storage 824. Disk storage 824 may also include devices such as, but not limited to, a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. Disk storage 824 may also include storage media separately from or in combination with other storage media. A removable or non-removable interface, such as interface 826, is typically used to facilitate connection of the disk storage 824 to the system bus 818. FIG. 8 also illustrates software that acts as an intermediary between a user and the basic computer resources described in the preferred operating environment 800. Such software may also include, for example, an operating system 828. Operating system 828 , which can be stored on disk storage 824 , acts to control and allocate resources of the computer 812 .

[0097] System applications 830 take advantage of the management of resources by operating system 828 through, for example, program modules 832 and program data 834 stored either in system memory 816 or on disk storage 824. It should be understood that the present disclosure may be implemented with various operating systems or combinations of operating systems. Users enter commands or information into computer 812 through input devices 836. Input devices 836 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, gamepad, satellite dish, scanner, television tuner card, digital camera, digital video camera, webcam, and the like. These and other input devices connect to processing unit 814 through system bus 818 via interface ports 838. Interface ports 838 include, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). Output devices 840 use several of the same types of ports as input devices 836. Thus, for example, a USB port may be used to provide input to computer 812 and to output information from computer 812 to output device 840. Output adapter 842 is provided to illustrate that there are some output devices 840, such as monitors, speakers, and printers, among other output devices 840, that require special adapters. Output adapters 842 include, by way of example and not limitation, video and sound cards that provide a means of connection between output device 840 and system bus 818. It should be noted that other devices or systems of devices, or combinations thereof, may provide both input and output capabilities, such as remote computer(s) 844.

[0098] The computer 812 may operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 844. The remote computer 844 may be a computer, a server, a router, a network PC, a workstation, a microprocessor-based device, a peer device, or other common network node, and may typically include many or all of the elements described relative to the computer 812. For purposes of simplicity, only a memory storage device 846 is shown with the remote computer 844. The remote computer 844 is logically connected to the computer 812 through a network interface 848 and is then physically connected via a communication connection 850. The network interface 848 encompasses a wired and / or wireless communication network, such as a local area network (LAN), a wide area network (WAN), a cellular network, or another wired and / or wireless communication network, or a combination thereof. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and its variations, packet-switched networks, and Digital Subscriber Lines (DSL). Communications connection(s) 850 refer to the hardware / software utilized to connect network interface 848 to system bus 818. For clarity of illustration, communications connection(s) 850 are shown internal to computer 812, but could also be external to computer 812. The hardware / software for connecting to network interface 848 could also include, by way of example only, internal and external technologies such as ordinary telephone-grade modems, cable modems, modems including DSL modems, ISDN adapters, Ethernet cards, etc.

[0099] Referring now to FIG. 9 , an exemplary cloud computing environment 950 is illustrated. As shown, the cloud computing environment 950 includes one or more cloud computing nodes 910 with which local computing devices used by cloud consumers, such as a personal digital assistant (PDA) or cellular phone 954A, a desktop computer 954B, a laptop computer 954C, or an automobile computer system 954N, or combinations thereof, may communicate. Although not shown in FIG. 9 , the cloud computing nodes 910 may further include a quantum platform (e.g., a quantum computer, quantum hardware, quantum software, or another quantum platform, or combinations thereof) with which the local computing devices used by the cloud consumers may communicate. The nodes 910 may communicate with each other. The nodes may be physically or virtually grouped (not shown) in one or more networks, such as a private cloud, a community cloud, a public cloud, or a hybrid cloud, or combinations thereof, as described above. This enables the cloud computing environment 950 to provide infrastructure, platform, or software, or combinations thereof, as a service without the cloud consumer having to maintain resources on their local computing devices. It should be understood that the types of computing devices 954A-N illustrated in FIG. 9 are intended to be exemplary only, and that computing node 910 and cloud computing environment 950 can communicate with any type of computerized device through any type of network or network-addressable connection (e.g., using a web browser), or both.

[0100] 10, a set of functional abstraction layers provided by cloud computing environment 950 (FIG. 9) is shown. It should be understood in advance that the components, layers, and functions shown in FIG. 10 are intended to be illustrative only, and that embodiments of the invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0101] Hardware and software layer 1060 includes hardware and software components. Examples of hardware components include mainframe 1061, RISC (minimum instruction set computer) architecture-based servers 1062, servers 1063, blade servers 1064, storage devices 1065, and networks and network components 1066. In some embodiments, software components include network application server software 1067, database software 1068, Quantum Platform routing software (not shown in FIG. 10), or Quantum software (not shown in FIG. 10), or a combination thereof.

[0102] The virtualization layer 1070 provides an abstraction layer from which the following example virtual entities can be provided: virtual servers 1071, virtual storage 1072, virtual networks including virtual private networks 1073, virtual applications and operating systems 1074, and virtual clients 1075.

[0103] In one example, management layer 1080 may provide the functions described below. Resource provisioning 1081 provides dynamic procurement of computing resources and other resources utilized to perform tasks within the cloud computing environment. Metering and pricing 1082 provides cost tracking as resources are used within the cloud computing environment and charging or billing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification of cloud consumers and protection for tasks, data, and other resources. User portal 1083 provides access to the cloud computing environment for consumers and system administrators. Service level management 1084 provides cloud computing resource allocation and management to ensure required service levels are met. Service level agreement (SLA) planning and fulfillment 1085 provides advance arrangements and procurement of cloud computing resources in anticipation of future requirements according to SLAs.

[0104] Workload tier 1090 provides examples of functionality for which a cloud computing environment may be utilized. Non-limiting examples of workloads and functions that may be provided from this tier include mapping and navigation 1091, software development and lifecycle management 1092, virtual classroom instruction delivery 1093, data analytics processing 1094, transaction processing 1095, and routine evaluation software 1096.

[0105] The present invention may be a system, method, apparatus, or computer program product, or combination thereof, at any possible level of technical detail of integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to perform aspects of the present invention. A computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media may also include portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or raised structures in grooves with instructions recorded on them, and any suitable combination of the above. Computer-readable storage media as used herein should not be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagated through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted through wires.

[0106] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device, or may be downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device. The computer-readable program instructions for carrying out operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk®, C++, or the like, or conventional procedural programming languages such as the “C” programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet Service Provider).In some embodiments, to carry out aspects of the present invention, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry.

[0107] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to create a machine. The instructions, executed by the processor of the computer or other programmable data processing apparatus, thereby form means for implementing the function / acts specified in a block or blocks of the flowchart illustrations or block diagrams, or a combination thereof. These computer-readable program instructions can also be stored on a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner. A computer-readable storage medium having instructions stored thereon thereby includes a product including instructions that implement an aspect of the function / acts specified in a block or blocks of the flowchart illustrations or block diagrams, or a combination thereof. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational acts to be performed on the computer, other programmable apparatus, or other device to create a computer-implemented process, whereby the instructions executing on the computer, other programmable apparatus, or other device implement the function / acts specified in a block or blocks of the flowchart or block diagram, or a combination thereof.

[0108] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, depending on the functionality involved, or the blocks may even be executed in the reverse order. In addition, it will be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0109] Although the subject matter has been described above in the general context of computer-executable instructions for a computer program product executing on a computer, or multiple computers, or both, those skilled in the art will recognize that the present disclosure can also be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, or other program modules, or combinations thereof, that perform particular tasks or implement particular abstract data types, or both. Furthermore, those skilled in the art will recognize that the computer-implemented methods of the present invention can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputing devices, mainframe computers, computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronics, etc. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices linked through a communications network. However, some, if not all, aspects of the present disclosure can be practiced on stand-alone computers. In a distributed computing environment, program modules may be located in both local and remote memory storage devices. For example, in one or more embodiments, the computer-executable components may execute from a memory that may include or consist of one or more distributed memory units. As used herein, the terms "memory" and "memory unit" are interchangeable. Furthermore, one or more embodiments described herein may execute code of the computer-executable components in a distributed manner (e.g., multiple processors combining or acting cooperatively to execute code from one or more distributed memory units). As used herein, the term "memory" may encompass a single memory or memory unit in one location, or multiple memories or memory units in one or more locations.

[0110] As used herein, terms such as “component,” “system,” “platform,” and “interface” may refer to and / or include computer-related entities or entities associated with an operating machine having one or more specific functionalities. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer, or combinations thereof. By way of example, both an application running on a server and the server may be a component. One or more components may reside within a process or thread of execution, or both, and a component may be localized on one computer, distributed between two or more computers, or both. In another example, each component may execute from various computer-readable media having various data structures stored thereon. Components may communicate via local or remote processes, or both, such as according to signals comprising one or more data packets (e.g., data from one component interacting with another component in a network such as the Internet, a local system, a distributed system, or other systems via signals, or a combination thereof). As another example, a component may be a device having inherent functionality provided by mechanical parts operated by electrical or electronic circuits operated by software or firmware applications executed by a processor. In such cases, the processor may be internal or external to the device and may execute at least a portion of the software or firmware applications.As yet another example, a component may be a device that provides its inherent functionality without mechanical parts through electronic components, which may include a processor or other means for executing software or firmware that provides at least a portion of the functionality of the electronic component. In some aspects, a component may emulate an electronic component via, for example, a virtual machine in a cloud computing system.

[0111] Additionally, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from context, "X utilizes A or B" is intended to mean any of the natural inclusive permutations. That is, if X utilizes A, X utilizes B, or X utilizes both A and B, then "X utilizes A or B" is satisfied under any of the foregoing examples. Furthermore, the articles "a" and "an," as used in this specification and the accompanying drawings, should generally be construed to mean "one or more" unless otherwise specified or clear from context that the singular is intended. As used herein, the terms "example" and "exemplary," or both, are used to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. Additionally, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0112] The term "processor" as used herein may refer to virtually any computing processing unit or device, including, but not limited to, a single-core processor, a single processor with software multithreading execution capabilities, a multi-core processor, a multi-core processor with software multithreading execution capabilities, a multi-core processor with hardware multithreading technology, a parallel platform, and a parallel platform with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user equipment. A processor may also be implemented as a combination of computing processing units. In this disclosure, terms such as "store," "storage," "data store," "data storage," "database," and substantially any other information storage component associated with the operation and functionality of a component are utilized to refer to a "memory" or a "memory component" entity embodied in a component that includes memory. It should be understood that memory or memory components or combinations thereof described herein may be either volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, which may act as external cache memory, for example. By way of example, and not limitation, RAM is available in many forms, including synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of systems or computer-implemented methods herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0113] The foregoing includes only example systems and computer-implemented methods. Of course, for purposes of describing the present disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present disclosure are possible. Furthermore, to the extent that terms such as "including," "having," "comprising," and the like are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in the same manner as the term "comprising" is interpreted when used as a transitional phrase in the claims.

[0114] The description of various embodiments is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will become apparent to those skilled in the art that do not depart from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, their practical applications or technical improvements over technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. According to this specification, the following items are also disclosed. [Item 1] 1. A system comprising a processor that executes computer-executable components stored in a memory, the computer-executable components comprising: a compilation component that simultaneously executes different quantum circuit optimization sequences on multiple copies of the quantum circuit; an identification component that identifies at least one of the different quantum circuit optimization sequences that generates an output quantum circuit that includes the defined criteria; and A system having: [Item 2] 2. The system of claim 1, wherein the compilation component simultaneously performs the different quantum circuit optimization sequences on the multiple copies of the quantum circuit based on one or more properties of a quantum device capable of executing at least one of the quantum circuit or the output quantum circuit. [Item 3] 3. The system of claim 1, wherein the defined criteria is selected from the group consisting of a defined quantum circuit-based metric and a defined pulse-based metric. [Item 4] 4. The system of claim 1, wherein the compilation component simultaneously executes the different quantum circuit optimization sequences on the multiple copies of the quantum circuit to generate multiple output quantum circuits, each including a different defined criterion, and reduces processing workload associated with identifying a quantum circuit optimization sequence that produces the output quantum circuit including the defined criterion. [Item 5] 5. The system of claim 1, wherein the computer-executable components comprise a storage component that stores multiple output quantum circuits generated from simultaneously executing the different quantum circuit optimization sequences on the multiple copies of the quantum circuit, each of the multiple output quantum circuits further comprising a different defined criterion. [Item 6] executing, by a system operatively coupled to the processor, different quantum circuit optimization sequences simultaneously on multiple copies of the quantum circuit; identifying, by the system, at least one of the different quantum circuit optimization sequences that produces an output quantum circuit that includes a defined criterion; A computer-implemented method comprising: [Item 7] 7. The computer-implemented method of claim 6, further comprising: performing, by the system, the different quantum circuit optimization sequences simultaneously on the multiple copies of the quantum circuit based on one or more properties of a quantum device capable of implementing at least one of the quantum circuit or the output quantum circuit. [Item 8] 8. The computer-implemented method of claim 6 or 7, wherein the defined criteria are selected from the group consisting of a defined quantum circuit-based metric and a defined pulse-based metric. [Item 9] 9. The computer-implemented method of claim 6, further comprising: performing, by the system, the different quantum circuit optimization sequences simultaneously on the multiple copies of the quantum circuit to generate multiple output quantum circuits, each output quantum circuit including a different defined criterion; and reducing the processing workload associated with identifying the quantum circuit optimization sequence that produces the output quantum circuit including the defined criterion. [Item 10] 7. The computer-implemented method of claim 6, further comprising storing, by the system, multiple output quantum circuits generated from simultaneously executing the different quantum circuit optimization sequences on the multiple copies of the quantum circuit, each of the multiple output quantum circuits including a different defined criterion. [Item 11] 1. A computer program comprising program instructions, The program instructions may cause the processor to: simultaneously running different quantum circuit optimization sequences on multiple copies of the quantum circuit; identifying at least one of the different quantum circuit optimization sequences that produces an output quantum circuit that includes the defined criteria; and A computer program executable by the processor to cause the processor to execute the steps of: [Item 12] The program instructions cause the processor to: 12. The computer program of claim 11, further executable by the processor to cause the different quantum circuit optimization sequences to be executed simultaneously on the multiple copies of the quantum circuit based on one or more properties of a quantum device capable of executing at least one of the quantum circuit or the output quantum circuit. [Item 13] 13. The computer program of claim 11, wherein the defined criteria are selected from the group consisting of a defined quantum circuit-based metric and a defined pulse-based metric. [Item 14] The program instructions cause the processor to: simultaneously executing the different quantum circuit optimization sequences on the multiple copies of the quantum circuit to generate multiple output quantum circuits, each including a different defined criterion; and reducing the processing workload associated with identifying the quantum circuit optimization sequences that generate the output quantum circuits including the defined criterion. 14. The computer program of any one of items 11 to 13, further executable by the processor to cause the processor to execute the following: [Item 15] The program instructions cause the processor to: 15. The computer program of any one of claims 11 to 14, further executable by the processor to store a plurality of output quantum circuits generated from simultaneously executing the different quantum circuit optimization sequences on the multiple copies of the quantum circuit, each of the plurality of output quantum circuits comprising a different defined criterion. [Item 16] 1. A system comprising a processor that executes computer-executable components stored in a memory, the computer-executable components comprising: a knowledge base component that generates a knowledge base including multiple output quantum circuits generated from simultaneously executing different quantum circuit optimization sequences on multiple copies of the quantum circuit; a recommendation component that utilizes the trained model to recommend at least one of the different quantum circuit optimization sequences to generate an output quantum circuit that includes the defined criteria; and A system having: [Item 17] The computer-executable components include: Item 17. The system of item 16, further comprising a compilation component that simultaneously executes the different quantum circuit optimization sequences on the multiple copies of the quantum circuit based on one or more properties of a quantum device capable of executing at least one of the quantum circuit or the output quantum circuit. [Item 18] 18. The system of claim 16 or 17, wherein the defined criteria are selected from the group consisting of a defined quantum circuit-based metric and a defined pulse-based metric. [Item 19] 19. The system of any one of items 16 to 18, wherein each of the plurality of output quantum circuits includes a different defined criterion. [Item 20] 20. The system of any one of claims 16 to 19, wherein the recommendation component further utilizes the trained model to rank the at least one of the different quantum circuit optimization sequences based on defined entity criteria. [Item 21] generating, by a system operatively coupled to the processor, a knowledge base including a plurality of output quantum circuits generated from simultaneously executing different quantum circuit optimization sequences on multiple copies of the quantum circuit; utilizing, by the system, the trained model that recommends at least one of the different quantum circuit optimization sequences to generate an output quantum circuit that includes the defined criteria; A computer-implemented method comprising: [Item 22] 22. The computer-implemented method of claim 21, further comprising: executing, by the system, the different quantum circuit optimization sequences simultaneously on the multiple copies of the quantum circuit based on one or more properties of a quantum device capable of implementing at least one of the quantum circuit or the output quantum circuit. [Item 23] 23. The computer-implemented method of claim 21 or 22, wherein the defined criteria are selected from the group consisting of a defined quantum circuit-based metric and a defined pulse-based metric. [Item 24] 24. The computer-implemented method of any one of items 21 to 23, wherein each of the plurality of output quantum circuits includes a different defined criterion. [Item 25] 25. The computer-implemented method of any one of claims 21 to 24, further comprising concurrently utilizing the trained model by the system to rank the at least one of the different quantum circuit optimization sequences based on defined entity criteria.

Claims

1. 1. A system comprising a processor that executes computer-executable components stored in a memory, the computer-executable components comprising: a compilation component that simultaneously executes different quantum circuit optimization sequences on multiple copies of the quantum circuit using compiler runtimes corresponding to each of the multiple copies of the quantum circuit; an identification component that identifies at least one of the different quantum circuit optimization sequences that produces an output quantum circuit that includes a defined criterion, the defined criterion being selected from the group consisting of a defined quantum circuit-based metric and a defined pulse-based metric; A system having:

2. 2. The system of claim 1 , wherein the compilation component simultaneously executes the different quantum circuit optimization sequences on the multiple copies of the quantum circuit using a quantum device capable of executing at least one of the quantum circuit or the output quantum circuit.

3. 3. The system of claim 1, wherein the compilation component simultaneously executes the different quantum circuit optimization sequences on the multiple copies of the quantum circuit to generate multiple output quantum circuits, each output quantum circuit including a different defined criterion, and reduces processing workload associated with identifying a quantum circuit optimization sequence that produces the output quantum circuit including the defined criterion.

4. 4. The system of claim 1, wherein the computer-executable components comprise a storage component that stores multiple output quantum circuits generated from simultaneously executing the different quantum circuit optimization sequences on the multiple copies of the quantum circuit, each of the multiple output quantum circuits further comprising a different defined criterion.

5. executing, by a system operatively coupled to a processor, different quantum circuit optimization sequences simultaneously on multiple copies of the quantum circuit using compiler runtimes corresponding to each of the multiple copies of the quantum circuit; identifying, by the system, at least one of the different quantum circuit optimization sequences that produces an output quantum circuit that includes a defined criterion, the defined criterion being selected from the group consisting of a defined quantum circuit-based metric and a defined pulse-based metric; A computer-implemented method comprising:

6. 6. The computer-implemented method of claim 5, further comprising: executing, by the system, the different quantum circuit optimization sequences simultaneously on the multiple copies of the quantum circuit using a quantum device capable of executing at least one of the quantum circuit or the output quantum circuit.

7. 7. The computer-implemented method of claim 5, further comprising: executing, by the system, the different quantum circuit optimization sequences simultaneously on the multiple copies of the quantum circuit to generate multiple output quantum circuits, each including a different defined criterion; and reducing processing workload associated with identifying a quantum circuit optimization sequence that produces the output quantum circuit that includes the defined criterion.

8. 6. The computer-implemented method of claim 5, further comprising storing, by the system, multiple output quantum circuits generated from simultaneously executing the different quantum circuit optimization sequences on the multiple copies of the quantum circuit, each of the multiple output quantum circuits comprising a different defined criterion.

9. 1. A computer program comprising program instructions, The program instructions may cause a processor to: simultaneously executing different quantum circuit optimization sequences on multiple copies of the quantum circuit using compiler runtimes corresponding to each of the multiple copies of the quantum circuit; identifying at least one of the different quantum circuit optimization sequences that produces an output quantum circuit that includes a defined criterion, the defined criterion being selected from the group consisting of a defined quantum circuit-based metric and a defined pulse-based metric; a computer program executable by the processor to cause the processor to execute the steps of:

10. The program instructions may cause the processor to:

10. The computer program of claim 9, further executable by the processor to cause the different quantum circuit optimization sequences to be executed simultaneously on the multiple copies of the quantum circuit using a quantum device capable of executing at least one of the quantum circuit or the output quantum circuit.

11. The program instructions may cause the processor to: simultaneously executing the different quantum circuit optimization sequences on the multiple copies of the quantum circuit to generate multiple output quantum circuits, each including a different defined criterion; and reducing processing workload associated with identifying quantum circuit optimization sequences that produce the output quantum circuits that include the defined criterion.

11. A computer program product according to claim 9 or 10, further executable by the processor to cause the processor to execute:

12. The program instructions may cause the processor to:

12. The computer program of claim 9, further executable by the processor to cause storing of a plurality of output quantum circuits produced from simultaneously executing the different quantum circuit optimization sequences on the plurality of copies of the quantum circuit, each of the plurality of output quantum circuits comprising a different defined criterion.

13. 1. A system comprising a processor that executes computer-executable components stored in a memory, the computer-executable components comprising: a knowledge base component that generates a knowledge base including a plurality of output quantum circuits generated from simultaneously executing different quantum circuit optimization sequences on the plurality of copies of the quantum circuit using a compiler runtime corresponding to each of the plurality of copies of the quantum circuit; a recommendation component that utilizes a model trained using the knowledge base to recommend at least one quantum circuit optimization sequence among different quantum circuit optimization sequences to recommend at least one quantum circuit optimization sequence for generating an output quantum circuit that includes defined criteria, the defined criteria being selected from the group consisting of a defined quantum circuit-based metric and a defined pulse-based metric; and A system having:

14. The computer-executable components include:

14. The system of claim 13, further comprising a compilation component that executes the different quantum circuit optimization sequences simultaneously on the multiple copies of the quantum circuit using a quantum device capable of executing at least one of the quantum circuit or the output quantum circuit.

15. 15. The system of claim 13 or 14, wherein each of the plurality of output quantum circuits includes a different defined criterion.

16. 16. The system of claim 13, wherein the recommendation component further utilizes the trained model to rank the at least one of the different quantum circuit optimization sequences based on the defined criteria defined by an entity.

17. generating, by a system operatively coupled to a processor, a knowledge base including a plurality of output quantum circuits generated from simultaneously executing different quantum circuit optimization sequences on a plurality of copies of the quantum circuit using a compiler runtime corresponding to each of the plurality of copies of the quantum circuit; recommending, by the system, at least one quantum circuit optimization sequence for generating an output quantum circuit comprising defined criteria, using a model trained using the knowledge base and which recommends at least one quantum circuit optimization sequence among different quantum circuit optimization sequences, the defined criteria being selected from the group consisting of a defined quantum circuit-based metric and a defined pulse-based metric; A computer-implemented method comprising:

18. 20. The computer-implemented method of claim 17, further comprising: executing, by the system, the different quantum circuit optimization sequences simultaneously on the multiple copies of the quantum circuit using a quantum device capable of executing at least one of the quantum circuit or the output quantum circuit.

19. 19. The computer-implemented method of claim 17 or 18, wherein each of the plurality of output quantum circuits includes a different defined criterion.

20. 20. The computer-implemented method of claim 17, further comprising concurrently utilizing, by the system, the trained models defined by an entity to rank the at least one of the different quantum circuit optimization sequences based on the defined criteria.

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