Multilayer ceramic capacitor, circuit module, and method for manufacturing the circuit module

Abstract

The present invention provides a multilayer ceramic capacitor which is able to be formed thinner when mounted to a circuit module without being decreased in the flexural strength as a component. This multilayer ceramic capacitor 1 is provided with: a multilayer body 10 which is obtained by staking a plurality of dielectric layers 20 that contain a ceramic material and a plurality of internal electrode layers 30; and two pairs of external electrodes 40 which are respectively arranged on two main surfaces TS1, TS2 of the multilayer body 10. The multilayer body 10 has: a first capacitor unit which comprises some internal electrode layers 30 among the plurality of internal electrode layers 30; and a second capacitor unit which comprises the other internal electrode layers 30 among the plurality of internal electrode layers 30. The some internal electrode layers 30 in the first capacitor unit are connected to one pair of external electrodes 40 among the two pairs of external electrodes 40; and the other internal electrode layers 30 in the second capacitor unit are connected to the other pair of external electrodes 40 among the two pairs of external electrodes 40.

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor, a circuit module using the same, and a method for manufacturing the circuit module. [Background technology]

[0002] Patent Document 1 discloses a multilayer ceramic capacitor. This multilayer ceramic capacitor includes a laminate in which a plurality of dielectric layers containing a ceramic material and a plurality of internal electrode layers are stacked, and external electrodes provided on end faces of the laminate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-76582 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a demand for thinner circuit modules in which electronic circuit components including such multilayer ceramic capacitors are mounted on a circuit board. Accordingly, there is also a demand for thinner multilayer ceramic capacitors. However, because the dielectric layers and internal electrode layers that constitute a multilayer ceramic capacitor are extremely thin, reducing the thickness of a multilayer ceramic capacitor, i.e., reducing the number of dielectric layers and internal electrode layers, weakens its flexural strength and makes it difficult to handle.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor that can be made thinner when mounted on a circuit module without reducing the component's flexural strength, a circuit module using the same, and a method for manufacturing the circuit module. [Means for solving the problem]

[0006] The multilayer ceramic capacitor according to the present invention is a laminate including a plurality of dielectric layers containing a ceramic material and a plurality of internal electrode layers stacked together, the laminate having two main surfaces opposing each other in a thickness direction, two side surfaces opposing each other in a width direction intersecting the thickness direction, and two end faces opposing each other in a length direction intersecting the thickness direction and the width direction, and two external electrode pairs arranged on each of the two main surfaces of the laminate. The laminate has a first capacitance section including some of the internal electrode layers, with adjacent internal electrode layers of the some internal electrode layers facing each other, and a second capacitance section including other internal electrode layers of the plurality of internal electrode layers other than the some internal electrode layers, with adjacent internal electrode layers of the other internal electrode layers facing each other. The some internal electrode layers in the first capacitance section are connected to one of the two external electrode pairs, and the other internal electrode layers in the second capacitance section are connected to the other external electrode pair.

[0007] A circuit module according to the present invention is a circuit module in which an electronic circuit component is mounted on a circuit board, and includes the circuit board, the multilayer ceramic capacitor as the electronic circuit component mounted on the circuit board, and a resin molding member arranged around the multilayer ceramic capacitor. The multilayer ceramic capacitor has a portion removed in the thickness direction to comprise either the first capacitance portion or the second capacitance portion, and the surface roughness of the main surface of the multilayer ceramic capacitor opposite the circuit board is greater than the surface roughness of the laminate of the multilayer ceramic capacitor facing the resin molding member arranged around the multilayer ceramic capacitor.

[0008] The method for manufacturing a circuit module according to the present invention is a method for manufacturing the above-mentioned circuit module, which comprises mounting the multilayer ceramic capacitor, which is the electronic circuit component, on the circuit board, filling the periphery of the multilayer ceramic capacitor with the resin molding material, and polishing the multilayer ceramic capacitor and the resin molding material in the thickness direction. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can be thinned when mounted on a circuit module without reducing the flexural strength of the component. Furthermore, according to the present invention, it is possible to provide a circuit module that can be thinned using the multilayer ceramic capacitor, and a method for manufacturing the circuit module. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention; [Figure 2] 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. [Figure 3A] 3 is a cross-sectional view taken along line IIIA-IIIA of the multilayer ceramic capacitor shown in FIG. 2. [Figure 3B] 3 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 2 taken along line IIIB-IIIB. [Figure 4] FIG. 3C is a perspective view showing an internal electrode layer in the multilayer ceramic capacitor shown in FIGS. 1 to 3B. [Figure 5A] 1 is a cross-sectional view showing an example of a circuit module according to an embodiment of the present invention. [Figure 5B] 5B is a side view showing the multilayer ceramic capacitor in the circuit module shown in FIG. 5A after polishing. FIG. [Figure 5C] 5B is a perspective view showing a multilayer ceramic capacitor in the circuit module shown in FIG. 5A after polishing. [Figure 6A] 5B is a cross-sectional view showing the circuit module after polishing in the manufacturing process of the circuit module shown in FIG. 5A. FIG. [Figure 6B] 6B is a side view showing a multilayer ceramic capacitor before polishing in the circuit module before polishing shown in FIG. 6A. FIG. [Figure 6C] 6B is a perspective view showing a multilayer ceramic capacitor before polishing in the circuit module before polishing shown in FIG. 6A. FIG. [Figure 7]FIG. 10 is a perspective view showing a multilayer ceramic capacitor according to a modified example of the present embodiment. [Figure 8] 8 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 7 taken along line VIII-VIII. [Figure 9A] 9 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 8 taken along line IXA-IXA. [Figure 9B] 9 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 8 taken along line IXB-IXB. [Figure 10] FIG. 9C is a perspective view showing an internal electrode layer in the multilayer ceramic capacitor shown in FIGS. 7 to 9B. [Figure 11] FIG. 10 is a perspective view showing a multilayer ceramic capacitor according to a modified example of the present embodiment. [Figure 12] 12 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 11 taken along line XII-XII. [Figure 13] 13 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 11 taken along line XIII-XIII. [Figure 14] FIG. 14 is a perspective view showing an internal electrode layer in the multilayer ceramic capacitor shown in FIGS. DETAILED DESCRIPTION OF THE INVENTION

[0011] An example of an embodiment of the present invention will be described below with reference to the accompanying drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0012] (multilayer ceramic capacitors) Fig. 1 is a perspective view showing a multilayer ceramic capacitor according to this embodiment, and Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line II-II. Fig. 3A is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 2 taken along line IIIA-IIIA, and Fig. 3B is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 2 taken along line IIIB-IIIB. The multilayer ceramic capacitor 1 shown in Figs. 1 to 3B includes a laminate 10 and two external electrode pairs 40. Each of the external electrode pairs 40 includes a first external electrode 41 and a second external electrode 42.

[0013] 1 to 3B show an XYZ Cartesian coordinate system. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the thickness direction T of the multilayer ceramic capacitor 1 and the laminate 10. Therefore, the cross section shown in FIG. 2 is also referred to as a WT cross section, and the cross sections shown in FIGS. 3A and 3B are also referred to as an LT cross section. Note that the length direction L, the width direction W, and the thickness direction T do not necessarily have to be orthogonal to each other, and may intersect each other.

[0014] FIG. 4 is a perspective view showing the internal electrode layers in the multilayer ceramic capacitor shown in FIGS. 1 to 3B, and FIG. 1 shows the internal electrode layers and one of the external electrode pair shown in FIG. 4 in a see-through manner.

[0015] The laminate 10 has a substantially rectangular parallelepiped shape and has a first main surface TS1 and a second main surface TS2 that face each other in the thickness direction T, a first side surface WS1 and a second side surface WS2 that face each other in the width direction W, and a first end surface LS1 and a second end surface LS2 that face each other in the length direction L. It is preferable that the corners and ridges of the laminate 10 are rounded. The corners are the portions where three faces of the laminate 10 intersect, and the ridges are the portions where two faces of the laminate 10 intersect.

[0016] 2, 3A, and 3B, the laminate 10 has a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked in the width direction W. As a result, the laminate 10 has, in the width direction W, i.e., the stacking direction, an inner layer portion 100 and a first outer layer portion 101 and a second outer layer portion 102 arranged to sandwich the inner layer portion 100.

[0017] The laminate 10 also has a first capacitive portion 110, a second capacitive portion 120, and a non-capacitive portion 130 in the thickness direction T. The first capacitive portion 110 is disposed on the first main surface TS1 side of the laminate 10, and the second capacitive portion 120 is disposed on the second main surface TS2 side of the laminate 10. The non-capacitive portion 130 is located between the first capacitive portion 110 and the second capacitive portion 120.

[0018] The inner layer portion 100 includes some of the dielectric layers 20 and some of the internal electrode layers 30. More specifically, the first capacitance portion 110 in the inner layer portion 100 includes some of the dielectric layers 20 and some of the internal electrode layers 30. The second capacitance portion 120 in the inner layer portion 100 includes some of the dielectric layers 20 and some of the internal electrode layers 30 other than the portion for the first capacitance portion 110. In the first capacitance portion 110 and the second capacitance portion 120, adjacent internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The first capacitance portion 110 and the second capacitance portion 120 are portions that generate capacitance and essentially function as capacitors. On the other hand, the non-capacitance portion 130 in the inner layer portion 100 does not include an internal electrode layer 30 but includes multiple dielectric layers 20.

[0019] The first outer layer portion 101 is disposed on the first side surface WS1 side of the laminate 10, and the second outer layer portion 102 is disposed on the second side surface WS2 side of the laminate 10. More specifically, the first outer layer portion 101 is disposed between the first side surface WS1 and an internal electrode layer 30 of the multiple internal electrode layers 30 that is closest to the first side surface WS1, and the second outer layer portion 102 is disposed between the second side surface WS2 and an internal electrode layer 30 of the multiple internal electrode layers 30 that is closest to the second side surface WS2. The first outer layer portion 101 and the second outer layer portion 102 do not include the internal electrode layer 30, but each include a portion of the multiple dielectric layers 20 other than the portion for the internal layer portion 100. The first outer layer portion 101 and the second outer layer portion 102 are portions of the internal layer portion 100 that function as protective layers for the first capacitive portion 110 and the second capacitive portion 120.

[0020] The material of the dielectric layer 20 may be a dielectric ceramic containing, for example, BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component. The material of the dielectric layer 20 may also contain a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound.

[0021] The thickness of the dielectric layers 20 is not particularly limited, but is preferably, for example, 0.4 μm or more and 2.0 μm or less. The number of dielectric layers 20 is not particularly limited, but is preferably, for example, 50 or more and 450 or less. The number of dielectric layers 20 is the total number of the dielectric layers in the inner layer portion and the dielectric layers in the outer layer portion.

[0022] 2 to 4, each of the first capacitive section 110 and the second capacitive section 120 includes a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32 as the plurality of internal electrode layers 30. The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312, and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322.

[0023] In the first capacitance portion 110, the opposing electrode portion 311 and the opposing electrode portion 321 face each other across the dielectric layer 20 in the stacking direction of the laminate 10, i.e., the width direction W. The shapes of the opposing electrode portion 311 and the opposing electrode portion 321 are not particularly limited and may be, for example, approximately rectangular. The opposing electrode portion 311 and the opposing electrode portion 321 are portions that generate electrostatic capacitance and essentially function as a capacitor.

[0024] In the first capacitive section 110, the extraction electrode section 312 extends from a portion of the counter electrode section 311 on the first end face LS1 side of the laminate 10 toward the first main surface TS1 of the laminate 10 and is exposed at the first main surface TS1. The extraction electrode section 322 extends from a portion of the counter electrode section 321 on the second end face LS2 side of the laminate 10 toward the first main surface TS1 of the laminate 10 and is exposed at the first main surface TS1. The shapes of the extraction electrode section 312 and the extraction electrode section 322 are not particularly limited and may be, for example, approximately rectangular.

[0025] As a result, in the first capacitive section 110, the first internal electrode layer 31 is connected to the first external electrode 41 of the external electrode pair 40 arranged on the first main surface TS1 of the laminate 10, and is separated from the second external electrode 42 of the external electrode pair 40 arranged on the first main surface TS1. In addition, the second internal electrode layer 32 is connected to the second external electrode 42 of the external electrode pair 40 arranged on the first main surface TS1 of the laminate 10, and is separated from the first external electrode 41 of the external electrode pair 40 arranged on the first main surface TS1.

[0026] Similarly, in the second capacitive section 120, the counter electrode section 311 and the counter electrode section 321 face each other across the dielectric layer 20 in the stacking direction of the laminate 10, i.e., the width direction W. In the second capacitive section 120, the extraction electrode section 312 extends from a portion of the counter electrode section 311 on the first end face LS1 side of the laminate 10 toward the second main surface TS2 of the laminate 10 and is exposed at the second main surface TS2. The extraction electrode section 322 extends from a portion of the counter electrode section 321 on the second end face LS2 side of the laminate 10 toward the second main surface TS2 of the laminate 10 and is exposed at the second main surface TS2.

[0027] As a result, in the second capacitive section 120, the first internal electrode layer 31 is connected to the first external electrode 41 of the external electrode pair 40 arranged on the second main surface TS2 of the laminate 10, and is separated from the second external electrode 42 of the external electrode pair 40 arranged on the second main surface TS2. In addition, the second internal electrode layer 32 is connected to the second external electrode 42 of the external electrode pair 40 arranged on the second main surface TS2 of the laminate 10, and is separated from the first external electrode 41 of the external electrode pair 40 arranged on the second main surface TS2.

[0028] The multiple internal electrode layers 30 in the first capacitive section 110 and the multiple internal electrode layers 30 in the second capacitive section 120 may be plane-symmetric with respect to the center in the thickness direction T. Alternatively, the multiple internal electrode layers 30 in the first capacitive section 110 and the multiple internal electrode layers 30 in the second capacitive section 120 may be rotationally symmetric with respect to the center in the thickness direction T and the center in the width direction W. When the thickness in the width direction W of the first outer layer section 101 and the thickness in the width direction W of the second outer layer section 102 are different, the multiple internal electrode layers 30 in the first capacitive section 110 and the multiple internal electrode layers 30 in the second capacitive section 120 may be rotationally symmetric with respect to the center in the thickness direction T of the laminate 10 and the center in the width direction W of the inner layer section 100 of the laminate 10.

[0029] The thickness T1 of the internal electrode layer 30 in the thickness direction T in the first capacitive portion 110, in other words, the thickness T1 from the first main surface TS1 of the internal electrode layer 30 in the first capacitive portion 110, is preferably 25 μm or more and 70 μm or less. Also, the thickness T1 of the internal electrode layer 30 in the thickness direction T in the second capacitive portion 120, in other words, the thickness T1 from the second main surface TS2 of the internal electrode layer 30 in the second capacitive portion 120, is preferably 25 μm or more and 70 μm or less.

[0030] The first internal electrode layer 31 and the second internal electrode layer 32 contain metal Ni as a main component. The first internal electrode layer 31 and the second internal electrode layer 32 may contain at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals, such as an Ag-Pd alloy, as a main component or as a component other than the main component. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may contain particles of a dielectric material having the same composition as the ceramic contained in the dielectric layer 20 as a component other than the main component. In this specification, the main component metal is defined as the metal component with the highest weight percentage.

[0031] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 0.2 μm or more and 1.0 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 2 to 430.

[0032] The dimensions of the laminate 10 described above are not particularly limited, but it is preferable that, for example, the length in the longitudinal direction L is 0.2 mm or more and 0.6 mm or less, the width in the width direction W is 0.1 mm or more and 0.3 mm or less, and the thickness in the thickness direction T is 0.1 mm or more and 0.3 mm or less.

[0033] One of the two external electrode pairs 40 is disposed on a first main surface TS1 of the laminate 10, and the other of the two external electrode pairs 40 is disposed on a second main surface TS2 of the laminate 10. Each external electrode pair 40 includes a first external electrode 41 and a second external electrode 42.

[0034] The first external electrode 41 in one external electrode pair 40 is arranged on the first end face LS1 side of the first main surface TS1 of the laminate 10, and the second external electrode 42 in the other external electrode pair 40 is arranged on the second end face LS2 side of the first main surface TS1 of the laminate 10. The first external electrode 41 is connected to the first internal electrode layer 31 in the first capacitive section 110, and the second external electrode 42 is connected to the second internal electrode layer 32 in the first capacitive section 110.

[0035] The first external electrode 41 of the other external electrode pair 40 is arranged on the first end face LS1 side of the second main surface TS2 of the laminate 10, and the second external electrode 42 of the other external electrode pair 40 is arranged on the second end face LS2 side of the second main surface TS2 of the laminate 10. The first external electrode 41 is connected to the first internal electrode layer 31 of the second capacitive section 120, and the second external electrode 42 is connected to the second internal electrode layer 32 of the second capacitive section 120.

[0036] The first external electrode 41 and the second external electrode 42 are preferably metal layers consisting of plating. That is, the first external electrode 41 and the second external electrode 42 are preferably metal layers including only plating layers. The metal layer consisting of plating includes at least one selected from metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag-Pd alloys.

[0037] The metal layer made of plating may be formed of multiple layers. Preferably, it has a three-layer structure of Cu plating, Ni plating, and Sn plating. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, allowing for easier mounting. The thickness of each metal layer made of plating is not particularly limited and may be 1 μm or more and 10 μm or less.

[0038] The first external electrode 41 and the second external electrode 42 may have an underlayer made of a metal layer formed by plating. The underlayer may be a thin film layer of 1 μm or less formed by depositing metal particles using a thin film formation method such as sputtering or vapor deposition. The total thickness of the first external electrode 41 and the second external electrode 42 is preferably 4 μm or more and 16 μm or less.

[0039] Alternatively, the underlayer may be a fired layer containing a metal and glass. The glass may include a glass component containing at least one element selected from B, Si, Ba, Mg, Al, Li, etc. A specific example is borosilicate glass. The metal may contain Cu as a main component. The metal may also contain at least one element selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, as a main component or as a component other than the main component.

[0040] The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by a dipping method and firing the layer. The fired layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The fired layer may also be a multi-layer structure.

[0041] Alternatively, the underlayer may be a resin layer containing conductive particles and a thermosetting resin. The resin layer may be formed on the fired layer described above, or may be formed directly on the laminate without forming a fired layer.

[0042] The resin layer is a layer formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and then firing the layer. The resin layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The resin layer may also be a multi-layered layer.

[0043] The thickness of each of the baked layers or the underlayers as resin layers is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0044] (circuit module) Next, a circuit module mounting the above-described multilayer ceramic capacitor 1 will be described. FIG. 5A is a cross-sectional view showing an example of a circuit module according to this embodiment. FIG. 5B is a side view showing the multilayer ceramic capacitor in the circuit module shown in FIG. 5A after polishing, and FIG. 5C is a perspective view showing the multilayer ceramic capacitor in the circuit module shown in FIG. 5A after polishing. After polishing, the polished surface has a greater surface roughness than the side surfaces WS1 and WS2 and the end surfaces LS1 and LS2. The surface roughness RA is measured using a laser displacement meter or the like.

[0045] As shown in Fig. 5A, the circuit module 500 includes a circuit board CB, electronic circuit components, and a resin mold member RMM. While Fig. 5A illustrates a multilayer ceramic capacitor 1A and an integrated circuit IC as examples of the electronic circuit components, the present invention is not limited to these, and various other electronic circuit components are applicable. For example, the electronic circuit components may include capacitors, inductors, resistors, semiconductor ICs (such as switch ICs, LNA ICs, controller ICs, and PA ICs), filters (such as SAW filters, BAW filters, and LC filters), and the like.

[0046] Electronic circuit components, such as a multilayer ceramic capacitor 1A and an integrated circuit IC, are mounted on one main surface of a circuit board CB. The periphery of the multilayer ceramic capacitor 1A and the integrated circuit IC is filled with a resin molding member RMM. This allows the resin molding member RMM to be disposed around the multilayer ceramic capacitor 1A and the integrated circuit IC. Note that electronic circuit components may also be mounted on the other main surface of the circuit board CB.

[0047] As will be described later, the multilayer ceramic capacitor 1A and the integrated circuit IC are polished and removed after being molded with the resin molding member RMM. As a result, the main surface of the multilayer ceramic capacitor 1A opposite the circuit board CB and the main surface of the resin molding member RMM opposite the circuit board CB are aligned in the thickness direction T. Furthermore, the surface roughness (polished surface) of the main surface of the multilayer ceramic capacitor 1A opposite the circuit board CB is greater than the surface roughness (side surfaces WS1 and WS2 and end faces LS1 and LS2) of the multilayer ceramic capacitor 1A facing the resin molding member RMM arranged around the multilayer ceramic capacitor 1A.

[0048] 5B and 5C, the multilayer ceramic capacitor 1A is obtained by polishing the above-described multilayer ceramic capacitor 1 in the thickness direction T and removing a portion of the multilayer ceramic capacitor 1 in the thickness direction T. More specifically, the multilayer ceramic capacitor 1A consists of either the first capacitive portion 110 or the second capacitive portion 120 of the above-described multilayer ceramic capacitor 1. That is, the multilayer ceramic capacitor 1A includes only one of the first capacitive portion 110 and the second capacitive portion 120 of the above-described multilayer ceramic capacitor 1, with the other of the first capacitive portion 110 and the second capacitive portion 120 being removed.

[0049] The ridges where the main surface of the multilayer ceramic capacitor 1A opposite the circuit board CB intersects with the end faces LS1 and LS2, and the ridges where the main surface of the multilayer ceramic capacitor 1A opposite the circuit board CB intersects with the side faces WS1 and WS2, are not chamfered or rounded. More specifically, the radius of curvature of these ridges is 10 μm or less. The ridges where the main surfaces TS1 and TS2 of the laminate 10 intersect with the end faces LS1 and LS2, and the ridges where the main surfaces TS1 and TS2 of the laminate 10 intersect with the side faces WS1 and WS2, i.e., the chamfered ridges, have a radius of curvature of, for example, 10 μm or more and 35 μm or less. The thickness T2 of the multilayer ceramic capacitor 1A from the circuit board CB is preferably 29 μm or more and 86 μm or less.

[0050] (Manufacturing method of multilayer ceramic capacitors) Next, a method for manufacturing the above-mentioned multilayer ceramic capacitor 1 will be described. First, a dielectric sheet for the dielectric layers 20 and a conductive paste for the internal electrode layers 30 are prepared. The dielectric sheet and the conductive paste contain a binder and a solvent. Known materials can be used as the binder and the solvent.

[0051] Next, a conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode pattern on the dielectric sheet. The internal electrode pattern can be formed by screen printing, gravure printing, or the like.

[0052] Next, a predetermined number of dielectric sheets for the second outer layer portion 102, on which no internal electrode pattern is printed, are stacked. On top of these, dielectric sheets for the inner layer portion 100, on which internal electrode patterns are printed, are stacked in sequence. On top of these, a predetermined number of dielectric sheets for the first outer layer portion 101, on which no internal electrode pattern is printed, are stacked. In this way, a laminated sheet is produced.

[0053] Next, the laminated sheet is pressed in the lamination direction using a means such as a hydrostatic press to produce a laminated block. Next, the laminated block is cut to a predetermined size to cut out laminated chips. At this time, the corners and ridges of the laminated chips are rounded by barrel polishing or the like. Next, the laminated chips are fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric and internal electrodes, but is preferably 900°C or higher and 1400°C or lower.

[0054] Next, a metal layer consisting of plating is formed on the first main surface TS1 of the laminate 10 to form one of the external electrode pairs 40. Also, a metal layer consisting of plating is formed on the second main surface TS2 of the laminate 10 to form the other of the external electrode pairs 40. Through the above steps, the multilayer ceramic capacitor 1 described above is obtained.

[0055] (Circuit module manufacturing method) Next, a method for manufacturing the above-mentioned circuit module 500 will be described. Fig. 6A is a cross-sectional view showing the circuit module after polishing in the manufacturing process of the circuit module shown in Fig. 5A. Fig. 6B is a side view showing the multilayer ceramic capacitor before polishing in the circuit module before polishing shown in Fig. 6A, and Fig. 6C is a perspective view showing the multilayer ceramic capacitor before polishing in the circuit module before polishing shown in Fig. 6A.

[0056] 6A, electronic circuit components, such as the multilayer ceramic capacitor 1 and integrated circuit IC, are mounted on one main surface of the circuit board CB. Next, the electronic circuit components, such as the multilayer ceramic capacitor 1 and the integrated circuit IC, are filled with a resin molding member RMM.

[0057] 5A, the electronic circuit components, for example, the multilayer ceramic capacitor 1 and the integrated circuit IC, and the resin molding member RMM are polished in the thickness direction T. At this time, the exposed surfaces of the electronic circuit components may be remolded.

[0058] After that, electronic circuit components may be mounted on the other main surface of the circuit board CB, and the periphery of the electronic circuit components may be filled with a resin molding member. This results in the circuit module 500 shown in FIG. 5A.

[0059] As described above, the multilayer ceramic capacitor 1 of this embodiment includes two capacitive sections 110 and 120 and two external electrode pairs 40 corresponding to the two capacitive sections 110 and 120, respectively. More specifically, the multilayer ceramic capacitor 1 of this embodiment includes two capacitive sections 110 and 120 in the thickness direction T. As a result, by polishing and removing one capacitive section in the thickness direction T, a thin capacitor can be obtained using the other capacitive section. In this way, the component before polishing does not have a reduced flexural strength. Meanwhile, when mounting on a circuit module, polishing in the thickness direction T can reduce the thickness.

[0060] Furthermore, according to the multilayer ceramic capacitor 1 of this embodiment, if the external electrode pairs 40 are metal layers made of plating, in other words, if they do not include a fired layer or a resin layer, it is possible to further reduce the thickness.

[0061] Furthermore, according to the multilayer ceramic capacitor 1 of this embodiment, the internal electrode layers 30 in the first capacitance section 110 and the internal electrode layers 30 in the second capacitance section 120 are plane-symmetric or rotationally symmetric with respect to the center in the thickness direction T. This eliminates the need to distinguish between the front and back of the multilayer ceramic capacitor 1.

[0062] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various modifications and variations are possible. For example, the above-described embodiments illustrate a multilayer ceramic capacitor 1 in which two external electrode pairs 40 are arranged on each of the first main surface TS1 and the second main surface TS2 of the laminate 10. However, the shape of the external electrode pairs 40 is not limited to this, and the external electrode pairs 40 may extend from the main surface TS1 or TS2 to the end surface LS1 or LS2 (see Modification 1 described below). Furthermore, the external electrode pairs 40 may extend from the main surface TS1 or TS2 to the side surface WS1 or WS2 (see Modification 2 described below).

[0063] (Variation 1) Fig. 7 is a perspective view showing a multilayer ceramic capacitor according to a modified example of this embodiment, and Fig. 8 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 7 taken along line VIII-VIII. Fig. 9A is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 8 taken along line IXA-IXA, and Fig. 9B is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 8 taken along line IXB-IXB. Fig. 10 is a perspective view showing internal electrode layers in the multilayer ceramic capacitor shown in Figs. 7 to 9B, and Fig. 7 shows the internal electrode layers and one of the external electrode pairs shown in Fig. 10 in a see-through manner.

[0064] The multilayer ceramic capacitor 1 shown in Figures 7 to 9B differs from the multilayer ceramic capacitor 1 shown in Figures 1 to 3B in the shapes of the two external electrode pairs 40 and the shapes of the internal electrode layers 30 in the first capacitive section 110 and the second capacitive section 120 of the laminate 10.

[0065] Specifically, the first external electrode 41 of one external electrode pair 40 arranged on the first main surface TS1 of the laminate 10 may extend from the first main surface TS1 to a part of the first end face LS1, and the second external electrode 42 of one external electrode pair 40 may extend from the first main surface TS1 to a part of the second end face LS2. This makes it possible to improve the bonding strength by utilizing the wettability of the solder when mounting on a circuit board.

[0066] Similarly, the first external electrode 41 of the other external electrode pair 40 arranged on the second main surface TS2 of the laminate 10 may extend from the second main surface TS2 to a part of the first end face LS1, and the second external electrode 42 of the other external electrode pair 40 may extend from the second main surface TS2 to a part of the second end face LS2. This makes it possible to improve the bonding strength by utilizing the wettability of the solder when mounting on a circuit board.

[0067] In the first capacitive section 110, the first internal electrode layer 31, more specifically the extraction electrode portion 312, extends from a portion of the counter electrode portion 311 on the first end face LS1 side of the laminate 10 toward the first end face LS1 of the laminate 10 and is exposed at the first end face LS1 as well. This allows the first internal electrode layer 31 and the first external electrode 41 to be connected not only at the first main surface TS1 but also at the first end face LS1 and the ridge where the first main surface TS1 and the first end face LS1 intersect. This increases the contact area between the first internal electrode layer 31 and the first external electrode 41, thereby reducing the contact resistance between the first internal electrode layer 31 and the first external electrode 41.

[0068] Furthermore, in the first capacitive section 110, the second internal electrode layer 32, more specifically the lead-out electrode portion 322, extends from a portion of the counter electrode portion 321 on the second end face LS2 side of the laminate 10 toward the second end face LS2 of the laminate 10 and is exposed at the second end face LS2 as well. This allows the second internal electrode layer 32 and the second external electrode 42 to be connected not only at the first main surface TS1 but also at the second end face LS2 and at the ridge portion of the laminate 10 where the first main surface TS1 and the second end face LS2 intersect. This increases the contact area between the second internal electrode layer 32 and the second external electrode 42, thereby reducing the contact resistance between the second internal electrode layer 32 and the second external electrode 42.

[0069] Similarly, in the second capacitive section 120, the first internal electrode layer 31, more specifically the extraction electrode portion 312, extends from a portion of the counter electrode portion 311 on the first end face LS1 side of the laminate 10 toward the first end face LS1 of the laminate 10 and is exposed at the first end face LS1 as well. This allows the first internal electrode layer 31 and the first external electrode 41 to be connected not only at the second main surface TS2 but also at the first end face LS1 and at the ridge portion of the laminate 10 where the second main surface TS2 and the first end face LS1 intersect. This increases the contact area between the first internal electrode layer 31 and the first external electrode 41, thereby reducing the contact resistance between the first internal electrode layer 31 and the first external electrode 41.

[0070] Furthermore, the second internal electrode layer 32, more specifically the lead electrode portion 322, extends from a portion of the opposing electrode portion 321 on the second end face LS2 side of the laminate 10 toward the second end face LS2 of the laminate 10 and is exposed at the second end face LS2 as well. This allows the second internal electrode layer 32 and the second external electrode 42 to be connected not only at the second main surface TS2 but also at the second end face LS2 and at the ridge portion of the laminate 10 where the second main surface TS2 and the second end face LS2 intersect. This makes it possible to increase the contact area between the second internal electrode layer 32 and the second external electrode 42 and reduce the contact resistance between the second internal electrode layer 32 and the second external electrode 42.

[0071] It is preferable that the corners of the first internal electrode layer 31 are rounded along the ridge where the main surface TS1 or TS2 of the laminate 10 intersects with the end face LS1, and it is preferable that the corners of the second internal electrode layer 32 are rounded along the ridge where the main surface TS1 or TS2 of the laminate 10 intersects with the end face LS2.

[0072] (Variation 2) Fig. 11 is a perspective view showing a multilayer ceramic capacitor according to a modified example of this embodiment, Fig. 12 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 11 taken along line XII-XII, and Fig. 13 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 11 taken along line XIII-XIII. Also, Fig. 14 is a perspective view showing internal electrode layers in the multilayer ceramic capacitor shown in Figs. 11 to 13, and Fig. 11 shows the internal electrode layers and one of the external electrode pairs shown in Fig. 14 in a see-through manner.

[0073] The multilayer ceramic capacitor 1 shown in FIGS. 11 to 13 differs from the multilayer ceramic capacitor 1 shown in FIGS. 1 to 3B in the shapes of the two external electrode pairs 40 and the shape of the laminate 10.

[0074] Specifically, the first external electrode 41 of one external electrode pair 40 arranged on the first main surface TS1 of the laminate 10 may extend from the first main surface TS1 to a portion of the first end face LS1, a portion of the first side face WS1, and a portion of the second side face WS2. Furthermore, the second external electrode 42 of one external electrode pair 40 may extend from the first main surface TS1 to a portion of the second end face LS2, a portion of the first side face WS1, and a portion of the second side face WS2. This makes it possible to improve the bonding strength by utilizing the wettability of the solder when mounting on a circuit board.

[0075] Similarly, the first external electrode 41 of the other external electrode pair 40 arranged on the second main surface TS2 of the laminate 10 may extend from the second main surface TS2 to a portion of the first end face LS1, a portion of the first side face WS1, and a portion of the second side face WS2. Furthermore, the second external electrode 42 of the other external electrode pair 40 may extend from the second main surface TS2 to a portion of the second end face LS2, a portion of the first side face WS1, and a portion of the second side face WS2. This makes it possible to improve the bonding strength by utilizing the wettability of the solder when mounting on a circuit board.

[0076] In this case, the internal electrode layers and the external electrode layers can be connected at the end faces and side faces of the laminate. Therefore, the thickness direction of the laminate may be the stacking direction. Specifically, as shown in Figures 12 and 13, the laminate 10 may have a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked in the thickness direction T. As a result, the laminate 10 has, in the thickness direction T, an internal layer portion 100 and a first external layer portion 101 and a second external layer portion 102 arranged to sandwich the internal layer portion 100.

[0077] Furthermore, similarly to the above-described embodiment, the laminate 10 has, in the thickness direction T, a first capacitive section 110, a second capacitive section 120, and a non-capacitive section 130.

[0078] The inner layer portion 100 includes some of the dielectric layers 20 and some of the internal electrode layers 30. More specifically, the first capacitance portion 110 in the inner layer portion 100 includes some of the dielectric layers 20 and some of the internal electrode layers 30. The second capacitance portion 120 in the inner layer portion 100 includes some of the dielectric layers 20 and some of the internal electrode layers 30 other than the portion for the first capacitance portion 110. In the first capacitance portion 110 and the second capacitance portion 120, adjacent internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The first capacitance portion 110 and the second capacitance portion 120 are portions that generate capacitance and essentially function as capacitors. On the other hand, the non-capacitance portion 130 in the inner layer portion 100 does not include an internal electrode layer 30 but includes multiple dielectric layers 20.

[0079] The first outer layer portion 101 is disposed on the first main surface TS1 side of the laminate 10, and the second outer layer portion 102 is disposed on the second main surface TS2 side of the laminate 10. More specifically, the first outer layer portion 101 is disposed between the first main surface TS1 and an internal electrode layer 30 of the multiple internal electrode layers 30 that is closest to the first main surface TS1, and the second outer layer portion 102 is disposed between the second main surface TS2 and an internal electrode layer 30 of the multiple internal electrode layers 30 that is closest to the second main surface TS2. The first outer layer portion 101 and the second outer layer portion 102 do not include the internal electrode layer 30, but each include a portion of the multiple dielectric layers 20 other than the portion intended for the internal layer portion 100. The first outer layer portion 101 and the second outer layer portion 102 are portions of the internal layer portion 100 that function as protective layers for the first capacitive portion 110 and the second capacitive portion 120.

[0080] 12 to 14, each of the first capacitive portion 110 and the second capacitive portion 120 includes a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32 as the plurality of internal electrode layers 30. The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312, and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322.

[0081] In the first capacitance portion 110, the opposing electrode portion 311 and the opposing electrode portion 321 face each other via the dielectric layer 20 in the stacking direction of the laminate 10, i.e., the thickness direction T. The opposing electrode portion 311 and the opposing electrode portion 321 are portions that generate electrostatic capacitance and essentially function as a capacitor.

[0082] In the first capacitive section 110, the extraction electrode section 312 extends from a portion of the counter electrode section 311 on the first end face LS1 side of the laminate 10 toward the first end face LS1, first side face WS1, and second side face WS2 of the laminate 10, and is exposed at the first end face LS1, first side face WS1, and second side face WS2. The extraction electrode section 322 extends from a portion of the counter electrode section 321 on the second end face LS2 side of the laminate 10 toward the second end face LS2, first side face WS1, and second side face WS2 of the laminate 10, and is exposed at the second end face LS2, first side face WS1, and second side face WS2.

[0083] As a result, in the first capacitive section 110, the first internal electrode layer 31 is connected to the first external electrode 41 of the external electrode pair 40 arranged on the first main surface TS1 of the laminate 10 at the first end face LS1, the first side face WS1, the second side face WS2, and at ridge portions of the laminate 10 where the end face LS1 intersects with the side faces WS1 and WS2. Also, the second internal electrode layer 32 is connected to the second external electrode 42 of the external electrode pair 40 arranged on the first main surface TS1 of the laminate 10 at the second end face LS2, the first side face WS1, the second side face WS2, and at ridge portions of the laminate 10 where the end face LS2 intersects with the side faces WS1 and WS2.

[0084] Similarly, in the second capacitive section 120, the extraction electrode section 312 extends from a portion of the counter electrode section 311 on the first end face LS1 side of the laminate 10 toward the first end face LS1, first side face WS1, and second side face WS2 of the laminate 10, and is exposed at the first end face LS1, first side face WS1, and second side face WS2. The extraction electrode section 322 extends from a portion of the counter electrode section 321 on the second end face LS2 side of the laminate 10 toward the second end face LS2, first side face WS1, and second side face WS2 of the laminate 10, and is exposed at the second end face LS2, first side face WS1, and second side face WS2.

[0085] As a result, in the second capacitive section 120, the first internal electrode layer 31 is connected to the first external electrode 41 of the external electrode pair 40 arranged on the second main surface TS2 of the laminate 10 at the first end face LS1, the first side face WS1, the second side face WS2, and at ridge portions of the laminate 10 where the end face LS1 intersects with the side faces WS1 and WS2. Also, the second internal electrode layer 32 is connected to the second external electrode 42 of the external electrode pair 40 arranged on the second main surface TS2 of the laminate 10 at the second end face LS2, the first side face WS1, the second side face WS2, and at ridge portions of the laminate 10 where the end face LS2 intersects with the side faces WS1 and WS2.

[0086] It is preferable that the corners of the first internal electrode layer 31 are rounded along the ridge where the end face LS1 of the laminate 10 intersects with the side faces WS1 and WS2, and it is preferable that the corners of the second internal electrode layer 32 are rounded along the ridge where the end face LS2 of the laminate 10 intersects with the side faces WS1 or WS2.

[0087] The multiple internal electrode layers 30 in the first capacitive portion 110 and the multiple internal electrode layers 30 in the second capacitive portion 120 may be plane-symmetric with respect to the center in the thickness direction T. Alternatively, the multiple internal electrode layers 30 in the first capacitive portion 110 and the multiple internal electrode layers 30 in the second capacitive portion 120 may be rotationally symmetric with respect to the center in the thickness direction T and the center in the width direction W. When the thickness in the width direction W of the first outer layer portion 101 and the thickness in the width direction W of the second outer layer portion 102 are different, the multiple internal electrode layers 30 in the first capacitive portion 110 and the multiple internal electrode layers 30 in the second capacitive portion 120 may be plane-symmetric with respect to the center in the thickness direction T of the inner layer portion 100 of the laminate 10, or may be rotationally symmetric with respect to the center in the thickness direction T of the inner layer portion 100 of the laminate 10 and the center in the width direction W of the laminate 10.

[0088] The thickness T1 of the internal electrode layer 30 in the thickness direction T in the first capacitive portion 110, in other words, the thickness T1 from the first main surface TS1 of the internal electrode layer 30 in the first capacitive portion 110, is preferably 25 μm or more and 70 μm or less. Also, the thickness T1 of the internal electrode layer 30 in the thickness direction T in the second capacitive portion 120, in other words, the thickness T1 from the second main surface TS2 of the internal electrode layer 30 in the second capacitive portion 120, is preferably 25 μm or more and 70 μm or less.

[0089] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 0.4 μm or more and 2.0 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 2 to 35.

[0090] Furthermore, the first outer layer portion 101 and the second outer layer portion 102 may include a plurality of conductor portions 50. The plurality of conductor portions 50 includes first conductor portions 511 and 512 and second conductor portions 521 and 522.

[0091] The first conductor 511 is disposed on the first end face LS1 side of the first outer layer portion 101, and the first conductor 512 is disposed on the second end face LS2 side of the first outer layer portion 101. The second conductor 521 is disposed on the first end face LS1 side of the second outer layer portion 102, and the second conductor 522 is disposed on the second end face LS2 side of the second outer layer portion 102.

[0092] Each of the first conductor portions 511 and 512 and the second conductor portions 521 and 522 has a plurality of conductor layers 50M. The shape of the conductor layers 50M is not particularly limited and may be, for example, a substantially rectangular shape. The plurality of conductor layers 50M are stacked in the thickness direction T, i.e., the stacking direction, with the dielectric layer 20 interposed therebetween.

[0093] An end portion of the conductor layer 50M of the first conductor portion 511 is exposed at the first end face LS1, the first side face WS1, and the second side face WS2. As a result, the end portion of the conductor layer 50M of the first conductor portion 511 is connected to the first external electrode 41 of the external electrode pair 40 arranged on the first main surface TS1 of the laminate 10 at the first end face LS1, the first side face WS1, the second side face WS2, and at ridge portions of the laminate 10 where the end face LS1 intersects with the side faces WS1 and WS2. In addition, an end portion of the conductor layer 50M of the first conductor portion 512 is exposed at the second end face LS2, the first side face WS1, and the second side face WS2. As a result, the end of the conductor layer 50M of the first conductor portion 512 is connected to the second external electrode 42 in the external electrode pair 40 arranged on the first main surface TS1 of the laminate 10, and to the second external electrode 42 at the second end face LS2, the first side face WS1, the second side face WS2, and the ridge portion of the laminate 10 where these end face LS2 intersect with the side faces WS1 and WS2.

[0094] Similarly, the end of the conductor layer 50M of the second conductor portion 521 is exposed at the first end face LS1, the first side face WS1, and the second side face WS2. As a result, the end of the conductor layer 50M of the second conductor portion 521 is connected to the first external electrode 41 of the external electrode pair 40 arranged on the second main surface TS2 of the laminate 10, and to the first external electrode 41 at the first end face LS1, the first side face WS1, the second side face WS2, and the ridges of the laminate 10 where the end face LS1 intersects with the side faces WS1 and WS2. Furthermore, the end of the conductor layer 50M of the second conductor portion 522 is exposed at the second end face LS2, the first side face WS1, and the second side face WS2. As a result, the end of the conductor layer 50M of the second conductor portion 522 is connected to the second external electrode 42 in the external electrode pair 40 arranged on the second main surface TS2 of the laminate 10, and to the second external electrode 42 at the second end face LS2, the first side face WS1, the second side face WS2, and the ridge portion of the laminate 10 where these end face LS2 intersect with the side faces WS1 and WS2.

[0095] It is preferable that the corners of the conductor layer 50M are rounded along the ridge where the end face LS1 of the laminate 10 intersects with the side faces WS1 and WS2, or along the ridge where the end face LS2 of the laminate 10 intersects with the side faces WS1 or WS2.

[0096] The material of the conductor layers 50M is not particularly limited, but may include, for example, the same material as the internal electrode layers 30. The thickness of the plurality of conductor layers 50M is not particularly limited, but is preferably, for example, 0.2 μm to 1.0 μm. The number of the plurality of conductor layers 50M in each of the first conductor portions 511 and 512 and the second conductor portions 521 and 522 is not particularly limited, but is preferably, for example, 2 to 30.

[0097] Providing the conductor layer 50M in this manner can improve the adhesion of the external electrode pairs 40 to the laminate 10. In particular, when the external electrode pairs 40 are made of plating only, the conductor layer 50M serves as a growth starting point for the plating. [Explanation of symbols]

[0098] 1. Multilayer ceramic capacitors 1A Multilayer ceramic capacitor after polishing 10 Laminate 20 dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 Counter electrode section 312 Extraction electrode section 32 Second internal electrode layer 321 Counter electrode section 322 Extraction electrode section 40 external electrode pair 41 First external electrode 42 Second external electrode 50 Conductor 511, 512 First conductor part 521, 522 Second conductor section 50M conductor layer 100 Inner layer 101 First outer layer 102 Second outer layer 110 first capacitance section 120 second capacitance part 130 Non-capacitive part 500 Circuit Module CB circuit board RMM resin molded parts IC Integrated Circuit L lengthwise T thickness direction W width direction LS1 First end face LS2 Second end face TS1 First principal surface TS2 Second principal surface WS1 First Aspect WS2 Second Aspect

Claims

1. a laminate having a first main surface and a second main surface that face each other in a thickness direction, a first side surface and a second side surface that face each other in a width direction that intersects the thickness direction, and a first end surface and a second end surface that face each other in a length direction that intersects the thickness direction and the width direction; two pairs of external electrodes respectively disposed on the first main surface and the second main surface of the laminate; Equipped with The laminate is a first capacitance section including some of the plurality of internal electrode layers, wherein adjacent internal electrode layers of the some of the internal electrode layers face each other; a second capacitance section including internal electrode layers of another part other than the part of the plurality of internal electrode layers, wherein adjacent internal electrode layers of the other part of the internal electrode layers face each other; and One of the two external electrode pairs is a first external electrode disposed on the first main surface and the first end surface; a second external electrode disposed on the first principal surface and the second end surface; and The other of the two external electrode pairs is a first external electrode disposed on the second principal surface and the first end surface; a second external electrode disposed on the second main surface and the second end surface; and the part of the internal electrode layers in the first capacitance section is connected to one of the external electrode pairs, the other internal electrode layer in the second capacitance section is connected to the other external electrode pair, the first external electrode of one of the external electrode pairs and the first external electrode of the other of the external electrode pairs are arranged spaced apart on the first end surface; Multilayer ceramic capacitor.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the two external electrode pairs are metal layers made of plating.

3. The part of the internal electrode layers in the first capacitance part includes a first internal electrode layer and a second internal electrode layer, a first internal electrode layer in the first capacitance section is exposed on the first main surface and the first end surface; the second internal electrode layer in the first capacitance section is exposed on the first main surface and the second end surface; 3. The multilayer ceramic capacitor according to claim 1.

4. The internal electrode layer of the other part in the second capacitance part includes a first internal electrode layer and a second internal electrode layer, a first internal electrode layer in the second capacitance section is exposed on the second main surface and the first end surface; the second internal electrode layer in the second capacitance section is exposed on the second main surface and the second end surface; The multilayer ceramic capacitor according to claim 3 .

5. The first internal electrode layer in the first capacitance portion is continuously exposed on the first main surface and the first end surface, the second internal electrode layer in the first capacitance section is continuously exposed on the first main surface and the second end surface; The multilayer ceramic capacitor according to claim 3 .

6. The first internal electrode layer in the second capacitance portion is continuously exposed on the second main surface and the first end surface, the second internal electrode layer in the second capacitance section is continuously exposed on the second main surface and the second end surface; The multilayer ceramic capacitor according to claim 4.

7. One of the external electrode pairs is first external electrodes disposed on the first main surface, the first end surface, the first side surface, and the second side surface; second external electrodes disposed on the first main surface, the second end surface, the first side surface, and the second side surface; and The other pair of external electrodes is first external electrodes disposed on the second main surface, the first end surface, the first side surface, and the second side surface; second external electrodes disposed on the second main surface, the second end surface, the first side surface, and the second side surface; having The multilayer ceramic capacitor according to claim 1 .

8. The part of the internal electrode layers in the first capacitance part includes a first internal electrode layer and a second internal electrode layer, a first internal electrode layer in the first capacitance portion is exposed on the first end face, the first side face, and the second side face; the second internal electrode layer in the first capacitance section is exposed on the second end face, the first side face, and the second side face; The multilayer ceramic capacitor according to claim 7.

9. The internal electrode layer of the other part in the second capacitance part includes a first internal electrode layer and a second internal electrode layer, a first internal electrode layer in the second capacitance section is exposed on the first end face, the first side face, and the second side face; the second internal electrode layer in the second capacitance section is exposed on the second end face, the first side face, and the second side face; The multilayer ceramic capacitor according to claim 8.

10. A circuit module in which electronic circuit components are mounted on a circuit board, the circuit board; The multilayer ceramic capacitor according to claim 1 or 7 is the electronic circuit component mounted on the circuit board; a resin molding member disposed around the multilayer ceramic capacitor; Equipped with the multilayer ceramic capacitor is formed by removing a portion in the thickness direction, and is composed of either the first capacitance portion or the second capacitance portion; the surface roughness of the main surface of the multilayer ceramic capacitor opposite to the circuit board is greater than the surface roughness of the laminate of the multilayer ceramic capacitor facing the resin molding member arranged around the multilayer ceramic capacitor; Circuit module.

11. 11. The method for manufacturing a circuit module according to claim 10, Mounting the multilayer ceramic capacitor, which is the electronic circuit component, on the circuit board; The periphery of the multilayer ceramic capacitor is filled with the resin molding member; polishing the multilayer ceramic capacitor and the resin mold member in the thickness direction; A method for manufacturing a circuit module.

12. A circuit module in which electronic circuit components are mounted on a circuit board, the circuit board; a multilayer ceramic capacitor, which is the electronic circuit component, mounted on the circuit board; a resin molding member disposed around the multilayer ceramic capacitor; Equipped with The multilayer ceramic capacitor comprises: a laminate having a first main surface and a second main surface that face each other in a thickness direction, a first side surface and a second side surface that face each other in a width direction that intersects the thickness direction, and a first end surface and a second end surface that face each other in a length direction that intersects the thickness direction and the width direction; two pairs of external electrodes respectively disposed on the first main surface and the second main surface of the laminate; Equipped with The laminate is a first capacitance section including some of the plurality of internal electrode layers, wherein adjacent internal electrode layers of the some of the internal electrode layers face each other; a second capacitance section including internal electrode layers of another part other than the part of the plurality of internal electrode layers, wherein adjacent internal electrode layers of the other part of the internal electrode layers face each other; and the part of the internal electrode layers in the first capacitance section is connected to one of the two external electrode pairs, the other internal electrode layer in the second capacitance section is connected to the other external electrode pair of the two external electrode pairs, a portion in the thickness direction is removed to form either the first capacitance portion or the second capacitance portion; the surface roughness of the main surface of the multilayer ceramic capacitor opposite to the circuit board is greater than the surface roughness of the laminate of the multilayer ceramic capacitor facing the resin molding member arranged around the multilayer ceramic capacitor; Circuit module.

13. A method for manufacturing the circuit module according to claim 12, comprising: Mounting the multilayer ceramic capacitor, which is the electronic circuit component, on the circuit board; The periphery of the multilayer ceramic capacitor is filled with the resin molding member; polishing the multilayer ceramic capacitor and the resin mold member in the thickness direction; A method for manufacturing a circuit module.

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