Memory system, access control method and program

Abstract

To provide a memory access technique that enables performance improvement without increasing the load on a host device side.SOLUTION: A memory system is provided, comprising a non-volatile memory having a plurality of logical areas, and a controller for controlling an access to each logical area of the non-volatile memory, where the controller includes an execution order control unit configured to set the execution order of received commands according to predetermined priority levels assigned to the logical areas specified by the commands.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a memory system, an access control method, and a program. [Background technology]

[0002] For example, there are memory systems equipped with non-volatile memory such as solid-state drives (SSDs) that use the non-volatile memory express (NVMe) interface protocol. Such memory systems logically divide and use their storage areas. Each divided logical area is called a name space (NS).

[0003] One technique for improving the usability of SSDs is to adaptively control the performance of canceling write requests (write commands) to the SSD by setting an atomic write cancellation priority for each NS from the host device (see, for example, Patent Document 1). According to the technique disclosed in Patent Document 1, a cancellation priority is set for each NS, and the cancellation processing method is changed depending on the set priority. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-107318 Summary of the Invention [Problem to be solved by the invention]

[0005] The following analysis was carried out by the inventors.

[0006] Generally, in memory systems with NVMe SSDs and the like, NSs are generated for each application. Depending on the application, high speed may or may not be required. For example, in an in-vehicle device, driving information (current location and surrounding information) for autonomous driving must be provided immediately, even at the expense of other information. On the other hand, information on mileage and remaining fuel can be provided later. Therefore, when using such a memory system in an in-vehicle device, this information can be stored in different NSs for each application.

[0007] According to the technology disclosed in Patent Document 1, the processing speed of a single command varies depending on the priority set in the NS. However, in such a memory system, commands are processed in the order in which they are issued. Therefore, even if information requiring immediacy is stored in a high-priority NS, if a command for that information is issued after a command for an NS with information that does not require immediacy, the former will only be executed after the latter has been processed. Furthermore, the technology disclosed in Patent Document 1 only supports cancel commands. However, there are a wide variety of commands from the host device to the memory system, not just cancel commands.

[0008] To control the execution order of consecutively issued commands, the host device must control the order in which commands are issued to non-volatile memory such as NVMe SSDs, which requires complex processing in the host device application.

[0009] As such, currently, when multiple commands are issued consecutively, unless complex processing is imposed on the host device, the command execution order cannot be properly controlled, resulting in waiting times in processing within the memory system, which prevents the memory system from speeding up processing and prevents the response performance from being fully utilized.

[0010] The present disclosure has been made in consideration of the above circumstances, and aims to provide a memory access technique that can improve performance without increasing the load on the host device side. [Means for solving the problem]

[0011] According to a first aspect of the present disclosure, The memory system is a non-volatile memory having a plurality of logic regions; and a controller that controls access to each logical area of ​​the nonvolatile memory. The controller The execution order of the received command is determined by the The specified purpose is set In the logic area configured Priority The command priority is The execution order control unit determines the execution order according to the The logic area to teeth, In advance, the priority and Purpose Toga It is set. The controller further includes an execution unit that executes the commands according to an execution queue in which the commands are queued in the order of execution. Each time the execution order control unit receives a new command, it adds the new command to the end of the commands in the execution queue that have the same command priority as the command priority of the new command, thereby rearranging the commands in the execution queue in descending order of the command priority of each command. .

[0012] According to a second aspect of the present disclosure, An access control method for controlling access to each logic area in a nonvolatile memory having a plurality of logic areas includes: The execution order of the received command is command To be determined according to priority. The logic area to teeth, In advance, the priority and Purpose Toga It is set. The control method includes: each time a new command is received, the command is added to the end of the commands in the execution queue in which the commands are queued in order of execution, the command having the same command priority as the command priority set in the logical area in which the use specified by the command is set, thereby rearranging the commands in the execution queue in order of the command priority of each command, from highest to lowest; The commands are executed according to the execution queue.

[0013] According to a third aspect of the present disclosure, a program causes a controller of a nonvolatile memory having a plurality of logical areas to execute the above access control method.

[0014] These programs can be recorded on a computer-readable storage medium. The storage medium can be a non-transient medium such as a semiconductor memory, a hard disk, a magnetic recording medium, or an optical recording medium. The present invention can also be embodied as a computer program product. [Effects of the Invention]

[0015] According to the present disclosure, it is possible to improve the performance of a memory system without increasing the load on the host device side. [Brief explanation of the drawings]

[0016] [Figure 1] 1A and 1B are diagrams illustrating an example of the configuration and hardware, respectively, of a memory system according to an embodiment of the present disclosure. [Figure 2] 1A and 1B are diagrams illustrating an example of the configuration of an information processing system and a memory system, respectively, according to an embodiment of the present disclosure. [Figure 3] 10A to 10C are diagrams illustrating an example of a create command, an MS Management command, and a command issued during operation, respectively, according to an embodiment of the present disclosure. [Figure 4] FIG. 1A is a diagram for explaining an example of an MS table according to an embodiment of the present disclosure, and FIG. 1B is a diagram for explaining an example of execution order control according to an embodiment of the present disclosure. [Figure 5] 10 is a flowchart of an NS creation process according to an embodiment of the present disclosure. [Figure 6] 10 is a flowchart of a command process according to an embodiment of the present disclosure. [Figure 7] 10A and 10B are diagrams illustrating an example of a command execution order according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0017] An outline of one embodiment of the present disclosure (hereinafter referred to as the present embodiment) will be described below with reference to the drawings. Note that reference numerals in the drawings are assigned to each element for convenience as an example to facilitate understanding, and are not intended to limit the present disclosure to the illustrated form. Furthermore, connecting lines between blocks in the drawings and the like referred to in the following description include both bidirectional and unidirectional lines. Unidirectional arrows are used to schematically indicate the flow of a main signal (data) and do not exclude bidirectionality.

[0018] In addition, although there are ports and interfaces at the connection points of input and output of each block in the figure, they are not shown. In the following explanation, "A and / or B" means either A or B, or A and B.

[0019] <<First Embodiment>> Hereinafter, one embodiment (first embodiment) of the present disclosure will be described with reference to the drawings.

[0020] The memory system 200 of this embodiment is a system capable of controlling the execution order of commands in a storage area configured with nonvolatile memory, for example, an SSD (Solid State Drive) that employs NVMe (Non-Volatile Memory Express). The memory system 200 operates as a storage device, stores received data, and outputs the stored data in response to a request.

[0021] In this embodiment, the storage area (non-volatile memory) is divided into multiple logical areas (Name spaces; NS), each of which is assigned a predetermined priority. Received commands are then executed in order of the NS priority specified by each command.

[0022] 1(a) is a configuration diagram of a memory system 200 according to this embodiment. The memory system 200 is implemented, for example, by an NVMe SSD, and includes a controller 210 and a nonvolatile memory 220 that functions as a storage area.

[0023] The nonvolatile memory 220 is realized by, for example, a NAND flash memory. In this embodiment, the nonvolatile memory 220 is logically divided into a plurality of logical areas. As described above, each logical area is called a Name Space (NS). A priority that determines the execution order of commands is set in advance for each NS.

[0024] 1 illustrates an example in which the nonvolatile memory 220 includes NS231, NS232, and NS233. However, the number of NSs may be any number and is not limited to three. Hereinafter, when it is not necessary to distinguish between the NSs, they will be represented by NS230.

[0025] The controller 210 exchanges data (signals) with the host device that issues the command, and also controls access to the nonvolatile memory 220. A command received from the host device includes information specifying the NS 230 in which the data to be executed by the command is stored.

[0026] The controller 210 includes an execution order control unit 212 that controls the execution order of commands. The execution order control unit 212 of this embodiment determines the execution order of received commands according to the priority order predetermined for the NS 230 specified by the command.

[0027] In the controller 210, unexecuted commands received from the host device are queued in an execution queue in the order of execution. When the execution order control unit 212 of this embodiment receives a new command from the host device, it rearranges the commands queued in the execution queue in the order of the priority of the NS 230 specified by the command. Specifically, the commands are rearranged so that the command specifying the NS 230 with the higher priority is executed first.

[0028] The controller 210 executes commands according to the execution queue rearranged by the execution order control unit 212. Commands received from the host device include, for example, read, erase, and write.

[0029] Additionally, the controller 210 may detect and correct errors in the nonvolatile memory 220. Furthermore, the controller 210 may disable the use of a memory block in which some kind of defect has occurred and allocate a spare block (redundant block) instead. Furthermore, if a NAND flash memory is used for the nonvolatile memory 220, the controller 210 may store the number of erases for each memory block of the NAND flash memory and perform wear leveling to equalize the number of rewrites.

[0030] As described above, according to this embodiment, the memory system 200 pre-sets the priority of command execution for each NS 230. Then, the execution order of the commands is controlled according to the priority set for the NS 230 specified by each command. That is, the memory system 200 rearranges the execution order of the commands so that commands specifying NSs 230 with higher priority are executed first.

[0031] As a result, the memory system 200 of this embodiment can physically control processing performance on the side of the memory system 200. That is, according to this embodiment, in the memory system 200 in which multiple NSs 230 are set, appropriate priority processing can be realized without burdening the host device side, i.e., the user.

[0032] This makes it possible to suppress a decrease in NS performance due to commands with low priority but high load, and according to this embodiment, it is possible to realize a memory system 200 that is highly efficient, fast, and responsive. In other words, it is possible to make the most of the performance of the memory system.

[0033] Furthermore, according to this embodiment, in a system where IOs (Input / Output; commands) with different performance requirements coexist, command processing can be realized with a simpler configuration, at lower cost, and with desired priorities, compared to methods using virtualization, etc. This is particularly useful in, for example, data centers and edge areas where a variety of applications exist.

[0034] <<Second embodiment>> Next, a second embodiment of the present disclosure will be described. In this embodiment, when the controller 210 configures (creates) a logical area (NS230) in the nonvolatile memory 220 in accordance with an instruction from the host device, the controller 210 sets the priority of the NS230.

[0035] 2(a) is a diagram showing the overall configuration of an information processing system 100 according to this embodiment. The information processing system 100 according to this embodiment includes a host device 300 and a memory system 200. The memory system 200 is realized by an SSD or the like, similar to the first embodiment.

[0036] Hereinafter, in this embodiment, the memory system 200 will be referred to as SSD 200. Furthermore, with regard to the functions within the SSD 200, the same functions as those in the first embodiment will be assigned the same reference numerals.

[0037] The host device 300 issues commands to the SSD 200. The host device 300 is, for example, a PC (Personal Computer), a server, storage, Edge equipment, etc. The host device 300 is not limited to these, and may be any device that can issue commands to the SSD 200 and can send and receive data to and from the SSD 200.

[0038] In this embodiment, the host device 300 includes, for example, an NVMe device driver, and issues various commands defined in the NVMe specifications to the SSD 200. Specifically, the command issued by the host device 300 to the SSD 200 includes information for specifying the NS 230 to be used.

[0039] When creating an NS 230 in the SSD 200, the host device 300 transmits a create command 310 to the SSD 200. The create command 310 is issued for each NS 230 to be created. For example, when creating three NSs 230, a create command 310 with three NSIDs 311 is issued for each NS 230.

[0040] An example of a create command 310 is shown in Figure 3(a). The create command 310 comprises an NSID 311, a priority 312, a size 313, and a function 314. The NSID 311 is an identifier (ID) that can uniquely identify the NS 230 to be created. The priority 312 is the priority of the NS 230. The size 313 is the size of the logical area of ​​the NS to be created. The function 314 is information that indicates the use of the NS 230.

[0041] For example, the priority may be set using an existing NS Management command. An example of an NS Management command 320 is shown in Fig. 3(b). In this case, the priority of the NSID is set in the SSD using a bit in a currently reserved area of ​​the Operation Code (Opcode), for example, in the Function Field 321 of the NS Management command 320. Note that the priority setting is not limited to this, and any reserved bit in a field in an existing command may be used.

[0042] Note that one create command 310 may include the above information for each NS 230 along with the number of divisions.

[0043] The command 330 issued by the host device 300 to the SSD 200 during operation includes, as shown in Figure 3(c), a command ID 331 that uniquely identifies the command 330, an NSID 332 of the NS 230 in which the data to be executed (processed) is stored, and the processing content of the command (command processing content) 333.

[0044] The SSD 200 basically has the same configuration as in the first embodiment. Hereinafter, the same names and symbols will be used for components with the same functions as in the first embodiment.

[0045] As shown in FIG. 2( b ), the SSD 200 includes a controller 210 , a nonvolatile memory 220 , and a buffer memory 240 .

[0046] As in the first embodiment, the controller 210 functions as an interface with the host device 300 and controls access to the non-volatile memory 220. The controller 210 of this embodiment comprises an NS creation unit 211, an execution order control unit 212, an execution unit 213, a transmission / reception unit 214, and an NS management unit 215.

[0047] The transmitting / receiving unit 214 transmits and receives data, including commands, to and from the host device 300 .

[0048] When the NS creation unit 211 receives a create command 310 from the host device 300, it generates the specified number of NSs 230 in the nonvolatile memory 220. At this time, it sets a priority order for each NS 230. In other words, the NS creation unit 211 also functions as a priority order setting unit.

[0049] Specifically, the NS creation unit 211 divides the nonvolatile memory 220 into a specified number of logical areas each having a specified size, and creates each of these logical areas as the NS 230. Note that any existing NSs are deleted before the creation.

[0050] At this time, the NS creation unit 211 generates an NS table 250 that includes each piece of information specified in the create command 310 and information that associates the generated NS 230 with a physical area (simply referred to as a physical area). The generated NS table 250 is stored in the NS management unit 215. The NS management unit 215 is constructed in, for example, a storage unit or the like of the controller 210. The NS management unit 215 may also be constructed in the non-volatile memory 220.

[0051] 4(a) shows an example of the NS table 250 generated by the NS generation unit 211. The NS table 250 includes, for each generated NS 230, its NSID 251, priority 252, size 253, function 254, and physical area 255.

[0052] The NSID 251, priority 252, size 253, and function 254 are registered with the same information names in the create command 310 when generating the NS 230. The physical area 255 is information that associates each generated NS 230 with a physical utilization area in the nonvolatile memory 220.

[0053] As in the first embodiment, the execution order control unit 212 controls the execution order of commands 330 issued from the host device 300. When a command 330 is issued from the host device 300, the execution order control unit 212 queues it in an execution queue. At this time, the execution order control unit 212 compares the priority of the NSID 332 included in the queued command 330 (hereinafter referred to as the command priority) with the priority of a newly received command to be queued, and inserts the command into the execution queue so that it is executed in order of priority.

[0054] When the execution order control unit 212 receives a command 330 via the transmission / reception unit 214, it extracts the NSID 332 included in the command 330. Then, it references the NS table 250 and identifies the priority 252 associated with the NSID 251 that matches the extracted NSID 332. Then, it inserts the command into the execution queue. At this time, for example, the identified priority 252 may be added to the command 330.

[0055] The method by which the execution order control unit 212 adds a newly received command 330 to the execution queue will be described with reference to Fig. 4(b). Note that in Fig. 4(b), the command processing content 333 of the command 330 is omitted. In Fig. 4(b), as an example, it is assumed that a command 330 with a command ID 331 of "command 08" and a specified NSID 332 of "002" has been received.

[0056] Using the above-described method, the execution order control unit 212 assigns a priority 252 to the newly received command 330. In this case, since the NSID 332 is "002", the priority 252 is 2.

[0057] The execution order control unit 212 then determines where in the execution queue 340, which has already been sorted in order of priority, this command 330 should be inserted. Specifically, for example, starting from the top command in the execution queue, the execution order control unit 212 compares the priority 252 of each command with the priority 252 assigned to the newly received command 330. If the priority 252 assigned to the newly received command 330 is higher than the priority 252 assigned to the command 330 being compared in the execution queue, the newly received command 330 is inserted immediately before the command 330 being compared.

[0058] 4(b), the execution order control unit 212 compares the commands 330 in the execution queue 340 in order from highest to lowest priority, and when it compares them with command 02, the priority 252 of the command 330 received for the first time is higher than the priority 252 of the command 330 being compared. Therefore, the newly received command is inserted immediately before command 02, and the execution queue 340 is updated.

[0059] In addition, if the priority 252 assigned to the newly received command 330 is the lowest among the priorities of the NS230 set for that SSD200, the command 330 may be added to the end of the execution queue without performing the comparison process described above.

[0060] The method for determining the insertion position is not limited to this. It is also possible to compare the command from the end of the execution queue, or to use a bisection method or other existing sorting methods.

[0061] The execution unit 213 executes the commands according to the execution queue determined by the execution order control unit 212 .

[0062] The transmitting / receiving unit 214 controls the transmission and reception of data to and from the host device 300 .

[0063] As described above, the NS management unit 215 manages the NS 230. In this embodiment, the NS management unit 215 stores the NS table 250.

[0064] The nonvolatile memory 220 includes, for example, a plurality of NAND flash memories. In accordance with instructions from the controller 210, the nonvolatile memory 220 is logically divided to generate one or more logical areas. As in the first embodiment, each logical area is called an NS230. Here, NS231, NS232, and NS233 are shown as examples. The number of NSs and the number of NAND flash memories in each NS are not limited to these.

[0065] The buffer memory 240 is configured, for example, by a DRAM (Dynamic Random Access Memory), etc. In this embodiment, it is used as a work area for the controller 210.

[0066] [NS creation process] Next, the flow of the NS creation process by the controller 210 in this embodiment will be explained. Fig. 5 shows the processing flow of the NS creation process in this embodiment. This process is executed when the NS creation unit 211 receives a create command 310 from the host device 300 via the transmission / reception unit 214.

[0067] The NS creating unit 211 deletes the existing NS 230 in the nonvolatile memory 220 (step S1101). Note that if an NS has not been created in the nonvolatile memory 220, this process does not need to be performed.

[0068] The NS creating unit 211 creates the number of NSs 230 designated by the host device 300, each having a designated size (step S1102).

[0069] Then, the NS creation unit 211 registers information about each NS 230 in the NS table 250 (step S1103), and ends the process. Here, as described above, the NSID 251, priority 252, size 253, function 254, and physical area 255 are registered.

[0070] [Command Processing] Next, the flow of command processing when a command 330 is received from the host device 300 after the NS is generated will be described. Fig. 6 shows the processing flow of command processing in this embodiment. This processing is executed by the execution order control unit 212 and the execution unit 213 every time a command 330 with a priority (with NSID 332) is received from the host device 300 via the transmission / reception unit 214.

[0071] The execution order control unit 212 interprets the received command 330 and extracts the specified NSID 332 (step S1201).

[0072] The execution order control unit 212 refers to the NS table 250 and identifies the priority order 252 registered in association with the NSID 251 that matches the extracted NSID 332 (step S1202). The priority order 252 identified here is represented as PR0.

[0073] The execution order control unit 212 then determines whether the identified priority 252 (PR0) is the lowest among the priorities set in the NS 230 (step S1203). If it is the lowest (S1203: Yes), the execution order control unit 212 updates the execution queue 340 by queuing the received command at the end of the execution queue 340 (step S1211).

[0074] Otherwise (S1203: No), the execution order control unit 212 compares the identified priority 252 with each command in the execution queue 340, starting from the top command, to determine the insertion point and update the execution queue 340. This method will be described in detail below. Here, it is assumed that N commands are queued. Furthermore, the nth command from the top of the execution order in the execution queue 340 is called the nth command.

[0075] The execution order control unit 212 initializes a counter n (n=1) (step S1204). If n is greater than N (S1205: Yes), the process proceeds to step S1211.

[0076] Otherwise (S1205: No), the execution order control unit 212 compares the priority (PRn) of the n-th command from the top with the identified priority (PR0), and determines whether PR0 is higher (greater) than PRn (step S1206).

[0077] If PR0 is higher than PRn (S1206: Yes), the execution order control unit 212 inserts the received command 330 immediately before the n-th command and updates the execution queue (step S1210).

[0078] On the other hand, if PR0 is equal to or less than PRn (S1206: No), n is incremented by 1 (step S1207), and the process returns to step S1205 to repeat the process. That is, n is compared with the priority of the next command in the execution order until it exceeds N.

[0079] Once the execution queue 340 has been updated, the execution unit 213 executes the command from the top of the execution queue 340 (step S1220), and ends the process.

[0080] As an example of the above embodiment, the execution order when a write command and a read command are issued from the host device 300 will be described below.

[0081] For example, the order of issuance and the actual order of execution when three write commands are issued will be explained. Fig. 7(a) is a diagram for explaining the order of execution. Here, it is assumed that three write commands IO1, IO2, and IO3 are issued in this order, and NSID:01, NSID:02, and NSID:03 are specified as the NS230 to be executed, respectively.

[0082] In this case, the priority of the NSs specified in each write command is 1, 2, and 3, respectively, according to the NS table 250 in FIG. 4(a), so the execution order is IO3, IO2, and IO1.

[0083] Similarly, Figure 7(b) shows the execution order when three read commands IO1, IO2, and IO3 are issued in this order. As shown in this figure, the NSs specified in each read command IO1, IO2, and IO3 are NSID:01, NSID:02, and NSID:03, respectively, as above. In this case, the execution order is IO3, IO2, and IO1.

[0084] As described above, according to the information processing system 100 of this embodiment, an execution priority is set for each NS 230 in the memory system 200. Therefore, on the host device 300 side, by simply specifying the NS 230 to be executed in the command 330, each command is processed in the desired priority order even when multiple commands conflict. Therefore, the same effects as in the first embodiment can be obtained.

[0085] Furthermore, in this embodiment, the priority of each NS 230 is specified by the host device 300 when the NS 230 is created. Each NS 230 can be set for each purpose, so commands can be processed according to the user's desired priority for each purpose.

[0086] Therefore, according to this embodiment, a memory system 200 with high efficiency, high speed, and quick response can be realized.

[0087] [Hardware configuration] The configuration of the controller 210 in each of the above embodiments is shown in Fig. 1(b). As shown in this figure, the controller 210 may include a CPU (Central Processing Unit) 291, a DRAM interface (I / F) 292, a memory I / F 293, and a host I / F 294, which are connected to each other via a bus.

[0088] The CPU 291 is a processor that realizes the above-mentioned functions of the controller 210. The CPU 291 realizes the above-mentioned functions by, for example, loading a program such as firmware stored in the nonvolatile memory 220 or the like onto a RAM such as a DRAM and executing it.

[0089] The DRAM I / F 292, memory I / F 293, and host I / F 294 control data transmission and reception with RAM such as DRAM, the nonvolatile memory 220, and the host device 300, respectively.

[0090] Each function implemented by the CPU 291, the DRAM I / F 292, the memory I / F 293, and the host I / F 294 may be implemented by dedicated hardware, such as an integrated circuit (IC) dedicated to each process, an application specific integrated circuit (ASIC), a system on chip (SOC), or a field programmable gate array (FPGA).

[0091] <Variation 1> In the above embodiment, the memory system 200 is an SSD. However, the memory system 200 is not limited to an SSD. It may be any storage device equipped with nonvolatile memory accessible by the Nonvolatile Memory Express (NVMe) protocol. For example, it may be a flash device.

[0092] Furthermore, a NAND memory has been described as an example of the nonvolatile memory 220 included in the memory system 200. However, the nonvolatile memory 220 is not limited to this. For example, the nonvolatile memory 220 may be any of various other nonvolatile memories such as MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change Random Access Memory), ReRAM (Resistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory).

[0093] <Variation 2> Furthermore, an NVMe device can have multiple controllers, and an NS 230 is assigned to each controller. In the above embodiments, an example has been described in which there is one controller 210 in the memory system 200, but there may be multiple controllers 210. In each controller 210, the priority of commands to the assigned NS 230 can be controlled using the method of each of the above embodiments.

[0094] <Variation 3> In each of the above embodiments, the command 330 at the time of execution includes the NSID 332. However, this is not limited to this. For example, if a function is defined for each NS 230, the function may be specified.

[0095] Alternatively, the host device 300 may have a table that associates functions with the NS230 (NSID). In this case, the user specifies a function when issuing a command. The host device 300 may then refer to the table to identify the NSID corresponding to the specified function and include it in the command to be issued.

[0096] Alternatively, a function may be predetermined for each command. Then, host device 300 may be configured to identify the function for each command, identify the corresponding NSID by referencing a table, and issue command 330.

[0097] <Variation 4> Alternatively, a priority may be specified in the command 330 instead of the NSID 332. In this case, the execution order control unit 212 extracts the priority specified from the command 330 and determines the insertion position of the command 330 in the execution queue 340 according to the priority. The execution order control unit 212 or the execution unit 213 also refers to the NS table 250, identifies the NSID 251 corresponding to the matching priority 252, and determines the NS 230 to be processed.

[0098] <Variation 5> Furthermore, in each of the above embodiments, a different priority 252 is set for each NS 230, but this is not limiting. For example, the same priority 252 may be set for multiple NSs 230.

[0099] <Variation 6> Furthermore, in each of the above embodiments, if correspondence information between logical areas and physical areas is stored in advance, information for specifying the logical area may be stored in the NS table 250 instead of the physical area 255 .

[0100] <Variation 7> In addition, in each of the above embodiments, the host device 300 and the memory system (SSD) 200 are independent devices, but this is not limiting. The memory system 200 may be built into the host device 300 as a storage device of the host device 300.

[0101] In the flowcharts used in the above explanation, multiple steps (processes) are described in order, but the order in which each step is performed is not limited to the order described. For example, the order of the steps shown in the drawings can be changed to the extent that the content is not affected, such as by performing each process in parallel.

[0102] Furthermore, the program stored in the nonvolatile memory 220 and implementing the functions of the controller 210 can be provided as a program product recorded on a non-transitory computer-readable storage medium, which can be used to store various programs recorded on the non-transitory computer-readable storage medium for the medium to long term.

[0103] Although the embodiments and modifications of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and can be modified in various ways that would be understandable to a person skilled in the art. Each embodiment and modification can be combined with other embodiments as appropriate. Furthermore, for example, the network configurations and element configurations shown in the drawings are examples intended to aid in understanding the present disclosure and are not limited to the configurations shown in these drawings.

[0104] Finally, preferred embodiments of the present disclosure will be summarized. Some or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes. (Appendix 1) a non-volatile memory having a plurality of logic regions; a controller that controls access to each logic area of ​​the nonvolatile memory; The controller includes an execution order control unit that determines the execution order of received commands according to a priority predetermined for the logical area specified by the command. (Appendix 2) 10. The memory system of claim 1, an execution unit that executes the commands according to an execution queue in which the commands are queued in order of execution; It is desirable that the execution order control unit rearranges the execution queue in descending order of priority of the logical areas specified by each command each time a new command is received. (Appendix 3) 3. The memory system according to claim 1, It is preferable that the controller further includes a priority setting unit that sets the priorities when dividing the nonvolatile memory into the plurality of logical areas. (Appendix 4) In the memory system according to any one of Supplementary Notes 1 to 3, It is desirable that the logic area be set for each purpose. (Appendix 5) 1. An access control method for controlling access to each logical area in a nonvolatile memory having a plurality of logical areas, comprising: An access control method for determining an execution order of received commands according to a priority order predetermined for the logical area specified by the command. (Appendix 6) A controller for a non-volatile memory having a plurality of logic regions, A program that executes the access control method described in Appendix 5. In addition, the forms of Supplementary Notes 5 and 6 can be expanded into the forms of Supplementary Notes 2-4, just like Supplementary Note 1.

[0105] The disclosures of the above-mentioned patent documents and other documents are incorporated herein by reference. Modifications and adjustments of the embodiments and variations are possible within the scope of the entire disclosure (including the claims), and further based on the basic technical concepts thereof. Furthermore, various combinations and selections of the various disclosed elements (including each element of each claim, each element of each embodiment or variation, each element of each drawing, etc.) are possible within the scope of the disclosure. In other words, this disclosure naturally includes various modifications and alterations that would be possible by a person skilled in the art in accordance with the entire disclosure, including the claims, and the technical concepts thereof. In particular, with regard to the numerical ranges set forth herein, any numerical value or subrange within that range should be construed as specifically set forth, even if not otherwise specified. [Explanation of symbols]

[0106] 100: Information processing systems, 200: Memory system, 210: Controller, 211: NS creation unit, 212: Execution order control unit, 213: Execution unit, 214: Transmitting / receiving unit, 215: NS management unit, 220: Non-volatile memory, 230: NS (name space), 231: NS, 232: NS, 233: NS, 240: Buffer memory (DRAM), 250: NS table, 251: NSID, 252: Priority, 253: Size, 254: Function, 255: Physical area, 291: CPU, 292: DRAM I / F, 293: Memory I / F, 294: Host I / F, 300: Host device, 310: Create command, 311: NSID, 312: Priority, 313: Size, 314: Function, 320: NS Management command, 321: Function field, 330: Command, 331: Command ID, 332: NSID, 333: Command processing content, 340: Execution queue

Claims

1. a non-volatile memory having a plurality of logic regions; a controller that controls access to each logic area of ​​the nonvolatile memory; The controller an execution order control unit that determines the execution order of received commands in accordance with a command priority that is a priority set in the logical area in which the purpose specified by the command is set; an execution unit that executes the commands according to an execution queue in which the commands are queued in order of execution, The priority order and the purpose are set in advance in the logical area, the execution order control unit, each time it receives a new command, adds the command to the end of the commands in the execution queue that have the same command priority as the command's command priority, thereby rearranging the commands in the execution queue in descending order of the command priority of each command.

2. 2. The memory system of claim 1, The memory system, wherein the controller further comprises a priority setting unit that sets the priorities when dividing the nonvolatile memory into the plurality of logical areas.

3. 3. The memory system of claim 2, The memory system, wherein the priority setting unit further sets the uses when dividing the nonvolatile memory into the plurality of logical areas.

4. 1. An access control method for controlling access to each logical area in a nonvolatile memory having a plurality of logical areas, comprising: each time a new command is received, the command is added to the end of the commands in the execution queue, in which the commands are queued in order of execution, that have the same command priority as the command priority set in the logical area to which the use specified by the command is set, thereby rearranging the commands in the execution queue in order of the command priority of each command, and determining the execution order of the received commands according to the command priority of the command; Executing the commands according to the execution queue; An access control method, wherein the priority and the purpose are set in advance in the logical area.

5. A controller for a non-volatile memory having a plurality of logic regions, A program for causing execution of the access control method according to claim 4.

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