Amplification equipment

Abstract

To provide an amplifier which reduces a residual offset by reducing a glitch noise.SOLUTION: An amplifier 1A includes two auto zero amplifiers 21A, 22A mutually connected in parallel. The auto zero amplifiers 21A, 22A are provided to be switchable to: an offset calibration mode in which, after an output end is separated from an output of a transconductance amplifier 201, a calibration signal of reducing an offset component and a low frequency noise component of the transconductance amplifier 201 is sampled; an amplification mode in which, after the output end is connected to the output of the transconductance amplifier 201, the output of the transconductance amplifier 201 having the reduced offset component and low frequency noise component by the calibration signal, is output from the output end; and a glitch calibration mode in which, in a state that the output end is separated from the output of the transconductance amplifier 201, the output of the transconductance amplifier 201 is approached to the output of the output end.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an amplifier device. [Background technology]

[0002] Amplifiers are widely used to amplify sensor signals, etc., but some applications require that the offset and low-frequency noise components inside the amplifier be extremely small. Conventional amplifiers cannot meet these requirements in terms of the offset and low-frequency noise components, so there are many methods for reducing the offset and low-frequency noise components.

[0003] An auto-zero amplifier is known as a method for reducing offset components and low-frequency noise components (Patent Document 1, Non-Patent Document 1). An auto-zero amplifier is a method for reducing the offset components and low-frequency noise components of an amplifier using a built-in calibration circuit. Generally, an auto-zero amplifier operates alternately between a calibration mode and an amplification mode. In the calibration mode, the inverting and non-inverting inputs of the amplifier built into the auto-zero amplifier are shorted, and the output is connected to a sampling capacitor. This allows the sampling capacitor to sample a calibration voltage for reducing the offset components and low-frequency noise components. In the amplification mode, an input signal is input to the amplifier built into the auto-zero amplifier, and the amplifier amplifies the input signal to output an output signal. In the amplification mode, the offset components and low-frequency noise components included in the output signal are reduced by the sampled calibration voltage.

[0004] Therefore, since a single auto-zero amplifier cannot amplify the input signal in calibration mode, a Ping-Pong auto-zero amplifier is used, which has two auto-zero amplifiers, so that when one auto-zero amplifier is in calibration mode, the other is in amplification mode and amplifies the input signal. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 6,476,671 [Non-patent literature]

[0006] [Non-Patent Document 1] Ion E. Opris and Gregory TA Kovacs, “A Rail-to-Rail Ping-Pong Op-Amp”, IEEE J. Solid-State Circuits, vol. 31, no 9, pp. 1320-1324, Sep. 1996. Summary of the Invention [Problem to be solved by the invention]

[0007] In the Ping-Pong auto-zero amplifier described above, to switch the amplification mode from one auto-zero amplifier to the other, the output of one auto-zero amplifier is disconnected from the output terminal and the output of the other auto-zero amplifier is connected to the output terminal. The output voltage of the auto-zero amplifier described above differs between the calibration mode and the amplification mode. This causes a voltage difference between the output of the other auto-zero amplifier and the output terminal, resulting in sawtooth-wave glitch noise N in the output voltage V2 at the output terminal, as shown in Figure 20. This causes a problem in that the DC component of the glitch noise N becomes a residual offset component of the amplifier device.

[0008] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an amplifier device that reduces residual offset by reducing glitch noise. [Means for solving the problem]

[0009] In order to achieve the above-mentioned object, the amplifier according to the present invention is characterized by the following [1] to [6]. [1] an offset calibration mode in which the output terminal is separated from the output of the first amplifier, and a calibration signal is sampled to reduce the offset component and low-frequency noise component of the output voltage output from the output of the first amplifier; an amplification mode in which the output terminal and the output of the first amplifier are connected to each other, and the output voltage output from the output of the first amplifier, in which the offset component and the low-frequency noise component have been reduced by the calibration signal, is output from the output terminal; an auto-zero amplifier switchable between a glitch calibration mode and a glitch correction mode in which, while the output terminal and the output of the first amplifier are disconnected, the output voltage output from the output of the first amplifier is made to approach a fixed output voltage output from the output terminal; a control circuit that switches the auto-zero amplifier between the offset calibration mode, the glitch calibration mode, and the amplification mode in this order, and repeats this switching; the auto-zero amplifier includes a second amplifier; the control circuit controls connection of the second amplifier so that, in the glitch calibration mode, an input of the second amplifier configured as a 1x buffer is connected to the output terminal and an output of the second amplifier is connected to an output of the first amplifier; a plurality of the auto-zero amplifiers are provided for one of the output terminals; When the control circuit controls at least one of the plurality of auto-zero amplifiers to the amplification mode, the control circuit controls one or more other auto-zero amplifiers to the offset calibration mode or the glitch calibration mode. It is an amplification device. [2] [1] The amplifier according to the present invention, the auto-zero amplifier has a first switch connected between one of the two inputs of the second amplifier and the output of the second amplifier; the control circuit turns on the first switch in the glitch calibration mode to set the second amplifier in a 1x buffer configuration, and turns off the first switch in the amplification mode to set the second amplifier in an amplifier configuration, and controls the connection of the second amplifier so that the input of the second amplifier in the amplifier configuration is connected to an input terminal connected to the input of the first amplifier, and the output of the second amplifier is connected to the output of the first amplifier. It is an amplification device. [3] [2] The amplifier according to the present invention, the auto-zero amplifier has a 1x buffer; The control circuit, in the offset calibration mode, 1x buffer and controlling a connection of the 1x buffer so that the input of the 1x buffer is connected to the output terminal and the output of the 1x buffer is connected to the input of the second amplifier. It is an amplification device. [4] [1] or [2], the auto-zero amplifier has a filter circuit connected between the input of the second amplifier and the output terminal; It is an amplification device. [5] an offset calibration mode in which the output terminal is separated from the output of the first amplifier, and a calibration signal is sampled to reduce the offset component and low-frequency noise component of the output voltage output from the output of the first amplifier; an amplification mode in which the output terminal and the output of the first amplifier are connected to each other, and the output voltage output from the output of the first amplifier, in which the offset component and the low-frequency noise component are reduced by the calibration signal, is output from the output terminal; an auto-zero amplifier switchable between a glitch calibration mode and a glitch correction mode in which, while the output terminal and the output of the first amplifier are disconnected, the output voltage output from the output of the first amplifier is made to approach a fixed output voltage output from the output terminal; a control circuit that switches the auto-zero amplifier between the offset calibration mode, the glitch calibration mode, and the amplification mode in this order, and repeats this switching; As the auto-zero amplifier, a first auto-zero amplifier that performs inverting amplification for one of the output terminals in the amplification mode and a second auto-zero amplifier that performs non-inverting amplification for one of the output terminals in the amplification mode are provided, the control circuit controls the second auto-zero amplifier to the amplification mode when controlling the first auto-zero amplifier to the offset calibration mode or the glitch calibration mode, and controls the first auto-zero amplifier to the amplification mode when controlling the second auto-zero amplifier to the offset calibration mode or the glitch calibration mode. It is an amplification device. [6] The amplifier according to any one of [1] to [5], the control circuit controls the auto-zero amplifier in the glitch calibration mode for a period of time shorter than the period of time in the offset calibration mode; It is an amplification device. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide an amplifier device in which residual offset is reduced by reducing glitch noise.

[0011] The present invention has been briefly described above. The details of the present invention will become clearer by reading the following detailed description of the invention (hereinafter referred to as "embodiments") with reference to the accompanying drawings. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing the configuration of an amplifier device in an offset calibration mode according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing the configuration of the amplifier device in the glitch correction mode of the first embodiment. [Figure 3] FIG. 3 is a diagram showing the configuration of the amplification device in the amplification mode of the first embodiment. [Figure 4]FIG. 4 is a time chart of clocks supplied to the switches of the amplifying device shown in FIGS. [Figure 5] FIG. 5 is a time chart of the output voltages V1 and V2 of the amplifier device shown in FIG. [Figure 6] FIG. 6 is a diagram showing the configuration of the amplifier device in the offset calibration mode according to the second embodiment. [Figure 7] FIG. 7 is a diagram showing the configuration of the amplifier device in the glitch correction mode according to the second embodiment. [Figure 8] FIG. 8 is a diagram showing the configuration of the amplification device in the amplification mode according to the second embodiment. [Figure 9] FIG. 9 is a diagram showing the configuration of the amplifier device in the offset calibration mode according to the third embodiment. [Figure 10] FIG. 10 is a diagram showing the configuration of an amplifier device in the glitch correction mode according to the third embodiment. [Figure 11] FIG. 11 is a diagram showing the configuration of an amplifying device in the amplification mode according to the third embodiment. [Figure 12] FIG. 12 is a diagram showing an example of the configuration of an amplifier device according to a modified example of the third embodiment. [Figure 13] FIG. 13 is a diagram showing an example of the configuration of an amplifier device according to a modified example of the third embodiment. [Figure 14] FIG. 14 is a diagram illustrating an example of the configuration of an amplifying device according to the fourth embodiment. [Figure 15] FIG. 15 is a diagram showing an example of the configuration of a chopper-stabilized amplifier incorporating the amplifying device of the fifth embodiment. [Figure 16] FIG. 16 is a characteristic diagram showing an example of the time waveforms and frequency characteristics of the signal component, noise component, and offset component of the chopper stabilized amplifier shown in FIG. [Figure 17] FIG. 17 is a circuit diagram showing an example of a chopper modulator that constitutes the chopper stabilized amplifier shown in FIG. [Figure 18] FIG. 18 is a circuit diagram showing an example of a chopper modulator that constitutes the chopper modulator amplifier shown in FIG. [Figure 19]FIG. 19 is a diagram illustrating an example of the configuration of the amplifier shown in FIG. 15 according to another embodiment. [Figure 20] FIG. 20 is a time chart of the signal Vout output from the output terminal of the conventional amplifier device. DETAILED DESCRIPTION OF THE INVENTION

[0013] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0014] (First embodiment) 1 to 3 are diagrams showing the configuration of an amplifying device according to a first embodiment. The amplifying device 1A according to the first embodiment is composed of a Ping-Pong auto-zero amplifier. The amplifying device 1A includes two auto-zero amplifiers 21A and 22A (a first auto-zero amplifier and a second auto-zero amplifier) ​​connected in parallel. The auto-zero amplifiers 21A and 22A are connected in parallel and invert and amplify the input. The two auto-zero amplifiers 21A and 22A have the same configuration. Here, the auto-zero amplifier 21A will be described as a representative example, and a detailed description of the auto-zero amplifier 22A will be omitted.

[0015] The auto-zero amplifier 21A includes a transconductance amplifier 201 (first amplifier), an offset calibration circuit 202, and a glitch calibration circuit 203A. The transconductance amplifier 201 amplifies a signal Vin supplied to an input terminal and outputs the amplified signal as a signal Vout from an output terminal.

[0016] The offset calibration circuit 202 is a circuit that reduces the offset components and low-frequency noise components included in the signal Vout of the transconductance amplifier 201 and transconductance amplifiers 205 and 206 (described later). The offset calibration circuit 202 includes switches S1 and S2, switches S31 and S32, switches S41 and S42, a transconductance amplifier 204, and sampling capacitors C1 and C2.

[0017] Switch S1 is connected between the positive input terminal and the inverting input of transconductance amplifier 201. Switch S2 is connected between the inverting input and non-inverting input of transconductance amplifier 201. Switches S31 and S32 are connected between the output of transconductance amplifier 201 and the output terminal. That is, switch S31 is connected between the positive output of transconductance amplifier 201 and the positive output terminal. Switch S32 is connected between the negative output of transconductance amplifier 201 and the negative output terminal.

[0018] The switches S41 and S42 are connected between the output of the transconductance amplifier 201, the junction of the switches S31 and S32, and the sampling capacitors C1 and C2. One end of the sampling capacitor C1 is connected to ground, and the other end is connected to the negative output of the transconductance amplifier 201 via the switch S42. The sampling capacitor C2 has one end connected to ground, and the other end is connected to the positive output of the transconductance amplifier 201 via the switch S41. The transconductance amplifier 204 has the other end of the sampling capacitor C1 connected to its inverting input and the other end of the sampling capacitor C2 connected to its non-inverting input. The positive output of the transconductance amplifier 204 is connected to the negative output of the transconductance amplifier 201, and the negative output of the transconductance amplifier 201 is connected to the positive output of the transconductance amplifier 201.

[0019] The auto-zero amplifier 21A has two operating modes: an offset calibration mode, which is a calibration mode, and an amplification mode, thanks to the offset calibration circuit 202. The offset calibration mode is a mode in which calibration voltages for reducing offset components and low-frequency noise components of the transconductance amplifier 201 and transconductance amplifiers 205 and 206 (described later) are sampled into the sampling capacitors C1 and C2.

[0020] As shown in Figure 1, in the offset calibration mode, switch S1 is turned off and switch S2 is turned on. This shorts the inverting and non-inverting inputs of transconductance amplifier 201, causing the transconductance amplifier 201 to output an offset component and a low-frequency noise component. Also in the offset calibration mode, switches S31 and S32 are turned off, disconnecting the output of transconductance amplifier 201 from the output terminal. Also in the offset calibration mode, switches S41 and S42 are turned on, connecting the output of transconductance amplifier 201 to sampling capacitors C1 and C2. This allows the offset component and low-frequency noise component output from transconductance amplifier 201 to be sampled as calibration voltages by sampling capacitors C1 and C2.

[0021] In the amplification mode, a signal Vin is input to the transconductance amplifier 201, and a signal Vout obtained by amplifying the signal Vin is output from the transconductance amplifier 201. In addition, in the amplification mode, the offset component and low-frequency noise component contained in the signal Vout are reduced by the sampled calibration voltage.

[0022] 3, in the amplification mode, switch S2 is turned off, and switch S1, switches S31, and S32 are turned on. As a result, transconductance amplifier 201 is connected to the input terminal and output terminal, and signal Vout, which is obtained by amplifying signal Vin by transconductance amplifier 201, is output from the output terminal. Also, in the amplification mode, switches S41 and S42 are turned off. As a result, the calibration voltages sampled in sampling capacitors C1 and C2 are applied to the output of transconductance amplifier 201 via transconductance amplifier 204, and the offset component and low-frequency noise component included in signal Vout are reduced.

[0023] In the amplifying device 1A, when the auto-zero amplifier 21A is switched to the offset calibration mode, the auto-zero amplifier 22A is switched to the amplification mode. When the auto-zero amplifier 21A is switched to the amplification mode, the auto-zero amplifier 22A is switched to the offset calibration mode. This allows the amplifying device 1A to always output a signal Vout in which the offset component and low-frequency component are reduced.

[0024] The output voltage V1 of the transconductance amplifier 201 differs between the offset calibration mode and the amplification mode. Therefore, when the offset calibration mode is switched to the amplification mode and the switches S31 and S32 are turned on, a sawtooth glitch noise occurs at the output terminal due to the voltage difference between the output voltage V1 of the transconductance amplifier 201 and the output voltage V2 at the output terminal. Therefore, in this embodiment, a glitch calibration circuit 203A is provided to divide the calibration mode into the offset calibration mode described above and a glitch calibration mode described later, and to bring the output voltage V1 closer to the output voltage V2 before switching from the calibration mode to the amplification mode.

[0025] Glitch calibration circuit 203A includes two transconductance amplifiers 205 and 206 (second amplifiers), switches S51 and S52, and switches S61 and S62. Transconductance amplifier 205 has an inverting input connected to the negative side of the output terminal, and a non-inverting input connected to the negative side output via switch S51. Transconductance amplifier 205 has a positive side output connected to the positive side output of transconductance amplifier 201, and a negative side output connected to the negative side output of transconductance amplifier 201.

[0026] The transconductance amplifier 206 has a non-inverting input connected to the positive output terminal and an inverting input connected to the positive output via switch S52. The transconductance amplifier 206 has a positive output connected to the positive output of the transconductance amplifier 201 and a negative output connected to the negative output of the transconductance amplifier 201. Switches S61 and S62 are connected between the inverting and non-inverting inputs of the transconductance amplifiers 205 and 206.

[0027] By providing the glitch calibration circuit 203A, the amplifying device 1A has the above-mentioned offset calibration mode and glitch calibration mode as calibration modes. In the offset calibration mode, as shown in FIG. 1, the glitch calibration circuit 203A turns on switches S61 and S62 and turns off switches S51 and S52. This causes the transconductance amplifiers 205 and 206 to apply their own offset components and low-frequency noise components to the output of the transconductance amplifier 201. This causes the offset components and low-frequency noise components of the transconductance amplifiers 205 and 206 to be sampled as calibration voltages by the sampling capacitors C1 and C2.

[0028] The glitch calibration mode is a mode in which output voltage V1 is made to approach output voltage V2. In the glitch calibration mode, in glitch calibration circuit 203A, switches S51 and S52 are turned on and switches S61 and S62 are turned off, as shown in FIG. 2. As a result, transconductance amplifiers 205 and 206, which are configured as a buffer with a gain of 1, are connected between the output of transconductance amplifier 201 and the output terminal. Then, parasitic capacitance Cp connected to the output of transconductance amplifier 201 is charged by output voltage V2 at the output terminal, and output voltage V1 approaches output voltage V2.

[0029] In the glitch calibration mode, the switches S41 and S42 are also turned off, so that the calibration voltages sampled by the sampling capacitors C1 and C2 are applied to the output of the transconductance amplifier 201, thereby reducing the offset component and low-frequency noise component contained in the output voltage V2 applied to the output of the transconductance amplifier 201.

[0030] In the amplification mode, as shown in FIG. 3, the switches S61 and S62 are turned on, and the switches S51 and S52 are turned off.

[0031] Next, the operation of the amplifier device configured as described above will be described with reference to the timing chart shown in Fig. 4. A clock CLK1 is supplied to switches S1, S31, and S32 of auto-zero amplifier 21A, a clock CLK2 is supplied to switch S2, and a clock CLK3 is supplied to switches S41 and S42. A clock CLK4 is supplied to switches S51 and S52, and a clock CLK5 is supplied to switches S61 and S62. These clocks CLK1 to CLK5 cause auto-zero amplifier 21A to switch its operating mode in the order of offset calibration mode (Fig. 1), glitch calibration mode (Fig. 2), and amplification mode (Fig. 3), and this switching is repeated. A circuit (not shown) that supplies these clocks CLK1 to CLK5 constitutes the control circuit of auto-zero amplifiers 21A and 22A.

[0032] Clocks CLK1 to CLK5 that are 180 degrees out of phase with each other are supplied to switches S1, S2, S31, S32, S41, S42, S51, S52, S61, and S62 of the auto-zero amplifier 22A. Similarly, the auto-zero amplifier 22A switches between the offset calibration mode, the glitch calibration mode, and the amplification mode in that order. At this time, when the auto-zero amplifier 21A is in the amplification mode, the auto-zero amplifier 22A is in the offset calibration mode or the glitch calibration mode. Also, when the auto-zero amplifier 21A is in the offset calibration mode or the glitch calibration mode, the auto-zero amplifier 22A is in the amplification mode.

[0033] According to the above-described embodiment, in the glitch calibration mode, the output voltage V1 of the transconductance amplifier 201 approaches the output voltage V2, as shown by the dotted line in Fig. 5. This allows switching to the amplification mode with the output voltage V1 approaching the output voltage V2, thereby reducing the glitch noise N as shown in Fig. 5.

[0034] Furthermore, according to the above-described embodiment, in the glitch calibration mode, transconductance amplifiers 205 and 206 with a gain of 1 are connected between the output terminal and the output of transconductance amplifier 201 to bring output voltage V1 closer to output voltage V2. These transconductance amplifiers 205 and 206 allow output voltage V2 to be supplied to the output of transconductance amplifier 201 without affecting output voltage V2.

[0035] Furthermore, according to the above-described embodiment, two auto-zero amplifiers 21A and 22A are provided, and when one of the auto-zero amplifiers 21A and 22A is controlled in the offset calibration mode or the glitch calibration mode, the other is controlled in the amplification mode, thereby enabling the signal Vout, which is an amplified version of the signal Vin, to be output from the output terminal at all times.

[0036] Furthermore, according to the above-described embodiment, the time during which the auto-zero amplifiers 21A and 22A are in the glitch calibration mode is shorter than the time during which they are in the offset calibration mode.

[0037] (Second embodiment) Next, a second embodiment will be described. Figures 6 to 8 are diagrams showing the configuration of an amplifying device of the second embodiment. In Figures 6 to 8, parts equivalent to those of the amplifying device 1A shown in Figures 1 to 3 already described in the first embodiment above are given the same reference numerals, and detailed description thereof will be omitted.

[0038] The amplifying device 1B includes two auto-zero amplifiers 21B and 22B. The auto-zero amplifiers 21B and 22B may include a glitch calibration circuit 203B having a function of amplifying the signal Vin, instead of the glitch calibration circuit 203A shown in FIGS. 1 to 3. The glitch calibration circuit 203B includes two transconductance amplifiers 205 and 206 and switches S51, S52, S61, and S62, as in the first embodiment. The glitch calibration circuit 203B also includes switches S71 to S74.

[0039] Switches S71 to S74 are connected between the inputs and input terminals of transconductance amplifiers 205 and 206. That is, switches S71 and S73 are connected between the inverting inputs and positive input terminals of transconductance amplifiers 205 and 206, and switches S72 and S74 are connected between the non-inverting inputs and negative input terminals of transconductance amplifiers 205 and 206. A clock CLK1 is supplied to these switches S71 to S74, and in amplification mode, the input terminals are connected to the inputs of transconductance amplifiers 205 and 206, and a signal Vin is input.

[0040] Switches S81 and S82 are provided between the input and output terminals of the transconductance amplifiers 205 and 206. A clock CLK2 is supplied to the switches S81 and S82, and disconnect the input and output terminals of the transconductance amplifiers 205 and 206 in the amplification mode.

[0041] Furthermore, CLK3 is supplied to switches S61 and S62 instead of CLK5. As a result, the inverting and non-inverting inputs of transconductance amplifiers 205 and 206 are not short-circuited in the amplification mode. Therefore, signal Vin is input to the inputs of transconductance amplifiers 205 and 206 in the amplification mode. Transconductance amplifiers 205 and 206 amplify signal Vin and apply it to the output of transconductance amplifier 201. This allows transconductance amplifiers 205 and 206 to also contribute to the amplification of signal Vin. In other words, in the amplification mode, transconductance amplifiers 205 and 206 function as amplifiers. Furthermore, although the second embodiment includes transconductance amplifier 201, the present invention is not limited to this and transconductance amplifier 201 may be omitted.

[0042] (Third embodiment) Next, a third embodiment will be described. Figures 9 to 11 are diagrams showing the configuration of an amplifying device according to the third embodiment. In Figures 9 to 11, parts equivalent to those of the amplifying device 1B shown in Figures 6 to 8 and already explained in the second embodiment above are given the same reference numerals, and detailed explanations thereof will be omitted.

[0043] The amplifying device 1C includes two auto-zero amplifiers 21C and 22C. The auto-zero amplifiers 21C and 22C include a glitch calibration circuit 203C instead of the glitch calibration circuit 203B shown in FIGS. 6 to 8. In an actual circuit, as shown in FIGS. 9 to 11, parasitic capacitances Cp1 and Cp2 exist between the output terminal and the inputs of the transconductance amplifiers 205 and 206. Therefore, when the glitch calibration mode is switched to and the inputs of the transconductance amplifiers 205 and 206 are connected to the output terminal, as in the second embodiment, the parasitic capacitances Cp1 and Cp2 are charged. This charging of the parasitic capacitances Cp1 and Cp2 may cause glitch noise to appear at the output terminal. Therefore, the glitch calibration circuit 203C of the third embodiment includes 1x buffers 207 and 208 to charge the parasitic capacitances Cp1 and Cp2 before switching to the glitch calibration mode.

[0044] More specifically, glitch calibration circuit 203C of the third embodiment includes, in addition to transconductance amplifiers 205 and 206 and switches S51, S52, S61, S62, S71 to S74, S81, and S82, 1x buffers 207 and 208 and switches S91 and S92, as in the second embodiment. Clock CLK3 is supplied to switches S91 and S92, and they are turned on only in the offset calibration mode.

[0045] As a result, in the offset calibration mode, the parasitic capacitances Cp1 and Cp2 can be charged via the 1x buffers 207 and 208. Furthermore, because the parasitic capacitances Cp1 and Cp2 are connected to the output terminal via the 1x buffers 207 and 208, glitch noise caused by charging the parasitic capacitances Cp1 and Cp2 does not occur at the output terminal.

[0046] Next, when the glitch calibration mode is switched to, switches S81 and S82 are turned on, and the inputs of transconductance amplifiers 205 and 206 are connected to the output terminals, the parasitic capacitances Cp1 and Cp2 are already charged to a certain extent, thereby reducing the occurrence of glitch noise. Because the 1x buffers 207 and 208 have offset components, the charges charged in the parasitic capacitances Cp1 and Cp2 differ from the output voltage V2 by the amount of the offset components, but this is effective when the output voltage V2 is greater than or equal to the offset components of the 1x buffers 207 and 208.

[0047] 9 to 11, the auto-zero amplifiers 21C and 22C are each provided with two 1x buffers 207 and 208, but this is not limitative. As shown in Fig. 12, the two auto-zero amplifiers 21C and 22C may share the two 1x buffers 207 and 208.

[0048] 13, a filter circuit 209 may be provided in place of the two buffers 207 and 208, and may be shared. The output terminals and the inputs of the transconductance amplifiers 205 and 206 are connected via the filter circuit 209. In this case as well, the amount of glitch noise that appears at the output terminals due to charging and discharging of the parasitic capacitances Cp1 and Cp2 can be reduced.

[0049] (Fourth embodiment) Next, a fourth embodiment will be described. Fig. 14 is a diagram showing the configuration of an amplifying device in the fourth embodiment. An amplifier 100 may be further connected to the amplifying devices 1A to 1C shown in the first to third embodiments described above to form a two-stage amplifying device. The internal circuit of the amplifier 100 may be configured in a multi-stage configuration to form an amplifying device with two or more stages.

[0050] (Fifth embodiment) Next, a fifth embodiment will be described. Fig. 15 is a diagram showing the configuration of a chopper stabilized amplifier incorporating the amplifying device of the fifth embodiment. The amplifying device of the fifth embodiment is used in a chopper stabilized amplifier. A chopper stabilized amplifier 1D includes a chopper modulator 31, a transconductance amplifier 32, a chopper modulator 33 including the auto-zero amplifiers 21A to 21C and 22A to 22C shown in the first to fourth embodiments, and an amplifier 34A.

[0051] The chopper modulator 31 modulates the signal Vin input from the input terminal to a high frequency band (see FIGS. 16(A) and (B)). The transconductance amplifier 32 amplifies the output of the chopper modulator 31. The chopper modulator 33 modulates the signal component of the output of the transconductance amplifier 32 to a low frequency band, and modulates the offset component and low frequency noise component to a high frequency band (see FIGS. 16(B) and (C)).

[0052] The amplifier 34A amplifies the signal demodulated by the chopper modulator 31. In the fifth embodiment, the amplifier 34A has a transconductance amplifier 341, an amplifier 342, and a phase compensation circuit 343 that performs phase compensation for the transconductance amplifier 341 and the amplifier 342. The input of the amplifier 342 is connected to the output of the transconductance amplifier 341, and the output of the amplifier 342 becomes the output terminal of the chopper-stabilized amplifier.

[0053] The phase compensation circuit 343 is composed of capacitors Cc1 to Cc3. The capacitor Cc1 is connected between the input and output of the amplifier 342. The capacitor Cc2 is connected between the inverting input of the transconductance amplifier 341 and the output of the amplifier 342. The capacitor Cc3 is connected between the non-inverting input of the transconductance amplifier 341 and ground. In addition, a transconductance amplifier 35 functioning as a feedforward amplifier may be connected between the output of the transconductance amplifier 341 and the input of the amplifier 342.

[0054] 17, the chopper modulator 33 is provided with a noise reduction loop circuit 331. As shown in the figure, the chopper modulator 33 includes the noise reduction loop circuit 331 and a chopper modulator main body 333.

[0055] The noise reduction loop circuit 331 is a circuit that extracts the offset component of the transconductance amplifier 32 and negatively feeds back the extracted offset component and low-frequency noise component to the output of the transconductance amplifier 32. The noise reduction loop circuit 331 reduces the offset component and low-frequency noise component generated in the transconductance amplifier 32, thereby reducing the ripple noise included in the output of the chopper modulator 33 (see FIGS. 16(B) and 16(C)).

[0056] The noise reduction loop circuit 331 has an input connected to the output of the transconductance amplifier 32 and includes the amplifying devices 1A to 1C shown in the first to fourth embodiments described above that amplify the input, a filter circuit 334 that reduces high-frequency signal components in the outputs of the amplifying devices 1A to 1C, and a transconductance amplifier 335 that amplifies the output of the filter circuit 334 and applies it to the output of the transconductance amplifier 32. The noise reduction loop circuit 331 extracts the offset component of the transconductance amplifier 32 using the filter circuit 334 and feeds it back to the output of the transconductance amplifier 32, thereby reducing the offset component and low-frequency noise.

[0057] The chopper modulator 33 may be provided with a ripple calibration circuit 332 as shown in Fig. 18. As shown in the figure, the chopper modulator 33 includes a ripple calibration circuit 332 and a chopper modulator main body 333. The ripple calibration circuit 332 is a circuit that extracts high-frequency noise components (ripple noise) from the output of the chopper modulator 33, modulates the extracted ripple noise into an offset component, and negatively feeds back the modulated offset component to the output of the transconductance amplifier 32. The ripple calibration circuit 332 reduces the offset component included in the output of the transconductance amplifier 32, thereby reducing the ripple noise included in the output of the chopper modulator 33 (see Figs. 16(B) and (C)).

[0058] The ripple calibration circuit 332 has an input connected to the output of the chopper modulator 33 and includes a high-pass filter 336 that reduces the input low-frequency noise components and detects ripple noise, a phase-inverting auto-zero amplifier 337 that demodulates the ripple noise at the output of the high-pass filter 336 into low-frequency components and modulates it into an offset component, a filter circuit 338 that reduces the high-frequency components at the output of the phase-inverting auto-zero amplifier 337, and a transconductance amplifier 339 that amplifies the output of the filter circuit 338 and applies it to the output of the transconductance amplifier 32.

[0059] The phase-inverting auto-zero amplifier 337 is configured with two auto-zero amplifiers 21A to 21C, 22A to 22C described in the first to fourth embodiments. The auto-zero amplifiers 21A to 21C invert and amplify their inputs. The auto-zero amplifiers 22A to 22C non-invert and amplify their inputs. With the phase-inverting auto-zero amplifier 337 configured as described above, when the two auto-zero amplifiers 21A to 21C, 22A to 22C are alternately switched between amplification mode and calibration mode, they are alternately switched between inverting amplification and non-inverting amplification. This allows the phase-inverting auto-zero amplifier 337 to modulate the input.

[0060] The present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. Furthermore, the material, shape, size, number, location, etc. of each component in the above-described embodiments are arbitrary and not limited as long as they can achieve the present invention.

[0061] For example, the output stage amplifier 34A shown in the fifth embodiment is composed of a transconductance amplifier 341 and an amplifier 342, but this is not limited to this. For example, as shown in FIG. 19, an amplifier 34B composed of two transconductance amplifiers 344 and 345 may be provided. In the example shown in FIG. 19, a phase compensation circuit 346 is composed of two capacitors Cc4 and Cc5. Capacitor Cc4 is connected between the inverting input and the positive output of the transconductance amplifier 344. Capacitor Cc5 is connected between the non-inverting input and the negative output of the transconductance amplifier 344.

[0062] Furthermore, in the above-described embodiment, the amplifying devices 1A to 1C include two auto-zero amplifiers 21A to 21C and 22A to 22C, but this is not limited to this. The amplifying devices may include three or more auto-zero amplifiers. At least one of the three or more auto-zero amplifiers is controlled to be in amplification mode.

[0063] Furthermore, in the above-described embodiment, in the glitch calibration mode, the output terminal and the output of the transconductance amplifier 201 are connected via the transconductance amplifiers 205 and 206 with a 1x buffer configuration, thereby bringing the output voltage V1 closer to the output voltage V2 without affecting the output terminal. However, this is not limitative. A capacitor may be used to bring the output voltage V1 closer to the output voltage V2. [Explanation of symbols]

[0064] 1A~1C amplifier 21A~21C Auto-zero amplifier (first auto-zero amplifier) 22A~22C Auto-zero amplifier (second auto-zero amplifier) 201 Transconductance amplifier (first amplifier) 205, 206 Transconductance amplifier (second amplifier) 207, 208 1x buffer 209 Filter Circuit

Claims

1. an offset calibration mode in which the output terminal is separated from the output of the first amplifier, and a calibration signal is sampled to reduce the offset component and low-frequency noise component of the output voltage output from the output of the first amplifier; an amplification mode in which the output terminal and the output of the first amplifier are connected to each other, and the output voltage output from the output of the first amplifier, in which the offset component and the low-frequency noise component are reduced by the calibration signal, is output from the output terminal; an auto-zero amplifier switchable between a glitch calibration mode and a glitch correction mode in which, while the output terminal and the output of the first amplifier are disconnected, the output voltage output from the output of the first amplifier is made to approach a fixed output voltage output from the output terminal; a control circuit that switches the auto-zero amplifier between the offset calibration mode, the glitch calibration mode, and the amplification mode in this order, and repeats this switching; the auto-zero amplifier includes a second amplifier; the control circuit controls connection of the second amplifier so that, in the glitch correction mode, an input of the second amplifier configured as a 1x buffer is connected to the output terminal and an output of the second amplifier is connected to an output of the first amplifier; a plurality of the auto-zero amplifiers are provided for one of the output terminals; the control circuit, when controlling at least one of the plurality of auto-zero amplifiers to the amplification mode, controls one or more other auto-zero amplifiers to the offset calibration mode or the glitch calibration mode; Amplification device.

2. 2. The amplifier device according to claim 1, the auto-zero amplifier has a first switch connected between one of the two inputs of the second amplifier and the output of the second amplifier; the control circuit turns on the first switch in the glitch correction mode to set the second amplifier in a 1x buffer configuration, and turns off the first switch in the amplification mode to set the second amplifier in an amplifier configuration, and controls the connection of the second amplifier so that the input of the second amplifier in the amplifier configuration is connected to an input terminal connected to the input of the first amplifier, and the output of the second amplifier is connected to the output of the first amplifier. Amplification device.

3. 3. The amplifier device according to claim 2, the auto-zero amplifier includes a 1x buffer; the control circuit controls connection of the 1x buffer so that, in the offset calibration mode, the input of the 1x buffer is connected to the output terminal and the output of the 1x buffer is connected to the input of the second amplifier. Amplification device.

4. 3. The amplifier device according to claim 1, the auto-zero amplifier has a filter circuit connected between the input of the second amplifier and the output terminal; Amplification device.

5. an offset calibration mode in which the output terminal is separated from the output of the first amplifier, and a calibration signal is sampled to reduce the offset component and low-frequency noise component of the output voltage output from the output of the first amplifier; an amplification mode in which the output terminal and the output of the first amplifier are connected to each other, and the output voltage output from the output of the first amplifier, in which the offset component and the low-frequency noise component are reduced by the calibration signal, is output from the output terminal; an auto-zero amplifier switchable between a glitch calibration mode and a glitch correction mode in which, while the output terminal and the output of the first amplifier are disconnected, the output voltage output from the output of the first amplifier is made to approach a fixed output voltage output from the output terminal; a control circuit that switches the auto-zero amplifier between the offset calibration mode, the glitch calibration mode, and the amplification mode in this order, and repeats this switching; The auto-zero amplifiers include a first auto-zero amplifier that performs inverting amplification for one of the output terminals in the amplification mode, and a second auto-zero amplifier that performs non-inverting amplification for one of the output terminals in the amplification mode, the control circuit controls the second auto-zero amplifier to the amplification mode when controlling the first auto-zero amplifier to the offset calibration mode or the glitch calibration mode, and controls the first auto-zero amplifier to the amplification mode when controlling the second auto-zero amplifier to the offset calibration mode or the glitch calibration mode. Amplification device.

6. The amplifier device according to any one of claims 1 to 5, the control circuit controls the auto-zero amplifier in the glitch calibration mode for a period of time shorter than the period of time in the offset calibration mode; Amplification device.

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