Photoelectric conversion device

Abstract

To provide a photoelectric conversion device that has reduced a correction error.SOLUTION: In a first drive mode of acquiring a correction amount, an analog-digital conversion unit compares a first analog signal with a reference signal to acquire the correction amount. In a second drive mode of reading a pixel signal, based on a result of the comparison of the pixel signal with a threshold signal, a condition for reading is set. In a third drive mode, at least one of the first analog signal and the threshold signal is controlled to reduce the difference between the electric potential of the first analog signal and the electric potential of the threshold signal.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] Patent Document 1 describes an imaging device having an analog-to-digital (AD) converter. The AD converter has a reference signal supply unit that outputs a first reference signal whose potential changes by a first amount per unit time and a second reference signal whose potential changes by a second amount per unit time that is larger than the first amount. The AD converter generates a digital signal by switching between the first and second reference signals and performing AD conversion according to the amount of incident light. Patent Document 1 also describes a technique for correcting errors in the digital signal caused by variations in the ratio between the amount of change in potential per unit time of the first reference signal and the amount of change in potential per unit time of the second reference signal.

[0003] Patent Document 2 describes a technology for performing AD conversion by switching the gain of an amplifier circuit that amplifies signals from pixels according to the amount of incident light. Patent Document 2 also describes a technology for correcting errors in digital signals that occur due to variations in the gain ratio. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-140152 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-079464 Summary of the Invention [Problem to be solved by the invention]

[0005] In the signal correction techniques after AD conversion as described in Patent Documents 1 and 2, there is a demand for a method that can further reduce correction errors in order to improve signal quality. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a photoelectric conversion device that can further reduce correction errors. [Means for solving the problem]

[0006] According to one aspect of the present invention, a comparison circuit that compares a potential of the signal output from the amplifier with a potential of the reference signal and outputs a comparison result signal, and an analog-to-digital converter that performs analog-to-digital conversion of the input signal based on the comparison result signal, wherein in a first drive mode in which correction values ​​are obtained for the signals amplified by the first gain and the second gain, the analog-to-digital converter generates a first digital signal based on the comparison result signal output by the comparison circuit by comparing a signal obtained by amplifying the first analog signal by the first gain with the reference signal, and generates a second digital signal based on the comparison result signal output by the comparison circuit by comparing a signal obtained by amplifying the first analog signal by the second gain with the reference signal, and and in a second drive mode in which a pixel signal based on an output from the pixel is read, the comparator circuit compares a potential of the pixel signal with a potential of a threshold signal, the amplifier is set to the first gain when the potential of the pixel signal is smaller than the potential of the threshold signal, and is set to the second gain when the potential of the pixel signal is equal to or larger than the potential of the threshold signal, and the analog-to-digital converter performs analog-to-digital conversion of the pixel signal amplified by the set first gain or the second gain, and controls at least one of the first analog signal and the threshold signal, based on a comparison result signal output by the comparator circuit comparing the signal amplified by the first gain with the threshold signal, at least one of the first analog signal and the threshold signal is controlled so as to reduce a difference between a potential of the signal amplified by the first gain and a potential of the threshold signal. is provided.

[0007] According to another aspect of the present invention, The above Photoelectric conversion device Equipment equipped with is provided. [Effects of the Invention]

[0008] According to the present invention, a photoelectric conversion device capable of further reducing correction errors is provided. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a photoelectric conversion device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram of a pixel according to the first embodiment. [Figure 3] FIG. 2 is a circuit diagram of a test signal supply unit according to the first embodiment. [Figure 4] 1 is a diagram illustrating a configuration of a digital signal processor according to a first embodiment. [Figure 5] FIG. 3 is a timing chart showing the operation of the photoelectric conversion device according to the first embodiment. [Figure 6] 5A to 5C are diagrams illustrating a level shift operation according to the first embodiment. [Figure 7] 10 is a graph illustrating a case where correction value calculation is not performed. [Figure 8] FIG. 4 is a timing chart showing a correction value calculation operation according to the first embodiment. [Figure 9] 10 is a graph illustrating a case where correction value calculation is not performed. [Figure 10] 10 is a graph illustrating an offset caused by calculation of a correction value. [Figure 11]10 is a graph illustrating a case where no offset occurs due to correction value calculation. [Figure 12] 5 is a timing chart illustrating a correction value calculation potential adjustment operation according to the first embodiment. FIG. [Figure 13] FIG. 10 is a diagram illustrating an example of the configuration of a photoelectric conversion device according to a second embodiment. [Figure 14] FIG. 10 is a diagram illustrating an example of the configuration of a column amplifier according to a second embodiment. [Figure 15] FIG. 10 is a diagram illustrating an example of the configuration of a comparison gain setting circuit according to a second embodiment. [Figure 16] FIG. 10 is a diagram illustrating an example of the configuration of a test signal supply unit according to the second embodiment. [Figure 17] FIG. 10 is a timing chart illustrating the operation of the photoelectric conversion device according to the second embodiment. [Figure 18] 10 is a graph illustrating calculation of a correction value according to the second embodiment. [Figure 19] FIG. 10 is a timing chart showing a correction value calculation operation according to the second embodiment. [Figure 20] 10 is a graph illustrating a case where correction value calculation is not performed. [Figure 21] 10 is a graph illustrating an offset caused by calculation of a correction value. [Figure 22] 10 is a graph illustrating a case where no offset occurs due to correction value calculation. [Figure 23] FIG. 10 is a timing chart illustrating a correction value calculation potential adjustment operation according to the second embodiment. [Figure 24] 11 is a graph showing the relationship between a test signal and an offset according to the third embodiment. [Figure 25] FIG. 10 is a circuit diagram of a test signal generation circuit according to a fourth embodiment. [Figure 26] FIG. 10 is a circuit diagram of a test signal generation circuit according to a fifth embodiment. [Figure 27] FIG. 13 is a timing chart illustrating a correction value calculation potential adjustment operation according to the sixth embodiment. [Figure 28]FIG. 13 is a timing chart illustrating a correction value calculation and potential adjustment operation according to the seventh embodiment. [Figure 29] FIG. 13 is a timing chart illustrating a correction value calculation and potential adjustment operation according to the eighth embodiment. [Figure 30] FIG. 13 is a block diagram of a device according to a ninth embodiment. [Figure 31] FIG. 19 is a block diagram of a device according to a tenth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Identical or corresponding elements throughout the drawings are designated by common reference numerals, and their description may be omitted or simplified. In each of the following embodiments, an imaging device will be mainly described as an example of a photoelectric conversion device. However, the photoelectric conversion device in each embodiment is not limited to an imaging device and may also be applied to other devices. Examples of other devices include a range finder and a photometric device. The range finder may be, for example, a focus detection device, a distance measurement device using TOF (Time-Of-Flight), etc. The photometric device may be a device that measures the amount of light incident on the device.

[0011] [First embodiment] Fig. 1 is a schematic block diagram of a photoelectric conversion device 100 according to this embodiment. The photoelectric conversion device 100 shown in Fig. 1 is an imaging device that acquires an image. Although the photoelectric conversion device 100 shown in Fig. 1 is formed on the same semiconductor substrate, the elements that make up the photoelectric conversion device 100 may be formed separately on multiple semiconductor substrates.

[0012] The photoelectric conversion device 100 includes a pixel section 10, a vertical scanning circuit 15, an amplifier section 20, a reference signal supply section 25, a comparator section 30, a counter 40, a memory section 50, and a horizontal scanning circuit 60. The photoelectric conversion device 100 also includes a timing generator (TG) 70, a digital signal processor (DSP) 80, an output circuit 90, and a test signal supply section 200.

[0013] The pixel unit 10 has a plurality of pixels 1 arranged in a plurality of rows and a plurality of columns. Each pixel 1 outputs a signal corresponding to the scanning of a control signal output from a vertical scanning circuit 15 to an amplifier unit 20 via a column signal line 2. The pixel 1 has a photoelectric conversion unit that photoelectrically converts incident light. The pixel 1 outputs a signal corresponding to the amount of received light. The pixel signal based on the output from the pixel 1 includes a reset signal based on the reset state of the pixel 1 and a photoelectric conversion signal based on the charge obtained by photoelectrically converting the incident light.

[0014] The vertical scanning circuit 15 supplies control signals for controlling the transistors included in the pixels 1 to be on (conductive state) or off (non-conductive state) based on the signals output from the TG 70 via control signal lines provided in each row of the pixel unit 10. The vertical scanning circuit 15 can be configured by logic circuits such as a shift register and an address decoder.

[0015] The amplifier unit 20 is provided on an electrical path between the comparator unit 30 and the pixel 1. The amplifier unit 20 may have a column amplifier unit provided corresponding to each column of the pixel unit 10. The amplifier unit 20 amplifies the signal output from the pixel 1 of each column and outputs the amplified signal to the comparator unit 30.

[0016] The comparator 30 includes a comparison circuit 301, a selection circuit 302, and a switch 303, each provided for each column of the pixel unit 10. The reference signal supply unit 25 outputs a plurality of reference signals Vr1 and Vr2 to the selection circuit 302 of each column under the control of the TG 70. The comparison circuit 301 receives the output signal of the amplifier 20 and the output signal of the selection circuit 302. The switch 303 is connected between the output terminal of the comparison circuit 301 and the selection signal input terminal of the selection circuit 302. The switch 303 is controlled to be turned on or off based on a control signal SC1 output from the TG 70. The comparison circuit 301 outputs a selection signal SEL to the selection circuit 302 via the switch 303 based on a comparison result signal CMP indicating the result of comparing the output signal of the amplifier 20 with a threshold signal. The selection circuit 302 selects a reference signal to be output to the comparison circuit 301 from the plurality of reference signals Vr1 and Vr2 based on the selection signal SEL. The threshold signal is a signal that corresponds to the potential of the reference signal Vr1 during a predetermined period.

[0017] The comparator circuit 301 outputs a comparison result signal CMP indicating the result of comparing the signal output by the amplifier unit 20 with the reference signal Vr1 or Vr2 to the memory unit 50. The memory unit 50 has a flag memory 501, a first memory 502, and a second memory 503 provided corresponding to each column of the pixel unit 10. The TG70 outputs a control signal F_En to the flag memory 501, a control signal M1_En to the first memory 502, and a control signal M2_En to the second memory 503. These control signals are input in common to the memories of each column. The counter 40, under the control of the TG70, counts the number of externally input clock signals CLK and outputs count signals to the first memory 502 and the second memory 503.

[0018] The first memory 502 and the second memory 503 hold a count signal indicating the time from when the potential of the reference signal Vr1 or Vr2 starts to change until the magnitude relationship with the potential of the output signal of the amplifier unit 20 is reversed. As a result, the first memory 502 and the second memory 503 hold a signal obtained by converting the output signal of the amplifier unit 20 into a digital signal. The analog-to-digital converter (AD converter) 110 includes a comparison circuit 301, a selection circuit 302, a switch 303, a flag memory 501, the first memory 502, and the second memory 503. The AD converter 110 has a function of performing analog-to-digital conversion (AD conversion) of the output signal of the amplifier unit 20 and holding the generated digital signal. The AD converter 110 is provided corresponding to each column of the pixel unit 10.

[0019] The horizontal scanning circuit 60, under the control of the TG 70, performs horizontal transfer to sequentially output the digital signals held in the flag memory 501, the first memory 502, and the second memory 503 of each column to the DSP 80. The horizontal scanning circuit 60 can be configured with logic circuits such as a shift register and an address decoder.

[0020] The DSP 80 processes the signals output from the flag memory 501, the first memory 502, and the second memory 503, and outputs the processed signals to the output circuit 90. The output circuit 90 outputs the signals to the outside of the photoelectric conversion device 100 in accordance with the control of the TG 70.

[0021] The test signal supplying section 200 receives the control signals SC2 and SC3 output from the TG 70 and the control signal from the DSP 80. The test signal supplying section 200 outputs test signals VS1 and VS2 to the column signal lines 2 based on these control signals.

[0022] FIG. 2 is a circuit diagram of a pixel 1 according to the first embodiment. The pixel 1 includes a photoelectric conversion unit PD, a transfer transistor MTX, a reset transistor MRS, an amplifier transistor MSF, and a selection transistor MSEL. These transistors are configured as NMOS transistors having gates as control electrodes. Control signals φPTX, φPRS, and φPSEL for controlling these transistors are input to the gates of the transfer transistor MTX, the reset transistor MRS, and the selection transistor MSEL from the vertical scanning circuit 15 via control signal lines. When these control signals are at an H level (high level), the corresponding transistors are turned on, and when these control signals are at an L level (low level), the corresponding transistors are turned off. Note that these transistors may be PMOS transistors, in which case the designations of the gate and drain, the relationship between the level of the control signal and on / off, and the like may be changed as appropriate.

[0023] The photoelectric conversion unit PD is a photoelectric conversion element that generates charges according to incident light through photoelectric conversion and accumulates the charges. The photoelectric conversion unit PD can be configured with a photodiode formed in a semiconductor substrate. The anode of the photodiode that configures the photoelectric conversion unit PD is connected to a ground wiring that supplies a ground potential. The cathode of the photodiode that configures the photoelectric conversion unit PD is connected to the source of the transfer transistor MTX.

[0024] The drain of the transfer transistor MTX, the source of the reset transistor MRS, and the gate of the amplification transistor MSF are connected to the floating diffusion FD. When the transfer transistor MTX is turned on, it transfers the charge of the photoelectric conversion unit PD to the floating diffusion FD. Due to the capacitance of the floating diffusion FD, the potential of the floating diffusion FD changes depending on the charge transferred from the photoelectric conversion unit PD.

[0025] The drain of the reset transistor MRS and the drain of the amplifying transistor MSF are connected to a power supply wiring having a power supply potential. The source of the amplifying transistor MSF is connected to the drain of the selecting transistor MSEL. The source of the selecting transistor MSEL is connected to a column signal line 2. The amplifying transistor MSF forms a source follower circuit together with a current source (not shown) connected to the column signal line 2. This source follower circuit outputs a signal based on the potential of the floating diffusion FD to the column signal line 2 via the selecting transistor MSEL. The reset transistor MRS resets the potential of the floating diffusion FD by turning on.

[0026] The pixel 1 also has a microlens and a color filter arranged on the optical path of incident light before it is guided to the photoelectric conversion unit PD. The microlens focuses the incident light onto the photoelectric conversion unit PD. The color filter selectively transmits light of a predetermined color.

[0027] 3 is a circuit diagram showing an example of the configuration of the test signal supply unit 200. The test signal supply unit 200 (analog signal supply unit) has a test signal selection unit 201, a test signal supply line 202, and a plurality of switches 203. The test signal selection unit 201 has a multiplexer MX0. Test signals VS1 and VS2 of different potentials are input to two input terminals of the multiplexer MX0, respectively. A control signal SC2 output from the TG70 is input to a control terminal of the multiplexer MX0. An output terminal of the multiplexer MX0 is connected to the test signal supply line 202. Either the test signal VS1 or the test signal VS2 is output to the test signal supply line 202 based on the level of the control signal SC2.

[0028] In this embodiment, the potential of the test signal VS1 corresponds to the potential of the reset signal of the pixel 1. In addition, in this embodiment, the potential of the test signal VS2 is a predetermined value that is equal to or lower than the peak potential of the reference signal Vr1. In addition, the potential of the test signal VS2 is controlled in response to a control signal from the DSP 80.

[0029] The multiple switches 203 are arranged corresponding to the multiple column signal lines 2. First terminals of the multiple switches 203 are connected to the test signal supply line 202. Second terminals of each of the multiple switches 203 are connected to the column signal line 2 of the corresponding column. A control signal SC3 output from the TG70 is input to control terminals of the multiple switches 203. The multiple switches 203 are turned on when the control signal SC3 is at H level, and are turned off when the control signal SC3 is at L level. When the multiple switches 203 are turned on, a potential based on either the test signal VS1 or the test signal VS2 is output to the column signal line 2.

[0030] FIG. 4 is a diagram showing the configuration of a DSP 80 according to this embodiment. The configuration of the components other than the DSP 80 is the same as that shown in FIG. 1 , and therefore description thereof will be omitted. The DSP 80 includes a level shift unit 81, a correction value acquisition unit 82, a correction calculation unit 83, and a difference acquisition unit 84. The level shift unit 81 shifts each bit of the signal stored in the first memory 502 to higher order by two bits when the signal value stored in the flag memory 501 is at the L level. When performing the correction operation shown in FIG. 8 , the level shift unit 81 outputs a signal to the correction value acquisition unit 82. The correction value acquisition unit 82 also acquires a signal stored in the second memory 503. The correction value acquisition unit 82 generates a correction value based on these signals and outputs it to the correction calculation unit 83. The correction calculation unit 83 corrects the signal output from the level shift unit 81 and outputs the corrected signal to the difference acquisition unit 84. The difference acquisition unit 84 acquires the difference between the signal output from the correction calculation unit 83 and the signal output from the second memory 503, and outputs the difference to the output circuit 90. The DSP 80 is a correction unit in this embodiment.

[0031] FIG. 5 is a timing diagram showing the operation of the photoelectric conversion device 100 according to this embodiment. The operation of the photoelectric conversion device 100 will be described with reference to FIG. 5. Out_Amp shown in FIG. 5 indicates the potential of the output signal of the amplifier unit 20. Vr1 and Vr2 shown in FIG. 5 respectively indicate the potentials of the reference signals Vr1 and Vr2 output from the reference signal supply unit 25. As shown in FIG. 5, the slope of the potential of the reference signal Vr2 is larger than the slope of the potential of the reference signal Vr1. That is, the reference signal Vr1 is a first reference signal whose potential changes by a first change amount per unit time. Furthermore, the reference signal Vr2 is a second reference signal whose potential changes by a second change amount per unit time that is larger than the first change amount.

[0032] Vr_Cmp shown in FIG. 5 indicates the potential of the reference signal Vr_Cmp that the selection circuit 302 selects and outputs to the comparison circuit 301, either the reference signal Vr1 or Vr2. CMP shown in FIG. 5 indicates the potential of the comparison result signal CMP, which indicates the result of the comparison circuit 301 comparing the potential of the output signal Out_Amp of the amplifier unit 20 with the potential of the reference signal Vr_Cmp. The comparison result signal CMP temporarily goes high when the potential of the reference signal Vr_Cmp becomes greater than the potential of the output signal Out_Amp of the amplifier unit 20, reversing the magnitude relationship. A control signal SC1 shown in FIG. 5 is a signal that controls the conduction of the switch 303, and when the control signal SC1 is high, the switch 303 is turned on.

[0033] 5 also shows control signals F_En, M1_En, and M2_En. When the control signal F_En goes high, the flag memory 501 holds the comparison result signal CMP. The control signals M1_En and M2_En are signals that enable the first memory 502 and the second memory 503 to hold the count signal, respectively. The first memory 502 holds the count signal when the control signal M1_En is high and the signal value of the comparison result signal CMP changes. The second memory 503 holds the count signal when the control signal M2_En is high and the signal value of the comparison result signal CMP changes.

[0034] At time t1, the comparison result signal CMP and the control signals SC1, F_En, M1_En, and M2_En are at L level, and the selection signal SEL is at H level.

[0035] At time t2, a reset signal is output from the pixel 1. The amplifier 20 outputs a signal obtained by amplifying the reset signal, which changes the potential of the output signal Out_Amp of the amplifier 20.

[0036] At time t3, the reference signal supplying unit 25 starts changing the potential of the reference signal Vr1 depending on time. When the selection signal SEL is at H level, the selection circuit 302 selects the reference signal Vr1 from the input reference signals Vr1 and Vr2 and outputs it to the comparison circuit 301. Also, at time t3, the control signal M2_En becomes H level.

[0037] At time t4, the magnitude relationship between the output signal Out_Amp of the amplifier unit 20 and the reference signal Vr_Cmp is reversed, and the signal value of the comparison result signal CMP changes. Because the control signal M1_En is at L level and the control signal M2_En is at H level, the second memory 503 holds the count signal at this time.

[0038] At time t5, the reference signal supplying unit 25 stops the time-dependent change of the potential of the reference signal Vr1 and sets the potential of the reference signal Vr1 to the potential at time t3. Also, the TG 70 sets the control signal M2_En to L level.

[0039] At time t6, the pixel 1 outputs a photoelectric conversion signal. The amplifier 20 outputs a signal obtained by amplifying the photoelectric conversion signal to the comparison circuit 301. This causes the potential of the output signal Out_Amp of the amplifier 20 to change.

[0040] At time t7, the reference signal supplying unit 25 raises the potential of the reference signal Vr1 to the potential of the threshold signal VREF. The potential of the threshold signal VREF is a predetermined potential that is equal to or lower than the peak potential of the reference signal Vr1 at time t11, which will be described later. When the potential of the output signal of the amplifying unit 20 is equal to or higher than the potential of the threshold signal VREF, the comparing circuit 301 outputs an L-level comparison result signal CMP. Conversely, when the potential of the output signal of the amplifying unit 20 is lower than the potential of the threshold signal VREF, the comparing circuit 301 outputs an H-level comparison result signal CMP. Here, it is assumed that the potential of the output signal of the amplifying unit 20 is lower than the potential of the threshold signal VREF, and the comparison result signal CMP is at an L-level.

[0041] Also, at time t7, the control signal SC1 output by the TG70 goes high, causing the comparison result signal CMP at low level to be output as the selection signal SEL from the comparison circuit 301 to the selection circuit 302. The selection circuit 302 selects the reference signal to be output to the comparison circuit 301 after time t9, based on the signal value of the selection signal SEL at time t7.

[0042] The relationship between the operation of the selection circuit 302 and the signal value of the selection signal SEL from time t7 to time t9 will be described. Even if the selection signal SEL goes low at time t7, the selection circuit 302 continues to output the reference signal Vr1 to the comparison circuit 301 during the period from time t7 to time t9. Then, based on the signal value of the selection signal SEL, the selection circuit 302 selects either the reference signal Vr1 or Vr2 as the reference signal to be output after time t9.

[0043] Also, at time t7, the TG 70 sets the control signal F_En to level H. As a result, the flag memory 501 holds the comparison result signal CMP at time t7, that is, the comparison result signal CMP at level L.

[0044] At time t8, the reference signal supplying unit 25 reduces the potential of the reference signal Vr1 to the potential at time t3, and the TG 70 sets the control signal F_En to the L level.

[0045] At time t9, the reference signal supplying unit 25 starts changing the potentials of the reference signals Vr1 and Vr2 depending on time. Based on the low-level selection signal SEL, the selection circuit 302 selects the reference signal Vr2 from the input reference signals Vr1 and Vr2 and outputs it to the comparison circuit 301. The TG 70 sets the control signal M1_En to the high level.

[0046] At time t10, the magnitude relationship between the output signal Out_Amp of the amplifier unit 20 and the reference signal Vr_Cmp is reversed, and the signal value of the comparison result signal CMP changes. Because the control signal M1_En is at H level and the control signal M2_En is at L level, the first memory 502 holds the count signal at this time.

[0047] At time t11, the reference signal supplying unit 25 stops the time-dependent change of the potentials of the reference signals Vr1 and Vr2, and sets the potential of the reference signal Vr1 to the potential at time t3. The TG 70 sets the control signal M1_En to the L level.

[0048] After time t11, the horizontal scanning circuit 60 sequentially scans the memory units 50 of each column, and causes the flag memory 501, the first memory 502, and the second memory 503 of each column to output the digital signals held therein to the DSP 80.

[0049] FIG. 6 is a diagram illustrating the level shift operation according to this embodiment. The operation of the level shift unit 81 of the DSP 80 will be described with reference to FIG. 6. DN in FIG. 6 is a schematic representation of a digital signal held in the second memory 503. DS-1 in FIG. 6 is a schematic representation of a digital signal obtained by comparing the reference signal Vr1 with the output signal of the amplifier unit 20 and held in the first memory 502. DS-2 in FIG. 6 is a digital signal obtained by comparing the reference signal Vr2 with the output signal of the amplifier unit 20 and held in a first memory 502 in a column different from the first memory 502 in which the digital signal of DS-1 is held. Data0 to Data13 indicate the values ​​of each bit constituting the digital signal.

[0050] As shown in FIG. 6, the digital signal stored in the second memory 503 is 10 bits, and the digital signal stored in the first memory 502 is 12 bits. FIG. 6 illustrates an example in which the amount of change in potential per unit time of the reference signal Vr2 is four times the amount of change in potential per unit time of the reference signal Vr1. In this case, to correct the difference in conversion rate during AD conversion, the value of the digital signal DS-2 must be four times the value of the digital signal DS-1. Since log24=2, the operation of quadrupling a binary number is equivalent to shifting the value of each bit two bits higher. Therefore, the level shift unit 81 shifts each bit of the digital signal DS-2 two bits higher to generate the digital signal ED_DS-2. FIG. 6 illustrates the digital signal ED_DS-2 obtained by level shifting.

[0051] The difference acquiring unit 84 subtracts the digital signal DN from the digital signal DS-1. Then, the difference acquiring unit 84 sets the signal values ​​of Data12 and Data13 (the most significant two bits) to 0 and outputs the result as a 14-bit signal to the output circuit 90. The difference acquiring unit 84 also sets the signal values ​​of Data0 and Data1 (the least significant two bits) of the digital signal ED_DS-2 to 0, and then subtracts the digital signal DN. As a result, the digital signal output from the DSP 80 becomes a 14-bit signal from Data0 to Data13. Note that the history of whether the digital signal held in the first memory 502 was obtained using the reference signal Vr1 or Vr2 can be determined based on the signal held in the flag memory 501. That is, in the operation shown in FIG. 5, if the signal held in the flag memory 501 is at an H level, the signal held in the first memory 502 is a signal obtained using the reference signal Vr1. Similarly, if the signal held in the flag memory 501 is at L level, the signal held in the first memory 502 is a signal obtained using the reference signal Vr2.

[0052] 7 is a graph illustrating a case where the correction value calculation is not performed. First, the signal value of the digital signal obtained when the correction operation of this embodiment is not performed will be described with reference to FIG.

[0053] Fig. 7 shows the relationship between the amount of incident light and the digital signal value output by the DSP 80 when the correction of this embodiment, which will be described later, is not performed. The horizontal axis of Fig. 7 shows the amount of incident light to the photoelectric conversion unit PD of pixel 1, and the vertical axis of Fig. 7 shows the signal value of the digital signal output from the DSP 80. Note that the digital signal value is actually a discrete value, but is shown as a continuous value for simplicity.

[0054] In FIG. 7, line LX indicates the relationship between the amount of incident light and the digital signal value when AD conversion is performed using reference signal Vr1. Also, in FIG. 7, lines LY1 and LY2 indicate the relationship between the amount of incident light and the digital signal value when AD conversion is performed using reference signal Vr2. IL in FIG. 7 indicates the region where reference signal Vr1 is selected as the reference signal to be compared with the output signal of amplifier 20. IH in FIG. 7 indicates the region where reference signal Vr2 is selected as the reference signal to be compared with the output signal of amplifier 20. IO in FIG. 7 is the boundary between IL and IH. The solid line graph in FIG. 7 indicates the relationship between the amount of incident light and the digital signal value generated by AD conversion using reference signal Vr1 in region IL and reference signal Vr2 in region IH. The dashed line graph in FIG. 7 indicates the relationship between the amount of incident light and the digital signal generated by AD conversion using reference signal Vr1 in region IH.

[0055] Lines LY1 and LY2 will be described in detail. Line LY1 indicates the case where the ratio of the amount of change in potential per unit time of reference signal Vr2 to the amount of change in potential per unit time of reference signal Vr1 is exactly four times. On the other hand, line LY2 indicates the case where the ratio of the amount of change in potential per unit time of reference signal Vr2 to the amount of change in potential per unit time of reference signal Vr1 is less than four times due to an error. Note that the intercepts of lines LY1 and LY2 are both offset from the intercept of line LX due to an error. At the boundary IO between region IL and region IH, the digital signal values ​​corresponding to line LX and line LY1 are denoted as D1io and D2io, respectively. Furthermore, at the boundary IO, the digital signal value corresponding to line LY2 is denoted as D3io. As described above, because the ratio of the amount of change in potential per unit time of reference signal Vr2 to the amount of change in potential per unit time of reference signal Vr1 is less than four times, D3io is smaller than D2io. In this way, a difference (offset) in the digital signal value may occur between the line LX and the line LY2 at the boundary IO. The photoelectric conversion device 100 of this embodiment performs a correction operation to reduce this difference.

[0056] FIG. 8 is a timing diagram illustrating the correction value calculation operation according to this embodiment. The correction operation of the photoelectric conversion device 100 of this embodiment will be described with reference to FIG. 8. Control signals SC2 and SC3 shown in FIG. 8 are signals that control the multiplexer MX0 and the multiple switches 203 of the test signal supply unit 200. When the control signal SC2 is at an H level, the multiplexer MX0 selects and outputs the test signal VS1. When the control signal SC2 is at an L level, the multiplexer MX0 selects and outputs the test signal VS2. When the control signal SC3 is at an H level, the switch 203 is turned on, and when the control signal SC3 is at an L level, the switch 203 is turned off. In FIG. 8, the "operation" in the "count" column indicates the period during which the counter 40 counts the clock signal CLK and outputs a count signal, and the "stop" in the "count" column indicates the period during which the counter 40 does not output a count signal. The reference signal Vr_Cmp in FIG. 8 is illustrated with a potential corresponding to the test signal VS1 or VS2 supplied to the column signal line 2 superimposed thereon.

[0057] At time t40, the control signal SC3 goes high, turning on the switches 203. This causes the signal on the test signal supply line 202 to be output to the column signal line 2 of each column. Also, at time t40, the selection signal SEL is high, and the reference signal Vr1 is input to the comparison circuit 301.

[0058] At time t41, the TG 70 sets the control signal SC2 to H level, which causes the test signal VS1 to be output to the column signal line 2 of each column via the test signal supply line 202 and the switch 203 (second analog signal).

[0059] At time t42-1, the reference signal supplying unit 25 starts changing the potential of the reference signal Vr1 depending on time. The TG 70 also sets the control signal M2_En to H level. Subsequently, at time t42-2, the counter 40 starts counting the clock signal CLK and outputting the count signal.

[0060] At time t43, the magnitude relationship between the potential of the test signal VS1 and the potential of the reference signal Vr1 is reversed, and the signal value of the comparison result signal CMP changes. The second memory 503 holds the count signal at this time. Hereinafter, the count signal held by the second memory 503 at this time will be referred to as a digital signal DN1. The digital signal DN1 is a third digital signal generated by the AD conversion unit 110 based on the comparison result signal CMP output by the comparison unit 30 by comparing the first reference signal with the second analog signal.

[0061] At time t44, the reference signal supplying section 25 stops the time-dependent change in potential of the reference signal Vr1, and the counter 40 stops counting the clock signal CLK and outputting the count signal.

[0062] At time t45, the TG 70 sets the control signal SC2 to level L. As a result, the test signal VS2 is output to the column signal line 2 of each column via the test signal supply line 202 and the switch 203 (first analog signal).

[0063] At time t46-1, the reference signal supplying unit 25 starts changing the potential of the reference signal Vr1 over time. The TG 70 also sets the control signal M1_En to H level. Subsequently, at time t46-2, the counter 40 starts counting the clock signal CLK and outputting a count signal.

[0064] At time t47, the magnitude relationship between the potential of the test signal VS2 and the potential of the reference signal Vr1 is reversed, and the signal value of the comparison result signal CMP changes. The first memory 502 holds the count signal at this time. Hereinafter, the count signal held by the first memory 502 at this time will be referred to as a digital signal DS1. The digital signal DS1 is a first digital signal generated by the AD conversion unit 110 based on the comparison result signal CMP output by the comparison unit 30 by comparing the first reference signal with a first analog signal whose signal value is different from that of the second analog signal.

[0065] At time t48, the reference signal supply unit 25 stops changing the potential of the reference signal Vr1 depending on time. During the period from time t48 to time t50, the horizontal scanning circuit 60 sequentially transfers the signals held in the first memory 502 and the second memory 503 for each column to the DSP 80.

[0066] At time t49, the TG70 sets the control signal SC2 to H level, which causes the test signal VS1 to be output to the column signal line 2 of each column via the test signal supply line 202 and the switch 203 (second analog signal). In addition, the TG70 sets the selection signal SEL to L level.

[0067] At time t50-1, the reference signal supplying unit 25 starts changing the potential of the reference signal Vr2 depending on time. The TG 70 also sets the control signal M2_En to H level. Subsequently, at time t50-2, the counter 40 starts counting the clock signal CLK and outputting the count signal.

[0068] At time t51, the magnitude relationship between the potential of the test signal VS1 and the potential of the reference signal Vr2 is reversed, and the signal value of the comparison result signal CMP changes. The second memory 503 holds the count signal at this time. Hereinafter, the count signal held by the second memory 503 at this time will be referred to as a digital signal DN2. The digital signal DN2 is a fourth digital signal generated by the AD conversion unit 110 based on the comparison result signal CMP output by the comparison unit 30 by comparing the second reference signal with the second analog signal.

[0069] At time t52, the reference signal supplying unit 25 stops the time-dependent change in potential of the reference signal Vr2, and the counter 40 stops counting the clock signal CLK and outputting the count signal.

[0070] At time t53, the TG 70 sets the control signal SC2 to level L. As a result, the test signal VS2 is output to the column signal line 2 of each column via the test signal supply line 202 and the switch 203 (first analog signal).

[0071] At time t54-1, the reference signal supplying unit 25 starts changing the potential of the reference signal Vr2 depending on time. The TG 70 also sets the control signal M1_En to H level. Subsequently, at time t54-2, the counter 40 starts counting the clock signal CLK and outputting a count signal.

[0072] At time t55, the magnitude relationship between the potential of the test signal VS2 and the potential of the reference signal Vr2 is reversed, and the signal value of the comparison result signal CMP changes. The first memory 502 holds the count signal at this time. Hereinafter, the count signal held by the first memory 502 at this time will be referred to as a digital signal DS2. The digital signal DS2 is a second digital signal generated by the AD conversion unit 110 based on the comparison result signal CMP output by the comparison unit 30 after comparing the second reference signal with the first analog signal.

[0073] At time t56, the reference signal supplying unit 25 stops the time-dependent change in potential of the reference signal Vr2, and the counter 40 stops counting the clock signal CLK and outputting the count signal.

[0074] After time t56, the horizontal scanning circuit 60 sequentially transfers the signals held in the first memory 502 and the second memory 503 for each column to the DSP 80.

[0075] Next, the correction operation in this embodiment will be described. The correction value acquisition unit 82 acquires the correction values ​​α and β using the following equations (1) and (2). α = DS1-4 × β × DS2 (1) β=(DS1-DN1) / {4×(DS2-DN2)} (2)

[0076] The correction value acquisition unit 82 outputs the acquired correction values ​​α and β to the correction calculation unit 83. The digital signal held in the first memory 502 of the column where the flag memory 501 is at L level is shifted by two bits to higher order by the level shift unit 81 and output to the correction calculation unit 83. The correction calculation unit 83 performs correction on the signal bit-shifted by the level shift unit 81 based on the following equation (3). CAL_DS=α+ED_DS×β (3)

[0077] Here, ED_DS in equation (3) is a signal obtained by the level shifter 81 shifting the digital signal held in the first memory 502 of the column where the flag memory 501 is at L level by two bits to higher order and outputting the signal to the correction calculation unit 83. CAL_DS is a corrected digital signal output by the correction calculation unit 83.

[0078] On the other hand, for the digital signal held in the first memory 502 of the column where the flag memory 501 is at H level, the bit shift operation in the level shift unit 81 and the addition of the correction value α in the correction calculation unit 83 are not performed.

[0079] A linearity deviation may occur in the reference signal output from the reference signal supply unit 25. The potential of the reference signal is not completely linear with respect to time and may include non-linear portions. This may cause an error in AD conversion. FIG. 9 is a graph illustrating a case where a correction value is not calculated. The signal value of a digital signal obtained when a linearity deviation occurs and the correction operation of this embodiment is not performed will be described with reference to FIG. 9.

[0080] 7, Fig. 9 shows the relationship between the amount of incident light and the digital signal value output by the DSP 80. The horizontal axis of Fig. 9 shows the amount of incident light to the photoelectric conversion unit PD of the pixel 1, and the vertical axis of Fig. 9 shows the signal value of the digital signal output from the DSP 80.

[0081] 9, line LX shows the relationship between the amount of incident light and the digital signal value when AD conversion is performed using reference signal Vr1 with good linearity, and lines LY1 and LY2 show the relationship between the amount of incident light and the digital signal value when AD conversion is performed using reference signal Vr2.

[0082] At the boundary IO between the region IL and the region IH, the digital signal values ​​corresponding to the line LX, the line LY1, and the line LY2 are respectively designated as D1io, D2io, and D3io. Because the ratio of the amount of change in potential per unit time of the reference signal Vr2 to the amount of change in potential per unit time of the reference signal Vr1 is less than four times, D3io is smaller than D2io.

[0083] 9, a linearity deviation occurs in the reference signal Vr1 near the boundary IO. Due to the linearity deviation near the boundary IO, the digital signal value obtained by the reference signal Vr1 at the boundary IO is D4io, which is larger than D1io.

[0084] Next, a correction operation for reducing the offset (discontinuity) of the difference between D4io and D1io occurring at the boundary IO when there is a linearity deviation as shown in FIG. 9 will be described.

[0085] Fig. 10 is a graph illustrating an offset caused by calculation of a correction value. First, a case where an offset occurs at the boundary IO will be described with reference to Fig. 10. Note that VS1, VS2, and VREF in Fig. 10 represent the amount of incident light corresponding to the potentials of the test signals VS1, VS2, and the threshold signal VREF.

[0086] As described above, the boundary IO is determined by the level of the threshold signal VREF because, when the potential of the output signal of the amplifier unit 20 is equal to or greater than the potential of the threshold signal VREF, AD conversion is performed using the reference signal Vr2, and when the potential of the output signal of the amplifier unit 20 is smaller than the potential of the threshold signal VREF, AD conversion is performed using the reference signal Vr1.

[0087] The potential of the test signal VS1 used to acquire the correction value in this embodiment corresponds to the reset signal of pixel 1. In the graph of Fig. 10, the potential of the test signal VS1 corresponds to the origin of the horizontal axis of the graph. Furthermore, the potential of the test signal VS2 is equal to or less than the maximum value of the reference signal Vr1, i.e., VS2≦VREF.

[0088] 10 shows a case where the potential of test signal VS2 corresponds to an incident light amount below which a linearity deviation occurs. Because the linearity of reference signal Vr1 is good in the region between test signal VS1 and test signal VS2, correction is performed to prevent an offset from occurring at the incident light amount corresponding to test signal VS2. However, because reference signals Vr1 and Vr2 switch at boundary IO during pixel signal readout, a linearity deviation of reference signal Vr1 causes an offset (D4io - D1io) at boundary IO.

[0089] 11 is a graph illustrating a case where no offset occurs due to the calculation of the correction value. A case where the potential of the test signal VS2 is equal to the potential of the threshold signal VREF will be described with reference to FIG.

[0090] Even when the potential of test signal VS2 is equal to the potential of threshold signal VREF, the correction calculation is performed, as described above, assuming that reference signal Vr1 is linear between test signal VS1 and test signal VS2. That is, the correction is performed so that an offset does not occur in the amount of incident light corresponding to test signal VS2. Because the potential of test signal VS2 is equal to the potential of threshold signal VREF, the amount of incident light corresponding to test signal VS2 is the boundary IO. Therefore, when the potential of test signal VS2 is equal to the potential of threshold signal VREF, no offset occurs at boundary IO.

[0091] In this case, the slope in the region IH is corrected so as to deviate from the desired slope. However, compared to when an offset occurs at the boundary IO, the change in the digital signal value relative to the amount of incident light is gradual, so the image quality is less likely to be affected.

[0092] In this way, when the linearity of the reference signal is poor, it is desirable that the difference between the potential of the test signal VS2 and the potential of the threshold signal VREF is small. Therefore, in this embodiment, an operation (correction value calculation potential adjustment operation) is added to adjust the difference between the potential of the test signal VS2 and the potential of the threshold signal VREF so as to reduce it.

[0093] FIG. 12 is a timing diagram illustrating the correction value calculation potential adjustment operation according to this embodiment. The correction value calculation potential adjustment operation will be described using FIG. 12. FIG. 12 schematically illustrates the waveforms of the reference signal Vr_Cmp and the test signals VS1 and VS2 during the correction value calculation potential adjustment operation (third drive mode), the correction value calculation operation (first drive mode), and the pixel signal readout operation (second drive mode). The correction value calculation operation and the pixel signal readout operation are similar to those in FIG. 8 and FIG. 5, respectively, and therefore their description will be omitted. Furthermore, the correction value calculation potential adjustment operation will be simplified for operations that have already been described. Note that in FIG. 12, VRAMP_H indicates the one of the two types of reference signals with the greater slope (i.e., reference signal Vr2), and VRAMP_L indicates the one of the two types of reference signals with the smaller slope (i.e., reference signal Vr1).

[0094] 12 will be described. During the period from time t20 to time t21, the potential of the reference signal Vr_Cmp input to the comparator circuit 301 becomes the potential of the threshold signal VREF. Also, during the period from time t20 to time t21, the test signal VS2 is output from the test signal supply unit 200 to the column signal line 2. The comparator circuit 301 compares the potential of the test signal VS2 with the potential of the threshold signal VREF.

[0095] When the potential of the test signal VS2 is equal to or greater than the potential of the threshold signal VREF, the comparator circuit 301 outputs an L-level comparison result signal CMP. Conversely, when the potential of the test signal VS2 is smaller than the potential of the threshold signal VREF, the comparator circuit 301 outputs an H-level comparison result signal CMP. The flag memory 501 holds the comparison result signal CMP output by the comparator circuit 301. The horizontal scanning circuit 60 sequentially scans the flag memories 501 of each column and transfers an H-level or L-level digital signal to the DSP 80.

[0096] At time t22, the DSP 80 outputs a control signal to the test signal supplying unit 200 to change the potential of the test signal VS2 based on the level of the digital signal transferred from the flag memory 501. If the level of the digital signal transferred from the flag memory 501 is L level, the DSP 80 outputs a control signal to lower the potential of the test signal VS2, and if the level is H level, the DSP 80 outputs a control signal to raise the potential of the test signal VS2. Fig. 12 shows an example in which the potential of the test signal VS2 is raised to approximately the same as the potential of the threshold signal VREF.

[0097] This reduces the difference between the potential of the test signal VS2 and the potential of the threshold signal VREF. After the above-described correction value calculation potential adjustment operation is completed, the above-described correction value calculation operation and pixel signal readout operation are performed using the adjusted test signal VS2. In this way, by performing the correction operation of the test signal VS2 by the DSP 80, it is possible to reduce the offset that may occur at the boundary IO, as described with reference to FIGS. 10 and 11.

[0098] The threshold signal VREF is generated by the reference signal supply unit 25, and the test signal VS2 is generated by supplying a potential from the test signal supply unit 200 to the column signal line 2. As described above, the potentials of the two signals are generated at different locations and by different methods. Therefore, even if they are designed to have the same potential, a difference may occur between the two potentials due to process variations during manufacturing, etc. In this embodiment, the comparison circuit 301 determines the difference between the potential of the threshold signal VREF and the potential of the test signal VS2, and a process is performed to reduce the difference. Therefore, the difference between the two potentials can be reduced even when process variations, etc. exist.

[0099] As described above, by performing the process of reducing the difference between the potential of the test signal VS2 and the potential of the threshold signal VREF, it is possible to reduce the offset of the digital signal value that occurs at the boundary IO due to the deviation in linearity of the reference signal. Therefore, according to this embodiment, it is possible to provide a photoelectric conversion device 100 that can further reduce correction errors.

[0100] The correction value calculation potential adjustment operation and the correction value calculation operation in this embodiment may be performed when the photoelectric conversion device 100 is powered on. Also, the correction value calculation potential adjustment operation and the correction value calculation operation in this embodiment may be performed during a blanking period after the vertical scanning circuit 15 has scanned all rows of the pixel unit 10 and before the next scanning of the pixel unit 10 is started. Also, the correction value calculation potential adjustment operation and the correction value calculation operation in this embodiment may be performed when the imaging mode (signal acquisition mode) is changed, such as between moving images and still images.

[0101] Although the linearity deviation of the reference signal has been exemplified as a cause of the linearity deviation described above, the linearity deviation may also be caused by a signal other than the reference signal or a circuit element other than the reference signal supply unit 25. Even in such a case, the correction method of this embodiment is effective.

[0102] [Second embodiment] The photoelectric conversion device 100 of this embodiment performs AD conversion by selecting from a plurality of types of gain for the amplifier unit 20 in accordance with the level of the signal output from the pixel 1. That is, the photoelectric conversion device 100 of this embodiment has a configuration in which the analog signal can be amplified by a variable gain before being input to the comparison circuit 301. In the description of this embodiment, the description of elements common to the first embodiment may be omitted or simplified.

[0103] Fig. 13 is a diagram illustrating an example of the configuration of a photoelectric conversion device 100 according to this embodiment. The photoelectric conversion device 100 shown in Fig. 13 is an imaging device that acquires an image. Although the photoelectric conversion device 100 shown in Fig. 13 is formed on the same semiconductor substrate, the elements that make up the photoelectric conversion device 100 may be formed separately on multiple semiconductor substrates.

[0104] The photoelectric conversion device 100 includes a pixel unit 10, a vertical scanning circuit 15, an amplifier unit 20, a reference signal supply unit 25, a comparison gain setting circuit 310, a counter 40, a memory unit 50, a horizontal scanning circuit 60, a TG 70, a DSP 80, and a test signal supply unit 200. The pixel unit 10 includes a plurality of pixels 1 arranged in a plurality of rows and a plurality of columns. FIG. 13 illustrates an example in which the pixel unit 10 includes four rows and three columns of pixels 1. However, the arrangement of the pixel unit 10 is not limited to this. The configuration of the pixels 1 is similar to that of the first embodiment, and therefore will not be described again. Furthermore, the plurality of pixels 1 arranged in the same column are commonly connected to one column signal line 2. A signal supplied to the amplifier unit 20 via the column signal line 2 is referred to as a column signal Vvl. When a signal is read from the pixel 1 to the column signal line 2, the column signal Vvl assumes a value corresponding to the signal output from the pixel. Note that FIG. 13 does not illustrate wiring for supplying control signals from the TG 70 to each unit.

[0105] The amplifier unit 20 has a column amplifier unit 20a corresponding to each column signal line 2. The column amplifier unit 20a generates an amplified signal Vamp by amplifying the column signal Vvl, and supplies the amplified signal Vamp to the comparison gain setting circuit 310. As will be described later, the column amplifier unit 20a selects one of a plurality of gains to amplify the column signal Vvl, thereby generating the amplified signal Vamp. When the column signal Vvl has a value corresponding to the output signal from the pixel, the column amplifier unit 20a amplifies this output signal.

[0106] 14 is a diagram illustrating an example configuration of a column amplifier 20a according to this embodiment. The column amplifier 20a includes an inverting amplifier AMP, capacitors CIN, CFB1, CFB2, switches SWA1, SWA2, and an OR gate G1. A column signal Vvl is supplied to the input terminal of the inverting amplifier AMP via the capacitor CIN. A switch SWA1 and a capacitor CFB1 are connected in parallel between the input terminal and output terminal of the inverting amplifier AMP. Furthermore, a switch SWA2 and a capacitor CFB2, which are connected in series, are further connected in parallel between the input terminal and output terminal of the inverting amplifier AMP.

[0107] The capacitor CFB1 acts as a feedback capacitor. The OR gate G1 outputs the logical sum of the setting signal ATT and the control signal φFB2 to the control terminal of the switch SWA2. That is, the on / off of the switch SWA2 is controlled by the logical sum of the setting signal ATT and the control signal φFB2. When this logical sum is at H level, the switch SWA2 is turned on and the capacitor CFB2 acts as a feedback capacitor. When this logical sum is at L level, the switch SWA2 is turned off and the capacitor CFB2 does not act as a feedback capacitor. The setting signal ATT is a signal that indicates the gain setting of the column amplifier unit 20a and is input from the comparison gain setting circuit 310.

[0108] When the control signal φARS is at H level, the switch SWA1 is turned on, and the charges accumulated in the capacitors CFB1 and CFB2 are reset. As an example, the capacitance values ​​of the capacitors CIN, CFB1, and CFB2 in this embodiment are assumed to be C, C, and 3C, respectively. When the switch SWA2 is off, the gain of the column amplifier 20a is set to 1, and when the switch SWA2 is on, the gain of the column amplifier 20a is set to 4. The inverting amplifier AMP amplifies the column signal Vvl with the gain set in this manner and outputs the resulting signal as the amplified signal Vamp. The capacitance values ​​of the capacitors CIN, CFB1, and CFB2 can be set appropriately depending on the gain to be set in the column amplifier 20a and are not limited to the above example.

[0109] Fig. 15 is a diagram illustrating an example of the configuration of the comparison gain setting circuit 310 according to this embodiment. The configuration and operation of the comparison gain setting circuit 310 and its peripheral circuits will be described with reference to Fig. 13 and Fig. 15. The comparison gain setting circuit 310 includes a comparison circuit 301 and a setting circuit 105.

[0110] First, an outline of the operation of the comparison circuit 301 and the setting circuit 105 will be described. The comparison circuit 301 receives the amplified signal Vamp from the column amplifier 20a and the reference signal Vr from the reference signal supply unit 25. The reference signal supply unit 25 outputs the reference signal Vr, the potential of which changes over time, in response to a control signal from the TG 70. In this embodiment, the reference signal Vr includes a ramp signal. A ramp signal is a signal whose potential changes at a constant rate over time. The comparison circuit 301 compares the amplified signal Vamp with the reference signal Vr and supplies a comparison signal Vcmp corresponding to the comparison result to the memory unit 50. As an example, the comparison circuit 301 of this embodiment sets the comparison signal Vcmp to an L level when the potential of the amplified signal Vamp is equal to or greater than the potential of the reference signal Vr, and sets the comparison signal Vcmp to an H level when the potential of the amplified signal Vamp is smaller than the potential of the reference signal Vr. The comparison circuit 301 may be, for example, a comparator.

[0111] In addition to the amplified signal Vamp, a threshold signal Vsh is also supplied to the comparison circuit 301. The threshold signal Vsh is supplied by changing the potential of the reference signal Vr supplied from the reference signal supply unit 25 to a predetermined value.

[0112] The comparator circuit 301 compares the potential of the amplified signal Vamp with the potential of the threshold signal Vsh. Based on the comparison result, the setting circuit 105 sets the gain of the column amplifier unit 20a. The setting circuit 105 supplies a setting signal ATT indicating the gain setting of the column amplifier unit 20a to the column amplifier unit 20a and the memory unit 50. As an example, the setting circuit 105 of this embodiment sets the setting signal ATT to L level when the potential of the amplified signal Vamp is lower than the potential of the threshold signal Vsh, and sets the setting signal ATT to H level when the potential of the amplified signal Vamp is equal to or higher than the threshold signal Vsh. The column amplifier unit 20a maintains or changes the gain used to amplify the column signal Vvl depending on the level of the setting signal ATT. That is, the setting circuit 105 determines whether the column amplifier unit 20a should change the gain. The gain is changed while the column amplifier unit 20a is amplifying the signal from the pixel.

[0113] The memory unit 50 is supplied with the setting signal ATT and the comparison signal Vcmp from the comparison gain setting circuit 310, as well as the count signal CNT from the counter 40. The counter 40 starts counting when the reference signal supply unit 25 starts increasing the potential of the ramp signal in response to a control signal from the TG 70. The counter 40 then counts up the count value represented by the count signal CNT over time.

[0114] The memory unit 50 has a flag memory 501, a first memory 502, and a second memory 503, each provided corresponding to one column of the pixel unit 10. The flag memory 501 holds the level of the setting signal ATT supplied from the setting circuit 105. The first memory 502 and the second memory 503 each hold a count value at the time when the level of the comparison signal Vcmp is switched. That is, the reference signal supply unit 25, the comparison gain setting circuit 310, the counter 40, and the memory unit 50 constitute an AD conversion circuit that converts the amplified signal Vamp into a digital value. The second memory 503 holds a digital value corresponding to the amplified signal Vamp output by the amplifier unit 20 when the pixel 1 is reset. The first memory 502 holds a digital value corresponding to the amplified signal Vamp output by the amplifier unit 20 when a photoelectric conversion signal is read out from the pixel 1.

[0115] As shown in FIGS. 13 and 15, the column amplifier unit 20a, setting circuit 105, comparison gain setting circuit 310, flag memory 501, first memory 502, and second memory 503 are arranged corresponding to the column signal line 2. The horizontal scanning circuit 60 sequentially reads digital values ​​from the memory of each column to the DSP 80. The DSP 80 generates a digital signal D corresponding to the pixel signal based on the digital value read from the memory unit 50. An output circuit (not shown in FIG. 13) outputs the digital signal D to the outside of the photoelectric conversion device 100. The digital signal D represents the pixel value of each pixel 1. The TG 70 controls the operation of each component of the photoelectric conversion device 100 by supplying control signals to each component.

[0116] 15, a more detailed description will be given of an example of the circuit configuration and operation of the comparison gain setting circuit 310. The comparison circuit 301 includes a comparator CMP1 and a NOT gate G2. The setting circuit 105 includes a D latch circuit DL and an AND gate G3.

[0117] The amplified signal Vamp is supplied to the non-inverting input terminal of the comparator CMP1. The reference signal Vr is supplied to the inverting input terminal of the comparator CMP1. In other words, during the period when the potential of the reference signal Vr is the potential of the threshold signal Vsh, the threshold signal Vsh is supplied to the inverting input terminal of the comparator CMP1. The comparator CMP1 determines whether the potential of the amplified signal Vamp is larger than the potential of the threshold signal Vsh and supplies a signal corresponding to the determination result to the D terminal of the D latch circuit DL. The comparator CMP1 outputs an L-level signal when the potential of the amplified signal Vamp is smaller than the potential of the threshold signal Vsh, and outputs an H-level signal when the potential of the amplified signal Vamp is equal to or greater than the potential of the threshold signal Vsh. The comparator CMP1 also compares the amplified signal Vamp with the reference signal Vr. The NOT gate G2 outputs a comparison signal Vcmp, which is an inverted version of the comparison result, to the memory unit 50.

[0118] The D latch circuit DL holds the level of the signal supplied to the D terminal in response to a control signal φDL supplied to the E terminal. The D latch circuit DL also supplies a signal of the level of the signal it is holding to a first input terminal of an AND gate G3. A control signal φDLO is supplied to a second input terminal of the AND gate G3. When the control signal φDLO is H level, the AND gate G3 outputs a signal of the level of the signal held by the D latch circuit DL as a setting signal ATT to the amplifier unit 20 and the memory unit 50. When the control signal φDLO is L level, the AND gate G3 also outputs a signal of L level as a setting signal ATT to the amplifier unit 20 and the memory unit 50.

[0119] 16 is a diagram illustrating an example of the configuration of the test signal supply unit 200 according to this embodiment. An example of the circuit configuration of the test signal supply unit 200 will be described with reference to Fig. 16. The test signal supply unit 200 includes a multiplexer MX1 ​​controlled by a control signal φTS1, a multiplexer MX2 controlled by a control signal φTS2, and a transistor M8 connected to the column signal line 2 of each column.

[0120] The transistor M8 is an NMOS transistor. The source of the transistor M8 is connected to the column signal line 2, and the drain of the transistor M8 is connected to the power supply line. The transistor M8 controls the potential of the column signal line 2 in response to a gate potential controlled by the multiplexer MX2. The multiplexer MX2 is supplied with a potential VS0_3 and an output signal of the multiplexer MX1. The multiplexer MX1 ​​is supplied with potentials VS0_1 and VS0_2. The multiplexer MX1 ​​outputs the potential VS0_1 when the control signal φTS1 is at an L level, and outputs the potential VS0_2 when the control signal φTS1 is at an H level. A signal that the test signal supply unit 200 supplies to the column signal line 2 when the potential VS0_1 is supplied to the gate of the transistor M8 is called a test signal VS1. A signal that the test signal supply unit 200 supplies to the column signal line 2 when the potential VS0_2 is supplied to the gate of the transistor M8 is called a test signal VS2. The test signals VS1 and VS2 are analog signals with different potentials.

[0121] When the control signal φTS2 is at the L level, the multiplexer MX2 selects the potential VS0_3, and the potential VS0_3 is supplied to the gate of the transistor M8. On the other hand, when the control signal φTS2 is at the H level, the multiplexer MX2 selects the output signal of the multiplexer MX1, and the potential VS0_1 or the potential VS0_2 is supplied to the gate of the transistor M8.

[0122] In the correction value calculation operation, the control signal φTS2 goes to H level, and the test signal VS1 or the test signal VS2 is supplied as the column signal Vvl to the column signal line 2. In addition, in the pixel signal readout operation, the control signal φTS2 goes to L level, and the potential of the column signal line 2 is clipped in accordance with the potential VS0_3. Since the test signal supply unit 200 has such a clipping function, it is possible to prevent an excessive voltage drop of the column signal line 2 that may occur when the level of the pixel signal increases locally, and it is possible to obtain the effect of reducing smear.

[0123] Next, the operation of the photoelectric conversion device 100 will be described. The operation of the photoelectric conversion device 100 is performed by the TG70 controlling the operation of each component of the photoelectric conversion device 100. The operation of the pixel 1 is performed by the TG70 controlling the vertical scanning circuit 15. Furthermore, the reading of digital values ​​from the memory unit 50 to the DSP 80 is performed by the TG70 controlling the horizontal scanning circuit 60. The photoelectric conversion device 100 mainly performs a pixel signal readout operation, a correction value calculation operation, a pixel value calculation operation, and a correction value calculation potential adjustment operation. The pixel signal readout operation is an operation of reading pixel signals from pixels and storing digital values ​​corresponding to the pixel signals in the memory unit 50. The correction value calculation operation is an operation of calculating a correction value for correcting these digital values. The pixel value calculation operation is an operation of calculating pixel values ​​by correcting these digital values. The correction value calculation potential adjustment operation will be described later. Below, the pixel signal readout operation, pixel value calculation operation, correction value calculation operation, and correction value calculation potential adjustment operation will be described in that order.

[0124] FIG. 17 is a timing diagram illustrating the operation of the photoelectric conversion device 100 according to this embodiment. A pixel signal readout operation will be described with reference to the timing diagram of FIG. 17. FIG. 17 illustrates an operation for reading out a pixel signal from one pixel 1 once. The operation illustrated in FIG. 17 is performed simultaneously on multiple pixels 1 arranged in the same row. FIG. 17 illustrates the levels of the control signals φPRS, φPTX, φARS, φFB2, φDL, and φDLO, the column signal Vvl, the amplification signal Vamp, the setting signal ATT, the reference signal Vr, the gain of the column amplifier unit 20a, and the count period of the counter 40.

[0125] 17 for each of the plurality of pixel rows constituting the pixel unit 10, the photoelectric conversion device 100 reads out pixel signals from each pixel of the pixel unit 10. Throughout the period shown in FIG. 17, the vertical scanning circuit 15 maintains the control signal φPSEL supplied to the pixel 1 that is the target of the pixel signal readout operation at H level, and maintains the control signals φPSEL supplied to the other pixels 1 at L level.

[0126] When the pixel signal readout operation starts, the vertical scanning circuit 15 temporarily sets the control signal φPRS to H level during the period from time t60 to time t61. This turns on the reset transistor MRS, resetting the pixel 1. At this time, a signal corresponding to the reset state of the pixel 1 is read out to the column signal line 2. This signal is called a reset signal. When the reset signal is read out to the column signal line 2, the column signal Vvl takes on a value corresponding to this signal.

[0127] Between time t60 and time t62, TG70 temporarily sets the control signal φFB2 to the H level in parallel with the pixel reset. Also, between time t60 and time t63, TG70 temporarily sets the control signal φARS to the H level in parallel with the pixel reset. These operations reset the charges accumulated in capacitors CFB1 and CFB2.

[0128] During the above operation, the TG70 sets the control signal φDLO to L level. As a result, the setting signal ATT output by the setting circuit 105 becomes L level. After time t62, because the setting signal ATT and the control signal φFB2 are both L level, the switch SWA2 of the column amplifier unit 20a is off, and the capacitance value of the feedback capacitor connected to the inverting amplifier AMP is C. Because the capacitance value of the input capacitor connected to the inverting amplifier AMP is also C, the gain of the column amplifier unit 20a is set to 1 (first gain).

[0129] At time t64, the reference signal supplying unit 25 starts to supply a ramp signal as the reference signal Vr in response to the control signal from the TG 70. In other words, the reference signal supplying unit 25 starts to change the potential of the reference signal Vr at a constant rate over time. At the same time, the counter 40 starts to count up the count value it outputs from zero in response to the control signal from the TG 70.

[0130] At time t65, when the potential of the reference signal Vr exceeds the potential of the amplified signal Vamp and the comparison signal Vcmp switches from L level to H level, the second memory 503 holds the count value from the counter 40 at that time. This count value corresponds to a digital value obtained by AD converting the amplified signal Vamp obtained by amplifying the reset signal with a gain of 1. Hereinafter, this digital value will be referred to as N.

[0131] Between time t66 and time t67, the vertical scanning circuit 15 temporarily sets the control signal φPTX to the H level. This causes the charge accumulated in the photoelectric conversion unit PD to be transferred to the floating diffusion FD. After that, the photoelectric conversion signal is read out from the pixel 1 to the column signal line 2, and the column signal Vvl takes a value corresponding to the photoelectric conversion signal. The amount of change in the column signal Vvl relative to the time when the pixel 1 was reset (i.e., the difference between the photoelectric conversion signal and the reset signal) is represented by ΔVvl. ΔVvl is a value corresponding to the amount of light incident on the pixel 1. As the column signal Vvl changes, the amplified signal Vamp also changes. The amount of change in the amplified signal Vamp when the gain of the column amplifier 20a is set to 1 is referred to as ΔVamp1.

[0132] During the period from time t68 to time t70, the TG70 changes the potential of the reference signal Vr supplied by the reference signal supply unit 25 to the potential of the threshold signal Vsh. The threshold signal Vsh is set to ¼ or less of the output dynamic range of the column amplifier 20a. The photoelectric conversion device 100 performs different operations when the amplified signal Vamp is equal to or greater than the threshold signal Vsh and when the amplified signal Vamp is less than the threshold signal Vsh. The following describes a case where the potential of the amplified signal Vamp obtained by amplifying the photoelectric conversion signal with a gain of 1 is greater than the potential of the threshold signal Vsh.

[0133] From time t69 to time t70, which is a predetermined time period after the vertical scanning circuit 15 sets the control signal φPTX to L level, the TG70 temporarily sets the control signal φDL to H level. In the example of Fig. 17, the potential of the amplified signal Vamp is greater than the potential of the threshold signal Vsh, so the D latch circuit DL is held at H level.

[0134] At time t70, the TG70 sets the control signal φDLO to H level. The setting circuit 105 outputs the signal held in the D latch circuit DL, and the setting signal ATT goes to H level. As a result, the switch SWA2 of the column amplifier 20a is turned on, the capacitor CFB2 is connected to the inverting amplifier AMP, and the combined capacitance value of the feedback capacitors connected to the inverting amplifier AMP becomes 4C. Because the capacitance value of the input capacitor connected to the inverting amplifier AMP is C, the gain of the column amplifier 20a is set to 1 / 4 (second gain). Accordingly, the potential of the amplified signal Vamp also changes. The amount of change in the amplified signal Vamp when the gain of the amplifier 20 is set to 1 / 4 is called ΔVamp2.

[0135] Then, from time t71 to time t72, the photoelectric conversion device 100 performs AD conversion on the amplified signal Vamp obtained by amplifying the signal from the pixel. This process is generally similar to the process performed on the reset signal from time t64 to time t65. The first memory 502 holds the digital value obtained by AD converting the amplified signal Vamp. Hereinafter, this digital value will be referred to as S. Then, the flag memory 501 holds the level of the setting signal ATT. At time t73, the TG70 sets the control signal φDLO to L level, thereby setting the setting signal ATT to L level, and the pixel signal readout operation proceeds to readout of the next row.

[0136] Through the above operations, the level of the setting signal ATT when the pixel signal is AD converted is stored in the flag memory 501. Furthermore, a digital value N representing the amplified reset signal is stored in the second memory 503, and a digital value S representing the amplified photoelectric conversion signal is stored in the first memory 502. As in the above example, when the gain of the column amplifier 20a is changed from 1x to ¼x, the flag memory 501 stores the setting signal ATT at an H level, and the first memory 502 stores the digital value representing the photoelectric conversion signal amplified with a ¼x gain. On the other hand, when the potential of the amplified signal Vamp obtained by amplifying the photoelectric conversion signal with a 1x gain is smaller than the potential of the threshold signal Vsh, the gain of the column amplifier 20a is maintained at 1x. In this case, the flag memory 501 stores the setting signal ATT at an L level, and the first memory 502 stores the digital value S representing the photoelectric conversion signal amplified with a 1x gain. In both cases where the gain of the column amplifier unit 20a is changed from 1x to 1 / 4x and where it is maintained at 1x, the second memory 503 holds a digital value N representing the reset signal amplified with a gain of 1x.

[0137] Next, the pixel value calculation operation will be described. The DSP 80 calculates the pixel value based on the digital value stored in the memory unit 50. First, a case where an L-level setting signal ATT is stored in the flag memory 501 will be described. In this case, the first memory 502 stores a digital value S representing a photoelectric conversion signal amplified with a gain of 1, and the second memory 503 stores a digital value N representing a reset signal amplified with a gain of 1. The DSP 80 calculates the pixel value by performing digital CDS (Correlated Double Sampling) processing using these digital values. Specifically, the DSP 80 calculates the difference between the digital value S and the digital value N, i.e., SN, and sets this value as the pixel value.

[0138] Next, a case where the flag memory 501 holds a setting signal ATT at H level will be described. In this case, the first memory 502 holds a digital value S representing a pixel signal amplified with a gain of 1 / 4, and the second memory 503 holds a digital value N representing a reset signal amplified with a gain of 1. Therefore, the DSP 80 cannot calculate a correct pixel value simply by performing digital CDS processing using the digital values ​​S and N as they are. Furthermore, because it is difficult to control the gain accurately, even if the gain of the column amplifier 20a is set to 1 / 4, the actual amplified signal Vamp may be amplified with a different gain value. The reason for this will be described with reference to FIG. 18.

[0139] FIG. 18 is a graph illustrating calculation of a correction value according to this embodiment. The horizontal axis of the graph in FIG. 18 represents a change ΔVvl in the column signal Vvl. The vertical axis of the graph in FIG. 18 represents a digital signal value. The change ΔVvl corresponds to the amount of incident light incident on the pixel 1. When the column signal Vvl has a value corresponding to the reset signal, the change ΔVvl is zero (the origin of the graph in FIG. 18). The change ΔVvl is divided into a region where the column amplifier 20a outputs a signal with a gain of 1x and a region where the column amplifier 20a outputs a signal with a gain of 1 / 4. IO is the boundary between the two regions.

[0140] A straight line L1 indicates the relationship between the amount of change ΔVvl and the digital signal D1 calculated by the following equation (4) in the range in which the gain of the column amplifier 20a is set to 1. D1=SN (4)

[0141] Since both the digital value S and the digital value N are values ​​generated when the gain of the column amplifier 20a is set to 1, a digital signal D1 that appropriately represents the amount of incident light is obtained by performing digital CDS processing. For example, when the change amount ΔVvl is zero, the digital signal D1 is also zero. When the gain of the amplifier 20 is set to 1, the DSP 80 sets the digital signal D1 as the digital signal D, which is the output signal of the photoelectric conversion device 100.

[0142] A straight line L2 indicates the relationship between the amount of change ΔVvl and the digital signal D2 calculated by the following equation (5) in the range in which the gain of the column amplifier 20a is set to ¼. D2=4(SN) (5)

[0143] In equation (5), the SN obtained by digital CDS processing is multiplied by "4," which is the reciprocal of the gain, so the slope of line L2 theoretically matches the slope of line L1. However, due to gain error, the slopes of these lines may not match. In this case, even if offset correction, as described below, is performed, the digital signal D will not have good linearity. Therefore, the DSP 80 of this embodiment determines the coefficient by which to multiply the SN based on the actually obtained amplified signal Vamp, rather than based on the theoretical value of "4," which is the reciprocal of the gain.

[0144] In one example, the DSP 80 calculates a correction coefficient b for correcting the gain correction value, and multiplies the correction coefficient b by the reciprocal of the theoretical gain value, "4," to obtain a gain correction value β G Specifically, the DSP 80 calculates the correction coefficient b so that the gradient of a straight line L3 representing the digital signal D3 calculated by the following equation (6) matches the gradient of the straight line L1. The method for calculating the correction coefficient b will be described later. D3=4b(SN) (6)

[0145] Then, the DSP 80 calculates the offset correction value α from D3. G That is, the DSP 80 calculates the digital signal D4 by the following equation (7). D4=4b(SN)-α G (7)

[0146] A straight line L4 indicates the relationship between the change amount ΔVvl included in the range in which the gain of the column amplifier 20a is set to ¼ and the digital signal D4 calculated according to the above-described equation (7). As shown in FIG. 18, the straight line L4 has good linearity with respect to the straight line L1. When the gain of the column amplifier 20a is set to ¼ (i.e., when the flag memory 501 holds an H level), the DSP 80 outputs the digital signal D4 as the above-described digital signal D.

[0147] FIG. 19 is a timing diagram showing the correction value calculation operation according to this embodiment. The correction value calculation operation will be described with reference to the timing diagram of FIG. 19. FIG. 19 shows the operation of calculating a correction value corresponding to one column amplifier unit 20a. This correction value is used for multiple pixels 1 commonly connected to that column amplifier unit 20a. The vertical scanning circuit 15 maintains the control signal φPSEL supplied to all pixels 1 at the L level throughout the period shown in FIG. 19. The correction value calculation operation is performed during four consecutive periods H1 to H4.

[0148] During period H1, the test signal supply unit 200 supplies a test signal VS1 as the column signal Vvl. During period H1, the TG70 performs an operation similar to the pixel signal readout operation, causing the second memory 503 to store a digital value N1, and then causes the first memory 502 to store a digital value S1. During period H1, the TG70 sets the control signal φDLO to an L level, causing the setting circuit 105 to output an L-level setting signal ATT to the column amplifier unit 20a. Therefore, the digital value S1 (third digital value) and the digital value N1 represent the amplified signal Vamp obtained with a gain of 1. The DSP80 reads out the digital values ​​N1 and S1 from the memory unit 50 and stores them in its internal memory.

[0149] In the following periods, signal acquisition is performed by similar processing while switching the relationship between the column signal Vvl and the gain. During period H2, a digital value N2 is generated with the column signal Vvl being the test signal VS1 and the gain set to 1. Thereafter, a digital value S2 (fourth digital signal) is generated with the column signal Vvl being the test signal VS1 and the gain set to 1 / 4. The DSP 80 reads the digital values ​​N2 and S2 from the memory unit 50 and stores them in its internal memory.

[0150] During period H3, a digital value N3 is generated with the column signal Vvl being the test signal VS1 and the gain set to 1. Thereafter, a digital value S3 (first digital value) is generated with the column signal Vvl being the test signal VS2 and the gain set to 1. The DSP 80 reads the digital values ​​N3 and S3 from the memory unit 50 and stores them in its internal memory.

[0151] During period H4, the column signal Vvl is the test signal VS1, and a digital value N4 is generated with the gain set to 1. Thereafter, the column signal Vvl is the test signal VS2, and a digital value S4 (second digital value) is generated with the gain set to 1 / 4. The DSP 80 reads the digital values ​​N4 and S4 from the memory unit 50 and stores them in its internal memory.

[0152] If the gain set in the amplifier unit 20 after the change is G (1 / 4 in the above example), the DSP 80 calculates the correction coefficient b and the gain correction value β using the following equations (8) to (10): G and the offset correction value α G The DSP 80 calculates the gain correction value β G and the offset correction value α G is stored in the memory inside the DSP80. b={(S3-N3)-(S1-N1)} / {(S4-N4) / G-(S2-N2) / G} (8) β G =b / G (9) α G =b(S2-N2) / G-(S1-N1) (10)

[0153] Next, the signal value of the digital signal obtained when a linearity deviation occurs in the column amplifier 20a and no correction operation is performed will be described with reference to FIG.

[0154] Fig. 20 is a graph illustrating a case where a correction value is not calculated. In Fig. 20, a line LY1 shows the relationship between the change amount ΔVvl of the column signal Vvl and the digital signal calculated by the above-mentioned equation (6) in the range where the gain of the column amplifier 20a is set to 1 / 4.

[0155] The line LY2 shows the relationship between the change amount ΔVvl of the column signal Vvl and the digital signal calculated by the above-mentioned equation (5) in the range where the gain of the column amplifier 20a is set to 1 / 4. In Fig. 20, the slope of the line LY2 is shown assuming that the gain ratio of the column amplifier 20a is smaller than 1 / 4 due to an error.

[0156] Line LX shows the relationship between the change amount ΔVvl in the column signal Vvl and the corrected digital signal value when linearity is good within the range where the gain of the column amplifier 20a is set to 1 / 4. At the boundary IO, the signal values ​​of the digital signals obtained at (X) and (Y1) corresponding to line LX, line LY1, and line LY2, respectively, are D1io, D2io, and D3io, respectively. Because the gain ratio of the column amplifier 20a is smaller than 1 / 4 due to an error, D3io is smaller than D2io.

[0157] 20, a linearity deviation occurs near the boundary IO of the range in which the gain of the column amplifier 20a is set to 1. Due to the linearity deviation near the boundary IO, the signal value of the digital signal obtained near the boundary IO of the range in which the gain of the column amplifier 20a is set to 1 is D4io, which is larger than D1io.

[0158] Next, a correction operation for reducing the offset (discontinuity) of the difference between D4io and D1io that occurs at the boundary IO when there is a linearity deviation as shown in FIG. 20 will be described.

[0159] Fig. 21 is a graph illustrating an offset caused by calculation of a correction value. First, a case where an offset occurs at the boundary IO will be described with reference to Fig. 21. Note that VS1, VS2, and Vsh in Fig. 21 represent a change amount ΔVvl corresponding to the potentials of the test signals VS1, VS2, and the threshold signal Vsh.

[0160] As described above, the boundary IO is determined by the level of the threshold signal Vsh because the gain of the column amplifier 20a is set to 1 / 4 when the potential of the amplified signal Vamp is equal to or greater than the potential of the threshold signal Vsh, and the gain of the column amplifier 20a is set to 1 when the potential of the amplified signal Vamp is smaller than the potential of the threshold signal Vsh.

[0161] The potential of the test signal VS1 used to acquire the correction value in this embodiment corresponds to the reset signal of the pixel 1. In the graph of Fig. 21, the potential of the test signal VS1 corresponds to the origin of the horizontal axis of the graph. The potential of the test signal VS2 is set to be equal to or less than ¼ of the output dynamic range of the column amplifier unit 20a, i.e., VS2≦Vsh.

[0162] 21 shows a case where the potential of the test signal VS2 is below the change amount ΔVvl at which a linearity deviation occurs. Since the column amplifier 20a has good linearity in the region between the test signals VS1 and VS2, correction is performed to prevent an offset from occurring at the change amount ΔVvl corresponding to the test signal VS2. However, since the gain of the column amplifier 20a switches at the boundary IO, an offset (D4io-D1io) occurs at the boundary IO due to a linearity deviation of the column amplifier 20a.

[0163] 22 is a graph illustrating a case where no offset occurs due to the calculation of the correction value. A case where the potential of the test signal VS2 is equal to the potential of the threshold signal Vsh will be described with reference to FIG.

[0164] Even when the potential of the test signal VS2 is equal to the potential of the threshold signal Vsh, the correction calculation is performed, as described above, assuming that the gain of the column amplifier unit 20a is linear between the test signals VS1 and VS2. That is, the correction is performed so that an offset does not occur in the change amount ΔVvl corresponding to the test signal VS2. Because the potential of the test signal VS2 is equal to the potential of the threshold signal Vsh, the change amount ΔVvl corresponding to the test signal VS2 is the boundary IO. Therefore, when the potential of the test signal VS2 is equal to the potential of the threshold signal Vsh, no offset occurs at the boundary IO.

[0165] In this case, the gradient in the region where the gain of the column amplifier 20a is set to 1 is corrected to deviate from the desired gradient. However, compared to the case where an offset occurs at the boundary IO, the change in the digital signal value relative to the change amount ΔVvl (i.e., the amount of incident light) is gentler, and therefore the image quality is less likely to be affected.

[0166] In this way, when the linearity of the column amplifier 20a is poor, it is desirable that the difference between the potential of the test signal VS2 and the potential of the threshold signal Vsh is small. Therefore, in this embodiment, an operation of adjusting the difference between the potential of the test signal VS2 and the potential of the threshold signal Vsh so as to reduce the difference (correction value calculation potential adjustment operation) is added.

[0167] 23 is a timing diagram illustrating the correction value calculation potential adjustment operation according to this embodiment. Fig. 23 schematically illustrates the waveforms of the reference signal Vr and the test signals VS1 and VS2 during the correction value calculation potential adjustment operation (third drive mode), the correction value calculation operation (first drive mode), and the pixel signal readout operation (second drive mode). The correction value calculation operation and the pixel signal readout operation are similar to those in Figs. 19 and 17, respectively, and therefore their explanations are omitted. Furthermore, the explanation of the correction value calculation potential adjustment operation, which has already been explained, will be simplified.

[0168] 23 will be described. During the period from time t20 to time t21, the potential of the reference signal Vr input to the comparison gain setting circuit 310 becomes the potential of the threshold signal Vsh. Also, during the period from time t20 to time t21, the test signal VS2 is output from the test signal supply unit 200 to the column signal line 2. The comparison gain setting circuit 310 compares the potential of the test signal VS2 with the potential of the threshold signal Vsh.

[0169] When the potential of the test signal VS2 is equal to or greater than the potential of the threshold signal Vsh, the comparison gain setting circuit 310 outputs an H-level setting signal ATT. Conversely, when the potential of the test signal VS2 is smaller than the potential of the threshold signal VREF, the comparison gain setting circuit 310 outputs an L-level setting signal ATT. The flag memory 501 holds the setting signal ATT output by the comparison gain setting circuit 310. The horizontal scanning circuit 60 sequentially scans the flag memories 501 for each column and transfers an H-level or L-level digital signal to the DSP 80.

[0170] At time t22, the DSP 80 outputs a control signal to the test signal supplying section 200 to change the potential of the test signal VS2 based on the level of the digital signal transferred from the flag memory 501. If the level of the digital signal transferred from the flag memory 501 is H level, the DSP 80 outputs a control signal to lower the potential of the test signal VS2, and if the level is L level, the DSP 80 outputs a control signal to raise the potential of the test signal VS2. Fig. 23 shows an example in which the potential of the test signal VS2 is raised to approximately the same as the potential of the threshold signal Vsh.

[0171] This reduces the difference between the potential of the test signal VS2 and the potential of the threshold signal Vsh. After the above-described correction value calculation potential adjustment operation is completed, the above-described correction value calculation operation and pixel signal readout operation are performed using the adjusted test signal VS2. In this way, by performing the correction operation of the test signal VS2 by the DSP 80, it is possible to reduce the offset that may occur at the boundary IO, as described with reference to FIGS. 21 and 22.

[0172] The threshold signal Vsh is generated by the reference signal supply unit 25, and the test signal VS2 is generated by supplying a potential from the test signal supply unit 200 to the column signal line 2. As described above, the potentials of the two signals are generated at different locations and by different methods. Therefore, even if they are designed to have the same potential, a difference may occur between the two potentials due to process variations during manufacturing, etc. In this embodiment, the comparison circuit 301 determines the difference between the potential of the threshold signal Vsh and the potential of the test signal VS2, and processing is performed to reduce this difference. Therefore, the difference between the two potentials can be reduced even when process variations, etc. exist.

[0173] As described above, by performing the process of reducing the difference between the potential of the test signal VS2 and the potential of the threshold signal Vsh, it is possible to reduce the offset of the digital signal value that occurs at the boundary IO due to the linearity deviation of the column amplifier unit 20a. Therefore, according to this embodiment, it is possible to provide a photoelectric conversion device 100 that can further reduce correction errors.

[0174] The correction value calculation potential adjustment operation and the correction value calculation operation in this embodiment may be performed when the photoelectric conversion device 100 is powered on. Also, the correction value calculation potential adjustment operation and the correction value calculation operation in this embodiment may be performed during a blanking period after the vertical scanning circuit 15 has scanned all rows of the pixel unit 10 and before the next scanning of the pixel unit 10 is started. Also, the correction value calculation potential adjustment operation and the correction value calculation operation in this embodiment may be performed when the imaging mode (signal acquisition mode) is changed, such as between moving images and still images.

[0175] Although the linearity deviation of the column amplifier 20a has been exemplified as a cause of the linearity deviation described above, the linearity deviation may also be caused by a circuit element other than the column amplifier 20a or a signal output from a circuit element other than the column amplifier 20a. Even in such a case, the correction method of this embodiment is effective.

[0176] [Third embodiment] In the above-described embodiment, it has been described that the offset can be reduced by reducing the difference between the potential of the test signal and the potential of the threshold signal. In this embodiment, a range of the difference between the potential of the test signal and the potential of the threshold signal that can more suitably reduce the offset will be described.

[0177] FIG. 24 is a graph showing the relationship between the test signal VS2 and the offset according to the third embodiment. FIG. 24 shows actual measurement values ​​of the offset when the potential of the test signal VS2 is changed in the configuration of the third embodiment. The horizontal axis of FIG. 24 shows the potential (V) for acquiring a correction value that is input to the comparator circuit 301 based on the test signal VS2. Note that the potential shown in FIG. 24 is acquired at a stage subsequent to the column amplifier unit 20a, and includes the influence of the gain of the column amplifier unit 20a. The vertical axis of FIG. 24 is a value showing the degree of offset in units of the least significant bit (LSB) of a digital signal.

[0178] The slope of the approximation line shown in FIG. 24 is approximately 3 LSB / 0.1 V. If the deviation of the correction value acquisition potential from the optimal potential (approximately 0.6 V in the example of FIG. 24) with zero offset is allowed to be approximately ±5%, the magnitude of the offset can be reduced to approximately 1 LSB or less, thereby sufficiently reducing the offset. Therefore, it is desirable that the difference between the correction value acquisition potential and the potential of the threshold signal Vsh be within ±5%. In other words, after potential control by the correction value calculation potential adjustment operation, it is desirable that the ratio of the potential of the signal obtained by amplifying the test signal VS2 by the first gain to the threshold signal Vsh be 0.95 or more and 1.05 or less. Note that the example in FIG. 24 is an example of actual measurements in the configuration of the second embodiment, but the same applies to the configuration of the first embodiment. In other words, after potential control by the correction value calculation potential adjustment operation, it is desirable that the ratio of the potential of the test signal VS2 to the threshold signal VREF be 0.95 or more and 1.05 or less.

[0179] [Fourth embodiment] In the above-described embodiment, the test signal supplying section 200 may be any section that is capable of supplying the test signals VS1 and VS2 and that is capable of changing the potential of the test signal VS2 in response to a control signal from the DSP 80. The configuration of the test signal generating circuit for supplying such test signals VS1 and VS2 is not particularly limited, but in this embodiment, an example of a test signal generating circuit will be described.

[0180] 25 is a circuit diagram of the test signal generation circuit according to this embodiment. The test signal generation circuit has N switches SW1 to SWN and N+2 resistors R0 to R(N+1) (N is an integer equal to or greater than 2).

[0181] Resistors R0 to R(N+1) are connected in series between a potential wiring having a power supply potential VDD and a ground wiring having a ground potential GND. The node between resistors R0 and R1 is the output terminal of the test signal VS1. The first terminals of switches SW1 to SWN are connected to each other and are the output terminal of the test signal VS2. The second terminal of switch SW1 is connected to the node between resistors R1 and R2. The second terminal of switch SW2 is connected to the node between resistors R2 and R3. Switches SW3 to SWN have a similar connection relationship. A control signal output from the DSP 80 is input to the control terminals of switches SW1 to SWN. This control signal turns on one of switches SW1 to SWN and turns off the other N-1 switches. The output terminal of the test signal VS2 has a different potential depending on which switch is turned on. Therefore, the switches SW1 to SWN of the test signal generation circuit of this embodiment and N+2 resistors R0 to R(N+1) form a digital-to-analog conversion circuit that generates an analog potential based on the digital control signal output from the DSP 80.

[0182] By employing the test signal generating circuit of FIG. 25, the potential of the test signal VS1 can be fixed, and the potential of the test signal VS2 can be made variable by a control signal from the DSP 80.

[0183] [Fifth embodiment] In this embodiment, another example of a test signal generation circuit will be described. Fig. 26 is a circuit diagram of the test signal generation circuit according to this embodiment. The test signal generation circuit includes a current source Ic1, transistors MR1, MR2, MR3, and MR4, and a capacitor CR. The transistors MR1, MR2, and MR3 are PMOS transistors, and the transistor MR4 is an NMOS transistor.

[0184] The drain of transistor MR1, the gate of transistor MR1, and the gate of transistor MR2 are connected to current source Ic1. The sources of transistor MR1 and transistor MR2 are connected to a potential wiring having a power supply potential VDD. The drain of transistor MR2 is connected to the source of transistor MR3. The drain of transistor MR3 is connected to the drain of transistor MR4 and the first terminal of capacitor CR. The source of transistor MR4 and the second terminal of capacitor CR are connected to a ground wiring.

[0185] The transistor MR3 is controlled to be turned on or off based on a control signal φMR3 output from the DSP 80. The transistor MR4 is controlled to be turned on or off based on a control signal φMR4 output from the DSP 80. The connection node between the drain of the transistor MR3, the drain of the transistor MR4, and the first terminal of the capacitor CR is the output terminal VSX of the test signal generation circuit. The test signal VS1 or the test signal VS2 is output from the output terminal VSX.

[0186] Transistors MR1 ​​and MR2 form a current mirror circuit, and when transistor MR3 is turned on, a constant current flows through transistors MR2 and MR3. By setting both control signals φMR3 and φMR4 to L level, transistor MR3 is turned on and transistor MR4 is turned off. At this time, a charge based on the constant current flowing through transistors MR2 and MR3 is stored in capacitor CR. The potential of the first terminal of capacitor CR rises approximately linearly depending on the time the constant current flows. In this way, the test signal generation circuit of this embodiment operates as a ramp signal generation circuit. Therefore, the potential of the output terminal VSX can be controlled depending on the duration of the pulse that sets control signals φMR3 and φMR4 to L level.

[0187] The test signal generation circuit of Fig. 26 can generate a desired potential according to the pulse time width. By adopting the test signal generation circuit of Fig. 25, it is possible to generate variable potentials for the test signal VS1 and the test signal VS2 in response to control signals from the DSP 80.

[0188] The test signal generation circuits of the fourth and fifth embodiments can be applied to the power supplies (VS1, VS2) in the test signal selection unit 201 in Fig. 3 or the power supplies (VS0_1, VS0_2, VS0_3) in the test signal supply unit 200 in Fig. 16. In this case, the multiplexers shown in these figures may be omitted.

[0189] [Sixth embodiment] The photoelectric conversion device 100 of this embodiment is a modification of the correction value calculation and potential adjustment operation of the first embodiment shown in Fig. 12. Other elements are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0190] FIG. 27 is a timing diagram illustrating the correction value calculation potential adjustment operation according to this embodiment. In the photoelectric conversion device 100 of this embodiment, an operation similar to the correction value calculation potential adjustment operation shown in FIG. 12 is executed multiple times (three times in the example of FIG. 27). As shown in FIG. 27, by comparing the potential of the test signal VS2 with the potential of the threshold signal VREF and repeating the operation of reducing the difference between them multiple times, the difference between the potential of the test signal VS2 and the potential of the threshold signal VREF can be further reduced. Therefore, according to this embodiment, the offset can be further reduced, and therefore it is possible to provide a photoelectric conversion device 100 that can further reduce correction errors.

[0191] The number of times the correction value calculation potential adjustment operation is performed may be predetermined, and may be repeated until the difference between the potential of the test signal VS2 and the potential of the threshold signal VREF falls within a predetermined range, which may be, for example, within ±5% for the reasons described in the third embodiment.

[0192] [Seventh embodiment] The photoelectric conversion device 100 of this embodiment is a modified example of the correction value calculation and potential adjustment operation in Fig. 12 of the first embodiment or Fig. 27 of the sixth embodiment. The other elements are the same as those in the first or sixth embodiment, and therefore description thereof will be omitted.

[0193] 28 is a timing diagram illustrating the correction value calculation potential adjustment operation according to this embodiment. As shown in FIG. 28, the photoelectric conversion device 100 of this embodiment differs from the first or sixth embodiment in that, in the correction value calculation potential adjustment operation, the potential of the threshold signal VREF is changed instead of the potential of the test signal VS2. The process of changing the potential of the threshold signal VREF is performed by the TG70 controlling the reference signal supply unit 25.

[0194] If the potential of the test signal VS2 is equal to or greater than the potential of the threshold signal VREF, the comparator circuit 301 outputs an L-level comparison result signal CMP. Conversely, if the potential of the test signal VS2 is smaller than the potential of the threshold signal VREF, the comparator circuit 301 outputs an H-level comparison result signal CMP. The comparison result signal CMP is held in the flag memory 501. The horizontal scanning circuit 60 sequentially scans the flag memories 501 of each column and transfers an H-level or L-level digital signal to the DSP 80.

[0195] The DSP 80 outputs a control signal to the TG 70 to change the potential of the threshold signal VREF based on the comparison result signal CMP. The TG 70 outputs a control signal to the reference signal supply unit 25 to change the potential of the threshold signal VREF based on this control signal. In this process, when the comparison result signal CMP is at an L level, a control signal to increase the potential of the threshold signal VREF is output, and when the comparison result signal CMP is at an H level, a signal to decrease the potential of the threshold signal VREF is output. This reduces the difference between the potential of the test signal VS2 and the potential of the threshold signal VREF, thereby reducing the offset of the digital signal value that occurs at the boundary IO. Therefore, according to this embodiment, a photoelectric conversion device 100 that can further reduce correction errors can be provided.

[0196] The correction value calculation potential adjustment operation may be performed once, or may be performed multiple times as shown in Fig. 28 (in the example of Fig. 28, it is performed three times). As a result, similar to the sixth embodiment, the difference between the potential of the test signal VS2 and the potential of the threshold signal VREF can be further reduced by repeating the operation of reducing the difference between the two multiple times.

[0197] Furthermore, in the correction value calculation potential adjustment operation, in addition to changing the potential of the test signal VS2 as in the first embodiment, the potential of the threshold signal VREF may be changed as in this embodiment. In other words, both the potential of the test signal VS2 and the potential of the threshold signal VREF may be changed. In this case, the difference between the potential of the test signal VS2 and the potential of the threshold signal VREF can also be reduced.

[0198] [Eighth embodiment] The photoelectric conversion device 100 of this embodiment is a modification of the correction value calculation and potential adjustment operation of the first embodiment shown in Fig. 12. Other elements are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0199] Fig. 29 is a timing diagram illustrating the correction value calculation potential adjustment operation according to this embodiment. As shown in Fig. 29, the photoelectric conversion device 100 according to this embodiment is capable of changing the potential of the test signal VS2 over time. A ramp signal generation circuit as shown in Fig. 26 may be used to generate the test signal VS2 whose potential changes over time.

[0200] At time t25, the test signal supply section 200 starts changing the potential of the test signal VS2 in a time-dependent manner, and the counter 40 starts counting the clock signal CLK and outputting a count signal.

[0201] At time t26, the magnitude relationship between the potential of the test signal VS2 and the potential of the threshold signal VREF is reversed, and the signal value of the comparison result signal CMP changes. The memory unit 50 stores the count value at time t26. At time t27, the counter 40 finishes counting. The horizontal scanning circuit 60 transfers the count value stored in the memory unit 50 to the DSP 80.

[0202] At time t28, the DSP 80 outputs a control signal to the test signal supplying section 200 to change the potential of the test signal VS2 based on the count value, thereby adjusting the potential of the test signal VS2 to match the potential of the threshold signal VREF.

[0203] In this embodiment, by changing the potential of the test signal VS2 and measuring the potential that coincides with the potential of the threshold signal VREF, it is possible to more suitably reduce the difference between the potential of the test signal VS2 and the potential of the threshold signal VREF in a single process. Therefore, according to this embodiment, it is possible to provide a photoelectric conversion device 100 that can further reduce the offset and therefore further reduce the correction error.

[0204] [Ninth embodiment] The photoelectric conversion device in the above-described embodiment can be applied to various devices, such as digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, and surveillance cameras. Fig. 30 shows a block diagram of a digital still camera as an example of such a device.

[0205] The device 7 shown in FIG. 30 includes a barrier 706, a lens 702, an aperture 704, and an imaging device 70 (an example of a photoelectric conversion device). The device 7 also includes a signal processing unit (processing device) 708, a timing generating unit 720, an overall control / calculation unit 718 (control device), a memory unit 710 (storage device), a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. At least one of the barrier 706, the lens 702, and the aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of a subject on the imaging device 70. The aperture 704 varies the amount of light passing through the lens 702. The imaging device 70 is configured as in the above-described embodiment, and converts the optical image formed by the lens 702 into image data (image signals). The signal processing unit 708 performs various corrections, data compression, etc. on the imaging data output from the imaging device 70. The timing generation unit 720 outputs various timing signals to the imaging device 70 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer, etc. Timing signals may be input from outside the device. The device 7 may also include a display device (monitor, electronic viewfinder, etc.) that displays information obtained by the photoelectric conversion device. The device 7 includes at least a photoelectric conversion device. The device 7 further includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. The mechanical device is a movable part (e.g., a robot arm) that operates in response to a signal from the photoelectric conversion device.

[0206] Each pixel may include a plurality of photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process a pixel signal based on the charge generated in the first photoelectric conversion unit and a pixel signal based on the charge generated in the second photoelectric conversion unit, and acquire information about the distance from the image capture device 70 to the subject.

[0207] [Tenth embodiment] 31(a) and 31(b) are block diagrams of devices related to an in-vehicle camera according to this embodiment. The device 8 includes an image capture device 800 (an example of a photoelectric conversion device) according to the above-described embodiment and a signal processing device (processing device) that processes signals from the image capture device 800. The device 8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the image capture device 800, and a parallax calculation unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the device 8. The device 8 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information includes information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0208] The device 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The device 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The device 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel. The device 8 functions as a control means for controlling the operation of controlling the vehicle as described above.

[0209] In this embodiment, the device 8 captures images of the surroundings of the vehicle, for example, the front or rear. FIG. 31(b) shows the device when capturing an image of the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810, which serves as an imaging control means, sends an instruction to the device 8 or the imaging device 800 to perform an imaging operation. This configuration can further improve the accuracy of distance measurement.

[0210] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the present invention is not limited to vehicles such as automobiles, but can be applied to moving objects (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present invention can be applied to a wide range of devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, without being limited to moving objects.

[0211] [Modified embodiment] The present invention is not limited to the above-described embodiments and can be modified in various ways. For example, an example in which part of the configuration of one embodiment is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also an embodiment of the present invention.

[0212] The photoelectric conversion device 100 of the above-described embodiment may be a non-stacked type in which all of the components shown in FIG. 1 or 13 are arranged on a single semiconductor substrate, or may be a stacked type in which these components are arranged on multiple semiconductor substrates that are stacked on top of each other. In the stacked type in which a first substrate and a second substrate are stacked, the pixel section 10 may be arranged on the first substrate. A second substrate different from the first substrate may be arranged with some or all of the components shown in FIG. 1 or 13 other than the pixel section 10. The photoelectric conversion device 100 may also be a stacked type in which a third substrate different from the first and second substrates is further stacked. In this case, each of the second and third substrates may be arranged with some of the components shown in FIG. 1 or 13.

[0213] The functions of the DSP 80 shown in Fig. 4 are merely examples and are not limiting. Functions other than those shown in Fig. 4 may be further included, and some of the functions may be realized by other devices. For example, at least one of the correction value acquisition unit 82 and the correction calculation unit 83 may be disposed in a device external to the photoelectric conversion device 100.

[0214] The sixth to eighth embodiments described above have been described as modified versions of the first embodiment, but the configuration of the second embodiment may be modified to perform the same correction value calculation potential adjustment operation as the sixth to eighth embodiments.

[0215] The disclosure of this specification includes the complement of the concepts described in this specification. In other words, if this specification states, for example, that "A is B" (A=B), then this specification is deemed to disclose or suggest that "A is not B" even if the statement that "A is not B" (A≠B) is omitted. This is because when "A is B," it is assumed that the case where "A is not B" is taken into consideration.

[0216] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0217] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0218] 1 pixel 25 Reference signal supply section 110 AD conversion section 301 Comparison circuit 302 Selection circuit

Claims

1. a pixel that outputs a signal according to the amount of received light; an amplifier that amplifies an input signal by a first gain or a second gain that is smaller than the first gain; a reference signal supply unit that outputs a reference signal whose potential changes depending on time; an analog-to-digital converter including a comparator circuit that compares a potential of the signal output from the amplifier unit with a potential of the reference signal and outputs a comparison result signal, and that performs analog-to-digital conversion of the input signal based on the comparison result signal; and In a first driving mode in which correction values ​​of signals amplified by the first gain and the second gain are obtained, the analog-to-digital conversion unit generates a first digital signal based on a comparison result signal output by the comparison circuit when the comparison circuit compares the signal obtained by amplifying the first analog signal by the first gain with the reference signal, and generates a second digital signal based on a comparison result signal output by the comparison circuit when the comparison circuit compares the signal obtained by amplifying the first analog signal by the second gain with the reference signal, The correction value is obtained based on the first digital signal and the second digital signal; In a second driving mode in which a pixel signal based on an output from the pixel is read out, the comparison circuit compares the potential of the pixel signal with the potential of a threshold signal; the amplifier is set to the first gain when a potential of the pixel signal is smaller than a potential of the threshold signal, and is set to the second gain when the potential of the pixel signal is equal to or greater than a potential of the threshold signal; the analog-to-digital converter performs analog-to-digital conversion of the pixel signal amplified by the set first gain or the set second gain, In a third driving mode for controlling at least one of the first analog signal and the threshold signal, Based on a comparison result signal output by the comparator circuit when the comparator compares the signal obtained by amplifying the first analog signal by the first gain with the threshold signal, at least one of the first analog signal and the threshold signal is controlled so as to reduce a difference between a potential of the signal obtained by amplifying the first analog signal by the first gain and a potential of the threshold signal. A photoelectric conversion device characterized by:

2. After the control in the third driving mode, a ratio of a potential of the signal obtained by amplifying the first analog signal by the first gain to a potential of the threshold signal is equal to or greater than 0.95 and equal to or less than 1.

05.

2. The photoelectric conversion device according to claim 1.

3. In the first driving mode, the analog-to-digital conversion unit generates a third digital signal based on a comparison result signal output by the comparison circuit when the comparison circuit compares a signal obtained by amplifying a second analog signal, different from the first analog signal, by the first gain with the reference signal, and generates a fourth digital signal based on a comparison result signal output by the comparison circuit when the comparison circuit compares a signal obtained by amplifying the second analog signal by the second gain with the reference signal; The correction value is obtained based on the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal.

3. The photoelectric conversion device according to claim 1 or 2.

4. In the third driving mode, the first analog signal is changed to control the potential difference to be reduced.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

5. In the third driving mode, the threshold signal is changed to control the potential difference to be reduced.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

6. The threshold signal is output from the reference signal supply unit.

6. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

7. a signal line through which the signal is output from the pixel; an analog signal supply unit that outputs the first analog signal to the signal line; 7. The photoelectric conversion device according to claim 1, further comprising:

8. In the third driving mode, the analog signal supply unit changes the potential output to the signal line, thereby performing control to reduce the potential difference.

8. The photoelectric conversion device according to claim 7.

9. The analog signal supply unit includes a digital-to-analog conversion circuit.

9. The photoelectric conversion device according to claim 7 or 8.

10. The analog signal supply unit includes a ramp signal generation circuit.

10. The photoelectric conversion device according to claim 7, wherein the first and second electrodes are electrically connected to each other.

11. The control in the third driving mode is executed when the photoelectric conversion device is powered on.

11. The photoelectric conversion device according to claim 1.

12. The control in the third driving mode is executed when the signal acquisition mode of the photoelectric conversion device is changed.

12. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

13. The control in the third driving mode is executed a plurality of times before the correction value is obtained in the first driving mode.

13. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

14. In the third driving mode, control is performed to reduce the potential difference based on a comparison result signal obtained in a state in which the potential of the first analog signal is changed depending on time.

14. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

15. The photoelectric conversion device according to any one of claims 1 to 14, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

16. 16. The device according to claim 15, wherein the processing device processes the image signals generated by the plurality of photoelectric conversion units, respectively, and acquires distance information from the photoelectric conversion units to the subject.

Images