Semiconductor Devices

Abstract

To provide technique enabling reduction of the circuit scale of a crystal oscillation circuit and furthermore enabling shortening of a startup time of the crystal oscillation circuit.SOLUTION: A semiconductor device has a crystal oscillation circuit 10, a first noise application circuit NIC1, and a second noise application circuit NIC2. The first noise application circuit NIC1 is connected to the crystal oscillation circuit 10 and configured in such a manner that initial noises having phases opposite each other are selectively applied to a first external terminal X1 and a second external terminal X2 to thereby drive a crystal oscillator XTAL. The second noise application circuit NIC2 amplifies a signal at the external terminal X1 and returns the amplified signal to the external terminal X1 to thereby apply second noise to the external terminal X1 and drive an oscillation amplifier AMP of the crystal oscillation circuit 10 and the crystal oscillator XTAL, thereby shortening a startup time of the crystal oscillation circuit 10.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, and is particularly a technique that is effective when applied to a semiconductor device having an oscillation circuit that is coupled to a quartz crystal unit and performs oscillation. [Background technology]

[0002] One type of oscillator circuit used in semiconductor devices is one that consists of a crystal resonator, a single-stage amplifier such as an inverter, a feedback resistor, and two external load capacitors. This crystal oscillator circuit has good frequency accuracy but a long start-up time. Non-Patent Document 1 and Non-Patent Document 2 propose techniques for shortening the start-up time of crystal oscillator circuits.

[0003] Non-Patent Document 1 describes a chirp injection method in which the output CLK of a VCO (voltage controlled oscillator) is applied to a crystal oscillator as initial noise to shorten the startup time of the crystal oscillator circuit. Non-Patent Document 2 describes a method in which noise is applied to a crystal oscillator in two stages to shorten the startup time. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] Shunta Iguchi, “92% Start-up Time Reduction by Variation-Tolerant Chirp Injection (CI) and Negative Resistance Booster (NRB) in 39MHz Crystal Oscillator”, IEEE Symposium. VLSI Circuits Digest of Technical Papers, Jun. 2014, pp.236-237 [Non-patent document 2] Karim M. Megawer, “A 54MHz Crystal Oscillator with 30× Start-Up TimeReduction Using 2-Step Injection in 65nm CMOS”, IEEE International Solid-State Circuits Conference(ISSCC), Feb. 2019, pp.302-304 Summary of the Invention [Problem to be solved by the invention]

[0005] In Non-Patent Document 1, it is thought that the effect of reducing the startup time is small when only noise is applied by the VCO, because the VCO frequency and the crystal resonance frequency cross each other only once.

[0006] Non-Patent Document 2 applies a noise frequency that is nearly the same as the crystal frequency in the second stage, which is effective in shortening startup time, but it requires a PLL (phase-locked loop circuit) and a highly precisely trimmed built-in oscillator (DCRO). Non-Patent Document 2 also requires the built-in oscillator to have a frequency accuracy of 0.5% when applying noise in the first stage, but achieving this is technically difficult and would inevitably result in a large circuit size. In other words, Non-Patent Document 2 is effective in shortening startup time, but the large circuit size makes it difficult to apply to mass-produced semiconductor devices.

[0007] An object of the present disclosure is to provide a technology that can reduce the startup time of a crystal oscillation circuit while reducing the circuit size.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A brief summary of representative aspects of this disclosure is as follows.

[0010] According to one embodiment, a semiconductor device includes: a first external terminal; a second external terminal; a crystal oscillation circuit connected to the first external terminal and the second external terminal; a first noise application circuit connected to the crystal oscillation circuit; a second noise application circuit connected to the crystal oscillation circuit; the crystal oscillation circuit includes an oscillation amplifier connected between the first external terminal and the second external terminal, a feedback resistor connected between the first external terminal and the second external terminal, an external first capacitance element connected between the first external terminal and an external ground potential line, an external second capacitance element connected between the second external terminal and the external ground potential line, and an external crystal resonator connected between the first external terminal and the second external terminal, the first noise application circuit is configured to selectively apply initial noises having opposite phases to the first external terminal and the second external terminal to drive the crystal resonator; the second noise application circuit has a third switch, a first capacitive coupling circuit, an amplifier circuit, and a second capacitive coupling circuit; the third switch is provided between the first external terminal and the first capacitive coupling circuit, the amplifier circuit is provided between the first capacitive coupling circuit and the second capacitive coupling circuit, the second capacitive coupling circuit is connected to the first external terminal via the third switch; the first capacitive coupling circuit is configured to separate a DC voltage at the first external terminal from a DC voltage at an input terminal of the amplifier circuit, and to capture an AC component of a signal on the first external terminal; the second capacitive coupling circuit is provided to separate a DC voltage at the output terminal of the amplifier circuit from a DC voltage at the first external terminal, and to output an AC component of the amplifier circuit; the amplifier circuit is provided to amplify the AC component taken in by the first capacitive coupling circuit, convert the amplified AC component into a clock signal, and drive the first external terminal with the converted clock signal; the third switch is provided to disconnect the amplifier circuit from the first external terminal after startup of the crystal oscillation circuit is completed, so that capacitance values ​​of the first capacitive coupling circuit and the second capacitive coupling circuit do not affect oscillation; The second noise application circuit amplifies the signal at the first external terminal and returns the amplified signal to the first external terminal, thereby applying second noise to the first external terminal, driving the oscillation amplifier and the crystal resonator, and shortening the startup time of the crystal oscillation circuit. [Effects of the Invention]

[0011] According to the semiconductor device of the above embodiment, it is possible to reduce the startup time of the crystal oscillation circuit while reducing the circuit size. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a schematic diagram of a semiconductor device including a crystal oscillation circuit according to a first embodiment. [Figure 2] FIG. 2 is a waveform diagram illustrating the operation of the first noise injection circuit NIC1 of FIG. [Figure 3] FIG. 3 is a diagram illustrating the operation of the crystal oscillation circuit 10 when the amplitude is small immediately after the start of oscillation. [Figure 4] FIG. 4 is a diagram illustrating the operation of the crystal oscillation circuit 10 when the amplitude is large after the oscillation has stabilized. [Figure 5] FIG. 5 is a diagram illustrating the operating waveforms of the noise injection circuit NIC2. [Figure 6] FIG. 6 is an equivalent circuit diagram of the oscillator circuit OSC of the first embodiment. [Figure 7] FIG. 7 is a waveform diagram illustrating the operation of the oscillation circuit OSC of the first embodiment. [Figure 8] FIG. 8 is a schematic diagram of a semiconductor device including a crystal oscillation circuit according to the second embodiment. [Figure 9] FIG. 9 is a diagram illustrating the operating waveforms of the noise injection circuit NIC2 of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, examples will be described with reference to the drawings. However, in the following description, the same components will be assigned the same reference numerals, and repeated explanations may be omitted. Note that the drawings may be more schematic than the actual embodiment in order to clarify the description, but they are merely examples and do not limit the interpretation of the present invention. [Example]

[0014] FIG. 1 is a schematic diagram of a semiconductor device including a crystal oscillation circuit according to a first embodiment.

[0015] 1, the semiconductor device 1 has an oscillator circuit OSC formed on a semiconductor chip IC. A clock signal GCLK generated from the oscillator circuit OSC is supplied as an operating clock to a processing device 11 formed on the semiconductor chip IC. The processing device 11 can be, for example, a data processing device such as a central processing unit CPU, a USB (Universal Serial Bus) communication device, or a Bluetooth communication device for BLE (Bluetooth Low Energy) communication.

[0016] The oscillator circuit OSC includes a crystal oscillator circuit 10, a first-stage noise application circuit (also referred to as a first noise application circuit) NIC1, and a second-stage noise application circuit (also referred to as a second noise application circuit) NIC2. The first noise application circuit NIC1 and the second noise application circuit NIC2 are connected to the crystal oscillator circuit 10.

[0017] The crystal oscillation circuit 10 includes an external crystal resonator XTAL, a first external load capacitance element (first capacitance element) Cx1, a second external load capacitance element (second capacitance element) Cx2, a one-stage oscillation amplifier AMP such as an inverter, and a feedback resistance element RF.

[0018] The crystal resonator XTAL is connected outside the semiconductor chip IC between a first external terminal X1 and a second external terminal X2 of the semiconductor device 1. The load capacitance element Cx1 is connected between the external terminal X1 and a ground potential line (external ground potential line) LGND provided outside the semiconductor chip IC. Similarly, the load capacitance element Cx2 is connected between the external terminal X2 and the ground potential line LGND.

[0019] The oscillation amplifier AMP and the feedback resistor RF are connected between the first external terminal X1 and the second external terminal X2 inside the semiconductor chip IC. The oscillation amplifier AMP can be a single-stage inverting amplifier. The feedback resistor RF is connected in parallel to the oscillation amplifier AMP to determine the DC (direct current) operating point of the oscillation amplifier AMP. The oscillation amplifier AMP and the feedback resistor RF drive the external capacitance elements Cx1 and Cx2 and the external crystal resonator XTAL, causing the crystal resonator XTAL to oscillate. The clock signal GCLK generated by the crystal oscillation circuit 10 is output from the output terminal of the oscillation amplifier AMP, which is connected to the second external terminal X2, and supplied to the processing device 11.

[0020] The first noise application circuit NIC1 is connected to the crystal oscillation circuit 10 and is configured to selectively apply initial noises of opposite phases to the first external terminal X1 and the second external terminal X2 to drive the crystal resonator XTAL. The first noise application circuit NIC1 has a first switch SW1, a second switch SW2, an inverter circuit IV1, a voltage-controlled oscillator VCO, a first counter (first counter circuit) CNT1, a capacitance element Ccnt, a constant current circuit CSC, a current switch CSW, and a NAND circuit NA1.

[0021] The output terminal of the voltage-controlled oscillator VCO is connected via a first switch SW1 to a first wiring LX1 connected to a first external terminal X1, so that the output clock of the voltage-controlled oscillator VCO is supplied to the first wiring LX1 connected to the first external terminal X1. The output terminal of the voltage-controlled oscillator VCO is connected via an inverter circuit IV1 and a second switch SW2 to a second wiring LX2 connected to a second external terminal X2, so that the output clock of the voltage-controlled oscillator VCO is inverted by the inverter circuit IV1 and supplied to the second wiring LX2 connected to the second external terminal X2. The first switch SW1 and the second switch SW2 are supplied with a first enable signal EN1, so that the first switch SW1 and the second switch SW2 are selectively turned on when the enable signal EN1 is at a high level, and the first switch SW1 and the second switch SW2 are selectively turned off when the enable signal EN1 is at a low level.

[0022] The input terminal of the voltage-controlled oscillator VCO is connected to the capacitance element Ccnt, and a clock signal oscillating at a frequency based on the voltage Vcnt stored in the capacitance element Ccnt is generated from the output of the voltage-controlled oscillator VCO. The clock signal is supplied to a first switch SW1, a second switch SW2, and a counter CNT1.

[0023] Counter CNT1 counts the clock signals output by the voltage-controlled oscillator VCO. Counter CNT1 counts the number of clock signals. When the count reaches a predetermined number, the output signal of counter CNT1 changes from high level to low level.

[0024] The NAND circuit NA1 has a first input that receives the output signal of the counter CNT1 and a second input that receives the enable signal EN1, and is configured so that a second enable signal EN2 is output from the output of the NAND circuit NA1.

[0025] The constant current circuit CSC includes a pair of P-channel MOSFETs M1 and M2, a first resistor Rcnt, and an inverter-type current switch CSW. The source-drain path of the MOSFET M1 and the resistor Rcnt are connected in series between a power supply line supplied with a power supply potential VDD, which is a first reference potential of the semiconductor device IC, and a ground line supplied with a ground potential GND, which is a second reference potential lower than the first reference potential. The gate of the MOSFET M1 is connected to the gate and drain of the MOSFET M2, and the source of the MOSFET M2 is connected to the power supply line supplied with the power supply potential VDD. In other words, the pair of MOSFETs M1 and M2 are connected in a current mirror configuration, with a mirror ratio (area ratio of the source regions) of the MOSFETs M1 and M2 being M:1. A current I output from the drain of the MOSFET M2 is supplied to the current switch CSW. The resistor Rcnt may be replaced by a current source.

[0026] The current switch CSW is a charge / discharge selector switch in an inverter configuration, and includes a P-channel MOSFET M3 and an N-channel MOSFET M4. The source / drain path of the MOSFET M3 and the source / drain path of the MOSFET M4 are connected in series between the drain of the MOSFET M2 and a ground wiring to which the ground potential GND is supplied. The gate of the MOSFET M3 and the gate of the N-channel MOSFET M4 are connected to receive a second enable signal EN2. The junction of the source / drain path of the MOSFET M3 and the source / drain path of the MOSFET M4 is connected to the capacitance element Ccnt and the input of the voltage-controlled oscillator VCO. The current switch CSW functions as a switch for switching between charging and discharging the capacitance element Ccnt.

[0027] The second noise application circuit NIC2 is configured to include a first capacitive coupling circuit CC1, a clock conversion circuit CCC, an inverter threshold generation circuit IV2, a second resistive element Rbias, a buffer circuit BAF1, a second capacitive coupling circuit CC2, a second counter (second counter circuit) CNT2, and a third switch SW3.

[0028] The third switch SW3 is connected between the first line LX1 and the capacitive coupling circuit CC2, and is configured such that the on and off operations of the third switch SW3 are controlled by the output of the counter CNT2.

[0029] One end of the capacitive coupling circuit CC1 is connected between the third switch SW3 and the capacitive coupling circuit CC2, and the other end of the capacitive coupling circuit CC1 is connected to the input terminal of the clock conversion circuit CCC.

[0030] The threshold generation circuit IV2 is a bias setting circuit that generates a threshold for the inverter. The bias setting circuit is provided to set a bias potential for the input terminal of the clock conversion circuit CCC. The threshold generation circuit IV2 includes an inverter, whose input and output terminals are connected. The input of the inverter is also connected to the input terminal of the clock conversion circuit CCC via a second resistor Rbias. The second resistor Rbias is a high-resistance element that extracts only a DC voltage (direct current voltage) from the threshold generation circuit IV2. The threshold generation circuit IV2 is connected to the input terminal of the clock conversion circuit CCC to set the input terminal of the clock conversion circuit CCC to a predetermined bias potential, i.e., a bias voltage that provides a high gain, enabling small-amplitude signals to be amplified.

[0031] The clock conversion circuit CCC is configured as an amplifier circuit with a Schmitt trigger function (noise reduction function), and its output terminal is connected to the input terminal of the buffer circuit BAF1. The output terminal of the buffer circuit BAF1 is connected to the capacitive coupling circuit CC2 and also to the input terminal of the second counter CNT2.

[0032] The second counter CNT2 receives the clock signal CLK1 from the output terminal of the buffer circuit BAF1 and counts the number of clocks of the clock signal CLK1. When the count reaches a predetermined number, the output signal of the counter CNT2 changes from high to low. The high level of the output signal of the counter CNT2 turns on the third switch SW3, and the low level of the output signal of the counter CNT2 turns off the third switch SW3.

[0033] The first capacitive coupling circuit CC1 is provided to separate the DC (direct current) voltage at the external terminal X1 of the crystal oscillator circuit 10 from the DC voltage at the input terminal of the clock conversion circuit CCC, which is an amplifier circuit, and to capture only the AC (alternating current) component of the signal on the external terminal X1 (wiring Lx1).

[0034] The second capacitive coupling circuit CC2 is provided to separate the DC (direct current) voltage at the output terminal of the clock conversion circuit CCC from the DC (direct current) voltage at the external terminal X1 and output only the AC (alternating current) component of the clock conversion circuit CCC.

[0035] The clock conversion circuit CCC amplifies only the AC component captured by the first capacitive coupling circuit CC1, converts it into a clock signal, and drives the external terminal X1 with this converted clock signal. The converted clock signal is supplied to the external terminal X1 via the second capacitive coupling circuit CC2, and drives the external terminal X1. The noise removal function of the clock conversion circuit CCC is designed to remove harmonic components caused by power supply noise and amplify only the signal component.

[0036] The third switch SW3 is provided to disconnect the clock conversion circuit CCC from the external terminal X1 after startup of the crystal oscillation circuit 10 is complete, thereby preventing the capacitance values ​​of the first capacitive coupling circuit CC1 and the second capacitive coupling circuit CC2 from affecting oscillation. The control signal that controls the third switch SW3 is also connected to the clock conversion circuit CCC and the buffer circuit BAF1, and is configured to also stop the clock conversion circuit CCC and the buffer circuit BAF1 after startup is complete.

[0037] The second noise application circuit NIC2 amplifies the signal at the external terminal X1 and applies the second noise to the external terminal X1 by returning the amplified signal to the external terminal X1, thereby driving the oscillation amplifier AMP and the crystal resonator XTAL and shortening the start-up time of the crystal oscillation circuit 10.

[0038] The oscillator circuit OSC of this embodiment can reduce the startup time of the crystal oscillator circuit 10 by using the first-stage noise injection circuit NIC1 and the second-stage noise injection circuit NIC2. The operation of the noise injection circuit NIC1 and the noise injection circuit NIC2 will now be described.

[0039] (Explanation of the first noise injection circuit NIC1) The operation of the noise injection circuit NIC1 will be described with reference to Figures 1 and 2. Figure 2 is a waveform diagram illustrating the operation of the first noise injection circuit NIC1 of Figure 1. Figure 2 shows waveforms of EN1, EN2, voltage Vcnt, the output of counter CNT1, and external terminals X1 and X2.

[0040] The noise injection circuit NIC1 is used when the oscillation amplifier AMP and the second-stage noise injection circuit NIC2 are OFF. At this time, EN1 = H (high level), SW1 = SW2 = ON (on state), and SW3 = OFF (off state). Switches SW1 and SW2 apply the output of the voltage-controlled oscillator VCO to external terminals X1 and X2 when the noise injection circuit NIC1 is operating, and disconnect the output of the voltage-controlled oscillator VCO from external terminals X1 and X2 when the noise injection circuit NIC1 is OFF.

[0041] The noise injection circuit NIC1 is composed of a constant current circuit CSC, a current switch CSW, a capacitance element Ccnt, a voltage-controlled oscillator VCO whose output frequency can be varied by the voltage of Vcnt, and a counter CNT1 to which its output is connected.The output of the voltage-controlled oscillator VCO is connected to the input (wire Lx1 side) and output (wire Lx2 side) of the oscillation amplifier AMP, and the output clocks of the voltage-controlled oscillator VCO applied to external terminals X1 and X2 have opposite phases to each other.

[0042] During standby (EN1 = L (low level)), the current switch CSW keeps the voltage Vcnt at the GND level (ground potential level). When the noise injection circuit NIC1 begins to operate, the voltage Vcnt is slowly charged toward VDD using a time constant determined by the capacitance element Ccnt and the current I, slowly increasing the output frequency of the voltage-controlled oscillator VCO and causing the resonant frequency of the crystal resonator XTAL and the frequency of the voltage-controlled oscillator VCO to intersect.

[0043] The output of the voltage-controlled oscillator VCO is also connected to a counter CNT1, which counts the frequency and serves to turn off the noise injection circuit NIC1 after a certain period of time has elapsed.

[0044] (Explanation of the second noise injection circuit NIC2) The noise injection circuit NIC2 starts operating after the operation of the noise injection circuit NIC1 is completed. At this time, the noise injection circuit NIC2 and the oscillation amplifier AMP are simultaneously turned ON, with SW1=SW2=OFF and SW3=ON.

[0045] The noise injection circuit NIC2 must be connected to the external terminal X1 (line Lx1). The reason for connecting the noise injection circuit NIC2 to the external terminal X1 is that injecting noise into the external terminal X1 is more effective in shortening the startup time of the crystal oscillator circuit 10. After the noise injection circuit NIC1 is activated, the oscillation amplitude of the crystal resonator XTAL is generated at the external terminals X1 and X2, and the amplitude at the external terminal X2 (line Lx2) grows faster. However, the phases of the external terminals X1 and X2 are not completely out of phase with each other; they are shifted by approximately 90 degrees from 180 degrees. Therefore, the signal at the external terminal X2 cannot be inverted and returned to the external terminal X1 (as will be explained in Figures 3 and 4). For these reasons, the signal at the external terminal X1 must be amplified and returned directly to the external terminal X1. To shorten the startup time, the delay time from the capacitive coupling circuit CC1 to the third switch SW3 must be kept to less than one-quarter of the oscillation frequency period (as will be explained in Figure 5).

[0046] When the noise injection circuit NIC2 begins operating, it takes in the oscillation amplitude of the external terminal X1 (wire Lx1) through the capacitive coupling circuit CC1, amplifies it using the clock conversion circuit CCC and buffer circuit BAF1, converts it into a clock, and returns it to the external terminal X1 (wire Lx1) through the capacitive coupling circuit CC2. When the noise injection circuit NIC2 begins operating, the oscillation amplitude of the external terminal X1 (wire Lx1) is very small, about 10 mVpp, as shown in Figure 1, and cannot be converted into a clock as is. Therefore, the capacitive coupling circuit CC1 separates the DC (direct current) voltage of the external terminal X1 of the oscillation amplifier AMP from the DC voltage of the clock conversion circuit CCC. At this time, the DC voltage threshold of the clock conversion circuit CCC is set by the threshold generation circuit IV2, which shorts the input and output of the inverter, and the high-resistance resistor element Rbias, which extracts only the DC signal from it. Furthermore, because power supply noise and other noises are superimposed on the small oscillation amplitude (about 10 mVpp) of external terminal X1, the clock conversion circuit CCC must be equipped with a Schmitt trigger circuit (with noise removal functionality) to remove this noise. The Schmitt trigger circuit is an example of a return path with noise removal functionality.

[0047] A buffer circuit BAF1 is connected to the output of the clock conversion circuit CCC in order to further amplify the output of the clock conversion circuit CCC and bring it closer to an ideal clock.

[0048] The capacitive coupling circuit CC2 is a capacitor that separates the DC voltage output by the buffer circuit BAF1 from the DC bias voltage of the external terminal X1. If the clock generated by the buffer circuit BAF1 were input directly to the external terminal X1 without going through the capacitive coupling circuit CC2, the oscillation of the crystal resonator XTAL connected to the external terminal X1 would stop, and therefore this capacitive coupling circuit CC2 is necessary.

[0049] The noise injection circuit NIC2 will continue to operate if left as is, so it must be stopped. By counting the output of the buffer circuit BAF1 with the counter CNT2, the third switch SW3 is turned off after a certain period of time has elapsed, and the noise injection circuit NIC2 itself is also turned off as necessary.

[0050] (Explanation of the phase of external terminals X1 and X2) First, the operation of the crystal oscillation circuit 10 when the amplitude is small immediately after oscillation starts will be explained using Figure 3. Figure 3 is a diagram explaining the operation of the crystal oscillation circuit 10 when the amplitude is small immediately after oscillation starts. In Figure 3, (A) shows the configuration of the crystal oscillation circuit 10, and the loop formed by the oscillation amplifier AMP and the crystal resonator XTAL is cut at the part marked with an x. A simulation was performed using the equivalent circuit configuration shown in (B), and the phases of points v1 (X1), v2 (X2), and v1' were considered. (C) in Figure 3 is a graph showing the results of the simulation.

[0051] Immediately after oscillation begins, when the amplitude is small, the phase difference between external terminals X1 and X2 is 270°. As shown in Figure 3(C), the amplitude of external terminal X2 grows rapidly, so it would seem better to convert the amplitude of external terminal X2 into a clock. However, at the small amplitude immediately after oscillation begins, the phase difference between external terminals X1 and X2 is 270°, not 180°. Therefore, even if the amplitude of external terminal X2 is converted into a clock (CLKX2), inverted to generate an inverted clock ( / CLKX2), and returned to external terminal X1 with zero delay difference, the constraint of being within 1 / 4 of the oscillation frequency period (T3) (>(1 / 4) T3) cannot be met. In other words, if a clock (CLKX2) is generated at external terminal X2 (point v2) and then returned to external terminal X1 (point v1), there will always be a delay of at least 1 / 4 of a period. Therefore, a clock must be generated from external terminal X1 and returned to external terminal X1.

[0052] Next, we will first use Figure 4 to explain the operation of the crystal oscillation circuit 10 when the amplitude is large after oscillation has stabilized. Figure 4 is a diagram that explains the operation of the crystal oscillation circuit 10 when the amplitude is large after oscillation has stabilized. In Figure 4, (A) shows an equivalent circuit configuration of the crystal oscillation circuit 10, and a simulation was performed using this circuit configuration to consider the phases at point v1 (X1), point v2 (X2), and point v1'. (B) in Figure 4 is a graph showing the results of the simulation. After oscillation has stabilized and the amplitude is large, the phase difference between external terminals X1 and X2 is 180°.

[0053] (Explanation of the waveform inside the noise injection circuit NIC2) Next, the waveforms inside the noise injection circuit NIC2 will be described with reference to Fig. 5. Fig. 5 is a diagram illustrating the operating waveforms of the noise injection circuit NIC2.

[0054] In Figure 5, (A) shows the waveform of the first capacitive coupling circuit CC1, where the peak-to-peak differential potential (the differential potential between the highest and lowest values) is approximately 10 mVpp. (B) shows the waveform of the output of the buffer circuit BAF1. The waveform of the output of the buffer circuit BAF1 (B) is a clock generated from the waveform of the capacitive coupling circuit CC1 (A). (C) shows the waveform of the third switch SW3 after passing through the buffer circuit BAF1 and the second capacitive coupling circuit CC2. Electric charge is generated by the output of the buffer circuit BAF1 and the second capacitive coupling circuit CC2. The delay time td between the output of the capacitive coupling circuit CC1 and the buffer circuit BAF1 is set to 1 / 4 period or less. (D) shows the waveform of the output of the buffer circuit BAF1 of the signal returning from the third switch SW3 to the capacitive coupling circuit CC1, where the clock generation is repeated. (E) shows the waveform of the third switch SW3 after passing through the buffer circuit BAF1 and the second capacitive coupling circuit CC2 again, where the charge operation is repeated.

[0055] Next, this embodiment will be summarized with reference to Fig. 6 and Fig. 7. Fig. 6 is an equivalent circuit diagram of the oscillation circuit OSC of the first embodiment. Fig. 7 is a waveform diagram illustrating the operation of the oscillation circuit OSC of the first embodiment.

[0056] As shown in Figure 6, the oscillator circuit OSC of the first embodiment has a crystal oscillator circuit 10 connected to a first-stage noise injection circuit NIC1 and a second-stage noise injection circuit NIC2, thereby reducing the startup time of the oscillator circuit OSC. In Figure 6, the noise injection circuit NIC1 is equivalently depicted as including a voltage-controlled oscillator VCO (oscillating circuit) OS, a first switch SW1 that selectively supplies the oscillation output (fVCO) of the voltage-controlled oscillator VCO to an external terminal X1, an inverter IV1 that inverts the oscillation output (fVCO) of the voltage-controlled oscillator VCO, and an inverter SW2 that selectively supplies the oscillation output inverted by the inverter to an external terminal X2. The noise injection circuit NIC2 includes a clock conversion circuit CCC (amplifying circuit), a first capacitive coupling circuit CC1 connected between the external terminal X1 and the input terminal of the clock conversion circuit CCC, and a second capacitive coupling circuit CC2 connected between the output terminal of the clock conversion circuit CCC and the external terminal X1.

[0057] The noise for shortening the startup time is divided into a first noise generated from a first-stage noise application circuit NIC1 and a second noise generated from a second-stage noise application circuit NIC2, and applied to the crystal oscillation circuit 10.

[0058] The noise injection by the second-stage noise injection circuit NIC2 is characterized in that it amplifies a signal of exactly the same frequency as the resonant frequency (fxtal) of the crystal unit XTAL and applies it to the crystal unit XTAL.

[0059] After the first-stage noise injection circuit NIC1 is turned OFF, the second-stage noise injection circuit NIC2 and oscillation amplifier AMP are turned ON together. In the noise injection circuit NIC2, the capacitive coupling circuit CC1, the clock conversion circuit CCC (an amplifier circuit), and the capacitive coupling circuit CC2 amplify the small-amplitude crystal oscillation signal generated at external terminal X1 by the first-stage noise injection circuit NIC1, and return it to external terminal X1, which is the input of the noise injection circuit NIC2 itself.

[0060] As shown in Figure 7, first, the noise injection circuit NIC1 is turned ON (at this time, the noise injection circuit NIC2 and the oscillation amplifier AMP are OFF). This causes the voltage-controlled oscillator VCO to oscillate based on the voltage Vcnt. Then, the oscillation output (fvco) of the voltage-controlled oscillator VCO and its inverted oscillation signal are applied to the external terminals X1 and X2 as the first noise.

[0061] Next, the noise injection circuit NIC1 is turned off, and the noise injection circuit NIC2 and oscillation amplifier AMP are turned on. A clock signal CLK1 is generated in the noise injection circuit NIC2, and the resulting signal, which passes through the capacitive coupling circuit CC2, is applied to the external terminal X1 as second noise. The second noise has the exact same frequency as the resonant frequency (fxtal) of the crystal resonator XTAL. This causes the crystal oscillation circuit 10 to begin oscillating.

[0062] After that, the noise injection circuit NIC2 is turned off, and the crystal oscillation circuit 10 oscillates with high frequency accuracy (oscillation state at fxtal). Therefore, the start-up time Tstart of the crystal oscillation circuit 10 can be shortened. Here, the start-up time Tstart is the time from when the noise injection circuit NIC1 is turned on until the crystal oscillation circuit 10 oscillates with high frequency accuracy.

[0063] According to the first embodiment, the following effects can be obtained.

[0064] 1) The startup time of the crystal oscillator circuit can be significantly reduced. In the first embodiment, when a 16 MHz crystal oscillator is used, the startup time of the crystal oscillator circuit can be reduced to a range of 0.14 ms to 0.38 ms. The startup time of the crystal oscillator circuit prior to the first embodiment was in the range of 0.98 ms to 1.40 ms.

[0065] 2) In semiconductor device applications where high frequency accuracy of the crystal oscillator is required and low power consumption is also required, the power consumption of the semiconductor device can be reduced by intermittently operating the semiconductor device.

[0066] 3) The startup time of the crystal oscillator circuit can be shortened and the overall circuit scale of the oscillator circuit OSC can be reduced.Since the overall circuit scale of the oscillator circuit OSC is small, an increase in the chip area of ​​the semiconductor device can be prevented, making it easy to apply the semiconductor device to mass-produced products. [Example]

[0067] Next, an oscillator circuit OSC according to a second embodiment will be described with reference to Fig. 8. Fig. 8 is a schematic configuration diagram of a semiconductor device including a crystal oscillator circuit according to a second embodiment. Fig. 9 is a diagram illustrating the operating waveforms of the noise injection circuit NIC2 of Fig. 8.

[0068] In the oscillator circuit OSC of the second embodiment, as compared with the oscillator circuit OSC of the first embodiment, for example, a capacitive coupling circuit CC2 is configured with five capacitive elements C01-C05 and five switch elements (capacitance selection switch elements) SW31-SW35. The five switch elements SW31-SW5 of the five capacitive elements C01-C05 are connected between the output terminal of the buffer circuit BAF1 and the third switch SW3 (external terminal X1). That is, "a plurality of pairs of one capacitance element and one switch element are connected in parallel between the output terminal of the buffer circuit BAF1 and the third switch SW3. The capacitance values ​​of the capacitance elements C01-C05 are set to weighted capacitance values, for example, 0.2 pF, 0.2 pF, 0.4 pF, 0.6 pF, and 0.6 pF. The output of the second counter circuit CNT2 is connected to the newly added switch elements SW31-SW35 (one switch element is provided for one capacitance element). The switch elements SW31-SW35 are configured to be able to switch the overall capacitance value of the capacitive coupling circuit CC2. The counter circuit CNT2 The on / off of the switch elements SW31-SW35 is controlled by the output of the second counter circuit CNT2 so that the overall capacitance value of the capacitive coupling circuit CC2 increases stepwise over time in accordance with the count number. That is, first, switch element SW31 turns on, then switch element SW32 turns on, switch element SW33 turns on, switch element SW34 turns on, and finally switch element SW35 turns on. As a result, the overall capacitance value (Ctotal) of the capacitive coupling circuit CC2 changes from 0.2 pF to 0.4 pF to 0.8 pF to 1.4 pF to 2.0 pF. This significantly reduces the startup time.

[0069] The second counter circuit CNT2 counts the output clock of the clock conversion circuit CCC and sequentially turns on the switch elements SW31-SW35 of the capacitive elements C01-C05 at predetermined intervals, thereby increasing the capacitance between the output terminal of the clock conversion circuit CCC and the third switch SW3 over time. Five control signals CT1, which are the counter outputs of the second counter circuit CNT2, are connected to the five switch elements SW31-SW35, respectively. After startup is complete, these five switch elements SW31-SW35 and the third switch element SW3 are turned off based on the counter output of the second counter circuit CNT2. The control signal CT2, which is the output signal of the second counter circuit CNT2, is configured to shut down the entire second noise injection circuit NIC2 (the clock conversion circuit CCC, which is an amplifier circuit, and the threshold generation circuit IV2, which is a bias setting circuit) after a certain period of time has elapsed. Although not shown in FIG. 1, shutting down the clock conversion circuit CCC and the threshold generation circuit IV2 using the control signal CT2 can also be used in Example 1.

[0070] In Figure 9, (A) shows the waveform of the first capacitive coupling circuit CC1. The peak-to-peak potential difference (the potential difference between the highest and lowest values) of the waveform is approximately 10 mVpp. (B) shows the waveform of the output of the buffer circuit BAF1. The waveform of the output of the buffer circuit BAF1 (B) is a clock generated from the waveform of the capacitive coupling circuit CC1 (A). (C) shows the waveform of the third switch SW3 after passing through the buffer circuit BAF1 and the second capacitive coupling circuit CC2. Charge is generated by the output of the buffer circuit BAF1 and the second capacitive coupling circuit CC2. The delay time td between the output of the capacitive coupling circuit CC1 and the buffer circuit BAF1 is set to 1 / 4 period or less. The charge is generated by the capacitive coupling circuit CC2. However, if the capacitance value of the capacitive coupling circuit CC2 is too small relative to the amplitude of the sine wave in (C), the effect is insufficient. If it is too large, the sine wave will be distorted and out of phase. Therefore, the capacitance value of the capacitive coupling circuit CC2 must be optimized depending on the amplitude. 8, by configuring the capacitive coupling circuit CC2 with five capacitive elements C01-C05 and five switches SW31-SW35, the overall capacitance value of the capacitive coupling circuit CC2 can be adjusted to an optimum value depending on the amplitude, thereby shortening the start-up time of the crystal oscillation circuit 10.

[0071] In the second embodiment, the same effects as those in the first embodiment can be obtained.

[0072] The invention made by the inventor has been specifically described above based on examples, but it goes without saying that the present invention is not limited to the above-described embodiments and examples, and various modifications are possible. [Explanation of symbols]

[0073] 1: Semiconductor device 10: Crystal oscillator circuit NIC1: First noise injection circuit NIC2: Second noise injection circuit

Claims

1. a first external terminal; a second external terminal; a crystal oscillation circuit connected to the first external terminal and the second external terminal; a first noise application circuit connected to the crystal oscillation circuit; a second noise application circuit connected to the crystal oscillation circuit; the crystal oscillation circuit includes: an oscillation amplifier connected between the first external terminal and the second external terminal; a feedback resistor connected between the first external terminal and the second external terminal; an external first capacitance element connected between the first external terminal and an external ground potential line; an external second capacitance element connected between the second external terminal and the external ground potential line; and an external crystal resonator connected between the first external terminal and the second external terminal; the first noise application circuit is configured to selectively apply initial noises having opposite phases to the first external terminal and the second external terminal to drive the crystal resonator; the second noise application circuit includes a third switch, a first capacitive coupling circuit, an amplifier circuit, and a second capacitive coupling circuit; the third switch is provided between the first external terminal and the first capacitive coupling circuit, the amplifier circuit is provided between the first capacitive coupling circuit and the second capacitive coupling circuit, the second capacitive coupling circuit is connected to the first external terminal via the third switch; the first capacitive coupling circuit is configured to separate a DC voltage at the first external terminal from a DC voltage at an input terminal of the amplifier circuit, and to capture an AC component of a signal on the first external terminal; the second capacitive coupling circuit is provided to separate a DC voltage at the output terminal of the amplifier circuit from a DC voltage at the first external terminal, and to output an AC component of the amplifier circuit; the amplifier circuit amplifies the AC component captured by the first capacitive coupling circuit, converts the AC component into a clock signal, and drives the first external terminal with the converted clock signal; the third switch is provided to disconnect the amplifier circuit from the first external terminal after startup of the crystal oscillation circuit is completed, so that capacitance values ​​of the first capacitive coupling circuit and the second capacitive coupling circuit do not affect oscillation; the second noise application circuit amplifies the signal at the first external terminal and returns the amplified signal to the first external terminal, thereby applying second noise to the first external terminal, thereby driving the oscillation amplifier and the crystal resonator, and shortening the startup time of the crystal oscillation circuit.

2. 2. The semiconductor device of claim 1, The amplifier circuit has a noise removal function to remove harmonic components due to power supply noise and amplify only the signal components.

3. 2. The semiconductor device of claim 1, The first noise injection circuit an oscillator; a first switch provided between an output terminal of the oscillator and the first external terminal; an inverter circuit and a second switch provided between the output terminal of the oscillator and the second external terminal, the oscillator generates the initial noise; The semiconductor device, wherein the first switch and the second switch are turned off after the initial noise is applied to the first external terminal and the second external terminal.

4. 4. The semiconductor device of claim 3, the oscillator includes a voltage controlled oscillator; The semiconductor device slowly increases the frequency of the voltage-controlled oscillator so that the resonant frequency of the crystal resonator and the frequency of the voltage-controlled oscillator intersect.

5. 2. The semiconductor device of claim 1, The second capacitive coupling circuit is A plurality of pairs of one capacitance element and one switch element are connected in parallel, a counter circuit that counts the output clock of the amplifier circuit; the counter circuit sequentially turns on a plurality of switch elements in the plurality of sets at predetermined time intervals, thereby increasing a capacitance value between the output terminal of the amplifier circuit and the first external terminal over time.

6. 6. The semiconductor device of claim 5, The semiconductor device, wherein the plurality of switch elements and the third switch are turned off after startup of the crystal oscillation circuit is completed.

7. 6. The semiconductor device of claim 5, a bias setting circuit that sets the input terminal of the amplifier circuit to a predetermined bias potential; The control signal generated by the counter circuit stops the operation of the amplifier circuit and the bias setting circuit after a certain time has elapsed.

8. 2. The semiconductor device of claim 1, The second capacitive coupling circuit is a counter circuit that counts the output clock of the amplifier circuit; a bias setting circuit that sets the input terminal of the amplifier circuit to a predetermined bias potential.

9. 9. The semiconductor device of claim 8, The control signal generated by the counter circuit stops the operation of the amplifier circuit and the bias setting circuit after a certain time has elapsed.

Images