Signal level conversion circuit, drive circuit, display driver and display device

Abstract

To provide a driving circuit, a display driver, and a display device that convert an input voltage signal of a low voltage into a first polarity high voltage signal and a second polarity high voltage signal.SOLUTION: A driving circuit 200_1 contains: a transistor switch 11 that supplies a voltage of a first node Ns11 to an output terminal DL1 at an ON state, and disconnects a connection between the first node and the output terminal at an OFF state; a positive electrode output SW control unit 112 that supplies a second polarity high voltage output control signal GP performing an ON / OFF control of the transistor switch 11 to a control terminal of the transistor switch 11 in response to second polarity high voltage control signals SB4 L and XSB4 L; and a signal level conversion circuit 100_2.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a signal level conversion circuit that converts an input signal into a high-voltage signal of positive polarity and a high-voltage signal of negative polarity, a drive circuit including the signal level conversion circuit, and a display driver and display device including the drive circuit. [Background technology]

[0002] Currently, liquid crystal display devices using active matrix driven liquid crystal panels are used as display devices in a variety of applications, including TVs, monitors, PCs, car navigation systems, etc. These liquid crystal display devices are becoming larger in screen size and higher in quality every year, and there is an increasing demand for higher resolution and higher driving frequencies.

[0003] The liquid crystal panel has a plurality of data lines that extend vertically on the two-dimensional screen and a plurality of gate lines that extend horizontally on the two-dimensional screen, and each of the data lines and gate lines is arranged to intersect with each other. Furthermore, at each intersection of the data lines and gate lines, a pixel portion connected to the data lines and gate lines is formed.

[0004] A liquid crystal display device includes such a liquid crystal panel as well as a data driver that supplies grayscale data signals having analog voltage values ​​corresponding to the luminance levels of each pixel to data lines using data pulses in units of one horizontal scanning period.

[0005] In order to prevent deterioration of the liquid crystal panel, the data driver performs polarity inversion driving, which alternately supplies a grayscale data signal of a first polarity (positive polarity) and a grayscale data signal of a second polarity (negative polarity) to the liquid crystal panel every predetermined frame period.

[0006] As a data driver that performs such polarity inversion driving, one has been proposed that includes a drive circuit that switches between a positive drive voltage and a negative drive voltage based on 0 volts and outputs them (see, for example, Figures 8 to 10 of Patent Document 1). The drive circuit described in Patent Document 1 uses switches SW1 to SW12 shown in Figure 8 of the same document to switch from a state in which a positive voltage signal (5 V) is output from output pad OUT1 (the state in Figure 8 of the same document) to a state in which a negative voltage signal (-5 V) is output from output pad OUT1 (the state in Figure 10 of the same document).

[0007] Furthermore, when switching polarity in this way, the drive circuit first sets one end of each switch to 0V as shown in Figure 9 of the same document, and then switches it to the state shown in Figure 10 of the same document. This makes it possible to configure each switch (transistor) using low-voltage elements whose normal operating withstand voltage is approximately half the liquid crystal drive voltage range. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-102211 Summary of the Invention [Problem to be solved by the invention]

[0009] The switch SW1 described in Patent Document 1 is a switch (e.g., a CMOS transistor switch) that passes a positive voltage signal (0V to 5V) and operates within the positive voltage range. The switch SW9 is a switch (e.g., an NMOS transistor switch) that resets the node that passes the positive voltage signal to 0V and operates within the positive voltage range. The switch SW5 outputs a positive voltage signal (0V to 5V) to the output terminal OUT1 when on, and blocks the negative voltage signal (0V to -5V) output to the output terminal OUT1 when off so that it does not enter the positive voltage signal output circuit. For this reason, the switch SW5 is configured as a PMOS transistor switch. In this case, in order for the PMOS transistor switch SW5 to pass the positive voltage signal (0V to 5V), the gate of the PMOS transistor switch SW5 must be controlled within the negative voltage range (0V to -5V) within the device's withstand voltage. Switch SW2 is a switch (e.g., a CMOS transistor switch) that passes a negative voltage signal (0V to -5V) and operates within the negative voltage range. Switch SW10 is a switch (e.g., a PMOS transistor switch) that resets the node that passes the negative voltage signal to 0V and operates within the negative voltage range. Switch SW6 outputs a negative voltage signal (0V to -5V) to output terminal OUT1 when on, and blocks the positive voltage signal (0V to 5V) output to output terminal OUT1 when off so that it does not enter the negative voltage signal output circuit. For this reason, switch SW6 is configured as an NMOS transistor switch. In order for NMOS transistor switch SW6 to pass a negative voltage signal (0V to -5V), the gate of NMOS transistor switch SW6 must be controlled within the positive voltage range (0V to 5V) within the device's withstand voltage.

[0010] As described above, in the drive circuit described in Patent Document 1, when a positive voltage signal is output to output terminal OUT1, switches SW1 and SW9 must be controlled with a control signal in the positive voltage range, and switch SW5 must be controlled with a control signal in the negative voltage range. Also, when a negative voltage signal is output to output terminal OUT1, switches SW2 and SW10 must be controlled with a control signal in the negative voltage range, and switch SW6 must be controlled with a control signal in the positive voltage range.

[0011] Furthermore, in the above drive circuit, in order to correctly switch polarity, it is necessary to synchronize the timing of the positive control signal and the negative control signal.

[0012] However, the circuit (positive control circuit) for the positive control signal is configured within the positive side's withstand voltage range (0V to 5V), and the circuit (negative control circuit) for the negative control signal is configured within the negative side's withstand voltage range (0V to -5V), and from the perspective of cost reduction, elements with a withstand voltage spanning both positive and negative voltage ranges cannot be used. Also, due to the circuit configuration, there are cases where the circuit delay of the positive control circuit and the circuit delay of the negative control circuit do not match.

[0013] In this case, if the timing of the positive control signal and the negative control signal is not synchronized, signal noise and increased power consumption may occur due to the generation of a through current within the drive circuit during drive control by the drive circuit, or the ability to handle high drive frequencies may be limited by extending the period during which one end of the switch is driven to 0V to prevent the element from exceeding its withstand voltage when switching polarity.

[0014] Therefore, an object of the present invention is to provide a signal level conversion circuit that can convert a low-voltage input voltage signal into a high-voltage signal of a first polarity and a high-voltage signal of a second polarity using a switch element with a lower element breakdown voltage than the output voltage range, and output these signals at synchronized timing, as well as a drive circuit, a display driver, and a display device that include the signal level conversion circuit. [Means for solving the problem]

[0015] A signal level conversion circuit according to the present invention is a signal level conversion circuit that level-shifts the amplitude of an input voltage signal, and includes: a first level shift unit that generates a voltage signal by converting the amplitude of the input voltage signal into an amplitude between a first power supply voltage having a first polarity with respect to a predetermined reference power supply voltage and a second power supply voltage having a second polarity with respect to the reference power supply voltage that is opposite to the first polarity; The power supply voltage regulator may further include a second level shift unit that converts the amplitude of the voltage signal into an amplitude between the reference power supply voltage and the first power supply voltage, and generates, as a first polarity voltage signal, a signal obtained by converting the amplitude of the first polarity voltage signal into an amplitude between the reference power supply voltage and a third power supply voltage of a first polarity whose voltage difference from the reference power supply voltage is larger than the first power supply voltage, and outputs, as a first polarity high voltage signal, a signal obtained by converting the amplitude of the voltage signal generated by the first level shift unit into an amplitude between the reference power supply voltage and the second power supply voltage, and a fifth level shift unit that converts the amplitude of the second polarity voltage signal into an amplitude between the reference power supply voltage and a fourth power supply voltage of a second polarity whose voltage difference from the reference power supply voltage is larger than the second power supply voltage, and outputs, as a second polarity high voltage signal.

[0016] A signal level conversion circuit according to the present invention is a signal level conversion circuit that level-shifts the amplitudes of first and second input voltage signals, and includes a first level shift unit that generates a first voltage signal by converting the amplitude of the first input voltage signal into an amplitude between a first power supply voltage of a first polarity with respect to a predetermined reference power supply voltage and a second power supply voltage of a second polarity with respect to the reference power supply voltage and opposite polarity to the first polarity; a second level shift unit that converts the amplitude of the first voltage signal into an amplitude between the reference power supply voltage and the first power supply voltage and generates a first polarity voltage signal; a third level shift unit that converts the amplitude of the second input voltage signal into an amplitude between the first power supply voltage and the second power supply voltage, and outputs the converted signal as a high-voltage signal of a first polarity; a fourth level shift unit that generates a second voltage signal by converting the amplitude of the second voltage signal into an amplitude between the reference power supply voltage and the second power supply voltage; a fifth level shift unit that converts the amplitude of the second voltage signal into an amplitude between the reference power supply voltage and the second power supply voltage, and generates a second-polarity voltage signal; and a sixth level shift unit that converts the amplitude of the second-polarity voltage signal into an amplitude between the reference power supply voltage and a fourth power supply voltage of a second polarity whose voltage difference from the reference power supply voltage is larger than that of the second power supply voltage, and outputs the second-polarity high-voltage signal.

[0017] A drive circuit according to the present invention has drive timing controlled based on a group of low-voltage control signals, and outputs a first-polarity drive voltage signal of a high voltage having a first polarity relative to a predetermined reference power supply voltage from an output terminal when driving a load, the drive circuit including an output section that receives a high-voltage input signal of a first polarity, and outputs the first-polarity drive voltage signal obtained by amplifying the high-voltage input signal of the first polarity to a first node in response to a high-voltage control signal of a first polarity; a first conductivity type transistor switch that supplies the voltage of the first node to the output terminal in an on state, and cuts off the connection between the first node and the output terminal in an off state; a control section that supplies a high-voltage output control signal of a second polarity to a control terminal of the first conductivity type transistor switch in response to a high-voltage control signal of a second polarity that controls the on / off of the first conductivity type transistor switch; and first and second signal level conversion circuits. and a signal level conversion unit including a path, wherein the first signal level conversion circuit converts the amplitude of a first control signal of the group of low-voltage control signals to an amplitude between a first power supply voltage of a first polarity and a second power supply voltage of a second polarity, and then converts the amplitude to an amplitude between a third power supply voltage of a first polarity whose voltage difference from the reference power supply voltage is larger than the first power supply voltage, and the reference power supply voltage, and supplies the generated signal to the first output unit as the first high-voltage control signal of the first polarity, and the second signal level conversion circuit converts the amplitude of a second control signal of the group of low-voltage control signals to an amplitude between the first power supply voltage of a first polarity and the second power supply voltage of a second polarity, and then converts the amplitude to an amplitude between a fourth power supply voltage of a second polarity whose voltage difference from the reference power supply voltage is larger than the second power supply voltage, and the reference power supply voltage, and supplies the generated signal to the first control unit as the first high-voltage control signal of the second polarity.

[0018] A drive circuit according to the present invention has drive timing controlled based on a group of low-voltage control signals, and when driving a load, selects one of a first-polarity drive voltage signal having a high voltage of a first polarity and a second-polarity drive voltage signal having a high voltage of a second polarity with respect to a predetermined reference power supply voltage, and outputs the selected signal from an output terminal, the drive circuit comprising: a first output section that receives a high-voltage input signal of a first polarity, amplifies the high-voltage input signal of the first polarity, and outputs the amplified first-polarity drive voltage signal to a first node in response to a first high-voltage control signal of the first polarity; and a second output section that supplies the voltage of the first node to the output terminal in an on state, and cuts off the connection between the first node and the output terminal in an off state. a first control section that supplies a high-voltage output control signal of a second polarity to a control terminal of the first conductivity type transistor switch in response to a first high-voltage control signal of a second polarity, the high-voltage output control signal controlling the on / off of the first conductivity type transistor switch; a second output section that receives a high-voltage input signal of a second polarity, and outputs the second-polarity drive voltage signal obtained by amplifying the high-voltage input signal of the second polarity to a second node in response to the second high-voltage control signal of the second polarity; and a second conductivity type transistor switch that supplies the voltage of the second node to the output terminal in an on state, and cuts off the connection between the second node and the output terminal in an off state.a second control unit that supplies a high-voltage output control signal of a first polarity to a control end of the second conductivity type transistor switch in response to a second high-voltage control signal of a first polarity, the high-voltage output control signal controlling on / off of the second conductivity type transistor switch; and a signal level conversion unit including first to fourth signal level conversion circuits, wherein the first signal level conversion circuit temporarily converts the amplitude of a first control signal of the low-voltage control signal group to an amplitude between a first power supply voltage of a first polarity and a second power supply voltage of a second polarity, and then converts the amplitude to an amplitude between a third power supply voltage of a first polarity whose voltage difference from the reference power supply voltage is greater than the first power supply voltage, and the reference power supply voltage, and supplies the generated signal to the first output unit as a first high-voltage control signal of the first polarity; and the second signal level conversion circuit temporarily converts the amplitude of a second control signal of the low-voltage control signal group to an amplitude between the first power supply voltage of a first polarity and the second power supply voltage of a second polarity, and then converts the amplitude to an amplitude between the first power supply voltage of a first polarity and the second power supply voltage of a second polarity, and then converts the generated signal to an amplitude between the reference power supply voltage of the first polarity and the reference power supply voltage, the third signal level conversion circuit converts the amplitude of the third control signal of the low-voltage control signal group to an amplitude between the first power supply voltage of the first polarity and the second power supply voltage of the second polarity, and then converts it into an amplitude between the fourth power supply voltage of the second polarity and the reference power supply voltage, and supplies the generated signal to the first control unit as a first high-voltage control signal of the second polarity; the fourth signal level conversion circuit converts the amplitude of the fourth control signal of the low-voltage control signal group to an amplitude between the first power supply voltage of the first polarity and the second power supply voltage of the second polarity, and then converts it into an amplitude between the third power supply voltage of the first polarity and the reference power supply voltage, and supplies the generated signal to the second output unit as a second high-voltage control signal of the second polarity; and the fourth signal level conversion circuit converts the amplitude of the fourth control signal of the low-voltage control signal group to an amplitude between the first power supply voltage of the first polarity and the second power supply voltage of the second polarity, and then converts it into an amplitude between the third power supply voltage of the first polarity and the reference power supply voltage, and supplies the generated signal to the second control unit as a second high-voltage control signal of the first polarity.

[0019] Also, a display driver according to the present invention includes a data register latch that takes in a series of pixel data pieces that represent the luminance level of each pixel based on a video signal and outputs the taken-in plurality of pixel data pieces; a plurality of level shift circuits that convert the signal levels of each of the plurality of pixel data pieces output from the data register latch into a positive high voltage signal and a negative high voltage signal, respectively; a decoder unit that converts the positive high voltage signal and the negative high voltage signal for each of the pixel data pieces into a positive gray scale voltage signal and a negative gray scale voltage signal, respectively; and a decoder unit that converts the positive high voltage signal and the negative high voltage signal for each of the pixel data pieces into a positive gray scale voltage signal and a negative gray scale voltage signal for each of the output channels based on a group of low voltage control signals that control drive timing. and a drive circuit group that outputs a signal alternately selected from the voltage signals as a drive voltage signal via an output terminal, wherein the drive circuit group is supplied with a drive reference power supply voltage, a low-voltage positive power supply voltage and a high-voltage positive power supply voltage that are positive with respect to the reference power supply voltage, and a low-voltage negative power supply voltage and a high-voltage negative power supply voltage that are negative with respect to the reference power supply voltage, and includes a signal level conversion unit that converts the voltage amplitude of the low-voltage control signal group to generate a high-voltage control signal group, and further is composed of all transistors with an element breakdown voltage lower than the voltage difference between the high-voltage positive power supply voltage and the high-voltage negative power supply voltage, and each drive circuit of the drive circuit group is the drive circuit according to the present invention described above.

[0020] Furthermore, a display device according to the present invention includes the display driver according to the present invention described above, and a liquid crystal display panel that is driven in accordance with the drive voltage signals output from the output terminals of the display driver for each of the output channels. [Effects of the Invention]

[0021] In the signal level conversion circuit according to the present invention, first, a first level shift unit level-shifts the amplitude of a low-voltage input signal to the polarity opposite to that of the input signal, thereby obtaining a voltage signal that oscillates in a range from a low positive voltage to a low negative voltage. Next, the voltage signal that oscillates in a range from a low positive voltage to a low negative voltage is converted into a low positive voltage signal in a second level shift unit, and the amplitude of the low positive voltage signal is level-shifted to a high positive voltage signal in a third level shift unit. Furthermore, the voltage signal that oscillates in a range from a low positive voltage to a low negative voltage is converted into a low negative voltage signal in a fourth level shift unit, and the amplitude of the low negative voltage signal is level-shifted to a high negative voltage signal in a fifth level shift unit.

[0022] With this configuration, it is possible to make the processing time in the positive polarity signal level conversion unit consisting of the first, second, and third level shift units equal to the processing time in the negative polarity signal level conversion unit consisting of the first, fourth, and fifth level shift units.

[0023] Furthermore, in each of the first to fifth level shift sections, it becomes possible to use a switch element (transistor) with a withstand voltage lower than the output voltage range from a negative high voltage signal to a positive high voltage signal.

[0024] Therefore, the signal level conversion circuit according to the present invention can convert a low-voltage input voltage signal into a high-voltage signal of a first polarity and a high-voltage signal of a second polarity using a switch element having a withstand voltage lower than the output voltage range, and output the signals at synchronized timing. Furthermore, even when a plurality of low-voltage input voltage signals are converted into high-voltage signals of a first polarity and high-voltage signals of a second polarity by the signal level conversion circuit according to the present invention, the conversion into high-voltage signals of a first polarity and high-voltage signals of a second polarity can be performed while maintaining the timing between the plurality of low-voltage input voltage signals.

[0025] Furthermore, by employing the above-described signal level conversion circuit in a drive circuit that alternately outputs high-voltage positive drive voltage signals and negative drive voltage signals from one output terminal in response to low-voltage control signals and converting the low-voltage control signals into high-voltage positive and negative control signals for drive timing control, it is possible to realize an area-saving drive circuit composed of transistors with element voltage resistance lower than the output voltage range, and also to support high drive frequencies that require highly accurate drive timing control. [Brief explanation of the drawings]

[0026] [Figure 1] 1 is a block diagram showing an example of the configuration of a signal level conversion circuit 100 according to a first embodiment of the present invention. [Figure 2A] FIG. 1 is a block diagram showing a modification 100_H of the signal level conversion circuit 100 according to the first exemplary embodiment of the present invention. [Figure 2B] FIG. 10 is a block diagram showing another modified example 100_L of the signal level conversion circuit 100 according to the first exemplary embodiment of the present invention. [Figure 3] FIG. 10 is a circuit diagram showing a configuration of a signal level conversion circuit 100_1 according to a second embodiment of the present invention. [Figure 4] FIG. 10 is a block diagram showing a configuration of a drive circuit 200_1 according to a third embodiment of the present invention. [Figure 5] FIG. 10 is a block diagram showing a configuration of a drive circuit 200_2 according to a fourth embodiment of the present invention. [Figure 6] 10 is a time chart showing a control operation in the drive circuit 200_1 or 200_2 as a fifth embodiment of the present invention. [Figure 7] FIG. 10 is a block diagram showing the configuration of a liquid crystal display device 400 according to a sixth embodiment of the present invention, which is provided with a data driver including a signal level conversion circuit and a drive circuit according to the present invention. [Figure 8] FIG. 2 is a block diagram showing the configuration of a data driver 80. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0027] FIG. 1 is a block diagram showing an example of the configuration of a signal level conversion circuit 100 according to a first embodiment of the present invention.

[0028] The signal level conversion circuit 100 receives a voltage signal S1 of a first polarity (positive polarity) output from the logic circuit 9 based on, for example, an input voltage signal SS0, and a complementary signal XS1 obtained by inverting the phase of the voltage signal S1. Hereinafter, the voltage signals SS0, S1, and XS1 are also referred to as LV (low voltage) voltage signals SS0, S1, and XS1, since they are low-voltage signals for the logic circuit. Furthermore, the signal level conversion circuit 100 receives a plurality of power supply voltages (VDD2L, VDD1L, VGND, VDD1H, VDD2H) having the following magnitude relationship, where a reference power supply voltage VGND is used as the reference and a voltage equal to or higher than the reference power supply voltage VGND is defined as a first polarity (positive polarity), and a voltage equal to or lower than the reference power supply voltage VGND is defined as a second polarity (negative polarity).

[0029] VDD2L <VDD1L<VGND<VDD1H<VDD2H (VDD1H-VDD1L)≦VDD2H (VDD1H-VDD1L)≦|VDD2L| Hereinafter, the power supply voltages VDD1H and VDD1L will be referred to as LV power supply voltages, and the power supply voltages VDD2H and VDD2L will be referred to as HV (High voltage) power supply voltages because they are higher than the LV power supply voltages.

[0030] The signal level conversion circuit 100 receives an LV voltage signal S1 and its complementary signal XS1, and converts the LV voltage signal S1 into a voltage signal (hereinafter referred to as an HV voltage signal) of a first polarity (positive polarity) high voltage (VDD2H) and an HV voltage signal of a second polarity (negative polarity) high voltage (VDD2L). The withstand voltages (normal use withstand voltages) of the elements constituting the level conversion circuit 100 are those that satisfy the following relationship, where the low-voltage elements have a withstand voltage VDD1M and the high-voltage elements have a withstand voltage VDD2M:

[0031] VDD1M ≒ VDD1H + Δ1 VDD1M ≒ |VDD1L| + Δ1 VDD2M ≒ VDD2H + Δ2 VDD2M ≒ |VDD2L| + Δ2 Δ1, Δ2: Voltage margin As shown in FIG. 1, the signal level conversion circuit 100 includes a first level shift section 10, a second level shift section 20, a third level shift section 30, a fourth level shift section 40, and a fifth level shift section 50.

[0032] The first level shift unit 10 converts the amplitudes (VDD1H to VGND) of the LV voltage signals S1 and XS1 into voltage signals having amplitudes (VDD1L to VDD1H) level-shifted so as to expand the amplitude toward the second polarity (negative polarity) with respect to the reference power supply voltage VGND. Specifically, the first level shift unit 10 converts the LV voltage signals S1 and XS1 into a voltage signal S2H (VDD1L, VDD1H) for the first polarity (positive polarity) and an HV voltage signal S2L for the second polarity (negative polarity). The first level shift unit 10 supplies the voltage signal S2H to the second level shift unit 20 and supplies the voltage signal S2L to the third level shift unit 30.

[0033] The second level shift unit 20 converts the amplitude (VDD1L to VDD1H) of the voltage signal S2H supplied from the first level shift unit 10 into a voltage signal S3H of a first polarity (positive polarity) and its complementary signal XS3H having an amplitude (VGND to VDD1H) level-shifted based on the reference power supply voltage VGND, and supplies the voltage signals S3H and XS3H to the third level shift unit 30.

[0034] The third level shift unit 30 converts the amplitude (VGND to VDD1H) of the voltage signals S3H and XS3H into a first polarity (positive) HV voltage signal S4H and its complementary signal XS4H having an amplitude (VGND to VDD2H) level-shifted to expand toward the first polarity (positive) side based on the reference power supply voltage VGND, and outputs one or both of the HV voltage signals S4H and XS4H.

[0035] The fourth level shift unit 40 converts the amplitude (VDD1L to VDD1H) of the voltage signal S2L supplied from the first level shift unit 10 into a voltage signal S3L and its complementary signal XS3L having an amplitude (VGND to VDD1L) level-shifted based on the reference power supply voltage VGND, and supplies the voltage signals S3L and XS3L to the fifth level shift unit 50.

[0036] The fifth level shift unit 50 converts the amplitude (VGND to VDD1L) of the voltage signals S3L and XS3L into a second polarity (negative) HV voltage signal S4L and its complementary signal XS4L, which have an amplitude (VGND to VDD2L) level-shifted to expand toward the second polarity (negative) side based on the reference power supply voltage VGND, and outputs one or both of the HV voltage signals S4L and XS4L.

[0037] 1, the amplitudes of the LV voltage signals S1 and XS1, the signal levels of which are to be converted, are expanded toward the negative side by the first level shift unit 10, thereby obtaining voltage signals S2H and S2L having amplitudes ranging from negative to positive, VDD1H to VDD1L. At this time, the voltage signals S2H and S2L supplied from the first level shift unit 10 may be either in-phase signals or complementary signals, with the voltage signal S2H being output as a voltage signal for a first polarity (positive polarity) and the voltage signal S2L being output as a voltage signal for a second polarity (negative polarity).

[0038] The first polarity (positive polarity) voltage signal S2H is converted into a first polarity (positive polarity) HV voltage signal S4H (XS4H) whose amplitude is level-shifted to VGND to VDD2H by the first polarity level shifter (20, 30).Furthermore, the second polarity (negative polarity) voltage signal S2L is converted into a second polarity (negative polarity) HV voltage signal S4L (XS4L) whose amplitude is level-shifted to VGND to VDD2L by the second polarity level shifter (40, 50).

[0039] In short, the signal level conversion circuit 100 converts the level of a low-voltage input voltage signal into a high-voltage signal of a first polarity and a high-voltage signal of a second polarity using the following first to fifth level shift units. That is, the first level shift unit (10) converts the amplitude of the input voltage signal (S1, XS1) into an amplitude between a first negative power supply voltage (VDD1L) of negative polarity and a first positive power supply voltage (VDD1H) of positive polarity to generate voltage signals (S2H, S2L). The second level shift unit (20) converts the amplitude of the above-mentioned voltage signal (S2H) into an amplitude between a predetermined reference power supply voltage (VGND) and a first positive power supply voltage (VDD1H) to generate first polarity voltage signals (S3H, XS3H). The third level shift unit (30) converts the amplitude of the first polarity voltage signal (S3H, XS3H) into an amplitude between a second positive power supply voltage (VDD2H) higher than the first positive power supply voltage (VDD1H) and a reference voltage, and outputs the converted signal as a first polarity high voltage signal (S4H, XS4H). The fourth level shift unit (40) converts the amplitude of the voltage signal (S2L) into an amplitude between a reference power supply voltage (VGND) and a first negative power supply voltage (VDD1L), and generates the converted signal as a second polarity voltage signal (S3L, XS3L). The fifth level shift unit (50) converts the amplitude of the second polarity voltage signal (S3L, XS3L) into an amplitude between a second negative power supply voltage (VDD2L) lower than the first negative power supply voltage (VDD1L) and the reference power supply voltage, and outputs the converted signal as a second polarity high voltage signal (S4L, XS4L). In this way, the signal level conversion circuit 100 includes level shift sections (20, 30 and 40, 50) that first convert a low-voltage input voltage signal into voltage signals S2H, S2L having an amplitude between VDD1L and VDD1H spanning from negative to positive polarity in the first level shift section (10), and then symmetrically expand the amplitude of the voltage signals S2H, S2L toward the positive and negative polarity, respectively, relative to the reference power supply voltage VGND.

[0040] With this configuration, the signal level conversion circuit 100 can align the amplitude conversion process times (timings) of the high-voltage signals of first polarity (S4H, XS4H) and second polarity (S4L, XS4L), which are amplitude-expanded signals for the low-voltage voltage signals (S1, XS1). Furthermore, fluctuations in the amplitude conversion process times (timings) can be suppressed even when characteristics of the elements constituting the signal level conversion circuit 100 vary due to factors such as the manufacturing process and ambient temperature. It is preferable that the positive power supply voltage VDD1H and the negative power supply voltage VDD1L have approximately the same voltage difference from the reference power supply voltage VGND. It is also preferable that the positive power supply voltage VDD2H and the negative power supply voltage VDD2L have approximately the same voltage difference from the reference power supply voltage VGND.

[0041] Furthermore, each of the first to fifth level shift units 10 to 50 can be configured with transistors with a device breakdown voltage lower than the power supply voltage range (VDD2L to VDD2H) from the negative high voltage signal (S4L) to the positive high voltage signal (S4H) (for example, approximately 1 / 2 of the power supply voltage range (VDD2L to VDD2H) spanning from positive to negative).

[0042] Therefore, the signal level conversion circuit 100 shown in FIG. 1 uses transistors with a device breakdown voltage lower than the output voltage range to convert the level of the LV voltage signal S1 into an HV voltage signal S4H of a first polarity (positive polarity) and an HV voltage signal S4L of a second polarity (negative polarity), and makes it possible to output each at synchronized timing.

[0043] In FIG. 1, the first, third and fifth level shift units 10, 30 and 50 are shown as an example of a configuration in which they receive two complementary signals and perform amplitude conversion, but they may also be configured to receive only one of the two signals.

[0044] The first polarity level shift section (20, 30) or the second polarity level shift section (40, 50) shown in FIG. 1 may be provided with a function for adjusting the output timing of both.

[0045] 1, one LV voltage signal S1 (XS1) is the target of signal level conversion, but the configuration may be expanded to convert two or more LV voltage signals into HV voltage signals of a first polarity (positive polarity) and a second polarity (negative polarity), respectively. For high-voltage signal groups of a first polarity and a second polarity whose amplitudes are expanded by the signal level conversion circuit 100 for a plurality of different low-voltage voltage signals, it is also possible to align the amplitude conversion processing time (timing) between polarities and between high-voltage signal groups while suppressing the effects of variations in element characteristics such as the manufacturing process and environmental temperature.

[0046] Furthermore, if necessary, the first level shift unit 10 may include a logic circuit that generates a control signal for synchronously controlling the first polarity level shift units (20, 30) and the second polarity level shift units (40, 50). Furthermore, in order to deal with excessive variations in element characteristics, the signal level conversion circuit 100 may be equipped with a function for correcting the timing difference between the HV voltage signals S4H and S4L using a control signal from outside the signal level conversion circuit 100.

[0047] 2A and 2B show modified examples of the signal level conversion circuit 100 of FIG. 1. FIG. 2A shows a signal level conversion circuit 100_H obtained by removing the fourth and fifth level shift units 40 and 50 from FIG. 1. The signal level conversion circuit 100_H of FIG. 2A converts the level of low-voltage voltage signals S1 and XS1 into a high-voltage signal S4H (XS4H) of a first polarity (positive polarity). FIG. 2B shows a signal level conversion circuit 100_L obtained by removing the second and third level shift units 20 and 30 from FIG. 1. The signal level conversion circuit 100_L of FIG. 2B converts the level of low-voltage voltage signals S1 and XS1 into a high-voltage signal S4L (XS4L) of a second polarity (negative polarity).

[0048] The signal level conversion circuits 100_H and 100_L in Figures 2A and 2B can be used when expanding the amplitude of a low-voltage voltage signal to only one of the positive and negative polarities. When generating multiple high-voltage signal groups (e.g., timing control signal groups) for each polarity from multiple different low-voltage voltage signal groups, generating multiple high-voltage signal groups using the signal level conversion circuits 100, 100_H, and 100_L allows for the generation of high-voltage signal groups with expanded amplitude while maintaining the timing between the multiple different low-voltage voltage signal groups. The high-voltage signal groups of first and second polarities thus generated can reduce the influence of element characteristic variations and align the amplitude conversion processing time (timing) between polarities and between high-voltage signal groups. [Example]

[0049] FIG. 3 is a circuit diagram showing a configuration of a signal level conversion circuit 100_1 according to a second embodiment of the present invention.

[0050] Fig. 3 shows specific circuit examples of each of the first level shift unit 10, the second level shift unit 20, the third level shift unit 30, the fourth level shift unit 40, and the fifth level shift unit 50 of the signal level conversion circuit 100 shown in Fig. 1. For convenience, Fig. 3 shows a configuration in which HV voltage signals (S4H, XS4H) of a first polarity (positive polarity) and HV voltage signals (S4L, XS4L) of a second polarity (negative polarity) are generated for one LV voltage signal SS0.

[0051] 2, the logic circuit 9 includes an inverter I1 that inverts the logical level of the LV voltage signal SS0 and outputs the inverted signal as the LV voltage signal S1. The first level shift unit 10 of the signal level conversion circuit 100_1 receives the LV voltage signal S1 and its complementary signal XS1 (=SS0) output from the inverter I1. Note that, for convenience, the logic circuit 9 in FIG. 3 is configured with only the inverter I1, but may have any configuration that outputs the LV voltage signals S1 and XS1.

[0052] The first level shift unit 10 includes PMOS transistors Q1 and Q2 receiving a power supply voltage VDD1H of a first polarity (positive polarity) at their respective sources, and NMOS transistors Q3 and Q4 receiving a power supply voltage VDD1L of a negative polarity at their respective sources.

[0053] The drain of the PMOS transistor Q1 is connected to the drain of the NMOS transistor Q3 and the gate of the NMOS transistor Q4. The gate of the PMOS transistor Q1 is supplied with an LV voltage signal S1 output from the logic circuit 9. The drain of the PMOS transistor Q2 is connected to the drain of the NMOS transistor Q4 and the gate of the NMOS transistor Q3. The gate of the PMOS transistor Q2 is supplied with an LV voltage signal XS1.

[0054] With this configuration, the first level shift unit 10 outputs the signal generated at the connection point between the drain of the PMOS transistor Q2 and the drain of the NMOS transistor Q4 as the negative voltage signal S2L. The first level shift unit 10 also outputs the signal generated at the connection point between the drain of the PMOS transistor Q1 and the drain of the NMOS transistor Q3, i.e., a complementary signal with the phase of the voltage signal S2L inverted, as the voltage signal S2H. The voltage signals S2L and S2H do not have to be complementary to each other. For example, either the signal generated at the connection point between the drain of the PMOS transistor Q2 and the drain of the NMOS transistor Q4 or the signal generated at the connection point between the drain of the PMOS transistor Q1 and the drain of the NMOS transistor Q3 may be output as the common voltage signals S2L and S2H.

[0055] The second level shift unit 20 includes inverters I2 and I3 connected in series, which receive a power supply voltage VDD1H of a first polarity (positive polarity) and a reference power supply voltage VGND.

[0056] The inverter I2 receives the voltage signal S2H, and when the voltage signal S2H represents the power supply voltage VDD1H of the first polarity (positive polarity), it outputs a signal representing the reference power supply voltage VGND. On the other hand, when the voltage signal S2H represents the power supply voltage VDD1L of the second polarity (negative polarity), the inverter I2 outputs a signal representing the power supply voltage VDD1H of the first polarity (positive polarity). The inverter I2 supplies the signal output as described above to the inverter I3 and the fourth level shift unit 40 as a voltage signal S3H. The inverter I3 supplies a complementary signal obtained by inverting the phase of the voltage signal S3H to the fourth level shift unit 40 as a voltage signal XS3H.

[0057] The fourth level shift unit 40 includes inverters I4 and I5 connected in series, which receive the reference power supply voltage VGND and the power supply voltage VDD1L of the second polarity (negative polarity).

[0058] The inverter I4 receives the voltage signal S2L, and when the voltage signal S2L represents the power supply voltage VDD1H of the first polarity (positive polarity), it outputs a signal representing the power supply voltage VDD1L of the second polarity (negative polarity). Furthermore, when the voltage signal S2L represents the power supply voltage VDD1L of the second polarity (negative polarity), the inverter I4 outputs a signal representing the reference power supply voltage VGND. The inverter I4 supplies the signal output as described above to the inverter I5 and the fifth level shift unit 50 as the voltage signal XS3L. The inverter I5 supplies a complementary signal obtained by inverting the phase of the voltage signal X3SL to the fifth level shift unit 50 as the voltage signal S3L.

[0059] The third level shift unit 30 includes PMOS transistors Q5 and Q6 receiving a power supply voltage VDD2H of a first polarity (positive polarity) at their respective sources, and NMOS transistors Q7 and Q8 receiving a reference power supply voltage VGND at their respective sources.

[0060] The drain of the PMOS transistor Q5 is connected to the gate of the PMOS transistor Q6 and the drain of the NMOS transistor Q7. The drain of the PMOS transistor Q6 is connected to the gate of the PMOS transistor Q5 and the drain of the NMOS transistor Q8. The gate of the NMOS transistor Q7 is supplied with a voltage signal XS3H output from the second level shift section 20. The gate of the NMOS transistor Q8 is supplied with a voltage signal S3H output from the second level shift section 20.

[0061] With this configuration, the third level shift unit 30 outputs a signal generated at the connection point between the drain of the PMOS transistor Q6 and the drain of the NMOS transistor Q8 as an HV voltage signal S4H of the first polarity (positive polarity).Furthermore, the third level shift unit 30 outputs a signal generated at the connection point between the drain of the PMOS transistor Q5 and the drain of the NMOS transistor Q7 as an HV voltage signal XS4H of the first polarity (positive polarity) that is the inverted phase of the HV voltage signal S4H.

[0062] The fifth level shift unit 50 includes PMOS transistors Q9 and Q10, each receiving a reference power supply voltage VGND at its source, and NMOS transistors Q11 and Q12, each receiving a power supply voltage VDD2L of the second polarity (negative polarity) at its source.

[0063] The drain of the PMOS transistor Q9 is connected to the gate of the NMOS transistor Q12 and the drain of the NMOS transistor Q11. The drain of the PMOS transistor Q10 is connected to the gate of the NMOS transistor Q11 and the drain of the NMOS transistor Q12. The gate of the NMOS transistor Q9 is supplied with a voltage signal S3L output from the fourth level shift section 40. The gate of the NMOS transistor Q10 is supplied with a voltage signal XS3L output from the fourth level shift section 40.

[0064] With this configuration, the fifth level shift unit 50 outputs a signal generated at the connection point between the drain of the PMOS transistor Q10 and the drain of the NMOS transistor Q12 as an HV voltage signal S4L of the second polarity (negative polarity).Furthermore, the fifth level shift unit 50 outputs a signal generated at the connection point between the drain of the PMOS transistor Q9 and the drain of the NMOS transistor Q11 as an HV voltage signal XS4L of the second polarity (negative polarity) that is the inverted phase of the HV voltage signal S4L.

[0065] This configuration can suppress timing discrepancies between HV voltage signals of different polarities due to variations in the characteristics of the NMOS and PMOS transistors that make up each level shift unit, fluctuations in temperature conditions, etc. Therefore, it is possible to convert the LV voltage signals S1 and XS1 into HV voltage signals (S4H and XS4H) of a first polarity (positive polarity) and HV voltage signals (S4L and XS4L) of a second polarity (negative polarity), and output them at synchronized timing.

[0066] In the signal level conversion circuit 100_1 shown in FIG. 2, the first level shift section 10, the third level shift section 30, and the fifth level shift section 50, which serve as level shift sections that expand the voltage amplitude of the input LV voltage signal (S1, XS1), are each configured with four MOS transistor elements, but other configurations may also be adopted. Furthermore, the second level shift unit 20 and the fourth level shift unit 40 are preferably configured symmetrically with respect to the reference power supply voltage VGND, and the third level shift unit 30 and the fifth level shift unit 50 are also preferably configured symmetrically with respect to the reference power supply voltage VGND. Specifically, as in the configuration example of Fig. 3, the fourth level shift unit 40 is preferably configured by replacing the power supply voltage VDD1H of a first polarity (positive polarity) supplied to the second level shift unit 20 with a power supply voltage VDD1L of a second polarity (negative polarity) and by swapping the conductivity types of the transistors constituting the second level shift unit 20. Similarly, the fifth level shift unit 50 is preferably configured by replacing the power supply voltage VDD2H of a first polarity (positive polarity) supplied to the third level shift unit 30 with a power supply voltage VDD2L of a second polarity (negative polarity) and by swapping the conductivity types of the transistors constituting the fourth level shift unit 40. This configuration can suppress timing discrepancies between HV voltage signals of different polarities when converting voltage amplitudes, making it easy to convert the LV voltage signals S1 and XS1 into HV voltage signals (S4H and XS4H) of a first polarity (positive polarity) and HV voltage signals (S4L and XS4L) of a second polarity (negative polarity), and output them at synchronized timing. [Example]

[0067] FIG. 4 is a block diagram showing a configuration of a drive circuit 200_1 according to a third embodiment of the present invention.

[0068] The drive circuit 200_1 receives a positive high-voltage input signal VP having a positive high-voltage value (VGND to VDD2H) and a negative high-voltage input signal VN having a negative high-voltage value (VDD2L to VGND) as high-voltage input signals for driving a load. The drive circuit 200_1 generates SA1, SB1, SC1, SD1 and their complementary signals XSA1, XSB1, XSC1, XSD1 of LV voltage signals (VGND to VDD1H) required for drive control of the drive circuit 200_1 in a logic circuit 9 to which a polarity switching signal POL indicating polarity switching timing and a plurality of low-voltage control signals SS for controlling output timing are supplied. The drive circuit 200_1 alternately switches between high-voltage positive and negative drive voltage signals VPA and VNA obtained by amplifying the positive high-voltage input signal VP and the negative high-voltage input signal VN, respectively, at timings according to the LV voltage signals, and outputs them from an output terminal DL1. The drive circuit 200_1 is also configured with transistors having a lower breakdown voltage than the output voltage range (VDD2L to VDD2H) of the positive and negative drive voltage signals VPA and VNA output to the output terminal DL1.

[0069] As shown in FIG. 4, the drive circuit 200_1 includes a PMOS output switch 11, an NMOS output switch 21, a signal level conversion unit 100_2, a positive signal output unit 111, a negative signal output unit 121, a positive output SW control unit 112, and a negative output SW control unit 122.

[0070] 1 (FIG. 3), 2A, and 2B are provided in a plurality of systems (100A, 100B, 100C, and 100D in FIG. 4) according to the type of control signal. The signal level conversion unit 100_2 is supplied with a reference power supply voltage VGND, a positive power supply voltage VDD1H, a negative power supply voltage VDD1L, a positive power supply voltage VDD2H whose voltage difference with respect to the reference power supply voltage VGND is larger than the power supply voltage VDD1H, and a negative power supply voltage VDD2L whose voltage difference with respect to the reference power supply voltage VGND is also larger than the power supply voltage VDD1L.

[0071] The signal level conversion circuit 100A level-shifts the amplitudes of the LV voltage signals SA1 and XSA1 for timing control as described above. That is, the signal level conversion circuit 100A first converts the amplitudes of the LV voltage signals SA1 and XSA1 to an amplitude between a positive power supply voltage VDD1H and a negative power supply voltage VDD1L, and then converts the amplitudes to an amplitude between a positive power supply voltage VDD2H and a reference power supply voltage VGND, generating signals that are supplied as positive HV voltage signals SA4H and XSA4H to the positive signal output unit 111. The signal level conversion circuit 100B first converts the amplitudes of the LV voltage signals SB1 and XSB1 for timing control to an amplitude between a positive power supply voltage VDD1H and a negative power supply voltage VDD1L, and then converts the amplitudes to an amplitude between a negative power supply voltage VDD2L and a reference power supply voltage VGND, generating signals that are supplied as negative HV voltage signals SB4L and XSB4L to the positive output SW control unit 112. The signal level conversion circuit 100C also converts the amplitudes of the LV voltage signals SC1 and XSC1 for timing control into amplitudes between a positive power supply voltage VDD1H and a negative power supply voltage VDD1L, and then converts them into amplitudes between a negative power supply voltage VDD2L and a reference power supply voltage VGND, generating signals that are supplied as negative HV voltage signals SC4L and XSC4L to the negative signal output unit 121. The signal level conversion circuit 100D also converts the amplitudes of the LV voltage signals SD1 and XSD1 for timing control into amplitudes between a positive power supply voltage VDD1H and a negative power supply voltage VDD1L, and then converts them into amplitudes between a positive power supply voltage VDD2H and a reference power supply voltage VGND, generating signals that are supplied to the negative output SW control unit 122.

[0072] In the signal level conversion unit 100_2 of FIG. 4, each of the signal level conversion circuits 100A to 100D is a signal level conversion circuit that converts an LV voltage signal into a positive or negative HV voltage signal. For example, the signal level conversion circuits 100A and 100D can adopt the configuration 100_H of FIG. 2A, and the signal level conversion circuits 100B and 100C can adopt the configuration 100_L of FIG. 2B.

[0073] The positive signal output unit 111 receives a first polarity (positive polarity) HV power supply voltage VDD2H and a reference power supply voltage VGND, and operates within a positive polarity HV voltage range (VGND to VDD2H). The positive signal output unit 111 amplifies a positive polarity high voltage input signal VP in accordance with the control timing of one or both of the first polarity (positive polarity) HV voltage signals SA4H and XSA4H, and supplies the amplified positive polarity drive voltage signal VPA to the source of the PMOS output switch 11 serving as a PMOS transistor via a node Ns11.

[0074] The positive output SW control unit 112 receives a second polarity (negative polarity) HV power supply voltage VDD2L and a reference power supply voltage VGND, and operates within a negative polarity HV voltage range (VDD2L to VGND). The positive output SW control unit 112 generates a negative polarity high voltage output control signal GP of at least two values ​​(for example, VGND and VDD1L) that can control the on / off of the PMOS output switch 11 with respect to the positive polarity drive voltage signal VPA within a predetermined element withstand voltage, in accordance with the control timing of one or both of the second polarity (negative polarity) HV voltage signals SB4L and XSB4L, and supplies this to the gate of the PMOS output switch 11.

[0075] The PMOS output switch 11 is a PMOS transistor, and its drain is connected to the output terminal DL1. The PMOS output switch 11 is set to an on or off state in response to a positive drive voltage signal VPA supplied to its source and a negative high voltage output control signal GP received at its gate. When the PMOS output switch 11 is in the on state, it outputs the positive drive voltage signal VPA supplied from the positive signal output unit 111 to the output terminal DL1. The drain, gate, and source (and back gate) of the PMOS output switch 11 are controlled to have a voltage difference that is equal to or less than the breakdown voltage of the element.

[0076] The negative signal output unit 121 receives a second polarity (negative polarity) HV power supply voltage VDD2L and a reference power supply voltage VGND, and operates within a negative polarity HV voltage range (VDD2L to VGND). The negative signal output unit 121 amplifies the negative polarity high voltage input signal VN and supplies the amplified negative polarity drive voltage signal VNA to the source of the NMOS output switch 21 via node Ns21 in accordance with the control timing of one or both of the second polarity (negative polarity) HV voltage signals SC4L and XSC4L.

[0077] The negative output SW control unit 122 receives a first polarity (positive polarity) HV power supply voltage VDD2H and a reference power supply voltage VGND, and operates within a positive polarity HV voltage range (VGND to VDD2H). The negative output SW control unit 122 generates a positive polarity high voltage output control signal GN of at least two values ​​(for example, VGND and VDD1H) that can control the on / off of the NMOS output switch 21 within a predetermined element breakdown voltage with respect to the negative polarity drive voltage signal VPA, in accordance with the control timing of one or both of the first polarity (positive polarity) HV voltage signals SD4H and XSD4H, and supplies this to the gate of the NMOS output switch 21.

[0078] The NMOS output switch 21 is an NMOS transistor, and its drain is connected to the output terminal DL1. The NMOS output switch 21 is set to an on or off state in response to a negative drive voltage signal VNA supplied to its source and a positive high voltage output control signal GN received at its gate. When the NMOS output switch 21 is in the on state, it outputs the negative drive voltage signal VNA supplied from the negative signal output unit 121 to the output terminal DL1. The drain, gate, and source (and back gate) of the NMOS output switch 21 are controlled to have a voltage difference that is equal to or less than the breakdown voltage of the element.

[0079] With this configuration, in the drive circuit 200_1, polarity switching of the drive voltage signal to the output terminal DL1 by the positive signal output unit 111, the negative signal output unit 121, the positive output SW control unit 112, and the negative output SW control unit 122 is controlled by the HV voltage signal group (SA1, SB1, SC1, SD1 and their complementary signals XSA1, XSB1, XSC1, XSD1) from the signal level conversion circuit 100_2. Here, the signal level conversion circuit 100_2 can output the HV voltage signal group (SA4H, SB4H and their complementary signals) responsible for output control on the positive side, the HV voltage signal group (SC4H, SD4H and their complementary signals) responsible for output control on the negative side, and the HV voltage signal groups between the positive and negative poles at synchronized timings.

[0080] Therefore, according to the drive circuit 200_1, in a drive circuit including the signal level conversion circuit 100_2 configured using transistors with element breakdown voltages lower than the output voltage range, it is possible to suppress drive timing deviations within the same polarity and between polarities, and to output the negative drive voltage signal VNA and the positive drive voltage signal VPA alternately to the capacitive load connected to the output terminal DL1 through highly accurate drive timing control, thereby suppressing the generation of through current and signal noise due to drive timing deviations and enabling support for high drive frequencies.

[0081] The following describes in detail the operations of the positive output SW control section 112 that controls the on / off of the PMOS output switch 11 and the negative output SW control section 122 that controls the on / off of the NMOS output switch 21.

[0082] When the PMOS output switch 11 outputs a positive drive voltage signal VPA having a voltage value relatively close to the power supply voltage VDD2H to the output terminal DL1, the positive output SW control unit 112 supplies a negative high-voltage output control signal GP having a reference power supply voltage VGND to the gate of the PMOS output switch 11. On the other hand, when the PMOS output switch 11 outputs a positive drive voltage signal VPA having a voltage value relatively close to the reference power supply voltage VGND to the output terminal DL1, the positive output SW control unit 112 supplies a negative high-voltage output control signal GP having an intermediate voltage between the reference power supply voltage VGND and the negative HV power supply voltage VDD2L to the gate of the PMOS output switch 11. That is, the positive output SW control unit 112 switches the voltage value of the negative high-voltage output control signal GP using at least two voltage values ​​according to the voltage value of the positive drive voltage signal VPA output to the output terminal DL1 in order to control the gate voltage to a value that allows the PMOS output switch 11 to be turned on within a device withstand voltage lower than the output voltage range (VDD2L to VDD2H). Similarly, the negative output SW control unit 122 switches the voltage value of the positive high voltage output control signal GN using at least two voltage values ​​according to the voltage value of the negative drive voltage signal VNA output to the output terminal DL1, in order to control the gate voltage at which the NMOS output switch 21 can be turned on within an element breakdown voltage lower than the output voltage range.

[0083] The configuration of the driving circuit 200_1 is not limited to that shown in FIG.

[0084] In short, the driving circuit 200_1 may have the following first and second output sections, a first conductivity type transistor switch, a second conductivity type transistor switch, first and second control sections, and a signal level conversion section including first to fourth signal level conversion circuits.

[0085] That is, the first output unit (111) receives a high-voltage input signal (VP) of a first polarity (positive polarity) and outputs a drive voltage signal (VPA) of a first polarity obtained by amplifying the high-voltage input signal of the first polarity to a first node (Ns11) in response to first high-voltage control signals (SA4H, XSA4H) of the first polarity. The first conductivity type transistor switch (11) supplies the voltage of the first node to the output terminal (DL1) in an on state, while disconnecting the first node from the output terminal (DL1) in an off state. The first control unit (112) supplies a high-voltage output control signal (GP) of a second polarity to the control end (gate) of the first conductivity type transistor switch in response to first high-voltage control signals (SB4L, XSB4L) of a second polarity, which controls the on / off of the first conductivity type transistor switch. The second output section (121) receives a high-voltage input signal (VN) of a second polarity and outputs a drive voltage signal (VNA) of a second polarity obtained by amplifying the high-voltage input signal of the second polarity to a second node (Ns21) in response to second high-voltage control signals (SC4L, XSC4L) of the second polarity. The second conductivity type transistor switch (21) supplies the voltage of the second node to the output terminal (DL1) when in an on state, while disconnecting the second node from the output terminal when in an off state. The second control section (122) supplies a high-voltage output control signal (GN) of a first polarity to the control end (gate) of the second conductivity type transistor switch (21) in response to second high-voltage control signals (SD4H, XSD4H) of the first polarity, which controls the on / off of the second conductivity type transistor switch (21).

[0086] The first signal level conversion circuit (100A) first converts the amplitude of the first control signal (SA1, XSA1) of the low-voltage control signal group (SA1, SB1, SC1, SD1 and their complementary signals) into an amplitude between a first power supply voltage (VDD1H) of a first polarity (positive polarity) and a second power supply voltage (VDD1L) of a second polarity (negative polarity), and then converts the amplitude into an amplitude between a third power supply voltage (VDD2H) of a first polarity whose voltage difference from a reference power supply voltage (VGND) is greater than that of the first power supply voltage, and the reference power supply voltage, and supplies the generated signal to the first output section (111) as a first high-voltage control signal (SA4H, XSA4H) of a first polarity. The second signal level conversion circuit (100B) converts the amplitude of the second control signal (SB1, XSB1) of the low-voltage control signal group to an amplitude between a first power supply voltage of a first polarity and a second power supply voltage of a second polarity, and then converts it to an amplitude between a fourth power supply voltage (VDD2L) of a second polarity whose voltage difference from the reference power supply voltage is larger than the second power supply voltage, and the reference power supply voltage, and supplies the generated signal to the first control unit (112) as a first high-voltage control signal (SB4L, XSB4L) of a second polarity. The third signal level conversion circuit (100C) converts the amplitude of the third control signal (SC1, XSC1) of the low-voltage control signal group to an amplitude between a first power supply voltage of a first polarity and a second power supply voltage of a second polarity, and then converts it to an amplitude between a fourth power supply voltage of a second polarity and the reference power supply voltage, and supplies the generated signal to the second output unit (121) as a second high-voltage control signal (SC4L, XSC4L). The fourth signal level conversion circuit (100D) first converts the amplitude of the fourth control signal (SD1, XSD1) of the low-voltage control signal group to an amplitude between a first power supply voltage of a first polarity and a second power supply voltage of a second polarity, and then converts it to an amplitude between a third power supply voltage of the first polarity and a reference power supply voltage, and supplies the generated signal to the second control unit as a second high-voltage control signal (SD4H, XSD4H) of a first polarity. [Example]

[0087] FIG. 5 is a block diagram showing the configuration of a drive circuit 200_2 according to a fourth embodiment of the present invention. The drive circuit 200_2 shown in FIG. 5 illustrates an example of the internal circuit configuration of the positive signal output unit 111, negative signal output unit 121, positive output SW control unit 112, and negative output SW control unit 122 of the drive circuit 200_1 shown in FIG. 4. Also, in FIG. 5, the LV voltage signals SB1 and SD1 of FIG. 4 are replaced by a common LV voltage signal SE1. The signal level conversion unit 100_3 of FIG. 5 includes a signal level conversion circuit 100E, instead of the signal level conversion circuits 100B and 100D of FIG. 4, that receives the LV voltage signals SE1 and XSE1 and converts them into positive HV voltage signals SE4H and XSE4H and negative HV voltage signals SE4L and XSE4L. The signal level conversion circuit 100E may have the configuration shown in FIG. 1, for example. The signal level conversion circuits 100A and 100C, the PMOS output switch 11, and the NMOS output switch 21 are the same as those in FIG.

[0088] As shown in FIG. 5, the positive signal output unit 111 includes an amplifier 131 and switches 132 and 133. The amplifier 131 is a voltage-follower operational amplifier connected to its inverting input terminal and output node. The amplifier 131 amplifies a positive high-voltage input signal VP received at its non-inverting input terminal and outputs a positive drive voltage signal VPA from its output node. The switch 132 is, for example, a CMOS switch, and is set to an ON or OFF state in response to the HV voltage signals SA4H and XSA4H supplied from the signal level conversion circuit 100A of the signal level conversion unit 100_3. When set to an ON state, the switch 132 connects the output node of the amplifier 131 to the source of the PMOS output switch 11 via a node Ns11. When set to an OFF state, the switch 132 disconnects the connection between the output node of the amplifier 131 and the source of the PMOS output switch 11. The switch 133 is configured by, for example, an NMOS switch, and is set to an ON or OFF state in response to the HV voltage signal XSA4H supplied from the signal level conversion circuit 100 A. When set to an ON state, the switch 133 applies the reference power supply voltage VGND to the source of the PMOS output switch 11. The positive output SW control unit 112 includes a changeover switch (hereinafter referred to as changeover switch 112) that generates a negative high-voltage output control signal GP by switching between a reference power supply voltage VGND or a negative control voltage VGp. The changeover switch 112 has, for example, an inverter configuration, and switches between the reference power supply voltage VGND or the negative control voltage VGn in accordance with the HV voltage signal SE4L (XSE4L) supplied from the signal level conversion circuit 100E of the signal level conversion unit 100_3, and supplies the negative high-voltage output control signal GP generated by the switching to the gate of the PMOS output switch 11. Note that the negative control voltage VGn may be a control voltage that is supplied in accordance with the positive drive voltage signal VPA and has a plurality of voltage values ​​including VGND that can be turned on and off by the PMOS output switch 11 within a predetermined element breakdown voltage.

[0089] The negative signal output unit 121 shown in FIG. 5 includes an amplifier 141 and switches 142 and 143. The amplifier 141 is a voltage-follower operational amplifier connected to its inverting input terminal and output node. The amplifier 141 amplifies a negative high-voltage input signal VN received at its non-inverting input terminal and outputs a negative drive voltage signal VNA from its output node. The switch 142 is set to an on or off state in response to HV voltage signals SC4L and XSC4L supplied from the signal level conversion circuit 100C of the signal level conversion unit 100_3. The switch 142 is, for example, a CMOS switch. When set to an on state, the switch 142 connects the output node of the amplifier 141 to the source of the NMOS output switch 21 via node Ns21. When set to an off state, the switch 142 disconnects the connection between the output node of the amplifier 141 and the source of the NMOS output switch 21. The switch 143 is configured by, for example, a PMOS switch, and is set to an ON or OFF state in response to the HV voltage signal XS4L supplied from the signal level conversion circuit 100 C. When the switch 143 is set to an ON state, the switch 143 applies the reference power supply voltage VGND to the source of the NMOS output switch 21.

[0090] The negative output SW control unit 122 includes a changeover switch (hereinafter referred to as changeover switch 122) that generates a positive high-voltage output control signal GN by switching between a reference power supply voltage VGND or a positive control voltage VGp. The changeover switch 122 has, for example, an inverter configuration, and switches between the reference power supply voltage VGND or the positive control voltage VGp in response to the HV voltage signal SE4H (XSE4H) supplied from the signal level conversion circuit 100E of the signal level conversion unit 100_3, and supplies the positive high-voltage output control signal GN generated by the switching to the gate of the NMOS output switch 21. Note that the positive control voltage VGp may be a control voltage that is supplied in response to the negative drive voltage signal VNA and has a plurality of voltage values ​​including VGND that can be turned on and off by the NMOS output switch 21 within a predetermined device breakdown voltage.

[0091] 5, the switch 132 may be provided inside the amplifier 131. In addition, in the negative signal output section 112, the switch 142 may be provided inside the amplifier 141. [Example]

[0092] FIG. 6 is a time chart showing a control operation in the drive circuit 200_1 or 200_2 as the fifth embodiment according to the present invention.

[0093] 6 shows an example of each signal (SA4H, XSA4H, SC4L, XSC4L, SE4H, SE4L, GP, GN) generated by the signal level conversion unit 100_3, the positive output SW control unit 112, and the negative output SW control unit 122 when the drive circuit 200_2 shown in FIG. 5 alternately outputs the positive drive voltage signal VPA and the negative drive voltage signal VNA in a predetermined positive drive period and a predetermined negative drive period (polarity inversion drive). Note that the control signal for the CMOS switch indicates only the control signal supplied to the gate of the NMOS switch.

[0094] 6 shows changes in the voltage V11 at the node Ns11 to which the source of the PMOS output switch 11 shown in FIG. 5 is connected, the voltage V21 at the node Ns21 to which the source of the NMOS output switch 21 is connected, and the voltage at the output terminal DL1. The positive drive voltage signal VPA and the negative drive voltage signal VNA may be step signals having single or multiple voltage levels within voltage ranges corresponding to their respective polarities, or analog signals such as sine waves.

[0095] As shown in Fig. 6, the drive period is divided into at least four periods T1 to T4, and switching periods T1 and T3 are provided between the positive drive period T2 and the negative drive period T4. Fig. 6 shows a time chart starting from the switching period (T1) after the previous negative drive period (not shown).

[0096] 6, first, during switching period T1, switches 132 and 142 are both turned off in response to HV voltage signals SA4H and SC4L, cutting off the supply of drive voltage signals from the positive signal output unit 111 and the negative signal output unit 121. Switch 133 is turned on in response to HV voltage signal XSA4H having power supply voltage VDD2H, causing voltage V11 at node Ns11 to be at reference power supply voltage VGND. Switch 143 is supplied with HV voltage signal SC4L having a second polarity (negative) power supply voltage VDD2L, so switch 143 is turned on. As shown in FIG. 6, voltage V21 at node Ns21 is raised from the negative drive voltage signal VNA of the previous negative drive period to reference power supply voltage VGND. Switch 112 also sets the negative high-voltage output control signal GP to reference power supply voltage VGND in response to HV voltage signal SE4L having power supply voltage VDD2L. As a result, a negative high-voltage output control signal GP having the reference power supply voltage VGND is supplied to the gate of the PMOS output switch 11, and the PMOS output switch 11 is turned off. Also, the changeover switch 122 sets the positive high-voltage output control signal GN to a positive control voltage VGp in response to the HV voltage signal SE4H having the reference power supply voltage VGND. As a result, a positive high-voltage output control signal GN having the control voltage VGp is ​​supplied to the gate of the NMOS output switch 21, and the NMOS output switch 21 is turned on.

[0097] Therefore, during the period T1, the reference power supply voltage VGND as the voltage V21 of the node Ns21 is applied to the output terminal DL1 via the NMOS output switch 21.

[0098] At this time, as shown in FIG. 6, the voltage of the output terminal DL1, which was in the state of the negative drive voltage signal VNA, is pulled up to the reference power supply voltage VGND via the NMOS output switch 21.

[0099] Throughout period T1, the terminals of the switch 133 and the changeover switch 122 are controlled between the reference power supply voltage VGND and a first polarity (positive polarity) power supply voltage VDD2H. The terminals of the PMOS output switch 11, the switch 143, and the changeover switch 112 are controlled between the reference power supply voltage VGND and a second polarity (negative polarity) power supply voltage VDD2L. The drain and source of the NMOS output switch 21 are controlled between the reference power supply voltage VGND and a second polarity (negative polarity) power supply voltage VDD2L. A control voltage VGp within a predetermined voltage difference (withstand voltage) is supplied to the gate of the NMOS output switch 21, which turns the NMOS output switch 21 on with respect to the drain and source in the state of the negative polarity drive voltage signal VNA, and the voltage difference between the terminals of the NMOS output switch 21 is reduced by the reference power supply voltage VGND supplied to node Ns21. Therefore, the PMOS output switch 11, NMOS output switch 21, switch 133, switch 143, changeover switch 112 and changeover switch 122 are controlled within a predetermined element withstand voltage range lower than the output voltage range (VDD2L to VDD2H) of the output terminal DL1.

[0100] Next, during period T2, the switch 133 is supplied with the HV voltage signal XSA4H having the reference power supply voltage VGND, turning the switch 133 off. The switch 143 is continuously supplied with the HV voltage signal SC4L having the power supply voltage VDD2L, turning the switch 143 on, and the voltage V21 at the node Ns21 becomes the reference power supply voltage VGND. Of the switches 132 and 142, only the switch 132 is turned on in response to the HV voltage signals SA4H and SC4L. This causes the positive drive voltage signal VPA generated by the positive signal output unit 111 to be supplied to the node Ns11. The selector switch 112 switches the negative high-voltage output control signal GP to the negative control voltage VGn in response to the HV voltage signal SE4L having the reference power supply voltage VGND. As a result, the PMOS output switch 11 is turned on. Furthermore, the changeover switch 122 switches the positive high voltage output control signal GN to the reference power supply voltage VGND in response to the HV voltage signal SE4H having the power supply voltage VDD2H, thereby switching the NMOS output switch 21 to the OFF state.

[0101] Therefore, during the period T2, the positive drive voltage signal VPA output from the positive signal output section 111 is output to the output terminal DL1 via the node Ns11 and the PMOS output switch 11.

[0102] At this time, the NMOS output switch 21 is in the OFF state, and the electrical connection with the output terminal DL1 is cut off. Therefore, as shown in Figure 6, the voltage V11 at the node Ns11 and the voltage at the output terminal DL1 are raised from the reference power supply voltage VGND to the positive drive voltage signal VPA. Meanwhile, the voltage V21 at the node Ns21 remains at the reference power supply voltage VGND, as shown in Figure 6.

[0103] During the period T2, the terminals of the switch 133, the changeover switch 122, and the NMOS output switch 21 are controlled between the reference power supply voltage VGND and a first (positive) power supply voltage VDD2H. The terminals of the switch 143 and the changeover switch 112 are controlled between the reference power supply voltage VGND and a second (negative) power supply voltage VDD2L. The drain and source of the PMOS output switch 11 are controlled by a positive drive voltage signal VPA between the reference power supply voltage VGND and the power supply voltage VDD2H. A negative control voltage VGn within a predetermined voltage difference (withstand voltage) relative to the positive drive voltage signal VPA is applied to the gate of the PMOS output switch 11, so that the PMOS output switch 11 is turned on. Therefore, the PMOS output switch 11, the NMOS output switch 21, the switch 133, the switch 143, the changeover switch 112, and the changeover switch 122 are controlled within a predetermined element withstand voltage range lower than the output voltage range (VDD2L to VDD2H) of the output terminal DL1.

[0104] Next, during period T3, switches 132 and 142 are both turned off in response to HV voltage signals S4H and S4L, cutting off the supply of drive voltage signals from the positive signal output unit 111 and the negative signal output unit 121. Since switch 133 is supplied with HV voltage signal XS4H having power supply voltage VDD2H, switch 133 is turned on, and voltage V11 at node Ns11 is pulled down from positive drive voltage signal VPA to reference power supply voltage VGND, as shown in FIG. 6. Since switch 143 continues to be supplied with HV voltage signal XS4L having power supply voltage VDD2L, it remains on, and voltage V21 at node Ns21 remains at reference power supply voltage VGND. Since the gate of PMOS output switch 11 continues to be supplied with negative high-voltage output control signal GP having control voltage VGn, PMOS output switch 11 remains on, as shown in FIG. 6. Furthermore, in response to HV voltage signal SE4H, the positive high-voltage output control signal GN is maintained at reference power supply voltage VGND. As a result, the NMOS output switch 21 remains in the off state as shown in FIG.

[0105] Therefore, during the period T3, the reference power supply voltage VGND as the voltage V11 of the node Ns11 is output to the output terminal DL1 via the PMOS output switch 11 as shown in FIG.

[0106] At this time, as shown in FIG. 6, the voltage of the output terminal DL1, which was the positive drive voltage signal VPA, is pulled down to the reference power supply voltage VGND via the PMOS output switch 11.

[0107] Although the switch 133 changes from an OFF state to an ON state throughout the period T3, the control voltage range of each switch remains unchanged. Therefore, similar to the period T2, the PMOS output switch 11, the NMOS output switch 21, the switch 133, the switch 143, the changeover switch 112, and the changeover switch 122 are controlled within a predetermined element withstand voltage range that is lower than the output voltage range (VDD2L to VDD2H) of the output terminal DL1.

[0108] Next, during period T4, the switch 133 continues to receive the HV voltage signal XSA4H having the first polarity (positive polarity) power supply voltage VDD2H, so the switch 133 is turned on, and the voltage V11 at node Ns11 remains at the reference power supply voltage VGND. The switch 143 receives the HV voltage signal SC4L having the reference power supply voltage VGND, so the switch 143 is turned off. In response to the HV voltage signals SA4H and SC4L, only the switch 142 of the switches 132 and 142 is switched on. As a result, the negative drive voltage signal VNA output from the negative signal output unit 121 is supplied to node Ns21. In response to the HV voltage signal SE4L having the power supply voltage VDD2L, the selector switch 112 switches the negative high-voltage output control signal GP to the reference power supply voltage VGND. As a result, the PMOS output switch 11 is turned off. Furthermore, the changeover switch 122 switches the positive high voltage output control signal GN to the positive control voltage VGp in response to the HV voltage signal SE4H having the reference power supply voltage VGND, thereby switching the NMOS output switch 21 to the ON state.

[0109] Therefore, during the period T4, the negative drive voltage signal VNA output from the negative signal output section 121 is output to the output terminal DL1 via the node Ns21 and the NMOS output switch 21.

[0110] At this time, as shown in Fig. 6, the PMOS output switch 11 is in the OFF state, and the electrical connection with the output terminal DL1 is cut off. Therefore, as shown in Fig. 6, the voltage V21 at the node Ns21 and the voltage at the output terminal DL1 are pulled down from the reference power supply voltage VGND to the negative drive voltage signal VNA. Meanwhile, the voltage V11 at the node Ns11 remains at the reference power supply voltage VGND, as shown in Fig. 6.

[0111] During period T4, the terminals of the switch 143, the changeover switch 112, and the PMOS output switch 11 are controlled between the reference power supply voltage VGND and a second (negative) power supply voltage VDD2L. The terminals of the switch 133 and the changeover switch 122 are controlled between the reference power supply voltage VGND and a first (positive) power supply voltage VDD2H. The drain and source of the NMOS output switch 21 are controlled by a negative drive voltage signal VNA between the reference power supply voltage VGND and the power supply voltage VDD2L. A positive control voltage VGp within a predetermined voltage difference (withstand voltage) relative to the negative drive voltage signal VNA is applied to the gate of the NMOS output switch 21, so that the NMOS output switch 21 is turned on. Therefore, the PMOS output switch 11, the NMOS output switch 21, the switch 133, the switch 143, the changeover switch 112, and the changeover switch 122 are controlled within a predetermined element withstand voltage range lower than the output voltage range (VDD2L to VDD2H) of the output terminal DL1.

[0112] In the drive control of Fig. 6, the drive circuit 200_2 of Fig. 5 switches between a positive drive voltage signal VPA and a negative drive voltage signal VNA at a predetermined cycle and outputs them to the output terminal DL1. Therefore, for example, in a drive circuit including a plurality of drive circuits 200_2 of Fig. 5, some circuits may be shared between the drive circuits 200_2 that output drive voltage signals of different polarities at the same timing. Specifically, the amplifier 131 of the positive signal output unit 111 and the amplifier 141 of the negative signal output unit 121 can be shared between the two drive circuits 200_2 that output drive voltage signals of different polarities at the same timing. [Example]

[0113] FIG. 7 is a block diagram showing the configuration of a liquid crystal display device 400 according to a sixth embodiment of the present invention, which includes a data driver including a signal level conversion section and a drive circuit according to the present invention.

[0114] In FIG. 7, the display panel 20 is an active matrix liquid crystal display panel, and includes m horizontal scan lines S1 to Sm (m is a natural number equal to or greater than 2) extending in the horizontal direction of the two-dimensional screen, and n data lines D1 to Dn (n is a natural number equal to or greater than 2) extending in the vertical direction of the two-dimensional screen. A display cell, which serves as a pixel, is formed at each intersection of the horizontal scan lines and the data lines. The display cell includes at least a switch element and a pixel electrode. When the switch element is turned on in response to a scan pulse on the horizontal scan line, a grayscale voltage signal on the data line is applied to the pixel electrode via the switch element, and the brightness of the liquid crystal display device is controlled in response to the grayscale voltage applied to the pixel electrode. Note that FIG. 7 does not specifically show the configuration of the display cell.

[0115] The display control unit 65 receives a video signal VD that integrates control signals and the like, generates a timing signal based on a horizontal synchronization signal from the video signal VD, and supplies the generated signal to the scan driver 70. Furthermore, based on the video signal VD, the display control unit 65 supplies to the data driver 80 a video digital signal that includes a group of control signals representing various timing signals including a polarity inversion signal POL, a start pulse, and a clock signal CLK, and a series of pixel data PD that indicates the brightness level of each pixel in, for example, an 8-bit brightness gradation.

[0116] The scan driver 70 sequentially applies horizontal scan pulses to each of the horizontal scan lines S1 to Sm of the display panel 20 at the timing indicated by the control signal supplied from the display control unit 65.

[0117] The data driver 80 is formed in a semiconductor device such as an LSI (Large Scale Integrated Circuit). The data driver 80 converts pixel data PD included in the digital video signal supplied from the display control unit 65 into driving voltage signals G1 to Gn having gradation voltages corresponding to each pixel data PD for one horizontal scanning line, i.e., for every n pixels. The data driver 80 then applies the driving voltage signals G1 to Gn to the data lines D1 to Dn of the display panel 20. Note that the scanning driver 70 or the data driver 80 may be partly or entirely formed as an integral circuit with the display panel 20. The data driver 80 may also incorporate the display control unit 65. The data driver 80 may also be formed from a plurality of LSIs.

[0118] FIG. 8 is a block diagram showing an example of the internal configuration of the data driver 80. As shown in FIG.

[0119] As shown in FIG. 8, the data driver 80 includes a positive reference voltage generating circuit 500P, a negative reference voltage generating circuit 500N, a shift register 600, a data register latch 700, a level shift circuit group 800, a decoder unit 900, and a drive circuit group 200_4. The drive circuit group 200_4 includes a signal level conversion unit 100_4. A reference power supply voltage VGND and a positive LV power supply voltage VDD1H are supplied to the shift register 600 and the data register latch 700, respectively. A reference power supply voltage VGND, a positive HV power supply voltage VDD2H, and a negative HV power supply voltage VDD2L are supplied to the decoder unit 900, respectively. The level shift circuit group 800 and the drive circuit group 200_4 are supplied with the reference power supply voltage VGND, the positive LV power supply voltages VDD1H and VDD2H, and the negative LV power supply voltages VDD1L and VDD2L.

[0120] The shift register 600 generates a plurality of latch timing signals for selecting latches in synchronization with the clock signal CLK in response to the start pulse, and supplies the signals to the data register latch 700 .

[0121] The data register latch 700 receives a group of LV control signals that control various timings such as the video digital signal and the polarity inversion signal POL, and based on each of the latch timing signals supplied from the shift register 600, captures multiple pixel data pieces contained in the video digital signal and supplies each of them at the above latch timing to the level shift circuit group 800. The data register latch 700 alternately supplies each of the captured pixel data pieces to a positive polarity level shift circuit and a negative polarity level shift circuit included in the level shift circuit group 800, depending on the polarity inversion signal POL.

[0122] The level shift circuit group 800 converts the signal level of each pixel data piece based on the LV power supply voltage (VDD1H, VGND) for the logic circuit into a positive polarity HV digital signal (VGND / VDD2H) and a negative polarity HV digital signal (VDD2L / VGND), and supplies them to a plurality of positive polarity decoders 90P and a plurality of negative polarity decoders 90N included in the decoder unit 900. The level shift circuit group 800 may be provided with a plurality of signal level conversion circuits 100, 100_H, 100_L, 100_1 shown in Figures 1 (Figure 3), 2A, and 2B, or a combination thereof.

[0123] The decoder unit 900 is configured, for example, by assigning a pair of a positive polarity decoder 90P and a negative polarity decoder 90N to each of two output terminals of the data driver 80. Note that the order of the positive polarity decoders 90P and negative polarity decoders 90N can be changed within the decoder unit 900. For example, to reduce the layout area, decoders of the same polarity for multiple outputs may be arranged together.

[0124] The positive polarity reference voltage generating circuit 50P and the negative polarity reference voltage generating circuit 50N generate a plurality of reference voltages with different voltage values ​​and supply them to the positive polarity decoder 90P and the negative polarity decoder 90N provided for each of the plurality of output terminals of the data driver 80, respectively.

[0125] The positive polarity decoder 90P and the negative polarity decoder 90N select a positive polarity reference voltage and a negative polarity reference voltage corresponding to the positive polarity HV digital signal and the negative polarity HV digital signal, respectively, from the above-mentioned plurality of reference voltages, and supply them to the drive circuit group 200_4 as a positive polarity gradation voltage and a negative polarity gradation voltage, respectively.

[0126] The driving circuit group 200_4 receives a polarity inversion signal POL and LV control signals indicating various timings, and generates HV voltage signals for controlling the timing of each driving circuit of the driving circuit group 200_4 in a signal level conversion unit 100_4. The signal level conversion unit 100_4 includes one or more signal level conversion circuits 100, 100_H, 100_L, and 100_1 shown in FIGS. 1 (FIG. 3), 2A, and 2B, depending on the system of the LV control signals. Each driving circuit of the driving circuit group 200_4 receives a positive grayscale voltage and a negative grayscale voltage supplied from the decoder unit 900 as a positive high-voltage input signal (VP) and a negative high-voltage input signal (VN), and outputs amplified positive driving voltage signals (VPA) and negative driving voltage signals (VNA) from each output terminal of the data driver 80. In this case, the drive circuit group 200_4 receives the polarity inversion signal POL and the timing control signal as an LV control signal group in a pair of drive circuits (for example, a pair of drive circuits that respectively drive two adjacent output terminals) that output drive voltage signals of different polarities, and switches the polarity of the drive voltage signals output from each output terminal of the pair of drive circuits at a drive timing according to the LV control signal group.

[0127] For example, at a drive timing according to the polarity inversion signal POL and the timing control signal, a state in which a positive drive voltage signal is output from one output terminal of a pair of drive circuits and a negative drive voltage signal is output from the other output terminal is switched to a state in which a negative drive voltage signal is output from one output terminal and a positive drive voltage signal is output from the other output terminal.

[0128] The level shift circuit group 800, the decoder unit 900, and the drive circuit group 200_4 can be configured with transistors having a device breakdown voltage (for example, about 1 / 2 of the voltage difference |VDD2H-VDD2L|) lower than the positive and negative drive voltage ranges (VDD2L to VDD2H), respectively, which reduces the driver area and enables cost reduction. [Explanation of symbols]

[0129] 10 First level shift section 20 Second level shift section 30 Third level shift section 40 Fourth level shift unit 50 5th level shift unit 80 Data Driver 100, 100_H, 100_L, 100_1, 100A, 100B, 100C, 100D, 100E Signal level conversion circuit 100_2, 100_3 Signal level conversion section 200_1, 200_2 drive circuit 400 LCD display device

Claims

1. A drive circuit in which drive timing is controlled based on a group of low-voltage control signals, and which outputs from an output terminal a high-voltage first-polarity drive voltage signal having a first polarity with respect to a predetermined reference power supply voltage when driving a load, an output section that receives a high voltage input signal of a first polarity, amplifies the high voltage input signal of the first polarity, and outputs the first polarity drive voltage signal to a first node in response to a high voltage control signal of the first polarity; a first conductivity type transistor switch that supplies the voltage of the first node to the output terminal when in an on state, and cuts off the connection between the first node and the output terminal when in an off state; a control unit that supplies a high-voltage output control signal of a second polarity to a control end of the first conductivity type transistor switch in response to a high-voltage control signal of a second polarity with respect to the reference power supply voltage, the high-voltage output control signal having a second polarity for controlling the on / off of the first conductivity type transistor switch; a signal level conversion unit including first and second signal level conversion circuits; the first signal level conversion circuit converts the amplitude of a first control signal of the group of low-voltage control signals into an amplitude between a first power supply voltage of a first polarity and a second power supply voltage of a second polarity, and then converts the amplitude into an amplitude between a third power supply voltage of a first polarity, the voltage difference of which from the reference power supply voltage is greater than the first power supply voltage, and the reference power supply voltage, and supplies the generated signal to the output section as the high-voltage control signal of the first polarity; the second signal level conversion circuit first converts the amplitude of a second control signal of the group of low-voltage control signals to an amplitude between the first power supply voltage of a first polarity and the second power supply voltage of a second polarity, and then converts the amplitude to an amplitude between the reference power supply voltage and a fourth power supply voltage of a second polarity whose voltage difference from the reference power supply voltage is larger than the second power supply voltage, and supplies the generated signal to the control unit as the high-voltage control signal of the second polarity.

2. A drive circuit in which drive timing is controlled based on a group of low-voltage control signals, and which selects and outputs from an output terminal one of a first polarity drive voltage signal having a high voltage of a first polarity and a second polarity drive voltage signal having a high voltage of a second polarity with respect to a predetermined reference power supply voltage when driving a load, a first output section that receives a high voltage input signal of a first polarity, amplifies the high voltage input signal of the first polarity, and outputs the first polarity drive voltage signal to a first node in response to a first high voltage control signal of a first polarity; a first conductivity type transistor switch that supplies the voltage of the first node to the output terminal when in an on state, and cuts off the connection between the first node and the output terminal when in an off state; a first control unit that supplies a high-voltage output control signal of a second polarity to a control end of the first conductivity type transistor switch in response to a first high-voltage control signal of a second polarity, the high-voltage output control signal controlling on / off of the first conductivity type transistor switch; a second output section that receives a high voltage input signal of a second polarity, amplifies the high voltage input signal of the second polarity, and outputs the second polarity drive voltage signal to a second node in response to a second high voltage control signal of a second polarity; a second conductivity type transistor switch that supplies the voltage of the second node to the output terminal when in an on state, and cuts off the connection between the second node and the output terminal when in an off state; a second control unit that supplies a high-voltage output control signal of a first polarity to a control end of the second conductivity type transistor switch in response to a second high-voltage control signal of a first polarity, the high-voltage output control signal controlling the second conductivity type transistor switch on and off; a signal level conversion unit including first to fourth signal level conversion circuits; the first signal level conversion circuit converts the amplitude of a first control signal of the group of low-voltage control signals into an amplitude between a first power supply voltage of a first polarity and a second power supply voltage of a second polarity, and then converts the amplitude into an amplitude between a third power supply voltage of a first polarity, the voltage difference of which from the reference power supply voltage is greater than the first power supply voltage, and the reference power supply voltage, and supplies the generated signal to the first output section as a first high-voltage control signal of the first polarity; the second signal level conversion circuit converts the amplitude of a second control signal of the low-voltage control signal group into an amplitude between the first power supply voltage of a first polarity and the second power supply voltage of a second polarity, and then converts the amplitude into an amplitude between the reference power supply voltage and a fourth power supply voltage of a second polarity whose voltage difference from the reference power supply voltage is larger than the second power supply voltage, and supplies the generated signal to the first control unit as a first high-voltage control signal of the second polarity; the third signal level conversion circuit converts the amplitude of a third control signal of the low-voltage control signal group to an amplitude between the first power supply voltage of a first polarity and the second power supply voltage of a second polarity, and then converts the amplitude to an amplitude between the fourth power supply voltage of a second polarity and the reference power supply voltage, and supplies the generated signal to the second output section as a second high-voltage control signal of the second polarity; the fourth signal level conversion circuit first converts the amplitude of a fourth control signal of the group of low-voltage control signals to an amplitude between the first power supply voltage of a first polarity and the second power supply voltage of a second polarity, and then converts the amplitude to an amplitude between the third power supply voltage of the first polarity and the reference power supply voltage, and supplies the generated signal to the second control unit as a second high-voltage control signal of the first polarity.

3. the fourth control signal is common to the second control signal; Instead of the second and fourth signal level conversion circuits, a fifth signal level conversion circuit that converts the amplitude of the second control signal of the group of low-voltage control signals into an amplitude between the first power supply voltage of a first polarity and the second power supply voltage of a second polarity to generate first and second voltage signals, and further converts the amplitude of the first voltage signal into an amplitude between the fourth power supply voltage of a second polarity and the reference power supply voltage to generate a signal, and outputs the generated signal as the first high-voltage control signal of the second polarity, and converts the amplitude of the second voltage signal into an amplitude between the third power supply voltage of a first polarity and the reference power supply voltage to generate a signal, and outputs the generated signal as the second high-voltage control signal of the first polarity.

4. 4. The drive circuit according to claim 2, wherein the drive circuit is configured with transistors having a breakdown voltage lower than a voltage difference between the third power supply voltage of the first polarity and the fourth power supply voltage of the second polarity.

5. a data register latch that captures a series of pixel data pieces representing the luminance level of each pixel based on a video signal and outputs the captured plurality of pixel data pieces; a plurality of level shift circuits for converting the signal levels of the plurality of pixel data pieces output from the data register latch into positive high voltage signals and negative high voltage signals, respectively; a decoder unit that converts the positive high voltage signal and the negative high voltage signal for each pixel data piece into a positive gradation voltage signal and a negative gradation voltage signal, respectively; a group of drive circuits for outputting, as drive voltage signals via output terminals, signals that alternately select the positive polarity grayscale voltage signals and the negative polarity grayscale voltage signals for each output channel based on a group of low-voltage control signals that control drive timing; the first polarity and the second polarity are positive and negative, respectively; the drive circuit group includes the signal level conversion unit that receives a drive reference power supply voltage corresponding to the reference power supply voltage, a low-voltage positive power supply voltage and a high-voltage positive power supply voltage of positive polarity corresponding to the first and third power supply voltages, respectively, with respect to the reference power supply voltage, and a low-voltage negative power supply voltage and a high-voltage negative power supply voltage of negative polarity corresponding to the second and fourth power supply voltages, respectively, with respect to the reference power supply voltage, and converts the voltage amplitude of the low-voltage control signal group to generate a high-voltage control signal group; the drive circuit group is composed of transistors having an element breakdown voltage lower than a voltage difference between the high voltage positive power supply voltage and the high voltage negative power supply voltage, 5. A display driver, wherein each of the driving circuits in the driving circuit group includes the driving circuit according to claim 2.

6. A display driver according to claim 5; a liquid crystal display panel that is driven in response to the drive voltage signals output from the output terminals of the display driver for each of the output channels.

Images