Display device

Abstract

To provide a display device which is free from wiring damage even after being repeatedly stretched.SOLUTION: A display device provided herein comprises a stretchable lower substrate and a pattern layer disposed on the lower substrate. The pattern layer includes first and second plate patterns and a plurality of first and second line patterns. The device includes a plurality of pixels formed on the plurality of first plate patterns, a plurality of first connection lines connecting the plurality of pixels, a gate driver formed on the plurality of second plate patterns, a power supply formed on the plurality of second plate patterns, a plurality of second connection lines, and a stretchable upper substrate.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to displays, and more particularly to stretchable displays. [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light-emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide range of applications, from computer monitors and TVs to personal portable devices, and research is underway to develop display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, display devices that are manufactured by forming a display unit, wiring, etc. on a flexible substrate such as a flexible material such as plastic, and that can be stretched and contracted in a specific direction and can be changed into a variety of shapes, have been attracting attention as next-generation display devices. Summary of the Invention [Problem to be solved by the invention]

[0005] One or more embodiments of the present invention provide a display device in which wiring is not damaged even when stretched repeatedly. One or more embodiments of the present invention provide a display device in which all regions of the display device can be biaxially stretched. A further embodiment of the present invention provides a display device that can prevent wiring from being torn off during a lift-off process. A further embodiment of the present invention provides a display device that can prevent a drop in driving voltage. The technical advantages of the present invention are not limited to the advantages mentioned above, and other advantages not mentioned will be apparent to those skilled in the art from the following description. [Means for solving the problem]

[0006] In order to achieve the above-mentioned advantages, a display device according to one embodiment of the present invention includes an extensible lower substrate having a display area and a non-display area; a pattern layer disposed on the lower substrate and including a plurality of first plate patterns and a plurality of first wiring patterns formed in the display area and a plurality of second plate patterns and a plurality of second wiring patterns formed in the non-display area; a plurality of pixels formed on the plurality of first plate patterns; a plurality of first connecting wires connecting the plurality of pixels; gate drivers formed on the plurality of second plate patterns; power supplies formed on the plurality of second plate patterns; a plurality of second connecting wires disposed in the non-display area; and an extensible upper substrate covering the gate drivers, the power supplies, and the plurality of pixels. The non-display area includes a first area located outside the display area, a second area located outside the first area and in which a plurality of gate drivers are disposed, and a third area located outside the second area and in which a plurality of power supplies are disposed. The plurality of second connecting wires disposed in the first area contact a metal pattern disposed in a layer different from the plurality of second connecting wires through anchor holes.

[0007] A display device according to another embodiment of the present invention includes a ductile substrate, a plurality of rigid patterns formed on the ductile substrate, a plurality of pixels formed on top of a plurality of first plate patterns spaced apart from one another among the plurality of rigid patterns, and a power supply formed on top of some of a plurality of second plate patterns spaced apart from one another among the plurality of rigid patterns, wherein the power supply supplies a driving voltage to the plurality of pixels and is composed of power blocks spaced apart from one another in a first direction and a second direction. Further details of the embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0008] According to the present invention, by forming anchor holes in the buffer wiring, the extension reliability of the display device can be stably ensured. In the present invention, the buffer wiring is fixed through the anchor holes, so that the display device is not damaged during lift-off. According to the present invention, the non-display area is stretched in two axial directions, which can improve the usability of the display device.

[0009] In the present invention, the power supply may include an additional power block electrically connected between the power blocks, thereby reducing or minimizing the drop in driving voltage. The effects of the present invention are not limited to the above-mentioned examples, and various other effects are included within the scope of the present invention. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view of a display device according to an embodiment of the present invention; [Figure 2] 1 is an enlarged plan view of a display area of ​​a display device according to an embodiment of the present invention; [Figure 3] FIG. 3 is a cross-sectional view taken along the line III-III' shown in FIG. 2. [Figure 4] FIG. 4 is a cross-sectional view taken along the line IV-IV′ shown in FIG. 2. [Figure 5] 3 is a cross-sectional view taken along the line VV' shown in FIG. 2. FIG. [Figure 6] FIG. 2 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present invention. [Figure 7] 3 is an enlarged plan view of a non-display area of ​​a display device according to an embodiment of the present invention. FIG. [Figure 8] 2 is an enlarged plan view of a first region of a display device according to an embodiment of the present invention. FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along the line IX-IX′ shown in FIG. 8. [Figure 10] FIG. 4 is an enlarged plan view of a third region of the display device according to the embodiment of the present invention. [Figure 11]11 is a cross-sectional view taken along the line XI-XI' shown in FIG. 10. FIG. [Figure 12] FIG. 10 is an enlarged plan view of a third region of a display device according to another embodiment of the present invention. [Figure 13] 13 is a cross-sectional view taken along the line XIII-XIII' shown in FIG. 12. DETAILED DESCRIPTION OF THE INVENTION

[0011] The advantages and features of the present invention, and methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are provided solely to ensure that this disclosure will be complete and to fully convey the scope of the invention to those skilled in the art.

[0012] The shapes, areas, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, number of elements, etc. disclosed in the drawings for illustrating embodiments of the present invention are illustrative only, and the present invention is not limited to the details shown. The same reference symbols refer to the same elements throughout the specification. Furthermore, when describing the present invention, if a detailed description of related prior art is deemed to unnecessarily obscure the gist of the present invention, such a detailed description will be omitted. When using words such as "include," "have," etc., other parts may be added unless "only" is used. When a component is expressed in the singular, the plural is also included unless otherwise explicitly stated.

[0013] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0014] When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used. When an element or layer is referred to as "on" another element or layer, it includes the case where the element or layer is directly on top of the other element or layer, or where there are other layers or elements interposed therebetween.

[0015] Furthermore, although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of the present invention.

[0016] Furthermore, when the terms "connect" or "contact" are used in the present invention, the terms "immediately" or "directly" are not used, and one or more other parts may be located between the two parts to be connected or in contact with each other. Like reference numbers refer to like elements throughout the specification. The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the area and thickness of the components shown.

[0017] The features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the others or may be implemented together in a related relationship.

[0018] Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. A display device according to an embodiment of the present invention is a display device that can display an image even when warped or stretched, and may also be referred to as a stretchable display device. The display device has not only high flexibility but also stretchability compared to conventional display devices. Therefore, a user can warp or stretch the display device, and the shape of the display device can be freely changed by the user's operation. For example, when a user pulls the end of the display device, the display device can stretch in the direction of the user's pulling. Alternatively, when a user places the display device on an uneven surface, the display device can be warped to conform to the shape of the surface. Furthermore, when the force applied by the user is removed, the display device can return to its original shape.

[0019] Stretchable substrate and patterned layer FIG. 1 is a plan view of a display device according to an embodiment of the present invention. 2 is an enlarged plan view of a display area of ​​a display device according to an embodiment of the present invention, specifically, an enlarged plan view of area A shown in FIG. FIG. 3 is a cross-sectional view taken along the line III-III' shown in FIG.

[0020] Referring to FIG. 1, a display device 100 according to an embodiment of the present invention may include a lower substrate 111, a pattern layer 120, a plurality of pixels PX, a gate driver GD, a data driver DD, and a power supply PS. The gate driver GD and the data driver DD may also be referred to as driving circuits. The power supply PS may also be referred to as a power supply circuit PS. Referring to FIG. 3, the display device 100 according to an embodiment of the present invention may further include a filler layer 190 and an upper substrate 112.

[0021] The lower substrate 111 is a substrate for supporting and protecting various components of the display device 100. The upper substrate 112 is a substrate for covering and protecting various components of the display device 100. That is, the lower substrate 111 is a substrate for supporting the pattern layer 120 on which the pixels PX, gate drivers GD, and power supplies PS are formed. The upper substrate 112 is a substrate for covering the pixels PX, gate drivers GD, and power supplies PS.

[0022] The lower substrate 111 and the upper substrate 112 are each a ductile substrate. (Flexible board) The lower substrate 111 and the upper substrate 112 may be made of an insulating material that can bend or stretch. For example, the lower substrate 111 and the upper substrate 112 may be made of an elastomer such as silicone rubber (e.g., polydimethylsiloxane (PDMS)), polyurethane (PU), or PTFE (polytetrafluoroethylene), and thus have flexibility. The materials of the lower substrate 111 and the upper substrate 112 may be the same, but are not limited thereto and may be variously modified.

[0023] The lower substrate 111 and the upper substrate 112 may each be a ductile substrate capable of reversibly expanding and contracting. Therefore, the lower substrate 111 may also be referred to as a lower stretchable substrate, lower elastic substrate, lower stretchable substrate, lower ductile substrate, lower flexible substrate, first stretchable substrate, first elastic substrate, first stretchable substrate, first ductile substrate, or first flexible substrate. The upper substrate 112 may also be referred to as an upper stretchable substrate, upper elastic substrate, upper stretchable substrate, upper ductile substrate, upper flexible substrate, second stretchable substrate, second elastic substrate, second stretchable substrate, second ductile substrate, or second flexible substrate. The lower substrate 111 and the upper substrate 112 may each have a modulus of elasticity ranging from several MPa to several hundred MPa. The lower substrate 111 and the upper substrate 112 may each have a ductile breaking rate of 100% or more. In some embodiments, the ductile failure rate refers to the stretch rate at which a stretched object breaks or cracks. In other embodiments, the ductile failure rate refers to the elongation distance at which a stretched object breaks or cracks. That is, the ductile failure rate is defined as the percentage ratio of the original length of the object to the length of the stretched object at the point at which the object is sufficiently stretched to be considered broken. For example, if the length of an object (e.g., the lower substrate 111) is 100 cm when the object is not stretched, and then reaches a length of 110 cm when the object is stretched long enough to break or crack, the object has been stretched to 110% of its original length. In this case, the ductile failure rate of the object is 110%. This number can also be referred to as the ductile fracture ratio, because it is the ratio of the original unstretched length to the stretched length at the point at which failure occurs.

[0024] An object is considered broken when it no longer functions properly in a structure or circuit. For example, a conductor wire would be considered broken when there is a significant degradation in its ability to carry current and it no longer operates within the circuit specifications. Thus, in some embodiments, a complete severance of the wire is not required to be considered broken; rather, a small stress at the connection end, a small crack, a slight misalignment of the wire, or other movement that causes it to no longer function within its expected range of function would be considered a broken wire. An insulation is considered broken when it has been stretched sufficiently that it can no longer provide the amount of insulation required for a structure or circuit. Breaking, in some embodiments, also includes inelastic stretching, where the object is stretched sufficiently that it does not return to its original length and / or shape when unstretched.

[0025] The thickness of the lower substrate may be, but is not limited to, 10 um to 1 mm. The lower substrate 111 may have a display area (active area) AA and a non-active area (non-active area) NA surrounding the display area AA.

[0026] The display area AA is an area where an image is displayed on the display device 100. A plurality of pixels PX are arranged in the display area AA. Each pixel PX may include a display element and various driving elements for driving the display element. The various driving elements may include, but are not limited to, at least one thin film transistor (TFT) and a capacitor. Each of the plurality of pixels PX may be connected to various wirings. For example, each of the plurality of pixels PX may be connected to various wirings such as a gate wiring, a data wiring, a high potential power supply wiring, a low potential power supply wiring, a reference voltage wiring, etc.

[0027] The non-display area NA is an area where no image is displayed. The non-display area NA may be an area adjacent to and surrounding the display area AA. However, the non-display area NA is not limited thereto and may correspond to an area of ​​the lower substrate 111 excluding the display area AA, and may be deformed and separated into various shapes. Components for driving the pixels PX arranged in the display area AA may be arranged in the non-display area NA. A gate driver GD and a power supply PS may be arranged in the non-display area NA. A plurality of pads connected to the gate driver GD and the data driver DD may also be arranged in the non-display area NA, and each pad may be connected to a respective one of the pixels PX in the display area AA.

[0028] A pattern layer 120 made of a plastic material having lower flexibility than the lower substrate 111 may be disposed on the lower substrate 111. For example, the pattern layer 120 may be made of polyimide (PI), polyacrylate, polyacetate, or the like.

[0029] The pattern layer 120 may include a plurality of first plate patterns 121 (also referred to as a plurality of first plate structures 121) and a plurality of first wiring (line) patterns 122 arranged in the display area AA, and a plurality of second plate patterns 123 (also referred to as a plurality of second plate structures 123) and a plurality of second wiring (line) patterns 124 arranged in the non-display area NA.

[0030] The plurality of first plate patterns 121 are disposed in the display area AA of the lower substrate 111, and the plurality of pixels PX are formed on the plurality of first plate patterns 121. The plurality of second plate patterns 123 are disposed in the non-display area NA of the lower substrate 111, and the plurality of second plate patterns 123 are formed on the plurality of second plate patterns 123.

[0031] The first and second plate patterns 121 and 123 are arranged in an island shape, spaced apart from one another, and may be individually separated from one another. Therefore, the first and second plate patterns 121 and 123 may be referred to as first and second island patterns or first and second individual patterns. The first plate patterns 121, which are spaced apart from one another, may be connected by a first wiring pattern 122. The second plate patterns 123, which are spaced apart from one another in the non-display area NA, may be connected by a second wiring pattern 124. Specifically, the plurality of second plate patterns 123 arranged in the non-display area NA include a plurality of first sub-plate patterns 123a in which anchor holes are arranged, a plurality of second sub-plate patterns 123b in which gate drivers GD are arranged, and a plurality of third sub-plate patterns 123c in which power supplies PS are arranged.

[0032] 1, the plurality of first sub-board patterns 123a may be arranged adjacent to the display area AA in a first direction (e.g., the X-axis direction) and spaced apart in a second direction (e.g., the Y-axis direction). That is, the first sub-board patterns 123a may be arranged on both sides of the display area AA based on the first direction X. However, without being limited thereto, the first sub-board patterns 123a may be arranged only on one side of the display area AA in the first direction X. Anchor holes for connecting the plurality of connecting wires may be arranged on the plurality of first sub-board patterns 123a.

[0033] The second sub-plate patterns 123b may be arranged adjacent to the first sub-plate patterns 123a in the first direction X and spaced apart in the second direction Y. That is, the second sub-plate patterns 123b may be arranged on both sides of the first sub-plate patterns 123a based on the first direction X. However, this is not limited thereto, and the second sub-plate patterns 123b may be arranged only on one side of the first sub-plate patterns 123a.

[0034] A gate driver GD may be mounted on the plurality of second sub-plate patterns 123b. The gate driver GD may be formed on the second sub-plate pattern 123b using a gate-in-panel (GIP) method when manufacturing various components on the first plate pattern 121. Therefore, various circuit components constituting the gate driver GD, such as various transistors, capacitors, wiring, etc., may be disposed on the plurality of second sub-plate patterns 123b. However, without being limited thereto, the gate driver GD may also be mounted using a chip-on-film (COF) method.

[0035] The plurality of third sub-plate patterns 123c may be disposed adjacent to the plurality of second sub-plate patterns 123b in the first direction X and spaced apart in the second direction Y. That is, the plurality of third sub-plate patterns 123c may be disposed on both sides of the plurality of second sub-plate patterns 123b in the first direction X. However, this is not limited thereto, and the third sub-plate patterns 123c may be disposed only on one side of the plurality of second sub-plate patterns 123b in the first direction X. The plurality of third sub-plate patterns 123c may also be mounted with power supplies PS. The power supplies PS are a plurality of power blocks patterned during the manufacture of various components on the first plate pattern 121 and may be formed on the third sub-plate pattern 123c. Therefore, power blocks disposed on different layers may be disposed on the third sub-plate pattern 123c.

[0036] 1, the size of the plurality of first sub-board patterns 123a may be smaller than the size of the plurality of first board patterns 121. Specifically, the size of each of the plurality of first sub-board patterns 123a may be smaller than the size of each of the plurality of first board patterns 121. As described above, an anchor hole AH is arranged in each of the plurality of first sub-board patterns 123a, and the area occupied by the anchor hole AH is smaller than the area occupied by the pixel PX, so the size of each of the plurality of first sub-board patterns 123a may be smaller than the size of each of the plurality of first board patterns 121.

[0037] The size of the plurality of second sub-board patterns 123b may be larger than the size of the plurality of first board patterns 121. Specifically, the size of each of the plurality of second sub-board patterns 123b may be larger than the size of each of the plurality of first board patterns 121. As described above, the gate driver GD may be disposed on each of the plurality of second sub-board patterns 123b, and one stage of the gate driver GD may be disposed on each of the plurality of second sub-board patterns 123b. Therefore, since the area occupied by the various circuit components constituting one stage of the gate driver GD is relatively larger than the area occupied by the pixel PX, the size of each of the plurality of second sub-board patterns 123b may be larger than the size of each of the plurality of first board patterns 121.

[0038] 1, the plurality of second plate patterns 123 are shown to be arranged on both sides of the non-display area NA in the first direction X, but are not limited thereto and may be arranged in any area of ​​the non-display area NA. Also, the plurality of first plate patterns 121 and the plurality of second plate patterns 123 are shown to be rectangular, but are not limited thereto and the plurality of first plate patterns 121 and the plurality of second plate patterns 123 may be modified into various shapes.

[0039] Referring to Figures 1 and 3, the pattern layer 120 may further include a plurality of first wiring (line) patterns 122 arranged in the display area AA and a plurality of second wiring (line) patterns 124 arranged in the non-display area NA.

[0040] A plurality of first wiring patterns 122 may be arranged in the display area AA. The plurality of first wiring patterns 122 are patterns that connect adjacent first plate patterns 121 and may be referred to as first connecting patterns. That is, the plurality of first wiring patterns 122 are arranged between the plurality of first plate patterns 121.

[0041] A plurality of second wiring patterns 124 may be arranged in the non-display area NA. The plurality of second wiring patterns 124 may connect adjacent first and second plate patterns 121 and 123. For example, the plurality of second wiring patterns 124 may connect a first plate pattern 121 located at the edge of the display area AA to a second plate pattern 123 located in an area adjacent to the first plate pattern 121 in the non-display area NA. The plurality of second wiring patterns 124 may also be patterns that connect adjacent second plate patterns 123. Therefore, the plurality of second wiring patterns 124 may be referred to as second connecting patterns. That is, the plurality of second wiring patterns 124 are arranged between adjacent first and second plate patterns 121 and 123, and between adjacent second plate patterns 123.

[0042] 1, the plurality of first wiring patterns 122 and the plurality of second wiring patterns 124 have a curved shape. For example, the plurality of first wiring patterns 122 and the plurality of second wiring patterns 124 may have a sinusoidal wave shape. However, the shape of the plurality of first wiring patterns 122 and the plurality of second wiring patterns 124 is not limited thereto. For example, the plurality of first wiring patterns 122 and the plurality of second wiring patterns 124 may extend in a zigzag shape or may have various other shapes, such as a plurality of diamond-shaped substrates connected at their vertices. In addition, the number and shape of the plurality of first wiring patterns 122 and the plurality of second wiring patterns 124 shown in FIG. 1 are merely exemplary, and the number and shape of the plurality of first wiring patterns 122 and the plurality of second wiring patterns 124 may be variously changed depending on the design.

[0043] The plurality of first plate patterns 121, the plurality of first wiring patterns 122, the plurality of second plate patterns 123, and the plurality of second wiring patterns 124 are rigid patterns. That is, the plurality of first plate patterns 121, the plurality of first wiring patterns 122, the plurality of second plate patterns 123, and the plurality of second wiring patterns 124 may be more rigid than the lower substrate 111 and the upper substrate 112. That is, the modulus of elasticity of the plurality of first plate patterns 121, the plurality of first wiring patterns 122, the plurality of second plate patterns 123, and the plurality of second wiring patterns 124 may be higher than the modulus of elasticity of the lower substrate 111. The modulus of elasticity is a parameter indicating the ratio of deformation to stress applied to a substrate, and when the modulus of elasticity is relatively high, the hardness may be relatively high. Therefore, the plurality of first plate patterns 121, the plurality of second plate patterns 123, and the plurality of second wiring patterns 124 may be referred to as a plurality of first rigidity patterns, a plurality of second rigidity patterns, a plurality of third rigidity patterns, and a plurality of fourth rigidity patterns, respectively. The elastic moduli of the plurality of first plate patterns 121, the plurality of first wiring patterns 122, the plurality of second plate patterns 123, and the plurality of second wiring patterns 124 may be 1000 times or more higher than the elastic moduli of the lower substrate 111 and the upper substrate 112, but are not limited thereto.

[0044] The plurality of first plate patterns 121, the plurality of first wiring patterns 122, the plurality of second plate patterns 123, and the plurality of second wiring patterns 124, which are the plurality of rigid substrates, may be made of a plastic material having lower flexibility than the lower substrate 111 and the upper substrate 112, for example, polyimide (PI), polyacrylate, polyacetate, etc. In this case, the plurality of first plate patterns 121, the plurality of first wiring patterns 122, the plurality of second plate patterns 123, and the plurality of second wiring patterns 124 may be made of the same material, but are not limited thereto, and may be made of different materials.

[0045] In some embodiments, the lower substrate 111 may be defined as including a plurality of first lower patterns and a plurality of second lower patterns. The plurality of first lower patterns are arranged in an area of ​​the lower substrate 111 overlapping with the plurality of first plate patterns 121 and the plurality of second plate patterns 123, and the second lower pattern may be arranged in an area excluding the area where the plurality of first plate patterns 121 and the plurality of second plate patterns 123 are arranged, or may be arranged over the entire area of ​​the display device 100.

[0046] Furthermore, the upper substrate 112 may be defined as including a plurality of first upper patterns and a plurality of second upper patterns. The plurality of first upper patterns are arranged in an area of ​​the upper substrate 112 overlapping with the plurality of first plate patterns 121 and the plurality of second plate patterns 123, and the second upper pattern may be arranged in an area excluding the area where the plurality of first plate patterns 121 and the plurality of second plate patterns 123 are arranged, or may be arranged over the entire area of ​​the display device 100.

[0047] In this case, the elastic modulus of the plurality of first lower patterns and the first upper substrate may be greater than the elastic modulus of the second lower pattern and the second upper pattern. For example, the plurality of first lower patterns and the first upper pattern may be made of the same material as the plurality of first plate patterns 121 and the plurality of second plate patterns 123, and the second lower pattern and the second upper pattern may be made of a material having a lower elastic modulus than the plurality of first plate patterns 121 and the plurality of second plate patterns 123.

[0048] That is, the first lower pattern and the first upper pattern may be made of polyimide (PI), polyacrylate, polyacetate, etc., and the second lower pattern and the second upper pattern may be made of elastomers such as silicone rubber (e.g., polydimethylsiloxane (PDMS)), polyurethane (PU), and PTFE (polytetrafluoroethylene).

[0049] Non-display area driving element The gate driver GD is a component that supplies gate voltages to the pixels PX arranged in the display area AA. The gate driver GD includes a plurality of stages formed on the second sub-plate pattern 123b of the plurality of second plate patterns 123. The stages of the gate driver GD are electrically connected to each other through a plurality of gate connection lines. Therefore, a gate voltage output from one stage can be transferred to another stage. Each stage can sequentially supply gate voltages to the pixels PX connected to that stage.

[0050] The power supply PS is connected to the gate driver GD and can supply a gate driving voltage and a gate clock voltage. The power supply PS is connected to the pixels PX and can supply a pixel driving voltage to each of the pixels PX. The power supply PS can be formed on the third sub-plate pattern 123c of the second plate patterns 123. That is, the power supply PS can be formed adjacent to the gate driver GD on the second plate pattern 123. Each of the power supplies PS formed on the third sub-plate patterns 123c can be electrically connected to the gate driver GD and each of the pixels PX. That is, the power supplies PS formed on the third sub-plate patterns 123c can be connected by gate power supply connecting lines and pixel power supply connecting lines. Each of the power supplies PS can supply a gate driving voltage, a gate clock voltage, and a pixel driving voltage.

[0051] The printed circuit board PCB transmits signals and voltages for driving the display elements from a controller to the display elements. Therefore, the printed circuit board PCB may also be referred to as a driver board. A controller such as an IC chip, a circuit unit, etc. may be mounted on the printed circuit board PCB. A memory, a processor, etc. may also be mounted on the printed circuit board PCB. The printed circuit board PCB included in the display device 100 may include a stretched region and a non-stretched region to ensure stretchability. The IC chip, the circuit unit, the memory, the processor, etc. may be mounted in the non-stretched region, and wiring electrically connected to the IC chip, the circuit unit, the memory, and the processor may be arranged in the stretched region.

[0052] The data driver DD is a component that supplies data voltages to a plurality of pixels PX arranged in the display area AA. The data driver DD may be configured in the form of an IC chip and may also be referred to as a data integrated circuit (D-IC). The data driver DD may be mounted in a non-extending area of ​​a printed circuit board PCB. That is, the data driver DD may be mounted on the printed circuit board PCB in the form of a COB (Chip On Board). Although FIG. 1 illustrates the data driver DD being mounted in the COB (Chip On Board) method, the present invention is not limited thereto, and the data driver DD may also be mounted in the form of a COF (Chip on Film), COG (Chip on Glass), TCP (Tape Carrier Package), etc.

[0053] 1, one data driver DD is arranged to correspond to one row of first plate patterns 121 arranged in the display area AA, but this is not limited thereto. That is, one data driver DD may be arranged to correspond to a plurality of rows of first plate patterns 121. Hereinafter, reference will be made to both FIGS. 4 and 5 for a more detailed description of the display area AA of the display device 100 according to an embodiment of the present invention.

[0054] Planar and cross-sectional structure of the display area FIG. 4 is a cross-sectional view taken along the line IV-IV' shown in FIG. FIG. 5 is a cross-sectional view taken along the line VV' shown in FIG. For convenience of explanation, the following description will be made with reference to both FIGS.

[0055] 1 and 2, in the display area AA, a plurality of first plate patterns 121 are disposed on the lower substrate 111. The plurality of first plate patterns 121 are spaced apart from one another and disposed on the lower substrate 111. For example, the plurality of first plate patterns 121 may be disposed in a matrix form on the lower substrate 111 as shown in FIG. 1, but are not limited thereto.

[0056] 2 and 3, a pixel PX including a plurality of sub-pixels SPX is disposed on the first plate pattern 121. Each of the sub-pixels SPX may include a light-emitting element 170 as a display element, and a driving transistor 160 and a switching transistor 150 for driving the light-emitting element 170. However, the display element in the sub-pixel SPX is not limited to a light-emitting element and may be an organic light-emitting diode (OLED). The sub-pixels SPX may include, but are not limited to, red, green, and blue sub-pixels, and the colors of the sub-pixels SPX may be variously modified as needed.

[0057] The plurality of sub-pixels SPX may be connected to the plurality of pixel connecting lines 181 and 182. That is, the plurality of sub-pixels SPX may be electrically connected to the first pixel connecting line 181 extending in the first direction X. The plurality of sub-pixels SPX may be electrically connected to the second pixel connecting line 182 extending in the second direction Y.

[0058] Meanwhile, the pixel connecting lines 181 and 182 arranged in the display area AA may be referred to as first connecting lines, and the buffer lines, gate connecting lines or power lines arranged in the non-display area NA may be referred to as second connecting lines.

[0059] The cross-sectional structure of the display area AA will be specifically described below with reference to FIG.

[0060] 3, a plurality of inorganic insulating layers are disposed on the plurality of first plate patterns 121. For example, the plurality of inorganic insulating layers may include, but are not limited to, a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, and a passivation layer 145. Various inorganic insulating layers may be further disposed on the plurality of first plate patterns 121, or one or more of the inorganic insulating layers, i.e., the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145, may be omitted.

[0061] Specifically, a buffer layer 141 is disposed on the plurality of first plate patterns 121. The buffer layer 141 is formed on the plurality of first plate patterns 121 to protect various components of the display device 100 from the penetration of moisture (H2O), oxygen (O2), etc. from the outside of the lower substrate 111 and the plurality of first plate patterns 121. The buffer layer 141 may be made of an insulating material. For example, the buffer layer 141 may be made of a single layer or multiple layers made of at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). However, the buffer layer 141 may be omitted depending on the structure and characteristics of the display device 100.

[0062] In the display area AA, the buffer layer 141 may be formed only in an area where the lower substrate 111 overlaps with the plurality of first plate patterns 121. As described above, the buffer layer 141 may be made of an inorganic material and may be easily damaged, such as cracked, during the process of stretching the display device 100. Therefore, in the display area AA, the buffer layer 141 may not be formed in an area between the plurality of first plate patterns 121, but may be patterned into the shape of the plurality of first plate patterns 121 and formed only on the plurality of first plate patterns 121.

[0063] Furthermore, in the non-display area NA, the buffer layer 141 may be formed only in an area where the lower substrate 111 overlaps with the plurality of second plate patterns 123. As described above, the buffer layer 141 may be made of an inorganic material and may be easily damaged, such as cracked, during the process of stretching the display device 100. Therefore, in the non-display area NA, the buffer layer 141 may not be formed in an area between the plurality of second plate patterns 123, but may be patterned into the shape of the plurality of second plate patterns 123 and formed only on the plurality of second plate patterns 123.

[0064] As such, the buffer layer 141 may be formed only in the region where the lower substrate 111 overlaps with the plurality of first plate patterns 121 and the plurality of second plate patterns 123. As described above, the buffer layer 141 may be made of an inorganic material and may be easily damaged, such as cracked, during the process of stretching the display device 100. Therefore, the buffer layer 141 may not be formed in the region between the plurality of first plate patterns 121 and the plurality of second plate patterns 123, but may be patterned into the shapes of the plurality of first plate patterns 121 and the plurality of second plate patterns 123 and formed only on the plurality of first plate patterns 121 and the plurality of second plate patterns 123. Therefore, in the display device 100 according to an embodiment of the present invention, the buffer layer 141 is formed only in the region where the lower substrate 111 overlaps with the plurality of first plate patterns 121 and the plurality of second plate patterns 123, which are rigid patterns, thereby preventing damage to various components of the display device 100 even when the display device 100 is deformed, such as warped or stretched.

[0065] Referring to FIG. 3, a switching transistor 150 including a gate electrode 151, an active layer 152, a source electrode 153, and a drain electrode 154, and a driving transistor 160 including a gate electrode 161, an active layer 162, a source electrode, and a drain electrode 164 are formed on the buffer layer 141.

[0066] 3, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 are disposed on the buffer layer 141. For example, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 may each be formed of an oxide semiconductor. Alternatively, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), an organic semiconductor, or the like.

[0067] A gate insulating layer 142 is disposed on the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160. The gate insulating layer 142 electrically insulates the gate electrode 151 of the switching transistor 150 from the active layer 152 of the switching transistor 150 and electrically insulates the gate electrode 161 of the driving transistor 160 from the active layer 162 of the driving transistor 160. The gate insulating layer 142 may be made of an insulating material. For example, the gate insulating layer 142 may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0068] A gate electrode 151 of the switching transistor 150 and a gate electrode 161 of the driving transistor 160 are disposed on the gate insulating layer 142. The gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 are disposed to be spaced apart from each other on the gate insulating layer 142. The gate electrode 151 of the switching transistor 150 overlaps with the active layer 152 of the switching transistor 150, and the gate electrode 161 of the driving transistor 160 overlaps with the active layer 162 of the driving transistor 160.

[0069] The gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160 may each be made of various metal materials, such as, but not limited to, any one or an alloy of two or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a multilayer thereof. A first interlayer insulating layer 143 is disposed on the gate electrode 151 of the switching transistor 150 and the gate electrode 161 of the driving transistor 160. The first interlayer insulating layer 143 insulates the gate electrode 161 of the driving transistor 160 from the intermediate metal layer IM. The first interlayer insulating layer 143 may be made of an inorganic material, similar to the buffer layer 141. For example, the first interlayer insulating layer 143 may be made of a single layer of inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0070] An intermediate metal layer IM is disposed on the first interlayer insulating layer 143. The intermediate metal layer IM overlaps with the gate electrode 161 of the driving transistor 160. A storage capacitor is formed in the overlapping region of the intermediate metal layer IM and the gate electrode 161 of the driving transistor 160. Specifically, the gate electrode 161 of the driving transistor 160, the first interlayer insulating layer 143, and the intermediate metal layer IM form the storage capacitor. However, the arrangement region of the intermediate metal layer IM is not limited thereto, and the intermediate metal layer IM may overlap with other electrodes to form various storage capacitors.

[0071] The intermediate metal layer IM may be made of any one of various metal materials, such as, but not limited to, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more of these, or a multilayer thereof.

[0072] A second interlayer insulating layer 144 is disposed on the intermediate metal layer IM. The second interlayer insulating layer 144 insulates the gate electrode 151 of the switching transistor 150 from the source electrode 153 and drain electrode 154 of the switching transistor 150. The second interlayer insulating layer 144 also insulates the intermediate metal layer IM from the source electrode and drain electrode 164 of the driving transistor 160. The second interlayer insulating layer 144 may be made of an inorganic material, similar to the buffer layer 141. For example, the first interlayer insulating layer 143 may be made of a single layer of inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0073] A source electrode 153 and a drain electrode 154 of the switching transistor 150 are disposed on the second interlayer insulating layer 144. A source electrode and a drain electrode 164 of the driving transistor 160 are disposed on the second interlayer insulating layer 144. The source electrode 153 and the drain electrode 154 of the switching transistor 150 are disposed spaced apart in the same layer. Although the source electrode of the driving transistor 160 is omitted in FIG. 3 , the source electrode of the driving transistor 160 is also disposed spaced apart in the same layer as the drain electrode 164. In the switching transistor 150, the source electrode 153 and the drain electrode 154 may be electrically connected to the active layer 152 in a manner that they contact the active layer 152. In the driving transistor 160, the source electrode and the drain electrode 164 may be electrically connected to the active layer 162 in a manner that they contact the active layer 162. The drain electrode 154 of the switching transistor 150 may be electrically connected to the gate electrode 161 of the driving transistor 160 by contacting the gate electrode 161 of the driving transistor 160 through a contact hole.

[0074] The source electrode 153 and the drain electrodes 154, 164 may be made of various metal materials, such as, but not limited to, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), an alloy of two or more of these, or a multilayer thereof.

[0075] Although the driving transistor 160 has been described herein as having a coplanar structure, various transistors such as a staggered structure may also be used.

[0076] A gate pad GP and a data pad DP may be disposed on the second interlayer insulating layer 144 .

[0077] 4, the gate pad GP is a pad for transmitting a gate voltage to a plurality of sub-pixels SPX. The gate pad GP is connected to the first pixel connecting line 181 through a contact hole CH. The gate voltage supplied from the first pixel connecting line 181 can be transmitted from the gate pad GP to the gate electrode 151 of the switching transistor 150 through a line formed on the first plate pattern 121.

[0078] The data pad DP is a pad for transmitting a data voltage to the sub-pixels SPX. The data pad DP is connected to the second pixel connecting line 182 through a contact hole. The data voltage supplied from the second pixel connecting line 182 can be transmitted from the data pad DP to the source electrode 153 of the switching transistor 150 through a line formed on the first plate pattern 121.

[0079] The gate pad GP and the data pad DP may be made of the same material as the source electrode 153 and the drain electrodes 154 and 164, but are not limited thereto.

[0080] 3, a passivation layer 145 is formed on the switching transistor 150 and the driving transistor 160. That is, the passivation layer 145 covers the switching transistor 150 and the driving transistor 160 to protect them from the penetration of moisture, oxygen, etc. The passivation layer 145 may be made of an inorganic material and may be formed as a single layer or multiple layers, but is not limited thereto.

[0081] The gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may be patterned and formed only in areas overlapping the plurality of first plate patterns 121. The gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may also be made of an inorganic material, like the buffer layer 141, and may be easily damaged, such as cracked, during the stretching of the display device 100. Therefore, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may not be formed in areas between the plurality of first plate patterns 121, but may be patterned into the shape of the plurality of first plate patterns 121 and formed only on the plurality of first plate patterns 121.

[0082] A planarization layer 146 is formed on the passivation layer 145. The planarization layer 146 planarizes the tops of the switching transistor 150 and the driving transistor 160. The planarization layer 146 may be configured as a single layer or multiple layers and may be made of an organic material. Therefore, the planarization layer 146 may also be referred to as an organic insulating layer. For example, the planarization layer 146 may be made of an acrylic organic material, but is not limited thereto.

[0083] 3 , the planarization layer 146 may be disposed on the plurality of first plate patterns 121 to cover the upper and side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. The planarization layer 146 surrounds the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 together with the plurality of first plate patterns 121. Specifically, the planarization layer 146 may be disposed to cover the upper and side surfaces of the passivation layer 145, the side surfaces of the first interlayer insulating layer 143, the side surfaces of the second interlayer insulating layer 144, the side surfaces of the gate insulating layer 142, the side surfaces of the buffer layer 141, and a portion of the upper surfaces of the plurality of first plate patterns 121. Therefore, the planarization layer 146 can complement the steps on the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145, and can increase the adhesive strength between the planarization layer 146 and the pixel connecting wires 181 and 182 arranged on the side surfaces of the planarization layer 146.

[0084] 3, the inclination angle of the side surface of the planarization layer 146 may be smaller than the inclination angles of the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. For example, the side surface of the planarization layer 146 may have a gentler inclination than the inclination angles of the side surfaces of the passivation layer 145, the side surfaces of the first interlayer insulating layer 143 and the second interlayer insulating layer 144, the side surfaces of the gate insulating layer 142, and the side surface of the buffer layer 141. Therefore, the pixel connecting lines 181 and 182 arranged to contact the side surfaces of the planarization layer 146 are arranged with a gentle inclination, which reduces stress generated in the pixel connecting lines 181 and 182 when the display device 100 is stretched, thereby preventing the pixel connecting lines 181 and 182 from cracking or peeling off at the side surfaces of the planarization layer 146.

[0085] 2 to 4, the pixel connecting wires 181 and 182 refer to wires that electrically connect pads on the plurality of first plate patterns 121. The pixel connecting wires 181 and 182 are disposed on the plurality of first wiring patterns 122. The pixel connecting wires 181 and 182 may also extend onto the plurality of first plate patterns 121 to be electrically connected to the gate pads GP and the data pads DP on the plurality of first plate patterns 121. Referring to FIG. 5, the first wiring patterns 122 are not disposed in regions between the plurality of first plate patterns 121 where the pixel connecting wires 181 and 182 are not disposed.

[0086] The pixel connecting wires 181 and 182 include a first pixel connecting wire 181 and a second pixel connecting wire 182. The first pixel connecting wire 181 and the second pixel connecting wire 182 are disposed between a plurality of first plate patterns 121. Specifically, the first pixel connecting wire 181 refers to a wire of the pixel connecting wires 181 and 182 that extends in the X-axis direction between a plurality of first plate patterns 121, and the second pixel connecting wire 182 refers to a wire of the pixel connecting wires 181 and 182 that extends in the Y-axis direction between a plurality of first plate patterns 121.

[0087] The pixel connecting wires 181 and 182 may be made of a metal material such as copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or may have a laminated structure of metal materials such as copper / molybdenum-titanium (Cu / MoTi), titanium / aluminum / titanium (Ti / Al / Ti), etc., but are not limited thereto.

[0088] In a typical display device, various wirings such as a plurality of gate wirings, a plurality of data wirings, etc. are arranged to extend linearly between a plurality of sub-pixels, and a plurality of sub-pixels are connected to one signal wiring. Therefore, in a typical display device, various wirings such as a plurality of gate wirings, a plurality of data wirings, a plurality of high potential power supply wirings, a plurality of reference voltage wirings, etc. are extended from one side to the other side of the organic light emitting display device without being interrupted on the substrate.

[0089] In contrast, in the display device 100 according to an embodiment of the present invention, various wirings such as linear gate wirings, data wirings, high potential power supply wirings, reference voltage wirings, etc., which are likely to be used in a general organic light emitting display device, are arranged only on the plurality of first plate patterns 121 and the plurality of second plate patterns 123. That is, in the display device 100 according to an embodiment of the present invention, linear wirings may be arranged only on the plurality of first plate patterns 121 and the plurality of second plate patterns 123.

[0090] In the display device 100 according to an embodiment of the present invention, pads on two adjacent first plate patterns 121 or two adjacent second plate patterns 123 may be connected by pixel connecting wires 181 and 182 to connect discontinuous wires on the first plate pattern 121 or the second plate pattern 123. That is, the pixel connecting wires 181 and 182 electrically connect the gate pads GP or the data pads DP on two adjacent first plate patterns 121. Therefore, the display device 100 according to an embodiment of the present invention may include a plurality of pixel connecting wires 181 and 182 to electrically connect various wires such as gate wires, data wires, high potential power supply wires, reference voltage wires, etc. between the plurality of first plate patterns 121 and the plurality of second plate patterns 123. For example, gate wires may be arranged on the plurality of first plate patterns 121 arranged adjacent to each other in the first direction X, and gate pads GP may be arranged at both ends of the gate wires. In this case, the gate pads GP on the first plate patterns 121 arranged adjacent to each other in the first direction X may be connected to each other by the first pixel connecting wires 181 functioning as gate wires. Thus, the gate wires arranged on the first plate patterns 121 and the first pixel connecting wire 181 arranged on the second plate pattern 123 may function as one gate wire. In addition, among all the various wires that may be included in the display device 100, wires extending in the first direction X, such as light emitting signal wires, low potential power supply wires, and high potential power supply wires, may also be electrically connected by the first pixel connecting wires 181 as described above.

[0091] 2 and 4, the first pixel connecting wire 181 may connect gate pads GP on two adjacent first plate patterns 121 among the gate pads GP on the plurality of first plate patterns 121 arranged adjacently in the first direction X. The first pixel connecting wire 181 may function as, but is not limited to, a gate wire, an emission signal wire, a high potential power supply wire, or a low potential power supply wire. For example, the first pixel connecting wire 181 may function as a gate wire and electrically connect gate pads GP on two first plate patterns 121 arranged adjacently in the first direction X. Therefore, as described above, the gate pads GP on the plurality of first plate patterns 121 arranged in the first direction X may be connected by the first pixel connecting wire 181 functioning as a gate wire, and one gate voltage may be transmitted thereto.

[0092] 3, the second pixel connecting wire 182 may connect data pads DP on two adjacent first plate patterns 121 among the data pads DP on the first plate patterns 121 arranged adjacently in the second direction Y. The second pixel connecting wire 182 may function as, but is not limited to, a data wire, a high potential power supply wire, a low potential power supply wire, or a reference voltage wire. For example, the second pixel connecting wire 182 may function as a data wire and electrically connect the data wires on the two first plate patterns 121 arranged adjacently in the second direction Y. As described above, the internal wires on the first plate patterns 121 arranged in the second direction Y may be connected by the second pixel connecting wires 182 functioning as data wires, and one data voltage may be transmitted.

[0093] 4, the first pixel connecting wire 181 may be formed in contact with the upper and side surfaces of the planarization layer 146 disposed on the first plate pattern 121 and extend to the upper surface of the first wiring pattern 122. Also, as shown in FIG. 3, the second pixel connecting wire 182 may be formed in contact with the upper and side surfaces of the planarization layer 146 disposed on the first plate pattern 121 and extend to the upper surface of the first wiring pattern 122.

[0094] However, as shown in FIG. 5, since there is no need to arrange a rigid pattern in the area where the first pixel connecting wire 181 and the second pixel connecting wire 182 are not arranged, the first wiring pattern 122, which is a rigid pattern, is not arranged below the first pixel connecting wire 181 and the second pixel connecting wire 182.

[0095] 3, a bank 147 is formed on the connection pad CNT, the pixel connecting wires 181 and 182, and the planarization layer 146. The bank 147 is a component that separates adjacent subpixels SPX. The bank 147 is disposed to cover at least a portion of the pad PD, the pixel connecting wires 181 and 182, and the planarization layer 146. The bank 147 may be made of an insulating material. The bank 147 may also include a black material. The black material in the bank 147 serves to shield the wires visible through the display area AA. The bank 147 may be made of a transparent carbon-based compound, specifically, carbon black. However, the bank 147 is not limited thereto and may be made of a transparent insulating material. Although the height of the bank 147 is shown to be lower than the height of the light emitting element 170 in FIG. 3, the height of the bank 147 is not limited thereto and may be the same as the height of the light emitting element 170.

[0096] 3, a light emitting element 170 is disposed on the connection pad CNT and the first pixel connecting wire 181. The light emitting element 170 includes an n-type layer 171, an active layer 172, a p-type layer 173, an n-electrode 174, and a p-electrode 175. The light emitting element 170 of the display device 100 according to an embodiment of the present invention has a flip-chip structure in which the n-electrode 174 and the p-electrode 175 are formed on one side.

[0097] The n-type layer 171 may be formed by implanting n-type impurities into gallium nitride (GaN) having excellent crystallinity. The n-type layer 171 may be disposed on a separate base substrate made of a material that can emit light.

[0098] An active layer 172 is disposed on the n-type layer 171. The active layer 172 is a light-emitting layer that emits light in the light-emitting element 170, and may be made of a nitride semiconductor, for example, indium gallium nitride (InGaN). A p-type layer 173 is disposed on the active layer 172. The p-type layer 173 may be formed by implanting p-type impurities into gallium nitride (GaN).

[0099] As described above, the light emitting device 170 according to an embodiment of the present invention is manufactured by sequentially stacking the n-type layer 171, the active layer 172, and the p-type layer 173, etching predetermined portions, and then forming the n-electrode 174 and the p-electrode 175. At this time, the predetermined portions are spaces for separating the n-electrode 174 and the p-electrode 175, and are etched to expose portions of the n-type layer 171. In other words, the surfaces of the light emitting device 170 on which the n-electrode 174 and the p-electrode 175 are disposed may have different height levels rather than being flat.

[0100] In this manner, an n-electrode 174 is disposed in the etched region, and may be made of a conductive material. A p-electrode 175 is disposed in the unetched region, and may also be made of a conductive material. For example, an n-electrode 174 is disposed on the n-type layer 171 exposed by the etching process, and a p-electrode 175 is disposed on the p-type layer 173. The p-electrode 175 may be made of the same material as the n-electrode 174.

[0101] The adhesive layer AD is disposed between the upper surfaces of the connection pads CNT and the first pixel connecting wires 181 and the connection pads CNT and the first pixel connecting wires 181, and the light emitting element 170 may be adhered onto the connection pads CNT and the first pixel connecting wires 181. In this case, the n-electrode 174 may be disposed on the first pixel connecting wires 181, and the p-electrode 175 may be disposed on the connection pads CNT.

[0102] The adhesive layer AD may be a conductive adhesive layer in which conductive balls are dispersed on an insulating base member. When heat or pressure is applied to the adhesive layer AD, the conductive balls are electrically connected in the heat- or pressure-applied portions, resulting in conductive properties, while the unpressured portions may be insulating. For example, the n-electrode 174 is electrically connected to the first pixel connecting line 181 through the adhesive layer AD, and the p-electrode 175 is electrically connected to the connection pad CNT through the adhesive layer AD. The adhesive layer AD may be applied to the upper surface of the first pixel connecting line 181 and the connection pad CNT by inkjet or other methods, and then the light emitting device 170 may be transferred onto the adhesive layer AD. The light emitting device 170 may be pressurized and heated to electrically connect the connection pad CNT to the p-electrode 175 and the first pixel connecting line 181 to the n-electrode 174. However, the adhesive layer AD, except for the portion of the adhesive layer AD disposed between the n-electrode 174 and the first pixel connecting line 181 and the portion of the adhesive layer AD disposed between the p-electrode 175 and the connection pad CNT, is insulating. Meanwhile, the adhesive layer AD may be disposed on the connection pad CNT and the first pixel connecting line 181 in a separated form.

[0103] The connection pad CNT is electrically connected to the drain electrode 164 of the driving transistor 160 and receives a driving voltage for driving the light emitting element 170 from the driving transistor 160. A low potential driving voltage for driving the light emitting element 170 is applied to the first pixel connecting wire 181. When the display device 100 is turned on, different voltage levels applied to the connection pad CNT and the first pixel connecting wire 181 are transmitted to the n-electrode 174 and the p-electrode 175, respectively, causing the light emitting element 170 to emit light.

[0104] The upper substrate 112 is a substrate that supports various components disposed below the upper substrate 112. Specifically, the upper substrate 112 may be formed by coating a material constituting the upper substrate 112 on the lower substrate 111 and the first plate pattern 121 and then curing the material, and may be disposed in contact with the lower substrate 111, the first plate pattern 121, the first wiring pattern 122, and the pixel connecting wires 181 and 182.

[0105] The upper substrate 112 may be made of the same material as the lower substrate 111. For example, the upper substrate 112 may be made of an elastomer such as silicone rubber, e.g., polydimethylsiloxane (PDMS), polyurethane (PU), or PTFE (polytetrafluoroethylene), and thus may have flexibility. However, the material of the upper substrate 112 is not limited thereto.

[0106] 3, a polarizing layer may be disposed on the upper substrate 112. The polarizing layer may polarize light incident from outside the display device 100 to reduce external light reflection. In addition, other optical films, etc., other than the polarizing layer may be disposed on the upper substrate 112.

[0107] In addition, a filler layer 190 may be disposed on the front surface of the lower substrate 111 to fill a gap between the components disposed on the upper substrate 112 and the lower substrate 111. The filler layer 190 may be made of a curable adhesive. Specifically, a material constituting the filler layer 190 may be coated on the front surface of the lower substrate 111 and then cured, so that the filler layer 190 may be disposed between the components disposed on the upper substrate 112 and the lower substrate 111. For example, the filler layer 190 may be an optically clear adhesive (OCA), and may be made of an acrylic adhesive, a silicone adhesive, a urethane adhesive, or the like.

[0108] Display area circuit structure FIG. 6 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present invention. In the following, for the sake of convenience, the structure and operation of a subpixel SPX of a display device according to one embodiment of the present invention will be described when the subpixel SPX is a 2T (Transistor) 1C (Capacitor) pixel circuit, but the present invention is not limited to this.

[0109] 3 and 6, a sub-pixel SPX of a display device according to an embodiment of the present invention may include a switching transistor 150, a driving transistor 160, a storage capacitor C, and a light emitting element 170.

[0110] The switching transistor 150 applies a data signal DATA, which is supplied through a second pixel connecting line 182, to the driving transistor 160 and the storage capacitor C in response to a gate signal SCAN, which is supplied through a first pixel connecting line 181.

[0111] The gate electrode 151 of the switching transistor 150 is electrically connected to the first pixel connecting wire 181, the source electrode 153 of the switching transistor 150 is connected to the second pixel connecting wire 182, and the drain electrode 154 of the switching transistor 150 is connected to the gate electrode 161 of the driving transistor 160.

[0112] The driving transistor 160 operates to allow a driving current to flow based on the high potential power supply VDD and the data voltage DATA supplied through the first pixel connecting line 181 in response to the data voltage DATA stored in the storage capacitor C.

[0113] The gate electrode 161 of the driving transistor 160 is electrically connected to the drain electrode 154 of the switching transistor 150, the source electrode of the driving transistor 160 is connected to the first pixel connecting line 181, and the drain electrode 164 of the driving transistor 160 is connected to the light-emitting element 170.

[0114] The light emitting device 170 can be operated to emit light by the driving current generated by the driving transistor 160. As described above, the n-electrode 174 of the light emitting device 170 is connected to the first pixel connecting line 181 and receives the low potential power supply VSS, and the p-electrode 175 of the light emitting device 170 is connected to the drain electrode 164 of the driving transistor 160 and receives a driving voltage corresponding to the driving current.

[0115] The subpixel SPX of the display device according to one embodiment of the present invention is configured as a 2T1C structure including a switching transistor 150, a driving transistor 160, a storage capacitor C, and a light emitting element 170, but when a compensation circuit is added, it can be configured in various ways such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

[0116] As described above, a display device according to one embodiment of the present invention may include a plurality of sub-pixels on a first substrate, which is a rigid substrate, and each of the plurality of sub-pixels SPX may include a switching transistor, a driving transistor, a storage capacitor, and a light-emitting element.

[0117] Therefore, the display device according to one embodiment of the present invention can not only be extended by the lower substrate, but also has a pixel circuit with a 2T1C structure on each first substrate, and can emit light according to the data voltage in accordance with each gate timing.

[0118] Pattern layer for hidden areas FIG. 7 is an enlarged plan view of a non-display area of ​​a display device according to an embodiment of the present invention. Specifically, Figure 7 is an enlarged plan view of region B shown in Figure 1. For reference, in Figure 7, thin wavy lines indicate that only the second wiring pattern is disposed, and thick wavy lines indicate that the second connecting wiring, such as a buffer wiring, a gate connecting wiring, or a power wiring, is disposed on the second wiring pattern.

[0119] 7, the non-display area NA includes a first area A1 located outside the display area AA, a second area A2 located outside the first area A1, and a third area A3 located outside the second area A2. For example, the non-display area NA includes the first area A1 disposed adjacent to the display area AA, the second area A2 disposed adjacent to the first area A1, and the third area A3 disposed adjacent to the second area A2. The second area A2 may be disposed between the first area A1 and the third area A3.

[0120] Anchor holes AH are arranged in the first region A1, gate drivers GD are arranged in the second region A2, and power blocks PB constituting the power supply PS are arranged in the third region A3.

[0121] That is, the first area A1, the second area A2, and the third area A3 are sequentially disposed outside the display area AA based on the first direction X. Therefore, the anchor holes AH, the gate drivers GD, and the power supplies PS are sequentially disposed in the area adjacent to the display area AA based on the first direction X.

[0122] A plurality of second plate patterns 123, on which gate drivers GD and power supplies PS are formed, may be arranged in the non-display area NA. Second wiring patterns 124 may be arranged to connect the adjacent first plate patterns 121 and second plate patterns 123 and to connect the adjacent second plate patterns 123. The second wiring patterns 124 may be referred to as second connecting patterns. For example, the second wiring patterns 124 may be arranged between the adjacent first plate patterns 121 and second plate patterns 123, and the second wiring patterns 124 may be arranged between the adjacent second plate patterns 123.

[0123] Specifically, the multiple second plate patterns 123 arranged in the non-display area NA include multiple first sub-plate patterns 123a located in the first region A1 and having anchor holes AH arranged therein, multiple second sub-plate patterns 123b located in the second region A2 and having gate drivers GD arranged therein, and multiple third sub-plate patterns 123c located in the third region A3 and having power supplies PS arranged therein.

[0124] More specifically, on one side of the non-display area NA, in the first area A1, a plurality of first sub-board patterns 123a are arranged in a row along the second direction Y, in the second area A2, a plurality of second sub-board patterns 123b are arranged in a row along the second direction Y, and in the third area A3, a plurality of third sub-board patterns 123c are arranged in multiple rows along the second direction Y.

[0125] For example, the plurality of first sub-plate patterns 123a may be arranged in a first region A1 and spaced apart from each other only in the second direction Y, the plurality of second sub-plate patterns 123b may be arranged in a second region A2 and spaced apart from each other only in the second direction Y, and the plurality of third sub-plate patterns 123c may be arranged in a third region A3 and spaced apart from each other in both the first direction X and the second direction Y.

[0126] The size of the plurality of first sub-board patterns 123a may be smaller than the size of the plurality of second sub-board patterns 123b. Specifically, the size of each of the plurality of first sub-board patterns 123a may be smaller than the size of each of the plurality of second sub-board patterns 123b. As described above, anchor holes AH may be disposed in each of the plurality of first sub-board patterns 123a. The area of ​​the anchor holes AH disposed in the plurality of first sub-board patterns 123a may be smaller than the area of ​​the gate drivers GD disposed in the plurality of second sub-board patterns 123b.

[0127] The multiple second wiring patterns 124 arranged in the non-display area NA include a first sub-wiring pattern 124a located in the first area A1, a second sub-wiring pattern 124b located in the second area A2, and a third sub-wiring pattern 124c located in the third area A3.

[0128] The first sub-wiring pattern 124a can connect the first board pattern 121 arranged in the display area AA to the first sub-board pattern 123a of the second board pattern 123 arranged in the non-display area NA. The first sub-wiring pattern 124a also connects the first sub-board pattern 123a and the second sub-board pattern 123b arranged in the non-display area NA.

[0129] More specifically, the first sub-wiring pattern 124a may include a 1-1 sub-wiring pattern 124a-1 and a 1-2 sub-wiring pattern 124a-2. The 1-1 sub-wiring pattern 124a-1 extends in the first direction X to connect the first board pattern 121 and the first sub-board pattern 123a, and to connect the first sub-board pattern 123a and the second sub-board pattern 123b. The 1-2 sub-wiring pattern 124a-2 extends in the second direction Y and the 1-1 sub-wiring pattern 124a-1 to connect the plurality of first sub-board patterns 123a.

[0130] The second sub-wiring pattern 124b extends in the second direction Y and connects the plurality of second sub-board patterns 123b.

[0131] The third sub-wiring pattern 124c includes a 3-1 sub-wiring pattern 124c-1 and a 3-2 sub-wiring pattern 124c-2. The 3-1 sub-wiring pattern 124c-1 extends in the first direction X and can connect the third sub-plate patterns 123c spaced apart in the first direction X. The 3-2 sub-wiring pattern 124c-2 extends in the second direction Y and can connect the third sub-plate patterns 123c spaced apart in the second direction Y.

[0132] Meanwhile, a plurality of gate connecting wires 184 are disposed on the second sub-wiring pattern 124b disposed in the second region A2 to electrically connect a plurality of gate drivers GD. That is, a gate driving voltage and a gate clock voltage are applied to the plurality of gate connecting wires 184 disposed on the second sub-wiring pattern 124b, allowing each of the plurality of gate drivers GD to output a gate voltage. Although FIG. 7 illustrates that the gate connecting wires 184 are disposed on only some of the plurality of second sub-wiring patterns 124b, this is not limiting, and the gate connecting wires 184 may be disposed on all of the plurality of second sub-wiring patterns 124b.

[0133] Furthermore, the gate connecting wires 184 formed on the second sub-wiring pattern 124b may have the same shape as the second sub-wiring pattern 124b. Specifically, each of the gate connecting wires 184 may have a bent shape. For example, each of the gate connecting wires 184 may have a sinusoidal wave shape. However, the shape of each of the gate connecting wires 184 is not limited thereto. For example, each of the gate connecting wires 184 may extend in a zigzag shape or may have various other shapes, such as a plurality of diamond-shaped substrates connected at their vertices. Furthermore, the number and shape of each of the gate connecting wires 184 shown in FIG. 8 are merely exemplary, and the number and shape of each of the gate connecting wires 184 may be variously changed according to design.

[0134] 7, the gate connecting wires 184 are not necessarily disposed on all of the second sub-wiring patterns 124b, and some second sub-wiring patterns 124b may not have the gate connecting wires 184. The second sub-wiring patterns 124b not having the gate connecting wires 184 may be additional structures provided to ensure rigidity against extension in the second direction Y.

[0135] Configuration of the first area FIG. 8 is an enlarged plan view of a first region of a display device according to an embodiment of the present invention. FIG. 9 is a cross-sectional view taken along the line IX-IX′ shown in FIG. 8, buffer wiring 183, which is wiring connecting a gate driver GD and a plurality of pixels PX, is arranged in the first region A1. Anchor holes AH for fixing the buffer wiring 183 may be arranged in the first region A1. For example, the buffer wiring 183 may be formed on the first sub-wiring pattern 124a connecting the first plate pattern 121 and the first sub-plate pattern 123a, and may connect the gate driver GD arranged on the first sub-plate pattern 123a to the pixels PX arranged on the first plate pattern 121.

[0136] 8, the widths of both ends of the 1-1 sub-wiring pattern 124a-1 located between the first board pattern 121 and the first sub-board pattern 123a may be greater than the width of the central region of the 1-1 sub-wiring pattern 124a-1. The widths of both ends of the 1-1 sub-wiring pattern 124a-1 formed between the first sub-board pattern 123a and the second sub-board pattern 123b may also be greater than the width of the central region.

[0137] Therefore, in the buffer wiring 183 formed on the 1-1 sub-wiring pattern 124a-1, the width of the buffer wiring 183 arranged in the area overlapping with the first board pattern 121, the first sub-board pattern 123a or the second sub-board pattern 123b may be larger than the width of the buffer wiring 183 arranged in the area overlapping with the 1-1 sub-wiring pattern 124a-1.

[0138] That is, because the width of the central region of the buffer wiring 183 is relatively thin, the buffer wiring 183 can be extended with less force. As a result, the extension rate of the buffer wiring 183 can be improved. Furthermore, because the width of both ends of the buffer wiring 183 is relatively thick, the area over which the buffer wiring 183 can contact and be fixed to the first plate pattern 121, the first sub-board pattern 123a, or the second sub-board pattern 123b increases. Therefore, even if the buffer wiring 183 is extended repeatedly, it is not separated from the first plate pattern 121, the first sub-board pattern 123a, or the second sub-board pattern 123b. As a result, the extension reliability of the buffer wiring 183 can be improved.

[0139] Each buffer line 183 extends in a first direction X to connect the gate driver GD to a plurality of pixels PX, and the plurality of buffer lines 183 are arranged in a second direction Y.

[0140] The plurality of buffer wirings 183 are arranged across the first sub-board pattern 123a and the first sub-wiring pattern 124a. Specifically, the first sub-wiring pattern 124a is composed of a 1-1 sub-wiring pattern 124a-1 extending in the first direction X and a 1-2 sub-wiring pattern 124a-2 extending in the second direction Y, or the buffer wirings 183 extend only in the first direction X. Therefore, the buffer wirings 183 may be formed on the first sub-board pattern 123a and the 1-1 sub-wiring pattern 124a-1. The buffer wirings 183 may not be formed on the 1-2 sub-wiring pattern 124a-2. Furthermore, the buffer wirings 183 formed on the 1-1 sub-wiring pattern 124a-1 may have the same shape as the 1-1 sub-wiring pattern 124a-1. Specifically, each of the plurality of buffer wirings 183 has a bent shape. For example, each of the plurality of buffer wirings 183 may have a sinusoidal shape. However, the shape of each of the plurality of buffer wirings 183 is not limited thereto, and each of the plurality of buffer wirings 183 may have various shapes, such as extending in a zigzag pattern or extending in a pattern of a plurality of diamond-shaped substrates connected at their vertices. In addition, the number and shape of each of the plurality of buffer wirings 183 shown in FIG. 8 are merely exemplary, and the number and shape of each of the plurality of buffer wirings 183 may be variously changed depending on the design.

[0141] The buffer wiring 183 formed on the first sub-board pattern 123a may have a linear shape extending in the first direction X. However, the shape of the buffer wiring 183 formed on the first sub-board pattern 123a is not limited thereto and may have a curved shape as described above. The width of the buffer wiring 183 formed on the first sub-board pattern 123a may be greater than the width of the buffer wiring 183 formed on the 1-1 sub-wiring pattern 124a-1. Referring to FIG. 8 , the width of the 1-1 sub-wiring pattern 124a-1 may be different. For example, the width of the 1-1 sub-wiring pattern 124a-1 disposed in a region adjacent to the first sub-board pattern 123a or the first plate pattern 121 may be greater than the width of the curved region of the 1-1 sub-wiring pattern 124a-1.

[0142] Therefore, by having some of the plurality of buffer wirings 183 bent, the first area A1 of the non-display area NA can be extended in the first direction X. And by having other parts of the plurality of buffer wirings 183 linear, it is possible to reduce the resistance of the buffer wirings 183. Therefore, it is possible to reduce or minimize the delay of the gate voltage transmitted by the plurality of buffer wirings 183.

[0143] A plurality of anchor holes AH are formed on the first sub-board pattern 123a, and bring the plurality of buffer wirings 183 into contact with metal patterns MT (or conductive patterns MT) arranged on different layers.

[0144] 8, the anchor holes AH may be formed to overlap the buffer wiring 183 formed on the first sub-board pattern 123a. Specifically, since the buffer wiring 183 formed on the first sub-board pattern 123a extends in the first direction X, the anchor holes AH may be arranged in the first direction X by the buffer wiring 183 formed on the first sub-board pattern 123a.

[0145] For example, on the first sub-board pattern 123a, a plurality of buffer wirings 183 extending in the first direction X are arranged in the second direction Y, and therefore a plurality of anchor holes AH arranged in the first direction X may be arranged in the second direction Y.

[0146] 9, the buffer wirings 183 can be in direct contact with other metal patterns MT through the anchor holes AH, respectively.

[0147] On the first sub-plate pattern 123a disposed on the lower substrate 111, a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, and a passivation layer 145, which are inorganic insulating layers, and a planarization layer 146, which is an organic insulating layer, may be disposed.

[0148] The buffer wiring 183 is arranged on the planarization layer 146, and the metal pattern MT can be arranged between the inorganic insulating layer, i.e., the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145.

[0149] 9, the metal pattern MT may be formed of the same material as the source and drain electrodes of the transistor disposed between the second interlayer insulating layer 144 and the passivation layer 145. That is, the metal pattern MT may be formed of the same material in the same layer as the source and drain electrodes of the transistor.

[0150] However, the metal pattern MT is not limited to this, and the metal pattern MT may be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer 143 and the second interlayer insulating layer 144, or the metal pattern MT may be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer 142 and the first interlayer insulating layer 143.

[0151] A filler layer 190 and an upper substrate 112 may be sequentially disposed on the buffer wiring 183 and the planarization layer.

[0152] As described above, the display device according to an embodiment of the present invention may include anchor holes AH for fixing the buffer wiring 183. Therefore, even if the display device is repeatedly extended, the buffer wiring 183 will not peel off from the underlying components. Furthermore, because the buffer wiring 183 is fixed onto the first sub-plate pattern 123a through the anchor holes AH, the area in which the buffer wiring 183 can move freely is reduced. Therefore, the extension stress experienced by the buffer wiring 183 can be reliably reduced. As a result, the formation of the anchor holes AH in the display device according to an embodiment of the present invention can stably ensure the extension reliability of the display device.

[0153] During the manufacture of a display device, components are placed on a lower substrate, which is then lifted off and separated, and then a filler layer and an upper substrate are attached. As described above, when components placed on the lower substrate are lifted off, a problem occurs in that components placed on the lower substrate, such as buffer wiring, are removed. Therefore, in a display device according to an embodiment of the present invention, the buffer wiring is fixed through anchor holes, so that the display device is not damaged during lift-off. As a result, a display device according to an embodiment of the present invention can also achieve process stability.

[0154] Third Area Configuration FIG. 10 is an enlarged plan view of a third region of a display device according to an embodiment of the present invention. FIG. 11 is a cross-sectional view taken along the line XI-XI' shown in FIG. As shown in FIG. 10, in the third area A3, a plurality of power blocks PB constituting the power supply PS and power wiring 185 connecting the plurality of power blocks PB are arranged.

[0155] The plurality of power blocks PB are respectively formed on the plurality of third sub-plate patterns 123c spaced apart from one another. As described above, the third sub-plate patterns 123c may be arranged in an island shape spaced apart from one another in the first direction X and the second direction Y, and therefore the plurality of power blocks PB may also be arranged in an island shape spaced apart from one another in the first direction X and the second direction Y.

[0156] 10 shows a plurality of power blocks PB arranged in a 4×2 matrix on each of a plurality of third sub-board patterns 123c, but the arrangement of the power blocks PB is not limited to this and may be modified in various ways. For example, instead of only one power block PB being arranged on each third sub-board pattern 123c, a plurality of power blocks PB may be arranged in a matrix.

[0157] 11, each of the plurality of power blocks PB may include a plurality of power patterns PP arranged on different layers. Specifically, the plurality of power blocks PB may include a first power pattern PP1 and a second power pattern PP2 arranged on different layers.

[0158] On the third sub-plate pattern 123c arranged on the lower substrate 111, a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, and a passivation layer 145, which are inorganic insulating layers, and a planarization layer 146, which is an organic insulating layer, may be arranged.

[0159] The first power pattern PP1 may be disposed among the inorganic insulating layers, i.e., the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. The second power pattern PP2 may be disposed on the planarization layer 146.

[0160] 11, the first power pattern PP1 may be formed of the same material as the source and drain electrodes of the transistor disposed between the second interlayer insulating layer 144 and the passivation layer 145. That is, the first power pattern PP1 may be formed of the same material in the same layer as the source and drain electrodes of the transistor.

[0161] However, the first power pattern PP1 is not limited to this, and the first power pattern PP1 may be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer 143 and the second interlayer insulating layer 144, or the first power pattern PP1 may be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer 142 and the first interlayer insulating layer 143.

[0162] However, in FIG. 11, the power block PB is shown as being composed of only two power pattern layers PP1 and PP2, but this is not limited to this and the power block PB may be composed of three or more power pattern layers arranged on different layers.

[0163] A filler layer 190 and an upper substrate 112 may be sequentially disposed on the second power pattern PP2 and the planarization layer.

[0164] Meanwhile, the plurality of power wirings 185 connect the plurality of power blocks PB arranged in an island shape to each other, and the plurality of power wirings 185 include first power wirings 185a extending in a first direction X and second power wirings 185b extending in a second direction Y.

[0165] The multiple first power wirings 185a extending in the first direction X are arranged on the 3-1 sub-wiring pattern 124c-1 extending in the first direction X, and the multiple second power wirings 185b extending in the second direction Y are arranged on the 3-2 sub-wiring pattern 124c-2 extending in the second direction Y.

[0166] Furthermore, the first power wires 185a formed on the 3-1 sub-wiring pattern 124c-1 may have the same shape as the 3-1 sub-wiring pattern 124c-1, and the second power wires 185b formed on the 3-2 sub-wiring pattern 124c-2 may have the same shape as the 3-2 sub-wiring pattern 124c-2. Specifically, each of the first power wires 185a and the second power wires 185b has a bent shape. For example, each of the first power wires 185a and the second power wires 185b may have a sinusoidal wave shape. However, the shape of each of the first power wires 185a and the second power wires 185b is not limited thereto. For example, each of the first power wires 185a and the second power wires 185b may extend in a zigzag pattern or may have various other shapes, such as a plurality of diamond-shaped substrates connected at their vertices. Furthermore, in FIG. 10, six first power wires 185a are shown as forming a group to electrically connect a plurality of power blocks PB adjacent to each other in the first direction X, and three second power wires 185b are shown as forming a group to electrically connect a plurality of power blocks PB adjacent to each other in the second direction Y. However, the number and shape of each of the first power wires 185a and the second power wires 185b shown are merely examples, and the number and shape of each of the first power wires 185a and the second power wires 185b may be variously changed depending on the design.

[0167] 11, the plurality of first power wirings 185a and the plurality of second power wirings 185b may each include a plurality of power wiring layers arranged in different layers. Specifically, the plurality of first power wirings 185a may include a 1-1 power wiring and a 1-2 power wiring arranged in different layers. The plurality of second power wirings 185b may include a 2-1 power wiring 185b-1 and a 2-2 power wiring 185b-2 arranged in different layers.

[0168] Since FIG. 11 is a cross-sectional view of the second power wiring 185b, the interlayer structure of the second power wiring 185b will be described.

[0169] The 2-1 power wiring 185b-1 may be disposed on the 3-2 sub-wiring pattern 124c-2 disposed on the lower substrate 111. Then, a passivation layer 145 and a planarization layer 146 may be disposed on the 2-1 power wiring 185b-1, and the 2-2 power wiring 185b-2 may be disposed on the planarization layer 146.

[0170] The 2-1 power wiring 185b-1 may be made of the same material as the first power pattern PP1, and the 2-2 power wiring 185b-2 may be made of the same material as the second power pattern PP2.

[0171] 11, the 2-1 power wiring 185b-1 may be formed of the same material as the source electrode and drain electrode of the transistor. However, the 2-1 power wiring 185b-1 is not limited to this, and the 2-1 power wiring 185b-1 may be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer 143 and the second interlayer insulating layer 144, or the 2-1 power wiring 185b-1 may be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer 142 and the first interlayer insulating layer 143.

[0172] However, although FIG. 11 shows the second power wiring 185b as being composed of only two power wiring layers 185b-1 and 185b-2, the present invention is not limited to this and the second power wiring 185b may be composed of three or more power wiring layers arranged on different layers.

[0173] The interlayer structure of the first power wiring 185a is the same as the interlayer structure of the second power wiring 185b.

[0174] Specifically, the 1-1 power wiring may be disposed on the 3-1 sub-wiring pattern 124c-1 disposed on the lower substrate 111. Then, a passivation layer 145 and a planarization layer 146 may be disposed on the 1-1 power wiring, and the 1-2 power wiring may be disposed on the planarization layer 146.

[0175] The 1-1 power wiring may be made of the same material as the first power pattern PP1, and the 1-2 power wiring may be made of the same material as the second power pattern PP2.

[0176] However, although the first power wiring 185a is shown as being composed of only two power wiring layers, it is not limited to this and may be composed of three or more power wiring layers arranged on different layers of the first power wiring 185a.

[0177] As described above, the first-1 power wiring and the second-1 power wiring 185b-1 are made of the same material as the first power pattern PP1, and the first-1 power wiring, the second-1 power wiring 185b-1, and the first power pattern PP1 may be electrically connected to each other. Thus, a low-potential driving voltage may be applied to the first power patterns PP1 disposed on one side through the link wiring. The low-potential driving voltage is then stored in the first power pattern PP1 disposed on the other side through the first-1 power wiring and the second-1 power wiring 185b-1, and the low-potential driving voltage may be supplied to the plurality of pixels through the first-1 power wiring and the second-1 power wiring 185b-1.

[0178] The first-2 power wiring and the second-2 power wiring 185b-2 are made of the same material as the second power pattern PP2, and the first-2 power wiring, the second-2 power wiring 185b-2, and the second power pattern PP2 may be electrically connected to each other. Thus, a high-potential driving voltage may be applied to the second power patterns PP2 arranged on one side through the link wiring. The high-potential driving voltage is stored in the second power pattern PP2 arranged on the other side through the first-2 power wiring and the second-2 power wiring 185b-2, and the high-potential driving voltage may be supplied to the plurality of pixels through the first-2 power wiring and the second-2 power wiring 185b-2.

[0179] That is, as described above, a high potential driving voltage is supplied to the pixel through the 1-2 power wiring, the 2-2 power wiring 185b-2, and the second power pattern PP2, which are components arranged in a relatively upper layer in the power supply PS, and a low potential driving voltage is supplied to the pixel through the 1-1 power wiring, the 2-1 power wiring 185b-1, and the first power pattern PP1, which are components arranged in a relatively lower layer in the power supply PS.

[0180] However, without being limited thereto, among the first-2 power wiring, the second-2 power wiring 185b-2, and the second power pattern PP2, which are components arranged on a relatively upper layer in the power supply PS, a high-potential driving voltage may be applied to components arranged in one region through a link wiring, and a low-potential driving voltage may be applied to components arranged in another region of the first-2 power wiring, the second-2 power wiring 185b-2, and the second power pattern PP2 through a link wiring. The second power pattern PP2 arranged in another region is electrically connected to the first power pattern PP1 arranged on a relatively lower layer through a contact hole. Thus, a low-potential driving voltage is stored in the first-1 power wiring, the second-1 power wiring 185b-1, and the first power pattern PP1, and the low-potential driving voltage may be supplied to the pixel through the first-1 power wiring, the second-1 power wiring 185b-1, and the first power pattern PP1.

[0181] For example, as shown in FIG. 10, when power blocks PB are arranged in a 4×2 matrix, the second power pattern PP2 of the power block PB in a 2×2 matrix arranged relatively inside the third region A3 can receive a high potential driving voltage from the link wiring and apply the high potential driving voltage to the pixel through the power wiring 185.

[0182] Meanwhile, the second power patterns PP2 of the power blocks PB arranged in a 2×2 matrix, which are disposed relatively outside the third region A3, receive a low-potential driving voltage from the link wiring, and transmit the low-potential driving voltage through contact holes to the first power patterns PP1 of the power blocks PB arranged in a 4×2 matrix across the third region A3. The low-potential driving voltage can then be applied to the pixels through the power wiring 185 connected to the first power patterns PP1.

[0183] In the above case, a high potential driving voltage is applied to the 2×2 matrix-shaped power blocks PB arranged inside the third region A3, and a low potential driving voltage is applied to the 2×2 matrix-shaped power blocks PB arranged outside the third region A3, so the 2×2 matrix-shaped power blocks PB arranged inside the third region A3 and the 2×2 matrix-shaped power blocks PB arranged outside the third region A3 should not be electrically connected. Therefore, power wiring 185 does not need to be arranged between the 2×2 matrix-shaped power blocks PB arranged inside the third region A3 and the 2×2 matrix-shaped power blocks PB arranged outside the third region A3.

[0184] As described above, in the display device according to an embodiment of the present invention, the power supply PS may be formed on a plurality of third sub-plate patterns 123c spaced apart in an island shape. That is, the power supply PS itself, including the power blocks PB spaced apart in two axial directions of the power supply PS and the power wiring 185 connecting them, may extend not only in the first direction X but also in the second direction Y. Therefore, in an embodiment of the present invention, the non-display area NA of the display device may also be stretched in two axial directions. This may expand the application range of the stretchable display device and improve the usability of the stretchable display device. Furthermore, as the stretching direction of the stretchable display device is expanded, stretching stress in one direction may be significantly reduced. Therefore, the display device according to an embodiment of the present invention may have an improved stretch ratio. Furthermore, by applying different voltages to the upper and lower layers of the power supply of the display device, the power supply can apply various types of driving voltages even in a limited space. Furthermore, by connecting multiple power wirings of the power supply in parallel, it is possible to reduce or minimize the drop in the driving voltage to be transmitted.

[0185] Another embodiment of the present invention - additional power block The following describes in detail a display device 200 according to another embodiment of the present invention. The display device 200 according to the other embodiment of the present invention differs from the display device 100 according to the first embodiment of the present invention in terms of an additional power block arranged in the third region. Therefore, the same content between the display device according to the other embodiment of the present invention and the display device according to the first embodiment of the present invention will be omitted, and the above-mentioned differences will be described in detail.

[0186] FIG. 12 is an enlarged plan view of a third region of a display device according to another embodiment of the present invention.

[0187] FIG. 13 is a cross-sectional view taken along the line XIII-XIII' shown in FIG.

[0188] A display device 200 according to another embodiment of the present invention may further include a plurality of additional power blocks APB (or a plurality of auxiliary power blocks APB) arranged on the fourth sub-board pattern 123d (or the fourth sub-board structure 123d), and additional power wiring 186 connecting the additional power blocks APB to each other.

[0189] 12, in the third region of the non-display region of the display device 200 according to another embodiment of the present invention, not only are a plurality of power blocks PB constituting the power supply PS and power wiring 185 connecting the plurality of power blocks PB arranged, but also a plurality of additional power blocks APB and additional power wiring 186 connecting the additional power blocks APB and the additional power blocks APB may be arranged. In some embodiments, the plurality of additional power blocks APB and additional power wiring 186 are also part of the power supply circuit PS.

[0190] The additional power blocks APB are respectively formed on the fourth sub-plate patterns 123d spaced apart from one another. As described above, the fourth sub-plate patterns 123d may be disposed between the third sub-plate patterns 123c disposed in the third direction Z, Z'. The fourth sub-plate patterns 123d may also be disposed in an island shape spaced apart from one another in the first direction X and the second direction Y. Thus, the additional power blocks APB may also be disposed in an island shape spaced apart from one another in the first direction X and the second direction Y.

[0191] In other words, referring to FIG. 12, the multiple additional power blocks APB can be arranged between the multiple power blocks PB arranged in the third direction Z, Z', between the multiple first power wirings 185a, or between the multiple second power wirings 185b.

[0192] Since the above-mentioned fourth sub-plate pattern 123d is a component of the second plate pattern, the fourth sub-plate pattern 123d may also be a rectangular rigid pattern.

[0193] 12, one additional power block APB is shown on each fourth sub-plate pattern 123d, but the arrangement of the additional power blocks APB is not limited to this and may be modified in various ways. For example, instead of only one additional power block APB being arranged on each fourth sub-plate pattern 123d, multiple additional power blocks APB may be arranged in a matrix.

[0194] 13, each of the additional power blocks APB may include a plurality of additional power patterns APP1 and APP2 arranged on different layers. Specifically, the additional power blocks APB may include a first additional power pattern APP1 and a second additional power pattern APP2 arranged on different layers.

[0195] The first additional power pattern APP1 may be formed on the same layer and made of the same material as the first power pattern PP1, and the second additional power pattern APP2 may be formed on the same layer and made of the same material as the second power pattern PP2.

[0196] That is, the first additional power pattern APP1 may be arranged between the inorganic insulating layers, i.e., the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144 and the passivation layer 145, and the second additional power pattern APP2 may be arranged on the planarization layer 146.

[0197] For example, the first additional power pattern APP1 may be formed of the same material as the source and drain electrodes of a transistor disposed between the second interlayer insulating layer 144 and the passivation layer 145. That is, the first additional power pattern APP1 may be formed of the same material in the same layer as the source and drain electrodes of the transistor.

[0198] However, the first additional power pattern APP1 is not limited to this, and the first power pattern PP1 may be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer 143 and the second interlayer insulating layer 144, or the first additional power pattern APP1 may be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer 142 and the first interlayer insulating layer 143.

[0199] However, although FIG. 13 shows the additional power block APB as being composed of only two additional power pattern layers PP1 and PP2, this is not limited thereto, and the additional power block APB may be composed of three or more additional power pattern layers arranged on different layers.

[0200] Meanwhile, the power block PB and the additional power block APB are connected by a plurality of additional power wires 186. Since the power block PB and the additional power block APB are spaced apart from each other in the third direction Z, Z', the plurality of additional power wires 186 connecting the power block PB and the additional power block APB may also extend in the third direction Z, Z'.

[0201] The multiple additional power wirings 186 extending in the third direction Z, Z' can be disposed on the multiple fourth sub-wiring patterns 124d extending in the third direction Z, Z'.

[0202] Furthermore, the shape of the plurality of additional power wires 186 may be the same as the shape of the plurality of fourth sub-wiring patterns 124d. Specifically, the plurality of fourth sub-wiring patterns 124d and the plurality of additional power wires 186 each have a bent shape. For example, the plurality of fourth sub-wiring patterns 124d and the plurality of additional power wires 186 may each have a sinusoidal wave shape. However, the shape of the plurality of fourth sub-wiring patterns 124d and the plurality of additional power wires 186 is not limited thereto, and may have various other shapes, such as extending in a zigzag pattern or extending in a pattern of multiple diamond-shaped substrates connected at their vertices.

[0203] 13, each of the plurality of additional power wires 186 may include a plurality of power wiring layers disposed on different layers. Specifically, the plurality of additional power wires 186 may include a first additional power wire 186-1 and a second additional power wire 186-2 disposed on different layers.

[0204] A first additional power wiring 186-1 may be disposed on the fourth sub-wiring pattern 124d disposed on the lower substrate 111, and a passivation layer 145 and a planarization layer 146 may be disposed on the first additional power wiring 186-1, and a second additional power wiring 186-2 may be disposed on the planarization layer 146.

[0205] The first additional power wiring 186-1 may be made of the same material as the first additional power pattern APP1 and the first power pattern PP1, and the second additional power wiring 186-2 may be made of the same material as the first additional power pattern APP1 and the second power pattern PP2.

[0206] 13, the first additional power wiring 186-1 may be formed of the same material as the source electrode and drain electrode of the transistor. However, the first additional power wiring 186-1 is not limited thereto, and the first additional power wiring 186-1 may be formed of the same material as the intermediate metal layer disposed between the first interlayer insulating layer 143 and the second interlayer insulating layer 144, or the first additional power wiring 186-1 may be formed of the same material as the gate electrode of the transistor disposed between the gate insulating layer 142 and the first interlayer insulating layer 143.

[0207] However, although FIG. 13 shows the additional power wiring 186 as being composed of only two additional power wiring layers 186-1 and 186-2, the additional power wiring 186 is not limited to this, and may be composed of three or more power wiring layers arranged on different layers.

[0208] In a display device according to another embodiment of the present invention, components arranged on a relatively upper layer in the power supply PS may include not only the first-2 power wiring, the second-2 power wiring 185b-2, and the second power pattern PP2, but also the second additional power pattern APP2 and the second additional power wiring 186-2. That is, in this embodiment of the present invention, by including the second additional power pattern APP2 and the second additional power wiring 186-2, the area of ​​the components that store the high potential voltage may be increased. That is, in this embodiment of the present invention, the power supply may reduce or minimize the resistance of the components that store the high potential voltage, thereby reducing or minimizing the voltage drop of the high potential voltage.

[0209] Furthermore, components arranged on a relatively lower layer in the power supply PS may include not only the first-1 power wiring, the second-1 power wiring 185b-1, and the first power pattern PP1, but also the first additional power pattern APP1 and the first additional power wiring 186-1. That is, in another embodiment of the present invention, by further including the first additional power pattern APP1 and the first additional power wiring 186-1, the area of ​​the components that store the low-potential voltage may be increased. That is, in another embodiment of the present invention, the power supply may reduce or minimize the resistance of the components that store the low-potential voltage, thereby reducing or minimizing the voltage drop of the low-potential voltage.

[0210] That is, in the display device according to another embodiment of the present invention, the power supply may include an additional power block to reduce or minimize the drop in driving voltage, and thus a uniform voltage may be applied to all pixels of the display device according to another embodiment of the present invention, thereby achieving uniform image quality.

[0211] An embodiment of the present invention can also be described as follows. According to an aspect of the present invention, in order to solve the above-mentioned problems, a display device according to an embodiment of the present invention includes an extendable lower substrate including a display area and a non-display area; a pattern layer disposed on the lower substrate and including a plurality of first plate patterns and a plurality of first wiring patterns formed in the display area and a plurality of second plate patterns and a plurality of second wiring patterns formed in the non-display area; a plurality of pixels formed on the plurality of first plate patterns; a plurality of first connecting wires connecting the plurality of pixels; gate drivers formed on the plurality of second plate patterns; power supplies formed on the plurality of second plate patterns; a plurality of second connecting wires disposed in the non-display area; and an extendable upper substrate covering the gate drivers, the power supplies, and the plurality of pixels, wherein the non-display area includes a first region located outside the display area, a second region located outside the first region and in which a plurality of gate drivers are disposed, and a third region located outside the second region and in which a plurality of power supplies are disposed, and the plurality of second connecting wires disposed in the first region contact a metal pattern disposed in a layer different from the plurality of second connecting wires through anchor holes.

[0212] The plurality of second board patterns include a plurality of first sub-board patterns arranged in a first region, a plurality of second sub-board patterns arranged in a second region, and a plurality of third sub-board patterns arranged in a third region, and the plurality of second wiring patterns include a plurality of first sub-wiring patterns arranged in the first region, a plurality of second sub-wiring patterns arranged in the second region, and a plurality of third sub-wiring patterns arranged in the third region, and anchor holes may be formed on the plurality of first sub-board patterns.

[0213] According to another aspect of the present invention, each of the plurality of pixels includes a transistor having a gate electrode, a source electrode, and a drain electrode, and the metal pattern can be formed in the same layer as the source electrode and the drain electrode.

[0214] According to another aspect of the present invention, each of the plurality of pixels includes a transistor having a gate electrode, a source electrode, and a drain electrode, and the metal pattern can be formed in the same layer as the gate electrode.

[0215] According to another aspect of the present invention, the plurality of second sub-plate patterns may be spaced apart from one another only in the second direction, and the plurality of third sub-plate patterns may be spaced apart from one another in both the first and second directions.

[0216] According to another feature of the present invention, multiple stages constituting a gate driver may be arranged on multiple second sub-board patterns, and multiple power blocks constituting a power supply may be arranged on multiple third sub-board patterns.

[0217] According to another aspect of the present invention, the plurality of power blocks may include a first power pattern and a second power pattern arranged on different layers.

[0218] According to another aspect of the present invention, each of the plurality of pixels includes a transistor having a gate electrode, a source electrode, and a drain electrode, the first power pattern may be formed of the same material as the source electrode and the drain electrode, and the second power pattern may be formed of the same material as the second connecting wire.

[0219] According to another feature of the present invention, the plurality of third sub-wiring patterns may include a 3-1 sub-wiring pattern connecting a plurality of third sub-board patterns spaced apart in a first direction and a 3-2 sub-wiring pattern connecting a plurality of third sub-board patterns spaced apart in a second direction.

[0220] According to another feature of the present invention, the plurality of second connecting wires arranged in the third region connect the plurality of power blocks, and the plurality of second connecting wires arranged in the third region may include a first power wire arranged on the 3-1 sub-wiring pattern and a second power wire arranged on the 3-2 sub-wiring pattern.

[0221] According to another feature of the present invention, the first power wiring may include a 1-1 power wiring and a 1-2 power wiring arranged on different layers, and the second power wiring may include a 2-1 power wiring and a 2-2 power wiring arranged on different layers.

[0222] According to another feature of the present invention, the 1-1 power wiring and the 2-1 power wiring may be made of the same material as the first power pattern, and the 1-2 power wiring and the 2-2 power wiring may be made of the same material as the second power pattern.

[0223] According to another aspect of the present invention, the display device may further include a plurality of additional power blocks disposed between the plurality of power blocks spaced apart in the third direction.

[0224] According to another aspect of the present invention, the plurality of additional power blocks may include a first additional power pattern and a second additional power pattern disposed on different layers.

[0225] According to another aspect of the present invention, the first additional power pattern may be electrically connected to the first power pattern, and the second additional power pattern may be electrically connected to the second power pattern.

[0226] According to another aspect of the present invention, in order to solve the above-mentioned problems, a display device according to another embodiment of the present invention includes a ductile substrate, a plurality of rigid patterns formed on the ductile substrate, a plurality of pixels formed on top of a plurality of first plate patterns spaced apart from each other among the plurality of rigid patterns, and a power supply formed on top of some of a plurality of second plate patterns spaced apart from each other among the plurality of rigid patterns, wherein the power supply supplies driving voltages to the plurality of pixels and may be composed of power blocks spaced apart from each other in a first direction and a second direction.

[0227] According to another feature of the present invention, the plurality of power blocks may include a first power pattern and a second power pattern arranged on different layers.

[0228] According to another aspect of the present invention, different driving voltages may be applied to the first power pattern and the second power pattern.

[0229] According to another aspect of the present invention, the plurality of power blocks may be connected by a plurality of first power wires extending in a first direction and a plurality of second power wires extending in a second direction.

[0230] According to another feature of the present invention, the first power wiring may include a 1-1 power wiring and a 1-2 power wiring arranged on different layers, and the second power wiring may include a 2-1 power wiring and a 2-2 power wiring arranged on different layers.

[0231] According to another aspect of the present invention, the 1-1 power wiring and the 2-1 power wiring may be electrically connected to the first power pattern, and the 1-2 power wiring and the 2-2 power wiring may be electrically connected to the second power pattern.

[0232] According to another aspect of the present invention, the power supply may further include a plurality of additional power blocks disposed between the plurality of first power wirings and between the plurality of second power wirings.

[0233] According to another aspect of the present invention, the plurality of additional power blocks may include a first additional power pattern and a second additional power pattern disposed on different layers.

[0234] According to another aspect of the present invention, the first additional power pattern may be electrically connected to the first power pattern, and the second additional power pattern may be electrically connected to the second power pattern.

[0235] According to another aspect of the present invention, the display device further includes a gate driver between the power supply and the plurality of pixels, the gate driver and the plurality of pixels being connected by a plurality of buffer lines, and the plurality of buffer lines may be fixed to a metal layer formed in a layer different from the plurality of buffer lines through anchor holes.

[0236] According to another aspect of the present invention, the anchor holes may be formed on other portions of the second plate patterns spaced apart from one another among the rigid patterns.

[0237] Although the embodiments of the present invention have been described in more detail, the present invention is not necessarily limited to these embodiments and may be variously modified within the scope of the technical concept of the present invention. Therefore, the embodiments disclosed herein are for illustrative purposes only and do not limit the technical concept of the present invention. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not restrictive. The scope of the present invention should be interpreted by the scope of the following claims, and all technical concepts within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

[0238] The various embodiments described above can be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent literature referenced herein and / or listed in the Application Data Sheets are incorporated herein by reference in their entirety. Aspects of the embodiments can be modified, as necessary, to incorporate concepts from various patents, applications, and publications to provide further embodiments.

[0239] These and other variations can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but rather to include all possible embodiments, along with the full range of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. flexible substrate; a plurality of rigid patterns formed on the flexible substrate, the rigid patterns including a plurality of first plate patterns and a plurality of second plate patterns; a plurality of pixels formed on the first plate patterns spaced apart from one another among the plurality of rigid patterns; and a power supply formed on an upper portion of some of the second plate patterns spaced apart from each other among the rigid patterns; the power supply supplies a driving voltage to the plurality of pixels and is composed of power blocks spaced apart from each other in a first direction and a second direction; the plurality of power blocks are coupled by a plurality of first power wirings in the first direction and a plurality of second power wirings in the second direction; the first power wiring includes a 1-1 power wiring layer and a 1-2 power wiring layer that are arranged in different layers from each other; The second power wiring includes a 2-1 power wiring layer and a 2-2 power wiring layer that are arranged in different layers.

2. flexible substrate; a plurality of rigid patterns formed on the flexible substrate, the rigid patterns including a plurality of first plate patterns and a plurality of second plate patterns; a plurality of pixels formed on the first plate patterns spaced apart from one another among the plurality of rigid patterns; and A display device including a power supply formed on an upper portion of a part of the plurality of second plate patterns spaced apart from each other among the plurality of rigid patterns, the power supply supplies a driving voltage to the plurality of pixels and is composed of power blocks spaced apart from each other in a first direction and a second direction; the plurality of power blocks include a first power pattern layer and a second power pattern layer disposed on different layers; The display device further includes a plurality of additional power blocks connected to the plurality of power blocks and disposed between the plurality of first power wirings and the plurality of second power wirings.

3. The display device of claim 2 , wherein different driving voltages are applied to the first power pattern layer and the second power pattern layer.

4. The plurality of power blocks include a first power pattern layer and a second power pattern layer arranged on different layers from each other; the first-1 power wiring layer and the second-1 power wiring layer are electrically connected to the first power pattern layer; 2. The display device of claim 1, wherein the first-second power wiring layer and the second-second power wiring layer are electrically connected to the second power pattern layer.

5. The plurality of additional power blocks include: The display device according to claim 2 , further comprising a first additional power pattern layer and a second additional power pattern layer disposed on different layers.

6. the first additional power pattern layer is electrically connected to the first power pattern layer; The display device of claim 5 , wherein the second additional power pattern layer is electrically connected to the second power pattern layer.

7. a gate driver between the power supply and the plurality of pixels; the gate driver and the plurality of pixels are coupled by a plurality of buffer lines; 3. The display device according to claim 1, wherein the plurality of buffer wirings are fixed to a metal layer formed in a different layer from the plurality of buffer wirings through anchor holes.

8. The display device of claim 7 , wherein the anchor hole is formed on another part of a plurality of second plate patterns spaced apart from each other among the plurality of rigid patterns.

9. a flexible substrate having a display area thereon and a non-display area adjacent to the display area; a plurality of first plate structures on the display area of ​​the flexible substrate; a plurality of second plate structures on the non-display area of ​​the flexible substrate, each of the plurality of second plate structures being spaced apart from one another; at least one wiring pattern coupled to at least one of the plurality of second plate structures; at least one buffer wiring on the at least one of the plurality of second plate structures; and at least one anchor hole on the at least one second plate structure electrically connecting the at least one buffer wiring and at least one of the plurality of second plate structures, the at least one anchor hole fixing the at least one buffer wiring on the at least one of the plurality of second plate structures; Equipped with the non-display area of ​​the flexible substrate includes a first non-display area, a second non-display area, and a third non-display area, the first non-display area being between the display area and the second non-display area, and the second non-display area being between the first non-display area and the third non-display area; the first non-display area includes the at least one second plate structure having the at least one anchor hole thereon; the third non-display area includes a second group of the plurality of second plate structures having power supply circuits thereon, each of the second plate structures of the second group being spaced apart from one another and electrically connected via a plurality of power wirings; the display device further comprising at least one sub-board structure in the third non-display area, the at least one sub-board structure being disposed in an area of ​​the second board structure not occupied by the second group and the plurality of power wirings; an additional power block on the at least one sub-plate structure; and a display device comprising additional power wiring coupled to the additional power block, the additional power wiring including a first additional power pattern layer and a second additional power pattern layer;

10. 10. The display device according to claim 9, wherein the conductive pattern on the at least one second plate structure, the conductive pattern arranged from the buffer wiring, is electrically connected to the buffer wiring via the anchor hole.

11. The display device of claim 10 , wherein the conductive pattern is formed of the same material as a source electrode or a drain electrode of a driving transistor disposed in the display region of the flexible substrate.

12. 11. The display device of claim 10, wherein the second non-display area includes a first group of the plurality of second plate structures having driving circuits thereon, and each of the second plate structures of the first group is spaced apart from one another and electrically connected via a plurality of first connecting wires.

13. the plurality of power wirings include a first power pattern layer and a second power pattern layer, each of which is disposed on a different layer; 10. The display device of claim 9, wherein in operation, different voltages are applied to the first power pattern layer and the second power pattern layer.

14. The display device of claim 13 , wherein the additional power wiring is coupled to the second group of second plate structures adjacent to the at least one sub-plate structure.

15. the first additional power pattern layer and the second additional power pattern layer are disposed on different layers, 15. The display device of claim 14, wherein the first additional power pattern layer is formed of the same material as the first power pattern layer, and the second additional power pattern layer is formed of the same material as the second power pattern layer.

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