Radiation Image Detector

Abstract

To provide a radiographic image detector which includes a plurality of control circuits and enables the control circuits to be stably supplied with electric power.SOLUTION: An electronic cassette has a detection panel (light detection substrate) in which pixels accumulating electric charges according to the radiation are arrayed. The electronic cassette comprises: two gate control circuits which control the operation of a gate drive circuit; a power source circuit which supplies power to the gate control circuits; first wiring; and second wiring. The first wiring connects the power source circuit to each of the two gate control circuits and supplies the electric power from the electric power source circuit to each of the two gate control circuits. The second wiring connects the two gate control circuits to each other. The second wiring distributes the electric power from the electric power source circuit supplied to one of the two gate control circuits to the other.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The technology of the present disclosure relates to a radiation image detector. [Background technology]

[0002] Radiation image detectors are known that have a detection panel on which pixels that accumulate electric charges in response to radiation are arranged. Detection panels are also called FPDs (Flat Panel Detectors). Radiation image detectors contain various circuits, such as a gate drive circuit, a gate control circuit that controls the operation of the gate drive circuit, a readout circuit, a readout control circuit that controls the operation of the readout circuit, and a power supply circuit that supplies power to these circuits. The gate drive circuit is a circuit that provides gate pulses to the pixel switching elements to read out electric charges from the pixels. The readout circuit is a circuit that converts electric charges from the pixels into analog voltage signals and then converts the analog voltage signals into digital signals to output a radiation image.

[0003] Patent Document 1 describes a radiation image detector having a plurality of gate drive circuits and a plurality of readout circuits. The plurality of gate drive circuits are each responsible for a group of equally divided rows of pixels in the detection panel (for example, 240 rows obtained by dividing 2880 rows into 12 equal parts). Similarly, the plurality of readout circuits are each responsible for a group of equally divided columns of pixels in the detection panel (for example, 144 columns obtained by dividing 2304 columns into 16 equal parts). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2019 / 004233 Summary of the Invention [Problem to be solved by the invention]

[0005] When multiple gate drive circuits and multiple readout circuits are provided as in Patent Document 1, the operational control of the multiple gate drive circuits or multiple readout circuits may be shared among multiple control circuits (multiple gate control circuits or multiple readout control circuits) to reduce the control burden. For example, when the operational control of multiple gate drive circuits is shared among two control circuits, one control circuit is provided to handle the gate drive circuits for the upper half of the pixel rows of the detection panel, and the other control circuit is provided to handle the gate drive circuits for the lower half. When multiple control circuits are provided in this way, power is supplied from the power supply circuit to each of the multiple control circuits, which can lead to unstable power supply.

[0006] One embodiment of the technique of the present disclosure provides a radiation image detector capable of stably supplying power to a plurality of control circuits. [Means for solving the problem]

[0007] The radiation image detector of the present disclosure is a radiation image detector having a detection panel in which pixels that accumulate electric charges in response to radiation are arranged, and is equipped with a plurality of control circuits that control the operation of the detection panel, a power supply circuit that supplies power to the plurality of control circuits, a first wiring that connects the power supply circuit to each of the plurality of control circuits and supplies power from the power supply circuit to each of the plurality of control circuits, and at least one second wiring that connects at least two of the plurality of control circuits.

[0008] The control circuit preferably has a first power supply receiving terminal to which the first wiring is connected and a second power supply receiving terminal to which the second wiring is connected, and the first power supply receiving terminal and the second power supply receiving terminal are connected in series.

[0009] It is preferable that the shape is rectangular in plan view, and that the length of the long side is longer than 431.8 mm.

[0010] The length of one second wiring is preferably shorter than the total length of the first wirings.

[0011] The second wiring is preferably connected directly to the control circuit without an intervening connecting component.

[0012] The control circuit is preferably mounted on a flexible substrate.

[0013] The control circuit is preferably a gate control circuit that controls the operation of a gate drive circuit that applies a gate pulse to a switching element of the pixel for reading out charge from the pixel. [Effects of the Invention]

[0014] According to the technique of the present disclosure, it is possible to provide a radiation image detector that can stably supply power to a plurality of control circuits. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 2 is a perspective view of an electronic cassette. [Figure 2] FIG. 2 is a plan view of the electronic cassette. [Figure 3] FIG. 2 is a diagram showing various circuit boards attached to the rear surface of the base. [Figure 4] FIG. 2 is a diagram showing the connection relationships of various circuits. [Figure 5] FIG. 2 is a diagram showing the connection relationship between a power supply circuit and a gate control circuit. [Figure 6] FIG. 10 is a diagram showing the flow of power during operation of the upper half of the gate drive circuit. [Figure 7] FIG. 10 is a diagram showing the flow of power during operation of the lower half of the gate drive circuit. [Figure 8] 10A and 10B are diagrams illustrating a method of connecting a second wire and a second power supply receiving terminal. [Figure 9] FIG. 2 is a diagram showing a configuration of a photodetector substrate. [Figure 10] FIG. 2 is a diagram illustrating a configuration of a read circuit. [Figure 11] FIG. 10 is a diagram illustrating another example of the connection relationship between the power supply circuit and the gate control circuit. [Figure 12] FIG. 10 is a diagram showing a second embodiment in which the detection panel is bent into an arc shape. DETAILED DESCRIPTION OF THE INVENTION

[0016] [First embodiment] As an example, as shown in FIG. 1, an electronic cassette 10 is a portable radiation image detector that outputs a radiation image corresponding to radiation that has passed through a subject. The electronic cassette 10 is used by being housed in a holder on an imaging table installed in a radiography room in a medical facility. The electronic cassette 10 can also be removed from the holder on the imaging table and used by being held by a subject or by being inserted under a subject lying supine on a bed in a hospital room. The electronic cassette 10 is an example of a "radiation image detector" according to the technology of the present disclosure.

[0017] The electronic cassette 10 has a housing 11 that is flat, box-shaped (rectangular in plan view). The housing 11 is made of conductive metal or resin. Therefore, the housing 11 also functions as an electromagnetic shield to prevent electromagnetic noise from entering the interior of the electronic cassette 10 and from radiating electromagnetic noise from the electronic cassette 10 to the outside. A rectangular radiation-transmitting plate 12 that is slightly smaller than the housing 11 is attached to the front of the housing 11, where radiation is incident. The radiation-transmitting plate 12 is made of, for example, a carbon material that is lightweight, highly rigid, and highly radiation-transmitting.

[0018] The housing 11 houses a detection panel 13. The detection panel 13 is attached to a rectangular metal base 14. The detection panel 13 is composed of a scintillator 15 and a photodetector substrate 16, both of which have approximately the same size as the radiation transmitting plate 12.

[0019] The scintillator 15 and photodetector substrate 16 are stacked in this order when viewed from the front side of the housing 11 where radiation is incident. The scintillator 15 contains a phosphor such as CsI:Tl (thallium-activated cesium iodide) or GOS (Gd2O2S:Tb, terbium-activated gadolinium oxysulfide), and converts incident radiation into visible light and emits it. The photodetector substrate 16 has a configuration in which multiple pixels 60 (see FIG. 9) are arranged on a single TFT (Thin Film Transistor) active matrix substrate, and detects the visible light emitted from the scintillator 15 and converts it into an electrical signal.

[0020] The scintillator 15 and the photodetector substrate 16 may be stacked in this order when viewed from the front side: photodetector substrate 16, scintillator 15. Furthermore, the detection panel 13 may be a direct conversion type that directly converts radiation into an electrical signal, rather than an indirect conversion type in this example in which radiation converted into visible light by the scintillator 15 is converted into an electrical signal by the photodetector substrate 16.

[0021] Although not shown, a battery and an antenna are built into the housing 11. When wireless communication with an external device is performed via the antenna, the electronic cassette 10 is powered by the battery and can be used wirelessly.

[0022] 2, the length LSL of the long side 20 of the housing 11 is, for example, 787.4 mm (≈31 inches). In contrast, the length SSL of the short side 21 of the housing 11 is, for example, 431.8 mm (≈17 inches). In other words, the length LSL of the long side 20 is longer than 431.8 mm.

[0023] As shown in FIG. 3 as an example, a gate drive circuit 25, a gate control circuit board 26A, a gate control circuit board 26B, a readout circuit 27, a readout control circuit board 28A, a readout control circuit board 28B, and a power supply circuit board 29 are mounted on the back surface of the base 14. A gate control circuit 30A is mounted on the gate control circuit board 26A, and a gate control circuit 30B is mounted on the gate control circuit board 26B. A readout control circuit 31A is mounted on the readout control circuit board 28A, and a readout control circuit 31B is mounted on the readout control circuit board 28B. A power supply circuit 32 is mounted on the power supply circuit board 29. Ground terminals (not shown) of the gate control circuits 30A, 30B, 31A, 31B, and 32 are connected to the base 14. In the following description, the gate control circuits 30A and 30B may be collectively referred to as gate control circuits 30. Similarly, the readout control circuits 31A and 31B may be collectively referred to as readout control circuits 31.

[0024] The gate drive circuit 25 is a circuit that applies a gate pulse to the TFT 62 (see FIG. 9) of the pixel 60 to read out electric charge from the pixel 60. The gate drive circuit 25 is an integrated circuit (IC). There are multiple gate drive circuits 25, 12 in this example, and they are arranged at equal intervals along one of the two long sides 33 of the base 14.

[0025] Gate control circuit boards 26A and 26B are mounted near the long side 33 on which the gate drive circuits 25 are arranged. Gate control circuit board 26A is connected to six gate drive circuits 25 in the upper half of long side 33. Gate control circuit 30A controls the operation of these six gate drive circuits 25 in the upper half. Conversely, gate control circuit board 26B is connected to six gate drive circuits 25 in the lower half of long side 33. Gate control circuit 30B controls the operation of these six gate drive circuits 25 in the lower half. When one of the six gate drive circuits 25 in the upper half and the six gate drive circuits 25 in the lower half, and therefore gate control circuits 30A and 30B, is operating, the other is not operating. More specifically, when the six gate drive circuits 25 in the upper half are operating due to gate control circuit 30A, gate control circuit 30B is not operating, and when the six gate drive circuits 25 in the lower half are operating due to gate control circuit 30B, gate control circuit 30A is not operating.

[0026] The readout circuit 27 is a circuit that converts the electric charges from the pixels 60 into analog voltage signals, and then converts the analog voltage signals into digital signals to output a radiographic image. The readout circuits 27 are also integrated circuits, like the gate drive circuits 25. There are 12 readout circuits 27, like the gate drive circuits 25, and they are arranged at equal intervals on one of the two short sides 34 of the base 14.

[0027] Readout control circuit boards 28A and 28B are attached at positions close to the short side 34 on which the readout circuits 27 are arranged. Six readout circuits 27 in the right half of the short side 34 (the left half when viewed from the front surface of the base 14) are connected to readout control circuit board 28A. Readout control circuit 31A controls the operation of these six readout circuits 27 in the right half. In contrast, six readout circuits 27 in the left half of the short side 34 (the right half when viewed from the front surface of the base 14) are connected to readout control circuit board 28B. Readout control circuit 31B controls the operation of these six readout circuits 27 in the left half. Unlike the case of gate drive circuit 25, the six readout circuits 27 in the right half and the six readout circuits 27 in the left half, and therefore readout control circuits 31A and 31B, operate simultaneously.

[0028] The power supply circuit board 29 is mounted to the right of the gate control circuit board 26B and above the readout control circuit boards 28A and 28B. The power supply circuit 32 supplies power to each of the circuits 25, 27, 30A, 30B, 31A, and 31B.

[0029] 4, the gate control circuit 30A has a first power supply receiving terminal 40A and a second power supply receiving terminal 41A. The gate control circuit 30B has a first power supply receiving terminal 40B and a second power supply receiving terminal 41B. The read control circuit 31A has a power supply receiving terminal 42A, and the read control circuit 31B has a power supply receiving terminal 42B. The power supply circuit 32 has four power supply terminals 43.

[0030] One end of a first wire 44A is connected to a first power supply receiving terminal 40A of the gate control circuit 30A. The other end of the first wire 44A is connected to a power supply terminal 43 of the power supply circuit 32. Similarly, one end of a first wire 44B is connected to a first power supply receiving terminal 40B of the gate control circuit 30B. The other end of the first wire 44B is connected to the power supply terminal 43 of the power supply circuit 32. Power from the power supply circuit 32 is supplied to the gate control circuit 30A and the gate drive circuit 25 by the first wire 44A. Furthermore, power from the power supply circuit 32 is supplied to the gate control circuit 30B and the gate drive circuit 25 by the first wire 44B.

[0031] One end of the second wiring 45AB is connected to the second power supply receiving terminal 41A of the gate control circuit 30A. The other end of the second wiring 45AB is connected to the second power supply receiving terminal 41B of the gate control circuit 30B. That is, the gate control circuits 30A and 30B are connected by the second wiring 45AB. The length of the second wiring 45AB is sufficiently shorter than the combined length of the first wiring 44A and 44B. The second power supply receiving terminal 41A of the gate control circuit 30A and the second power supply receiving terminal 41B of the gate control circuit 30B are provided at opposing ends of the gate control circuits 30A and 30B to minimize the length of the second wiring 45AB. The gate control circuit 30A and the gate control circuit 30B are an example of a "control circuit" according to the technology of the present disclosure.

[0032] One end of a wire 46A is connected to a power supply receiving terminal 42A of the read control circuit 31A. The other end of the wire 46A is connected to a power supply terminal 43 of the power supply circuit 32. Similarly, one end of a wire 46B is connected to a power supply receiving terminal 42B of the read control circuit 31B. The other end of the wire 46B is connected to the power supply terminal 43 of the power supply circuit 32. Power from the power supply circuit 32 is supplied to the read control circuit 31A and the read circuit 27 by the wire 46A. Furthermore, power from the power supply circuit 32 is supplied to the read control circuit 31B and the read circuit 27 by the wire 46B.

[0033] As shown in FIG. 5 as an example, in gate control circuit 30A, first power supply receiving terminal 40A and second power supply receiving terminal 41A are connected in series. Similarly, in gate control circuit 30B, first power supply receiving terminal 40B and second power supply receiving terminal 41B are connected in series. Therefore, as shown in FIG. 6 as an example, when the upper half of gate drive circuit 25 is operating, i.e., when gate control circuit 30A is operating, power supplied from power supply circuit 32 to gate control circuit 30B is directed to gate control circuit 30A via second wiring 45AB. Conversely, as shown in FIG. 7 as an example, when the lower half of gate drive circuit 25 is operating, i.e., when gate control circuit 30B is operating, power supplied from power supply circuit 32 to gate control circuit 30A is directed to gate control circuit 30B via second wiring 45AB.

[0034] As an example, as shown in FIG. 8 , gate control circuit board 26A has an insertion hole 50A that leads to second power supply receiving terminal 41A. Similarly, gate control circuit board 26B has an insertion hole 50B that leads to second power supply receiving terminal 41B. Conductor 51A at one end of second wiring 45AB is inserted into insertion hole 50A. Conductor 51B at the other end of second wiring 45AB is inserted into insertion hole 50B. Conductor 51A is electrically connected to second power supply receiving terminal 41A with solder 52. Similarly, conductor 51B is electrically connected to second power supply receiving terminal 41B with solder 52. In other words, second wiring 45AB is a jumper wire that connects second power supply receiving terminals 41A and 41B, and is directly connected to gate control circuits 30A and 30B without using connecting parts such as connectors. Instead of solder 52, conductive paste such as silver paste may be used to connect conductor 51A to second power supply receiving terminal 41A, and conductor 51B to second power supply receiving terminal 41B.

[0035] As shown in FIG. 9 , the photodetector substrate 16 has a configuration in which a plurality of pixels 60 are arranged in a two-dimensional matrix along mutually orthogonal X and Y directions. The X direction is along the short sides 21 and 34, and the Y direction is along the long sides 20 and 33. If the number of pixels 60 arranged in the X direction is M and the number of pixels 60 arranged in the Y direction is N, M and N are integers of 2 or greater, e.g., M=2304 and N=4320. As is well known, each pixel 60 includes a photoelectric conversion unit 61 that generates and accumulates electric charges (electron-hole pairs) in response to incident visible light, and a TFT 62 that serves as a switching element for controlling the accumulation of electric charges in the photoelectric conversion unit 61 and the readout of electric charges from the photoelectric conversion unit 61. The photoelectric conversion unit 61 includes, for example, a PIN (P-Intrinsic-N) type semiconductor layer, an upper electrode disposed above the semiconductor layer, and a lower electrode disposed below the semiconductor layer. A bias voltage is applied to the upper electrode. The lower electrode is connected to the drain electrode of the TFT 62 .

[0036] The photodetector substrate 16 is formed with N scanning lines 63 extending parallel to the X direction and M signal lines 64 extending parallel to the Y direction. The N scanning lines 63 and M signal lines 64 are arranged in a grid pattern. Pixels 60 are arranged at the intersections of the scanning lines 63 and the signal lines 64. Specifically, in each pixel 60, a gate electrode of a TFT 62 is connected to the scanning line 63, and a source electrode of the TFT 62 is connected to the signal line 64. Each scanning line 63 is commonly connected to M pixels 60 in one row along the X direction. Each signal line 64 is commonly connected to N pixels 60 in one column along the Y direction. The scanning lines 63 are connected to a gate drive circuit 25. The signal lines 64 are connected to a readout circuit 27.

[0037] The 12 gate drive circuits 25 are responsible for a group of rows obtained by equally dividing the rows of pixels 60 (here, 360 rows obtained by dividing 4,320 rows into 12 equal parts). For example, of the six gate drive circuits 25 connected to the gate control circuit 30A, the first gate drive circuit 25 is connected to the scanning lines 63 of rows 1 to 360, and the second gate drive circuit 25 is connected to the scanning lines 63 of rows 361 to 720. Of the six gate drive circuits 25 connected to the gate control circuit 30B, the first gate drive circuit 25 is connected to the scanning lines 63 of rows 2,161 to 2,520, and the sixth gate drive circuit 25 is connected to the scanning lines 63 of rows 3,961 to 4,320. In other words, one gate drive circuit 25 is responsible for reading out electric charges from 360 rows of pixels 60.

[0038] The 12 readout circuits 27 are each responsible for a group of columns obtained by equally dividing the columns of pixels 60, in this case 192 columns obtained by equally dividing 2,304 columns in this case. For example, of the six readout circuits 27 connected to the readout control circuit 31A, the first readout circuit 27 is connected to the signal lines 64 of the 1st to 192nd columns, and the second readout circuit 27 is connected to the signal lines 64 of the 193rd to 384th columns. In other words, one readout circuit 27 is responsible for converting the charges from the pixels 60 of 192 columns into digital signals.

[0039] Under the control of gate control circuits 30A and 30B, the gate drive circuit 25 outputs a gate pulse to a scanning line 63. The gate pulse is uniformly applied to the gate electrodes of all TFTs 62 of the M pixels 60 connected to the scanning line 63. The TFTs 62 are turned on when the voltage of the gate pulse is at a high level, and turned off when the voltage of the gate pulse is at a low level. The time during which the TFTs 62 are in the on state is determined by the pulse width of the gate pulse. When the TFTs 62 are turned on, the electric charge accumulated in the photoelectric conversion units 61 of the pixels 60 is input to the readout circuit 27 via the signal line 64.

[0040] 10, the readout circuit 27 includes a charge amplifier 70, an amplifier 71, a CDS (Correlated Double Sampling) circuit (simply referred to as CDS in FIG. 10) 72, a multiplexer 73, and an A / D (Analog / Digital) converter 74. One charge amplifier 70, one amplifier 71, and one CDS circuit 72 are provided for each signal line 64, totaling 192 in this example.

[0041] Charge amplifier 70 integrates the electric charges input from signal line 64, converts the integrated value into an analog voltage signal, and outputs it. Charge amplifier 70 is composed of an operational amplifier 75, a capacitor 76, and a reset switch 77. Capacitor 76 and reset switch 77 are connected in parallel between the input terminal and output terminal of operational amplifier 75. Signal line 64 is connected to the input terminal of operational amplifier 75, and amplifier 71 is connected to the output terminal of operational amplifier 75.

[0042] The output terminal of the operational amplifier 75 for each column is connected to the input side of a multiplexer 73 via an amplifier 71 and a CDS circuit 72. An A / D converter 74 is connected to the output side of the multiplexer 73. The amplifier 71 amplifies the analog voltage signal at a predetermined amplification factor. The CDS circuit 72 removes reset noise components caused by the reset switch 77 by performing well-known correlated double sampling on the amplified analog voltage signal. The amplifier 71 is not limited to being provided between the charge amplifier 70 and the CDS circuit 72, and may be provided between the CDS circuit 72 and the A / D converter 74, for example, between the CDS circuit 72 and the multiplexer 73.

[0043] The multiplexer 73 sequentially selects the 192 connected CDS circuits 72, thereby sequentially inputting the analog voltage signals after correlated double sampling to the A / D converter 74. The A / D converter 74 sequentially converts the analog voltage signals input from the multiplexer 73 into digital signals and outputs the converted digital signals to the readout control circuit 31. The readout control circuit 31 has an image memory for one frame (not shown), and stores digital signals based on the charges accumulated in the photoelectric conversion units 61 of each pixel 60 as a radiographic image.

[0044] The gate control circuit 30 and the readout control circuit 31 cause the photodetector substrate 16 to perform one of an accumulation operation, an image detection operation, and a charge readout operation, thereby causing the photodetector substrate 16 to output a radiographic image. The accumulation operation is an operation that accumulates charges in the photoelectric conversion unit 61 according to the amount of incident radiation. During the accumulation operation, the gate control circuit 30 does not input a gate pulse from the gate drive circuit 25 to the TFT 62, turning the TFT 62 off. Thus, while the TFT 62 is in the off state, charges are accumulated in the photoelectric conversion unit 61.

[0045] The image detection operation is an operation of detecting, as a radiographic image, digital signals based on the charges accumulated in the photoelectric conversion units 61 during the accumulation operation. In the image detection operation, the gate control circuit 30 causes the gate drive circuit 25 to sequentially generate gate pulses that simultaneously turn on all of the TFTs 62 in the same row, thereby activating the scanning lines 63 row by row. When the TFTs 62 for one row are turned on, the charges accumulated in the photoelectric conversion units 61 of the pixels 60 for one row are input to the readout circuit 27 via the signal lines 64 for each column. As described above, in the readout circuit 27, the charges for one row are converted into analog voltage signals by the charge amplifier 70, and the analog voltage signals are further converted into digital signals by the A / D converter 74.

[0046] When the charge amplifier 70 outputs analog voltage signals for one row, the readout control circuit 31 turns on the reset switch 77 of the charge amplifier 70, thereby resetting the charge accumulated in the capacitor 76. After resetting the charge amplifier 70 in this manner, the gate control circuit 30 causes the gate drive circuit 25 to output a gate pulse to the scanning line 63 of the next row, causing the charge accumulated in the photoelectric conversion units 61 of the pixels 60 in the next row to be input to the readout circuit 27. The gate control circuit 30 and the readout control circuit 31 cause the photodetector substrate 16 to repeat these operations, thereby converting the charge accumulated in the photoelectric conversion units 61 of the pixels 60 in all rows into digital signals.

[0047] The charge readout operation is an operation of reading out unnecessary charges, such as dark charges generated regardless of whether radiation is irradiated or not, and residual charges from the previous radiography, from the photoelectric conversion unit 61. In this example, the gate control circuit 30 and readout control circuit 31 perform the charge readout operation using a sequential readout method in which unnecessary charges are read out row by row, similar to the image detection operation described above. Specifically, the gate control circuit 30 causes the gate drive circuit 25 to generate gate pulses to each scanning line 63, row by row, to turn on the TFTs 62, row by row. As a result, the unnecessary charges accumulated in the photoelectric conversion unit 61 are input to the readout circuit 27 via the signal lines 64.

[0048] The read control circuit 31 turns on the reset switch 77 of the charge amplifier 70 in synchronization with the generation of the gate pulse, resetting unnecessary charges. Thus, unlike the image detection operation, the charge read operation does not convert the charges into analog voltage signals or the analog voltage signals into digital signals. Of course, in order to obtain an offset correction image or an afterimage correction image, which will be described later, the charge read operation may also convert the charges into analog voltage signals and the analog voltage signals into digital signals, as in the image detection operation.

[0049] The electronic cassette 10 performs various correction processes on the radiographic image output by the image detection operation. Examples of the various correction processes include offset correction, afterimage correction, sensitivity correction, and defective pixel correction. Offset correction is a process in which an offset correction image detected without radiation exposure is subtracted from the radiographic image on a pixel-by-pixel basis. By performing this offset correction, fixed pattern noise caused by dark charge and the like is removed from the radiographic image. Afterimage correction is a process in which an afterimage correction image corresponding to residual charge from the previous radiographic imaging is subtracted from the radiographic image on a pixel-by-pixel basis. Sensitivity correction is a process in which variations in the sensitivity of the photoelectric conversion unit 61 of each pixel 60 and variations in the output characteristics of the readout circuit 27 are corrected based on sensitivity correction data. Defective pixel correction is a process in which the pixel values ​​of defective pixels with abnormal pixel values ​​are linearly interpolated with the pixel values ​​of surrounding normal pixels 60 based on information on defective pixels with abnormal pixel values ​​generated at the time of shipment or during periodic inspection. The electronic cassette 10 transmits the radiation image after various correction processes to an external device such as a console. Note that these various correction processes may be performed in an external device instead of the electronic cassette 10.

[0050] Next, the operation of the above configuration will be described. Power from the power supply circuit 32 is supplied to the gate control circuits 30A and 30B via the power supply terminal 43, the first wiring 44A and 44B, and the first power supply receiving terminals 40A and 40B. Furthermore, power from the power supply circuit 32 is supplied to the readout control circuits 31A and 31B via the power supply terminal 43, the wiring 46A and 46B, and the power supply receiving terminals 42A and 42B. This causes the gate control circuit 30 and the readout control circuit 31 to operate. Then, under the control of the gate control circuit 30, the gate drive circuit 25 operates, and under the control of the readout control circuit 31, the readout circuit 27 operates, and one of the above-mentioned accumulation operation, image detection operation, and charge readout operation is performed on the photodetector substrate 16.

[0051] In an image detection operation or a charge readout operation, gate pulses are output from the gate drive circuit 25 to the scanning lines 63 in sequence, row by row. As a result, the charges accumulated in the photoelectric conversion units 61 of the pixels 60 are input to the readout circuit 27 via the signal lines 64. At this time, as shown in FIG. 6, when the upper half of the gate drive circuits 25 are operating, power supplied from the power supply circuit 32 to the gate control circuit 30B is directed to the gate control circuit 30A via the second wiring 45AB. Conversely, as shown in FIG. 7, when the lower half of the gate drive circuits 25 are operating, power supplied from the power supply circuit 32 to the gate control circuit 30A is directed to the gate control circuit 30B via the second wiring 45AB.

[0052] As described above, the electronic cassette 10 includes a detection panel 13 (photodetector substrate 16) on which pixels 60 are arranged, each accumulating a charge corresponding to radiation. The electronic cassette 10 also includes gate control circuits 30A and 30B that control the operation of the gate drive circuit 25, a power supply circuit 32 that supplies power to the gate control circuits 30A and 30B, first wiring 44A and 44B, and second wiring 45AB. The first wiring 44A and 44B connect the power supply circuit 32 to each of the gate control circuits 30A and 30B, respectively, and supply power from the power supply circuit 32 to each of the gate control circuits 30A and 30B. The second wiring 45AB connects the gate control circuits 30A and 30B. Therefore, the power from the power supply circuit 32 that is supplied to one of the gate control circuits 30A and 30B is redirected to the other by the second wiring 45AB. The power supplied to one of the gate control circuits 30A and 30B can supplement the power of the other. Therefore, it is possible to stably supply power to the gate control circuits 30A and 30B.

[0053] As shown in Figure 4 and other figures, the gate control circuits 30A and 30B have first power supply receiving terminals 40A and 40B to which first wiring 44A and 44B are connected, and second power supply receiving terminals 41A and 41B to which second wiring 45AB is connected. As shown in Figure 5 and other figures, the first power supply receiving terminal 40A and the second power supply receiving terminal 41A are connected in series, and the first power supply receiving terminal 40B and the second power supply receiving terminal 41B are connected in series. This allows power supplied from the power supply circuit 32 to one of the gate control circuits 30A and 30B to be efficiently diverted to the other.

[0054] The longer the distance between the gate control circuits 30A and 30B and the power supply circuit 32, i.e., the longer the lengths of the first wirings 44A and 44B, the higher the probability that the power supply to the gate control circuits 30A and 30B will become unstable due to factors such as voltage drops caused by wiring resistance. Therefore, in the case of an electronic cassette 10 whose long side 20 is longer than 431.8 mm, as in this example, the probability that the power supply to the gate control circuits 30A and 30B will become unstable is higher than in electronic cassettes whose long side 20 is 431.8 mm or less. Therefore, by applying the technology of the present disclosure to an electronic cassette 10 whose long side 20 is longer than 431.8 mm, the effect of enabling a stable power supply to the gate control circuits 30A and 30B can be more effectively achieved.

[0055] 4, the length of one second wiring 45AB is shorter than the combined length of first wirings 44A and 44B. Therefore, the electrical impedance of second wiring 45AB is smaller than the combined length of first wirings 44A and 44B. This minimizes the effect of voltage drop due to the wiring resistance of second wiring 45AB, further stabilizing the supply of power to gate control circuits 30A and 30B.

[0056] 8, second wiring 45AB is connected directly to gate control circuits 30A and 30B without any connecting components, which eliminates the effect of voltage drops due to the resistance of the connecting components and further stabilizes the supply of power to gate control circuits 30A and 30B.

[0057] In this example, the control circuits are gate control circuits 30A and 30B that control the operation of the gate drive circuit 25, which applies gate pulses to the TFTs 62 of the pixels 60 to read out charges from the pixels 60. If power can be supplied stably to the gate control circuits 30A and 30B, there is no risk of step-like artifacts occurring at the boundary between the upper and lower halves of the radiographic image (at the center of the row of pixels 60). As a result, radiographic images of good quality can be stably output.

[0058] The number of gate control circuits 30 is not limited to the two shown in the example. For example, as shown in FIG. 11 , four gate control circuits 30A, 30B, 30C, and 30D may share the control of the operation of multiple gate drive circuits 25. In this case, the second power supply receiving terminal 41B of gate control circuit 30B is connected to the second power supply receiving terminal 41C of gate control circuit 30C by a second wiring 45BC. The second power supply receiving terminal 41C of gate control circuit 30C is connected to the second power supply receiving terminal 41D of gate control circuit 30D by a second wiring 45CD. As a result, when gate control circuit 30A is operating, for example, power from power supply circuit 32 supplied to gate control circuits 30B, 30C, and 30D is directed to gate control circuit 30A via the second wiring 45AB, 45BC, and 45CD. Furthermore, for example, when gate control circuit 30C is operating, power supplied from power supply circuit 32 to gate control circuits 30A, 30B, and 30D is directed to gate control circuit 30C via second wiring 45AB, 45BC, and 45CD. Reference numerals 40C and 40D denote first power supply receiving terminals of gate control circuits 30C and 30D. Reference numerals 44C and 44D denote first wirings connecting power supply circuit 32 to gate control circuits 30C and 30D, respectively.

[0059] 11, gate control circuits 30B and 30C are connected by second wiring 45BC, but second wiring 45BC may be omitted. In that case, gate control circuits 30A and 30B may share power supply with each other, and gate control circuits 30C and 30D may share power supply with each other.

[0060] [Second embodiment] 12 , a detection panel 80 of the second embodiment is attached to an arc-shaped base 81. The detection panel 80 is composed of a scintillator 82 and a photodetector substrate 83. The scintillator 82 and the photodetector substrate 83 are provided on a flexible thin film sheet made of resin such as polyimide, and are bent into an arc shape following the shape of the base 81. The arc shapes of the detection panel 80 and the base 81 are concave with respect to the radiation source that emits radiation.

[0061] In this case, the gate control circuits 30A and 30B are mounted on gate control circuit boards 84A and 84B, which are flexible substrates. The gate control circuit boards 84A and 84B are bent into an arc shape following the base 81 and attached to the back surface of the base 81. Although not shown, the readout control circuits 31A and 31B and the power supply circuit 32 are also mounted on the readout control circuit board, which is a flexible substrate, and the power supply circuit board, which is also a flexible substrate. These are then bent into an arc shape following the base 81 and attached to the back surface of the base 81.

[0062] As described above, in the second embodiment, the gate control circuits 30A and 30B are mounted on gate control circuit boards 84A and 84B, which are flexible boards. This makes it possible to apply the present invention to a curved detection panel such as the arc-shaped detection panel 80. The curved shape of the detection panel is not limited to an arc, and may be an elliptical arc or a bowl shape like a parabolic antenna.

[0063] In each of the above embodiments, the gate control circuit 30 is exemplified as a control circuit that connects the second wiring 45AB etc. to direct power from the power supply circuit 32 to other control circuits, but this is not limiting. Instead of or in addition to the gate control circuit 30, at least two of the multiple read control circuits 31 may be connected by at least one second wiring.

[0064] The above-described numbers of rows and columns of pixels 60, the numbers of gate drive circuits 25 and readout circuits 27, the number of rows of pixels 60 assigned to one gate drive circuit 25, and the number of columns of pixels 60 assigned to one readout circuit 27 are merely examples. For example, the number of gate drive circuits 25 may be eight, and the number of rows of pixels 60 assigned to one gate drive circuit 25 may be 240.

[0065] The rows of pixels 60 assigned to one gate drive circuit 25 do not have to be a single group of rows equally divided from the rows of pixels 60. For example, one gate drive circuit 25 may be assigned to 256 rows of pixels 60, and another gate drive circuit 25 may be assigned to 128 rows of pixels 60. Similarly, the columns of pixels 60 assigned to one readout circuit 27 do not have to be a single group of columns equally divided from the columns of pixels 60.

[0066] In the first embodiment, the electronic cassette 10 has the long side 20 longer than 431.8 mm, but this is not limiting. The electronic cassette may have a side length of less than 431.8 mm.

[0067] Although an electronic cassette has been exemplified as the radiation image detector, the present invention is not limited to this. A radiation image detector mounted on an imaging table may also be used. Alternatively, a radiation image detector fixed to a position facing the radiation source by a C-arm or the like may also be used.

[0068] The technology of the present disclosure can be appropriately combined with the various embodiments and / or various modified examples described above. Furthermore, it is needless to say that it is not limited to the above-described embodiments, and various configurations can be adopted as long as they do not deviate from the gist of the present disclosure.

[0069] The above-described description and illustrations are a detailed explanation of the parts related to the technology of the present disclosure and are merely an example of the technology of the present disclosure. For example, the above description of the configuration, functions, actions, and effects is an explanation of an example of the configuration, functions, actions, and effects of the parts related to the technology of the present disclosure. Therefore, it goes without saying that unnecessary parts may be deleted, new elements may be added, or replacements may be made to the above-described description and illustrations within the scope of the gist of the technology of the present disclosure. Furthermore, to avoid confusion and facilitate understanding of the parts related to the technology of the present disclosure, the above-described description and illustrations omit explanations of common technical knowledge that do not require particular explanation to enable the implementation of the technology of the present disclosure.

[0070] In this specification, "A and / or B" is synonymous with "at least one of A and B." In other words, "A and / or B" means that it may be only A, only B, or a combination of A and B. Furthermore, in this specification, the same concept as "A and / or B" is also applied when three or more things are expressed connected by "and / or."

[0071] All publications, patent applications, and technical standards mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication, patent application, or technical standard was specifically and individually indicated to be incorporated by reference. [Explanation of symbols]

[0072] 10 Electronic Cassette 11. Housing 12 Radiolucent plate 13, 80 detection panel 14, 81 Foundation 15, 82 Scintillator 16, 83 Photodetector substrate 20 Long side of the housing 21 Short side of the housing 25 Gate drive circuit 26A, 26B, 84A, 84B Gate control circuit board 27 Readout circuit 28A, 28B Readout control circuit board 29 Power supply circuit board 30, 30A, 30B, 30C, 30D Gate control circuit 31, 31A, 31B Read control circuit 32 Power supply circuit 33 Long side of base 34 Short side of base 40A, 40B, 40C, 40D First power supply terminal 41A, 41B, 41C, 41D Second power supply terminal 42A, 42B power supply terminals 43 Power supply terminal 44A, 44B, 44C, 44D 1st wiring 45AB, 45BC, 45CD second wiring 46A, 46B wiring 50A, 50B insertion holes 51A, 51B conductor 52 Solder 60 pixels 61 Photoelectric conversion unit 62 TFT 63 scan lines 64 signal line 70 Charge Amplifier 71 Amplifier 72 CDS circuit 73 Multiplexer 74 A / D converter 75 operational amplifiers 76 Capacitor 77 Reset Switch LSL: Length of the long side SSL Short Side Length

Claims

1. A radiation image detector having a detection panel in which pixels that accumulate electric charges in response to radiation are arranged, a plurality of control circuits for controlling the operation of the detection panel; a power supply circuit for supplying power to the plurality of control circuits; a first wiring that connects the power supply circuit and each of the plurality of control circuits and supplies power from the power supply circuit to each of the plurality of control circuits; at least one second wiring that connects at least two control circuits among the plurality of control circuits; Equipped with The control circuit a first power supply receiving terminal to which the first wiring is connected; a second power supply receiving terminal to which the second wiring is connected; and The first power supply receiving terminal and the second power supply receiving terminal are connected in series. Radiation imaging detector.

2. 2. The radiation image detector according to claim 1, which is rectangular in plan view and has a long side longer than 431.8 mm.

3. The radiation image detector according to claim 1 , wherein the length of one of the second wires is shorter than the total length of the first wires.

4. The radiation image detector according to claim 1 , wherein the second wiring is directly connected to the control circuit without using a connecting component.

5. 5. The radiation image detector according to claim 1, wherein the control circuit is mounted on a flexible substrate.

6. 6. The radiation image detector according to claim 1, wherein the control circuit is a gate control circuit that controls the operation of a gate drive circuit that applies a gate pulse to a switching element of the pixel to read out the charge from the pixel.

Images