Imaging device

Abstract

Provided is a multi-functional imaging device. This imaging device has first to fourth light-receiving elements and first and second functional layers. Each of the first to fourth light-receiving elements is a photoelectric conversion element having sensitivity to light of different wavelengths. The first and second functional layers respectively have first and second transistors. The first functional layer and the fourth to first light-receiving elements are stacked in this order on the second functional layer. The first to fourth light-receiving elements each have stacked thereon a first conductive layer, a first buffer layer, a photoelectric conversion layer, a second buffer layer, and a second conductive layer in this order. The photoelectric conversion layers include an organic compound, and the first buffer layers and the second buffer layers include a metal or an organic compound. The first transistor is electrically connected to the first conductive layer of any of the first to fourth light-receiving elements. The second transistor is electrically connected to the first transistor.

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] A technique for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device having a pixel circuit that uses a transistor that includes an oxide semiconductor and has extremely low off-state current. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-119711 Summary of the Invention [Problem to be solved by the invention]

[0005] The pixels of solid-state imaging devices such as CMOS image sensors are provided with sub-pixels that separate incident light into the three primary color components of light (red (R), green (G), and blue (B)) to acquire data. These sub-pixels are used to generate color image data. Generally, in order to obtain luminance information with high accuracy, many sub-pixels that acquire G information, which has high visibility, are arranged. For example, one pixel may have four sub-pixels arranged in an R, G, G, B array.

[0006] The R, G, and B components can be separated using color filters. Furthermore, infrared (IR) information can be obtained by using a filter that cuts out light with higher energy than infrared light. To simultaneously capture color and infrared images, an infrared sub-pixel is required in addition to the color sub-pixels.

[0007] For this reason, the sub-pixel configuration will be an R·G·G·B·IR array or an R·G·B·IR array. The former has five sub-pixels, so compared to an image sensor of the same size with an R·G·G·B array, the total number of pixels will be reduced and the resolution will be lower. In the latter case, in a similar comparison, the number of pixels will remain the same, but the ability to obtain brightness information will be reduced.

[0008] An object of one embodiment of the present invention is to provide an imaging device capable of capturing a color image with high resolution.An object of one embodiment of the present invention is to provide an imaging device capable of capturing a color image and an infrared image with high resolution.An object of one embodiment of the present invention is to provide an imaging device which can easily achieve high definition.An object of one embodiment of the present invention is to provide an imaging device which can easily achieve a high aperture ratio.An object of one embodiment of the present invention is to provide a multifunctional imaging device.

[0009] Another object of one embodiment of the present invention is to provide an imaging device with high reliability.Another object of one embodiment of the present invention is to provide an imaging device having a novel structure.Another object of one embodiment of the present invention is to provide a semiconductor device, an electronic device, or the like having a novel structure.Another object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is an imaging device having a first light receiving element, a second light receiving element, a third light receiving element, a fourth light receiving element, a first functional layer, and a second functional layer. The first light receiving element is a photoelectric conversion element sensitive to light of a first wavelength. The second light receiving element is a photoelectric conversion element sensitive to light of a second wavelength. The third light receiving element is a photoelectric conversion element sensitive to light of a third wavelength. The fourth light receiving element is a photoelectric conversion element sensitive to light of a fourth wavelength. The first functional layer has a first transistor. The second functional layer has a second transistor. The first functional layer, the fourth light receiving element, the third light receiving element, the second light receiving element, and the first light receiving element are stacked in this order on the second functional layer. The first light-receiving element, the second light-receiving element, the third light-receiving element, and the fourth light-receiving element each have a layered structure in which a first conductive layer, a first buffer layer, a photoelectric conversion layer, a second buffer layer, and a second conductive layer are stacked in this order. The photoelectric conversion layer contains an organic compound, and the first buffer layer and the second buffer layer each contain a metal or an organic compound. The first transistor is electrically connected to a first conductive layer included in any one of the first light-receiving element, the second light-receiving element, the third light-receiving element, and the fourth light-receiving element. The second transistor is electrically connected to the first transistor.

[0012] Another embodiment of the present invention is an imaging device including a first light receiving element, a second light receiving element, a third light receiving element, a fourth light receiving element, a first functional layer, and a second functional layer. The first light receiving element is a photoelectric conversion element sensitive to light of a first wavelength. The second light receiving element is a photoelectric conversion element sensitive to light of a second wavelength. The third light receiving element is a photoelectric conversion element sensitive to light of a third wavelength. The fourth light receiving element is a photoelectric conversion element sensitive to light of a fourth wavelength. The first functional layer includes a first transistor. The second functional layer includes a second transistor. The first functional layer, the fourth light receiving element, the third light receiving element, the second light receiving element, and the first light receiving element are stacked in this order on the second functional layer. The first light-receiving element, the second light-receiving element, and the third light-receiving element each have a layered structure in which a first conductive layer, a first buffer layer, a photoelectric conversion layer, a second buffer layer, and a second conductive layer are stacked in this order. The photoelectric conversion layer contains an organic compound, and the first buffer layer and the second buffer layer each contain a metal or an organic compound. The fourth light-receiving element is provided on a first single-crystal substrate and has a photoelectric conversion portion having a pn junction in the first single-crystal substrate. The first transistor is electrically connected to a first conductive layer of any one of the first light-receiving element, the second light-receiving element, and the third light-receiving element. The second transistor is electrically connected to the first transistor.

[0013] In the above, the first transistor is preferably provided over a first single crystal substrate and has a channel formation region in the first single crystal substrate.

[0014] In any of the above, the first transistor preferably contains silicon in a channel formation region, or preferably contains an oxide semiconductor in a channel formation region.

[0015] In any of the above, the second transistor is preferably provided over a first single crystal substrate and has a channel formation region in the first single crystal substrate.

[0016] In the above, it is preferable that a third functional layer is provided between the first functional layer and the second functional layer, the third functional layer has a third transistor, and the third transistor includes an oxide semiconductor in a channel formation region.

[0017] In any of the above, it is preferable that a plug is provided. In this case, the plug electrically connects one of the source and drain of the first transistor to the first conductive layer of the first light-receiving element. In addition, it is preferable that the photoelectric conversion layer of the second light-receiving element has a first opening. Furthermore, it is preferable that the second conductive layer of the second light-receiving element has a second opening. In this case, it is preferable that the plug has a portion that contacts the photoelectric conversion layer inside the first opening. Furthermore, it is preferable that the plug has a portion located inside the second opening and does not contact the first conductive layer and the second conductive layer.

[0018] Alternatively, in any of the above, it is preferable to have a plug. In this case, it is preferable that the plug electrically connects one of the source and drain of the first transistor to the first conductive layer of the first light-receiving element. Furthermore, it is preferable that the photoelectric conversion layer of the second light-receiving element has a first opening. Furthermore, it is preferable that the second conductive layer of the second light-receiving element has a second opening. Furthermore, it is preferable that the plug has a portion located inside the first opening and a portion located inside the second opening, and is not in contact with the first conductive layer, the photoelectric conversion layer, and the second conductive layer.

[0019] In any of the above, it is preferable that any three of the light of the first wavelength, the light of the second wavelength, the light of the third wavelength, and the light of the fourth wavelength are visible light, and the remaining one is infrared light or ultraviolet light.

[0020] In any of the above, the order of wavelengths from shortest to largest is preferably the first wavelength, the second wavelength, the third wavelength, and the fourth wavelength. [Effects of the Invention]

[0021] According to one aspect of the present invention, an imaging device capable of capturing a color image with high resolution can be provided. Alternatively, an imaging device capable of capturing a color image and an infrared light image with high resolution can be provided. Alternatively, an imaging device that can easily achieve high definition can be provided. Alternatively, an imaging device that can easily achieve a high aperture ratio can be provided. Alternatively, a multifunctional imaging device can be provided.

[0022] According to one embodiment of the present invention, a highly reliable imaging device can be provided. Alternatively, an imaging device having a novel structure can be provided. Alternatively, a semiconductor device, an electronic device, or the like having a novel structure can be provided. Alternatively, at least one of the problems of the prior art can be alleviated.

[0023] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0024] FIG. 1 is a diagram illustrating an example of the configuration of an imaging device. FIG. 2 is a diagram illustrating an example of the configuration of an imaging device. 3A to 3F are diagrams illustrating an example of the configuration of an imaging device. FIG. 4 is a diagram illustrating an example of the configuration of an imaging device. FIG. 5 is a diagram illustrating an example of the configuration of an imaging device. 6A and 6B are diagrams illustrating an example of the configuration of a light receiving element. 7A and 7B are diagrams illustrating an example of the configuration of a light receiving element. FIG. 8 is a diagram illustrating an example of the configuration of an imaging device. 9A to 9C are diagrams illustrating examples of the structure of a transistor. 10A to 10D illustrate examples of the structure of a transistor. FIG. 11 is a diagram illustrating an example of the configuration of an imaging device. FIG. 12 is a diagram illustrating an example of the configuration of an imaging device. FIG. 13 is a diagram illustrating an example of the configuration of an imaging device. FIG. 14 is a diagram illustrating an example of the configuration of an imaging device. FIG. 15 is a diagram illustrating an example of the configuration of an imaging device. FIG. 16 is a diagram illustrating an imaging device. FIG. 17 is a diagram illustrating a pixel block and a circuit. 18A and 18B are diagrams illustrating pixels. 19A and 19B are timing charts illustrating the operation of the pixel block and circuits. 20A and 20B are diagrams illustrating the circuit. FIG. 21 is a diagram illustrating a memory cell. 22A and 22B are diagrams showing examples of the configuration of a neural network. 23A1 to 23A3 and 23B1 to 23B3 are perspective views of a package and a module that house an imaging device. 24A to 24F are diagrams illustrating an electronic device. 25A and 25B are diagrams illustrating a moving object, and Fig. 25C is a diagram illustrating an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0027] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0028] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0029] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0030] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0031] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, coils, capacitive elements, and other elements with various functions.

[0032] In the following, expressions indicating directions such as "up" and "down" will basically be used in accordance with the directions in the drawings. However, for purposes such as facilitating explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided in the drawing (such as the surface to be formed, the supporting surface, the adhesive surface, or the flat surface) is located above the laminate, the direction toward that surface may be expressed as "down" and the opposite direction as "up."

[0033] (Embodiment 1) In this embodiment, an imaging device according to one embodiment of the present invention will be described.

[0034] One embodiment of the present invention is an imaging device having a plurality of light receiving elements, a first functional layer, and a second functional layer. The first functional layer and the second functional layer each have one or more transistors. The plurality of light receiving elements are photoelectric conversion elements each sensitive to light of a different wavelength. In one embodiment of the present invention, the first functional layer is stacked on the second functional layer, and a plurality of light receiving elements are further stacked on the first functional layer.

[0035] The multiple light receiving elements each have the function of absorbing light of a different wavelength and converting it into an electrical signal. The light receiving element (also referred to as the first light receiving element) located at the top (on the imaging surface side, on the light incident side) of the multiple light receiving elements absorbs light in a wavelength range including a first wavelength and transmits light in other wavelength ranges. The light receiving element (also referred to as the second light receiving element) located next to the first light receiving element from the top absorbs light in a wavelength range including a second wavelength from the light transmitted by the first light receiving element and transmits light in other wavelength ranges. The light receiving element located at the bottom of the multiple light receiving elements absorbs light in a wavelength range including a predetermined wavelength from the light transmitted by one or more light receiving elements (e.g., the first light receiving element and the second light receiving element) located above it. In this way, the multiple stacked light receiving elements can absorb light of different wavelengths and convert it into an electrical signal.

[0036] In the imaging device of one embodiment of the present invention, a plurality of photodetectors can be stacked, and therefore the light-receiving area of ​​each photodetector can be increased compared to when a plurality of photodetectors are arranged side by side. This allows the sensitivity of each photodetector to be increased. Furthermore, compared to when a plurality of photodetectors are arranged side by side, the area of ​​each pixel can be reduced, and therefore high resolution can be achieved without reducing sensitivity.

[0037] The first functional layer includes a transistor that constitutes a pixel circuit. The transistor (also referred to as a first transistor) included in the first functional layer is electrically connected to one of the multiple light-receiving elements stacked thereon. Furthermore, the transistor (also referred to as a second transistor) included in the second functional layer located below the first functional layer may be electrically connected to the first transistor or may be electrically connected to a wiring provided in the first functional layer. The second functional layer may also include another transistor that constitutes a pixel circuit.

[0038] The first functional layer may be provided with various circuits in addition to the pixel circuits, such as a driver circuit for driving the pixels, a readout circuit for reading pixel data, a protection circuit, a memory circuit, and the like.

[0039] The second functional layer can be provided with various circuits such as a drive circuit, a readout circuit, a protection circuit, a memory circuit, an arithmetic circuit, a power supply circuit, and a signal generation circuit. Furthermore, a circuit may be configured using elements (components) such as transistors, capacitors, resistors, and wiring included in the first functional layer and the corresponding elements (components) included in the second functional layer. Stacking the first functional layer and the second functional layer can achieve multi-functionality and miniaturization.

[0040] In particular, it is preferable to provide a driver circuit for driving the pixel circuit in the second functional layer. By arranging the driver circuit so as to overlap the pixel circuit and the light receiving element, the wiring between the driver circuit and the pixel circuit can be made extremely short compared to when they are arranged side by side. This makes it possible to suppress the effects of signal delay and signal level reduction.

[0041] Furthermore, it is preferable that the second functional layer is provided with a memory circuit and an arithmetic circuit. The memory circuit and the arithmetic circuit can perform image processing on image data captured by each pixel circuit and output the processed image data. In this case, it is preferable that the arithmetic circuit in the second functional layer has a product-sum operation circuit. This makes it possible to perform image processing using machine learning, particularly neural networks.

[0042] In this way, by stacking a plurality of functional layers and a plurality of light receiving elements, it is possible to achieve high sensitivity, high definition, multi-functionality, and miniaturization of the imaging device.

[0043] A more specific configuration example will be described below with reference to the drawings.

[0044] [Pixel configuration example] 1 shows a perspective schematic diagram of a portion corresponding to one pixel of the imaging device 10. The imaging device 10 has a light receiving element 20B, a light receiving element 20G, a light receiving element 20R, a light receiving element 20IR, a functional layer 11, and a functional layer 12. The functional layer 11 is stacked on the functional layer 12. The light receiving element 20IR, the light receiving element 20R, the light receiving element 20G, and the light receiving element 20B are stacked in this order on the functional layer 11. The light receiving element 20B, which is located in the uppermost layer among the multiple light receiving elements, corresponds to the imaging surface side (the light incident side).

[0045] The functional layer 11 and each light-receiving element are electrically connected by a plug. In Fig. 1, a plug 13IR electrically connecting the light-receiving element 20IR and the functional layer 11, a plug 13R electrically connecting the light-receiving element 20R and the functional layer 11, a plug 13G electrically connecting the light-receiving element 20G and the functional layer 11, and a plug 13B electrically connecting the light-receiving element 20B and the functional layer 11 are provided.

[0046] Here, the plug 13R electrically connects the functional layer 11 and the light-receiving element 20R via the layer in which the light-receiving element 20IR is provided. Therefore, the plug 13R and the light-receiving element 20IR are provided at a distance from each other to prevent an electrical short circuit.

[0047] Similarly, the plug 13G is provided at a distance from the light-receiving elements 20IR and 20R, which are located between the light-receiving element 20G and the functional layer 11. The plug 13B is provided at a distance from the light-receiving elements 20IR, 20R, and 20G, which are located between the light-receiving element 20B and the functional layer 11.

[0048] For example, the plug 13R and the light-receiving element 20IR need not be electrically shorted, and some of the layers constituting the light-receiving element 20IR may be in contact with the plug 13R. Similarly, the plugs 13G and 13B may be in contact with parts of the respective light-receiving elements.

[0049] FIG. 2 is a schematic cross-sectional view illustrating one pixel of the imaging device.

[0050] 2 includes a functional layer 12, a functional layer 11, a light receiving element 20IR, a light receiving element 20R, a light receiving element 20G, and a light receiving element 20B stacked in this order. A light-transmitting insulating layer 14 is provided between the two light receiving elements. An insulating layer 15 is provided between the functional layer 11 and the light receiving element 20IR.

[0051] Each light-receiving element has a conductive layer 22, a conductive layer 23, and a photoelectric conversion layer therebetween. The photoelectric conversion layer 21B of the light-receiving element 20B is sensitive to blue light (B). The photoelectric conversion layer 21G of the light-receiving element 20G is sensitive to green light (G). The photoelectric conversion layer 21R of the light-receiving element 20R is sensitive to red light (R). The photoelectric conversion layer 21IR of the light-receiving element 20IR is sensitive to infrared light (IR). The conductive layers 22 and 23 are translucent. Note that a light-shielding conductive material may be used for the conductive layer 22 of the light-receiving element 20IR located closest to the functional layer 11. In particular, by using a light-reflective conductive material, light that has passed through the photoelectric conversion layer 21IR can be reflected, thereby improving the conversion efficiency (also referred to as external quantum efficiency) of each light-receiving element.

[0052] A plurality of transistors 31 are provided in the functional layer 11. The transistors 31 are electrically connected to a conductive layer 22 of any one of the light receiving elements 20IR, 20R, 20G, and 20B. Here, an example is shown in which the conductive layer 22 is electrically connected to one of the source and drain of the transistor 31. A common potential (here, ground potential) is applied to the conductive layer 23 of each light receiving element. Note that different potentials may be applied to the conductive layer 23 of each light receiving element.

[0053] The functional layer 12 includes a plurality of transistors 32. The transistors 32 are electrically connected to the transistors 31, wirings, electrodes, or terminals included in the functional layer 11. In the example shown in FIG. 2, the gate of the transistor 32 is electrically connected to the other of the source and drain of the transistor 31.

[0054] The transistor 32 included in the functional layer 12 is preferably provided on a single crystal substrate. For example, a transistor having a channel formed in a part of the single crystal substrate can be suitably applied. Alternatively, a transistor having a channel formed in a semiconductor thin film formed on the single crystal substrate can be applied. A silicon substrate can be typically used as the single crystal substrate. Alternatively, a semiconductor substrate other than silicon, such as a silicon carbide substrate, a gallium nitride substrate, or an oxide semiconductor substrate, can be used as the single crystal substrate.

[0055] It is preferable that each photoelectric conversion layer of each light receiving element absorbs light in a wavelength range including a predetermined wavelength. This allows each light receiving element to be used as a light cut filter. In the example shown in FIG. 2, blue light (B) is absorbed by light receiving element 20B. Green light (G) passes through light receiving element 20B and is absorbed by light receiving element 20G. Red light (R) passes through light receiving element 20B and light receiving element 20G and is absorbed by light receiving element 20R. Infrared light (IR) passes through light receiving element 20B, light receiving element 20G, and light receiving element 20R and is absorbed by light receiving element 20IR.

[0056] The example shown in Figure 2 is an example in which light receiving elements sensitive to short wavelength light are stacked in order from the light incident side. Since short wavelength light is more easily scattered and absorbed than long wavelength light, by arranging light receiving elements that receive short wavelength light closer to the light incident side, the effect of light attenuation can be reduced and a highly sensitive imaging device can be realized.

[0057] The stacking order of each light receiving element is not limited to the configuration shown in Figures 1 and 2. The stacking order can be changed as appropriate depending on the characteristics of each light receiving element. For example, it is preferable that light receiving elements that absorb light in a narrower wavelength range are arranged closer to the light incident side, and light receiving elements that absorb light in a wider wavelength range are arranged closer to the light incident side. Each diagram in Figure 3 shows other examples of stacking orders.

[0058] 3A shows an example in which light receiving elements that receive light of longer wavelengths are arranged closer to the light incident side. Specifically, from the light incident side, light receiving element 20IR, light receiving element 20R, light receiving element 20G, and light receiving element 20B are stacked in this order.

[0059] FIG. 3B shows an example in which the light receiving element 20R, the light receiving element 20G, the light receiving element 20B, and the light receiving element 20IR are stacked in this order from the light incident side.

[0060] Fig. 3C shows an example in which light receiving element 20G, light receiving element 20B, light receiving element 20R, and light receiving element 20IR are stacked in this order from the light incident side, while Fig. 3D shows an example in which light receiving element 20R, light receiving element 20B, light receiving element 20G, and light receiving element 20IR are stacked in this order from the light incident side.

[0061] 3E and 3F show an example in which a light receiving element 20UV that receives ultraviolet light (UV) is used instead of the light receiving element 20IR that receives infrared light (IR).

[0062] Fig. 3E shows an example in which light receiving element 20UV, light receiving element 20B, light receiving element 20G, and light receiving element 20R are stacked in this order from the light incident side. Fig. 3F shows an example in which light receiving element 20B, light receiving element 20G, light receiving element 20R, and light receiving element 20UV are stacked in this order from the light incident side.

[0063] Although an example in which four types of light receiving elements are stacked has been shown here, the present invention is not limited to this, and a configuration in which three types of light receiving elements are stacked, or five or more types of light receiving elements may be stacked. A stacked structure including two or more of the same light receiving elements may also be used. Fig. 4 shows an example in which three types of light receiving elements, light receiving element 20B, light receiving element 20G, and light receiving element 20R, are stacked.

[0064] FIG. 5 is a schematic cross-sectional view of an imaging device 10 having a configuration that is partially different from that described above.

[0065] 5 shows an example in which no insulating layer 14 is provided between the light receiving elements. The four light receiving elements (20B, 20G, 20R, and 20IR) are connected in series. Furthermore, an electrode is shared between two adjacent light receiving elements.

[0066] Specifically, the photoelectric conversion layer 21IR and the photoelectric conversion layer 21R are stacked on the conductive layer 22 with the conductive layer 24 interposed therebetween. The conductive layer 24 functions as both the upper electrode of the light receiving element 20IR and the lower electrode of the light receiving element 20R. Similarly, the photoelectric conversion layer 21R and the photoelectric conversion layer 21G are stacked with the conductive layer 24 interposed therebetween. The photoelectric conversion layer 21G and the photoelectric conversion layer 21B are stacked with the conductive layer 24 interposed therebetween. A conductive layer 23 is provided on the photoelectric conversion layer 21B. The conductive layer 22 and each conductive layer 24 are electrically connected to a different transistor 31, respectively. A ground potential is applied to the conductive layer 23.

[0067] In the example shown in Figure 5, the potentials of the four conductive layers (conductive layer 22 and three conductive layers 24) are obtained, and the difference between them is calculated to obtain a signal corresponding to the intensity of the light received by each light receiving element.

[0068] [Photodetector configuration example] A more specific example of the configuration of the light receiving element will be described below, taking as an example the light receiving element (light receiving element 20IR) located at the bottom of the four light receiving elements illustrated in FIG.

[0069] Fig. 6A shows a schematic perspective view of a light receiving element 20IR for 2 x 2 pixels, and Fig. 6B shows a schematic perspective view in which each layer in Fig. 6A is expanded vertically.

[0070] As shown in Figure 6B, the conductive layer 22 has an island shape. Since an area for four pixels is shown here, four island-shaped conductive layers 22 are shown in Figure 6B. Plug 13IR is electrically connected to the conductive layer 22. In addition, the conductive layer 22 has a shape with notches provided on three sides so as not to contact the plugs 13B, 13G, and 13R. This makes it possible to maximize the light-receiving area of ​​the light-receiving element.

[0071] The photoelectric conversion layer 21IR has a stacked structure in which a buffer layer 21a, an active layer 21b, and a buffer layer 21c are stacked. The buffer layer 21a and the buffer layer 21c each function as a carrier transport layer. The active layer 21b has a function of generating charges by the photoelectric effect. The buffer layer 21a, the active layer 21b, and the buffer layer 21c each preferably contain an organic compound. The photoelectric conversion layer 21IR is provided so as to be continuous between adjacent pixels.

[0072] The photoelectric conversion layer 21IR has an opening 16a so as not to come into contact with the plugs 13B, 13G, and 13R. In Fig. 6B, three plugs are located inside the opening 16a.

[0073] The conductive layer 23 has the same top surface shape as the photoelectric conversion layer 21IR. That is, the conductive layer 23 and the photoelectric conversion layer 21IR can be processed using the same photomask, etc. The conductive layer 23 is provided so as to be continuous between adjacent pixels.

[0074] The conductive layer 23 has an opening 16b so as not to come into contact with the plugs 13B, 13G, and 13R. In Fig. 6B, three plugs are located inside the opening 16b.

[0075] 7A and 7B show an example in which the photoelectric conversion layer 21IR is in contact with each plug.

[0076] When low-electrical-conductivity materials are used for the buffer layer 21a, active layer 21b, and buffer layer 21c constituting the photoelectric conversion layer 21IR, there are cases where no problems occur even if the photoelectric conversion layer 21IR is provided in contact with the plug, as shown in Figures 7A and 7B. This configuration can simplify the process. Note that, if a highly electrically conductive material is included in each layer constituting the photoelectric conversion layer 21IR, there is a risk of electrical short-circuiting between the plugs, so the configuration shown in Figure 6A and the like is preferable.

[0077] [Configuration example 1 of imaging device] An example of the configuration of an imaging device will be described below.

[0078] Note that the elements such as insulating layers and conductive layers shown below are examples, and other elements may be included. Also, some of the elements shown below may be omitted. Also, the stacked structure shown below can be formed using a bonding process, a polishing process, or the like, as necessary.

[0079] [Configuration Example 1-1] 8 is a schematic cross-sectional view of the imaging device. The imaging device has a layered structure in which a functional layer 12, a functional layer 11, a light receiving element 20IR, a light receiving element 20R, a light receiving element 20G, and a light receiving element 20G are layered in this order. Note that the layering order of the light receiving elements is not limited to this and can be changed as appropriate.

[0080] The functional layer 12 has circuit elements provided on the silicon substrate 51. Here, a transistor 61a and a transistor 61b are shown as part of the circuit elements.

[0081] The functional layer 12 includes a silicon substrate 51, a transistor 61a, a transistor 61b, various insulating layers, and various conductive layers. Each insulating layer has one or more functions of a protective layer, an interlayer insulating layer, and a planarizing layer. Each conductive layer has one or more functions of a plug, wiring, electrode, etc.

[0082] The insulating layer may be an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, or an aluminum oxide film. Alternatively, an organic insulating film such as an acrylic resin or a polyimide resin may be used. The insulating layer may be a laminated film in which two or more of the above-mentioned inorganic insulating films or organic insulating films are laminated.

[0083] Furthermore, as a conductive layer that can be used as a wiring, an electrode, or a plug, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc., can be appropriately selected and used. As the conductive layer, a stacked film in which two or more conductive films containing the above-mentioned conductive materials are stacked may be used.

[0084] The transistors 61a and 61b are transistors (also referred to as Si transistors) whose channels are formed in a silicon substrate 51. FIG. 8 shows an example in which fin-type transistors are used as the transistors 61a and 61b. FIG. 9A shows a cross section of the fin-type Si transistor in the channel width direction. Note that the Si transistor may be a planar-type transistor, as shown in FIG. 9B.

[0085] 9C, the Si transistor may be a transistor having a silicon thin-film semiconductor layer 54. The semiconductor layer 54 may be, for example, single-crystal silicon (SOI: Silicon on Insulator) formed on an insulating layer 53 on a silicon substrate 51. Alternatively, polycrystalline silicon may be used as the semiconductor layer 54.

[0086] The functional layer 11 has circuit elements provided on the functional layer 12. Here, a transistor 62a and a transistor 62b are shown as part of the circuit elements.

[0087] The transistor 62a and the transistor 62b are transistors in which a channel is formed in an oxide semiconductor layer (also referred to as OS transistors).

[0088] An insulating layer 52 is provided between the functional layer 11 and the functional layer 12. The insulating layer 52 functions as a barrier film that prevents the diffusion of water, hydrogen, etc. As the insulating layer 52, it is preferable to use an insulating film with a high barrier property against water or hydrogen, such as a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, an yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, a hafnium oxynitride film, or an yttria-stabilized zirconia (YSZ) film.

[0089] In particular, it is preferable to use a film that has a function of preventing hydrogen diffusion as the insulating layer 52 that functions as a barrier film. In Si devices, hydrogen is required to terminate dangling bonds. However, hydrogen near an OS transistor can generate carriers in the oxide semiconductor layer, reducing reliability. Therefore, it is preferable to provide a hydrogen-blocking film between the layer where the Si device is formed and the layer where the OS transistor is formed.

[0090] 10A illustrates details of an OS transistor that can be used as the transistor 62a and the transistor 62b. The OS transistor illustrated in FIG. 10A has a self-aligned structure in which an insulating layer is provided over a stack of a semiconductor layer and a conductive layer, and source and drain electrodes are formed by providing openings that reach the semiconductor layer.

[0091] The OS transistor may have a channel formation region, a source region 73, and a drain region 74 formed in an oxide semiconductor, as well as a gate electrode 71 and a gate insulating layer 72. At least the gate insulating layer 72 and the gate electrode 71 are provided in the opening. A semiconductor layer 77 may also be provided in the opening. A source electrode 75 is provided on the source region 73, and a drain electrode 76 is provided on the drain region 74.

[0092] As shown in FIG. 10B, the OS transistor may have a self-aligned structure in which a source region 73 and a drain region 74 are formed in a semiconductor layer using a gate electrode 71 as a mask.

[0093] Alternatively, as shown in FIG. 10C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 75 or the drain electrode 76 overlaps with the gate electrode 71.

[0094] Although the OS transistor has a back gate 78 in this example, it may not have a back gate. The back gate 78 may be electrically connected to a gate electrode 71 that functions as a front gate of the OS transistor located opposite the back gate, as shown in the cross-sectional view of the OS transistor in the channel width direction in FIG. 10D . Note that FIG. 10D illustrates an example cross-section of the OS transistor shown in FIG. 10A , but the same applies to transistors with other structures. Alternatively, a fixed potential or signal different from that of the front gate may be supplied to the back gate 78.

[0095] In FIG. 8, on the functional layer 11, a light receiving element 20IR, a light receiving element 20R, a light receiving element 20G, and a light receiving element 20B are stacked.

[0096] Each light-receiving element has a laminated structure of a conductive layer 22, a buffer layer 21a, an active layer 21b, a buffer layer 21c, and a conductive layer 23. The active layer 21b of each light-receiving element preferably contains a different organic compound. The buffer layer 21a and the buffer layer 21c of each light-receiving element preferably contain a metal or an organic compound. The buffer layer 21a and the buffer layer 21c of each light-receiving element may contain different materials (metals or organic compounds), or the same material may be used for two or more light-receiving elements.

[0097] One of the buffer layer 21a and the buffer layer 21c functions as a hole transport layer and / or a hole injection layer, while the other of the buffer layer 21a and the buffer layer 21c functions as an electron transport layer and / or an electron injection layer, and the active layer 21b functions as a photoelectric conversion layer.

[0098] As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.

[0099] The buffer layer 21a, the active layer 21b, and the buffer layer 21c, as well as materials that can be used for these layers, will be described below.

[0100] The hole injection layer is a layer that injects holes from the electrode into the light-receiving element. The hole injection layer is a layer containing a material with high hole injection properties. Examples of the material with high hole injection properties include a composite material containing a hole transport material and an acceptor material (electron acceptor material), and an aromatic amine compound.

[0101] The hole transport layer is a layer that transports holes. The hole transport layer is a layer that contains a hole transporting material. -6 cm 2A material having a hole mobility of 1 / Vs or more is preferred. Note that other materials can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton), is preferred.

[0102] The electron transport layer is a layer that transports electrons. The electron transport layer is a layer that contains an electron transporting material. The electron transporting material is 1×10 -6 cm 2 A substance having an electron mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher electron transporting property than holes. Examples of electron-transporting materials that can be used include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, and metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and π-electron-deficient heteroaromatic compounds including nitrogen-containing heteroaromatic compounds.

[0103] The electron injection layer is a layer that injects electrons from the electrode to the light-receiving element. The electron injection layer is a layer containing a material with high electron injection properties. As the material with high electron injection properties, a material containing a metal such as an alkali metal, an alkaline earth metal, or a compound thereof can be used. As the material with high electron injection properties, a composite material containing an electron transport material and a donor material (electron donor material) can also be used.

[0104] The active layer 21b has an n-type semiconductor material such as fullerene (e.g., C 60 , C 70Examples of electron-accepting organic semiconductor materials include fullerene derivatives and other fullerenes. Fullerenes have a soccer ball-like shape, which is energetically stable. Fullerenes have deep (low) HOMO and LUMO levels. Because fullerenes have a deep LUMO level, they have extremely high electron-accepting (acceptor) properties. Normally, when the π-electron conjugation (resonance) spreads on a plane, as in benzene, the electron-donating (donor) properties increase, but fullerenes have a spherical shape, so they have high electron-accepting properties despite the large spread of π-electrons. High electron-accepting properties allow charge separation to occur quickly and efficiently, making them useful as light-receiving elements. C 60 , C 70 Both have a wide absorption band in the visible light region, especially C 70 is C 60 It is preferred because it has a larger π-electron conjugated system and a wide absorption band in the long wavelength region compared to the above.

[0105] Furthermore, examples of n-type semiconductor materials include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, naphthalene derivatives, anthracene derivatives, coumarin derivatives, rhodamine derivatives, triazine derivatives, and quinone derivatives.

[0106] Examples of the p-type semiconductor material of the active layer 21b include electron-donating organic semiconductor materials such as copper(II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), zinc phthalocyanine (ZnPc), tin phthalocyanine (SnPc), and quinacridone.

[0107] Examples of p-type semiconductor materials include carbazole derivatives, thiophene derivatives, furan derivatives, and compounds having an aromatic amine skeleton. Examples of p-type semiconductor materials include naphthalene derivatives, anthracene derivatives, tetracene derivatives, pyrene derivatives, triphenylene derivatives, fluorene derivatives, pyrrole derivatives, benzofuran derivatives, benzothiophene derivatives, indole derivatives, dibenzofuran derivatives, dibenzothiophene derivatives, indolocarbazole derivatives, porphyrin derivatives, phthalocyanine derivatives, naphthalocyanine derivatives, quinacridone derivatives, polyphenylenevinylene derivatives, polyparaphenylene derivatives, polyfluorene derivatives, polyvinylcarbazole derivatives, and polythiophene derivatives.

[0108] The HOMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the HOMO level of the electron-accepting organic semiconductor material, and the LUMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the LUMO level of the electron-accepting organic semiconductor material.

[0109] It is preferable to use a spherical fullerene as the electron-accepting organic semiconductor material and a planar organic semiconductor material as the electron-donating organic semiconductor material. Molecules with similar shapes tend to aggregate together, and when molecules of the same type aggregate, the energy levels of their molecular orbitals become close, which can improve carrier transport properties.

[0110] For example, the active layer 21b is preferably formed by co-evaporating an n-type semiconductor and a p-type semiconductor.

[0111] The buffer layer 21a, the active layer 21b, and the buffer layer 21c can be made of either a low molecular weight compound or a high molecular weight compound, and may contain an inorganic compound. Each layer can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0112] The buffer layer 21a, the active layer 21b, and the buffer layer 21c can have a single-layer structure containing a single material (compound), a single-layer structure containing multiple materials, a stacked structure of layers containing two or more single materials, a stacked structure of layers containing two or more multiple materials, or a stacked structure of a layer containing one or more single materials and a layer containing one or more multiple materials. When forming a layer containing multiple materials by vacuum deposition, either a co-evaporation method in which two or more materials are individually evaporated or sublimated to form a film, or a premix method in which a mixed material containing two or more materials is evaporated or sublimated to form a film, may be used. Alternatively, a layer containing three or more materials may be formed by combining the co-evaporation method and the premix method.

[0113] FIG. 8 clearly shows a plug 13IR that electrically connects the transistor 62a to the conductive layer 22 of the light-receiving element 20IR, and a plug 13B that electrically connects the transistor 62b to the conductive layer 22 of the light-receiving element 20B.

[0114] The plug 13IR is electrically connected to one of the source and drain of the transistor 62a. In Fig. 8, the other of the source and drain of the transistor 62a is electrically connected to the gate of the transistor 61a. Similarly, the plug 13B is electrically connected to one of the source and drain of the transistor 62b.

[0115] The other of the source and drain of transistor 62b is electrically connected to the gate of transistor 61b. In this case, transistors 62a and 61a form part of one pixel circuit, and transistors 62b and 61b form part of another pixel circuit. For example, transistors 62a and 62b each function as a transfer transistor, and transistors 61a and 61b function as amplification transistors. Note that the connection relationship between the transistors is not limited to the configuration shown in FIG. 8.

[0116] 8 shows an example in which the plug 13B is provided in contact with the buffer layer 21a, the active layer 21b, and the buffer layer 21c of the light-receiving element 20G, the light-receiving element 20R, and the light-receiving element 20IR. Note that, as shown in FIG. 6 and other examples, the plug 13B may not be in contact with these.

[0117] In FIG. 8, a microlens array 18 is provided on the light receiving element 20B via an insulating layer 17. The microlens array 18 has the function of concentrating incident light so that the light is efficiently incident on each light receiving element. The lenses of the microlens array 18 may be arranged for each pixel, or one for two or more pixels. For example, a microlens array in which lenses covering 2×2 pixels are arranged may be used.

[0118] [Configuration Example 1-2] An example of the configuration of an imaging device having a different configuration from the above will be described below. Note that a description of the same parts as those described above will be omitted, and only the different parts will be described.

[0119] 11 shows a schematic cross-sectional view of an imaging device that is partially different in configuration from Configuration Example 1. The imaging device shown in FIG. 11 differs from Configuration Example 1 mainly in that the configuration of the functional layer 11 is different.

[0120] The functional layer 11 has circuit elements provided on the silicon substrate 55. Here, a transistor 63a and a transistor 63b are shown as part of the circuit elements.

[0121] The functional layer 11 includes a silicon substrate, a transistor 63a, a transistor 63b, various insulating layers, and various conductive layers. Each insulating layer has one or more functions of a protective layer, an interlayer insulating layer, and a planarizing layer. Each conductive layer has one or more functions of a plug, wiring, electrode, etc.

[0122] The transistors 63a and 63b are Si transistors whose channels are formed in a silicon substrate 55. Fig. 11 shows an example in which fin-type transistors are used as the transistors 63a and 63b. Note that the transistors shown in Fig. 9A, 9B, or 9C may also be used.

[0123] The insulating layers 82 and 83 located between the functional layers 11 and 12 function as bonding layers. The surfaces of the insulating layers 82 and 83 corresponding to the bonding surfaces are each flattened. The insulating layers 82 and 83 are preferably formed from the same material.

[0124] A plug 81 is provided in the silicon substrate 55, reaching the bonding surface. One end of the plug 81 is electrically connected to the transistor 63a or the transistor 63b. The other end of the plug 81 is joined to a plug 84 included in the functional layer 12. The functional layer 11 and the functional layer 12 are electrically connected via the plug 81 and the plug 84, and signals can be exchanged via these.

[0125] [Configuration Example 1-3] 12 is different from the above-described configuration example 2 mainly in the configuration of the functional layer 11. The imaging device shown in FIG. 12 has a configuration in which the functional layer 11 is upside down compared to the above-described configuration example 2.

[0126] An insulating layer 86 is provided on the back surface of the silicon substrate 55 (the surface on which the transistor 63a and the like are not provided), and the light receiving element 20IR is provided on the insulating layer 86.

[0127] Some of the multiple plugs 81 provided inside the silicon substrate 55 are electrically connected to the plugs 13B and the like via the insulating layer 86. Other parts of the multiple plugs 81 are provided in contact with the conductive layer 22 of the light-receiving element 20IR. That is, in FIG. 12, the plugs 81 also serve as the plugs 13IR.

[0128] Furthermore, a plug 85 is provided on the bonding surface of the functional layer 11 that is bonded to the functional layer 12. The plug 85 is bonded to a plug 84 that the functional layer 12 has.

[0129] [Configuration example 2 of imaging device] A light receiving element formed on a semiconductor substrate can be used as one of the multiple light receiving elements of an imaging device. Below, an imaging device including both a light receiving element using an organic compound and a light receiving element formed on a semiconductor substrate will be described.

[0130] [Configuration Example 2-1] Fig. 13 shows a schematic cross-sectional view of an imaging device. The configuration shown in Fig. 13 differs from the configuration shown in Fig. 12 above mainly in that the configuration of the functional layer 11 is different and that a light receiving element 40 is provided instead of the light receiving element 20IR.

[0131] The light receiving element 40 is a pn junction photodiode formed on a silicon substrate 56. The light receiving element 40 has a region 41 corresponding to a p-type region and a region 42 corresponding to an n-type region. The light receiving element 40 shown in FIG. 13 is a buried photodiode, and can suppress dark current and reduce noise by using a thin p-type region (part of region 41) provided on the surface side (current extraction side) of region 42.

[0132] An element isolation layer is provided on the silicon substrate 56. Specifically, grooves for isolating pixels are provided in the silicon substrate 56, and an insulating layer 57 is provided on the upper surface of the silicon substrate 56 and in the grooves. The insulating layer 57 can prevent carriers generated in the light-receiving element 40 from flowing into adjacent pixels. The insulating layer 57 also has the function of suppressing the intrusion of stray light.

[0133] Furthermore, a region 43 corresponding to an n-type region is provided in the silicon substrate 56, separate from the light-receiving element 40. An opening reaching the region 43 is provided in the insulating layer 57 and the silicon substrate 56, and a plug 13B is provided in the opening. The plug 13B electrically connects the conductive layer 22 of the light-receiving element 20B to the region 43. Note that the plugs 13G and 13R (not shown) may also have a similar configuration.

[0134] The functional layer 11 includes a transistor 64a, a transistor 65a, a transistor 64b, and a transistor 65b. Each transistor has a channel formed in the silicon substrate 56.

[0135] A part of the region 42 of the light receiving element 40 serves as either the source or the drain of a transistor 64a. A region 43 provided in the silicon substrate 56 serves as either the source or the drain of a transistor 64b. FIG. 13 shows a transistor 65a connected in series with the transistor 64a and a transistor 65b connected in series with the transistor 64b.

[0136] The other of the source and drain of transistor 64a is electrically connected to the gate of transistor 61a in functional layer 12 via plugs 85 and 84. The other of the source and drain of transistor 64b is electrically connected to the gate of transistor 61b in functional layer 12 via plugs 85 and 84.

[0137] Here, the light receiving element 40 has an area overlapping with the transistor 64a, the transistor 65a, the transistor 64b, and the transistor 65b, which increases the aperture ratio (effective light receiving area ratio) of the pixel, thereby realizing a highly sensitive imaging device.

[0138] 13 may be configured such that, for example, the light receiving element 20B, the light receiving element 20G, and the light receiving element 20R receive blue light, green light, and red light, respectively, and the light receiving element 40 receives infrared light. However, the present invention is not limited to this, and the light receiving element 40 may be configured to receive any visible light.

[0139] Furthermore, a substrate other than silicon may be used as the substrate on which the light receiving element 40 is formed. For example, silicon carbide, oxide semiconductor, gallium nitride, or the like, which have a larger band gap than silicon, can be used. This makes it possible to form a light receiving element that generates charge by absorbing ultraviolet light.

[0140] [Configuration Example 2-2] The configuration shown in Fig. 14 differs from the configuration illustrated in Fig. 13 in that it has functional layers 11a and 11b instead of functional layer 11. That is, the imaging device shown in Fig. 14 has a configuration in which four light receiving elements and three functional layers are stacked.

[0141] 13 can be applied to the functional layer 11a and the light receiving element 40. That is, the light receiving element 40, the transistor 64a, the transistor 65a, the transistor 64b, and the transistor 65b are provided on a silicon substrate 56.

[0142] The functional layer 11b can have the same configuration as the functional layer 11 illustrated in Fig. 8. That is, OS transistors are used for the transistors 62a and 62b included in the functional layer 11b.

[0143] 14 is bonded between functional layers 11a and 11b. Specifically, an insulating layer 83 provided on the lower surface of functional layer 11a and an insulating layer 82 provided on the upper surface of functional layer 11b are bonded together. Signals can be exchanged between functional layers 11a and 11b via plugs 84 and 85.

[0144] 14, the other of the source and drain of transistor 64a is electrically connected to one of the source and drain of transistor 62a and the gate of transistor 61a. The other of the source and drain of transistor 64b is electrically connected to one of the source and drain of transistor 62b and the gate of transistor 61b. Note that the connection relationship between the transistors is not limited to this.

[0145] In this way, by stacking three or more functional layers, it is possible to realize an imaging device that has multiple functions while suppressing an increase in the occupied area.

[0146] [Configuration Example 2-3] The imaging device shown in FIG. 15 has a configuration in which the functional layer 11b illustrated in FIG. 14 is inverted vertically.

[0147] The functional layer 11b is formed by being laminated on the functional layer 11a with an insulating layer 52 interposed therebetween.

[0148] 15 is bonded between the functional layer 11b and the functional layer 12. Specifically, an insulating layer 83 provided on the lower surface of the functional layer 11b and an insulating layer 82 provided on the upper surface of the functional layer 12 are bonded together. Signals can be exchanged between the functional layer 11b and the functional layer 12 via a plug 85 and a plug 84.

[0149] The above is a description of an example of the configuration of the imaging device.

[0150] The imaging device exemplified in this embodiment has a configuration in which multiple light receiving elements and multiple functional layers are stacked. Furthermore, it is possible to capture not only full-color images using a single type of pixel, but also infrared light images. This not only reduces manufacturing costs but also the number of components and power consumption of electronic devices to which the imaging device is applied. Furthermore, compared to a case in which a visible light imaging element and an infrared light imaging element are arranged side by side, there is no misalignment in the imaging positions between color images and infrared light images. This provides a secondary effect, such as eliminating the need for image processing to correct the misalignment.

[0151] Furthermore, according to the imaging device exemplified in this embodiment, it is possible to reduce the area occupied by the pixel without sacrificing sensitivity and aperture ratio. Also, since it is possible to arrange various circuits over the pixel, it is easy to achieve multi-functionality. Also, it is possible to realize an imaging device capable of capturing color images with high resolution. Or, it is possible to realize an imaging device capable of capturing both color images and infrared light images with high resolution. Or, it is possible to realize an imaging device that can easily achieve high definition. Or, it is possible to realize an imaging device that can easily achieve a high aperture ratio. Or, it is possible to realize a multi-functional imaging device.

[0152] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0153] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0154] (Embodiment 2) In this embodiment, an imaging device having a calculation function which is one embodiment of the present invention will be described with reference to drawings.

[0155] One aspect of the present invention is an imaging device with additional functions such as image recognition. The imaging device has a function of storing analog data (image data) acquired during imaging in pixels, and extracting data obtained by multiplying the analog data by an arbitrary weighting coefficient. The imaging device also has a function of adding the data output from multiple pixels (product-sum operation function).

[0156] Furthermore, the data extracted from the pixels can be input into a neural network or the like provided inside or outside the imaging device, thereby enabling processing such as image recognition. In one aspect of the present invention, a huge amount of image data can be stored in the pixels in the form of analog data and can be calculated within the pixels, thereby enabling efficient processing.

[0157] The light receiving element included in the imaging device exemplified below can be a light receiving element having the organic compound exemplified in embodiment 1, or a light receiving element formed on a single crystal substrate. Furthermore, the circuits included in the imaging device exemplified below can be configured with transistors, wiring, electrodes, and the like included in functional layer 11 (or functional layer 11a and functional layer 11b) and functional layer 12 exemplified in embodiment 1.

[0158] [Imaging device] 16 is a block diagram illustrating an imaging device of one embodiment of the present invention. The imaging device includes a pixel array 300, a circuit 201, a circuit 302, a circuit 303, a circuit 304, and a circuit 305. Note that one or more of the circuit 201, the circuit 301, the circuit 302, the circuit 303, the circuit 304, and the circuit 305 may overlap with the pixel array 300. With this configuration, the area of ​​the imaging device can be reduced.

[0159] Note that in the imaging device of one embodiment of the present invention, a circuit having two or more of the functions of the circuit 201 and the circuits 301 to 305 may be used instead. Alternatively, circuits other than the circuit 201 and the circuits 301 to 305 may be used. Alternatively, one or more of the functions of the circuit 201 and the circuits 301 to 305 may be replaced by software operations. Alternatively, some of the circuits of the circuit 201 and the circuits 301 to 305 may be provided outside the imaging device.

[0160] The pixel array 300 can have an imaging function and a calculation function. The circuits 201 and 301 can have a calculation function. The circuit 302 can have a calculation function or a data conversion function and can output data to a wiring 311. The circuits 303 and 304 can have a selection function. The circuit 305 can have a function of supplying a potential (such as a weight) to a pixel. Note that a shift register, a decoder, or the like can be used as the circuit having the selection function.

[0161] 17 , the pixel array 300 includes a plurality of pixel blocks 200. As shown in FIG. 17 , the pixel block 200 includes a plurality of pixels 100 arranged in a matrix, and each pixel 100 is electrically connected to a circuit 201 via a wiring 113. Note that the circuit 201 can also be provided within the pixel block 200.

[0162] The pixel 100 can acquire image data and generate data by adding the image data and a weighting factor. While the pixel block 200 in FIG. 17 has 3×3 pixels as an example, this is not limiting. For example, it can have 2×2 or 4×4 pixels. Alternatively, the number of pixels in the horizontal and vertical directions may be different. Furthermore, some pixels may be shared between adjacent pixel blocks.

[0163] The pixel block 200 and the circuit 201 can be operated as a multiply-accumulate circuit.

[0164] [Pixel circuit] 18A, the pixel 100 can have a light receiving element 101, a transistor 102, a transistor 103, a capacitor 104, a transistor 105, a transistor 106, and a transistor 108. The light receiving element can also be called a light receiving device, a photoelectric conversion element, a photoelectric conversion device, or the like.

[0165] One electrode of the light-receiving element 101 is electrically connected to one of the source and drain of the transistor 102. The other of the source and drain of the transistor 102 is electrically connected to one of the source and drain of the transistor 103, one electrode of the capacitor 104, and the gate of the transistor 105. One of the source and drain of the transistor 105 is electrically connected to one of the source and drain of the transistor 108. The other electrode of the capacitor 104 is electrically connected to one of the source and drain of the transistor 106.

[0166] The other electrode of the light-receiving element 101 is electrically connected to a wiring 114. The gate of the transistor 102 is electrically connected to a wiring 116. The other of the source and the drain of the transistor 103 is electrically connected to a wiring 115. The gate of the transistor 103 is electrically connected to a wiring 117. The other of the source and the drain of the transistor 105 is electrically connected to a GND wiring or the like. The other of the source and the drain of the transistor 108 is electrically connected to a wiring 113. The other of the source and the drain of the transistor 106 is electrically connected to a wiring 111. The gate of the transistor 106 is electrically connected to a wiring 112. The gate of the transistor 108 is electrically connected to a wiring 122.

[0167] Here, the electrical connection point (wiring) between the other of the source or drain of the transistor 102, one of the source or drain of the transistor 103, one electrode of the capacitor 104, and the gate of the transistor 105 is referred to as a node N.

[0168] The wirings 114 and 115 can function as power supply lines. For example, the wiring 114 can function as a high-potential power supply line, and the wiring 115 can function as a low-potential power supply line. The wirings 112, 116, 117, and 122 can function as signal lines that control the conduction of each transistor. The wiring 111 can function as a wiring that supplies a potential corresponding to a weighting coefficient to the pixel 100. The wiring 113 can function as a wiring that electrically connects the pixel 100 and the circuit 201.

[0169] The wiring 113 may be electrically connected to an amplifier circuit, a gain adjustment circuit, or the like.

[0170] A photodiode can be used as the light receiving element 101. If it is desired to increase the light detection sensitivity at low illuminance, an avalanche photodiode may be used.

[0171] The transistor 102 can have a function of controlling the potential of the node N. The transistor 103 can have a function of initializing the potential of the node N. The transistor 105 can have a function of controlling the current flowing from the circuit 201 in accordance with the potential of the node N. The transistor 108 can have a function of selecting a pixel. The transistor 106 can have a function of supplying a potential corresponding to a weighting coefficient to the node N.

[0172] As shown in Figure 18B, the transistors 105 and 108 may have a configuration in which one of the source or drain of the transistor 105 is electrically connected to one of the source or drain of the transistor 108, the other of the source or drain of the transistor 105 is connected to a wiring 113, and the other of the source or drain of the transistor 108 is electrically connected to a GND wiring or the like.

[0173] 18A and 18B, the connection direction of a pair of electrodes of the light-receiving element 101 may be reversed. In this case, the wiring 114 may function as a low-potential power supply line, and the wiring 115 may function as a high-potential power supply line.

[0174] The transistors 102 and 103 are preferably OS transistors (OS transistors) that use metal oxide in their channel formation regions. OS transistors have extremely low off-state current. By using OS transistors as the transistors 102 and 103, the period during which charge can be held at the node N can be significantly extended. Furthermore, a global shutter system in which charge is accumulated simultaneously in all pixels can be applied without complicating the circuit configuration or operation method. Furthermore, while image data is held at the node N, multiple calculations can be performed using the image data.

[0175] On the other hand, it may be desirable for the transistor 105 to have excellent amplification characteristics. It may also be preferable to use high-mobility transistors that can operate at high speed as the transistors 106 and 108. Therefore, the transistors 105, 106, and 108 may be transistors that use silicon in their channel formation regions (Si transistors).

[0176] Note that the present invention is not limited to the above, and any combination of OS transistors and Si transistors may be used. Furthermore, all transistors may be OS transistors. Alternatively, all transistors may be Si transistors. Examples of Si transistors include transistors containing amorphous silicon and transistors containing crystalline silicon (microcrystalline silicon, low-temperature polysilicon, and single-crystal silicon).

[0177] The potential of the node N in the pixel 100 is determined by the sum of a reset potential supplied from the wiring 115 and a potential (image data) generated by photoelectric conversion by the light receiving element 101. Alternatively, the potential is determined by capacitively coupling a potential corresponding to a weighting factor supplied from the wiring 111. Therefore, the transistor 105 can pass a current corresponding to the data in which an arbitrary weighting factor has been added to the image data.

[0178] [Circuit 201] 17, the pixels 100 are electrically connected to each other through wirings 113. The circuit 201 can perform calculations using the sum of currents flowing through the transistors 105 of the pixels 100.

[0179] The circuit 201 includes a capacitor 202, a transistor 203, a transistor 204, a transistor 205, a transistor 206, and a transistor 207 as a voltage conversion circuit. A suitable analog potential (Bias) is applied to the gate of the transistor 207.

[0180] One electrode of the capacitor 202 is electrically connected to one of the source and drain of the transistor 203 and the gate of the transistor 204. One of the source and drain of the transistor 204 is electrically connected to one of the source and drain of the transistor 205 and one of the source and drain of the transistor 206. The other electrode of the capacitor 202 is electrically connected to the wiring 113 and one of the source and drain of the transistor 207.

[0181] The other of the source and the drain of the transistor 203 is electrically connected to a wiring 218. The other of the source and the drain of the transistor 204 is electrically connected to a wiring 219. The other of the source and the drain of the transistor 205 is electrically connected to a reference power supply line such as a GND wiring. The other of the source and the drain of the transistor 206 is electrically connected to a wiring 212. The other of the source and the drain of the transistor 207 is electrically connected to a wiring 217. The gate of the transistor 203 is electrically connected to a wiring 216. The gate of the transistor 205 is electrically connected to a wiring 215. The gate of the transistor 206 is electrically connected to a wiring 213.

[0182] The wirings 217, 218, and 219 can function as power supply lines. For example, the wiring 218 can function as a wiring that supplies a reset potential (Vr) for reading. The wirings 217 and 219 can function as high-potential power supply lines. The wirings 213, 215, and 216 can function as signal lines that control the conduction of each transistor. The wiring 212 is an output line and can be electrically connected to, for example, the circuit 301 shown in FIG. 16.

[0183] The transistor 203 can have a function of resetting the potential of the wiring 211 to the potential of the wiring 218. The transistors 204 and 205 can function as source follower circuits. The transistor 206 can have a function of controlling reading. Note that the circuit 201 has a function as a correlated double sampling circuit (CDS circuit) and can be replaced with a circuit having the same function.

[0184] In one embodiment of the present invention, offset components other than the product of image data (X) and a weighting coefficient (W) are removed to extract the target WX. WX can be calculated using data acquired from the same pixel with exposure (with imaging) and without exposure (without imaging), and data when weights are applied to each of the data.

[0185] The current (I p ) is the sum of kΣ(XV th ) 2 , the current (I p ) is the sum of kΣ(W+XV th ) 2 In addition, the current (I ref ) is the sum of kΣ(0-V th ) 2 , the current (I ref ) is the sum of kΣ(WV th ) 2 where k is a constant, V this the threshold voltage of transistor 105.

[0186] First, calculate the difference (data A) between the data with exposure and the data with weighting added to it. kΣ((XV th ) 2 -(W+XV th ) 2 )=kΣ(-W 2 -2W·X+2W·V th )

[0187] Next, calculate the difference (data B) between the data without exposure and the weighted data. kΣ((0-V th ) 2 -(WV th ) 2 )=kΣ(-W 2 +2W·V th )

[0188] Then, take the difference between data A and data B. kΣ(-W 2 -2W·X+2W·V th -(-W 2 +2W·V th ))=kΣ(-2W·X). In other words, it is possible to remove offset components other than the product of the image data (X) and the weighting coefficient (W).

[0189] The circuit 201 can read out data A and data B. Note that the difference between data A and data B can be calculated by the circuit 301, for example.

[0190] [Image capture operation] 19A is a timing chart illustrating the operation of calculating the difference (data A) between exposed data and weighted data in pixel block 200 and circuit 201. For convenience, the timing at which each signal is converted is shown together, but in practice, it is preferable to stagger the timings to take into account delays within the circuit. In the following description, high potential is represented by "H" and low potential by "L."

[0191] First, in a period T1, the potential of the wiring 117 is set to "H", the potential of the wiring 116 is set to "H", and the node N of the pixel 100 is set to a reset potential. In addition, the potential of the wiring 111 is set to "L", the potentials of the wirings 112_1 to 112_3 (the wirings 112 in the first to third rows) are set to "H", and a weighting coefficient of 0 is written.

[0192] The potential of the wiring 116 is maintained at "H" until the period T2, and the potential of the wiring 117 is set to "L", so that the potential X (image data) is written to the node N by photoelectric conversion of the light-receiving element 101.

[0193] In period T3, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to select all pixels 100 in the pixel block. At this time, a current corresponding to the potential X flows through the transistor 105 of each pixel 100. In addition, the potential of the wiring 216 is set to "H" to write the potential Vr of the wiring 218 to the wiring 211. The operation in periods T1 to T3 corresponds to obtaining data with exposure, and the data is initialized to the potential Vr of the wiring 211.

[0194] During period T4, the potential of wiring 111 is set to a potential corresponding to weighting coefficient W11 (weighting added to the pixels in the first row), and the potential of wiring 112_1 is set to "H," so that the weighting coefficient W11 is added to node N of pixel 100 in the first row through capacitive coupling of capacitor 104.

[0195] During period T5, the potential of wiring 111 is set to a potential corresponding to weighting coefficient W12 (weighting to be added to the pixels in the second row), and the potential of wiring 112_2 is set to "H," so that the weighting coefficient W12 is added to node N of pixel 100 in the second row through the capacitive coupling of capacitor 104.

[0196] In period T6, the potential of the wiring 111 is set to a potential corresponding to weighting coefficient W13 (weighting to be added to the pixels in the third row) and the potential of the wiring 112_3 is set to "H", so that the weighting coefficient W13 is added to the node N of the pixels 100 in the third row by the capacitive coupling of the capacitor 104. The operations in periods T4 to T6 correspond to the generation of data in which a weight is added to the data with imaging.

[0197] During period T7, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to select all pixels 100 in the pixel block. At this time, a current corresponding to the potential W11+X flows through the transistors 105 of the pixels 100 in the first row. A current corresponding to the potential W12+X flows through the transistors 105 of the pixels 100 in the second row. A current corresponding to the potential W13+X flows through the transistors 105 of the pixels 100 in the third row.

[0198] Here, the potential of the other electrode of capacitor 202 changes in accordance with the current flowing through wiring 113, and this change Y is added to the potential Vr of wiring 211 by capacitive coupling. Therefore, the potential of wiring 211 becomes "Vr+Y." If we consider Vr=0, then Y is the difference itself, and data A has been calculated.

[0199] In addition, the potential of the wiring 213 is set to "H" and the potential of the wiring 215 is set to "V bias By setting an appropriate analog potential such as "," the circuit 201 can output a signal potential according to the data A of the pixel block 200 in the first row by a source follower operation.

[0200] FIG. 19B is a timing chart illustrating the operation of pixel block 200 and circuit 201 to calculate the difference (data B) between data without exposure and data with a weight applied thereto. Data B may be acquired as needed. For example, if there is no change in the input weight, acquired data B may be stored in memory and data B may be read from the memory. Multiple pieces of data B corresponding to multiple weights may be stored in the memory. Either data A or data B may be acquired first.

[0201] First, during periods T1 and T2, the potential of the wiring 117 is set to "H", the potential of the wiring 116 is set to "H", and the node N of the pixel 100 is set to a reset potential (0). At the end of period T2, the potential of the wiring 117 is set to "L", and the potential of the wiring 116 is set to "L". That is, during this period, the potential of the node N is the reset potential regardless of the operation of the light-receiving element 101.

[0202] In the period T1, the potential of the wiring 111 is set to "L", the potentials of the wirings 112_1, 112_2, and 112_3 are set to "H", and the weighting coefficient is written as 0. This operation may be performed during a period in which the potential of the node N is the reset potential.

[0203] During period T3, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to select all pixels 100 in the pixel block. At this time, a current corresponding to the reset potential flows through the transistor 105 of each pixel 100. Furthermore, by setting the potential of the wiring 216 to "H," the potential Vr of the wiring 218 is written to the wiring 211. The operation during periods T1 to T3 corresponds to obtaining data without exposure, and the data is initialized to the potential Vr of the wiring 211.

[0204] During period T4, the potential of wiring 111 is set to a potential corresponding to weighting coefficient W11 (weighting added to the pixels in the first row), and the potential of wiring 112_1 is set to "H," so that the weighting coefficient W11 is added to node N of pixel 100 in the first row through capacitive coupling of capacitor 104.

[0205] During period T5, the potential of wiring 111 is set to a potential corresponding to weighting coefficient W12 (weighting to be added to the pixels in the second row), and the potential of wiring 112_2 is set to "H," so that the weighting coefficient W12 is added to node N of pixel 100 in the second row through the capacitive coupling of capacitor 104.

[0206] During period T6, the potential of the wiring 111 is set to a potential corresponding to weighting coefficient W13 (weighting to be added to the pixels in the third row) and the potential of the wiring 112_3 is set to "H", thereby adding weighting coefficient W13 to node N of the pixels 100 in the third row through capacitive coupling of capacitor 104. The operations during periods T4 and T6 correspond to the generation of data in which weighting is added to data without imaging.

[0207] During period T7, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to select all pixels 100 in the pixel block. At this time, a current corresponding to the potential W11+0 flows through the transistors 105 of the pixels 100 in the first row. A current corresponding to the potential W12+0 flows through the transistors 105 of the pixels 100 in the second row. A current corresponding to the potential W13+0 flows through the transistors 105 of the pixels 100 in the third row.

[0208] Here, the potential of the other electrode of capacitor 202 changes in accordance with the current flowing through wiring 113, and the change Y is added to the potential Vr of wiring 211. Therefore, the potential of wiring 211 becomes "Vr+Z." If we consider Vr=0, then Z is the difference itself, and data B has been calculated.

[0209] In addition, the potential of the wiring 213 is set to “H” and the potential of the wiring 215 is set to an appropriate analog potential (V bias ), the circuit 201 can output a signal potential according to the data B of the pixel block 200 in the first row by a source follower operation.

[0210] The data A and data B output from the circuit 201 by the above operation are input to the circuit 301. The circuit 301 performs an operation to find the difference between the data A and the data B, thereby making it possible to remove unnecessary offset components other than the product of the image data (potential X) and the weighting coefficient (potential W). The circuit 301 may have a configuration including an arithmetic circuit like the circuit 201, or may have a configuration in which the difference is found by using a memory circuit and software processing.

[0211] In the above operation, the potential of the wiring 211 of the circuit 201 is initialized to the same potential "Vr" for both the operation of acquiring data A and the operation of acquiring data B. Then, in the subsequent difference calculation, "(Vr+Y)-(Vr+Z)"="YZ", and the component of the potential "Vr" is removed. Furthermore, as described above, other unnecessary offset components are also removed, so that the product of the image data (potential X) and the weighting coefficient (potential W) can be extracted.

[0212] This operation corresponds to the initial operation of a neural network that performs inference, etc. Therefore, at least one calculation can be performed within the imaging device before a large amount of image data is output externally, reducing the load of external calculations or data input / output, increasing processing speed, and reducing power consumption.

[0213] Alternatively, as an alternative to the above, the potential of the wiring 211 of the circuit 201 may be initialized to different potentials during the data A acquisition operation and the data B acquisition operation. For example, assume that the potential is initialized to "Vr1" during the data A acquisition operation and to "Vr2" during the data B acquisition operation. In this case, the subsequent difference calculation results in "(Vr1+Y)-(Vr2+Z)" = "(Vr1-Vr2)+(YZ)." As in the above operation, "YZ" is extracted as the product of the image data (potential X) and the weighting coefficient (potential W), and then "Vr1-Vr2" is added to it. Here, "Vr1-Vr2" corresponds to the bias used to adjust the threshold value in the calculation of the intermediate layer of the neural network.

[0214] Furthermore, the weighting factor, for example, functions as a filter for a convolutional neural network (CNN), but may also amplify or attenuate data. For example, if the weighting factor (W) used during the acquisition of data A is the product of the filtering factor and the amplification factor, filtered data corrected to a brighter image can be extracted. Data B is data without imaging, and can also be considered black-level data. Therefore, the operation of calculating the difference between data A and data B can be said to be an operation that promotes the visualization of an image captured in a dark place. In other words, brightness correction using a neural network becomes possible.

[0215] As described above, one embodiment of the present invention allows for bias generation through the operation of the imaging device. Functional weighting can also be added within the imaging device. This reduces the load on external computations and can be used for a variety of applications. For example, in addition to subject inference, some of the following processes can be performed within the imaging device: image data resolution correction, brightness correction, color image generation from monochrome images, 3D image generation from 2D images, restoration of missing information, video generation from still images, and correction of out-of-focus images.

[0216] [Circuit 301, Circuit 302] 20A is a diagram illustrating circuits 301 and 302 connected to circuit 201. Data resulting from a product-sum operation output from circuit 201 is sequentially input to circuit 301. Circuit 301 may have various other operation functions in addition to the function of calculating the difference between data A and data B described above. For example, circuit 301 may have the same configuration as circuit 201. Alternatively, the function of circuit 301 may be replaced by software processing.

[0217] The circuit 301 may also include a circuit that performs activation function calculations. For example, a comparator circuit can be used for this circuit. The comparator circuit compares input data with a set threshold value and outputs the result as binary data. In other words, the pixel block 200 and the circuit 301 can function as part of a neural network.

[0218] The circuit 301 may also include an A / D converter. Regardless of whether a product-sum operation is performed or not, when image data is output from the pixel block 200 to the outside, the circuit 301 can convert analog data into digital data.

[0219] For example, in a pixel block 200 having 3x3 pixels 100, if the weights supplied to all pixels 100 are the same (for example, 0) and the transistor 108 of the pixel from which data is to be output is turned on, the sum of image data for the entire pixel block 200, the sum of image data for each row, or data for each pixel can be output from the pixel block 200.

[0220] Furthermore, the data output by the pixel block 200 corresponds to multi-bit image data, but if the circuit 301 can binarize it, it can also be said that the image data is compressed.

[0221] Data output from the circuit 301 is sequentially input to the circuit 302. The circuit 302 can have a configuration including, for example, a latch circuit and a shift register. This configuration enables parallel-serial conversion, and data input in parallel can be output to the wiring 311 as serial data.

[0222] 20B, the circuit 302 may include a neural network. The neural network includes memory cells arranged in a matrix, each of which holds a weighting coefficient. Data output from the circuit 301 is input to memory cells 320, where a product-sum operation can be performed. Note that the number of memory cells shown in FIG. 20B is an example and is not limited to this. Data after the product-sum operation can be output to wiring 311.

[0223] 20A and 20B, there is no limitation on the connection destination of the wiring 311. For example, it can be connected to a neural network, a storage device, a communication device, etc.

[0224] The neural network shown in FIG. 20B includes memory cells 320 and reference memory cells 325 arranged in a matrix, a circuit 330, a circuit 350, a circuit 360, and a circuit 370.

[0225] 21 shows an example of a memory cell 320 and a reference memory cell 325. The reference memory cell 325 is provided in any one column. The memory cell 320 and the reference memory cell 325 have the same configuration, and each include a transistor 161, a transistor 162, and a capacitor 163.

[0226] One of the source or drain of the transistor 161 is electrically connected to the gate of the transistor 162. The gate of the transistor 162 is electrically connected to one electrode of the capacitor 163. Here, the point where one of the source or drain of the transistor 161, the gate of the transistor 162, and one electrode of the capacitor 163 are connected is referred to as a node NM.

[0227] A gate of the transistor 161 is electrically connected to a wiring WL. The other electrode of the capacitor 163 is electrically connected to a wiring RW. One of the source and the drain of the transistor 162 is electrically connected to a reference potential wiring such as a GND wiring.

[0228] In the memory cell 320, the other of the source and the drain of the transistor 161 is electrically connected to a wiring WD. The other of the source and the drain of the transistor 162 is electrically connected to a wiring BL.

[0229] In the reference memory cell 325, the other of the source and the drain of the transistor 161 is electrically connected to a wiring WDref. The other of the source and the drain of the transistor 162 is electrically connected to a wiring BLref.

[0230] The wiring WL is electrically connected to the circuit 330. The circuit 330 can be a decoder, a shift register, or the like.

[0231] The wiring RW is electrically connected to the circuit 301. Binary data output from the circuit 301 is written to each memory cell. Note that a sequential circuit such as a shift register may be provided between the circuit 301 and each memory cell.

[0232] The wiring WD and the wiring WDref are electrically connected to the circuit 350. The circuit 350 may include a decoder, a shift register, or the like. The circuit 350 may also include a D / A converter, an SRAM, or the like. The circuit 350 can output the weighting coefficient written to the node NM.

[0233] The wiring BL and the wiring BLref are electrically connected to the circuit 360. The circuit 360 can have the same structure as the circuit 201. The circuit 360 can obtain a signal obtained by removing the offset component from the result of the product-sum operation.

[0234] Circuit 360 is electrically connected to circuit 370. Circuit 370 can also be described as an activation function circuit. The activation function circuit has a function of performing calculations to convert the signal input from circuit 360 according to a predefined activation function. Examples of the activation function that can be used include a sigmoid function, a tanh function, a softmax function, a ReLU function, and a threshold function. The signal converted by the activation function circuit is output to the outside as output data.

[0235] As shown in FIG. 22A, a neural network NN can be configured with an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. The input layer IL, output layer OL, and intermediate layer HL each have one or more neurons (units). The intermediate layer HL may have one layer or two or more layers. A neural network with two or more intermediate layers HL can also be called a DNN (deep neural network). Learning using a deep neural network can also be called deep learning.

[0236] Input data is input to each neuron in the input layer IL. An output signal from a neuron in the previous or next layer is input to each neuron in the hidden layer HL. An output signal from a neuron in the previous layer is input to each neuron in the output layer OL. Each neuron may be connected to all neurons in the previous or next layer (fully connected), or may be connected to only a portion of the neurons in the previous or next layer.

[0237] Figure 22B shows an example of a neuron's operation. It shows neuron N and two neurons in the previous layer that output signals to neuron N. Neuron N receives the output x1 of a neuron in the previous layer and the output x2 of a neuron in the previous layer. Neuron N then multiplies the output x1 by a weight w1 (x1w1) and the output x2 by a weight w2 (x2w2), calculating the sum x1w1+x2w2. After this, a bias b is added as necessary, resulting in a value a = x1w1+x2w2+b. The value a is then transformed by the activation function h, and neuron N outputs an output signal y = ah.

[0238] In this way, the computation by a neuron includes the sum of the product of the output of the neuron in the previous layer and the weight, i.e., the sum-of-products computation (x1w1+x2w2 above). This sum-of-products computation can be performed by software using a program, or by hardware.

[0239] In one embodiment of the present invention, a product-sum operation is performed using an analog circuit as hardware. When an analog circuit is used for the product-sum operation circuit, the circuit scale of the product-sum operation circuit can be reduced, or the number of accesses to a memory can be reduced, thereby improving the processing speed and reducing power consumption.

[0240] The product-sum circuit preferably includes an OS transistor. Since the off-state current of an OS transistor is extremely small, the OS transistor is suitable as a transistor constituting an analog memory of the product-sum circuit. Note that the product-sum circuit may be configured using both a Si transistor and an OS transistor.

[0241] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0242] (Embodiment 3) In this embodiment, a transistor that can be used in an imaging device of one embodiment of the present invention will be described, particularly a transistor including an oxide semiconductor (OS transistor).

[0243] The semiconductor material used for an OS transistor can be a metal oxide with an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. A typical example is an oxide semiconductor containing indium, such as CAAC-OS or CAC-OS, which will be described later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors that prioritize reliability. Furthermore, CAC-OS exhibits high mobility, making it suitable for transistors that operate at high speed.

[0244] Because of the large energy gap of the semiconductor layer, OS transistors exhibit extremely low off-state currents of a few yA / μm (current value per 1 μm of channel width). Furthermore, unlike Si transistors, OS transistors have characteristics such as the absence of impact ionization, avalanche breakdown, and short-channel effects, making them suitable for the formation of high-voltage, highly reliable circuits. Furthermore, OS transistors are less susceptible to variations in electrical characteristics due to non-uniformity in crystallinity, which is a problem with Si transistors.

[0245] The semiconductor layer of the OS transistor can be, for example, a film represented by an In-M-Zn oxide containing indium, zinc, and M (M is one or more metals selected from aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, hafnium, and the like). The In-M-Zn oxide can be formed by, for example, a sputtering method, an atomic layer deposition (ALD) method, or a metal organic chemical vapor deposition (MOCVD) method.

[0246] When forming an In-M-Zn oxide film by sputtering, the atomic ratio of the metal elements in the sputtering target preferably satisfies In≧M and Zn≧M. The atomic ratios of the metal elements in such sputtering targets are preferably In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=10:1:3, etc. The atomic ratios of the semiconductor layer to be formed can vary within ±40% of the atomic ratios of the metal elements contained in the sputtering target.

[0247] The semiconductor layer is made of an oxide semiconductor with a low carrier density. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 or less, more preferably 1 × 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 or less, more preferably 1 × 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 The above-described oxide semiconductors can be used. Such oxide semiconductors are called high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. Such oxide semiconductors have a low density of defect states and stable characteristics.

[0248] Note that the present invention is not limited to these, and an oxide semiconductor having an appropriate composition may be used depending on the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0249] When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen vacancies increase, resulting in n-type conductivity. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0250] In addition, when an alkali metal or alkaline earth metal is bonded to an oxide semiconductor, it may generate carriers, which may increase the off-state current of a transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0251] Furthermore, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons acting as carriers are generated, increasing the carrier density and making the semiconductor layer more likely to be n-type. As a result, transistors using oxide semiconductors that contain nitrogen tend to have normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0252] Furthermore, if hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it may react with oxygen bonded to metal atoms to form water, which may form oxygen vacancies in the oxide semiconductor. If oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies may function as donors and generate electrons that serve as carriers. Furthermore, some of the hydrogen may bond with oxygen that is bonded to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to exhibit normally-on characteristics.

[0253] A defect in which hydrogen is introduced into an oxygen vacancy can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, oxide semiconductors are sometimes evaluated using carrier concentration instead of donor concentration. Therefore, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as "donor concentration."

[0254] Therefore, it is preferable that the hydrogen concentration in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0255] The semiconductor layer may also have a non-single-crystal structure. Examples of the non-single-crystal structure include a c-axis aligned crystalline oxide semiconductor (CAAC-OS) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, and an amorphous structure. Among non-single-crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0256] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain any crystalline components, or an amorphous oxide film has, for example, a completely amorphous structure and does not contain any crystalline parts.

[0257] The semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single-crystal structure region. The mixed film may have a single layer structure or a multilayer structure including two or more of the above-mentioned regions.

[0258] The following describes the structure of a cloud-aligned composite (CAC)-OS, which is one type of non-single-crystal semiconductor layer.

[0259] CAC-OS is a material in which, for example, elements constituting an oxide semiconductor are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0260] The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0261] For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be particularly referred to as CAC-IGZO) is an indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or indium zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into mosaics, and the mosaic InO X1 , or In X2 Zn Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter also referred to as a cloud-like structure).

[0262] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the first region is said to have a higher In concentration than the second region.

[0263] IGZO is a common name and may refer to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number).

[0264] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure, where multiple IGZO nanocrystals are aligned along the c-axis and connected without being aligned in the ab-plane.

[0265] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. CAC-OS is a material structure containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern. Therefore, the crystal structure is a secondary element in CAC-OS.

[0266] Note that CAC-OS does not include a stacked structure of two or more films with different compositions, such as a two-layer structure consisting of a film mainly containing In and a film mainly containing Ga.

[0267] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In some cases, a clear boundary between the region where the main component is the chromatic aberration and the region where the chromatic aberration is the main component may not be observed.

[0268] When one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium are contained instead of gallium, the CAC-OS has a structure in which some regions observed to be nanoparticles containing the metal element as the main component and some regions observed to be nanoparticles containing In as the main component are randomly dispersed in a mosaic pattern.

[0269] The CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When the CAC-OS is formed by a sputtering method, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the better. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0270] CAC-OS has the characteristic that no clear peaks are observed when measured using the θ / 2θ scan by the out-of-plane X-ray diffraction (XRD) method, which indicates that the ab-plane and c-axis orientations of the measured region are not observed.

[0271] In addition, an electron beam diffraction pattern of CAC-OS obtained by irradiating it with an electron beam (also called a nanobeam electron beam) with a probe diameter of 1 nm shows a bright ring-shaped region with multiple bright spots within the ring-shaped region. This electron beam diffraction pattern indicates that the CAC-OS has a nano-crystal (nc) structure with no orientation in the planar or cross-sectional directions.

[0272] For example, in the case of CAC-OS made of In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) revealed that GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 It can be seen that the region where the main component is the crystalline silicon is unevenly distributed and mixed.

[0273] CAC-OS has a different structure from IGZO compounds, in which metal elements are uniformly distributed, and has different properties from IGZO compounds. X3 The region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 The structure is such that the regions are separated into a mosaic of regions each containing one of the elements as the main component and a region each containing one of the elements as the main component.

[0274] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 When carriers flow through the region where In is the main component, the conductivity of the oxide semiconductor is exhibited. X2 Zn Y2 O Z2 , or InO X1 When the region mainly composed of is distributed in a cloud-like shape in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0275] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InOX1 This region has higher insulating properties than the region where GaO is the main component. X3 When a region containing the above as a main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0276] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation due to X2 Zn Y2 O Z2 , or InO X1 The conductivity due to the gate insulating layer and the gate insulating layer work in a complementary manner, resulting in a high on-state current (I on ), and high field-effect mobility (μ) can be achieved.

[0277] Furthermore, semiconductor elements using CAC-OS have high reliability, making CAC-OS suitable as a constituent material for various semiconductor devices.

[0278] (Fourth embodiment) In this embodiment, a package and a module using the imaging device of one embodiment of the present invention will be described.

[0279] 23A1 is a perspective view of the top surface of a package containing an image sensor chip. The package includes a package substrate 410 for fixing an image sensor chip 450 (see FIG. 23A3), a cover glass 420, and an adhesive 430 for bonding the two together.

[0280] 23A2 is a perspective view of the underside of the package. The underside of the package has a BGA (Ball Grid Array) with solder balls as bumps 440. It should be noted that the package is not limited to a BGA, and may also have an LGA (Land Grid Array) or a PGA (Pin Grid Array), etc.

[0281] 23A3 is a perspective view of the package, with the cover glass 420 and part of the adhesive 430 omitted. Electrode pads 460 are formed on the package substrate 410, and are electrically connected to the bumps 440 via through holes. The electrode pads 460 are electrically connected to the image sensor chip 450 by wires 470.

[0282] 23B1 is a perspective view of the top surface of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 for fixing an image sensor chip 451 (see FIG. 23B3), a lens cover 421, and a lens 435. An IC chip 490 (see FIG. 23B3) having functions such as a drive circuit and a signal conversion circuit for the imaging device is also provided between the package substrate 411 and the image sensor chip 451, forming a SiP (System in Package) configuration.

[0283] 23B2 is a perspective view of the appearance of the underside of the camera module. The underside and side surfaces of package substrate 411 have a QFN (quad flat no-lead package) configuration with mounting lands 441 provided. Note that this configuration is just one example, and a QFP (quad flat package) or the aforementioned BGA may also be provided.

[0284] 23B3 is a perspective view of the module, omitting a portion of lens cover 421 and lens 435. Land 441 is electrically connected to electrode pad 461, and electrode pad 461 is electrically connected to image sensor chip 451 or IC chip 490 by wire 471.

[0285] By housing the image sensor chip in a package of the above-described type, it becomes easy to mount the image sensor chip on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0286] (Embodiment 5) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with a recording medium, mobile phones, game consoles including portable types, portable data terminals, e-book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIGS.

[0287] 24A illustrates an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor in the display portion 982. Any operation, such as making a call or inputting characters, can be performed by touching the display portion 982 with a finger or a stylus. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the mobile phone, and infrared images can be acquired in addition to color images.

[0288] 24B shows a portable data terminal including a housing 911, a display portion 912, a speaker 913, a camera 919, and the like. Information can be input and output using a touch panel function of the display portion 912. Characters and the like can be recognized from an image acquired by the camera 919 and output as voice through the speaker 913. The imaging device and an operating method thereof according to one embodiment of the present invention can be applied to the portable data terminal, and infrared images can be acquired in addition to color images.

[0289] FIG. 24C shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism and can be installed on the ceiling to capture images of the entire surroundings. The imaging device and its operating method according to one embodiment of the present invention can be applied to the elements for acquiring images in the camera unit, and infrared images can be acquired in addition to color images. Note that the term "surveillance camera" is a common name and is not intended to limit the application. For example, a device that functions as a surveillance camera is also called a camera or a video camera.

[0290] 24D shows a video camera including a first housing 971, a second housing 972, a display unit 973, operation keys 974, a lens 975, a connection unit 976, a speaker 977, a microphone 978, and the like. The operation keys 974 and the lens 975 are provided in the first housing 971, and the display unit 973 is provided in the second housing 972. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this video camera, and infrared light images can be acquired in addition to color images.

[0291] 24E shows a digital camera including a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device and the operating method of one embodiment of the present invention can be applied to this digital camera, and an infrared image can be acquired in addition to a color image.

[0292] 24F shows a wristwatch-type information terminal including a display unit 932, a housing / wristband 933, a camera 939, and the like. The display unit 932 includes a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 are flexible and therefore easily worn on the body. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this information terminal, and infrared images can be acquired in addition to color images.

[0293] 25A illustrates an external view of an automobile as an example of a moving object. FIG. 25B is a simplified diagram of data exchange within the automobile. The automobile 890 includes a plurality of cameras 891 and the like. The imaging device of one embodiment of the present invention can be applied to the cameras 891. The automobile 890 also includes various sensors (not shown), such as infrared radar, millimeter-wave radar, and laser radar.

[0294] In an automobile 890, an integrated circuit 893 can be used for a camera 891 or the like. The automobile 890 processes a plurality of images acquired by the camera 891 in a plurality of imaging directions 892 in the integrated circuit 893, and analyzes the plurality of images collectively by a host controller 895 or the like via a bus 894 or the like, thereby determining the surrounding traffic conditions, such as the presence or absence of guardrails or pedestrians, and can perform automatic driving. The automobile 890 can also be used in systems that provide road guidance, hazard prediction, etc.

[0295] In the automobile 890, the obtained image data can be subjected to arithmetic processing such as neural networks to perform processes such as increasing the image resolution, reducing image noise, facial recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reduction of reflected glare.

[0296] Although an automobile has been described above as an example of a moving body, the automobile may be any of an automobile having an internal combustion engine, an electric automobile, a hydrogen-powered automobile, and the like. Furthermore, the moving body is not limited to an automobile. For example, moving bodies may include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and a system using artificial intelligence can be provided to these moving bodies by applying a computer according to one embodiment of the present invention.

[0297] FIG. 25C shows an external view of an on-vehicle imaging camera.

[0298] The imaging camera of Fig. 25C can also be called a drive recorder. The imaging camera shown in Fig. 25C has a housing 861, a lens 862, a support portion 863, etc. By attaching double-sided tape or the like to the support portion 863, the imaging camera can be installed on the windshield, hood, rearview mirror support portion, etc. of an automobile. Note that the shapes and sizes of the support portion 863, housing 861, and lens are not limited to the configurations shown in Fig. 25C and can be changed as appropriate to suit the installation location.

[0299] The imaging device of one embodiment of the present invention can be applied inside the imaging camera in Fig. 25C. In addition, driving images can be recorded and stored inside the imaging camera or in a storage device mounted on the vehicle.

[0300] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification. [Explanation of symbols]

[0301] 10: Imaging device: 11a, 11b, 11, 12: Functional layer: 13B, 13G, 13IR, 13R: Plug: 14, 15: Insulating layer: 16a, 16b: Opening: 17: Insulating layer: 18: Microlens array: 20B, 20G, 20IR, 20R, 20UV: Light receiving element: 21a: Buffer layer: 21b: Active layer: 21c: Buffer layer: 21B, 21G, 21IR, 21R: Photoelectric conversion layer: 22, 23, 24: Conductive layer: 31, 32: Transistor: 40: Light receiving element: 41, 42, 43: Region: 51: Silicon substrate: 52, 53: Insulating layer: 54: Semiconductor layer: 55, 56: Silicon substrate: 57: Insulating layer: 61a, 61b, 62a, 62b, 63a, 63b, 64a, 64b, 65a, 65b: Transistor: 71: Gate electrode: 72: Gate insulating layer: 73: Source region: 74: Drain region: 75: Source electrode: 76: Drain electrode: 77: Semiconductor layer: 78: Back gate: 81: Plug: 82, 83: Insulating layer: 84, 85: Plug: 86: Insulating layer

Claims

1. a first light receiving element, a second light receiving element, a third light receiving element, a fourth light receiving element, a first functional layer, and a second functional layer; the first light receiving element is a photoelectric conversion element sensitive to light of a first wavelength, the second light receiving element is a photoelectric conversion element sensitive to light of a second wavelength, the third light receiving element is a photoelectric conversion element sensitive to light of a third wavelength, the fourth light receiving element is a photoelectric conversion element sensitive to light of a fourth wavelength, the first functional layer includes a first transistor having a function as a first transfer transistor and a second transistor having a function as a second transfer transistor; the second functional layer includes a third transistor having a function as a first amplifying transistor and a fourth transistor having a function as a second amplifying transistor; the first functional layer, the fourth light receiving element, the third light receiving element, the second light receiving element, and the first light receiving element are stacked in this order on the second functional layer; the first light-receiving element, the second light-receiving element, and the third light-receiving element each have a stacked structure in which a first conductive layer, a first buffer layer, a photoelectric conversion layer, a second buffer layer, and a second conductive layer are stacked in this order; the photoelectric conversion layer contains an organic compound, the first buffer layer and the second buffer layer each contain a metal or an organic compound; the fourth light-receiving element has a p-type region and a first n-type region disposed in a first silicon substrate; each of the first transistor and the second transistor has a channel formation region in the first silicon substrate; one of a source and a drain of the first transistor is electrically connected to the first conductive layer of any one of the first light-receiving element, the second light-receiving element, and the third light-receiving element via a second n-type region disposed in the first silicon substrate; one of a source and a drain of the second transistor is electrically connected to the first n-type region; the first n-type region overlaps with a channel formation region of the second transistor; a gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor; a gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor; Imaging device.

2. In claim 1, each of the third transistor and the fourth transistor has a channel formation region in a second silicon substrate; Imaging device.

3. In claim 1 or claim 2, having a plug, the plug electrically connects one of the source and the drain of the first transistor to the first conductive layer of the first light-receiving element; the photoelectric conversion layer of the second light receiving element has a first opening, the second conductive layer of the second light receiving element has a second opening; the plug has a portion in contact with the photoelectric conversion layer inside the first opening, the plug has a portion located inside the second opening and does not contact the first conductive layer and the second conductive layer of the second light-receiving element; Imaging device.

4. In any one of claims 1 to 3, having a plug, the plug electrically connects one of the source and the drain of the first transistor to the first conductive layer of the first light-receiving element; the photoelectric conversion layer of the second light receiving element has a first opening, the second conductive layer of the second light receiving element has a second opening; the plug has a portion located inside the first opening and a portion located inside the second opening, and is not in contact with the first conductive layer, the photoelectric conversion layer, and the second conductive layer of the second light-receiving element; Imaging device.

5. In any one of claims 1 to 4, any three of the light of the first wavelength, the light of the second wavelength, the light of the third wavelength, and the light of the fourth wavelength are visible light, and the remaining one is infrared light or ultraviolet light; Imaging device.

6. In any one of claims 1 to 5, The order of wavelengths from shortest to largest is the first wavelength, the second wavelength, the third wavelength, and the fourth wavelength. Imaging device.

Images