Dynamic Load Balancing for Real-Time Deep Learning Analytics

Abstract

In at least one embodiment, operations performed on a batch of frames of video (e.g., as part of a video analytics pipeline) are distributed between a first hardware accelerator and a second hardware accelerator by a load balancer.

Description

[Technical Field]

[0001] This application claims the benefit of U.S. Patent Application No. 17 / 330,710, filed May 26, 2021, entitled "DYNAMIC LOAD BALANCING OF OPERATIONS FOR REAL-TIME DEEP LEARNING ANALYTICS," and U.S. Provisional Application No. 63 / 060,666, filed August 3, 2020, entitled "DYNAMIC LOAD BALANCING ON GPUS FOR DEEP LEARNING BASED REAL-TIME VIDEO ANALYTICS APPLICATIONS," the entire contents of which are incorporated herein by reference. [Background technology]

[0002] A typical video analytics application consists of multiple processing elements operating in parallel and generating portions of the information for the overall application. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and previous and new editions of this standard) Summary of the Invention [Problem to be solved by the invention]

[0004] However, many of the processing elements have specific requirements regarding the resolution and format of the video frames. This results in several transformations (e.g., scaling, format conversion, camera correction, dewarping, etc.) that must be performed on the video frames throughout their lifetime in the processing pipeline. Furthermore, each element must finish processing its workload (e.g., a batch of video frames) within a certain amount of time, on average. Failure to complete processing on time can lead to delays in processing and, ultimately, to periodic dropping of video frames in order to keep up with the input video frame rate. This can lead to a loss of information and / or a failure to perform some operations (e.g., in real time). [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 illustrates an example of load balancing between hardware accelerators, according to at least one embodiment. [Figure 2] FIG. 1 illustrates an example deep learning video analysis pipeline utilizing load balancing between hardware accelerators, according to at least one embodiment. [Figure 3] FIG. 10 illustrates an example of a table used to track information during load balancing between hardware accelerators, according to at least one embodiment. [Figure 4] 10 is a flow diagram from load balancing between hardware accelerators, according to at least one embodiment. [Figure 5A] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 5B] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 6]FIG. 1 illustrates neural network training and deployment, according to at least one embodiment. [Figure 7] FIG. 1 illustrates an exemplary data center system, according to at least one embodiment. [Figure 8A] FIG. 1 illustrates an example of an autonomous vehicle, according to at least one embodiment. [Figure 8B] FIG. 8B illustrates an example of camera locations and fields of view for the autonomous vehicle of FIG. 8A, according to at least one embodiment. [Figure 8C] FIG. 8B is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 8A, according to at least one embodiment. [Figure 8D] FIG. 8B illustrates a system for communication between cloud-based server(s) and the autonomous vehicle of FIG. 8A, according to at least one embodiment. [Figure 9] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 10] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 11] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 12] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 13A] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 13B] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 13C] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 13D] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 13E] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 13F]FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 14] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor according to at least one embodiment. [Figure 15A] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor according to at least one embodiment. [Figure 15B] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor according to at least one embodiment. [Figure 16A] FIG. 10 illustrates additional exemplary graphics processor logic according to at least one embodiment. [Figure 16B] FIG. 10 illustrates additional exemplary graphics processor logic according to at least one embodiment. [Figure 17] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 18A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 18B] FIG. 1 illustrates a partition unit, according to at least one embodiment. [Figure 18C] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 18D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 19] FIG. 1 illustrates a multi-graphics processing unit (GPU) system according to at least one embodiment. [Figure 20] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 21] FIG. 1 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment. [Figure 22]FIG. 1 illustrates a deep learning application processor, according to at least one embodiment. [Figure 23] FIG. 1 is a block diagram illustrating an example neuromorphic processor, according to at least one embodiment. [Figure 24] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 25] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 26] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 27] FIG. 1 is a block diagram of a graphics processing engine of a graphics processor, according to at least one embodiment. [Figure 28] FIG. 1 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment. [Figure 29A] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 29B] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 30] FIG. 1 illustrates a parallel processing unit (“PPU”) according to at least one embodiment. [Figure 31] FIG. 1 illustrates a general processing cluster (“GPC”) according to at least one embodiment. [Figure 32] FIG. 1 illustrates a memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment. [Figure 33] FIG. 1 illustrates a streaming multiprocessor according to at least one embodiment. [Figure 34]FIG. 1 illustrates an exemplary data flow diagram for an advanced computing pipeline, according to at least one embodiment. [Figure 35] FIG. 1 is a system diagram for an exemplary system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment. [Figure 36] FIG. 35 includes an exemplary diagram of an advanced computing pipeline 3510A for processing imaging data, according to at least one embodiment. [Figure 37A] FIG. 10 includes an exemplary data flow diagram of a virtual instrument supporting an ultrasound device, according to at least one embodiment. [Figure 37B] FIG. 10 includes an exemplary data flow diagram of a virtual device supporting a CT scanner, according to at least one embodiment. [Figure 38A] FIG. 1 is a data flow diagram for a process for training a machine learning model, according to at least one embodiment. [Figure 38B] FIG. 1 is an exemplary diagram of a client-server architecture for extending an annotation tool with pre-trained annotation models, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] Embodiments of the present disclosure provide a novel solution for overcoming manual tuning and / or configuration of transformations, reducing bottlenecks, and improving stream density by implementing a load balancer to distribute work across available hardware accelerators, including various hardware accelerators described in more detail below. In one embodiment, the load balancer is used to improve the performance of one or more AI pipelines that include cascaded neural networks and computer vision (CV) algorithms that require different formats and frame resolutions as input. In various embodiments, the load balancer distributes work (e.g., operations to be performed on batches of N frames comprising frames from one or more video inputs, such as cameras or video files) among multiple hardware accelerators to increase efficiency, enable real-time applications, prevent bottlenecks, and reduce underutilization of computing resources. In one example, the load balancer processes work from one or more components of a video analytics pipeline to increase stream processing density, thereby enabling the video analytics pipeline to be deployed in real-time applications. In various embodiments, the hardware accelerator includes other hardware such as a video image compositor (VIC), a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), or a field programmable gate array (FPGA). For example, a load balancer (e.g., a process performed by a CPU) can distribute work to one or more VICs, one or more DPUs, and one or more GPUs to perform various operations of an application.

[0007] In various embodiments, the operations include operations of an application executed by a computing device. In one example, the application includes a deep learning (DL) pipeline that takes video as input and performs video analysis (e.g., object detection, classification, etc.). In such an example, various components of the DL pipeline have distinct requirements for processing the video (e.g., batches of frames of video). For example, the DL pipeline may include neural networks that require specific formats, resolutions, color spaces, or other requirements. To meet these requirements, various operations are performed on the video and / or batches of frames of video to enable processing by the various components of the DL pipeline, according to at least one embodiment. For example, the operations may include image scaling, color space conversion, gamma correction, image conversion, camera correction (e.g., removing fisheye effect / lens distortion, dewarping 360-degree camera frames, etc.), or any other operation to enable the video to be processed.

[0008] Thus, in various embodiments, the load balancer distributes the performance of operations among the hardware accelerators. Further, in various embodiments, the load balancer is application and / or user agnostic and does not require tuning and / or configuration. In one example, the load balancer transparently distributes operations based at least in part on various factors, such as the current load on the hardware accelerator, compute requirements, the percentage of hardware accelerator usage, deadlines associated with the operations, or other factors. Further, in one embodiment, the load balancer includes various preferences and / or configurations. For example, the load balancer may include a particular hardware accelerator, a preferred hardware accelerator, a usage limit associated with the preferred hardware accelerator for a particular operation, a per-process usage limit, and other configurations.

[0009] In various embodiments, the load balancer assigns a client identification number to an application and / or a component of an application. As described in more detail below, the client identification number, in one embodiment, includes information identifying the client (e.g., application, process, or other component) that submits work to be performed by the hardware accelerator. In various embodiments, the load balancer maintains a table of clients, including the hardware accelerators assigned to perform work submitted by the clients and the average time required to perform the work for the various hardware accelerators. In one example, all of the clients are assigned to a VIC after a time interval, and the average time required to perform the work is determined. In such an example, if the average time required to perform the work exceeds a threshold, the client is assigned to a different hardware accelerator, such as a GPU. In various embodiments, this process is repeated until the average time for all clients falls below the threshold. As described in more detail below, the threshold, according to at least one embodiment, may be determined at least in part based on various factors, such as the video frame rate and / or frame processing deadline. In various embodiments, the load balancer determines whether one or more clients can be reassigned to a VIC after a time interval. In one example, if the average time for clients assigned to a VIC falls below a threshold, the load balancer determines one or more clients assigned to other hardware accelerators to reassign to a VIC. In various embodiments, the load balancer determines one or more clients to reassign to a VIC based at least in part on various factors, such as the load on other hardware accelerators due to the clients, whether processing work will be faster on the VIC, or other factors.The load balancer, in one embodiment, distributes load (e.g., work generated by clients) cyclically or aperiodically among multiple hardware accelerators, such as VICs and GPUs.

[0010] In the above and following descriptions, various techniques are described. For purposes of explanation, specific configurations and details are set forth to provide a thorough understanding of possible ways to implement the techniques. However, it will also be apparent that the techniques described below may be practiced in different configurations without the specific details. Additionally, well-known features may be omitted or simplified to avoid obscuring the techniques being described.

[0011] The techniques described and suggested in this disclosure may improve the field of load balancing between hardware accelerators, particularly within the context of performing deep learning with limited computing resources, by providing a system for load balancing between hardware accelerators to increase system efficiency. Additionally, the techniques described and suggested in this disclosure may improve the speed of execution of deep learning pipelines, video analytics, and other applications that utilize hardware acceleration on various computing systems. Moreover, the techniques described and suggested in this disclosure are necessarily rooted in computer technology to overcome problems that arise, particularly with respect to performing deep learning analytics in real time with limited computing resources.

[0012] FIG. 1 illustrates an environment 100 in which a load balancer 104 distributes work units 120 among hardware accelerators, according to at least one embodiment. In various embodiments, one or more clients 106A-106C provide one or more work units 120 to a processor 102. For example, one or more clients 106A-106C include threads of a set of applications, such as a video analytics pipeline 108 or other applications executed by the processor. In various embodiments, the video analytics pipeline 108 includes a deep learning pipeline, such as described in more detail below with respect to FIG. 2. Furthermore, in various embodiments, the components of the environment 100 (e.g., processor 102, hardware accelerators, etc.) are components of a computer system, such as computer system 1100, described in more detail below with respect to FIG. 11. Furthermore, in various embodiments, the processor 102 includes various computing resources (e.g., one or more circuits), described in more detail below, such as processor 1010, described in more detail below with respect to FIG. 10.

[0013] In various embodiments, the processor 102 executes a load balancer 104. In one embodiment, the load balancer 104 is an application or other executable code that, when executed by the processor 102, causes work units to be distributed between the first hardware accelerator 110 and the second hardware accelerator 112. In various embodiments, the first hardware accelerator 110 and the second hardware accelerator 112 include other hardware, such as a video image compositor (VIC), a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA) or a data processing unit (DPU). Additionally, as shown in FIG. 1 , the first hardware accelerator 110 and the second hardware accelerator 112, in various embodiments, include multiple hardware accelerators. For example, environment 100 includes three VICs (e.g., first hardware accelerator 110) and three GPUs (e.g., second hardware accelerator 112). In various embodiments, first hardware accelerator 110 and / or second hardware accelerator 112 represent a class and / or type of computational resource (e.g., GPU, CPU, VIC, FPGA, DPU, or other circuitry). As described in more detail below, load balancer 104 includes a set of logic and / or heuristics (e.g., programming logic) for distributing work units 120 across first hardware accelerator 110 and / or second hardware accelerator 112. For example, the load balancer 104 may distribute work units 120 to a first hardware accelerator 110, and then, upon detecting that the first hardware accelerator 110 is overloaded (e.g., increasing latency, utilization, etc.), the load balancer 104 may distribute at least a portion of the work units 120 to a second hardware accelerator 112.

[0014] As described in more detail below, in one embodiment, the load balancer 104 determines the load on the first hardware accelerator 110 and / or the second hardware accelerator 112 at the expiration of a time interval and assigns one or more clients 106A-106C to a particular hardware accelerator. In various embodiments, the first hardware accelerator 110 and / or the second hardware accelerator 112 include various processing units, such as GPUs, which are described in more detail below with respect to FIGS. 13A-13F. In various embodiments, the work unit 120 includes conversion and / or compositing of a batch of frames of video. For example, the batch of frames may include 10 frames from a video file, video stream, camera, or other video source. Further, as described in this disclosure, conversion, according to one embodiment, includes various operations such as converting a video frame and / or image from a first format to a second format, scaling a video frame and / or image (e.g., increasing, decreasing, or otherwise modifying the resolution), modifying the color space of a video frame and / or image, or modifying one or more other attributes of a video frame and / or image. In one embodiment, work unit 120 operates on a set of input pixels (e.g., an input video frame and / or image). For example, a VIC processes several input pixels per processor cycle.

[0015] In various embodiments, the load balancer 104 generates or otherwise obtains statistics related to one or more clients 106A-106C, applications (e.g., applications executed by the processor 102 or other systems communicatively coupled to the processor 102), work units 120, hardware accelerators (e.g., the first hardware accelerator 110 and / or the second hardware accelerator 112), or other components of the environment 100. For example, as shown in FIG. 3 below, the load balancer 104 maintains a table containing statistical information, such as the average amount of time required to process one or more work units 120. In various embodiments, the load balancer 104 includes a set of heuristics that include actions to take based at least in part on the statistical information. In one example, if the average time required to process a particular work unit 120 exceeds a threshold, a heuristic in the set of heuristics indicates moving a particular client to a different hardware accelerator. In various embodiments, the set of heuristics defines a policy for balancing the load among the hardware accelerators, and in other embodiments, the set of heuristics is implemented as rules or other logic that causes the load balancer 104 to perform various actions described in this disclosure.

[0016] Additionally, in one embodiment, the load balancer 104 is agnostic to one or more users associated with an application. According to at least one embodiment, the load balancer 104 obtains transformation information based at least in part on application programming interface (API) calls generated by one or more clients 106A-106C. For example, the client 106A submits an API call to convert a batch of frames from a first format to a second format. In another example, the client 106A submits an API call to scale the batch of frames. Thus, in various embodiments, the load balancer 104 maintains information related to a set of transformation and / or other operation requests by one or more clients 106A-106C. Additionally, in various embodiments, the load balancer 104 maintains historical statistical compute requirements of various transformations performed on various hardware accelerators (e.g., GPUs and / or VICs). In one example, the load balancer 104 maintains statistical metrics (e.g., average, minimum, maximum, etc.) for all transformations (e.g., scaling, conversion, camera correction, color correction, etc.) for one or more clients 106A-106B. In another example, the load balancer maintains a rolling average of the amount of time it takes a hardware accelerator to perform a transformation (e.g., the last N transformations performed).

[0017] Additionally, in one embodiment, the load balancer 104 determines or otherwise obtains (e.g., through a system call or other mechanism) the current load of the first hardware accelerator 110 and / or the second hardware accelerator 112. In one example, the load balancer 104 estimates the load of a particular hardware accelerator based at least in part on maintained statistical information (e.g., current processing time versus historical processing time). In another example, the load balancer 104 obtains the load information directly from the hardware accelerators.

[0018] In various embodiments, the load balancer distributes the transformations and / or operations across the hardware accelerators (e.g., the first hardware accelerator 110 and / or the second hardware accelerator 112) based at least in part on various factors, such as the current load of the first hardware accelerator 110 and / or the second hardware accelerator 112, the compute requirements for the particular transformation and / or operation, the utilization rate of the first hardware accelerator 110 and / or the second hardware accelerator 112, information indicating deadlines for completing the particular transformation and / or operation, or other information related to the components shown in the environment 100. In one example, the transformations and / or operations are distributed transparently (e.g., without input or notification to the clients 106A-106C or other applications and / or users). In various embodiments, the load balancer 104 includes configuration information that can be modified by a user. In one example, a user and / or application modifies the load balancer's configuration information to provide a usage limit (e.g., a threshold percentage of load that should remain below) for a particular hardware accelerator. In various embodiments, other configuration information includes a particular transformation, a processing deadline, a preferred hardware accelerator for distribution, or other options for controlling the implementation of the transformation and / or operation.

[0019] In one embodiment, the load balancer 104 utilizes the first hardware accelerator 110 as the preferred hardware accelerator for all or a portion of the work units 120 (e.g., transformations). In one example, if the first hardware accelerator is a VIC, the load balancer 104 initially allocates all of the work units 120 to the VIC (e.g., load) until the load balancer 104 determines that the utilization of the VIC (e.g., load) exceeds a threshold. In various embodiments, if a utilization percentage (e.g., a percentage of the maximum amount of computation that can be performed) of a hardware accelerator is unavailable, the load balancer 104 utilizes a proxy for utilization percentage, such as a frame processing deadline (e.g., the maximum amount of time a hardware accelerator can take before causing delays in an application or a particular client), to determine whether to reallocate the load (e.g., move an incoming work unit 120 to the second hardware accelerator 112). In one example, the frame processing deadline depends on the video processing frame rate associated with the video analytics pipeline 108 (e.g., approximately 33 milliseconds for a 30 frames per second video stream). In various embodiments, the load balancer 104 assigns clients among one or more clients 106A-106C. For example, the load balancer 104 assigns client 106A to a first hardware accelerator 110, such that all of the work units 120 provided by client 106A are assigned to the first hardware accelerator 110 until the load balancer 104 determines to assign client 106A to a second hardware accelerator 112. As shown in FIG. 3 , the load balancer 104 maintains a table of clients, their assigned hardware accelerators, and the average time it takes to process work units provided by the clients to the hardware accelerators (e.g., if available).

[0020] In various embodiments, the load balancer 104 determines the time required to complete a work unit 120 (e.g., a transformation requested in an API call) for an API call received from one or more clients 106A-106C. Furthermore, in such embodiments, the time required includes both the amount of time spent in the execution queue as well as the amount of time spent during execution. In one example, the average time required is calculated over a moving window of transformations (e.g., the last N transformations, where N=4). In one embodiment, a processor thread associated with the load balancer 104 wakes up after the expiration of the time interval and determines a hardware accelerator (e.g., the first hardware accelerator 110 and / or the second hardware accelerator 112) for one or more clients 106A-106C based at least in part on the table and the frame processing deadline, and reallocates the hardware accelerator (e.g., the first hardware accelerator 110 and / or the second hardware accelerator 112) to one or more clients 106A-106C. For example, the load balancer 104 reallocates the hardware accelerator to one or more clients 106A-106C to maximize utilization and / or meet the frame processing deadline.

[0021] In various embodiments, the load balancer 104 obtains usage information (e.g., activity, rate, load, utilization, etc.) related to the hardware accelerators through system calls, web sockets, or other communications and uses the usage information to determine load balancing actions (e.g., assigning clients 106A-106C to hardware accelerators). In one embodiment, the load balancer 104 implements per-process and / or per-client limits on hardware accelerator usage for work units 120 (e.g., transformations). Additionally, the load balancer 104, in various embodiments, receives requests from applications for information related to the clients 106A-106C (e.g., client context, client ID, or other identifying information) from the load balancer 104. In response to this information, the application, in one embodiment, can cause the load balancer 104 to assign a particular client to a particular hardware accelerator, prevent the load balancer 104 from assigning a particular client to a particular hardware accelerator, or allow a particular client to be assigned to any hardware accelerator.

[0022] In various embodiments, the load balancer 104 executes as a separate and / or dedicated process or as a separate thread within an application process executed by the processor 102. Additionally, one or more clients 106A-106C, in one embodiment, request a particular hardware accelerator to process a work unit 120 from the load balancer 104 via interprocess communication (IPC). In such embodiments, execution is triggered by one or more clients 106A-106C, and the one or more clients 106A-106C report execution details back to the load balancer 104 via IPC. In such embodiments, as one or more clients 106A-106C trigger execution of a work unit 120 and communicate with the load balancer 104, the load balancer 104 determines or otherwise obtains statistical data. The statistical data may include, for example, the amount of load on a hardware accelerator and the total amount of load a particular client is generating on a hardware accelerator. Additionally, in various embodiments, statistical data is maintained for each client and for each hardware accelerator, including the average amount of load generated by work units submitted by a client that run on a particular hardware accelerator and the average amount of time required to execute work units submitted by a client that run on a particular hardware accelerator. In various embodiments, the statistical data is sampled at various intervals. For example, the load balancer 104 may utilize both statistical data generated over the last few sampling intervals (e.g., when higher weights are applied) and historical data (e.g., when lower weights are applied).In such an embodiment, work units 120 retrieved from a particular client execute on one hardware accelerator and / or one type of hardware accelerator (e.g., whichever of the first hardware accelerator 110 and / or the second hardware accelerator 112 the load balancer assigned to the particular client) for the duration of the sampling interval. In one example, the hardware accelerator assigned to a particular client changes every sampling interval.

[0023] FIG. 2 illustrates an environment 200 in which a parallel processing pipeline executes, according to at least one embodiment. In various embodiments, the parallel processing pipeline includes a video analytics pipeline 108, such as that described with reference to FIG. 1, a deep learning pipeline, an artificial intelligence pipeline, or any other pipeline in which the operations of the pipeline may be performed in parallel. In one example, the parallel processing pipeline performs real-time streaming video analysis. In such an example, a video analytics application (e.g., an application executing all or a portion of the parallel processing pipeline) comprises multiple processing elements that operate in parallel and are responsible for generating data or other information for use in the application. As shown in FIG. 2, the parallel processing pipeline comprises multiple components (e.g., a video source 202, video converters 204A and 204B, a multiplexer 206, a primary detector 208, an object tracker 210, secondary classifiers 212A-212C, and a renderer 216).

[0024] Additionally, in some embodiments, portions of the components (shown in FIG. 2 with cross-hatching) have different requirements for processing (e.g., specific resolutions or formats of video frames). For example, the primary detector 208 may require video frames in a first format, and the object tracker 210 may require video frames in a second format, which results in conversions or other processing that must be performed on the video source 202 to enable processing. Various computer systems include hardware accelerators, such as VICs and GPUs, to perform such conversions, as described in this disclosure. In various embodiments, components of a parallel processing pipeline must finish processing a work unit (e.g., a batch of video frames) within a time interval or an average amount of time (which may include padding or be otherwise extendable). In such embodiments, the amount of time to finish processing one or more work units is determined by the parallel processing pipeline architecture and the frame rate of the video source 202 and / or the video output. Failure to complete processing within a particular time interval may, in various embodiments, result in delays being introduced in the parallel processing pipeline and ultimately in the dropping of one or more frames of video in order to maintain processing of the video source 202.

[0025] In one embodiment, the parallel processing pipeline is implemented by any suitable processing system or unit (e.g., a GPU, a VIC, a parallel processing unit (PPU), a CPU, a DPU, an FPGA, etc.) and in any suitable manner, including serially, in parallel, and / or variations thereof. In various embodiments, the video source 202 comprises digital data encoding representing an image (e.g., a video). Further, the video source 202 comprises, for example, one or more images, also referred to as frames, which collectively form a video. In various embodiments, the video source 202 is implemented using any suitable digital video format, such as Advanced Video Coding (AVC), Motion Picture Experts Group (MPEG) format, and / or variations thereof. In one example, video source 202 comprises a sequence of images in any suitable raster image file format (e.g., bitmap image file, Joint Photographic Experts Group (JPEG) file) and / or vector image file format (e.g., Scalable Vector Graphics (SVG) file). Video source 202, according to various embodiments, includes compressed or uncompressed data. Furthermore, in various embodiments, video source 202 is generated by and / or acquired from one or more video and / or image capture devices, such as one or more systems, such as an autonomous vehicle, a robot, a surveillance system, a medical imaging system, a satellite imaging system, etc., as described in more detail below (e.g., FIGS. 8A-8D). Furthermore, video source 202, in one embodiment, includes files or other data stored in a storage device.Video source 202 may represent video in any suitable color scheme, such as red-green-blue (RGB), a YUV format such as NV12, black-and-white (BW), grayscale, and / or variations thereof. Additionally, video source 202 may, in various embodiments, include network-based cameras, surveillance systems, traffic cameras, industrial cameras, drones, and autonomous vehicles.

[0026] In various embodiments, the parallel processing pipeline acquires or is otherwise provided with video source 202 from one or more systems for various video and / or image capture devices. In some instances, the parallel processing pipeline is part of a system comprising video capture hardware and / or software, where the parallel processing pipeline acquires video source 202 from the video capture hardware and / or software. Video source 202 is acquired by or is otherwise provided to the system executing the parallel processing pipeline in any suitable manner, such as, for example, physically (e.g., via a wired connection to a device associated with the parallel processing pipeline), remotely (e.g., via a wireless communication network to a device associated with the parallel processing pipeline), and / or variations thereof. In various embodiments, the parallel processing pipeline includes additional, fewer, and / or alternative components. For example, the parallel processing pipeline includes a decoder for acquiring frames from compressed video source 202. In another instance, the parallel processing pipeline does not include multiplexer 206.

[0027] In various embodiments, the video conversion 204A and 204B components of the parallel processing pipeline process the video source 202 and convert it to a particular format (e.g., a requested video format or a video format required for a particular element of the parallel processing pipeline). In one embodiment, the video conversion 204A and 204B components include one or more hardware and / or software computing resources with instructions that, when executed by one or more processors, cause the system to perform one or more video processing operations. In one example, the video conversion 204A and 204B components determine frames from the video source 202 for conversion from one format to another. In some examples, if the video source 202 is compressed, the video conversion 204A component decompresses the video source 202 to determine frames of video. In yet other examples, the video source 202 includes one or more components for decompressing or otherwise decoding frames of video.

[0028] In various embodiments, the video conversion 204A component outputs frames (e.g., frames of the video source 202) to the primary detector 208. The primary detector 208, in various embodiments, processes batches of frames to detect objects within the frames. In one embodiment, the primary detector 208 includes a collection of one or more hardware and / or software computing resources having instructions that, when executed by one or more processors, cause the system to perform one or more object detection operations. The primary detector 208 may, for example, utilize various neural network models for object detection. Non-limiting examples of such neural network models may include a perceptron model, a radial basis network (RBN), an autoencoder (AE), a Boltzmann machine (BM), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a deep convolutional network (DCN), an extreme learning machine (ELM), a deep residual network (DRN), and / or variations thereof. In one example, the primary detector 208 determines features for a batch of frames. In another example, the primary detector 208 determines bounding boxes for objects depicted in one or more frames. An object, according to one embodiment, refers to any suitable entity or object of a scene depicted in one or more frames, such as a person, an environmental object, a vehicle, a robot, and / or variations thereof. Additionally, in at least one embodiment, a bounding box refers to an indication of the location and / or position of an object represented in an image, e.g., a bounding box defines a set of coordinates corresponding to the corners of a particular bounding box that encompasses all or a portion of an object depicted in one or more frames.Furthermore, a bounding box, according to one embodiment, indicates an area or region of an image (e.g., a frame) that contains a representation of an object. In various embodiments, primary detector 208 determines bounding boxes for any number of objects represented in one or more frames and outputs the bounding boxes and / or bounding box information (e.g., coordinates or other geometric information representing the bounding boxes) to object tracker 210.

[0029] In some embodiments, primary detector 208 does not determine a bounding box for each frame, but rather only determines bounding boxes for a subset of frames, where the determined bounding boxes are output to object tracker 210. In one embodiment, object tracker 210 includes a collection of one or more hardware and / or software computing resources that include instructions that, when executed by one or more processors, cause the system to perform one or more computer vision processes. Object tracker 210 executes one or more computer vision algorithms that determine bounding boxes for one or more frames based on bounding boxes of one or more previous frames and / or one or more subsequent frames, for example, to track the locations of multiple objects across adjacent frames. The primary detector 208 and / or object tracker 210, in various embodiments, are configured with a parameter (e.g., a tracking distance) that determines which frames should be processed by the primary detector 208 and / or object tracker 210. For example, the tracking distance may indicate the number of frames between frames that should be processed by the primary detector 208 and may be any suitable integer value. In another example, a tracking distance value of 0 indicates that the primary detector 208 should process every frame of the video source 202, a tracking distance value of 1 indicates that the primary detector 208 should process every other frame of the video source 202, and so on.

[0030] In various embodiments, the object tracker 210 determines bounding boxes for frames of the video source 202 that are not processed by the primary detector 208. For example, the primary detector 208 determines bounding boxes for every other frame of the video source 202 (e.g., the first frame, the third frame, the fifth frame, etc.), and the object tracker 210 determines bounding boxes for the remaining frames of the video source 202 (e.g., the second frame, the fourth frame, the sixth frame, etc.). In various embodiments, the object tracker 210 implements various object tracking processes, such as one or more kernel-based tracking processes and / or contour tracking processes, to determine a bounding box for an object in a frame based on a bounding box for that object in a previous frame and / or a bounding box for that object in a subsequent frame.

[0031] In one example, object tracker 210 determines bounding boxes for any number of objects in any suitable number of frames based on the bounding boxes determined by primary detector 208. Primary detector 208 and / or object tracker 210, in various embodiments, provide information (e.g., bounding boxes) to one or more secondary classifiers 212A-212C. The one or more secondary classifiers 212A-221C may include various neural network models trained to identify and / or classify objects depicted in images (e.g., frames), such as, for example, a perceptron model, a radial basis network (RBN), an auto-encoder (AE), a Boltzmann machine (BM), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a deep convolutional network (DCN), an extreme learning machine (ELM), a deep residual network (DRN), a logistic regression model, a naive Bayes model, a stochastic gradient descent model, a K-nearest neighbors model, a decision tree model, a random forest model, a support vector machine model, and / or variations thereof. For example, for a given frame (e.g., a frame of the video source 202) and a first bounding box representing a first object in the frame (e.g., determined by the primary detector 208 and / or the object tracker 210), a secondary classifier from one or more secondary classifiers 212A-221C determines the class of the object depicted in the bounding box.

[0032] In various embodiments, the renderer 216 generates video data, which may include information generated by the primary detector 208, the object tracker 210, and / or one or more secondary classifiers 212A-212C. In one example, the renderer 216 displays the generated video data. As described in this disclosure, components of the parallel processing pipeline require transformations of frames to generate such data. In various embodiments, these transformations are performed by a hardware accelerator, which may include various hardware processing components such as one or more PPUs, GPUs, etc. In one example, the hardware accelerator includes computer hardware specifically utilized to perform one or more processes (e.g., the transformations described above).

[0033] FIG. 3 illustrates a table 300 utilized by a load balancer to maintain usage statistics during load balancing operations. The load balancer, in various embodiments, includes the load balancer 104 described above with reference to FIG. 1. In various embodiments, the load balancer maintains a table containing information related to clients 302, the current hardware accelerator 304 assigned to a particular client, the average time taken on a first hardware accelerator 306, and the average time taken on a second hardware accelerator 308. In one example, the clients include clients 106A-106C described above with reference to FIG. 1. The information maintained in the table, in various embodiments, includes an identifier (e.g., a thread name) associated with the client. For example, an operating system assigns an identifier to a thread of an application executed by the system.

[0034] In various embodiments, the load balancer assigns a particular client (e.g., “Tracker”) to a particular hardware accelerator (e.g., “First”). As described above, a system implementing a load balancer may include multiple hardware accelerators suitable for performing operations on behalf of clients. Consequently, a particular row in table 300, in various embodiments, indicates a hardware accelerator assigned to a particular client during a first time interval 308. As described above, during a second time interval 310, in various embodiments, the load balancer determines one or more clients to assign to another hardware accelerator based at least in part on the average time taken on a particular hardware accelerator. For example, as shown in FIG. 3, during the second time interval 310, the load balancer determines to assign clients (e.g., “Tiler” and “Primary”) to a second hardware accelerator based at least in part on the average time taken on the first accelerator 306. As explained above, the average time taken includes the amount of time it takes for a set of operations (e.g., the previous four operations for a client) to be completed by the hardware accelerator.

[0035] With reference to FIG. 4, FIG. 4 is an exemplary method for load balancing among multiple hardware accelerators according to some embodiments of the present disclosure. It should be understood that this and other mechanisms described herein are provided by way of example only. Other mechanisms and elements (e.g., machines, interfaces, functions, orders, groupings of functions, etc.) may be used in addition to or instead of those shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional entities that may be implemented as separate or distributed components, or with other components, and in any suitable combination and location. Various functions described herein as being performed by entities may be performed by hardware, firmware, and / or software. For example, various functions may be performed by a processor executing instructions stored in memory. Furthermore, various functions illustrated in FIG. 4 may be performed in different orders (e.g., serially or in parallel) or omitted entirely.

[0036] Referring now to FIG. 4, each block of method 400 described herein includes a computing process that may be implemented using any combination of hardware, firmware, and / or software. For example, various functions may be performed by a processor executing instructions stored in a memory. The method may also be embodied as computer-usable instructions stored on a computer storage medium. The method may be provided as a standalone application, a service, or a hosted service (standalone or in combination with another hosted service), or as a plug-in to another product, to name a few examples. Furthermore, method 400 is illustratively described with respect to load balancer 104 of FIG. 1. However, these methods may additionally or alternatively be performed by any one system or combination of systems, including, but not limited to, those described herein.

[0037] FIG. 4 is a flow diagram illustrating a method 400 for balancing load among multiple hardware accelerators according to some embodiments of the present disclosure. Method 400 includes, at block 402, assigning a client(s) to a first hardware accelerator. The load balancer, in one embodiment, causes operations submitted by the client to be processed by the first hardware accelerator. In one example, the load balancer initially assigns the client to a VIC. As described above, in such an example, after a time interval, the average time it takes the VIC to process a transformation (e.g., perform an operation) is determined. In various embodiments, the information is maintained in a table, such as table 300 described with respect to FIG. 3.

[0038] At block 404, the load balancer, according to one embodiment, determines whether any of the clients exceed a threshold (e.g., a frame processing threshold). If one or more clients exceed the threshold, at block 406, the load balancer reallocates the clients to the second hardware accelerator. In various embodiments, the load balancer assigns the clients spending the least amount of time on the first hardware accelerator to the second hardware accelerator. In other embodiments, the load balancer assigns the clients spending the most amount of time on the first hardware accelerator to the second hardware accelerator. At block 408, the load balancer waits a time interval for the reallocation to take effect. After the time interval, the load balancer returns to block 404 to determine whether one or more clients exceed a usage threshold (e.g., for either the first hardware accelerator or the second hardware accelerator). Method 400, in various embodiments, is repeated until no clients exceed the threshold. Returning to block 404, if the average time for the clients is below the threshold, the load balancer selects one or more clients (if any) currently assigned to the second hardware accelerator to be reassigned to the first hardware accelerator in block 410. In block 412, the load balancer determines whether the selected one or more clients and / or operations (e.g., transformations) requested by the clients can be reassigned to the first hardware accelerator. If the clients can be reassigned, the load balancer reassigns the clients to the first hardware accelerator in block 414; otherwise, the load balancer continues to block 408. In various embodiments, the load balancer cannot reassign the clients to the first hardware accelerator as a result of the load balancer's configuration and / or the average amount of time it takes to process the operations.

[0039] In various embodiments, method 400 is modified. For example, an application and / or user can specify a preferred hardware accelerator(s), causing work belonging to a particular client to be assigned to the preferred hardware accelerator(s). The preference, in various embodiments, includes a ranked or ordered list. In other embodiments, clients are randomly or pseudo-randomly assigned to hardware accelerators. In other embodiments, the load balancer can still reassign clients if a threshold is not exceeded. For example, if the maximum number of clients assigned to a hardware accelerator is exceeded or if percentage utilization is exceeded. Furthermore, in various embodiments, the load balancer determines the efficiency of the hardware accelerator and assigns clients based on the efficiency. For example, if a particular hardware accelerator processes a particular transformation faster, the load balancer assigns clients requesting that particular transformation to a particular load balancer. Furthermore, in various embodiments, the load balancer throttles the application and / or one or more clients if it is unable to reassign the client.

[0040] Inference and Training Logic 5A illustrates inference and / or training logic 515 used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided below in conjunction with FIG. 5A and / or FIG. 5B.

[0041] In at least one embodiment, the inference and / or training logic 515 may include, but is not limited to, code and / or data storage 501 for storing forward and / or output weights and / or input / output data and / or other parameters for configuring neurons or layers of a neural network to be trained and / or used for inference in one or more embodiments. In at least one embodiment, the training logic 515 may include or be coupled to code and / or data storage 501 for storing graph code or other software for controlling the timing and / or order in which the weights and / or other parameter information should be loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads the weights or other parameter information into a processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, code and / or data storage 501 stores weight parameters and / or input / output data for each layer of a neural network that is trained or used in conjunction with one or more embodiments during forward propagation of the input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 501 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0042] In at least one embodiment, any portion of code and / or data storage 501 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 501 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the selection of whether code and / or data storage 501 is internal or external to the processor, for example, or includes DRAM, SRAM, flash, or some other storage type, may depend on available storage, on-chip versus off-chip, latency requirements of the training and / or inference functions being performed, batch size of data used in inferencing and / or training of the neural network, or some combination of these factors.

[0043] In at least one embodiment, the inference and / or training logic 515 may include, but is not limited to, code and / or data storage 505 for storing back and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used to infer in accordance with aspects of one or more embodiments. In at least one embodiment, the code and / or data storage 505 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, training logic 515 may include or be coupled to code and / or data storage 505 for storing graph code or other software for controlling timing and / or ordering, in which weights and / or other parameter information should be loaded to configure logic including integer and / or floating point units (collectively, arithmetic logic units (ALUs)).

[0044] In at least one embodiment, code, such as graph code, causes the loading of weight or other parameter information into a processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 505 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 505 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 505 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the selection of whether code and / or data storage 505 is internal or external to the processor, for example, or whether it includes DRAM, SRAM, flash memory, or some other storage type, may depend on available storage, on-chip versus off-chip, latency requirements of the training and / or inference functions being performed, batch sizes of data used in inferring and / or training the neural network, or some combination of these factors.

[0045] In at least one embodiment, code and / or data storage 501 and code and / or data storage 505 may be separate storage structures. In at least one embodiment, code and / or data storage 501 and code and / or data storage 505 may be combined storage structures. In at least one embodiment, code and / or data storage 501 and code and / or data storage 505 may be partially combined and partially separate. In at least one embodiment, code and / or data storage 501 and any portion of code and / or data storage 505 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0046] In at least one embodiment, inference and / or training logic 515 may include one or more arithmetic logic units (“ALUs”) 510, including, but not limited to, integer and / or floating point units, for performing logical and / or mathematical operations based at least in part on or indicated by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from layers or neurons in a neural network) that are stored in activation storage 520, where these activations are a function of input / output and / or weight parameter data stored in code and / or data storage 501 and / or code and / or data storage 505. In at least one embodiment, the activations stored in activation storage 520 are generated according to linear algebra and / or matrix-based mathematics performed by ALU(s) 510 in response to executing instructions or other code, and the weight values ​​stored in code and / or data storage 505 and / or data storage 501 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 505 or code and / or data storage 501, or in another storage, on-chip or off-chip.

[0047] In at least one embodiment, ALU(s) 510 are contained within one or more processors or other hardware logic devices or circuits, while in other embodiments, ALU(s) 510 may be external to the processor or other hardware logic device or circuit (e.g., a coprocessor) that uses them. In at least one embodiment, ALU 510 may be contained within an execution unit of a processor, or otherwise within a bank of ALUs accessible by execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing unit, graphics processing unit, fixed function unit, etc.). In at least one embodiment, code and / or data storage 501, code and / or data storage 505, and activation storage 520 may share a processor or other hardware logic device or circuit, while in other embodiments, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same processor or other hardware logic device or circuit and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 520 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the processor's fetch, decode, schedule, execute, retirement, and / or other logic circuitry.

[0048] In at least one embodiment, activation storage 520 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 520 may be completely or partially within or external to one or more processors or other logic circuits. In at least one embodiment, the selection of whether activation storage 520 is internal or external to a processor, for example, or whether it includes DRAM, SRAM, flash memory, or some other storage type, may depend on available storage, on-chip versus off-chip, latency requirements of the training and / or inference functions being performed, batch sizes of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0049] In at least one embodiment, the inference and / or training logic 515 shown in Figure 5A may be used in conjunction with an application-specific integrated circuit ("ASIC"), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., "Lake Crest") processor from Intel Corp. In at least one embodiment, the inference and / or training logic 515 shown in Figure 5A may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware, such as a field programmable gate array ("FPGA") or data processing unit (DPU).

[0050] FIG. 5B illustrates inference and / or training logic 515, according to at least one embodiment. In at least one embodiment, the inference and / or training logic 515 may include, but is not limited to, hardware logic in which computational resources are dedicated or otherwise used only in conjunction with weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, the inference and / or training logic 515 illustrated in FIG. 5B may be used in conjunction with an application-specific integrated circuit (ASIC), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, the inference and / or training logic 515 illustrated in FIG. 5B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware, such as field programmable gate array (FPGA) or data processing unit (DPU) hardware. In at least one embodiment, inference and / or training logic 515 includes, but is not limited to, code and / or data storage 501 and code and / or data storage 505, which may be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment shown in FIG. 5B , code and / or data storage 501 and code and / or data storage 505 are each associated with dedicated computational resources, such as computation hardware 502 and computation hardware 506, respectively. In at least one embodiment, computation hardware 502 and computation hardware 506 each include one or more ALUs that perform mathematical functions, such as linear algebra functions, solely on the information stored in code and / or data storage 501 and code and / or data storage 505, respectively, with the results stored in activation storage 520.

[0051] In at least one embodiment, each of the code and / or data storage 501 and 505 and corresponding computation hardware 502 and 506 corresponds to a different layer of a neural network, whereby activations resulting from one storage / computation pair 501 / 502 of code and / or data storage 501 and computation hardware 502 are provided as input to a next storage / computation pair 505 / 506 of code and / or data storage 505 and computation hardware 506 to mirror the conceptual organization of the neural network. In at least one embodiment, the storage / computation pairs 501 / 502 and 505 / 506 may correspond to two or more neural network layers. In at least one embodiment, additional storage / computation pairs (not shown) may be included in the inference and / or training logic 515 after or in parallel with the storage / computation pairs 501 / 502 and 505 / 506.

[0052] Neural Network Training and Deployment FIG. 6 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an untrained neural network 606 is trained using a training dataset 602. In at least one embodiment, the training framework 604 is the PyTorch framework, while in other embodiments, the training framework 604 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 604 trains the untrained neural network 606 and enables it to be trained using processing resources described herein to generate a trained neural network 608. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training may be performed in a supervised, semi-supervised, or unsupervised manner.

[0053] In at least one embodiment, the untrained neural network 606 is trained using supervised learning, where the training dataset 602 includes inputs paired with desired outputs for the inputs, or the training dataset 602 includes inputs with known outputs, and the outputs of the neural network 606 are manually scored. In at least one embodiment, the untrained neural network 606 is trained in a supervised manner, where inputs from the training dataset 602 are processed and the resulting outputs are compared to a set of expected or desired outputs. In at least one embodiment, errors are then back-propagated through the untrained neural network 606. In at least one embodiment, the training framework 604 adjusts the weights controlling the untrained neural network 606. In at least one embodiment, the training framework 604 includes tools for monitoring how well the untrained neural network 606 is converging toward a model, such as the trained neural network 608, suitable for generating correct answers, such as in the results 614, based on input data, such as the new dataset 612. In at least one embodiment, the training framework 604 iteratively trains the untrained neural network 606 and adjusts the weights using a loss function and a tuning algorithm, such as stochastic gradient descent, to improve the output of the untrained neural network 606. In at least one embodiment, the training framework 604 trains the untrained neural network 606 until the untrained neural network 606 achieves a desired accuracy. In at least one embodiment, the trained neural network 608 can then be deployed to implement any number of machine learning operations.

[0054] In at least one embodiment, the untrained neural network 606 is trained using unsupervised learning, where the untrained neural network 606 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 602 includes input data without any associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 606 can learn groupings within the training dataset 602 and determine how individual inputs relate to the untrained dataset 602. In at least one embodiment, unsupervised training can be used to generate self-organizing maps in the trained neural network 608, which can perform operations useful in reducing the dimensionality of the new dataset 612. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the new dataset 612 that deviate from the normal patterns of the new dataset 612.

[0055] In at least one embodiment, semi-supervised learning may be used, which is a technique that includes a mixture of labeled and unlabeled data in the training dataset 602. In at least one embodiment, the training framework 604 may be used to implement incremental learning, such as through a transfer learning technique. In at least one embodiment, incremental learning allows the trained neural network 608 to adapt to a new dataset 612 without forgetting knowledge instilled in the trained neural network 608 during initial training.

[0056] Data Center 7 illustrates an exemplary data center 700 in which at least one embodiment may be used. In at least one embodiment, the data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0057] In at least one embodiment, as shown in FIG. 7, a data center infrastructure layer 710 may include a resource orchestrator 712, grouped computing resources 714, and node computing resources (“node CR”) 716(1) through 716(N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, nodes CR 716(1)-716(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, data processing units, etc.), memory storage devices 718(1)-718(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, cooling modules, etc. In at least one embodiment, one or more nodes CR from among nodes CR 716(1)-716(N) may be a server having one or more of the computing resources described above.

[0058] In at least one embodiment, the grouped computing resources 714 may include a distinct grouping of node CRs housed within one or more racks (not shown), or many racks housed in a data center at various geographic locations (also not shown). In at least one embodiment, the distinct groupings of node CRs within the grouped computing resources 714 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0059] In at least one embodiment, resource orchestrator 712 may configure or otherwise control one or more nodes CR 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource orchestrator 712 may include a software design infrastructure (“SDI”) management entity for data center 700. In at least one embodiment, resource orchestrator 512 may include hardware, software, or some combination thereof.

[0060] 7 , framework layer 720 includes a job scheduler 722, a configuration manager 724, a resource manager 726, and a distributed file system 728. In at least one embodiment, framework layer 720 may include a framework for supporting software 732 in software layer 730 and / or one or more applications 742 in application layer 740. In at least one embodiment, software 732 or application(s) 742 may include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure, respectively. In at least one embodiment, framework layer 720 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter “Spark”), which may utilize distributed file system 728 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 722 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 700. In at least one embodiment, configuration manager 724 may be capable of configuring different tiers, such as software tier 730, as well as framework tier 720 including Spark and distributed file system 728 to support large-scale data processing. In at least one embodiment, resource manager 726 may be capable of managing clustered or grouped computing resources mapped or allocated to support distributed file system 728 and job scheduler 722. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 714 in data center infrastructure tier 710.In at least one embodiment, resource manager 726 may manage these mapped or allocated computing resources in coordination with resource orchestrator 712.

[0061] In at least one embodiment, software 732 included in software layer 730 may include software used by nodes CR 716(1)-716(N), grouped computing resources 714, and / or at least a portion of distributed file system 728 of framework layer 720. In at least one embodiment, the one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0062] In at least one embodiment, the application(s) 742 included in the application layer 740 may include one or more types of applications used by the nodes CR 716(1)-716(N), the grouped computing resources 714, and / or at least a portion of the distributed file system 728 of the framework layer 720. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0063] In at least one embodiment, any of configuration manager 724, resource manager 726, and resource orchestrator 712 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may relieve data center operators of data center 700 from determining potentially faulty configurations and potentially avoiding underutilized and / or underperforming portions of the data center.

[0064] In at least one embodiment, data center 700 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, machine learning models may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 700. In at least one embodiment, the trained machine learning models corresponding to the one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 700 by using the weight parameters calculated through one or more training techniques described herein.

[0065] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, DPU, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service to enable a user to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0066] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with Figures 5A and 5B. In at least one embodiment, inference and / or training logic 515 may be used in the system of Figure 7 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0067] In various embodiments, the data center executes a load balancer, as described above, that distributes operations (e.g., transformation of video frames) across CPUs, application specific integrated circuits (ASICs), GPUs, FPGAs, DPUs, or other hardware during the execution of a video analytics pipeline or other application.

[0068] Autonomous Vehicles 8A illustrates an example of an autonomous vehicle 800, according to at least one embodiment. In at least one embodiment, autonomous vehicle 800 (alternatively referred to herein as “vehicle 800”) may be a passenger vehicle, such as, but not limited to, a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 800 may be a semi-tractor-trailer truck used to transport cargo. In at least one embodiment, vehicle 800 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0069] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, published June 15, 2018; Standard No. J3016-201609, published September 30, 2016; and previous and new versions of this standard). In at least one embodiment, vehicle 800 may be capable of functionality according to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 800 may be capable of conditional automation (Level 3), highly automated (Level 4), and / or fully automated (Level 5), depending on the embodiment.

[0070] In at least one embodiment, vehicle 800 may include components such as, but not limited to, a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 800 may include a propulsion system 850 such as, but not limited to, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another propulsion system type. In at least one embodiment, propulsion system 850 may be connected to a drive train of vehicle 800, which may include, but is not limited to, a transmission to enable propulsion of vehicle 800. In at least one embodiment, propulsion system 850 may be controlled in response to receiving a signal from throttle / accelerator(s) 852.

[0071] In at least one embodiment, steering system 854, which may include, but is not limited to, a steering wheel, is used to steer vehicle 800 (e.g., along a desired path or route) when propulsion system 850 is operating (e.g., when vehicle 800 is moving). In at least one embodiment, steering system 854 may receive signals from steering actuator(s) 856. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 846 may be used to operate vehicle brakes in response to receiving signals from brake actuator(s) 848 and / or brake sensors.

[0072] In at least one embodiment, controller(s) 836, which may include, without limitation, one or more system-on-chip (“SoC”) (not shown in FIG. 8A ) and / or graphics processing unit(s) (“GPU”)(s), provide signals (e.g., representing commands) to one or more components and / or systems of vehicle 800. For example, in at least one embodiment, controller(s) 836 may send signals to operate vehicle brakes via brake actuator(s) 848, to operate steering system 854 via steering actuator(s) 856, and to operate propulsion system 850 via throttle / accelerator(s) 852. In at least one embodiment, controller(s) 836 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 800. In at least one embodiment, controller(s) 836 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functionalities, two or more controllers may handle a single functionality, and / or any combination thereof.

[0073] In at least one embodiment, controller(s) 836 provide signals to control one or more components and / or systems of vehicle 800 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, the sensor data may be received from, for example, but not limited to, global navigation satellite system ("GNSS") sensor(s) 858 (e.g., global positioning system sensor(s)), RADAR sensor(s) 860, ultrasonic sensor(s) 862, LIDAR sensor(s) 864, inertial measurement unit(s) ("IMU(s)"). The vehicle 800 vehicle information may be received from sensors 866 (e.g., accelerometer(s), gyroscope(s), magnetic compass(s), magnetometer(s), etc.), microphone(s) 896, stereo camera(s), wide-angle camera(s) (e.g., 360-degree camera(s), long-range camera(s) (not shown in FIG. 8A ), mid-range camera(s) (not shown in FIG. 8A ), speed sensor(s) 844 (e.g., for measuring the speed of the vehicle 800), vibration sensor(s) 842, steering sensor(s) 840, brake sensor(s) (e.g., as part of brake sensor system 846), and / or other sensor types.

[0074] In at least one embodiment, one or more of the controller(s) 836 may receive input (e.g., represented by input data) from an instrument cluster 832 of the vehicle 800 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 834, an audible annunciator, a loudspeaker, and / or via other components of the vehicle 800. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., a high-definition map (not shown in FIG. 8A )), location data (e.g., the location of the vehicle 800 on a map, etc.), direction, the locations of other vehicles (e.g., an occupancy grid), information about objects sensed by the controller(s) 836 and the status of the objects, etc. For example, in at least one embodiment, the HMI display 834 may display information regarding the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information regarding a driving maneuver the vehicle has performed, is performing, or will perform (e.g., currently changing lanes, taking exit 34B in 2 miles, etc.).

[0075] In at least one embodiment, vehicle 800 further includes a network interface 824, which may use wireless antenna(s) 826 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, network interface 824 may be capable of communicating over a Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") network, etc. Additionally, in at least one embodiment, the wireless antenna(s) 826 may enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area network(s) such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and / or low power wide-area network(s) (“LPWAN”) such as protocols like LoRaWAN, SigFox, etc.

[0076] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B. In at least one embodiment, inference and / or training logic 515 may be used in the system of FIG. 8A for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0077] In various embodiments, the autonomous vehicle executes a load balancer, as described above, that distributes operations (e.g., transformation of video frames) across CPUs, application specific integrated circuits (ASICs), GPUs, FPGAs, DPUs, or other hardware during the execution of a video analytics pipeline or other application.

[0078] 8B illustrates an example of camera locations and fields of view for autonomous vehicle 800 of FIG. 8A, according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are an illustrative example and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be located at different locations on vehicle 800.

[0079] In at least one embodiment, the camera type for the camera may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 800. In at least one embodiment, the camera(s) may operate at Automotive Safety Integrity Level (“ASIL”) B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor ("RGGB") color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, to increase light sensitivity.

[0080] In at least one embodiment, one or more of the camera(s) may be used to implement advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more (e.g., all) of the camera(s) may simultaneously record and provide image data (e.g., video).

[0081] In at least one embodiment, the camera(s) may be mounted in a mounting assembly, such as a custom-designed (e.g., three-dimensionally (“3D”) printed) assembly, to eliminate stray light and reflections from within the vehicle 800 (e.g., reflections reflected from the dashboard onto the windshield) that may interfere with camera image data capture capability. With reference to a door mirror mounting assembly, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate matches the shape of the door mirror. In at least one embodiment, the camera(s) may be integrated into the door mirror. In at least one embodiment, for a side view camera, the camera(s) may be integrated into the four pillars at each corner of the cabin.

[0082] In at least one embodiment, a camera (e.g., a front-facing camera) with a field of view that includes a portion of the environment ahead of vehicle 800 may be used for a surround view to help identify the path and obstacles ahead and, with the aid of one or more of controller(s) 836 and / or control SoCs, provide information essential for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many ADAS functions similar to LIDAR, including, but not limited to, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS functions and systems, including, but not limited to, Lane Departure Warning ("LDW"), Autonomous Cruise Control ("ACC"), and / or other functions such as traffic sign recognition.

[0083] In at least one embodiment, various cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal oxide semiconductor”) color imager. In at least one embodiment, a wide-angle camera 870 may be used to perceive objects (e.g., pedestrians, crossing traffic, or bicyclists) coming into view from the periphery. While only one wide-angle camera 870 is shown in FIG. 8B , in other embodiments, there may be any number (including zero) of wide-angle cameras on the vehicle 800. In at least one embodiment, any number of long-range camera(s) 898 (e.g., long-view stereo camera pairs) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range camera(s) 898 may also be used for object detection and classification, as well as basic object tracking.

[0084] In at least one embodiment, any number of stereo cameras 868 may also be included in the front-facing configuration. In at least one embodiment, one or more of the stereo camera(s) 868 may include an integrated control unit with a scalable processing unit, which may provide a programmable logic on a chip ("FPGA") and a multi-core microprocessor with an integrated controller area network ("CAN") or Ethernet interface. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 800 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo camera(s) 868 may include, but are not limited to, compact stereo vision sensor(s) that may include, but are not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that may measure distance from vehicle 800 to target objects and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo camera(s) 868 may be used in addition to or instead of those described herein.

[0085] In at least one embodiment, a camera with a field of view that includes portions of the environment to the sides of vehicle 800 (e.g., a side-view camera) may be used for the surroundings view, providing information used to create and update the occupancy grid and generate side collision warnings. For example, in at least one embodiment, surroundings camera(s) 874 (e.g., four surroundings cameras shown in FIG. 8B ) may be positioned on vehicle 800. In at least one embodiment, surroundings camera(s) 874 may include, without limitation, any number and combination of wide-angle cameras, fisheye camera(s), 360-degree camera(s), and / or the like. For example, in at least one embodiment, four fisheye cameras may be positioned in front, behind, and on the sides of vehicle 800. In at least one embodiment, vehicle 800 may use three surroundings cameras 874 (e.g., left, right, and rear) and utilize one or more other cameras (e.g., a front camera) as a fourth surroundings view camera.

[0086] In at least one embodiment, a camera (e.g., a rear-view camera) with a field of view that includes a portion of the environment behind vehicle 800 may be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a wide variety of cameras may be used, including, but not limited to, a camera that is also suitable as a front-facing camera(s) (e.g., long-range camera 898, and / or mid-range camera(s) 876, stereo camera(s) 868, infrared camera(s) 872, etc.), as described herein.

[0087] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, inference and / or training logic 515 may be used in the system of Figure 8B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0088] FIG. 8C is a block diagram illustrating an example system architecture for the autonomous vehicle 800 of FIG. 8A , according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 800 in FIG. 8C is shown as connected via a bus 802. In at least one embodiment, the bus 802 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, the CAN may be a network internal to the vehicle 800 used to help control various features and functionality of the vehicle 800, such as brake application, acceleration, brake control, steering, windshield wipers, etc. In at least one embodiment, the bus 802 may be configured to have tens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 802 may be read to determine steering wheel angle, ground speed, engine revolutions per minute (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 802 may be an ASIL B compliant CAN bus.

[0089] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or as an alternative to CAN. In at least one embodiment, there may be any number of buses forming bus 802, including, but not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or for redundancy. For example, a first bus may be used for collision avoidance functionality and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 802 may communicate with one of the components of vehicle 800, and two or more of buses of bus 802 may communicate with corresponding components. In at least one embodiment, each of any number of system-on-chip (“SoC”) 804 (e.g., SoC 804(A) and SoC 804(B)), each of the controller(s) 836, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in vehicle 800) and may be connected to a common bus, such as a CAN bus.

[0090] In at least one embodiment, vehicle 800 may include one or more controllers 836, such as those described herein with respect to FIG. 8A. In at least one embodiment, controller(s) 836 may be used for a variety of functions. In at least one embodiment, controller(s) 836 may be coupled to any of various other components and systems of vehicle 800 and may be used for control of vehicle 800, artificial intelligence of vehicle 800, infotainment for vehicle 800, and / or other functions.

[0091] In at least one embodiment, vehicle 800 may include any number of SoCs 804. In at least one embodiment, each of SoCs 804 may include, without limitation, a central processing unit (“CPU”) 806, a graphics processing unit (“GPU”) 808, processor(s) 810, cache(s) 812, accelerator(s) 814, data store(s) 816, and / or other components and features not shown. In at least one embodiment, SoC(s) 804 may be used to control vehicle 800 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 804 may be combined in a system (e.g., that of vehicle 800) with a high definition (“HD”) map 822 that may obtain map refreshes and / or updates via a network interface 824 from one or more servers (not shown in FIG. 8C ).

[0092] In at least one embodiment, the CPU(s) 806 may include a CPU cluster or CPU complex (alternatively referred to herein as a “CCPLEX”). In at least one embodiment, the CPU(s) 806 may include multiple cores and / or level 2 (“L2”) caches. For example, in at least one embodiment, the CPU(s) 806 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, the CPU(s) 806 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2 megabytes (MB) of L2 cache). In at least one embodiment, the CPU(s) 806 (e.g., a CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of clusters of the CPU(s) 806 to be active at any given time.

[0093] In at least one embodiment, one or more of the CPU(s) 806 may implement power management capabilities, including, but not limited to, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to conserve dynamic power; each core clock may be gated when such core is not actively executing instructions by execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, the CPU(s) 806 may further implement an advanced algorithm for managing power states, where the hardware / microcode determines what the best power state to enter for a core, cluster, and CCPLEX is given the allowed power states and expected wake-up times. In at least one embodiment, the processing core may support a simple power state entry sequence in software with the work offloaded to the microcode.

[0094] In at least one embodiment, the GPU(s) 808 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, the GPU(s) 808 may be programmable and efficient for parallel workloads. In at least one embodiment, the GPU(s) 808 may use an extended tensor instruction set. In at least one embodiment, the GPU(s) 808 may include one or more streaming microprocessors, each of which may include a level 1 (“L1”) cache (e.g., an L1 cache with at least 96 KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512 KB of storage capacity). In at least one embodiment, the GPU(s) 808 may include at least eight streaming microprocessors. In at least one embodiment, the GPU(s) 808 may use one or more compute application programming interfaces (APIs). In at least one embodiment, the GPU(s) 808 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0095] In at least one embodiment, one or more of the GPU(s) 808 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, the GPU(s) 808 may be fabricated on Fin field-effect transistor ("FinFET") circuitry. In at least one embodiment, each streaming microprocessor may incorporate several mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix arithmetic, a level 0 ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for efficient execution of workloads with a mix of computation and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation among parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0096] In at least one embodiment, one or more of the GPU(s) 808 may include high bandwidth memory ("HBM") and / or a 16 GB HBM2 memory subsystem to provide, in some instances, approximately 900 GB / s of peak memory bandwidth. In at least one embodiment, synchronous graphics random-access memory ("SGRAM"), such as graphics double data rate type five ("GDDR5"), may be used in addition to or as an alternative to the HBM memory.

[0097] In at least one embodiment, the GPU(s) 808 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to enable the GPU(s) 808 to directly access the page tables of the CPU(s) 806. In at least one embodiment, when the GPU 808 memory management unit ("MMU") encounters a GPU miss, an address translation request may be sent to the CPU(s) 806. In at least one embodiment, in response, one of the CPU(s) 806 may look up a virtual-to-physical mapping for the address in its page table and send the translation back to the GPU(s) 808. In at least one embodiment, the unified memory technology enables a single unified virtual address space for memory of both the CPU(s) 806 and the GPU(s) 808, which may simplify programming the GPU(s) 808 and porting applications to the GPU(s) 808.

[0098] In at least one embodiment, GPU(s) 808 may include any number of access counters that may track the frequency of GPU(s) 808's accesses to the memory of other processors. In at least one embodiment, the access counter(s) may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0099] In at least one embodiment, one or more of the SoC(s) 804 may include any number of caches 812, including those described herein. For example, in at least one embodiment, the cache(s) 812 may include a level 3 (“L3”) cache that is available to both the CPU(s) 806 and the GPU(s) 808 (e.g., connected to the CPU(s) 806 and the GPU(s) 808). In at least one embodiment, the cache(s) 812 may include a write-back cache that may track line state, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB or more of memory, depending on the embodiment, although smaller cache sizes may be used.

[0100] In at least one embodiment, one or more of the SoC(s) 804 may include one or more accelerators 814 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoC(s) 804 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may complement the GPU(s) 808 and be used to offload some of the tasks of the GPU(s) 808 (e.g., to free up more cycles of the GPU(s) 808 to perform other tasks). In at least one embodiment, accelerator 814 may be used for target workloads that are stable enough to accommodate acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, the CNNs may include region-based, i.e., regional convolutional neural networks (“RCNNs”), and Fast RCNNs (e.g., as used for object detection), or other types of CNNs.

[0101] In at least one embodiment, the accelerator(s) 814 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, the DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional tens of trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, the DLA(s) may be further optimized for a specific set of neural network types and floating-point operations, as well as for inference. In at least one embodiment, the design of the DLA(s) may provide more performance per millimeter than a typical general-purpose GPU, generally far exceeding the performance of a CPU. In at least one embodiment, the TPU(s) may perform several functions, including, for example, single-instance convolution functions, supporting INT8, INT16, and FP16 data types for both features and weights, and post-processor functions. In at least one embodiment, the DLA(s) may quickly and efficiently run neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to, CNNs for object identification and detection using data from a camera sensor, CNNs for distance estimation using data from a camera sensor, CNNs for emergency vehicle detection and identification using data from a microphone, CNNs for face recognition and vehicle owner identification using data from a camera sensor, and / or CNNs for security and / or safety-related events.

[0102] In at least one embodiment, the DLA(s) may perform any function of the GPU(s) 808; for example, by using an inference accelerator, a designer may target either the DLA(s) or the GPU(s) 808 for any function. For example, in at least one embodiment, a designer may centralize the processing of CNNs and floating-point operations in the DLA(s) and offload other functions to the GPU(s) 808 and / or the accelerator(s) 814.

[0103] In at least one embodiment, the accelerator(s) 814 may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, the PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 838, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVAs may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”) processors, and / or any number of vector processors.

[0104] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any camera described herein), image signal processor(s), etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, the RISC core may use any of several protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0105] In at least one embodiment, the DMA may enable components of the PVA to access system memory independently of the CPU(s) 806. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0106] In at least one embodiment, the vector processor is a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and can provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can operate as the PVA's primary processing engine and can include a vector processing unit ("VPU"), an instruction cache, and / or vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor, etc. In at least one embodiment, a combination of SIMD and VLIW may improve throughput and speed.

[0107] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of the vector processors may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to improve the overall security of the system.

[0108] In at least one embodiment, the accelerator(s) 814 may include a computer vision network-on-chip and static random-access memory ("SRAM") to provide high-bandwidth, low-latency SRAM for the accelerator(s) 814. In at least one embodiment, the on-chip memory may include, for example, but not limited to, at least 4 MB of SRAM including eight field-configurable memory blocks, which may be accessible by both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access memory through a backbone that provides the PVA and DLA with high-speed access to memory. In at least one embodiment, the backbone may include a computer vision network-on-chip that interconnects the PVA and DLA to memory (e.g., using APBs).

[0109] In at least one embodiment, the computer vision network-on-chip may include an interface that determines whether both the PVA and DLA provide ready and enable signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization (“ISO”) 26262 or International Electrotechnical Commission (“IEC”) 61508 standards, although other standards and protocols may be used.

[0110] In at least one embodiment, one or more of the SoC(s) 804 may include a real-time ray tracing hardware accelerator that may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general waveform propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0111] In at least one embodiment, accelerator(s) 814 can have diverse uses for autonomous driving. In at least one embodiment, PVAs can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, PVA capabilities are well-matched for algorithm domains that require predictable processing with low power and low latency. In other words, PVAs perform well on small data sets for semi-dense or dense regular calculations that may require predictable runtime with low latency and low power. In at least one embodiment, PVAs, such as in vehicle 800, can be designed to run traditional computer vision algorithms because they can be efficient at object detection and integer arithmetic.

[0112] For example, according to at least one embodiment of the technology, the PVA is used to perform computer stereo vision. In at least one embodiment, semi-global matching-based algorithms may be used in some instances, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0113] In at least one embodiment, the PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA may be used for time-of-flight depth processing, for example, by processing the raw time-of-flight data to provide processed time-of-flight data.

[0114] In at least one embodiment, DLA may be used to run any type of network for improving control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, confidence may be expressed or interpreted as the probability of each detection compared to other detections or as providing its relative “weight.” In at least one embodiment, the confidence measure allows the system to make further decisions regarding which detections should be considered true positives rather than false positives. In at least one embodiment, the system may set a confidence threshold and consider only detections above the threshold to be true positives. In embodiments where an automatic emergency braking (“AEB”) system is used, a false positive detection would cause the vehicle to automatically apply emergency braking, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered a trigger for AEB. In at least one embodiment, DLA may run a neural network to regress a confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), an output from IMU sensor(s) 866 that correlates with the orientation of the vehicle 800, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., LIDAR sensor(s) 864 or RADAR sensor(s) 860), among others.

[0115] In at least one embodiment, one or more of the SoC(s) 804 may include data store(s) 816 (e.g., memory). In at least one embodiment, the data store(s) 816 may be on-chip memory of the SoC(s) 804, which may store neural networks to be executed on the GPU(s) 808 and / or DLA. In at least one embodiment, the data store(s) 816 may be large enough in capacity to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, the data store(s) 816 may comprise L2 or L3 cache(s).

[0116] In at least one embodiment, one or more of the SoC(s) 804 may include number(s) of processor(s) 810 (e.g., embedded processor(s)). In at least one embodiment, the processor(s) 810 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC(s) 804 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist with system low power state transitions, manage thermal and temperature sensors of the SoC(s) 804, and / or manage the power state of the SoC(s) 804. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC(s) 804 may use the ring oscillator to detect the temperature of the CPU(s) 806, the GPU(s) 808, and / or the accelerator(s) 814. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine, place the SoC(s) 804 in a low power state, and / or place the vehicle 800 in a chauffeur to safe stop mode (e.g., bring the vehicle 800 to a safe stop).

[0117] In at least one embodiment, the processor(s) 810 may further include a set of embedded processors that may act as an audio processing engine, which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide variety of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0118] In at least one embodiment, the processor(s) 810 may further include an always-on processor engine that may provide the hardware features necessary to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0119] In at least one embodiment, the processor(s) 810 may further include a safety cluster engine, which may include, but is not limited to, a dedicated processor subsystem for handling safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, the two or more cores, in at least one embodiment, may operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, the processor(s) 810 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, the processor(s) 810 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0120] In at least one embodiment, the processor(s) 810 may include a video image composer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to produce a final image for the player window. In at least one embodiment, the video image composer may perform lens distortion correction for the wide-angle camera(s) 870, the surrounding camera(s) 874, and / or the in-cabin surveillance camera sensor(s). In at least one embodiment, the in-cabin surveillance camera sensor(s) is / are preferably monitored by a neural network running on another instance of the SoC 804 that is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading to, but is not limited to, activate cellular service, make phone calls, write emails, change vehicle destinations, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, some features are available to the driver when the vehicle is operating in autonomous mode and are disabled at other times.

[0121] In at least one embodiment, the video image combiner may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, noise reduction appropriately weights spatial information and reduces the weight of information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0122] In at least one embodiment, the video image composer may also be configured to perform stereo rectification on the input stereo lens frames. In at least one embodiment, the video image composer may further be used for user interface compositing when the operating system desktop is in use, so that the GPU(s) 808 are not required to continually render new surfaces. In at least one embodiment, when the GPU(s) 808 are powered on, active, and performing 3D rendering, the video image composer may be used to offload the GPU(s) 808 to improve performance and responsiveness.

[0123] In at least one embodiment, one or more of the SoC(s) 804 may further include a mobile industry processor interface ("MIPI") camera serial interface, a high-speed interface for receiving video and input from a camera, and / or a video input block that may be used for camera and related pixel input functions. In at least one embodiment, one or more of the SoC(s) 804 may further include input / output controller(s), which may be controlled by software and may be used to receive I / O signals that are not committed to a specific role.

[0124] In at least one embodiment, one or more of the SoC(s) 804 may further include a wide range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, the SoC(s) 804 may be used to process data from cameras (e.g., connected via a gigabit multimedia serial link and an Ethernet channel), data from sensors (e.g., LIDAR sensor(s) 864, RADAR sensor(s) 860, etc., which may be connected via an Ethernet channel), data from bus 802 (e.g., vehicle 800 speed, steering wheel position, etc.), data from GNSS sensor(s) 858 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more of the SoC(s) 804 may further include dedicated high performance mass storage controllers, which may include their own DMA engines and may be used to offload the CPU(s) 806 from routine data management tasks.

[0125] In at least one embodiment, the SoC(s) 804 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and may provide a platform for a flexible and reliable driving software stack, along with deep learning tools. In at least one embodiment, the SoC(s) 804 may be faster, more reliable, and more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator(s) 814, when combined with the CPU(s) 806, GPU(s) 808, and data store(s) 816, may provide a fast and efficient platform for a level 3-5 autonomous vehicle.

[0126] In at least one embodiment, computer vision algorithms may be executed on a CPU, which may be configured using a high-level programming language, such as C, to perform a wide variety of processing algorithms across a wide variety of visual data. However, in at least one embodiment, CPUs often cannot meet the performance requirements of many computer vision applications, including requirements related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, as used in in-vehicle ADAS applications and practical Level 3-5 autonomous vehicles.

[0127] The embodiments described herein allow multiple neural networks to be implemented simultaneously and / or sequentially, with the results being combined together to enable Levels 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN running on the DLA or a separate GPU (e.g., GPU(s) 820) can include text and word recognition, enabling the neural network to read and understand traffic signs, including signs for which it was not specifically trained. In at least one embodiment, the DLA can further include a neural network that can identify and interpret signs and provide a semantic understanding of the signs, which can then be passed to a route planning module running on the CPU complex.

[0128] In at least one embodiment, multiple neural networks may be run simultaneously for Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icy conditions" along with an electric light may be interpreted independently or collectively by several neural networks. In at least one embodiment, such a warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "Flashing lights indicate icy conditions" may be interpreted by a second deployed neural network, which, when the flashing light is detected, informs the vehicle's route planning software (preferably running on a CPU complex) that an icy condition exists. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the third deployed neural network informs the vehicle's route planning software of the presence (or absence) of the flashing light. In at least one embodiment, all three neural networks may be run simultaneously, such as within the DLA and / or on the GPU(s) 808.

[0129] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 800. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in security mode, disable such vehicle when the owner leaves such vehicle. In this manner, the SoC(s) 804 provide security against theft and / or carjacking.

[0130] In at least one embodiment, a CNN for emergency vehicle detection and identification may detect and identify emergency vehicle sirens using data from microphone 896. In at least one embodiment, SoC(s) 804 use CNNs to classify environmental and urban sounds as well as visual data. In at least one embodiment, a CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor(s) 858. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when in North America, the CNN attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, the control program may be used to execute an emergency vehicle safety routine, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle in conjunction with the ultrasonic sensor(s) 862 until the emergency vehicle has passed.

[0131] In at least one embodiment, vehicle 800 may include CPU(s) 818 (e.g., discrete CPU(s) or dCPU(s)), which may be coupled to SoC(s) 804 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU(s) 818 may include, for example, an X86 processor. CPU(s) 818 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between ADAS sensors and SoC(s) 804 and / or monitoring the status and health of controller(s) 836 and / or infotainment system on a chip ("infotainment SoC") 830.

[0132] In at least one embodiment, vehicle 800 may include GPU(s) 820 (e.g., discrete GPU(s) or dGPU(s)), which may be coupled to SoC(s) 804 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, GPU(s) 820 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of vehicle 800.

[0133] In at least one embodiment, vehicle 800 may further include a network interface 824, which may include, but is not limited to, wireless antenna(s) 826 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 824 may be used to enable wireless connectivity to Internet cloud services (e.g., with server(s) and / or other network devices) with other vehicles and / or computing devices (e.g., passenger client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 80 and the other vehicles and / or an indirect link may be established (e.g., across a network and via the Internet). In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 800 with information regarding vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 800). In at least one embodiment, such aforementioned functionality may be part of the cooperative adaptive cruise control functionality of vehicle 800.

[0134] In at least one embodiment, the network interface 824 may include an SoC that provides modulation and demodulation functionality and enables the controller(s) 836 to communicate over a wireless network. In at least one embodiment, the network interface 824 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, the frequency conversion may be performed in any technically feasible manner. For example, the frequency conversion may be performed through well-known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0135] In at least one embodiment, vehicle 800 may further include data store(s) 828, which may include, but are not limited to, off-chip storage (e.g., not on SoC(s) 804). In at least one embodiment, data store(s) 828 may include one or more storage elements, including, but not limited to, RAM, SRAM, dynamic random-access memory (“DRAM”), video random-access memory (“VRAM”), flash memory, a hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0136] In at least one embodiment, vehicle 800 may further include GNSS sensor(s) 858 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 858 may be used, including, for example, but not limited to, a GPS using a USB connector with an Ethernet-to-serial (e.g., RS-232) bridge.

[0137] In at least one embodiment, vehicle 800 may further include RADAR sensor(s) 860. In at least one embodiment, RADAR sensor(s) 860 may be used by vehicle 800 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, RADAR sensor(s) 860 may use a CAN bus and / or bus 802 for control (e.g., to transmit data generated by RADAR sensor(s) 860) and to access object tracking data, in some instances, along with access to an Ethernet channel for accessing raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, without limitation, RADAR sensor(s) 860 may be suitable for forward, rear, and side RADAR use. In at least one embodiment, one or more of the RADAR sensor(s) 860 is a pulse-Doppler RADAR sensor.

[0138] In at least one embodiment, the RADAR sensor(s) 860 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, and short-range lateral coverage. In at least one embodiment, the long-range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, the long-range RADAR system may provide a wide field of view achieved by two or more independent scans, such as within a 250 m (meter) range. In at least one embodiment, the RADAR sensor(s) 860 may help distinguish between static and moving objects and may be used by the ADAS system 838 for emergency braking assistance and forward collision warning. In at least one embodiment, the sensor(s) 860 included in the long-range RADAR system may include, but are not limited to, multiple (e.g., six or more) fixed RADAR antennas and monostatic and multimodal RADAR with high-speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the central four antennas may create a focused beam pattern designed to record the surroundings of vehicle 800 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the other two antennas may increase the field of view, which may allow for quick detection of vehicles entering or exiting vehicle 800's lane.

[0139] In at least one embodiment, the medium-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include any number of RADAR sensors 860 designed to be mounted on either end of a rear bumper, without limitation. When mounted on either end of a rear bumper, in at least one embodiment, the RADAR sensor system may create two beams that constantly monitor blind spots behind and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 838 for blind spot detection and / or lane change assistance.

[0140] In at least one embodiment, vehicle 800 may further include ultrasonic sensor(s) 862. In at least one embodiment, ultrasonic sensor(s) 862, which may be positioned at front, rear, and / or side locations of vehicle 800, may be used for parking assistance and / or to create and update an occupancy grid. In at least one embodiment, a variety of ultrasonic sensor(s) 862 may be used, and different ultrasonic sensor(s) 862 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensor(s) 862 may operate at a functional safety level of ASIL B.

[0141] In at least one embodiment, vehicle 800 may include one or more LIDAR sensors 864. In at least one embodiment, LIDAR sensor(s) 864 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor(s) 864 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 800 may include multiple LIDAR sensors 864 (e.g., two, four, six, etc.), which may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0142] In at least one embodiment, the LIDAR sensor(s) 864 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available LIDAR sensor(s) 864 may have an advertised range of approximately 100 meters, with an accuracy of 2 cm to 3 cm, and support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor(s) 864 may include small devices that may be integrated into front, rear, side, and / or corner locations of the vehicle 800. In at least one embodiment, the LIDAR sensor(s) 864 may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200 meters even for low-reflectivity objects. In at least one embodiment, the forward mounted LIDAR sensor(s) 864 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0143] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. In at least one embodiment, the 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 800 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receptor that records the transit time of the laser pulse and the reflected light on each pixel, which corresponds to a range from the vehicle 800 to the object. In at least one embodiment, the flash LIDAR allows a highly accurate, distortion-free image of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 800. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device may use 5 nanosecond Class I (eye-safe) laser pulses per frame and capture reflected laser light as a 3D range point cloud and co-registered intensity data.

[0144] In at least one embodiment, vehicle 800 may further include IMU sensor(s) 866. In at least one embodiment, IMU sensor(s) 866 may be located at the center of the rear axle of vehicle 800. In at least one embodiment, IMU sensor(s) 866 may include, for example, without limitation, accelerometer(s), magnetometer(s), gyroscope(s), magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, such as in a 6-axis application, IMU sensor(s) 866 may include, but are not limited to, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, IMU sensor(s) 866 may include, but are not limited to, an accelerometer, a gyroscope, and a magnetometer.

[0145] In at least one embodiment, the IMU sensor(s) 866 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor(s) 866 enable the vehicle 800 to estimate its heading by directly observing changes in velocity and correlating that from a GPS to the IMU sensor(s) 866 without requiring input from a magnetic sensor. In at least one embodiment, the IMU sensor(s) 866 and the GNSS sensor(s) 858 may be combined in a single integrated unit.

[0146] In at least one embodiment, vehicle 800 may include microphone(s) 896 positioned in and / or around vehicle 800. In at least one embodiment, microphone(s) 896 may be used for, among other things, emergency vehicle detection and identification.

[0147] In at least one embodiment, vehicle 800 may further include any number of camera types, including stereo camera(s) 868, wide-angle camera(s) 870, infrared camera(s) 872, surrounding camera(s) 874, long-range camera(s) 898, mid-range camera(s) 876, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around the entire perimeter of vehicle 800. In at least one embodiment, which types of cameras are used depends on vehicle 800. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 800. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 800 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example and not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, each camera may be as previously described in more detail herein with respect to Figures 8A and 8B.

[0148] In at least one embodiment, vehicle 800 may further include vibration sensor(s) 842. In at least one embodiment, vibration sensor(s) 842 may measure vibration of a component of vehicle 800, such as an axle(s). For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 842 are used, the difference in vibration may be used to determine the amount of friction or slippage of the road surface (e.g., when the difference in vibration is between a powered axle and a free-spinning axle).

[0149] In at least one embodiment, vehicle 800 may include an ADAS system 838. In at least one embodiment, ADAS system 838 may include, in some instances, an SoC, without limitation. In at least one embodiment, the ADAS system 838 may include, without limitation, any number and combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functionality.

[0150] In at least one embodiment, the ACC system may use RADAR sensor(s) 860, LIDAR sensor(s) 864, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 800 and automatically adjusts the speed of the vehicle 800 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system enforces distance maintenance and advises the vehicle 800 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0151] In at least one embodiment, the CACC system uses information from other vehicles, which may be received via a wireless link or indirectly, via a network connection (e.g., via the Internet), from other vehicles via network interface 824 and / or wireless antenna(s) 826. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, and the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Generally, V2V communication provides information about the immediate preceding vehicle (e.g., a vehicle immediately preceding vehicle 800 and in the same lane), and I2V communication provides information about traffic ahead. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, information about vehicles in front of vehicle 800 may make the CACC system more reliable, which may improve traffic flow and reduce congestion on roads.

[0152] In at least one embodiment, the FCW system is designed to alert the driver of a hazard so that such driver can take corrective action. In at least one embodiment, the FCW system uses a front-facing camera and / or RADAR sensor(s) 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system may provide warnings in the form of an audible, visual warning, vibration, and / or quick brake pulse.

[0153] In at least one embodiment, the AEB system may detect an imminent forward collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a front-facing camera(s) and / or a RADAR sensor(s) 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first alerts the driver to take corrective action to avoid the collision; if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the impact of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-crash braking.

[0154] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as vibration of the steering wheel or seat, to alert the driver when the vehicle 800 crosses a lane marker. In at least one embodiment, the LDW system does not activate when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, the LKA system provides steering inputs or brake control to correct the vehicle 800 if the vehicle 800 begins to leave its lane.

[0155] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver about the vehicles. In at least one embodiment, the BSW system may provide visual, audible, and / or haptic alerts to indicate that it is unsafe to merge or change lanes. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use rear-facing camera(s) and / or RADAR sensor(s) 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to driver feedback, such as a display, speaker, and / or vibration components.

[0156] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera when the vehicle 800 is backing up. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle brakes are applied to avoid a crash. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration components.

[0157] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting to the driver, but this is usually not a major issue because conventional ADAS systems alert the driver, allowing the driver to determine whether a safety condition truly exists and act accordingly. In at least one embodiment, vehicle 800 itself determines whether to follow the result from a primary computer (e.g., a first one of controllers 836) or a secondary computer (e.g., a second one of controllers 836) in the case of conflicting results. For example, in at least one embodiment, ADAS system 838 may be a backup and / or secondary computer for providing perception information to a backup computer rationality module. In at least one embodiment, a backup computer rationality monitor may run redundant and diverse software on hardware components to detect perception and dynamic driving task impairments. In at least one embodiment, output from ADAS system 838 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervising MCU determines how to reconcile the conflict to ensure safe operation.

[0158] In at least one embodiment, the primary computer may be configured to provide the supervising MCU with a reliability score indicating the primary computer's reliability in a selected outcome. In at least one embodiment, if the reliability score exceeds a threshold, the supervising MCU may follow the primary computer's instructions regardless of whether the secondary computers provide conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers exhibit different (e.g., conflicting) results, the supervising MCU may arbitrate between the computers to determine an appropriate outcome.

[0159] In at least one embodiment, the supervisory MCU can be configured to run neural network(s) trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on the output from the primary computer and the output from the secondary computer. In at least one embodiment, the neural network(s) in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the neural network(s) in the supervisory MCU can learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to disable LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the supervising MCU may include at least one of a DLA or a GPU suitable for running neural network(s) along with associated memory. In at least one embodiment, the supervising MCU may comprise and / or be included as a component of SoC(s) 804.

[0160] In at least one embodiment, the ADAS system 838 may include a secondary computer that implements ADAS functionality using traditional rules of computer vision. In at least one embodiment, the secondary computer may use traditional computer vision rules (if-then), and the presence of neural network(s) in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity may make the overall system more fault-tolerant, particularly to failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in software running on the primary computer and non-identical software code running on the secondary computer provides a consistent overall result, the supervisory MCU may have higher confidence that the overall result is correct and that a bug in the software or hardware on the primary computer did not cause a critical error.

[0161] In at least one embodiment, the output of the ADAS system 838 can be fed to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 838 indicates a frontal crash warning due to an upcoming object, the perception block can use this information when identifying the object. In at least one embodiment, the secondary computer can have its own neural network trained as described herein, thus reducing the risk of false positives.

[0162] In at least one embodiment, vehicle 800 may further include an infotainment SoC 830 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, infotainment system SoC 830, in at least one embodiment, may not be an SoC and may include, without limitation, two or more separate components. In at least one embodiment, infotainment SoC 830 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation system, reverse parking assist, wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening / closing, air filter information, etc.) to vehicle 800. For example, infotainment SoC 830 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display (“HUD”), an HMI display 834, telematics devices, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 830 may further be used to provide information (e.g., visual and / or auditory) to user(s) of vehicle 800, such as information from ADAS system 838, autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0163] In at least one embodiment, infotainment SoC 830 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 830 may communicate with other devices, systems, and / or components of vehicle 800 via bus 802. In at least one embodiment, infotainment SoC 830 may be coupled to a supervisory MCU such that the infotainment system's GPU may perform some self-driving functions if primary controller(s) 836 (e.g., vehicle 800's primary and / or backup computers) fail. In at least one embodiment, infotainment SoC 830 may place vehicle 800 in a driver-safety shutdown mode, as described herein.

[0164] In at least one embodiment, vehicle 800 may further include an instrument cluster 832 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 832 may include, but is not limited to, a controller and / or a supercomputer (e.g., a separate controller or supercomputer). In at least one embodiment, instrument cluster 832 may include any number and combination of instrumentation sets, such as, but not limited to, a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a direction indicator, a shift lever position indicator, seat belt warning light(s), parking brake warning light(s), engine malfunction light(s), supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some instances, information may be displayed and / or shared between infotainment SoC 830 and instrument cluster 832. In at least one embodiment, the instrument cluster 832 may be included as part of the infotainment SoC 830, or vice versa.

[0165] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, inference and / or training logic 515 may be used in the system of Figure 8C for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0166] 8D is a diagram of a system for communication between cloud-based server(s) and autonomous vehicle 800 of FIG. 8A , according to at least one embodiment. In at least one embodiment, the system may include, but is not limited to, server(s) 878, network(s) 890, and any number and types of vehicles, including vehicle 800. In at least one embodiment, server(s) 878 may include, but is not limited to, multiple GPUs 884(A)-884(H) (collectively referred to herein as GPUs 884), PCIe switches 882(A)-882(D) (collectively referred to herein as PCIe switch 882), and / or CPUs 880(A)-880(B) (collectively referred to herein as CPUs 880). In at least one embodiment, the GPUs 884, CPUs 880, and PCIe switches 882 may be interconnected with a high-speed interconnect, such as, but not limited to, an NVLink interface 888 and / or PCIe connections 886 developed by NVIDIA. In at least one embodiment, the GPUs 884 are connected via an NVLink and / or NVSwitch SoC, and the GPUs 884 and PCIe switches 882 are connected via a PCIe interconnect. While eight GPUs 884, two CPUs 880, and four PCIe switches 882 are shown, this is not intended to be limiting. In at least one embodiment, each of the server(s) 878 may include any number of GPUs 884, CPUs 880, and / or PCIe switches 882 in any combination, including, but not limited to, For example, in at least one embodiment, server(s) 878 may each include 8, 16, 32, and / or more GPUs 884.

[0167] In at least one embodiment, server(s) 878 may receive image data from the vehicle over network(s) 890 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, server(s) 878 may transmit updated or unupdated neural network 892 and / or map information 894, including, but not limited to, information regarding traffic and road conditions, to the vehicle over network(s) 890. In at least one embodiment, updates to map information 894 may include updates to HD map 822, such as, but not limited to, information regarding construction sites, potholes, detours, flooding, and / or other obstacles. In at least one embodiment, neural network 892 and / or map information 894 may have arisen from new training and / or experience represented in data received from any number of vehicles in the environment and / or may be based at least in part on training performed at a data center (e.g., using server(s) 878 and / or other servers).

[0168] In at least one embodiment, server(s) 878 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or subjected to other preprocessing (e.g., if the associated neural network benefits from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., sent to the vehicle via network(s) 890) and / or used by server(s) 878 to remotely monitor the vehicle.

[0169] In at least one embodiment, server(s) 878 may receive data from vehicles and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, server(s) 878 may include deep learning supercomputers and / or special-purpose AI computers powered by GPU(s) 884, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server(s) 878 may include a deep learning infrastructure using CPU-powered data centers.

[0170] In at least one embodiment, the deep learning infrastructure of server(s) 878 may be capable of fast real-time inference and may use that capability to assess and verify the health of processors, software, and / or associated hardware in vehicle 800. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 800, such as a series of images and / or objects that vehicle 800 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to the objects identified by vehicle 800; if the results do not match and the deep learning infrastructure concludes that the AI ​​in vehicle 800 has failed, server(s) 878 may send a signal to vehicle 800 instructing a fail-safe computer in vehicle 800 to assume control, notify passengers, and complete a safe parking maneuver.

[0171] In at least one embodiment, server(s) 878 may include GPU(s) 884 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT3 devices). In at least one embodiment, the combination of GPU-powered servers and inference acceleration may enable real-time response. In at least one embodiment, servers powered by CPUs, FPGAs, and other processors may be used for inference, such as when performance is less critical. In at least one embodiment, hardware structure(s) 515 are used to implement one or more embodiments. Details regarding hardware structure(s) 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B.

[0172] Computer Systems 9 is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components, a system-on-a-chip (SOC), or some combination thereof, formed with a processor that may include an execution unit for executing instructions according to at least one embodiment. In at least one embodiment, computer system 900 may include components such as processor 902 to employ an execution unit that includes logic for implementing algorithms to process data according to the present disclosure, such as, but not limited to, the embodiments described herein. In at least one embodiment, computer system 900 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™, and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 900 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used.

[0173] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, an embedded application may include a microcontroller, a digital signal processor ("DSP"), a system-on-chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system capable of implementing one or more instructions according to at least one embodiment.

[0174] In at least one embodiment, computer system 900 may include, but is not limited to, a processor 902, which may include one or more execution units 908 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 900 is a single-processor desktop or server system, while in other embodiments, computer system 900 may be a multi-processor system. In at least one embodiment, processor 902 may include, but is not limited to, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as, for example, a digital signal processor. In at least one embodiment, the processor 902 may be coupled to a processor bus 910 that may transmit data signals between the processor 902 and other components in the computer system 900.

[0175] In at least one embodiment, processor 902 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 904. In at least one embodiment, processor 902 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 902. Other embodiments may include a combination of both internal and external cache, depending on the particular implementation and needs. In at least one embodiment, register file 906 may store different types of data in various registers, including, but not limited to, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0176] In at least one embodiment, an execution unit 908 including logic for performing integer and floating-point operations may also be present in the processor 902. In at least one embodiment, the processor 902 may also include a microcode (“u-code”) read-only memory (“ROM”) that stores microcode for some macroinstructions. In at least one embodiment, the execution unit 908 may include logic for dealing with a packed instruction set 909. In at least one embodiment, by including the packed instruction set 909, along with associated circuitry for executing the instructions, in the instruction set of a general-purpose processor, operations used by many multimedia applications may be performed using packed data in the processor 902. In at least one embodiment, many multimedia applications may be accelerated and run more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0177] In at least one embodiment, the execution unit 908 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuitry. In at least one embodiment, the computer system 900 may include, but is not limited to, a memory 920. In at least one embodiment, the memory 920 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, the memory 920 may store instruction(s) 919 and / or data 921 represented by data signals that may be executed by the processor 902.

[0178] In at least one embodiment, a system logic chip may be coupled to the processor bus 910 and the memory 920. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 916, and the processor 902 may communicate with the MCH 916 via the processor bus 910. In at least one embodiment, the MCH 916 may provide a high-bandwidth memory path 918 to the memory 920 for instruction and data storage, and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 916 may direct data signals between the processor 902, the memory 920, and other components in the computer system 900, and may bridge data signals between the processor bus 910, the memory 920, and a system I / O interface 922. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 916 may be coupled to memory 920 through a high-bandwidth memory path 918, and the graphics / video card 912 may be coupled to the MCH 916 via an Accelerated Graphics Port (“AGP”) interconnect 914.

[0179] In at least one embodiment, computer system 900 may use system I / O interface 922 as a proprietary hub interface bus to couple MCH 916 to I / O controller hub (“ICH”) 930. In at least one embodiment, ICH 930 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripherals to memory 920, a chipset, and processor 902. Examples may include, but are not limited to, an audio controller 929, a firmware hub ("flash BIOS") 928, a wireless transceiver 926, data storage 924, a legacy I / O controller 923 including a user input and keyboard interface 925, a serial expansion port 927 such as a Universal Serial Bus ("USB") port, and a network controller 934. In at least one embodiment, data storage 924 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0180] In at least one embodiment, Figure 9 illustrates a system including interconnected hardware devices or "chips," although in other embodiments, Figure 9 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in Figure 9 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 900 are interconnected using a compute express link (CXL) interconnect.

[0181] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with Figures 5A and 5B. In at least one embodiment, inference and / or training logic 515 may be used in the system of Figure 9 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0182] In various embodiments, the computer system executes a load balancer, as described above, that distributes operations (e.g., transformation of video frames) across CPUs, application specific integrated circuits (ASICs), GPUs, FPGAs, DPUs, or other hardware during execution of a video analysis pipeline or other application.

[0183] 10 is a block diagram illustrating an electronic device 1000 for utilizing a processor 1010, according to at least one embodiment. In at least one embodiment, the electronic device 1000 may be, for example, but not limited to, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0184] In at least one embodiment, electronic device 1000 may include, without limitation, a processor 1010 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. 2The devices may be coupled using a bus or interface, such as a C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 10 illustrates a system including interconnected hardware devices or “chips,” although in other embodiments, FIG. 10 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 10 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 10 are interconnected using a Compute Express Link (CXL) interconnect.

[0185] In at least one embodiment, FIG. 10 includes a display 1024, a touch screen 1025, a touch pad 1030, a Near Field Communication ("NFC") unit 1045, a sensor hub 1040, a thermal sensor 1046, an Express Chipset ("EC") 1035, a Trusted Platform Module ("TPM") 1038, a BIOS / firmware / flash memory ("BIOS,FW flash") 1022, a DSP 1060, a drive 1020, such as a solid state disk ("SSD") or hard disk drive ("HDD"), a wireless local area network ("WLAN") unit 1050, a Bluetooth unit 1052, a wireless wide area network ("WWAN") unit 1054, a Bluetooth module 1056, a Bluetooth-enabled device 1058 ... Network) 1056, a Global Positioning System (GPS) unit 1055, a camera such as a USB 3.0 camera (“USB 3.0 Camera”) 1054, and / or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1015, implemented, for example, in the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0186] In at least one embodiment, other components may be communicatively coupled to the processor 1010 through the components described herein. In at least one embodiment, an accelerometer 1041, an ambient light sensor (“ALS”) 1042, a compass 1043, and a gyroscope 1044 may be communicatively coupled to the sensor hub 1040. In at least one embodiment, a thermal sensor 1039, a fan 1037, a keyboard 1036, and a touchpad 1030 may be communicatively coupled to the EC 1035. In at least one embodiment, a speaker 1063, headphones 1064, and a microphone (“mic”) 1065 may be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 1062, which may be communicatively coupled to the DSP 1060. In at least one embodiment, the audio unit 1062 may include, for example, without limitation, an audio coder / decoder ("codec") and a Class D amplifier. In at least one embodiment, a SIM card ("SIM") 1057 may be communicatively coupled to the WWAN unit 1056. In at least one embodiment, components such as the WLAN unit 1050 and Bluetooth unit 1052, and the WWAN unit 1056 may be implemented in a Next Generation Form Factor ("NGFF").

[0187] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, inference and / or training logic 515 may be used in the system of Figure 10 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0188] 11 illustrates a computer system 1100, according to at least one embodiment. In at least one embodiment, the computer system 1100 is configured to implement the various processes and methods described throughout this disclosure.

[0189] In at least one embodiment, computer system 1100 includes, but is not limited to, at least one central processing unit ("CPU") 1102 connected to a communication bus 1110 implemented using any suitable protocol, such as, but not limited to, PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol(s). In at least one embodiment, computer system 1100 includes, but is not limited to, main memory 1104 and control logic (e.g., implemented as hardware, software, or a combination thereof), with data stored in main memory 1104, which may be in the form of random-access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 1122 provides an interface to other computing devices and networks for computer system 1100 to receive data from and transmit data to other systems.

[0190] In at least one embodiment, computer system 1100 includes, but is not limited to, input device(s) 1108, a parallel processing system 1112, and a display device 1106, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED") display, plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device(s) 1108, such as a keyboard, mouse, touchpad, microphone, or the like. In at least one embodiment, each of the modules described herein may be on a single semiconductor platform to form a processing system.

[0191] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, inference and / or training logic 515 may be used in the system of Figure 11 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0192] 12 illustrates a computer system 1200, according to at least one embodiment. In at least one embodiment, computer system 1200 may include, but is not limited to, a computer 1210 and a USB stick 1220. In at least one embodiment, computer 1210 may include, but is not limited to, any number and type of processor (not shown) and memory (not shown). In at least one embodiment, computer 1210 may include, but is not limited to, a server, a cloud instance, a laptop, or a desktop computer.

[0193] In at least one embodiment, USB stick 1220 includes, but is not limited to, a processing unit 1230, a USB interface 1240, and USB interface logic 1250. In at least one embodiment, processing unit 1230 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1230 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1230 comprises an application specific integrated circuit ("ASIC") optimized to perform any quantity and type of operations related to machine learning. For example, in at least one embodiment, processing unit 1230 is a tensor processing unit ("TPC") optimized to perform machine vision inference operations. In at least one embodiment, processing unit 1230 is a vision processing unit ("VPU") optimized to perform machine vision and machine learning inference operations.

[0194] In at least one embodiment, USB interface 1240 can be any type of USB connector or socket. For example, in at least one embodiment, USB interface 1240 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1240 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1250 can include any amount and type of logic that enables processing unit 1230 to interface with a device (e.g., computer 1210) via USB connector 1240.

[0195] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with Figures 5A and 5B. In at least one embodiment, inference and / or training logic 515 may be used in the system of Figure 12 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0196] FIG. 13A illustrates an exemplary architecture in which multiple GPUs 1310(1)-1310(N) are communicatively coupled to multiple multicore processors 1305(1)-1305(M) via high-speed links 1340(1)-1340(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1340(1)-1340(N) support communication throughputs of 4 GB / s, 30 GB / s, 80 GB / s, or more. In at least one embodiment, various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure.

[0197] Further, in at least one embodiment, two or more of the GPUs 1310 are interconnected via high-speed links 1329(1)-1329(2), which may be implemented using similar or different protocols / links as those used for the high-speed links 1340(1)-1340(N). Similarly, two or more of the multicore processors 1305 may be connected via high-speed link 1328, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communications between the various system components shown in FIG. 13A may be achieved using similar protocols / links (e.g., via a common interconnect fabric).

[0198] In at least one embodiment, each multicore processor 1305 is communicatively coupled to processor memory 1301(1)-1301(M) via a memory interconnect 1326(1)-1326(M), respectively, and each GPU 1310(1)-1310(N) is communicatively coupled to GPU memory 1320(1)-1320(N), respectively, via a GPU memory interconnect 1350(1)-1350(N). In at least one embodiment, memory interconnects 1326 and 1350 may utilize similar or different memory access technologies. By way of illustration, and not limitation, processor memory 1301(1)-1301(M) and GPU memory 1320 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-Ram. In at least one embodiment, one portion of processor memory 1301 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0199] As described herein, various multicore processors 1305 and GPUs 1310 may each be physically coupled to a specific memory 1301, 1320, and / or a unified memory architecture may be implemented in which a virtual system address space (also called an "effective address" space) is distributed among various physical memories. For example, processor memories 1301(1) through 1301(M) may each have a 64 GB system memory address space, and GPU memories 1320(1) through 1320(N) may each have a 32 GB system memory address space, resulting in a total of 256 GB of addressable memory when M=2 and N=4. Other values ​​for N and M are possible.

[0200] 13B shows additional details of the interconnection between multi-core processor 1307 and graphics acceleration module 1346, according to one example embodiment. In at least one embodiment, graphics acceleration module 1346 may include one or more GPU chips integrated on a line card that is coupled to processor 1307 via high-speed link 1340 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1346 may alternatively be integrated into the package or chip with processor 1307.

[0201] In at least one embodiment, the processor 1307 includes multiple cores 1360A-1360D, each having a translation lookaside buffer (“TLB”) 1361A-1361D and one or more caches 1362A-1362D. In at least one embodiment, the cores 1360A-1360D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1362A-1362D may comprise a level 1 (L1) cache and a level 2 (L2) cache. Additionally, one or more shared caches 1356 may be included in the caches 1362A-1362D and shared by the set of cores 1360A-1360D. For example, one embodiment of processor 1307 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more of the L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, processor 1307 and graphics acceleration module 1346 interface with system memory 1314, which may include processor memories 1301(1)-1301(M) of FIG. 13A.

[0202] In at least one embodiment, coherency is maintained for data and instructions stored in the various caches 1362A-1362D, 1356 and system memory 1314 via inter-core communication over coherence bus 1364. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith for communicating over coherence bus 1364 in response to detected reads or writes to particular cache lines. In at least one embodiment, a cache snooping protocol is implemented over coherence bus 1364 to snoop cache accesses.

[0203] In at least one embodiment, proxy circuit 1325 communicatively couples graphics acceleration module 1346 to coherence bus 1364, which enables graphics acceleration module 1346 to participate in cache coherence protocols as a peer of cores 1360A-1360D. In particular, in at least one embodiment, interface 1335 provides connectivity to proxy circuit 1325 via high-speed link 1340, and interface 1337 connects graphics acceleration module 1346 to high-speed link 1340.

[0204] In at least one embodiment, the accelerator integrated circuit 1336 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1331(1)-1331(N) of the graphics acceleration module 1346. In at least one embodiment, the graphics processing engines 1331(1)-1331(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1331(1)-1331(N) may alternatively comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1346 may be a GPU with multiple graphics processing engines 1331(1)-1331(N), or the graphics processing engines 1331(1)-1331(N) may be individual GPUs integrated into a common package, line card, or chip.

[0205] In at least one embodiment, accelerator integrated circuitry 1336 includes a memory management unit (MMU) 1339 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation), and a memory access protocol for accessing system memory 1314. In at least one embodiment, MMU 1339 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1338 may store commands and data for efficient access by graphics processing engines 1331(1)-1331(N). In at least one embodiment, data stored in cache 1338 and graphics memory 1333(1)-1333(M) is kept coherent with core caches 1362A-1362D, 1356 and system memory 1314, possibly using fetch unit 1344. As noted, this may be accomplished via proxy circuitry 1325 on behalf of cache 1338 and memory 1333(1)-1333(M) (e.g., sending updates to and receiving updates from cache 1338 related to modifications / accesses of cache lines in processor caches 1362A-1362D, 1356).

[0206] In at least one embodiment, a set of registers 1345 stores context data for threads executed by graphics processing engines 1331(1)-1331(N), and a context management circuit 1348 manages thread contexts. For example, the context management circuit 1348 may perform save and restore operations to save and restore the context of various threads during a context switch (e.g., a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 1348 may store current register values ​​in a designated area in memory (e.g., identified by a context pointer). The context management circuit 1348 may then restore the register values ​​when returning to the context. In at least one embodiment, the interrupt management circuit 1347 receives and processes interrupts received from system devices.

[0207] In at least one embodiment, virtual / effective addresses from the graphics processing engine 1331 are translated to real / physical addresses in the system memory 1314 by the MMU 1339. In at least one embodiment, the accelerator integration circuit 1336 supports multiple (e.g., four, eight, or sixteen) graphics accelerator modules 1346 and / or other accelerator devices. In at least one embodiment, the graphics accelerator modules 1346 may be dedicated to a single application executing on the processor 1307 or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment exists in which the resources of the graphics processing engines 1331(1)-1331(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0208] In at least one embodiment, the accelerator integrated circuitry 1336 acts as a bridge to the system for the graphics acceleration module 1346 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuitry 1336 may provide a virtualization facility for a host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1331(1)-1331(N).

[0209] In at least one embodiment, the hardware resources of the graphics processing engines 1331(1)-1331(N) are explicitly mapped into the real address space seen by the host processor 1307, so that any host processor can directly address these resources using effective address values. In at least one embodiment, one function of the accelerator integrated circuitry 1336 is to physically separate the graphics processing engines 1331(1)-1331(N) so that they appear as independent units to the system.

[0210] In at least one embodiment, one or more graphics memories 1333(1) through 1333(M) are coupled to each of the graphics processing engines 1331(1) through 1331(N), respectively, where N=M. In at least one embodiment, the graphics memories 1333(1) through 1333(M) store instructions and data being processed by each of the graphics processing engines 1331(1) through 1331(N). In at least one embodiment, the graphics memories 1333(1) through 1333(M) may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0211] In at least one embodiment, to reduce data traffic over high-speed link 1340, biasing techniques may be used to ensure that the data stored in graphics memory 1333(1)-1333(M) will be most frequently used by graphics processing engines 1331(1)-1331(N) and preferably is data that is not used (or at least not frequently used) by cores 1360A-1360D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (preferably not needed by graphics processing engines 1331(1)-1331(N)) in caches 1362A-1362D, 1356, and system memory 1314.

[0212] 13C shows another exemplary embodiment in which the accelerator integration circuitry 1336 is incorporated within the processor 1307. In this embodiment, the graphics processing engines 1331(1)-1331(N) communicate directly over high-speed link 11340 to the accelerator integration circuitry 1336 via interface 1337 and interface 1335 (which again may be any form of bus or interface protocol). In at least one embodiment, the accelerator integration circuitry 1336 may perform operations similar to those described with respect to FIG. 13B, but potentially at a higher throughput given its proximity to the coherence bus 1364 and caches 1362A-1362D, 1356. In at least one embodiment, the accelerator integrated circuitry supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuitry 1336 and a programming model controlled by the graphics acceleration module 1346.

[0213] In at least one embodiment, graphics processing engines 1331(1)-1331(N) may be dedicated to a single application or process under a single operating system. In at least one embodiment, a single application may funnel other application requests to graphics processing engines 1331(1)-1331(N) to provide virtualization within a VM / partition.

[0214] In at least one embodiment, graphics processing engines 1331(1)-1331(N) may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize graphics processing engines 1331(1)-1331(N) to allow access by each operating system. In at least one embodiment, for a single-partition system without a hypervisor, graphics processing engines 1331(1)-1331(N) are owned by the operating system. In at least one embodiment, the operating system may virtualize graphics processing engines 1331(1)-1331(N) to provide access to each process or application.

[0215] In at least one embodiment, the graphics acceleration module 1346 or an individual graphics processing engine 1331(1)-1331(N) selects a process element using a process handle. In at least one embodiment, the process element is stored in system memory 1314 and is addressable using the effective address-to-real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to a host process when registering the host process's context with the graphics processing engine 1331(1)-1331(N) (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0216] FIG. 13D illustrates an exemplary accelerator integration slice 1390. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of accelerator integration circuitry 1336. In at least one embodiment, an application's effective address space 1382 in system memory 1314 stores a process element 1383. In at least one embodiment, the process element 1383 is stored in response to a GPU call 1381 from an application 1380 executing on processor 1307. In at least one embodiment, the process element 1383 contains the process state of the corresponding application 1380. In at least one embodiment, a work descriptor (WD) 1384 included in the process element 1383 may be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, the WD 1384 is a pointer to a job request queue in the application's effective address space 1382.

[0217] In at least one embodiment, the graphics acceleration module 1346 and / or the individual graphics processing engines 1331(1)-1331(N) may be shared by all or a subset of the processes in the system. In at least one embodiment, infrastructure may be included for setting process state and submitting WD 1384 to the graphics acceleration module 1346 to start jobs in a virtualized environment.

[0218] In at least one embodiment, the dedicated process programming model is implementation specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1346 or an individual graphics processing engine 1331. In at least one embodiment, when the graphics acceleration module 1346 is owned by a single process, the hypervisor initializes the accelerator integration circuitry 1336 for the owning partition, and the operating system initializes the accelerator integration circuitry 1336 for the owning process when the graphics acceleration module 1346 is allocated.

[0219] In at least one embodiment, in operation, a WD fetch unit 1391 in the accelerator integrated slice 1390 fetches the next WD 1384, which contains instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1346. In at least one embodiment, as shown, data from the WD 1384 is stored in registers 1345 and may be used by the MMU 1339, the interrupt management circuitry 1347, and / or the context management circuitry 1348. For example, one embodiment of the MMU 1339 includes segment / page walk circuitry for accessing a segment / page table 1386 within the OS virtual address space 1385. In at least one embodiment, the interrupt management circuitry 1347 may process an interrupt event 1392 received from the graphics acceleration module 1346. In at least one embodiment, when performing graphics operations, effective addresses 1393 generated by graphics processing engines 1331(1)-1331(N) are translated into real addresses by MMU 1339.

[0220] In at least one embodiment, registers 1345 may be replicated for each graphics processing engine 1331(1)-1331(N) and / or graphics acceleration module 1346 and initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers may be included in accelerator integration slice 1390. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Hypervisor Initialization Registers Register # Description 1 Slice Control Register 2 Real Address (RA) Scheduled Process Area Pointer 3 Permission Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Usage Record Pointer 9 Storage Description Registers

[0221] Exemplary registers that may be initialized by the operating system are shown in Table 2. Table 2 - Operating System Initialization Registers Register # Description 1 Process and Thread Identification 2 Effective Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) Accelerator Usage Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Permission Mask 6 Work Descriptor

[0222] In at least one embodiment, each WD 1384 is specific to a particular graphics acceleration module 1346 and / or graphics processing engine 1331(1)-1331(N). In at least one embodiment, WD 1384 contains all the information needed by a graphics processing engine 1331(1)-1331(N) to perform work, or it may be a pointer to a memory location where an application has set up a command queue for work to be completed.

[0223] 13E illustrates additional details of an exemplary embodiment of the sharing model. This embodiment includes a hypervisor real address space 1398 in which a process element list 1399 is stored. In at least one embodiment, the hypervisor real address space 1398 is accessible through a hypervisor 1396 that virtualizes a graphics acceleration module engine for an operating system 1395.

[0224] In at least one embodiment, a shared programming model allows all or a subset of processes from all or a subset of partitions in a system to use the graphics acceleration module 1346. In at least one embodiment, there are two programming models in which the graphics acceleration module 1346 is shared by multiple processes and partitions: timeslice shared and graphics-directed shared.

[0225] In at least one embodiment, in this model, system hypervisor 1396 owns graphics acceleration module 1346 and makes its functionality available to all operating systems 1395. In at least one embodiment, in order for graphics acceleration module 1346 to support virtualization by system hypervisor 1396, graphics acceleration module 1346 may adhere to several requirements, such as (1) an application's job requests must be autonomous (i.e., no state needs to be maintained between jobs) or graphics acceleration module 1346 must provide a context save and restore mechanism, (2) graphics acceleration module 1346 must guarantee that an application's job requests will complete in a specified amount of time, including any translation failures, or graphics acceleration module 1346 must provide the ability to preempt job processing, and (3) graphics acceleration module 1346 must guarantee fairness between processes when operating in a specified shared programming model.

[0226] In at least one embodiment, the application 1380 is required to make a system call to the operating system 1395 with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the acceleration function of interest for the system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1346 and may be in the form of a graphics acceleration module 1346 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure for describing the work to be performed by the graphics acceleration module 1346.

[0227] In at least one embodiment, the AMR value is the AMR state to use for the current process. In at least one embodiment, the value passed to the operating system is the same as the application setting the AMR. In at least one embodiment, if the accelerator integrated circuit 1336 (not shown) implementation and the graphics acceleration module 1346 implementation do not support a User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1396 may optionally apply the current Authority Mask Override Register (AMOR) value before passing the AMR to the process element 1383. In at least one embodiment, the CSRP is one of the registers 1345 that contains the effective address of an area in the application's effective address space 1382 for the graphics acceleration module 1346 to save and restore context state. In at least one embodiment, this pointer is optional if no state is required to be preserved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be pinned system memory.

[0228] Upon receiving the system call, the operating system 1395 may verify that the application 1380 is registered and authorized to use the graphics acceleration module 1346. In at least one embodiment, the operating system 1395 then calls the hypervisor 1396 with the information shown in Table 3. Table 3 - OS to Hypervisor Call Parameters Parameter# Description 1 Work Descriptor (WD) 2 Permission Mask Register (AMR) values ​​(potentially masked) 3 Effective Address (EA) Context Save / Restore Area Pointer (CSRP) 4. Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0229] In at least one embodiment, upon receiving the hypervisor call, the hypervisor 1396 verifies that the operating system 1395 is registered and authorized to use the graphics acceleration module 1346. In at least one embodiment, the hypervisor 1396 then places the process element 1383 in a process element linked list for the corresponding graphics acceleration module 1346 type. In at least one embodiment, the process element may include the information shown in Table 4. Table 4 - Process Element Information Element # Description 1 Work Descriptor (WD) 2 Permission Mask Register (AMR) values ​​(potentially masked) 3 Effective Address (EA) Context Save / Restore Area Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Usage Record Pointer (AURP) 6 Virtual address of the Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table derived from hypervisor call parameters 9 State register (SR) value 10 Logical partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Usage Record Pointer 12 Storage Descriptor Register (SDR)

[0230] In at least one embodiment, the hypervisor initializes a number of accelerator integration slice 1390 registers 1345 .

[0231] As shown in FIG. 13F, at least one embodiment uses a unified memory addressable via a common virtual memory address space used to access physical processor memory 1301(1)-1301(N) and GPU memory 1320(1)-1320(N). In this implementation, operations performed on GPUs 1310(1)-1310(N) utilize the same virtual / effective memory address space to access processor memory 1301(1)-1301(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1301(1), a second portion is allocated to second processor memory 1301(N), a third portion is allocated to GPU memory 1320(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of the processor memory 1301 and the GPU memory 1320, allowing either processor or GPU to access either physical memory where the virtual addresses are mapped to physical memory.

[0232] In at least one embodiment, bias / coherence management circuitry 1394A-1394E within one or more of the MMUs 1339A-1339E ensures cache coherence between caches of one or more host processors (e.g., 1305) and caches of the GPU 1310 and implements biasing techniques to indicate the physical memory in which some types of data should be stored. In at least one embodiment, although multiple instances of bias / coherence management circuitry 1394A-1394E are shown in FIG. 13F, bias / coherence circuitry may be implemented within the MMUs of one or more host processors 1305 and / or within the accelerator integration circuit 1336.

[0233] One embodiment allows GPU memory 1320 to be mapped as part of system memory and accessed using shared virtual memory (SVM) techniques, but without incurring the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1320 as system memory without cumbersome cache coherence overhead provides a beneficial operating environment for GPU offload. In at least one embodiment, this mechanism allows host processor 1305 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies involve driver calls, interrupts, and memory mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. In at least one embodiment, the ability to access GPU memory 1320 without cache coherence overhead can be essential to the execution time of offloaded computations. In at least one embodiment, for example, in the presence of significant streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1310. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation can play a role in determining the effectiveness of GPU offload.

[0234] In at least one embodiment, the selection of the GPU bias and the host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, and the bias table may be a page-granular structure including one or two bits per GPU-attached memory page (e.g., controlled at memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU memories 1320, with or without a bias cache in the GPU 1310 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the entire bias table may be maintained within the GPU.

[0235] In at least one embodiment, the bias table entry associated with each access to GPU-biased memory 1320 is accessed prior to the actual access to the GPU memory, causing the following actions: In at least one embodiment, a local request from the GPU 1310 that finds its page in the GPU bias is forwarded directly to the corresponding GPU memory 1320. In at least one embodiment, a local request from the GPU that finds its page in the host bias is forwarded to the processor 1305 (e.g., via the high-speed link described above). In at least one embodiment, a request from the processor 1305 that finds the requested page in the host processor bias completes the request like a normal memory read. Alternatively, a request targeting a GPU-biased page may be forwarded to the GPU 1310. In at least one embodiment, the GPU may then migrate the page to the host processor bias if it is not currently using the page. In at least one embodiment, the bias state of a page may be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or for a limited set of cases, solely by a hardware-based mechanism.

[0236] In at least one embodiment, one mechanism for changing the bias state employs an API call (e.g., OpenCL) that calls a GPU device driver, which sends a message (or queues a command descriptor) to the GPU instructing the GPU to change the bias state and, for some transitions, to perform a cache flushing operation at the host. In at least one embodiment, a cache flushing operation is used for transitions from host processor 1305 bias to GPU bias, but not for transitions in the opposite direction.

[0237] In at least one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages uncacheable by the host processor 1305. In at least one embodiment, to access these pages, the processor 1305 may request access from the GPU 1310, which may or may not immediately grant the access. Thus, in at least one embodiment, to reduce communication between the processor 1305 and the GPU 1310, it is beneficial to ensure that GPU-biased pages are those that are needed by the GPU but not by the host processor 1305, and vice versa.

[0238] To implement one or more embodiments, hardware structure(s) 515 are used, and details regarding the hardware structure(s) 515 may be provided herein in conjunction with Figures 5A and / or 5B.

[0239] 14 illustrates an exemplary integrated circuit and associated graphics processor that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0240] 14 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1400 that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, integrated circuit 1400 includes one or more application processors 1405 (e.g., CPUs), at least one graphics processor 1410, and may additionally include an image processor 1415 and / or a video processor 1420, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1400 includes a USB controller 1425, a UART controller 1430, an SPI / SDIO controller 1435, and an I / O controller 1440. 2 2S / I 2 The integrated circuit 1400 may include peripheral or bus logic including a HDMI (High-Definition Multimedia Interface) controller 1440. In at least one embodiment, the integrated circuit 1400 may include a display device 1445 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1450 and a Mobile Industry Processor Interface (MIPI) display interface 1455. In at least one embodiment, storage may be provided by a flash memory subsystem 1460 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1465 for access to an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1470.

[0241] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with FIGURES 5A and / or 5B. In at least one embodiment, inference and / or training logic 515 may be used in integrated circuit 1400 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0242] 15A-15B illustrate an exemplary integrated circuit and associated graphics processor that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0243] 15A and 15B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 15A illustrates an exemplary graphics processor 1510 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 15B illustrates an additional exemplary graphics processor 1540 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 1510 of FIG. 15A is a low-power graphics processor core. In at least one embodiment, graphics processor 1540 of FIG. 15B is a higher-performance graphics processor core. In at least one embodiment, each of graphics processors 1510, 1540 may be a variation of graphics processor 1410 of FIG. 14.

[0244] In at least one embodiment, the graphics processor 1510 includes a vertex processor 1505 and one or more fragment processors 1515A-1515N (e.g., 1515A, 1515B, 1515C, 1515D-1515N-1, and 1515N). In at least one embodiment, the graphics processor 1510 can execute different shader programs through separate logic, whereby the vertex processor 1505 is optimized to perform operations for vertex shader programs, and one or more fragment processors 1515A-1515N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1505 performs the vertex processing stage of the 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, the fragment processor(s) 1515A-1515N use the primitive and vertex data generated by the vertex processor 1505 to create a frame buffer that is displayed on a display device. In at least one embodiment, the fragment processor(s) 1515A-1515N are optimized to execute fragment shader programs such as those provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs such as those provided in the Direct 3D API.

[0245] In at least one embodiment, the graphics processor 1510 additionally includes one or more memory management units (MMUs) 1520A-1520B, cache(s) 1525A-1525B, and circuit interconnect(s) 1530A-1530B. In at least one embodiment, the one or more MMUs 1520A-1520B provide virtual-to-physical address mapping for the graphics processor 1510, including the vertex processor 1505 and / or fragment processor(s) 1515A-1515N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 1525A-1525B. In at least one embodiment, one or more MMUs 1520A-1520B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1405, image processor 1415, and / or video processor 1420 of Figure 14, thereby allowing each processor 1405-1420 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1530A-1530B enable graphics processor 1510 to interface with other IP cores in the SoC, either via the SoC's internal bus or via a direct connection.

[0246] 15B, the graphics processor 1540 includes one or more shader cores 1555A-1555N (e.g., 1555A, 1555B, 1555C, 1555D, 1555E, 1555F-1555N-1, and 1555N), where the one or more shader cores 1555A-1555N provide a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1540 includes an inter-core task manager 1545 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1555A-1555N, and a tiling unit 1558 for accelerating tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0247] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with FIG. 5A and / or 5B. In at least one embodiment, inference and / or training logic 515 may be used in integrated circuits 15A and / or 15B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0248] 16A-16B illustrate additional exemplary graphics processor logic according to embodiments described herein. FIG. 16A illustrates a graphics core 1600, which in at least one embodiment may be included within graphics processor 1410 of FIG. 14, or in at least one embodiment may be unified shader cores 1555A-1555N as in FIG. 15B. FIG. 16B illustrates a highly parallel general-purpose graphics processing unit ("GPGPU") 1630 suitable for implementation on a multi-chip module in at least one embodiment.

[0249] In at least one embodiment, graphics core 1600 includes a shared instruction cache 1602, a texture unit 1618, and a cache / shared memory 1620, which are common to execution resources within graphics core 1600. In at least one embodiment, graphics core 1600 may include multiple slices 1601A-1601N, or partitions for each core, and a graphics processor may include multiple instances of graphics core 1600. In at least one embodiment, slices 1601A-1601N may include support logic including local instruction caches 1604A-1604N, thread schedulers 1606A-1606N, thread dispatchers 1608A-1608N, and sets of registers 1610A-1610N. In at least one embodiment, slices 1601A-1601N may include a set of additional function units (AFUs) 1612A-1612N, floating-point units (FPUs) 1614A-1614N, integer arithmetic logic units (ALUs) 1616A-1616N, address computational units (ACUs) 1613A-1613N, double-precision floating-point units (DPFPUs) 1615A-1615N, and matrix processing units (MPUs) 1617A-1617N.

[0250] In at least one embodiment, the FPUs 1614A-1614N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 1615A-1615N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1616A-1616N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and may be configured for mixed-precision operations. In at least one embodiment, the MPUs 1617A-1617N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1617A-1617N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1612A-1612N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0251] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B. In at least one embodiment, inference and / or training logic 515 may be used in graphics core 1600 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0252] FIG. 16B illustrates a general-purpose processing unit (GPGPU) 1630, which in at least one embodiment may be configured to enable highly parallel compute operations to be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 1630 may be directly linked to other instances of the GPGPU 1630 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, the GPGPU 1630 includes a host interface 1632 to enable connection with a host processor. In at least one embodiment, the host interface 1632 is a PCI Express interface. In at least one embodiment, the host interface 1632 may be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 1630 receives commands from the host processor and distributes execution threads associated with those commands across a set of compute clusters 1636A-1636H using a global scheduler 1634. In at least one embodiment, the compute clusters 1636A-1636H share a cache memory 1638. In at least one embodiment, the cache memory 1638 can act as a higher-level cache for the cache memories within the compute clusters 1636A-1636H.

[0253] In at least one embodiment, GPGPU 1630 includes memory 1644A-1644B coupled to compute clusters 1636A-1636H via a set of memory controllers 1642A-1642B. In at least one embodiment, memory 1644A-1644B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0254] In at least one embodiment, compute clusters 1636A-1636H each include a set of graphics cores, such as graphics core 1600 of FIG. 16A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 1636A-1636H may be configured to perform 16-bit or 32-bit floating-point operations, and a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0255] In at least one embodiment, multiple instances of GPGPU 1630 may be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 1636A-1636H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 1630 communicate via host interface 1632. In at least one embodiment, GPGPU 1630 includes an I / O hub 1639 that couples GPGPU 1630 to a GPU link 1640 that enables direct connection to other instances of GPGPU 1630. In at least one embodiment, GPU link 1640 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1630. In at least one embodiment, GPU link 1640 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1630 are located in separate data processing systems and communicate via a network device accessible via host interface 1632. In at least one embodiment, GPU link 1640 may be configured to allow connection to a host processor in addition to, or as an alternative to, host interface 1632.

[0256] In at least one embodiment, the GPGPU 1630 may be configured to train a neural network. In at least one embodiment, the GPGPU 1630 may be used within an inference platform. In at least one embodiment, when the GPGPU 1630 is used for inference, the GPGPU 1630 may include fewer compute clusters 1636A-1636H than when the GPGPU 1630 is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 1644A-1644B may differ between the inference configuration and the training configuration, with higher bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1630 may support inference-specific instructions. For example, in at least one embodiment, the inference configuration may provide support for one or more 8-bit integer dot product instructions, which may be used during inference operations for the deployed neural network.

[0257] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B. In at least one embodiment, inference and / or training logic 515 may be used in GPGPU 1630 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0258] 17 is a block diagram illustrating a computing system 1700 according to at least one embodiment. In at least one embodiment, the computing system 1700 includes a processing subsystem 1701 having one or more processors 1702 and a system memory 1704 that communicate via an interconnection path that may include a memory hub 1705. In at least one embodiment, the memory hub 1705 may be a separate component within a chipset component or may be incorporated within the one or more processors 1702. In at least one embodiment, the memory hub 1705 couples to an I / O subsystem 1711 via a communication link 1706. In at least one embodiment, the I / O subsystem 1711 includes an I / O hub 1707 that may enable the computing system 1700 to receive input from one or more input devices 1708. In at least one embodiment, I / O hub 1707 can enable a display controller, which may be included in one or more processors 1702, to provide output to one or more display devices 1710A. In at least one embodiment, the one or more display devices 1710A coupled with I / O hub 1707 can include local, internal, or embedded display devices.

[0259] In at least one embodiment, processing subsystem 1701 includes one or more parallel processors 1712 coupled to memory hub 1705 via a bus or other communication link 1713. In at least one embodiment, communication link 1713 may use one of any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, one or more parallel processors 1712 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, some or all of the parallel processor(s) 1712 form a graphics processing subsystem, which can output pixels to one of one or more display devices 1710A coupled via I / O hub 1707. In at least one embodiment, the parallel processor(s) 1712 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1710B.

[0260] In at least one embodiment, system storage unit 1714 may connect to I / O hub 1707 to provide a storage mechanism for computing system 1700. In at least one embodiment, I / O switch 1716 may be used to provide an interface mechanism to enable connections between I / O hub 1707 and other components, such as network adapter 1718 and / or wireless network adapter 1719, which may be embedded in the platform, as well as various other devices, which may be added via one or more add-in devices 1720. In at least one embodiment, network adapter 1718 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1719 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0261] In at least one embodiment, computing system 1700 may include other components not expressly shown, including USB or other port connections, optical storage drives, video capture devices, etc., and may be connected to I / O hub 1707. In at least one embodiment, the communication paths interconnecting the various components in FIG. 17 may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface and / or protocol(s), or interconnection protocol, such as an NV-Link high-speed interconnect.

[0262] In at least one embodiment, the parallel processor(s) 1712 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, to form a graphics processing unit (GPU). In at least one embodiment, the parallel processor(s) 1712 incorporate circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 1700 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor(s) 1712, memory hub 1705, processor(s) 1702, and I / O hub 1707 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1700 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1700 may be incorporated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0263] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with Figures 5A and / or 5B. In at least one embodiment, inference and / or training logic 515 may be used in the system of Figure 17 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0264] Processor 18A illustrates a parallel processor 1800, according to at least one embodiment. In at least one embodiment, various components of the parallel processor 1800 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 1800 is a variation of the one or more parallel processors 1712 illustrated in FIG. 17, according to an example embodiment.

[0265] In at least one embodiment, parallel processor 1800 includes parallel processing units 1802. In at least one embodiment, parallel processing units 1802 include I / O units 1804 that enable communication with other devices, including other instances of parallel processing units 1802. In at least one embodiment, I / O units 1804 may be directly connected to other devices. In at least one embodiment, I / O units 1804 connect to other devices through the use of a hub or switch interface, such as memory hub 1805. In at least one embodiment, the connection between memory hub 1805 and I / O units 1804 forms communication link 1813. In at least one embodiment, I / O units 1804 connect to host interface 1806 and memory crossbar 1816, where host interface 1806 receives commands intended to perform processing operations and memory crossbar 1816 receives commands intended to perform memory operations.

[0266] In at least one embodiment, when host interface 1806 receives command buffers via I / O unit 1804, host interface 1806 can direct work operations to implement those commands to front end 1808. In at least one embodiment, front end 1808 is coupled to scheduler 1810, which is configured to distribute commands or other work items to processing cluster array 1812. In at least one embodiment, scheduler 1810 ensures that processing cluster array 1812 is properly configured and in a valid state before tasks are distributed to clusters in processing cluster array 1812. In at least one embodiment, scheduler 1810 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1810 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularities, allowing rapid preemption and context switching of threads executing on the processing array 1812. In at least one embodiment, host software can present workloads for scheduling on the processing cluster array 1812 via one of multiple graphics processing paths. In at least one embodiment, the workloads can then be automatically distributed across the processing array clusters 1812 by scheduler 1810 logic in the microcontroller that includes the scheduler 1810.

[0267] In at least one embodiment, processing cluster array 1812 can include up to “N” processing clusters (e.g., cluster 1814A, cluster 1814B through cluster 1814N), where “N” represents a positive integer (which may be a different integer “N” than that used in other figures). In at least one embodiment, each cluster 1814A through 1814N of processing cluster array 1812 can execute multiple concurrent threads. In at least one embodiment, scheduler 1810 can allocate work to clusters 1814A through 1814N of processing cluster array 1812 using various scheduling and / or work distribution algorithms, which may vary depending on the workload occurring for each type of program or computation. In at least one embodiment, scheduling can be handled dynamically by scheduler 1810 or can be partially assisted by compiler logic during compilation of program logic configured for execution by processing cluster array 1812. In at least one embodiment, different clusters 1814A-1814N of processing cluster array 1812 may be allocated to process different types of programs or to perform different types of calculations.

[0268] In at least one embodiment, processing cluster array 1812 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 1812 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 1812 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0269] In at least one embodiment, the processing cluster array 1812 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 1812 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 1812 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1802 may transfer data from system memory via the I / O unit 1804 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1822) during processing and then written back to system memory.

[0270] In at least one embodiment, when parallel processing unit 1802 is used to perform graphics processing, scheduler 1810 may be configured to divide the processing workload into tasks of approximately equal size to better enable distribution of graphics processing operations to multiple clusters 1814A-1814N of processing cluster array 1812. In at least one embodiment, portions of processing cluster array 1812 may be configured to perform different types of processing. For example, in at least one embodiment, to produce a rendered image for display, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data produced by one or more of clusters 1814A-1814N may be stored in a buffer to allow the intermediate data to be transmitted between clusters 1814A-1814N for further processing.

[0271] In at least one embodiment, the processing cluster array 1812 may receive processing tasks to be performed via a scheduler 1810, which receives commands defining the processing tasks from the front end 1808. In at least one embodiment, the processing tasks may include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how the data should be processed (e.g., which program should be executed). In at least one embodiment, the scheduler 1810 may be configured to fetch the index corresponding to the task or may receive the index from the front end 1808. In at least one embodiment, the front end 1808 may be configured to ensure that the processing cluster array 1812 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0272] In at least one embodiment, each of one or more instances of parallel processing unit 1802 can be coupled to parallel processor memory 1822. In at least one embodiment, parallel processor memory 1822 can be accessed via memory crossbar 1816, which can receive memory requests from processing cluster array 1812 as well as I / O unit 1804. In at least one embodiment, memory crossbar 1816 can access parallel processor memory 1822 via memory interface 1818. In at least one embodiment, memory interface 1818 can include multiple partition units (e.g., partition unit 1820A, partition unit 1820B through partition unit 1820N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 1822. In at least one embodiment, the number of partition units 1820A-1820N is configured to equal the number of memory units, such that a first partition unit 1820A has a corresponding first memory unit 1824A, a second partition unit 1820B has a corresponding memory unit 1824B, and an Nth partition unit 1820N has a corresponding Nth memory unit 1824N. In at least one embodiment, the number of partition units 1820A-1820N may not equal the number of memory devices.

[0273] In at least one embodiment, the memory units 1824A-1824N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 1824A-1824N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 1822, render targets, such as frame buffers or texture maps, may be stored across the memory units 1824A-1824N, allowing the partition units 1820A-1820N to write portions of each render target in parallel. In at least one embodiment, the local instance of parallel processor memory 1822 may be eliminated in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

[0274] In at least one embodiment, any one of the clusters 1814A-1814N in the processing cluster array 1812 can process data that is to be written to any one of the memory units 1824A-1824N in the parallel processor memory 1822. In at least one embodiment, the memory crossbar 1816 can be configured to forward the output of each cluster 1814A-1814N to any partition unit 1820A-1820N that can perform additional processing operations on the output, or to another cluster 1814A-1814N. In at least one embodiment, each cluster 1814A-1814N can communicate with a memory interface 1818 through the memory crossbar 1816 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 1816 has a connection to a memory interface 1818 for communicating with the I / O units 1804, as well as a connection to a local instance of parallel processor memory 1822, which allows processing units in different processing clusters 1814A-1814N to communicate with system memory or other memory not local to the parallel processing units 1802. In at least one embodiment, the memory crossbar 1816 can use virtual channels to separate traffic streams between the clusters 1814A-1814N and the partition units 1820A-1820N.

[0275] In at least one embodiment, multiple instances of parallel processing unit 1802 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 1802 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1802 may include higher precision floating-point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 1802 or parallel processor 1800 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0276] FIG. 18B is a block diagram of a partition unit 1820 according to at least one embodiment. In at least one embodiment, partition unit 1820 is an instance of one of partition units 1820A-1820N of FIG. 18A. In at least one embodiment, partition unit 1820 includes an L2 cache 1821, a frame buffer interface 1825, and a ROP 1826 (raster operation unit). In at least one embodiment, L2 cache 1821 is a read / write cache configured to perform load and store operations received from memory crossbar 1816 and ROP 1826. In at least one embodiment, read misses and urgent writeback requests are output by L2 cache 1821 to frame buffer interface 1825 for processing. In at least one embodiment, updates may also be sent to the frame buffer via frame buffer interface 1825 for processing. In at least one embodiment, frame buffer interface 1825 interfaces with one of the memory units in a parallel processor memory, such as memory units 1824A-1824N (e.g., in parallel processor memory 1822) of FIG. 18.

[0277] In at least one embodiment, ROP1826 is a processing unit that performs raster operations such as stencil, z-test, and blending. In at least one embodiment, ROP1826 then outputs the processed graphics data that is stored in graphics memory. In at least one embodiment, ROP1826 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic that utilizes one or more of a plurality of compression algorithms. In at least one embodiment, the type of compression performed by ROP1826 may vary based on statistical characteristics of the data to be compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0278] In at least one embodiment, ROP 1826 is included within each processing cluster (e.g., clusters 1814A-1814N of FIG. 18A ) rather than within partition unit 1820. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted through memory crossbar 1816. In at least one embodiment, the processed graphics data may be displayed on a display device, such as one of one or more display devices 1710 of FIG. 17 , routed for further processing by processor(s) 1702, or routed for further processing by one of the processing entities in parallel processor 1800 of FIG. 18A .

[0279] FIG. 18C is a block diagram of a processing cluster 1814 within a parallel processing unit, according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of the processing clusters 1814A-1814N of FIG. 18A. In at least one embodiment, the processing cluster 1814 may be configured to execute many threads in parallel, where a "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, a single-instruction, multiple-data (SIMD) instruction issue technique is used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, a single-instruction, multiple-thread (SIMT) technique is used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster of the processing cluster.

[0280] In at least one embodiment, operation of the processing clusters 1814 may be controlled via a pipeline manager 1832 that distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1832 receives instructions from the scheduler 1810 of FIG. 18A and manages the execution of those instructions via the graphics multiprocessor 1834 and / or the texture unit 1836. In at least one embodiment, the graphics multiprocessor 1834 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within the processing clusters 1814. In at least one embodiment, one or more instances of the graphics multiprocessor 1834 may be included within the processing clusters 1814. In at least one embodiment, the graphics multiprocessor 1834 may process data, and a data crossbar 1840 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 1832 can facilitate the distribution of the processed data by specifying a destination for the processed data to be distributed through the data crossbar 1840.

[0281] In at least one embodiment, each graphics multiprocessor 1834 in a processing cluster 1814 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, such that new instructions may be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0282] In at least one embodiment, instructions sent to a processing cluster 1814 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, the thread groups execute a common program on different input data. In at least one embodiment, each thread in a thread group may be assigned to a different processing engine in the graphics multiprocessor 1834. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in the graphics multiprocessor 1834. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in the graphics multiprocessor 1834. In at least one embodiment, when a thread group includes more threads than the number of processing engines in the graphics multiprocessor 1834, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on the graphics multiprocessor 1834.

[0283] In at least one embodiment, the graphics multiprocessor 1834 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1834 can forgo internal cache and use cache memory (e.g., L1 cache 1848) within the processing cluster 1814. In at least one embodiment, each graphics multiprocessor 1834 also has access to an L2 cache within a partition unit (e.g., partition units 1820A-1820N in FIG. 18A ), which is shared among all processing clusters 1814 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1834 can also access off-chip global memory, which can include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing units 1802 can be used as global memory. In at least one embodiment, processing cluster 1814 may include multiple instances of graphics multiprocessor 1834 and share common instructions and data, which may be stored in L1 cache 1848.

[0284] In at least one embodiment, each processing cluster 1814 may include an MMU 1845 (memory management unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1845 may reside in memory interface 1818 of FIG. 18A . In at least one embodiment, MMU 1845 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses of tiles and optionally cache line indexes. In at least one embodiment, MMU 1845 may include an address translation lookaside buffer (TLB) or cache, which may reside in graphics multiprocessor 1834 or L1 1848 cache or processing cluster 1814. In at least one embodiment, physical addresses are processed to distribute surface data accesses locally and enable efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0285] In at least one embodiment, processing cluster 1814 may be configured such that each graphics multiprocessor 1834 is coupled to a texture unit 1836 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 1834 and fetched as needed from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1834 outputs processed tasks to data crossbar 1840 to provide the processed tasks to another processing cluster 1814 for further processing, or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 1816. In at least one embodiment, a pre-ROP 1842 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1834 and direct the data to the ROP unit, which may be co-located with a partition unit as described herein (e.g., partition units 1820A-1820N in FIG. 18A ). In at least one embodiment, the pre-ROP 1842 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0286] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with FIG. 5A and / or 5B. In at least one embodiment, inference and / or training logic 515 may be used in graphics processing cluster 1814 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0287] 18D illustrates a graphics multiprocessor 1834, according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 1834 couples with a pipeline manager 1832 of a processing cluster 1814. In at least one embodiment, the graphics multiprocessor 1834 has an execution pipeline that includes, but is not limited to, an instruction cache 1852, an instruction unit 1854, an address mapping unit 1856, a register file 1858, one or more general-purpose graphics processing unit (GPGPU) cores 1862, and one or more load / store units 1866. In at least one embodiment, the GPGPU cores 1862 and the load / store units 1866 are coupled to a cache memory 1872 and a shared memory 1870 via a memory and cache interconnect 1868.

[0288] In at least one embodiment, instruction cache 1852 receives a stream of instructions to execute from pipeline manager 1832. In at least one embodiment, instructions are cached in instruction cache 1852 and dispatched for execution by instruction unit 1854. In at least one embodiment, instruction unit 1854 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group assigned to a different execution unit within GPGPU core 1862. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying addresses in the unified address space. In at least one embodiment, address mapping unit 1856 can be used to translate addresses in the unified address space into individual memory addresses that can be accessed by load / store unit 1866.

[0289] In at least one embodiment, register file 1858 provides a set of registers to the functional units of graphics multiprocessor 1834. In at least one embodiment, register file 1858 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU core 1862, load / store unit 1866) of graphics multiprocessor 1834. In at least one embodiment, register file 1858 is partitioned among each of the functional units such that each functional unit is allocated a dedicated portion of register file 1858. In one embodiment, register file 1858 is partitioned among different warps being executed by graphics multiprocessor 1834.

[0290] In at least one embodiment, GPGPU cores 1862 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions for graphics multiprocessor 1834. In at least one embodiment, GPGPU cores 1862 may be of similar or different architectures. In at least one embodiment, a first portion of GPGPU core 1862 includes a single-precision FPU and an integer ALU, and a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement IEEE 754-2008 standard floating-point arithmetic or may enable variable-precision floating-point arithmetic. In at least one embodiment, graphics multiprocessor 1834 may additionally include one or more fixed-function or special-function units for performing specific functions, such as rectangle copy operations or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1862 may also include fixed or special function logic.

[0291] In at least one embodiment, GPGPU core 1862 includes SIMD logic capable of performing a single instruction on multiple data sets. In at least one embodiment, GPGPU core 1862 physically executes SIMD4, SIMD8, and SIMD16 instructions and logically executes SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core may be generated at compile time by a shader compiler or automatically when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logical unit.

[0292] In at least one embodiment, memory and cache interconnect 1868 is an interconnect network connecting each functional unit of graphics multiprocessor 1834 to register file 1858 and shared memory 1870. In at least one embodiment, memory and cache interconnect 1868 is a crossbar interconnect that allows load / store unit 1866 to implement load and store operations between shared memory 1870 and register file 1858. In at least one embodiment, register file 1858 can operate at the same frequency as GPGPU cores 1862, and therefore data transfers between GPGPU cores 1862 and register file 1858 can have very low latency. In at least one embodiment, shared memory 1870 can be used to enable communication between threads executing on functional units within graphics multiprocessor 1834. In at least one embodiment, cache memory 1872 can be used as a data cache, for example, to cache texture data communicated between the functional units and texture unit 1836. In at least one embodiment, shared memory 1870 can also be used as a program-managed cache. In at least one embodiment, threads executing on GPGPU cores 1862 can programmatically store data in the shared memory in addition to the automatically cached data stored in cache memory 1872.

[0293] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated into a package or chip as a core and communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. In at least one embodiment, regardless of the manner in which the GPU is connected, a processor core may allocate work to such GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0294] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B. In at least one embodiment, inference and / or training logic 515 may be used in graphics multiprocessor 1834 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0295] FIG. 19 illustrates a multi-GPU computing system 1900 according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 1900 may include a processor 1902 coupled to multiple general-purpose graphics processing units (GPGPUs) 1906A-D via a host interface switch 1904. In at least one embodiment, the host interface switch 1904 is a PCI Express switch device that couples the processor 1902 to a PCI Express bus via which the processor 1902 can communicate with the GPGPUs 1906A-D. In at least one embodiment, the GPGPUs 1906A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 1916. In at least one embodiment, the GPU-to-GPU links 1916 connect to each of the GPGPUs 1906A-D via a dedicated GPU link. In at least one embodiment, P2P GPU link 1916 enables direct communication between each of GPGPUs 1906A-D without requiring communication via host interface bus 1904 to which processor 1902 is connected. In at least one embodiment, when there is GPU-to-GPU traffic directed to P2P GPU link 1916, host interface bus 1904 remains available for system memory access or to communicate with other instances of multi-GPU computing system 1900, for example, via one or more network devices. In at least one embodiment, GPGPUs 1906A-D connect to processor 1902 via host interface switch 1904, and in at least one embodiment, processor 1902 includes direct support for P2P GPU link 1916 and can connect directly to GPGPUs 1906A-D.

[0296] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B. In at least one embodiment, the inference and / or training logic 515 may be used in the multi-GPU computing system 1900 for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0297] 20 is a block diagram of a graphics processor 2000 according to at least one embodiment. In at least one embodiment, the graphics processor 2000 includes a ring interconnect 2002, a pipeline front end 2004, a media engine 2037, and graphics cores 2080A-2080N. In at least one embodiment, the ring interconnect 2002 couples the graphics processor 2000 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2000 is one of many processors incorporated within a multi-core processing system.

[0298] In at least one embodiment, graphics processor 2000 receives batches of commands via ring interconnect 2002. In at least one embodiment, the incoming commands are interpreted by command streamer 2003 in pipeline front end 2004. In at least one embodiment, graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via graphics core(s) 2080A-2080N. In at least one embodiment, for 3D geometry processing commands, command streamer 2003 supplies the commands to geometry pipeline 2036. In at least one embodiment, for at least some media processing commands, command streamer 2003 supplies the commands to video front end 2034, which couples to media engine 2037. In at least one embodiment, the media engine 2037 includes a Video Quality Engine (VQE) 2030 for video and image post-processing and a multi-format encode / decode (MFX) 2033 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2036 and the media engine 2037 each spawn execution threads for thread execution resources provided by at least one graphics core 2080.

[0299] In at least one embodiment, graphics processor 2000 includes scalable thread execution resources characterized by graphics cores 2080A-2080N (which may be modular and sometimes referred to as core slices), each having multiple sub-cores 2050A-2050N, 2060A-2060N (which may also be referred to as core sub-slices). In at least one embodiment, graphics processor 2000 can have any number of graphics cores 2080A. In at least one embodiment, graphics processor 2000 includes graphics core 2080A having at least a first sub-core 2050A and a second sub-core 2060A. In at least one embodiment, graphics processor 2000 is a low-power processor with a single sub-core (e.g., 2050A). In at least one embodiment, graphics processor 2000 includes multiple graphics cores 2080A-2080N, each including a first set of sub-cores 2050A-2050N and a second set of sub-cores 2060A-2060N. In at least one embodiment, each sub-core in first sub-cores 2050A-2050N includes at least a first set of execution units 2052A-2052N and media / texture samplers 2054A-2054N. In at least one embodiment, each sub-core in second sub-cores 2060A-2060N includes at least a second set of execution units 2062A-2062N and samplers 2064A-2064N. In at least one embodiment, each sub-core 2050A-2050N, 2060A-2060N shares a set of shared resources 2070A-2070N. In at least one embodiment, the shared resources include shared cache memory and pixel operating logic.

[0300] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 515 are provided herein in conjunction with FIGURES 5A and / or 5B. In at least one embodiment, inference and / or training logic 515 may be used in graphics processor 2000 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0301] FIG. 21 is a block diagram illustrating a microarchitecture for a processor 2100 that may include logic circuits for implementing instructions, according to at least one embodiment. In at least one embodiment, the processor 2100 may implement instructions including x86 instructions, AMR instructions, special instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2100 may include registers for storing packed data, such as 64-bit wide MMX™ registers in an MMX technology-enabled microprocessor from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point formats, may operate on packed data elements with Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extension (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, the processor 2100 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0302] In at least one embodiment, processor 2100 includes an in-order front end (“front end”) 2101 for fetching instructions to be executed and preparing instructions to be used later in the processor pipeline. In at least one embodiment, front end 2101 may include several units. In at least one embodiment, an instruction prefetcher 2126 fetches instructions from memory and feeds the instructions to an instruction decoder 2128, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2128 decodes received instructions into one or more operations, called “microinstructions” or “micro-operations” (also called “micro-ops” or “uops”), that the machine can execute. In at least one embodiment, instruction decoder 2128 parses instructions into opcodes and corresponding data and control fields that can be used by the microarchitecture to perform operations in accordance with at least one embodiment. In at least one embodiment, trace cache 2130 may assemble decoded uops into program-order sequences, or traces, for execution in uop queue 2134. In at least one embodiment, when trace cache 2130 encounters a complex instruction, microcode ROM 2132 provides the uops necessary to complete the operation.

[0303] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2128 may access the microcode ROM 2132 to implement the instruction. In at least one embodiment, an instruction may be decoded into a fewer number of micro-ops for processing in the instruction decoder 2128. In at least one embodiment, an instruction may be stored in the microcode ROM 2132 if several micro-ops are required to accomplish such an operation. In at least one embodiment, the trace cache 2130 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 2132 in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 2132 finishes sequencing micro-ops for an instruction, the machine front end 2101 may resume fetching micro-ops from the trace cache 2130.

[0304] In at least one embodiment, an out-of-order execution engine (“out-of-order engine”) 2103 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has several buffers to smooth the flow of instructions and reorder them to optimize performance as they move down the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2103 includes, but is not limited to, an allocator / register renamer 2140, a memory uop queue 2142, an integer / floating point uop queue 2144, a memory scheduler 2146, a fast scheduler 2102, a slow / general purpose floating point scheduler (“slow / general purpose FP scheduler”) 2104, and a simple floating point scheduler (“simple FP scheduler”) 2106. In at least one embodiment, the fast scheduler 2102, the slow / general purpose floating point scheduler 2104, and the simple floating point scheduler 2106 are also collectively referred to herein as "uop schedulers 2102, 2104, 2106." In at least one embodiment, the allocator / register renamer 2140 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, the allocator / register renamer 2140 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 2140 also allocates an entry for each uop in one of two uop queues: memory uop queue 2142 for memory operations and integer / floating point uop queue 2144 for non-memory operations, before memory scheduler 2146 and uop schedulers 2102, 2104, 2106. In at least one embodiment, uop schedulers 2102, 2104, 2106 determine when uops are ready to execute based on the readiness of their dependent input register operand sources and the availability of execution resources required by the uops to complete their operations.In at least one embodiment, the fast scheduler 2102 may schedule every half of a main clock cycle, and the slow / general purpose floating point scheduler 2104 and simple floating point scheduler 2106 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2102, 2104, 2106 arbitrate for dispatch ports to schedule uops for execution.

[0305] In at least one embodiment, execution block 2111 includes, but is not limited to, integer register file / bypass network 2108, floating point register file / bypass network (“FP register file / bypass network”) 2110, address generation units (“AGUs”) 2112 and 2114, fast arithmetic logic units (ALUs) (“fast ALUs”) 2116 and 2118, slower arithmetic logic unit (“slower ALU”) 2120, floating point ALU (“FP”) 2122, and floating point move unit (“FP move”) 2124. In at least one embodiment, integer register file / bypass network 2108 and floating point register file / bypass network 2110 are also referred to herein as “register files 2108, 2110.” In at least one embodiment, AGUs 2112 and 2114, fast ALUs 2116 and 2118, slow ALU 2120, floating-point ALU 2122, and floating-point move unit 2124 are also referred to herein as "execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124." In at least one embodiment, execution block 2111 may include any number and type of register files, bypass networks, address generation units, and execution units (including, but not limited to, zero), in any combination.

[0306] In at least one embodiment, the register networks 2108, 2110 may be disposed between the uop schedulers 2102, 2104, 2106 and the execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124. In at least one embodiment, the integer register file / bypass network 2108 performs integer operations. In at least one embodiment, the floating point register file / bypass network 2110 performs floating point operations. In at least one embodiment, each of the register networks 2108, 2110 may include, but is not limited to, a bypass network that may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, the register networks 2108, 2110 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2108 may include, but is not limited to, two separate register files: one register file for lower 32-bit data and a second register file for higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64 to 128 bits wide, so floating-point register file / bypass network 2110 may include, but is not limited to, 128-bit wide entries.

[0307] In at least one embodiment, execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124 may execute instructions. In at least one embodiment, register networks 2108 and 2110 store integer and floating-point data operand values ​​required by microinstructions to execute. In at least one embodiment, processor 2100 may include, without limitation, any number and combination of execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124. In at least one embodiment, floating-point ALU 2122 and floating-point move unit 2124 may execute floating-point, MMX, SIMD, AVX, and SEE, or other operations, including special machine learning instructions. In at least one embodiment, the floating-point ALU 2122 may include a 64-bit floating-point divider for performing, but not limited to, division, square root, and remainder micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the high-speed ALUs 2116, 2118. In at least one embodiment, the high-speed ALUs 2116, 2118 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the low-speed ALU 2120 may include integer execution hardware for long-latency type operations such as, but not limited to, multipliers, shifts, flag logic, and branching, so that most complex integer operations proceed to the low-speed ALU 2120. In at least one embodiment, memory load / store operations may be performed by the AGUs 2112, 2114. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc.In at least one embodiment, floating-point ALU 2122 and floating-point move unit 2124 may be implemented to support a variety of operands having various bit widths, such as 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0308] In at least one embodiment, the uop schedulers 2102, 2104, 2106 dispatch dependent operations before the parent load finishes executing. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 2100, the processor 2100 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline that have passed the scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0309] In at least one embodiment, a "register" may refer to an on-board processor storage location that may be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform functions described herein. In at least one embodiment, the registers described herein may be implemented by circuit elements within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0310] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B . In at least one embodiment, portions or all of the inference and / or training logic 515 may be incorporated into the execution block 2111 and other memory or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs shown in the execution block 2111. Moreover, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that comprise the ALUs of the execution block 2111 for implementing one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0311] 22 illustrates a deep learning application processor 2200, according to at least one embodiment. In at least one embodiment, the deep learning application processor 2200 uses instructions that, when executed by the deep learning application processor 2200, cause the deep learning application processor 2200 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2200 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 2200 performs a matrix multiplication operation, both "hard-wired" in hardware, as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2200 includes, but is not limited to, processing clusters 2210(1)-2210(12), inter-chip links ("ICL") 2220(1)-2220(12), inter-chip controllers ("ICC") 2230(1)-2230(2), high-bandwidth memory second generation ("HBM2") 2240(1)-2240(4), memory controllers ("Mem Ctrlr") 2242(1)-2242(4), and high-bandwidth memory physical layer ("HBM PHY") 2240(1)-2240(4). layer) 2244(1) to 2244(4), a management-controller central processing unit ("management-controller CPU") 2250, and serial peripheral interfaces, inter-integrated circuit, and general-purpose input / output ("SPI, I 2C, GPIO": Serial Peripheral Interface, Inter-Integrated Circuit, and General Purpose Input / Output) block 2260, Peripheral Component Interconnect Express Controller and Direct Memory Access ("PCIe Controller and DMA") block 2270, and 16-lane Peripheral Component Interconnect Express Port ("PCI Express x16") 2280.

[0312] In at least one embodiment, the processing clusters 2210 may perform deep learning operations, including inference or prediction operations, based on weight parameters calculated using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2210 may include any number and types of processors, without limitation. In at least one embodiment, the deep learning application processor 2200 may include any number and types of processing clusters 2200. In at least one embodiment, the inter-chip link 2220 is bidirectional. In at least one embodiment, the inter-chip link 2220 and the inter-chip controller 2230 enable multiple deep learning application processors 2200 to exchange information, including activation information resulting from implementing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2200 may include any number and types (including zero) of ICLs 2220 and ICCs 2230.

[0313] In at least one embodiment, the HBM2 2240 provides a total of 32 Gigabytes (GB) of memory. In at least one embodiment, an HBM2 2240(i) is associated with both a memory controller 2242(i) and an HBM PHY 2244(i), where "i" is any integer. In at least one embodiment, any number of HBM2s 2240 may provide any type and total amount of high-bandwidth memory and may be associated with any number and type of memory controllers 2242 and HBM PHYs 2244 (including zero). In at least one embodiment, SPI, I 2 C, GPIO 2260, PCIe controller and DMA 2270, and / or PCIe 2280 may be replaced with any number and types of blocks that enable any number and types of communication standards in any technically feasible manner.

[0314] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 515 are provided herein in conjunction with FIG. 5A and / or FIG. 5B. In at least one embodiment, the deep learning application processor 2200 is used to train a machine learning model, such as a neural network, to predict or infer information provided to the deep learning application processor 2200. In at least one embodiment, the deep learning application processor 2200 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) trained by another processor or system or by the deep learning application processor 2200. In at least one embodiment, the processor 2200 may be used to implement one or more neural network use cases described herein.

[0315] FIG. 23 is a block diagram of a neuromorphic processor 2300, according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2300 may receive one or more inputs from sources external to the neuromorphic processor 2300. In at least one embodiment, these inputs may be sent to one or more neurons 2302 within the neuromorphic processor 2300. In at least one embodiment, the neurons 2302 and their components may be implemented using circuit elements or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2300 may include, without limitation, thousands or millions of instances of neurons 2302, although any suitable number of neurons 2302 may be used. In at least one embodiment, each instance of a neuron 2302 may include a neuron input 2304 and a neuron output 2306. In at least one embodiment, neuron 2302 may generate an output, which may be sent to an input of another instance of neuron 2302. For example, in at least one embodiment, neuron input 2304 and neuron output 2306 may be interconnected via synapse 2308.

[0316] In at least one embodiment, neurons 2302 and synapses 2308 may be interconnected such that neuromorphic processor 2300 operates to process or analyze information received by neuromorphic processor 2300. In at least one embodiment, neuron 2302 may send an output pulse (or "fire" or "spike") when an input received through neuron input 2304 exceeds a threshold. In at least one embodiment, neuron 2302 may sum or integrate signals received at neuron input 2304. For example, in at least one embodiment, neuron 2302 may be implemented as a leaky integrate-and-fire neuron, and when the sum (called the "membrane potential") exceeds a threshold, neuron 2302 may generate an output (or "fire") using a transfer function such as a sigmoid function or a threshold function. In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron input 2304 into a membrane potential and may apply a damping factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron input 2304 quickly enough to exceed a threshold (i.e., before the membrane potential decay becomes too low to fire). In at least one embodiment, neuron 2302 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and damps the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Additionally, in at least one embodiment, neuron 2302 may include, but is not limited to, a comparator circuit or logic that generates an output spike at neuron output 2306 when the result of applying the transfer function to neuron input 2304 exceeds a threshold. In at least one embodiment, when a neuron 2302 fires, it may ignore previously received input information, for example, by resetting the membrane potential to 0 or another suitable default value.In at least one embodiment, once the membrane potential is reset to zero, neuron 2302 may resume normal operation after a suitable period of time (or refractory period).

[0317] In at least one embodiment, neurons 2302 may be interconnected through synapses 2308. In at least one embodiment, synapses 2308 may operate to transmit a signal from an output of a first neuron 2302 to an input of a second neuron 2302. In at least one embodiment, neurons 2302 may transmit information through two or more instances of synapses 2308. In at least one embodiment, one or more instances of neuron outputs 2306 may be connected to instances of neuron inputs 2304 in the same neuron 2302 through instances of synapses 2308. In at least one embodiment, an instance of neuron 2302 that generates an output to be transmitted through an instance of synapse 2308 may be referred to as a “pre-synaptic neuron” with respect to that instance of synapse 2308. In at least one embodiment, an instance of neuron 2302 that receives an input transmitted through an instance of synapse 2308 may be referred to as a “post-synaptic neuron” with respect to that instance of synapse 2308. In at least one embodiment, an instance of neuron 2302 may receive input from one or more instances of synapse 2308 and may send output through one or more instances of synapse 2308, so that a single instance of neuron 2302 may therefore be both a “pre-synaptic neuron” and a “post-synaptic neuron” with respect to various instances of synapse 2308.

[0318] In at least one embodiment, neurons 2302 may be organized into one or more layers. In at least one embodiment, each instance of neuron 2302 may have one neuron output 2306 that may fan out to one or more neuron inputs 2304 through one or more synapses 2308. In at least one embodiment, neuron output 2306 of neuron 2302 in a first layer 2310 may be connected to neuron input 2304 of neuron 2302 in a second layer 2312. In at least one embodiment, layer 2310 may be referred to as a "feed-forward layer." In at least one embodiment, each instance of neuron 2302 in an instance of first layer 2310 may fan out to each instance of neuron 2302 in the second layer 2312. In at least one embodiment, first layer 2310 may be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of neuron 2302 in an instance of second layer 2312 may fan out to fewer than all instances of neuron 2302 in third layer 2314. In at least one embodiment, second layer 2312 may be referred to as a "sparsely connected feed-forward layer." In at least one embodiment, neurons 2302 in second layer 2312 may fan out to neurons 2302 in multiple other layers, including neurons 2302 also in second layer 2312. In at least one embodiment, second layer 2312 may be referred to as a "recurrent layer." In at least one embodiment, neuromorphic processor 2300 may include any suitable combination of recurrent and feed-forward layers, including, but not limited to, both sparsely connected and fully connected feed-forward layers.

[0319] In at least one embodiment, neuromorphic processor 2300 may include, without limitation, a reconfigurable interconnect architecture or dedicated hardwired interconnects for connecting synapses 2308 to neurons 2302. In at least one embodiment, neuromorphic processor 2300 may include circuit elements or logic that allow synapses to be allocated to different neurons 2302 as needed based on neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2308 may be connected to neurons 2302 using an interconnect fabric, such as a network-on-chip, or using dedicated connections. In at least one embodiment, synaptic interconnects and their components may be implemented using circuit elements or logic.

[0320] 24 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 2400 includes one or more processors 2402 and one or more graphics processors 2408 and may be a single-processor desktop system, a multiprocessor workstation system, or a server system having multiple processors 2402 or processor cores 2407. In at least one embodiment, system 2400 is a processing platform integrated into a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0321] In at least one embodiment, system 2400 may include or be incorporated within a server-based gaming platform, a game console including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system 2400 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, processing system 2400 may also include, be coupled to, or be incorporated within a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 2400 is a television or set-top box device having one or more processors 2402 and a graphical interface generated by one or more graphics processors 2408.

[0322] In at least one embodiment, the one or more processors 2402 each include one or more processor cores 2407 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2407 is configured to process a particular instruction sequence 2409. In at least one embodiment, the instruction sequence 2409 may facilitate computing via Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or Very Long Instruction Word (VLIW). In at least one embodiment, the processor cores 2407 may each process a different instruction sequence 2409, and the instruction sequence 2409 may include instructions to facilitate emulation of other instruction sequences. In at least one embodiment, the processor cores 2407 may also include other processing devices, such as a digital signal processor (DSP).

[0323] In at least one embodiment, processor 2402 includes cache memory 2404. In at least one embodiment, processor 2402 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 2402. In at least one embodiment, processor 2402 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among processor cores 2407 using known cache coherency techniques. In at least one embodiment, processor 2402 additionally includes a register file 2406, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2406 may include general-purpose registers or other registers.

[0324] In at least one embodiment, the one or more processors 2402 are coupled to one or more interface buses 2410 for transmitting communication signals, such as address, data, or control signals, between the processors 2402 and other components in the system 2400. In at least one embodiment, the interface bus 2410 may be a processor bus such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 2410 is not limited to a DMI bus, but may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor(s) 2402 includes an integrated memory controller 2416 and a platform controller hub 2430. In at least one embodiment, memory controller 2416 facilitates communication between memory devices and other components of system 2400, and platform controller hub (PCH) 2430 provides connectivity to I / O devices via a local I / O bus.

[0325] In at least one embodiment, memory device 2420 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device with performance suitable for serving as process memory. In at least one embodiment, me...

Claims

1. one or more processors; A memory for storing instructions wherein the instructions, when executed by the one or more processors, result in the system: assigning a set of clients to a first hardware accelerator, wherein a first client of the set of clients provides a batch of frames for processing; generating a first determination indicating that a first metric associated with processing the batch of frames using the first hardware accelerator has exceeded a threshold; in response to the first determination, assigning a subset of clients of the set of clients to a second hardware accelerator; Let them do this, The memory, when executed by the one or more processors, provides the system with: generating a second determination indicating that the first metric associated with the first hardware accelerator has fallen below the threshold; and in response to the second determination, assigning the subset of clients of the set of clients to the first hardware accelerator; The system further stores instructions to cause the system to:

2. The system of claim 1 , wherein the first hardware accelerator further comprises a video image compositor (VIC).

3. The system of claim 1 , wherein the second hardware accelerator further comprises a graphics processing unit (GPU).

4. 2. The system of claim 1, wherein the first metric further comprises an amount of time the first client utilizes the first hardware accelerator to perform processing of the batch of frames.

5. The system of claim 1 , wherein the first metric further comprises an average amount of load generated by at least processing the batch of frames provided by the first client.

6. The system of claim 1 , wherein the first determination is generated during a time interval.

7. The system of claim 1 , wherein the first determination is made based at least in part on historical data.

8. 2. The system of claim 1, wherein the instructions that cause the system to assign the subset of clients of the set of clients to the second hardware accelerator, when executed by the one or more processors, further comprise instructions that cause the system to assign the subset of clients of the set of clients to the second hardware accelerator based at least in part on preferences provided by a user.

9. The system of claim 1 , wherein the threshold is specified by a user.

10. 2. The system of claim 1, wherein a user indicates a preference between the first hardware accelerator and the second hardware accelerator for processing on behalf of at least one client of the set of clients.

11. 10. The system of claim 1, wherein the first hardware accelerator further comprises a field-programmable gate array (FPGA).

12. 2. The system of claim 1, wherein the memory further stores instructions that, when executed by the one or more processors, cause the system to obtain the first metric through a system call.

13. The system of claim 1 , wherein the set of clients further comprises a set of components of an artificial intelligence pipeline.

14. 14. The system of claim 13, wherein the artificial intelligence pipeline includes one or more neural networks.

15. 2. The system of claim 1, wherein the memory further stores instructions that, when executed by the one or more processors, cause the system to cause the first hardware accelerator to process the batch of frames by at least converting the batch of frames from a first format to a second format.

16. 2. The system of claim 1, wherein the memory further stores instructions that, when executed by the one or more processors, cause the system to cause the first hardware accelerator to process the batch of frames by at least scaling the batch of frames.

17. 2. The system of claim 1, wherein the memory further stores instructions that, when executed by the one or more processors, cause the system to cause the first hardware accelerator to process the batch of frames by at least modifying one or more color values ​​associated with at least one frame of the batch of frames.

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