Cache data reading method and device

Abstract

To enable multiple pieces of data to be read in a one-piece complete data read process, and reduce read and write time overhead during execution of a large number of cached data read tasks.SOLUTION: A method for reading cached data includes: in response to receiving to-be-cached data, segmenting the to-be-cached data sequentially into at least two pieces of first fragmented data; writing the first fragmented data sequentially into first storage particles of at least two storage blocks in a time division multiplexing manner, and ensuring that the first fragmented data written into the respective first storage particles are different from each other; and saving a correspondence between first identifiers of the to-be-cached data and addresses of the first storage particles to a resource management table. The fragmented data are read in the time division multiplexing manner, and the fragmented data corresponding to one piece of complete data are stored in different storage blocks.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] (cross reference) This disclosure claims priority to Chinese patent application number 202310193368.3, filed on February 28, 2023, entitled "Cache Data Reading Method, Apparatus, Device and Medium," the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to the field of data processing, and more particularly to a method, apparatus and device for reading cache data. [Background technology]

[0003] Currently, computing devices generally employ multithreaded processors to improve data processing capabilities by using multithreaded processors to execute computing tasks in parallel, thereby realizing the data input and output of large data traffic. However, the memories employed by current multithreaded processors still employ a traditional data cache architecture, i.e., data is read and written in a frame-by-frame manner and allocated based on a single cache space. When cache data is read and written under this data cache architecture, if multiple threads execute cache data read and write tasks in parallel, the read and write tasks corresponding to a thread must be queued, which increases the overhead of data read and write times and reduces the effective utilization rate of the processor. Summary of the Invention [Problem to be solved by the invention]

[0004] To solve the above technical problems, the embodiments of the present disclosure provide a cache data reading method, device, apparatus, and medium. [Means for solving the problem]

[0005] According to a first aspect, an embodiment of the present disclosure provides a cache data reading method applied to a computing device, the computing device including a buffer storage area including at least two storage blocks, each of the storage blocks having an independent address bus and a data bus, and each of the storage blocks having a plurality of storage particles, the method including: In response to the received data to be cached, sequentially dividing the data to be cached into at least two first fragmented data pieces; sequentially writing the first fragmented data to first memory particles of at least two of the storage blocks in a time division multiplexed manner, and making the first fragmented data written to each of the first memory particles different; and storing a correspondence between the first indicator of the data waiting to be cached and the first storage particle address in a resource management table.

[0006] Optionally, the number of data waiting to be cached is a plurality of sets, and the number of sets of data waiting to be cached is equal to or less than the number of storage blocks; the step of sequentially dividing the data to be cached into at least two first fragmented data includes sequentially dividing each set of the data to be cached into at least two first fragmented data; The aforementioned sequentially writing the first fragmented data to the first memory particles of the at least two memory blocks in a time division multiplexing manner includes: The first fragmented data corresponding to each set of cache-waiting data is simultaneously written to first memory particles of the at least two memory blocks in the time-division multiplexing manner, wherein the memory blocks corresponding to each first fragmented data written at the same time are different from each other.

[0007] Optionally, the first fragmented data corresponding to each set of cache-waiting data is written to first memory particles of the at least two memory blocks simultaneously in a time-division multiplexed round-robin manner until all of the first fragmented data are written to the buffer memory area.

[0008] Optionally, the storage capacity of the storage particles in each of the storage blocks is the same; Sequentially dividing the data to be cached into at least two first fragmented data includes sequentially dividing the data to be cached into at least two first fragmented data according to a storage capacity of the storage particles.

[0009] Optionally, the method includes: in response to the acquired buffer data read command, extracting a second indicator in the buffer data read command, the second indicator being an indicator of data waiting to be output, wherein the sum of the number of sets of data waiting to be output and the number of sets of data waiting to be buffered is less than or equal to the number of storage blocks; querying a resource management table based on the second indicator to sequentially obtain addresses of at least two second memory particles distributed in at least two memory blocks, which are associated with the data waiting to be output; While sequentially writing the first fragmented data to first storage particles of at least two of the storage blocks in a time division multiplexed manner, the method includes: In a time division multiplexing manner, read out the second fragmented data from at least two memory blocks according to the address of the second memory particle, wherein the memory blocks corresponding to the first fragmented data written at the same time are different from the memory blocks corresponding to the second fragmented data being read out; The method further includes splicing the read second fragmented data until the data waiting to be output is obtained.

[0010] According to a second aspect, an embodiment of the present disclosure provides a cache data reading method applied to a computing device, the computing device including a buffer storage area including at least two storage blocks, each of the storage blocks having a plurality of storage particles and each of the storage blocks having an independent system bus, the method including: In response to the acquired buffer data read command, extracting a second indicator in the buffer data read command, the second indicator being an indicator of data waiting to be output; querying a resource management table based on the second indicator to sequentially obtain addresses of at least two second memory particles distributed in at least two memory blocks associated with the data waiting to be output; reading second fragmented data from the storage particles of at least two storage blocks according to the addresses of the second storage particles in a time division multiplexed manner; splicing the second fragmented data until obtaining the data awaiting output.

[0011] Optionally, the number of the data buffer read commands is at least two, and the number of the buffer data read commands is equal to or less than the number of the storage blocks; extracting the second indicator in the buffer data read command includes extracting the second indicator for each of the buffer data read commands; The above-mentioned reading of the second fragmented data from the memory particles of at least two memory blocks according to the addresses of the second memory particles in a time division multiplexing manner includes: The address of the second memory particle is simultaneously read from the memory address of at least two memory blocks according to the address of the second memory particle in the time division multiplexing manner, and the memory blocks corresponding to each of the second fragmented data read at the same time are different; The splicing of the second fragmented data until the data waiting to be output is obtained includes: splicing the second fragmented data corresponding to each of the second indicators respectively until all of the data waiting to be output is obtained.

[0012] According to a third aspect, an embodiment of the present disclosure provides a cache data reading device applied to a computing device, the computing device including a buffer storage area including at least two storage blocks, each of the storage blocks having an independent address bus and a data bus, and each of the storage blocks having a plurality of storage particles, the device comprising: a data splitting unit responsive to received cacheable data for sequentially splitting the cacheable data into at least two first fragmented data; a data writing unit for sequentially writing the first fragmented data to first memory particles of at least two of the storage blocks in a time division multiplex manner, and making the first fragmented data written to each of the first memory particles different; a correspondence storing unit for storing a correspondence between the first indicator of the data waiting to be cached and the first storage particle address in a resource management table;

[0013] Optionally, the number of data waiting to be cached is a plurality of sets, and the number of sets of data waiting to be cached is equal to or less than the number of storage blocks; The data writing unit simultaneously writes the first fragmented data corresponding to each set of cache-waiting data to the first memory particles of the at least two memory blocks in the time-division multiplexing manner, where the memory blocks corresponding to each first fragmented data written at the same time are different from each other.

[0014] Optionally, the data writing unit writes the first fragmented data corresponding to each set of cache-waiting data to the first memory particles of the at least two memory blocks simultaneously in a time-division multiplexed manner in a round-robin manner until all of the first fragmented data are written to the buffer memory area.

[0015] Optionally, the storage capacity of the storage particles in each of the storage blocks is the same; The data dividing unit sequentially divides the data to be cached into at least two of the first fragmented data according to the storage capacity of the storage particles.

[0016] Optionally, the device includes: an indicator extraction unit, responsive to the acquired buffer data read command, for extracting a second indicator in the buffer data read command, the second indicator being an indicator of data waiting to be output, wherein the sum of the number of sets of data waiting to be output and the number of sets of data waiting to be buffered is less than or equal to the number of storage blocks; a relation query unit for querying a resource management table based on the second indicator to sequentially obtain addresses of at least two second storage particles distributed in at least two storage blocks, which are associated with the data waiting to be output; a data read unit for the data write unit to sequentially write the first fragmented data to first memory particles of at least two of the storage blocks in a time division multiplexing manner, and simultaneously read second fragmented data from at least two storage blocks according to addresses of the second memory particles in a time division multiplexing manner, wherein the storage blocks corresponding to the first fragmented data written at the same time and the storage blocks corresponding to the second fragmented data being read are different; and a data splicing unit for splicing the read second fragmented data until the data waiting to be output is obtained.

[0017] According to a fourth aspect, an embodiment of the present disclosure provides a cache data reading device applied to a computing device, the computing device including a buffer storage area including at least two storage blocks, each of the storage blocks having a plurality of storage particles and each having an independent system bus, the device including: an indicator extraction unit for extracting a second indicator in the buffer data read command, the second indicator being an indicator of data waiting to be output, in response to the acquired buffer data read command; a relation query unit for querying a resource management table based on the second indicator to sequentially obtain addresses of at least two second storage particles distributed in at least two storage blocks, which are associated with the data waiting to be output; a data reading unit for reading second fragmented data from the storage particles of at least two storage blocks according to the addresses of the second storage particles in a time division multiplex manner; a data splicing unit for splicing the second fragmented data until obtaining the data waiting to be output.

[0018] Optionally, the number of the data buffer read commands is at least two, and the number of the buffer data read commands is equal to or less than the number of the storage blocks; the data reading unit simultaneously reads the addresses of the second memory particles from the storage addresses of at least two storage blocks according to the addresses of the second memory particles in the time division multiplexing manner, and the storage blocks corresponding to the second fragmented data being read at the same time are different; The data splicing unit splices the second fragmented data corresponding to each of the second markers respectively until all of the data waiting to be output is obtained.

[0019] According to a fifth aspect, an embodiment of the present disclosure provides a computing device including a processor, a volatile memory, and a non-volatile memory, wherein the volatile memory includes at least two memory blocks, each of which has an independent system bus and each of which has a plurality of memory particles, and the non-volatile memory is used to store a computer program, and when the computer program is loaded by the processor, causes the processor to perform the cache data reading method as described above.

[0020] According to a sixth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having stored thereon a computer program that, when executed by a processor, causes the processor to implement the cache data reading method as described above. [Effects of the Invention]

[0021] Compared with the prior art, the technical solution according to the embodiments of the present disclosure has the following advantages: By adopting the solution according to the embodiment of the present disclosure, the computing device writes first fragmented data of data to be cached to memory particles of at least two storage blocks in a time division multiplexing manner, or reads second fragmented data from the memory particles of at least two storage blocks, and uses the read second fragmented data to assemble data to be output. Because the fragmented data is read using time division multiplexing and the fragmented data corresponding to one complete data are stored in different storage blocks, multiple data can be read in the process of reading one complete data, and the read / write time overhead during the execution of a large amount of cache data reading task can be further reduced. [Brief explanation of the drawings]

[0022] The accompanying drawings herein, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0023] In order to more clearly describe the technical solutions in the embodiments or existing technologies of the present disclosure, the following briefly describes the accompanying drawings that need to be used in describing the embodiments or existing technologies. It is obvious that those skilled in the art can obtain other accompanying drawings based on these accompanying drawings without any creative efforts.

[0024] [Figure 1] FIG. 2 is a schematic diagram of a cache storage area architecture according to an embodiment of the present disclosure. [Figure 2] 1 is a flowchart of a cache data reading method according to an embodiment of the present disclosure. [Figure 3] 3A and 3B are schematic diagrams illustrating the process of storing cache data in some embodiments of the present disclosure. [Figure 4] FIG. 4 is a distribution schematic diagram of the first fragmented data acquired based on the storage process of FIG. 3; [Figure 5] 10 is a flowchart of another cache data reading method according to an embodiment of the present disclosure. [Figure 6] 10A to 10C are schematic diagrams illustrating the process of storing cache data in some other cases according to an embodiment of the present disclosure. [Figure 7] FIG. 6 is a distribution schematic diagram of the first fragmented data acquired based on the storage process of FIG. 5; [Figure 8] 10 is a flowchart of a method for reading data according to still other embodiments of the present disclosure. [Figure 9] 3A and 3B are schematic diagrams illustrating the process of reading cached data in some embodiments of the present disclosure. [Figure 10] 10A and 10B are schematic diagrams illustrating the process of reading cached data in some cases according to an embodiment of the present disclosure. [Figure 11] 10 is a flowchart of a method for reading data according to still other embodiments of the present disclosure. [Figure 12] FIG. 2 is a schematic diagram of a buffer data reading process according to some embodiments of the present disclosure. [Figure 13]1 is a flowchart of a method for determining a target audio frame in some embodiments of the present disclosure. [Figure 14] 1 is a structural schematic diagram of an audio playback control device according to some embodiments of the present disclosure. [Figure 15] FIG. 2 is a structural schematic diagram of a terminal device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0025]

[0023] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Although the drawings show several embodiments of the present disclosure, it should be understood that the present disclosure can be realized in various forms and should not be construed as being limited to the embodiments described herein, but rather provided for a more transparent and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are used only for illustrative purposes and are not used to limit the scope of protection of the present disclosure.

[0026] As used herein, the term "comprises" and variations thereof are openly inclusive, i.e., "including, but not limited to." The term "based on" means "based at least in part on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one other embodiment," and the term "some embodiments" means "at least some embodiments." Relevant definitions of other terms are provided below. Note that concepts such as "first," "second," and the like, referred to in this disclosure, are used only to distinguish different devices, modules, or units, and do not limit the order or interdependence of functions performed by these devices, modules, or units.

[0027] It should be noted that the modifications "a" and "a plurality" referred to in this disclosure are intended to be general rather than limiting and should be understood as "one or more" unless the context clearly indicates otherwise.

[0028] An embodiment of the present disclosure provides a buffer data reading method that is applied to a computing device, realizes parallel reading and writing of buffer data by changing a cache data reading policy, and then improves the cache data reading and writing speed of the computing device.

[0029] Since the buffer data reading method according to the embodiment of the present disclosure needs to be performed in a buffer storage area of ​​a specific architecture, the architecture of the specific buffer storage area will be analyzed first before describing the buffer data reading method.

[0030] The buffer storage area according to the embodiment of the present disclosure has at least two storage blocks, which can realize independent control of data reading, that is, the storage blocks have independent address buses and data buses. During the process of reading cache data, each storage block can realize parallel cache data reading through the corresponding address bus and data bus at one time.

[0031] 1 is a schematic diagram of the architecture of a cache storage area according to an embodiment of the present disclosure. As shown in FIG. 1, in one specific embodiment, the cache storage area includes four storage blocks (the four storage blocks are numbered 0, 1, 2, and 3, respectively). Each of the four storage blocks has an independent address bus and data bus, enabling four-way cache data parallel reading. Of course, in other embodiments, the number of storage blocks included in the cache storage area is not limited to four and may be other numbers, but the number of storage blocks is at least two.

[0032] Each of the memory blocks has a plurality of memory particles. For example, each of the memory blocks shown in FIG. 1 includes 1024 memory particles. A memory particle is a data storage unit with a predetermined capacity, and is essentially formed by a combination of a plurality of consecutive bits in the memory block. For example, in one application, the storage capacity of one memory particle may be 1024 bits. Of course, the storage capacity of a memory particle is not limited to 1024 bits and may be other capacities.

[0033] The buffer storage area may be a storage area located in random access memory (RAM) or a storage area located in cache memory (Cache), and the embodiments of the present disclosure are not limited thereto.

[0034] 2 is a flowchart of a cache data reading method according to an embodiment of the present disclosure. As shown in FIG. 2, the cache data reading method according to an embodiment of the present disclosure includes steps S110 to S130. The method shown in FIG. 2 is performed by a computing device that allocates the buffer storage area.

[0035] S110: In response to the received data to be cached, sequentially divide the data to be cached into at least two first fragmented data.

[0036] In an embodiment of the present disclosure, after a computing device is powered on, the computing device completes device initialization and opens a preset number of storage blocks in the corresponding physical memory (i.e., the RAM or Cache) to prepare storage cache data.

[0037] The data waiting to be cached is data stored in a buffer storage area, and may be data obtained by a CPU operation or data loaded from a non-volatile memory.

[0038] After receiving the data to be cached, the computing device then divides the data to be cached to obtain at least two first fragmented data. In a specific implementation, the computing device can divide the data to be cached in a streaming manner to obtain at least two first fragmented data. The streaming process obtains a portion of the data to be cached, and then the portion becomes the first fragmented data.

[0039] In a specific implementation, in order to enable full utilization of the capacity of the memory particles, the computing device can divide the capacity of the memory particles as a division capacity and divide the data waiting to be cached into at least two first fragmented data.

[0040] S120: Sequentially write the first fragmented data into the first storage particles of the at least two storage blocks in a time division multiplexed manner.

[0041] S130: The correspondence between the first indicator of the data waiting to be cached and the first storage particle address is stored in the resource management table.

[0042] In an embodiment of the present disclosure, after dividing a memory block to obtain at least one first fragmented data, the computing device writes the first fragmented data to first memory particles in each memory block in a time-division multiplexed manner, and makes the first fragmented data written to each first memory particle different from each other.

[0043] Writing data in a time division multiplexing manner means that when one first fragmented data of the data waiting to be cached is written to one first memory particle, other fragmented data of the data waiting to be cached is not simultaneously written to other memory blocks, that is, the first fragmented data formed by dividing one piece of data waiting to be cached is written to memory blocks sequentially in time, and is not written to at least two memory blocks simultaneously.

[0044] It should be noted that the first fragmented data written to each first storage block are different from each other. The above-mentioned "different" does not mean that the numbers of the first fragmented data are different from each other, but rather that the data contents of the first fragmented data are different. In actual implementation, due to the data characteristics of the data waiting to be cached, the data contents of the divided first fragmented data may be the same. Since the first fragmented data written to each first storage block are different from each other, it can be seen that each first fragmented data of the data waiting to be cached is written to the cache storage area only once.

[0045] In a specific implementation, to successfully store the data waiting to be cached in the buffer memory area, after receiving the data waiting to be cached, the resource management module in the computing device first determines whether there are sufficient memory resources available for allocation. If there are not enough memory resources available for allocation, the computing device can discard the data waiting to be cached. If there are enough memory particles, the computing device can obtain an idle memory particle address and then write the first fragmented data to the corresponding memory particle.

[0046] After allocating the spatial storage particle addresses to the first fragmented data, the computing device writes a correspondence between the first identifier of the data to be cached and the storage particle address (i.e., the first storage particle address) into a resource management table so that the first fragmented data can be retrieved later and the first fragmented data can be used to splice the data to be cached. As the first fragmented data is sequentially stored in the buffer storage area, the computing device writes the addresses of each first storage particle, which are sequentially allocated in a streaming manner, into the resource management table.

[0047] As described above, in the embodiment of the present disclosure, the computing device writes the first fragmented data to the first memory particles of at least two storage blocks. That is, the first fragmented data divided by the data to be cached is distributed and stored in at least two storage blocks. Meanwhile, the computing device stores the first fragmented data of the data to be cached in a time-division multiplexed manner. Therefore, at one time, the buffered data occupies the address bus and data bus of one data block. Therefore, while storing one piece of cached data, the address bus and data bus of other storage blocks are not occupied, and the corresponding memory blocks with unoccupied buses can be used to read other cached data. That is, when S120 is performed, each storage block can perform data read operations in parallel. That is, by employing the buffered data reading method according to the present disclosure, the computing device can execute multiple read tasks in parallel. Because multiple read tasks can be executed simultaneously, the overhead of data read and write time when the computing device executes a large amount of cached data read tasks can be reduced accordingly.

[0048] The following takes the buffer data reading method according to the embodiment of the present disclosure as an example for analysis.

[0049] 3 is a schematic diagram of a cache data storage process in some embodiments of the present disclosure. FIG. 4 is a schematic diagram of a distribution of first fragmented data obtained based on the storage process of FIG.

[0050] 3 , in some embodiments, during a certain period of time, the buffer storage area of ​​the computing device receives only one buffered data packet, and the buffered data packet is divided into eight first fragmented data packets. At time T0, the first fragmented data packet with number Data0 is written to the first memory particle of storage block 0, at time T1, the first fragmented data packet with number Data1 is written to the first memory particle of storage block 1, at time T2, the first fragmented data packet with number Data2 is written to the first memory particle of storage block 2, at time T3, the first fragmented data packet with number Data3 is written to the first memory particle of storage block 3, at time T4, the first fragmented data packet with number Data4 is written to the second memory particle of storage block 1, at time T5, the first fragmented data packet with number Data5 is written to the second memory particle of storage block 2, at time T6, the first fragmented data packet with number Data6 is written to the second memory particle of storage block 3, and at time T7, the first fragmented data packet with number Data7 is written to the second memory particle of storage block 3.

[0051] Thus, the first fragmented data is stored in the manner of FIG. 3, with Data0 and Data4 stored in storage block 0, Data1 and Data5 stored in storage block 2, Data2 and Data6 stored in storage block 2, and Data3 and Data7 stored in storage block 3.

[0052] 3, at times T0 and T4, the buses for storage blocks 1, 2, and 3 are idle; at times T1 and T5, the buses for storage blocks 0, 1, and 2 are idle; at times T2 and T6, the buses for storage blocks 0, 1, and 3 are idle; and at times T3 and T7, the buses for storage blocks 0, 1, and 2 are idle. If there are relatively many read tasks, by rationally arranging the storage locations of other buffer data, the computing device can simultaneously share the buses of the four storage blocks and achieve four parallel reads. If the data bus bandwidth of each storage block is xGbit / s, when a computing device arranges four storage blocks, its data bus can theoretically reach 4xGbit / s.

[0053] 5 is a flowchart of another cache data reading method according to an embodiment of the present disclosure. As shown in FIG. 5, the cache data reading method according to an embodiment of the present disclosure includes S210 to S230.

[0054] S210: In response to the received sets of data to be cached, sequentially divide each set of data to be cached into at least two first fragmented data.

[0055] In an embodiment of the present disclosure, the plurality of sets of buffered data is at least two sets, and the number of sets of cached data is equal to or less than the number M of storage blocks. In a specific embodiment, when the number of sets of buffered data is greater than the number M of storage blocks, the computing device can determine M sets of cached data to be processed preferentially according to a priority order.

[0056] Similar to the above-mentioned S110, in an embodiment of the present disclosure, the computing device sequentially divides each set of buffered data into at least two first fragmented data, and more preferentially, the size of the first fragmented data into which each set of buffered data is divided is the same, and each is the storage capacity of one memory particle.

[0057] S220: First fragmented data corresponding to each set of data waiting to be cached is simultaneously written to first memory particles of at least two memory blocks in a time division multiplexing manner, where the memory blocks corresponding to each first fragmented data written at the same time are different from each other.

[0058] The concept of time division multiplexing mentioned in S220 is the same as that in S120, where only one first fragmented data of a set of buffered data is written to a storage block at a time.

[0059] The difference from S120 is that in this embodiment, at the same time, first fragmented data corresponding to at least two sets of buffered data are stored simultaneously, but each first fragmented data is written to a different storage block.

[0060] S230: The correspondence between the first indicator of the data waiting to be cached and the first storage particle address is stored in the resource management table.

[0061] The execution process of S230 is the same as that described above, and will not be further described here, but you may refer to the above description for details.

[0062] 6 is a schematic diagram of a cache data storage process in another embodiment of the present disclosure. FIG. 7 is a schematic diagram of a distribution of first fragmented data acquired based on the storage process of FIG.

[0063] 6, in some embodiments, during a certain period, the buffer storage area of ​​the computing device receives four sets of buffered data, and each set of buffered data is divided into five first fragmented data pieces, and the first fragmentation numbers for each set of buffered data pieces are DA0-DA4, DB0-DB4, DC0-DC4, and DD0-DD4, respectively.

[0064] At time T0, the first fragmented data with number DA0 is written to the first memory particle of memory block 0, the first fragmented data with number DB0 is written to the first memory particle of memory block 1, the first fragmented data with number DC0 is written to the first memory particle of memory block 2, and the first fragmented data with number DD0 is written to the first memory particle of memory block 3.

[0065] At time T1, the first fragmented data with number DA1 is written to the first memory particle of memory block 1, the first fragmented data with number DB1 is written to the first memory particle of memory block 2, the first fragmented data with number DC1 is written to the first memory particle of memory block 3, and the first fragmented data with number DD1 is written to the first memory particle of memory block 0.

[0066] At time T2, the first fragmented data with number DA2 is written to the first memory particle of memory block 2, the first fragmented data with number DB3 is written to the first memory particle of memory block 3, the first fragmented data with number DC2 is written to the first memory particle of memory block 0, and the first fragmented data with number DD3 is written to the first memory particle of memory block 1.

[0067] At time T3, the first fragmented data with number DA3 is written to the first memory particle of memory block 3, the first fragmented data with number DB3 is written to the first memory particle of memory block 0, the first fragmented data with number DC3 is written to the first memory particle of memory block 1, and the first fragmented data with number DD3 is written to the first memory particle of memory block 2.

[0068] At time T5, the first fragmented data with number DA5 is written to the first memory particle of memory block 1, the first fragmented data with number DB5 is written to the first memory particle of memory block 2, the first fragmented data with number DC5 is written to the first memory particle of memory block 3, and the first fragmented data with number DD5 is written to the first memory particle of memory block 0.

[0069] As shown in Figure 7, the cache data stored in each memory block is as follows: memory block 0 {DA0, DD1, DC1, DB3, DA4}, memory block 1 {DB0, DA1, DD2, DC3, DB4}, memory block 2 {DC0, DB1, DA2, DD3, DC4}, memory block 4 {DD0, DC1, DB2, DA3, DD4}.

[0070] Furthermore, as can be seen from the above example, each cache-waiting data is simultaneously written to a different memory block in a time-division multiplexed manner, so that the storage of each cache-waiting data is performed in parallel without interfering with each other, and the bandwidth of the data bus of the computing device theoretically reaches 4xGbit / s.

[0071] As in the above example, in some embodiments of the present disclosure, when the computing device executes S220, it writes the first fragmented data corresponding to each set of cache-waiting data to the first memory particles of at least two memory blocks simultaneously in a time-division multiplexed manner in a round-robin manner until all of the first fragmented data are written to the buffer memory area.

[0072] In a specific implementation, the above operation is performed in a round-robin manner, that is, each cache-waiting data is stored sequentially according to data block 0 to data block 3, and the first fragmented data is stored sequentially for each data block when allocating storage particle resources, so that the additional resource overhead is relatively small.

[0073] 8 is a flowchart of a data reading method according to some other embodiments of the present disclosure. As shown in FIG. 8, in some embodiments of the present disclosure, the data reading method includes S310 to S340.

[0074] S310: In response to the acquired buffer data read command, a second indicator, which is an indicator of data waiting to be output, is extracted from the buffer data read command.

[0075] S320: Query the resource management table based on the second indicator, and sequentially obtain addresses of at least two second storage particles distributed in at least two storage blocks, which are associated with the data waiting to be output.

[0076] Before executing S310, after determining the data waiting to be output, the computing device generates a corresponding buffer data read command to the buffer data read management module.

[0077] After receiving the buffer data read command, the buffer data read management module obtains a second indicator of the data waiting to be output, and then searches the resource management table based on the second indicator to obtain the address of the second memory particle corresponding to the data waiting to be output. The second fragmented data corresponding to the data waiting to be output is stored in the data particle corresponding to the address.

[0078] S330: Read second fragmented data from the storage particles of the at least two storage blocks according to the addresses of the second storage particles in a time division multiplex manner.

[0079] S340: Splice the second fragmented data until data waiting to be output is obtained.

[0080] Then, the computing device sequentially reads the second fragmented data according to the addresses of the second memory particles in a time-division multiplexed manner, where the second fragmented data is stored in at least two memory blocks, that is, after reading some of the second fragmented data from one memory block, it needs to read some of the second fragmented data from another memory block to obtain all of the second fragmented data for splicing the data waiting to be output.

[0081] Since it is necessary to read all the second fragmented data corresponding to the data waiting to be output from two storage blocks, during the period when the data waiting to be output is read, the data bus and address bus of a certain data block are not always used to output this second fragmented data corresponding to the data waiting to be output, and other data reading tasks can be performed.

[0082] That is, by adopting the buffer data reading method according to the present disclosure, a computing device can execute multiple read tasks in parallel, and since multiple read tasks can be executed simultaneously, the data read / write time overhead when the computing device executes a large amount of cache data reading tasks can be correspondingly reduced.

[0083] 9 is a schematic diagram of the cached data reading process in some embodiments of the present disclosure. The cached data shown in FIG. 9 is the data stored in the storage space in FIG. 3. As shown in FIG. 9, during a certain period, the computing device only needs to read one cached data. At time T0, the second fragmented data with number Data0 is read from memory block 0, at time T1, the second fragmented data with number Data1 is read from memory block 1, at time T2, the second fragmented data with number Data2 is read from memory block 2, at time T3, the first fragmented data with number Data3 is read from memory block 3, at time T4, the second fragmented data with number Data4 is read from memory block 0, at time T5, the second fragmented data with number Data5 is read from memory block 1, at time T6, the second fragmented data with number Data6 is read from memory block 2, and at time T7, the first fragmented data with number Data7 is read from memory block 3. Then, after splicing each second fragmented data according to the read order, the data waiting to be output can be obtained.

[0084] In some embodiments of the present disclosure, the number of data buffer read commands obtained when the computing device executes S310 is at least two, but the number of buffer data read commands is equal to or less than the number of storage blocks. Extracting the second indicator in the buffer data read commands in S320 specifically extracts the second indicator of each buffer data read command.

[0085] Accordingly, when extracting the second indicator of each buffer data read command, S320 is specifically S321: simultaneously read the second fragmented data from the memory addresses of at least two memory blocks according to the addresses of the second memory particles in a time-division multiplexing manner, and the memory blocks corresponding to each second fragmented data being read at the same time are different from each other.

[0086] 10 is a schematic diagram of a cached data read process in some cases of an embodiment of the present disclosure. The cached data in FIG. 10 is the data stored in the storage space in FIG. 3. As shown in FIG. 10, during a certain period, multiple data request commands all need to read the buffered data shown in FIG. 3, and the data read lines corresponding to each data request command are line 0, line 1, line 2, and line 3, respectively.

[0087] As shown in FIG. 10, at time T0, the second fragmented data Data0 stored in storage block 0 is read and transmitted to line 0; at time T1, the second fragmented data Data1 stored in storage block 1 is read and transmitted to line 0, and simultaneously the second fragmented data Data0 stored in storage block 0 is read and transmitted to line 1; at time T2, the second fragmented data Data2 stored in storage block 2 is read and transmitted to line 0, and simultaneously the second fragmented data Data1 stored in storage block 1 is read and transmitted to line 1, and the second fragmented data Data0 stored in storage block 0 is read and transmitted to line 2; at time T3, the second fragmented data Data3 stored in storage block 3 is read and transmitted to line 0, and simultaneously the second fragmented data Data2 stored in storage block 2 is read and transmitted to line 1, and the second fragmented data Data1 stored in storage block 1 is read and transmitted to line 3; The second fragmented data Data0 stored in memory block 0 is read out and transmitted to line 0, and then, at time T4, the second fragmented data Data2 stored in memory block 0 is read out and transmitted to line 0, and simultaneously, the second fragmented data Data3 stored in memory block 3 is read out and transmitted to line 1, the second fragmented data Data2 stored in memory block 2 is read out and transmitted to line 2, the second fragmented data Data1 stored in memory block 1 is read out and transmitted to line 3, ..., at time T7, the second fragmented data Data7 stored in memory block 3 is read out and transmitted to line 0, and simultaneously, the second fragmented data Data6 stored in memory block 2 is read out and transmitted to line 1, the second fragmented data Data5 stored in memory block 1 is read out and transmitted to line 2, and the second fragmented data Data4 stored in memory block 0 is read out and transmitted to line 3, and at this time, line 0 obtains the data waiting to be output.

[0088] Then, at time T8, the second fragmented data Data7 stored in memory block 3 is read out and transmitted to line 1, and at the same time, the second fragmented data Data6 stored in memory block 2 is read out and transmitted to line 2, and at this time, line 1 obtains the data waiting to be output.

[0089] Then, at time T9, the second fragmented data Data7 stored in memory block 3 is read out and transmitted to line 2, and the second fragmented data Data6 stored in memory block 2 is read out and transmitted to line 2, and at this time, line 2 obtains the data waiting to be output.

[0090] Finally, at time T10, the second fragmented data Data7 stored in storage block 3 is read out and transmitted to line 3, at which time line 3 acquires the data waiting to be output.

[0091] Based on the above analysis, in the embodiment of the present disclosure, the computing device uses 11 periods to complete the output of the same waiting data to four lines, which can significantly improve the data read speed compared to the prior art solution that requires 32 periods to complete the data transmission.

[0092] 11 is a flowchart of a data reading method according to some other embodiments of the present disclosure. As shown in FIG. 11, in some other embodiments of the present disclosure, the data reading method includes S410 to S440.

[0093] S410: In response to the data waiting to be cached and the buffer data read command received simultaneously, sequentially divide the data waiting to be cached into at least two first fragmented data, and extract a second indicator in the buffer data read command.

[0094] The second indicator is an indicator of data waiting to be output. In the embodiment of the present disclosure, the sum of the number of sets of data waiting to be output and the number of sets of data waiting to be buffered is less than or equal to the number of storage blocks. For example, if the number of storage blocks is four, the sum of the number of sets of data waiting to be output and the number of sets of data waiting to be buffered is a maximum of four.

[0095] S420: Query the resource management table based on the second indicator to sequentially obtain addresses of at least two second storage particles associated with the data waiting to be output.

[0096] The second memory particles are distributed in at least two memory blocks. In a specific implementation, the execution process of S420 is the same as the execution process of S320, and will not be further described here.

[0097] S430: Sequentially write the first fragmented data into first memory particles of at least two memory blocks in a time division multiplexing manner, and read the second fragmented data from the at least two memory blocks according to the addresses of the second memory particles in a time division multiplexing manner.

[0098] S440: The correspondence between the first mark of the data waiting to be cached and the first storage particle address is stored in the resource management table, and the read second fragmented data is spliced ​​until the data waiting to be output is obtained.

[0099] In an embodiment of the present disclosure, the computing device writes first fragmented data to first memory particles of at least two memory blocks in a time-division multiplexed manner, and simultaneously reads second fragmented data from the at least two memory blocks according to addresses of the second memory particles.

[0100] 12 is a schematic diagram of a buffer data reading process according to some embodiments of the present disclosure. As shown in FIG. 12, line 0 transmits buffered data DA0-DA3, and line 1 simultaneously reads data waiting to be output from a data block. The data waiting to be output is specifically DB0-DB3, where DB0 is stored in memory block 0, DB1 is stored in memory block 1, DB2 is stored in memory block 2, and DB3 is stored in memory block 3. If a computing device simultaneously receives a data read command for the buffered data transmitted from line 1 and the data waiting to be output from line 2, since the priority of line 2 is higher than the priority of line 1, the computing device will preferentially allocate resources to line 2 and line 1. At time T0, the second fragmented data DB0 stored in memory block 0 is read and sent to line 2, and simultaneously the first fragmented data DA0 on line 1 is written to memory block 1; at time T1, the second fragmented data DB1 stored in memory block 1 is read and sent to line 2, and simultaneously the first fragmented data DA1 on line 1 is written to memory block 2; at time T2, the second fragmented data DB2 stored in memory block 2 is read and sent to line 2, and simultaneously the second fragmented data DA2 on line 1 is written to memory block 3; and at time T3, the second fragmented data DB3 stored in memory block 3 is read and sent to line 2, and simultaneously the second fragmented data DA3 on line 1 is written to memory block 0.

[0101] That is, by adopting four periods, writing of buffered data in line 1 and reading of output-awaiting data in line 2 can be realized simultaneously. Compared with the case where buffered data and output-awaiting data are simultaneously stored in one storage block, this can save four periods and improve the parallel data reading efficiency.

[0102] The above is a data reading method according to an embodiment of the present disclosure. In the above introduction, the number of second fragmented data stored in the data block is relatively small, and the memory particles corresponding to the second fragmented data are not reclaimed by discarding the second fragmented data, so the second fragmented data of the same cache data stored in each memory block are closer to each other. In actual application, if the number of second fragmented data stored in the data block is large, and some second fragmented data are discarded to reclaim the corresponding memory particles, the storage of the second fragmented data in the memory block will show various complex arrangements, and the embodiment of the present disclosure will not provide further examples.

[0103] Furthermore, when implementing various cache data reading methods according to the embodiments of the present disclosure, clock synchronization is performed for each memory block bus, ensuring that each memory block executes its respective data reading task in parallel at a given time.

[0104] In addition to the cache data reading method, the embodiment of the present disclosure further provides a structural diagram of a buffer data reading device. Figure 13 is a structural diagram of a cache data reading device according to the embodiment of the present disclosure. As shown in Figure 13, the buffer data reading device 1300 according to the embodiment of the present disclosure includes a data dividing unit 1301, a data writing unit 1302, and a correspondence saving unit 1303. Note that the cache data reading device is applied to a computing device, which includes a buffer memory area including at least two memory blocks, each with an independent address bus and data bus, and each with a plurality of memory particles.

[0105] The data division unit 1301 is used to respond to received data waiting to be cached and sequentially divide the data waiting to be cached into at least two first fragmented data; the data writing unit 1302 is used to sequentially write the first fragmented data to first memory particles of at least two memory blocks in a time division multiplexing manner, and make the first fragmented data written to each first memory particle different; and the correspondence saving unit 1303 is used to save the correspondence between the first indicator of the data waiting to be cached and the first memory particle address in the resource management table.

[0106] In some embodiments, the number of data waiting to be cached is a plurality of sets, and the number of sets of data waiting to be cached is equal to or less than the number of memory blocks, and the data writing unit 1302 simultaneously writes the first fragmented data corresponding to each set of data waiting to be cached to the first memory particles of at least two memory blocks in a time-division multiplexed manner, where the memory blocks corresponding to each first fragmented data written at the same time are different from each other.

[0107] In some embodiments, writing the first fragmented data corresponding to each set of cache-waiting data to the first memory particles of at least two memory blocks simultaneously in a time-division multiplexed manner includes the data writing unit 1302 writing the first fragmented data corresponding to each set of cache-waiting data to the first memory particles of the at least two memory blocks simultaneously in a time-division multiplexed manner in a round-robin manner until all of the first fragmented data are written to the buffer memory area.

[0108] In some embodiments, the storage capacities of the storage particles in each storage block are all the same, and the data division unit 1301 sequentially divides the data to be cached into at least two first fragmented data according to the storage capacities of the storage particles.

[0109] Optionally, the device includes: an indicator extraction unit, in response to the acquired buffer data read command, for extracting a second indicator in the buffer data read command, the second indicator being an indicator of data waiting to be output, where the sum of the number of sets of data waiting to be output and the number of sets of data waiting to be buffered is less than or equal to the number of storage blocks; a relation query unit for querying the resource management table according to the second indicator, and sequentially obtaining addresses of at least two second storage particles distributed in the at least two storage blocks, which are associated with the data waiting to be output; a data read unit for the data write unit 1302 to sequentially write first fragmented data to first memory particles of at least two memory blocks in a time division multiplexing manner, and simultaneously read second fragmented data from at least two memory blocks according to addresses of second memory particles in a time division multiplexing manner, wherein the memory blocks corresponding to the first fragmented data written at the same time and the memory blocks corresponding to the second fragmented data being read are different; and a data splicing unit for splicing the read second fragmented data until obtaining data waiting to be output.

[0110] 14 is a structural schematic diagram of a cache data reading device according to an embodiment of the present disclosure. As shown in FIG. 14, a cache data reading device 1400 according to an embodiment of the present disclosure includes an indicator extraction unit 1401, a relation query unit 1402, a data reading unit 1403, and a data splicing unit 1404.

[0111] The indicator extraction unit 1401 is used to extract a second indicator in the buffer data read command in response to the obtained buffer data read command, which is an indicator of data waiting to be output.

[0112] The relational query unit 1402 is used to query the resource management table based on the second indicator, and sequentially obtain addresses of at least two second memory particles distributed in at least two memory blocks that are related to the data waiting to be output.

[0113] The data reading unit 1403 is used for reading the second fragmented data from the storage particles of the at least two storage blocks according to the addresses of the second storage particles in a time-division multiplexed manner.

[0114] The data splicing unit 1404 is used to splice the second fragmented data until obtaining the data to be output.

[0115] In some embodiments, the number of data buffer read commands is at least two, and the number of buffer data read commands is less than or equal to the number of memory blocks, the data reading unit 1403 simultaneously reads the second fragmented data from the memory addresses of at least two memory blocks according to the addresses of the second memory particles in a time-division multiplexed manner, and the memory blocks corresponding to each of the second fragmented data read at the same time are different, and the data splicing unit 1404 splices the second fragmented data corresponding to each second mark respectively until all the data waiting to be output is obtained.

[0116] An embodiment of the present disclosure further provides a computing device including a processor and a memory storing a computer program that, when executed by the processor, can implement the method for recording a driver assistance system problem of any one of the above embodiments.

[0117] 15 is a structural schematic diagram of a computing device according to an embodiment of the present disclosure. Hereinafter, specific reference will be made to FIG. 15, which illustrates a structural schematic diagram suitable for implementing a computing device 1500 according to an embodiment of the present disclosure. It should be noted that the computing device illustrated in FIG. 15 is merely an example and does not limit the functionality and scope of use of the embodiment of the present disclosure.

[0118] 15, computing device 1500 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 1501, which can perform various appropriate operations and processes based on programs stored in read-only memory ROM 1502 or programs loaded from storage device 1508 into random access memory RAM 1503. RAM 1503 also stores various programs and data necessary to operate computing device 1500. Processing unit 1501, ROM 1502, and RAM 1503 are connected to each other by bus 1504. Input / output I / O interface 1505 is also connected to bus 1504.

[0119] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product including a computer program embodied on a non-transitory computer-readable medium, the computer program including program code for performing the methods shown in the flowcharts. In such embodiments, the computer program may be downloaded and installed from a network via the communication device 1509, or may be installed from the storage device 1508, or may be installed from the ROM 1502. When the computer program is executed by the processing device 1501, it performs the functions described above that are specific to the methods of the embodiments of the present disclosure.

[0120] It should be noted that the above-mentioned computer-readable medium in the present disclosure may be a computer-readable signal medium, a computer-readable storage medium, or any combination of the above. The computer-readable storage medium may be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of the computer-readable storage medium may include, but are not limited to, an electrical connection having one or more leads, a portable computer magnetic disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact magnetic disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program, which can be used by or in combination with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium may include a propagated data signal, either in baseband or as part of a carrier, bearing computer-readable program code. Such a propagated data signal may take multiple forms, including, but not limited to, an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may be any computer-readable medium other than a computer-readable storage medium, which is capable of transmitting, propagating, or transmitting a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted over any suitable medium, including, but not limited to, electrical wire, optical cable, RF (radio frequency), etc., or any suitable combination of the above.

[0121] The computer-readable medium may be included in the computing device or may exist separately and not integrated into the computing device.

[0122] The computer-readable device carries one or more programs, and when the one or more programs are executed by the computing device, the computing device responds to received data to be cached, sequentially divides the data to be cached into at least two first fragmented data, sequentially writes the first fragmented data to first memory particles of at least two memory blocks in a time-division multiplexed manner, makes the first fragmented data written to each first memory particle different, and calculates a correspondence between a first indicator of the data to be cached and an address of the first memory particle in a resource management table. In response to the buffer data read command obtained and / or stored in the resource management table, extract a second indicator in the buffer data read command, which is an indicator of data waiting to be output, query the resource management table based on the second indicator, sequentially obtain addresses of at least two second memory particles distributed in at least two memory blocks, which are related to the data waiting to be output, read the second fragmented data from the memory particles of the at least two memory blocks according to the addresses of the second memory particles in a time division multiplexing manner, and splice the second fragmented data until the data waiting to be output is obtained.

[0123] Computer program code for carrying out the operations of the present disclosure can be written in one or more programming languages ​​or a combination thereof, such as Java (registered trademark), Smalltalk, C++, and similar programming languages, and further includes conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may run entirely on the tester computer, partially on the tester computer, as a single, separate software package, partially on the tester computer and partially on a remote computer, or entirely on a remote computer or server. In the context of a remote computer, the remote computer may be connected to the tester computer by any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., connected by the Internet using an Internet Service Provider).

[0124] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functions, and operations that may be implemented in accordance with systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, program segment, or portion of code, which includes one or more executable instructions for implementing a given logical function. It should be noted that in some alternative implementations, the functions displayed in the blocks may occur in a different order than that displayed in the accompanying drawings. For example, two blocks shown in succession may actually be executed substantially in parallel or may be executed in the reverse order depending on the functionality involved. It should be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs a given function or operation, or by a combination of dedicated hardware and computer instructions.

[0125] The units described in relation to the embodiments of the present disclosure may be implemented in a software or hardware manner, and the names of the units do not necessarily constitute limitations on the units themselves.

[0126] The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), etc.

[0127] In the context of this disclosure, a machine-readable medium may be a tangible medium, including or storing a program used in or coupled to an instruction execution system, device, or appliance. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or appliance, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include an electrical connection with one or more leads, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0128] An embodiment of the present disclosure further provides a computer-readable storage medium storing a computer program that, when executed by a processor, can realize the method of any one of the above method embodiments, the execution manner of which is similar to beneficial effects and will not be further described herein.

[0129] It should be noted that, in this specification, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply the existence of any such actual relationship or ordering between those entities or operations. Furthermore, the terms "comprise," "include," "includes," or any other variant thereof are intended to cover a non-exclusive "comprise," whereby a process, method, article, or device comprising a set of elements not only includes those elements, but also other elements not expressly listed, or elements inherent in such process, method, article, or device. Absent further limitations, an element defined by the phrase "comprises one of," does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0130] The foregoing are merely specific embodiments of the present disclosure that will enable those skilled in the art to understand or realize the present disclosure. Various modifications to these examples will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other examples without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0131] (Addendum) (Appendix 1) A cache data reading method applied to a computing device, the computing device including a buffer storage area including at least two storage blocks, each of the storage blocks having an independent address bus and a data bus, and each of the storage blocks having a plurality of storage particles, the method comprising: In response to the received data to be cached, sequentially dividing the data to be cached into at least two first fragmented data pieces; sequentially writing the first fragmented data to first memory particles of at least two of the storage blocks in a time division multiplexed manner, and making the first fragmented data written to each of the first memory particles different; and storing a correspondence between the first indicator of the data waiting to be cached and the first storage particle address in a resource management table.

[0132] (Appendix 2) the number of data waiting to be cached is a plurality of sets, and the number of sets of data waiting to be cached is equal to or less than the number of storage blocks; the step of sequentially dividing the data to be cached into at least two first fragmented data includes sequentially dividing each set of the data to be cached into at least two first fragmented data; The aforementioned sequentially writing the first fragmented data to the first memory particles of the at least two memory blocks in a time division multiplexing manner includes: The method described in Appendix 1 includes simultaneously writing the first fragmented data corresponding to each set of cache-waiting data to first memory particles of the at least two memory blocks in a time-division multiplexed manner, wherein the memory blocks corresponding to each first fragmented data written at the same time are different from each other.

[0133] (Appendix 3) The above-mentioned writing the first fragmented data corresponding to each set of cache-waiting data to the first storage particles of the at least two storage blocks simultaneously in the time-division multiplexed manner includes: 3. The method of claim 2, further comprising writing the first fragmented data corresponding to each set of cache-waiting data to first memory particles of the at least two memory blocks simultaneously in a time-division multiplexed round-robin manner until all of the first fragmented data have been written to the buffer memory area.

[0134] (Appendix 4) The storage capacity of the storage particles in each of the storage blocks is the same; 2. The method of claim 1, wherein sequentially dividing the data to be cached into at least two first fragmented data includes sequentially dividing the data to be cached into at least two first fragmented data according to the storage capacity of the storage particles.

[0135] (Appendix 5) The method comprises: In response to the acquired buffer data read command, extract a second indicator in the buffer data read command, which is an indicator of data waiting to be output, wherein the sum of the number of sets of data waiting to be output and the number of sets of data waiting to be buffered is equal to or less than the number of storage blocks; querying a resource management table based on the second indicator to sequentially obtain addresses of at least two second memory particles distributed in at least two memory blocks, which are associated with the data waiting to be output; While sequentially writing the first fragmented data to first storage particles of at least two of the storage blocks in a time division multiplexed manner, the method includes: In a time division multiplexing manner, read out the second fragmented data from at least two memory blocks according to the address of the second memory particle, wherein the memory blocks corresponding to the first fragmented data written at the same time are different from the memory blocks corresponding to the second fragmented data being read out; 2. The method of claim 1, further comprising: splicing the read second fragmented data until the data waiting to be output is obtained.

[0136] (Appendix 6) A cache data reading method applied to a computing device, the computing device including a buffer storage area including at least two storage blocks, each of the storage blocks having a plurality of storage particles and each of the storage blocks having an independent system bus, the method comprising: In response to the acquired buffer data read command, extracting a second indicator in the buffer data read command, the second indicator being an indicator of data waiting to be output; querying a resource management table based on the second indicator to sequentially obtain addresses of at least two second memory particles distributed in at least two memory blocks associated with the data waiting to be output; reading second fragmented data from the storage particles of at least two storage blocks according to the addresses of the second storage particles in a time division multiplexed manner; splicing the second fragmented data until the data waiting to be output is obtained.

[0137] (Appendix 7) 7. The method of claim 6, wherein the number of data buffer read commands is at least two, and the number of buffer data read commands is less than or equal to the number of storage blocks.

[0138] (Appendix 8) 7. The method of claim 6, wherein extracting the second indicator in the buffer data read command includes extracting the second indicator for each of the buffer data read commands.

[0139] (Appendix 9) The above-mentioned reading of the second fragmented data from the memory particles of at least two memory blocks according to the addresses of the second memory particles in a time division multiplexing manner includes: 7. The method of claim 6, further comprising: simultaneously reading out second fragmented data from memory addresses of at least two memory blocks according to the addresses of the second memory particles in a time-division multiplexed manner, wherein the memory blocks corresponding to the second fragmented data being read out at the same time are different from each other.

[0140] (Appendix 10) The splicing of the second fragmented data until the data waiting to be output is obtained includes: 7. The method of claim 6, further comprising splicing second fragmented data corresponding to each of the second markers until all of the data waiting to be output is obtained.

[0141] (Appendix 11) A computing device including a processor, a volatile memory, and a non-volatile memory, wherein the volatile memory includes at least two storage blocks, each of which has an independent system bus and each of which has a plurality of storage particles, and the non-volatile memory is used to store a computer program, which, when loaded by the processor, causes the processor to execute a cache data reading method, the method being applied to a computing device, wherein the computing device includes a buffer storage area including at least two storage blocks, each of which has an independent address bus and data bus, and each of which has a plurality of storage particles, the method comprising: In response to the received data to be cached, sequentially dividing the data to be cached into at least two first fragmented data pieces; sequentially writing the first fragmented data to first memory particles of at least two of the storage blocks in a time division multiplexed manner, and making the first fragmented data written to each of the first memory particles different; and storing a correspondence between the first indicator of the data waiting to be cached and the first storage particle address in a resource management table.

[0142] (Appendix 12) the number of data waiting to be cached is a plurality of sets, and the number of sets of data waiting to be cached is equal to or less than the number of storage blocks; the step of sequentially dividing the data to be cached into at least two first fragmented data includes sequentially dividing each set of the data to be cached into at least two first fragmented data; The aforementioned sequentially writing the first fragmented data to the first memory particles of the at least two memory blocks in a time division multiplexing manner includes: 12. The computing device of claim 11, further comprising: simultaneously writing the first fragmented data corresponding to each set of cache-waiting data to first memory particles of the at least two memory blocks in a time-division multiplexed manner, wherein the memory blocks corresponding to each first fragmented data written at the same time are different from each other.

[0143] (Appendix 13) The above-mentioned writing the first fragmented data corresponding to each set of cache-waiting data to the first storage particles of the at least two storage blocks simultaneously in the time-division multiplexed manner includes: 13. The computing device of claim 12, further comprising: writing the first fragmented data corresponding to each set of cache-waiting data to first storage particles of the at least two storage blocks simultaneously in a time-division multiplexed round-robin manner until all of the first fragmented data have been written to the buffer storage area.

[0144] (Appendix 14) The storage capacity of the storage particles in each of the storage blocks is the same; 12. The computing device of claim 11, wherein sequentially dividing the data to be cached into at least two first fragmented data pieces includes sequentially dividing the data to be cached into at least two first fragmented data pieces according to a storage capacity of the storage particles.

[0145] (Appendix 15) The method comprises: In response to the acquired buffer data read command, extract a second indicator in the buffer data read command, which is an indicator of data waiting to be output, wherein the sum of the number of sets of data waiting to be output and the number of sets of data waiting to be buffered is equal to or less than the number of storage blocks; querying a resource management table based on the second indicator to sequentially obtain addresses of at least two second memory particles distributed in at least two memory blocks, which are associated with the data waiting to be output; While sequentially writing the first fragmented data to first storage particles of at least two of the storage blocks in a time division multiplexed manner, the method includes: In a time division multiplexing manner, read out the second fragmented data from at least two memory blocks according to the address of the second memory particle, wherein the memory blocks corresponding to the first fragmented data written at the same time are different from the memory blocks corresponding to the second fragmented data being read out; 12. The computing device of claim 11, further comprising: splicing the read second fragmented data until obtaining the data awaiting output.

Claims

1. A cache data reading method applied to a computing device, the computing device including a buffer storage area including at least two storage blocks, each of the storage blocks having an independent address bus and a data bus, and each of the storage blocks having a predetermined number of storage particles, the method comprising: In response to the received data to be cached, sequentially dividing the data to be cached into at least two first fragmented data; sequentially writing the first fragmented data to first memory particles at different locations of at least two of the storage blocks in a time division multiplexing manner, so that the first fragmented data written to each of the first memory particles at the same address of each of the storage blocks is different; storing a correspondence between the first indicator of the data waiting to be cached and the address of the first storage particle for each of the storage blocks in a resource management table.

2. the number of data waiting to be cached is a plurality of sets, and the number of sets of data waiting to be cached is equal to or less than the number of storage blocks; The aforementioned sequentially dividing the data to be cached into at least two first fragmented data includes sequentially dividing each set of the data to be cached into at least two first fragmented data; The above-mentioned writing of the first fragmented data sequentially to first memory particles at different positions of at least two of the storage blocks in a time division multiplexing manner includes:

2. The method of claim 1, further comprising: simultaneously writing the first fragmented data corresponding to each set of cache-waiting data to first memory particles of the at least two memory blocks in the time-division multiplexed manner, wherein the memory blocks corresponding to each of the first fragmented data written at the same time are different from each other.

3. The above-mentioned writing the first fragmented data corresponding to each set of cache-waiting data to the first storage particles of the at least two storage blocks simultaneously in the time-division multiplexed manner includes:

3. The method of claim 2, further comprising writing the first fragmented data corresponding to each set of cache-waiting data to first memory particles of the at least two memory blocks simultaneously in a time-division multiplexed round-robin manner until all of the first fragmented data have been written to the buffer memory area.

4. The storage capacity of the storage particles in each of the storage blocks is the same; 2. The method of claim 1, wherein sequentially dividing the data to be cached into at least two first fragmented data includes sequentially dividing the data to be cached into the at least two first fragmented data according to a storage capacity of the storage particles.

5. The method comprises: In response to the acquired buffer data read command, extract a second indicator in the buffer data read command, which is an indicator of data waiting to be output, and wherein the sum of the number of sets of data waiting to be output and data waiting to be buffered is equal to or less than the number of storage blocks; querying a resource management table based on the second indicator to sequentially obtain addresses of at least two second storage particles distributed in at least two storage blocks, which are associated with the data waiting to be output; While sequentially writing the first fragmented data to first storage particles of at least two of the storage blocks in a time division multiplexed manner, the method includes: In a time division multiplexing manner, read out the second fragmented data from at least two storage blocks according to the addresses of the second memory particles, wherein the storage blocks corresponding to the first fragmented data written at the same time are different from the storage blocks corresponding to the second fragmented data being read out; The method of claim 1 , further comprising: splicing the read second fragmented data until obtaining the data awaiting output.

6. A cache data reading method applied to a computing device, the computing device including a buffer storage area including at least two storage blocks, each of the storage blocks having a plurality of storage particles and each of the storage blocks having an independent system bus, the method comprising: In response to the acquired buffer data read command, extracting a second indicator in the buffer data read command, the second indicator being an indicator of data waiting to be output; querying a resource management table based on the second indicator to sequentially obtain addresses of at least two second storage particles for at least two storage blocks associated with the data waiting to be output; reading, for each of the storage blocks, second fragmented data from the storage particles of at least two storage blocks according to the addresses of the second storage particles in a time division multiplexing manner; splicing the second fragmented data until the data waiting to be output is obtained.

7. 7. The method of claim 6, wherein the number of the buffer data read commands is at least two, and the number of the buffer data read commands is less than or equal to the number of the storage blocks.

8. 7. The method of claim 6, wherein extracting the second indicator in the buffer data read command comprises extracting the second indicator for each of the buffer data read commands.

9. The above-mentioned reading of the second fragmented data from the memory particles of at least two memory blocks according to the addresses of the second memory particles for each of the memory blocks in a time division multiplexing manner includes:

7. The method of claim 6, further comprising: simultaneously reading out the second fragmented data from the memory addresses of at least two memory blocks according to the addresses of the second memory particles in the time division multiplexed manner, and the memory blocks corresponding to the second fragmented data being read out at the same time are different from each other.

10. The splicing of the second fragmented data until the data waiting to be output is obtained includes: The method of claim 6 , further comprising splicing second fragmented data corresponding to each of the second indicators respectively until all of the output data is obtained.

11. A computing device including a processor, a volatile memory, and a non-volatile memory, wherein the volatile memory includes at least two storage blocks, each of which has an independent system bus and each of which has a predetermined number of storage particles, and the non-volatile memory is used to store a computer program, and when the computer program is loaded by the processor, causes the processor to perform a cache data reading method, the method being applied to a computing device, wherein the computing device includes a buffer storage area including at least two storage blocks, each of which has an independent address bus and data bus and each of which has a plurality of storage particles, the method comprising: In response to the received data to be cached, sequentially dividing the data to be cached into at least two first fragmented data; sequentially writing the first fragmented data to first memory particles at different locations of at least two of the storage blocks in a time division multiplexing manner, so that the first fragmented data written to each of the first memory particles at the same address of each of the storage blocks is different; storing a correspondence between the first indication of the data waiting to be cached and an address of the first storage particle for each of the storage blocks in a resource management table.

12. the number of data waiting to be cached is a plurality of sets, and the number of sets of data waiting to be cached is equal to or less than the number of storage blocks; The aforementioned sequentially dividing the data to be cached into at least two first fragmented data includes sequentially dividing each set of the data to be cached into at least two first fragmented data; The above-mentioned writing of the first fragmented data sequentially to first memory particles at different positions of at least two of the storage blocks in a time division multiplexing manner includes:

12. The computing device of claim 11, further comprising: simultaneously writing the first fragmented data corresponding to each set of cache-waiting data to first memory particles of the at least two memory blocks in the time-division multiplexed manner, wherein the memory blocks corresponding to each of the first fragmented data written at the same time are different from each other.

13. The above-mentioned writing the first fragmented data corresponding to each set of cache-waiting data to the first storage particles of the at least two storage blocks simultaneously in the time-division multiplexed manner includes:

13. The computing device of claim 12, further comprising: writing the first fragmented data corresponding to each set of cache-waiting data to first storage particles of the at least two storage blocks simultaneously in a time-division multiplexed round-robin manner until all of the first fragmented data have been written to the buffer storage area.

14. The storage capacity of the storage particles in each of the storage blocks is the same; 12. The computing device of claim 11, wherein sequentially dividing the data to be cached into at least two first fragmented data pieces comprises sequentially dividing the data to be cached into the at least two first fragmented data pieces according to a storage capacity of the storage particles.

15. The method comprises: In response to the acquired buffer data read command, extract a second indicator in the buffer data read command, which is an indicator of data waiting to be output, and wherein the sum of the number of sets of data waiting to be output and data waiting to be buffered is equal to or less than the number of storage blocks; querying a resource management table based on the second indicator to sequentially obtain addresses of at least two second storage particles distributed in at least two storage blocks, which are associated with the data waiting to be output; While sequentially writing the first fragmented data to first storage particles of at least two of the storage blocks in a time division multiplexed manner, the method includes: In a time division multiplexing manner, read out the second fragmented data from at least two storage blocks according to the addresses of the second memory particles, wherein the storage blocks corresponding to the first fragmented data written at the same time are different from the storage blocks corresponding to the second fragmented data being read out; The computing device of claim 11 , further comprising: splicing the read second fragmented data until obtaining the data awaiting output.

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