Zero-Value Memory Compression

Abstract

The coherency management device receives a request to read or write data from or to an address in main memory. On a write, if the data contains zero data, an entry corresponding to the memory address is created in the cache directory if one does not exist and is set to an invalid state, indicating that the data contains zero data. The zero data is not written to main memory or the cache. On a read, the cache directory is checked for an entry corresponding to the memory address. If an entry exists in the cache directory, is invalid, and contains an indication that the data corresponding to the memory address contains zero data, the coherency management device returns the zero data in response to the request without fetching the data from main memory or the cache.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Patent Application No. 16 / 723,780, filed December 20, 2019, the contents of which are incorporated herein by reference. [Background technology]

[0002] The main memory of a computer system typically includes relatively inexpensive, high-density memory devices, such as dynamic random access memory (DRAM) devices. However, the access times of such devices are typically relatively long. Therefore, computer systems typically include at least one cache memory to improve performance. A cache memory is a relatively fast memory device that is typically located relatively close to the processor. In a multiprocessor computer system, each processor (or processor core) typically has its own dedicated level 1 (L1) cache and possibly shares other caches (e.g., level 2 (L2), level 3 (L3)) with other processors or processor cores.

[0003] In multi-node computer systems where each node (e.g., processor, core, or core complex) has its own dedicated cache, techniques are implemented to maintain coherency of data being used by different nodes. For example, when a processor attempts to access data stored in main memory at a particular memory address, it must first determine whether the data corresponding to that memory address is stored in another cache and has been modified. Some such approaches include a cache directory used to track cache lines currently in use by the system. In some cases, the cache directory improves memory bandwidth by reducing the number of memory requests and probe requests required by the computer system. Cache directories are typically oversized (due to "guard bands") to handle, for example, local "hot-spots" of particular data sets during application execution. Therefore, applications typically leave spare, unused entries in the cache directory.

[0004] In some applications, the processor writes zero data (i.e., data containing only zeros) to main memory. Such applications may include erasing memory (e.g., clearing memory for another purpose) or storing datasets characterized by a high degree of data sparsity (e.g., machine learning data).

[0005] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of an example device capable of implementing one or more features of the present disclosure. [Figure 2] FIG. 2 is a block diagram of the device of FIG. 1 illustrating additional details. [Figure 3] FIG. 1 is a block diagram illustrating portions of an exemplary computing system. [Figure 4] FIG. 1 is a block diagram illustrating portions of an exemplary multiprocessor computing system. [Figure 5] FIG. 2 is a block diagram illustrating an example implementation of a cache directory. [Figure 6] 10 is a flowchart illustrating an exemplary method for zero data compression by a coherence management device during a write operation. [Figure 7] 10 is a flowchart illustrating an exemplary method for zero data compression by a coherence management device during a read operation. DETAILED DESCRIPTION OF THE INVENTION

[0007] In some implementations, a coherency management device is provided. The coherency management device includes circuitry that receives a request to read data stored at an address in main memory. The coherency management device also includes circuitry that determines whether a cache directory includes a cache directory entry corresponding to the address. If the cache directory includes a cache directory entry corresponding to the address, the coherency management device also includes circuitry that determines whether the cache directory entry is invalid. If the cache directory entry is invalid, the coherency management device also includes circuitry that determines whether the cache directory entry includes an indication that the data corresponding to the memory address contains zero data. The coherency management device also includes circuitry that returns the zero data in response to the request if the cache directory entry includes the indication.

[0008] In some implementations of the coherency management device, the indication includes a bit in the cache directory entry. In some implementations, the indication includes a preliminary state in a state field of the cache directory entry. In some implementations, the indication includes at least one bit in the state field of the cache directory entry. In some implementations, the indication includes a bit in a shared vector field of the cache directory entry. In some implementations, the coherency management device does not read the main memory and returns zero data in response to the request if the cache directory entry is invalid and includes the indication. In some implementations, the coherency management device includes a coherent slave device, a probe filter device, and / or a snoop filter device. In some implementations, the coherency management device receives a request from a coherent master device. In some implementations, the request includes a non-transient read operation.

[0009] Some implementations provide a method implemented in a coherency management device for managing cache coherency in a computer system. The method includes receiving a request to read data stored at an address in main memory and determining whether a cache directory includes a cache directory entry corresponding to the address. The method also includes, if the cache directory includes a cache directory entry corresponding to the address, determining whether the cache directory entry is invalid. The method also includes, if the cache entry is invalid, determining whether the cache directory entry includes an indication that the data corresponding to the memory address contains zero data. If the cache directory entry includes the indication, the method also includes returning the zero data in response to the request.

[0010] In some implementations of the method, the indication includes a bit in the cache directory entry. In some implementations, the indication includes a spare state in a state field of the cache directory entry. In some implementations, the indication includes at least one bit in the state field of the cache directory entry. In some implementations, the indication includes a bit in a shared vector field of the cache directory entry. In some implementations, if the cache directory entry is invalid and includes the indication, the coherency management device does not allocate a cache entry to the system corresponding to the request. In some implementations, if the cache directory entry is invalid and includes the indication, the coherency management device returns zero data in response to the request without reading the main memory. In some implementations, the coherency management device includes a coherent slave device, a probe filter device, and / or a snoop filter device. In some implementations, the coherency management device receives a request from a coherent master device. In some implementations, the request includes a non-transient read operation.

[0011] Some implementations provide a coherency management device. The coherency management device includes circuitry that receives a request to write data stored at an address in main memory. The coherency management device also includes circuitry that determines whether the data includes zero data. The coherency management device also includes circuitry that determines whether a cache directory includes a cache directory entry corresponding to the address. The coherency management device also includes circuitry that, if the data includes the zero data and the cache directory includes the cache directory entry, sets a state of the cache directory entry as invalid and sets an indication in the cache directory entry that the data corresponding to the memory address includes zero data. The coherency management device also includes circuitry that, if the cache directory does not include the cache directory entry, creates a cache directory entry, sets a state of the cache directory entry as invalid, and sets an indication in the cache directory entry that the data corresponding to the memory address includes zero data.

[0012] In some implementations, determining by the coherency management device whether the data includes zero data includes determining by the coherency management device whether the data includes only zeros. In some implementations, determining by the coherency management device whether the data includes zero data includes determining by the coherency management device whether the request includes an instruction including an opcode that instructs writing zeros to the address. In some implementations, the indication includes at least one bit in a state field of the cache directory entry. In some implementations, the indication includes a bit in a shared vector field of the cache directory entry. In some implementations, the coherency management device sets the indicator in response to the request without writing to main memory if the data includes zero data. In some implementations, the coherency management device includes a coherent slave device, a probe filter device, and / or a snoop filter device. In some implementations, the coherency management device receives a request from a coherent master device. In some implementations, the request includes a non-transient write operation.

[0013] Some implementations provide a method implemented by a coherency management device for managing cache coherency in a computer system. The method includes receiving a request to write data to an address in main memory, determining whether the data contains zero data, and determining whether a cache directory contains a cache directory entry corresponding to the address. The method also includes, if the data contains zero data and the cache directory contains a cache directory entry, setting a state of the cache directory entry as invalid and setting an indication in the cache directory entry that the data corresponding to the memory address contains zero data. If the cache directory does not contain a cache directory entry, the method also includes creating a cache directory entry and setting the state of the cache directory entry to invalid and setting an indication in the cache directory entry that the data corresponding to the memory address contains zero data.

[0014] In some implementations of the method, determining by the coherency management device whether the data includes zero data includes determining by the coherency management device whether the data includes only zeros. In some implementations, determining by the coherency management device whether the data includes zero data includes determining by the coherency management device whether the request includes an instruction including an opcode that instructs writing zeros to the address. In some implementations, the indication includes at least one bit in a state field of the cache directory entry. In some implementations, the indication includes a bit in a shared vector field of the cache directory entry. In some implementations, the coherency management device sets the indicator in response to the request without writing to main memory if the data includes zero data. In some implementations, the coherency management device includes a coherent slave device, a probe filter device, and / or a snoop filter device. In some implementations, the coherency management device receives a request from a coherent master device. In some implementations, the request includes a non-transient write operation.

[0015] 1 is a block diagram of an example device 100 capable of implementing one or more features of the present disclosure. Device 100 may include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, a memory 104, a storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 may also optionally include an input driver 112 and an output driver 114. It should be understood that device 100 may include additional components not shown in FIG. 1 .

[0016] In various alternatives, processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, each of which may be a CPU or a GPU. In various alternatives, memory 104 is located on the same die as processor 102 or is located separately from processor 102. Memory 104 may include volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0017] The storage devices 106 include fixed or removable storage devices (e.g., hard disk drives, solid state drives, optical disks, flash drives). The input devices 108 include, but are not limited to, a keyboard, a keypad, a touch screen, a touch pad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals). The output devices 110 include, but are not limited to, a display, a speaker, a printer, a haptic feedback device, one or more lights, an antenna, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals).

[0018] The input driver 112 communicates with the processor 102 and the input device 108, allowing the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110, allowing the processor 102 to send output to the output device 110. Note that the input driver 112 and the output driver 114 are optional components, and that the device 100 operates similarly without the input driver 112 and the output driver 114. The output driver 116 includes an accelerated processing device (APD) 116 coupled to a display device 118. The APD accepts computational and graphics rendering commands from the processor 102, processes the computational and graphics rendering commands, and provides pixel output to the display device 118 for display. As described in further detail below, the APD 116 includes one or more parallel processing units that perform computations according to the single instruction, multiple data (SIMD) paradigm. As follows, although various functions are described herein as being performed by or in cooperation with APD 116, in various alternatives, the functions described as being performed by APD 116 are additionally or alternatively performed by other computing devices with similar capabilities that are not driven by a host processor (e.g., processor 102) and that provide graphics output to display device 118. For example, it is contemplated that any processing system that performs processing tasks according to the SIMD paradigm may perform the functions described herein. Alternatively, it is contemplated that computing systems that do not perform processing tasks according to the SIMD paradigm may perform the functions described herein.

[0019] 2 is a block diagram of device 100 illustrating further details related to the execution of processing tasks on APD 116. Processor 102 maintains, in system memory 104, one or more control logic modules for execution by processor 102. The control logic modules include operating system 120, kernel-mode driver 122, and applications 126. These control logic modules control various aspects of the operation of processor 102 and APD 116. For example, operating system 120 communicates directly with hardware and provides an interface to the hardware for other software executing on processor 102. Kernel-mode driver 122 controls the operation of APD 116 by, for example, providing an application programming interface (API) for software (e.g., applications 126) executing on processor 102 to access various features of APD 116. Kernel-mode driver 122 also includes a just-in-time compiler that compiles programs for execution by processing components of APD 116 (such as SIMD unit 138, described in more detail below).

[0020] APD 116 executes commands and programs for selected functions, such as graphics and non-graphics processing, which may be suitable for parallel processing. APD 116 can be used to perform graphics pipeline operations, such as pixel operations, geometric calculations, and to render images to display device 118 based on commands received from processor 102. APD 116 also performs computational operations not directly related to graphics operations, such as video-related operations, physics simulations, computational fluid dynamics, or other tasks, based on commands received from processor 102.

[0021] The APD 116 includes a compute unit 132 that includes one or more SIMD units 138 that perform operations at the request of the processor 102 in parallel according to the SIMD paradigm. The SIMD paradigm allows multiple processing elements to share a single program control flow unit and program counter, thus executing the same program but with different data. In one example, each SIMD unit 138 includes 16 lanes, each of which executes the same instruction simultaneously with other lanes in the SIMD unit 138, but can execute the instruction with different data. Prediction can be used to turn off lanes when not all lanes need to execute a given instruction. Prediction can also be used to execute programs with branching control flow. More specifically, for programs with conditional branches or other instructions whose control flow is based on calculations performed by individual lanes, prediction of lanes corresponding to currently unexecuted control flow paths and serial execution of different control flow paths allows for arbitrary control flow.

[0022] The basic unit of execution on the compute units 132 is the work-item. Each work-item represents a single instantiation of a program executing in parallel on a particular lane. Work-items may execute simultaneously on a single SIMD processing unit 138 as a "wavefront." One or more wavefronts are included in a "workgroup," which includes a collection of work-items designated to execute the same program. A workgroup can be executed by executing each of the wavefronts that make up the workgroup. Alternatively, a wavefront may execute serially on a single SIMD unit 138, or partially or fully in parallel on different SIMD units 138. A wavefront can be thought of as the largest collection of work-items that can execute simultaneously on a single SIMD unit 138. Thus, if commands received from processor 102 indicate that a particular program is to be parallelized to such an extent that the program cannot run simultaneously on a single SIMD unit 138, then the program is divided into wavefronts that are processed in parallel on two or more SIMD units 138, or that are processed serially (or both in parallel and serially, as appropriate) on the same SIMD unit 138. Scheduler 136 performs the operations associated with scheduling the various wavefronts on the different compute units 132 and SIMD units 138.

[0023] The parallelism permitted by the compute units 132 is appropriate for graphics-related operations such as pixel value calculations, vertex transformations, and other graphics operations. Thus, in some examples, the graphics pipeline 134, which receives graphics processing commands from the processor 102, provides computational tasks to the compute units 132 for execution in parallel.

[0024] Computation unit 132 is also used to perform computational tasks that are not related to graphics or that are not performed as part of the "normal" operation of graphics pipeline 134 (e.g., custom operations performed to supplement the processing performed on the operation of graphics pipeline 134). Applications 126 or other software running on processor 102 send programs defining such computational tasks to APD 116 for execution.

[0025] 3 is a block diagram illustrating portions of an exemplary computing system 300. In some examples, computing system 300 is implemented using some or all of device 100 as shown and described with respect to FIGS. 1 and 2. Computing system 300 includes one or more core complexes 310A-310N, an input / output (I / O) interface 320, an interconnect 330, a memory controller 340, and a network interface 350. In other examples, computing system 300 includes additional or different components and / or is configured differently.

[0026] In some implementations, each of the core complexes 310A-310N includes at least one processing device. In this example, at least one of the core complexes 310A-310N includes one or more general-purpose processing devices, such as a CPU. Note that a "core complex" is also sometimes referred to as a "processing node." In some implementations, such a processor is implemented using the processor 102, as shown and described with respect to FIG. 1. In this example, at least one of the core complexes 310A-310N includes one or more data-parallel processors. Examples of data-parallel processors include a GPU, a digital signal processor (DSP), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc. In some implementations, such a processor is implemented using the APD 116, as shown and described with respect to FIG. 1.

[0027] In some implementations, the processor cores in the core complexes 310A-310N include a cache subsystem with one or more levels of cache, and in some implementations, each core complex 310A-310N includes a cache (e.g., a level 3 (L3) cache) that is shared among multiple processor cores.

[0028] Memory controller 340 includes at least one memory controller accessible by core complexes 310A-310N, for example, via interconnect 330. Memory controller 340 includes one or more memory controllers of any suitable type. Each memory controller is coupled to (or otherwise communicates with) and controls access to any number and type of memory devices (not shown). In some implementations, such memory devices include dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and / or any other suitable memory devices. Interconnect 330 includes any computer communication medium suitable for communication between the devices shown in FIG. 3, such as a bus, a data fabric, etc.

[0029] I / O interface 320 includes one or more I / O interfaces (e.g., a Peripheral Component Interconnect (PCI) bus, a PCI Extended (PCI-X), a PCI Express (PCIE) bus, a Gigabit Ethernet (GBE) bus, or a Universal Serial Bus (USB)). In some implementations, I / O interface 320 is implemented using input drivers 112 and / or output drivers 114, as shown and described with respect to FIG. 1 . Various types of peripheral devices can be coupled to I / O interface 320. Such peripheral devices include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc. In some implementations, such peripheral devices are implemented using input devices 108 and / or output devices 118, as shown and described with respect to FIG. 1 .

[0030] FIG. 4 is a block diagram illustrating portions of an exemplary multiprocessor computing system 400. System 400 includes one or more core complexes 410A-410N and one or more memory controllers 440A-440N that communicate with core complexes 410A-410N (e.g., via other components) via an interconnect 430. In some examples, core complexes 410A-410N are coupled to interconnect 430 via coherent masters 415A-415N, and memory controllers 440A-440N are coupled to interconnect 430 via coherent slaves 445A-445N. Interconnect 430 includes any computer communication medium suitable for communication between the devices shown in FIG. 4, such as a bus, a data fabric, etc. While processor system 400 is described with reference to core complexes as an example, it should be noted that in other implementations, a processing node may include a single processor, a processor core not implemented in a core complex, or other suitable processing node.

[0031] Each core complex 410A-410N includes one or more processor cores 412A-412N. Note that in some implementations, processing devices are not organized into core complexes. In some cases, such processors are referred to as such (e.g., processing devices) rather than as core complexes. Each core complex 410A-410N also includes a corresponding cache subsystem 414A-414N. Each cache subsystem 414A-414N includes any suitable number of cache levels and any suitable cache hierarchy structure usable to support caching for the core complex 410A-410N.

[0032] Each core complex 410A-410N communicates with a corresponding coherent master 415A-415N. In some implementations, a coherent master is an agent that handles traffic flowing on an interconnect (e.g., interconnect 430) and manages coherency for connected CPUs or core complexes. In some implementations, to manage coherency, a coherent master receives and processes coherency-related messages and probes and generates and sends coherency-related requests and probes.

[0033] Each core complex 410A-410N communicates with one or more coherent slaves 445A-445N via a corresponding coherent master 415A-415N through interconnect 430. A coherent slave is an agent device that manages coherency for a memory controller (e.g., a memory controller connected to the coherent slave). In some implementations, to manage coherency, a coherent slave receives and processes requests and probes targeted to the corresponding memory controller.

[0034] 4, core complex 410A communicates with coherent master 415A and coherent slave 445A via interconnect 430. Coherent slave (CS) 445A communicates with memory controller (MC) 440A to control memory devices (e.g., main memory DRAM devices).

[0035] Each of the coherent slaves 445A-445N communicates with (or includes) a respective cache directory (CD) 450A-450N. Cache directories are sometimes referred to as "probe filters." Cache directory 450A includes entries for memory addresses or regions of memory accessible via memory controller 440A, for example, that are cached in cache lines (e.g., cache subsystems 414A-414N) of system 400. In some implementations, each core complex 410A-410N communicates with any suitable number of memory controllers 440A-440N via a corresponding coherent master 415A-415N and a corresponding coherent slave 445A-445N.

[0036] A probe comprises a message passed from a coherency point (e.g., a coherent slave) to one or more caches in a computer system, requesting a response indicating whether the cache has a copy of the block of data, and in some implementations indicating the state of the cache in which the cache places the block of data. In some implementations, when a coherent slave receives a memory request targeted to a corresponding memory controller (e.g., a memory request for data stored at an address or region of addresses in memory controlled by a memory controller for which the coherent slave manages coherency), the coherent slave performs a lookup (e.g., a tag-based lookup) in the corresponding cache directory to determine whether the request targets a memory address or region cached in at least one cache line of the cache subsystem.

[0037] In some implementations, the cache directory tracks cache regions, where the region contains multiple cache lines. The size of the tracked region may vary from embodiment to embodiment. Note that a "region" may also be referred to herein as a "page." In some such implementations, when a coherent slave receives a cache request, the coherent slave determines the region covered by the request and performs a lookup of this region in the cache directory. If the lookup results in a hit, the coherent slave sends a probe to the CPU(s) identified in the hit entry. The type of probe generated by the coherent slave depends on the coherency state specified by the hit entry. Note that the examples described herein using line-based tracking can also be implemented using region-based tracking.

[0038] In some implementations, interconnect 430 is connected to and / or communicates with other components not shown in Figure 4 for ease of illustration. For example, in some implementations, interconnect 430 includes a connection to one or more I / O interfaces and / or one or more I / O devices (e.g., corresponding to I / O interface 320 and network interface 350 as shown and described with respect to Figure 3).

[0039] 5 is a block diagram illustrating an example implementation of cache directory 450A shown and described with respect to FIG. Cache directory 450A includes a control unit 500 and an array 510. Array 510 includes any suitable number of directory entries 520 for saving the state of memory addresses or regions. The number of directory entries 520 is sized to achieve an appropriate level of slashing, and thus there are typically some spare directory entries 520 available (e.g., in an invalid state) that can be used opportunistically (i.e., when available) for other purposes, such as zero tracking as described herein.

[0040] In some implementations, each directory entry 520 includes a state field 550, a shared vector field 540, and a tag field 530. In some implementations, the directory entry 520 includes other, different fields and / or is arranged in another field in an appropriate manner. The tag field 530 includes multiple address bits that specify a subset of the bits of a memory address. In some implementations, the tag field 530 includes all the bits of a memory address. In such cases, the field may be referred to as an address field. The bits of the tag field 530 identify a memory location or a group of memory locations within a memory that maps to the directory entry. In this example, the tag field 530 indicates a subset of the address bits of a memory location of a memory (e.g., DRAM) controlled by the memory controller 440A shown and described with reference to FIG. 4.

[0041] The sharing vector 540 includes a number of bits that indicate which caches in the system, if any, have copies of the cache line that maps to the directory entry 520. In this example, the sharing vector 540 indicates which cache subsystems 414A-414N, if any, have cached copies of the cache line that corresponds to the directory entry 520. The state field 550 includes one or more state bits that specify the state of the directory entry 520. In some implementations, the state field 550 may indicate that particular directory entry 520 is in a particular state. An appropriate number of bits is provided to indicate various states. For example, if three states are represented by the state field 550, two bits are used in some implementations. Note that this configuration provides an additional unused bit value for the state field 550. Similarly, if six states are represented by the state field 550, three bits are used in some implementations. Note that this configuration provides an additional two unused bit values ​​for the state field 550.

[0042] FIG. 6 is a flowchart illustrating an example method 600 for zero data compression by a coherence management device, such as a coherent slave or other suitable coherence management device described herein, during a write operation.

[0043] In step 610, the coherence management device receives a request to write data to an address in main memory and determines whether the request is to write zero data. In some implementations, the request includes a non-transient write operation. A non-transient write operation bypasses the cache structure but can be monitored by the coherence management device. In some implementations, the coherence management device determines whether the request is to write zero data based on the payload of the request (e.g., whether the data contained in the payload is all zeros). Note that in other implementations, other types of data can be detected for compression in this manner, such as all payloads or payloads with a predetermined pattern. In some implementations, the coherence management device determines whether the request is to write zero data based on the opcode of the request (e.g., whether the opcode indicates a particular type of write instruction that writes zero data).

[0044] In condition 620, where the request is to write non-zero data, the coherence management device processes the write of the data based on the typical operations of step 630 (e.g., performing a cache directory lookup, cache invalidation, and write to memory as appropriate). If the request is instead to write zero data, the coherence management device determines whether the entries in the associated cache directory contain an entry that corresponds to the memory address. In some implementations, the coherence management device makes this determination by comparing the memory address with a tag field of a cache directory entry that contains the memory address or a portion of the memory address (or communicating the request to a cache directory that performs the comparison).

[0045] In condition 640, if the cache directory contains an entry corresponding to the address, the state of the cache directory entry is set to invalid to indicate that the cached copy of the data (e.g., in cache subsystems 414A-414N) is not valid, and a zero index is set in the cache directory entry in step 660. In some implementations, a spare state is set in the cache directory entry to indicate both invalid and zero data. In condition 640, if the cache directory does not contain an entry corresponding to the address, and a spare, unused, or invalid entry is available in the cache directory, in step 650, the cache directory creates an entry corresponding to the address before setting a zero index (or setting the spare state to indicate both) in step 660 to the cache directory entry whose state is set to invalid. If a spare, unused, or invalid entry is not available in the cache directory, the coherence management device processes the write of the data based on typical operations in step 630 (e.g., performing a cache directory lookup, cache invalidation, and, if necessary, a write to memory).

[0046] The operations of step 660 may be performed in any suitable order, or may be performed simultaneously or in parallel. In some implementations, the indicator of zero data is a bit in a cache directory entry. A bit used to indicate zero data in this manner may be referred to as a "zero detect" or "ZD" bit. In some implementations, the ZD bit is a reclaim bit in the sharing vector of the cache directory entry. For example, an invalid entry implies that none of the cache subsystems 414A-414N has a valid copy of the data corresponding to the cached main memory address. Thus, the sharing vector need not indicate which cache contains a valid copy and can be reclaimed for other indications, such as indicating zero data.

[0047] In some implementations, the zero indication is a spare state set in the state field of the cache directory entry. For example, if the state field includes two bits to represent three states (e.g., cached, invalid, and exclusive), the spare state exists because the two bits can be used to represent four states using binary encoding. Therefore, the spare state can be assigned as a zero-detect or ZD state. In such implementations, the ZD state functions as an invalid state and also indicates that the data corresponding to the address in main memory is zero data.

[0048] In some implementations, the zero data is not written to main memory or is not written to main memory at this time. This may have the advantage of saving memory bandwidth in some cases. In some implementations, data does not need to be written to main memory when the zero data index is set in the corresponding cache directory because the corresponding read operation returns zero data based on an index (e.g., a ZD bit or ZD state) in the cache directory entry. Some implementations that do not write zero data to main memory when the zero data index is set in the corresponding cache directory entry include logic to write zero data to main memory when the cache directory entry is evicted.

[0049] Similarly, in some implementations, zero data is not cached (e.g., not allocated to any of the cache subsystems 414A-414N). In such implementations, zero data is not cached because the cache entry is set to invalid and / or set to a ZD state, allowing the zero data to be returned without having to fetch the data from any cache or main memory. This can have the advantage of conserving bus bandwidth by not requiring a probe request to the cache to fetch the data on a read request before returning the data in response to the read request.

[0050] FIG. 7 is a flowchart illustrating an example method 700 for zero data compression by a coherence management device, such as a coherent slave or other suitable coherence management device, during a read operation.

[0051] In step 710, the coherence management device receives a request to read data from an address in main memory, and the coherence management device determines whether an entry in an associated cache directory contains an entry corresponding to the memory address. In some implementations, the coherence management device makes this determination by comparing the memory address with a tag field of a cache directory entry that contains the memory address or a portion of the memory address (or by communicating the request to a cache directory that performs the comparison). In some implementations, the request includes a non-transient read operation. A non-transient read operation bypasses the cache structure but can be monitored by the coherence management device.

[0052] In condition 720 where the cache directory does not contain an entry corresponding to the address, the coherence management device processes the read of the data based on typical operations (e.g., performs a cache directory lookup and reads from the cache or main memory as needed) in step 730. Alternatively, in condition 720 where the cache directory does contain an entry corresponding to the address, the coherence management device determines whether the entry is invalid (e.g., has a status field indicating an invalid or ZD state).

[0053] In the condition 740 where the cache entry is not invalid, the coherence management device processes the read of the data based on typical operations in step 730. Alternatively, in the condition 740 where the cache entry is invalid, the coherence management device determines whether the directory entry includes an indication that the data read from the address in main memory contains zero data (e.g., includes a ZD bit or ZD state).

[0054] In the condition 750 where the cache entry does not include an indication that the data being read contains zero data, the coherence management device processes the read of the data based on typical operations in step 730. Alternatively, in the condition 750 where the cache entry includes an indication that the data read from the address in main memory contains zero data, the coherence management device returns zero data in response to the request to read the data (step 760).

[0055] In some implementations, the zero data is not read from main memory or a cache; rather, a coherence management device (e.g., a coherent slave) returns zero data in response to a read request based on an indication in a cache directory entry (e.g., a ZD bit or ZD state), which may have the advantage of saving memory bandwidth in some cases.

[0056] Similarly, in some implementations, zero data is not cached (e.g., not allocated to any of the cache subsystems 414A-414N). In such implementations, zero data is not cached because the cache entry is set to invalid and / or set to the ZD state, allowing the zero data to be returned by the coherency management device (such as a coherent slave) without having to fetch the data from any cache or main memory. This can have the advantage of saving bus bandwidth by not requiring a probe request to the cache to fetch the data before returning the data in response to a read request.

[0057] It should be understood that many variations are possible based on the disclosure herein, and although features and elements have been described above in particular combinations, each feature or element can be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0058] The various functional units illustrated in the figures and / or described herein (including, but not limited to, processor 102, input driver 112, input device 108, output driver 114, output device 110, accelerated processing device 116, scheduler 136, graphics processing pipeline 134, computation unit 132, and SIMD unit 138) may be implemented as a general-purpose computer, processor, or processor core, or as a program, software, or firmware stored in a non-transitory computer-readable storage medium or another medium and executable by the general-purpose computer, processor, or processor core. The provided methods may be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, by way of example, a general-purpose processor, a special-purpose processor, a conventional processor, a digital signal processor (DSP), multiple microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) circuit, other types of integrated circuits (ICs), and / or state machines. Such a processor may be fabricated by configuring a manufacturing process with the results of processing hardware description language (HDL) instructions or other intermediate data, including netlists (such as instructions that may be stored on a computer-readable medium). The results of such processing may be a maskwork used in a semiconductor manufacturing process to produce a processor that implements features of the present disclosure.

[0059] The methods or flow charts provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. 1. A coherency management device, comprising: a circuit configured to receive a request to read data stored at an address in the main memory; circuitry configured to determine whether a cache directory contains a cache directory entry corresponding to the address; circuitry configured to determine, if the cache directory contains the cache directory entry corresponding to the address, whether the cache directory entry is invalid; a circuit configured to determine, if the cache directory entry is invalid, whether the cache directory entry includes an indication that the data corresponding to the address includes zero data; and circuitry configured to return zero data in response to the request if the cache directory entry includes the index. Coherency management device.

2. the indication includes a bit in the cache directory entry, a spare state in a status field of the cache directory entry, a bit in a status field of the cache directory entry, and / or a bit in a shared vector field of the cache directory entry; The coherency management device of claim 1 .

3. the coherency management device is configured to return the zero data in response to the request without reading the main memory if the cache directory entry is invalid and includes the indication. The coherency management device of claim 1 .

4. the coherency management device comprises a coherent slave device, a probe filter device, and / or a snoop filter device; The coherency management device of claim 1 .

5. the coherency management device receives the request from a coherent master device; The coherency management device of claim 1 .

6. the request includes a non-transient read operation; The coherency management device of claim 1 .

7. 1. A method for managing cache coherence in a computer system, comprising: receiving a request from a coherency management device to read data stored at an address in main memory; the coherency management device determining whether a cache directory contains a cache directory entry corresponding to the address; If the cache directory contains the cache directory entry corresponding to the address, determining whether the cache directory entry is invalid; If the cache directory entry is invalid, determining whether the cache directory entry includes an indication that the data corresponding to the address includes zero data; returning zero data in response to the request if the cache directory entry includes the index. method.

8. the indication includes a bit in the cache directory entry, a spare state in a status field of the cache directory entry, a bit in a status field of the cache directory entry, and / or a bit in a shared vector field of the cache directory entry; The method of claim 7.

9. the coherency management device returning the zero data in response to the request without reading the main memory if the cache directory entry is invalid and includes the indicator. The method of claim 7.

10. the coherency management device receives the request from a coherent master device; The method of claim 7.

11. the request includes a non-transient read operation; The method of claim 7.

12. 1. A coherency management device, comprising: a circuit configured to receive a request to write data to an address in the main memory; a circuit configured to determine whether the data includes zero data; a circuit configured to determine whether a cache directory contains a cache directory entry corresponding to the address; circuitry configured, if the data contains zero data and the cache directory contains the cache directory entry, to set a state of the cache directory entry to invalid and to set an indication in the cache directory entry that the data corresponding to the address contains zero data; and circuitry configured to, if the cache directory does not contain the cache directory entry, create the cache directory entry, set a state of the cache directory entry to invalid, and set an indication in the cache directory entry that the data corresponding to the address contains zero data. Coherency management device.

13. the coherency management device determining whether the data includes zero data includes the coherency management device determining whether the data includes only zeros, and / or the coherency management device determining whether the request includes an instruction including an opcode instructing writing zero to the address. The coherency management device of claim 12.

14. the indication includes at least one bit of a status field of the cache directory entry, a spare state of a status field of the cache directory entry, a bit of a status field of the cache directory entry, and / or a bit of a shared vector field of the cache directory entry; The coherency management device of claim 12.

15. the coherency management device is configured to set the indicator in response to the request without writing to the main memory if the data includes zero data. The coherency management device of claim 12.

16. the coherency management device includes a coherent slave device, a probe filter device, and / or a snoop filter device; The coherency management device of claim 12.

17. the coherency management device receives the request from a coherent master device; The coherency management device of claim 12.

18. the request includes a non-transient write operation. The coherency management device of claim 12.

19. 1. A method for managing cache coherence in a computer system, comprising: receiving a request by a coherency management device to write data to an address in main memory; the coherency management device determining whether the data includes zero data; the coherency management device determining whether a cache directory contains a cache directory entry corresponding to the address; If the data contains zero data and the cache directory contains the cache directory entry, setting a state of the cache directory entry to invalid and setting an indication in the cache directory entry that the data corresponding to the address contains zero data; if the cache directory does not contain the cache directory entry, creating the cache directory entry, setting a state of the cache directory entry to invalid, and setting an indication in the cache directory entry that data corresponding to the address contains zero data; method.

20. the coherency management device determining whether the data includes zero data includes the coherency management device determining whether the data includes only zeros, and / or the coherency management device determining whether the request includes an instruction including an opcode instructing writing zero to the address.

20. The method of claim 19.

21. the indication includes at least one bit of a status field of the cache directory entry, a spare state of a status field of the cache directory entry, a bit of a status field of the cache directory entry, and / or a bit of a shared vector field of the cache directory entry; 20. The method of claim 19.

22. the coherency management device sets the index in response to the request without writing to the main memory if the data includes zero data.

20. The method of claim 19.

23. the coherency management device includes a coherent slave device, a probe filter device, and / or a snoop filter device; 20. The method of claim 19.

24. the coherency management device receives the request from a coherent master device; 20. The method of claim 19.

25. the request includes a non-transient write operation.

20. The method of claim 19.

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