Signaling maximum transform size and residual coding method

Abstract

This disclosure provides systems and methods for signaling a maximum transform size and a residual coding method. According to certain disclosed embodiments, the method includes receiving a bitstream including a picture set, determining a value of a coding tree block size according to the received bitstream, and determining whether to signal a flag indicating a maximum transform size for luma samples based on the value of the coding tree block size.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This disclosure claims priority to U.S. Provisional Patent Application No. 62 / 980,117, filed February 21, 2020, which is incorporated herein by reference in its entirety.

[0002] Technical Field FIELD OF THE DISCLOSURE

[0002] The present disclosure relates generally to video processing, and more particularly to a method and apparatus for signaling maximum transform size and residual coding method. [Background technology]

[0003] background

[0003] A video is a series of still pictures (or "frames") that capture visual information. To reduce storage memory and transmission bandwidth, a video may be compressed before storage or transmission and decompressed before display. The compression process is usually called encoding, and the decompression process is usually called decoding. There are various video coding formats that use standardized video coding techniques, most commonly based on prediction, transform, quantization, entropy coding, and in-loop filtering. Video coding standards, such as the High Efficiency Video Coding (HEVC) / H.265 standard, the Versatile Video Coding (VVC) / H.266 standard, and the AVS standard, that specify specific video coding formats are developed by standardization organizations. As increasingly advanced video coding techniques are adopted into video standards, the coding efficiency of new video coding standards becomes increasingly higher. Summary of the Invention [Means for solving the problem]

[0004] Disclosure Overview

[0004] Embodiments of the present disclosure provide a method and apparatus for signaling a maximum transform size. In some example embodiments, the method includes receiving a bitstream including a picture set, determining a value of a coding tree block size according to the received bitstream, and determining whether to signal a flag indicating a maximum transform size for luma samples based on the value of the coding tree block size.

[0005]

[0005] The device includes a memory that stores an instruction set and one or more processors, and the one or more processors are configured to execute the instruction set to cause the device to receive a bitstream that includes a picture set, determine a value of a coding tree block size according to the received bitstream, and determine whether to signal a flag indicating a maximum transform size for luma samples based on the value of the coding tree block size.

[0006]

[0006] An embodiment of the present disclosure further provides a non-transitory computer-readable medium storing an instruction set, the instruction set being executable by at least one processor of the computer to cause the computer to perform a method for signaling a maximum transform size, the method including receiving a bitstream including a picture set, determining a value of a coding tree block size according to the received bitstream, and determining whether to signal a flag indicating a maximum transform size for luma samples based on the value of the coding tree block size.

[0007]

[0007] Embodiments of the present disclosure also provide a method and apparatus for signaling a residual coding method. In some example embodiments, the method includes receiving a bitstream including a picture set, determining, according to the received bitstream, a value of a first flag indicating whether a transform skip mode is enabled, and determining, based on the value of the first flag, whether to signal a second flag indicating a residual coding method.

[0008]

[0008] The apparatus includes a memory that stores an instruction set and one or more processors, and the one or more processors are configured to execute the instruction set to cause the apparatus to receive a bitstream including a picture set, determine, according to the received bitstream, the value of a first flag indicating whether a transform skip mode is enabled, and determine, based on the value of the first flag, whether to signal a second flag indicating a residual coding method.

[0009]

[0009] An embodiment of the present disclosure further provides a non-transitory computer-readable medium storing an instruction set, the instruction set being executable by at least one processor of the computer to cause the computer to perform a method of signaling a residual encoding method, the method including receiving a bitstream including a picture set; determining, according to the received bitstream, a value of a first flag indicating whether a transform skip mode is enabled; and determining, based on the value of the first flag, whether to signal a second flag indicating the residual encoding method.

[0010] BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments and various aspects of the present disclosure are set forth in the following detailed description and accompanying drawings, in which various features are not drawn to scale. [Brief explanation of the drawings]

[0011] [Figure 1]

[0011] FIG. 1 is a schematic diagram illustrating the structure of an example video sequence, consistent with some embodiments of the present disclosure. [Figure 2A]

[0012] FIG. 1 is a schematic diagram illustrating an example encoding process of a hybrid video coding system, consistent with some embodiments of the present disclosure. [Figure 2B]

[0013] FIG. 2 is a schematic diagram illustrating another example encoding process of a hybrid video coding system, consistent with some embodiments of the present disclosure. [Figure 3A]

[0014] FIG. 2 is a schematic diagram illustrating an example decoding process of a hybrid video coding system, consistent with some embodiments of the present disclosure. [Figure 3B]

[0015] FIG. 10 is a schematic diagram illustrating another example decoding process of a hybrid video coding system, consistent with some embodiments of the present disclosure. [Figure 4]

[0016] 1 is a block diagram of an exemplary apparatus for encoding or decoding video consistent with some embodiments of the present disclosure. [Figure 5A]

[0017] 1 is an exemplary method for signaling a maximum transform size, consistent with certain embodiments of the present disclosure. [Figure 5B]

[0018] 1 is an exemplary method for signaling a maximum transform size, consistent with certain embodiments of the present disclosure. [Figure 6A]

[0019] 1 is an exemplary method for signaling a residual coding method, consistent with some embodiments of this disclosure. [Figure 6B]

[0020] 1 is an exemplary method for signaling a residual coding method, consistent with some embodiments of this disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] Detailed Description

[0021] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description will refer to the accompanying drawings, in which like numbers in different drawings represent the same or similar elements unless otherwise stated. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the present invention. Instead, they are merely examples of apparatus and methods consistent with aspects related to the present invention as set forth in the appended claims. Certain aspects of the present disclosure are described in more detail below. In the event of a conflict with incorporated terms and / or definitions, the terms and definitions provided herein will control.

[0013]

[0022] The ITU-T Video Coding Expert Group (VCEG) and the ISO / IEC Moving Picture Expert Group (MPEG) Joint Video Experts Team (JVET) are currently developing the Versatile Video Coding (VVC) / H.266 standard. The VVC standard aims to double the compression efficiency of its predecessor, the High Efficiency Video Coding (HEVC) / H.265 standard. In other words, the goal of VVC is to achieve the same subjective quality as HEVC / H.265 but with half the bandwidth.

[0014]

[0023] To achieve the same subjective quality as HEVC / H.265 at half the bandwidth, JVET has developed technology that exceeds HEVC using the JEM (joint exploration model) reference software. As the coding technology has been incorporated into JEM, JEM has achieved significantly higher coding performance than HEVC.

[0015]

[0024] The VVC standard is a recent development and continues to add more coding techniques that provide better compression performance. VVC is based on the same hybrid video coding system that has been used in modern video compression standards such as HEVC, H.264 / AVC, MPEG2, and H.263.

[0016]

[0025] Video is a series of still pictures (or "frames") arranged in time sequence to preserve visual information. A video capture device (e.g., a camera) can be used to capture and store these pictures in time sequence, and a video playback device (e.g., a television, a computer, a smartphone, a tablet computer, a video player, or any end-user terminal with a display capability) can be used to display such pictures in time sequence. In some applications, such as for surveillance, conference hosting, or live broadcasting, the video capture device can transmit the captured video in real time to a video playback device (e.g., a computer with a monitor).

[0017]

[0026] To reduce the storage space and transmission bandwidth required for such applications, video may be compressed before storage and transmission and decompressed before display. Compression and decompression may be performed by software executed by a processor (e.g., a general-purpose computer processor) or dedicated hardware. The compression module is commonly referred to as an "encoder," and the decompression module is commonly referred to as a "decoder." Encoders and decoders may be collectively referred to as a "codec." The encoders and decoders may be implemented as any of a variety of suitable hardware, software, or combinations thereof. For example, hardware implementations of encoders and decoders may include circuitry such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, or any combination thereof. Software implementations of encoders and decoders may include program code, computer-executable instructions, firmware, or any suitable computer-implemented algorithm or process fixed on a computer-readable medium. Video compression and decompression may be performed by various algorithms or standards, such as MPEG-1, MPEG-2, MPEG-4, and the H.26x family. In some applications, a codec can reconstruct video from a first encoding standard and recompress the reconstructed video using a second encoding standard, in which case the codec is sometimes called a "transcoder."

[0018]

[0027] A video encoding process can identify and retain useful information that can be used for picture reconstruction and ignore information that is not important for reconstruction. If the ignored, unimportant information cannot be perfectly reconstructed, such an encoding process may be called "lossy." Otherwise, it may be called "lossless." Most encoding processes are lossy; this is a tradeoff to reduce the required storage space and transmission bandwidth.

[0019]

[0028] Useful information about the picture being encoded (called the "current picture") includes changes relative to a reference picture (e.g., a previously encoded and reconstructed picture). Such changes may include pixel position changes, luminance changes, or color changes, of which position changes are the most important. Position changes of pixels representing an object may reflect the object's motion between the reference picture and the current picture.

[0020]

[0029] A picture that is coded without referencing another picture (i.e., it is its own reference picture) is called an "I-picture." A picture that is coded using a previous picture as a reference picture is called a "P-picture." A picture that is coded using both a previous picture and a future picture as reference pictures (i.e., the referencing is "bidirectional") is called a "B-picture."

[0021]

[0030] 1 illustrates the structure of an example video sequence 100 according to some embodiments of the present disclosure. The video sequence 100 may be live video or captured and archived video. The video 100 may be actual video, computer-generated video (e.g., computer game video), or a combination thereof (e.g., actual video with augmented reality effects). The video sequence 100 may be input from a video capture device (e.g., a camera), a video archive containing previously captured video (e.g., video files saved on a storage device), or a video feed interface (e.g., a video broadcast transceiver) for receiving video from a video content provider.

[0022]

[0031] As shown in FIG. 1, video sequence 100 may include a series of pictures arranged temporally along a timeline, including pictures 102, 104, 106, and 108. Pictures 102-106 are consecutive, with more pictures between pictures 106 and 108. In FIG. 1, picture 102 is an I-picture, and its reference picture is picture 102 itself. Picture 104 is a P-picture, and its reference picture is picture 102, as indicated by the arrow. Picture 106 is a B-picture, and its reference pictures are pictures 104 and 108, as indicated by the arrows. In some embodiments, the reference picture for a picture (e.g., picture 104) may not be immediately preceding or following that picture. For example, picture 104's reference picture may be a picture preceding picture 102. It should be noted that the reference pictures of pictures 102-106 are merely examples, and this disclosure does not limit the reference picture embodiment to the example shown in FIG.

[0023]

[0032] Typically, video codecs do not encode or decode an entire picture at once due to the computational complexity of such a task. Rather, they may divide a picture into basic segments and encode or decode the picture segment by segment. Such basic segments are referred to as basic processing units ("BPUs") in this disclosure. For example, structure 110 in FIG. 1 illustrates an example structure for a picture (e.g., any of pictures 102-108) in video sequence 100. In structure 110, the picture is divided into 4x4 basic processing units, the boundaries of which are indicated by dashed lines. In some embodiments, a basic processing unit may be called a "macroblock" in some video coding standards (e.g., the MPEG family, H.261, H.263, or H.264 / AVC) or a "coding tree unit" (CTU) in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing unit may have a variable size of a picture, such as 128x128, 64x64, 32x32, 16x16, 4x8, 16x32, or any shape and size of pixels. The size and shape of the basic processing unit may be selected for each picture based on a balance between coding efficiency and the level of detail to be maintained in the basic processing unit. A CTU is the largest block unit and may contain as many as 128x128 luma samples (plus corresponding chroma samples, depending on the chroma format). The CTUs can be further partitioned into coding units (CUs) using a quadtree, a binary tree, a ternary tree, or a combination thereof.

[0024]

[0033] A basic processing unit may be a logical unit that may include a collection of different types of video data stored in computer memory (e.g., in a video frame buffer). For example, a basic processing unit for a color picture may include a luma component (Y) representing achromatic lightness information, one or more chroma components (e.g., Cb and Cr) representing color information, and related syntax elements (where the luma and chroma components may have the same size basic processing unit). The luma and chroma components are sometimes referred to as "coding tree blocks" (CTBs) in some video coding standards (e.g., H.265 / HEVC or H.266 / VVC). Any operation performed on a basic processing unit can be repeated for each of its luma and chroma components.

[0025]

[0034] Video coding has multiple stages of operation, examples of which are shown in FIGS. 2A-2B and 3A-3B. At each stage, the size of the basic processing unit may still be too large to process and therefore may be further divided into segments referred to as "basic processing subunits" in this disclosure. In some embodiments, the basic processing subunits may be referred to as "blocks" in some video coding standards (e.g., MPEG family, H.261, H.263, or H.264 / AVC) or as "coding units" (CUs) in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing subunits may have the same or smaller size as the basic processing units. Similar to basic processing units, basic processing subunits are also logical units that may contain a collection of different types of video data (e.g., Y, Cb, Cr, and related syntax elements) stored in computer memory (e.g., in a video frame buffer). Any operation performed on a basic processing sub-unit can be repeated on each of its luma and chroma components. Note that such division can be performed to further levels depending on the processing needs. Note also that different stages can use different schemes to divide the basic processing units.

[0026]

[0035] For example, in a mode decision stage (an example of which is shown in FIG. 2B ), the encoder may decide which prediction mode (e.g., intra-picture prediction or inter-picture prediction) to use for a basic processing unit, which may be too large to make such a decision. The encoder may divide the basic processing unit into multiple basic processing sub-units (e.g., CUs in the case of H.265 / HEVC or H.266 / VVC) and decide the prediction type for each individual basic processing sub-unit.

[0027]

[0036] As another example, in the prediction stage (an example of which is shown in FIGS. 2A-2B), the encoder can perform prediction operations at the level of basic processing subunits (e.g., CUs). However, in some cases, the basic processing subunits may still be too large to process. The encoder can further divide the basic processing subunits into smaller segments (e.g., called "prediction blocks" or "PBs" in H.265 / HEVC or H.266 / VVC), and perform prediction operations at the level of the segments.

[0028]

[0037] As another example, in the transform stage (an example of which is shown in FIGS. 2A-2B), the encoder can perform transform operations on residual basic processing subunits (e.g., CUs). However, in some cases, the basic processing subunits may still be too large to process. The encoder can further divide the basic processing subunits into smaller segments (e.g., called "transform blocks" or "TBs" in H.265 / HEVC or H.266 / VVC), and perform transform operations at the segment level. Note that the division scheme of the same basic processing subunit may be different in the prediction stage and the transform stage. For example, in H.265 / HEVC or H.266 / VVC, the prediction blocks and transform blocks of the same CU may have different sizes and numbers.

[0029]

[0038] 1, the basic processing unit 112 is further divided into 3x3 basic processing sub-units, the boundaries of which are indicated by dotted lines. Different basic processing units of the same picture may be divided into basic processing sub-units in different schemes.

[0030]

[0039] In some implementations, to provide parallel processing capabilities and error resilience for video encoding and decoding, a picture may be divided into multiple regions for processing, such that for each region of a picture, the encoding or decoding process can be independent of information from any other region of the picture. That is, each region of a picture can be processed independently. In this way, a codec can process different regions of a picture in parallel, thus improving coding efficiency. Also, if data for one region is corrupted during processing or lost during network transmission, the codec can accurately encode or decode other regions of the same picture without relying on the corrupted or lost data, thus providing error resilience. In some video coding standards, a picture may be divided into different types of regions. For example, H.265 / HEVC and H.266 / VVC provide two region types: "slice" and "tile." It should also be noted that different pictures in video sequence 100 may have different partition schemes for dividing the picture into regions.

[0031]

[0040] 1, structure 110 is divided into three regions 114, 116, and 118, the boundaries of which are shown as solid lines within structure 110. Region 114 includes four basic processing units. Regions 116 and 118 each include six basic processing units. It should be noted that the basic processing units, basic processing subunits, and regions of structure 110 in FIG. 1 are merely examples, and the present disclosure is not limited to these embodiments.

[0032]

[0041] FIG. 2A illustrates a schematic diagram of an example encoding process 200A consistent with embodiments of the present disclosure. For example, encoding process 200A can be performed by an encoder. As shown in FIG. 2A, the encoder can encode a video sequence 202 into a video bitstream 228 according to process 200A. Similar to video sequence 100 of FIG. 1, video sequence 202 can include a set of pictures (referred to as "original pictures") arranged in a temporal order. Similar to structure 110 of FIG. 1, each original picture in video sequence 202 can be divided by the encoder into elementary processing units, elementary processing sub-units, or regions for processing. In some embodiments, the encoder can perform process 200A at the elementary processing unit level for each original picture in video sequence 202. For example, the encoder can perform process 200A in an iterative manner, in which case the encoder can encode one elementary processing unit in one iteration of process 200A. In some embodiments, the encoder may perform process 200A in parallel for a region of each original picture in video sequence 202 (eg, regions 114-118).

[0033]

[0042] In FIG. 2A , an encoder may send a fundamental processing unit (referred to as an “original BPU”) of an original picture of a video sequence 202 to a prediction stage 204 to generate prediction data 206 and a prediction BPU 208. The encoder may generate a residual BPU 210 by subtracting the prediction BPU 208 from the original BPU. The encoder may send the residual BPU 210 to a transform stage 212 and a quantization stage 214 to generate quantized transform coefficients 216. The encoder may send the prediction data 206 and the quantized transform coefficients 216 to a binary encoding stage 226 to generate a video bitstream 228. Components 202, 204, 206, 208, 210, 212, 214, 216, 226, and 228 may be referred to as the “forward path.” During process 200A, after quantization stage 214, the encoder may send quantized transform coefficients 216 to an inverse quantization stage 218 and an inverse transform stage 220 to generate a reconstructed residual BPU 222. The encoder may generate a prediction reference 224 to be used in prediction stage 204 for the next iteration of process 200A by adding reconstructed residual BPU 222 to prediction BPU 208. Components 218, 220, 222, and 224 of process 200A may be referred to as a "reconstruction path." The reconstruction path may be used to ensure that both the encoder and decoder use the same reference data for prediction.

[0034]

[0043] The encoder may perform process 200A iteratively to encode each original BPU of the original picture (in the forward path) and to generate a prediction reference 224 for encoding the next original BPU of the original picture (in the reconstruction path). After encoding all original BPUs of the original picture, the encoder may proceed to encode the next picture in the video sequence 202.

[0035]

[0044] Referring to process 200A, an encoder may receive a video sequence 202 generated by a video capture device (e.g., a camera). As used herein, the term "receive" may refer to any action of receiving, inputting, obtaining, retrieving, acquiring, reading, accessing, or any manner of inputting data.

[0036]

[0045] In the prediction stage 204, in the current iteration, the encoder may receive the original BPU and a prediction reference 224 and perform a prediction operation to generate predicted data 206 and a predicted BPU 208. The prediction reference 224 may be generated from the reconstruction path of a previous iteration of the process 200A. The purpose of the prediction stage 204 is to reduce information redundancy by extracting predicted data 206, which can be used to reconstruct the original BPU as a predicted BPU 208 from the predicted data 206 and the prediction reference 224.

[0037]

[0046] Ideally, predicted BPU 208 would be identical to the original BPU. However, due to non-ideal prediction and reconstruction operations, predicted BPU 208 typically differs slightly from the original BPU. To record such differences, after generating predicted BPU 208, the encoder can subtract it from the original BPU to generate residual BPU 210. For example, the encoder can subtract pixel values ​​(e.g., grayscale or RGB values) of predicted BPU 208 from corresponding pixel values ​​of the original BPU. Each pixel of residual BPU 210 may have a residual value as a result of such subtraction between corresponding pixels of the original BPU and predicted BPU 208. Compared to the original BPU, predicted data 206 and residual BPU 210 may have fewer bits, but can be used to reconstruct the original BPU without significant quality degradation. Thus, the original BPU is compressed.

[0038]

[0047] To further compress the residual BPU 210, in the transform stage 212, the encoder can reduce spatial redundancy in the residual BPU 210 by decomposing it into a set of two-dimensional "basis patterns," each associated with a "transform coefficient." The basis patterns may have the same size (e.g., the size of the residual BPU 210). Each basis pattern may represent a variation frequency (e.g., frequency of brightness variation) component of the residual BPU 210. No basis pattern can be reconstructed from any combination (e.g., linear combination) of the other basis patterns. That is, this decomposition can decompose the variation of the residual BPU 210 into the frequency domain. Such a decomposition is analogous to a discrete Fourier transform of a function, where the basis patterns are analogous to basis functions (e.g., trigonometric functions) of the discrete Fourier transform, and the transform coefficients are analogous to the coefficients associated with the basis functions.

[0039]

[0048] Different transform algorithms can use different basis patterns. For example, various transform algorithms, such as a discrete cosine transform or a discrete sine transform, can be used in transform stage 212. The transform in transform stage 212 is reversible. That is, the encoder can reconstruct residual BPU 210 by inverting the transform (called the "inverse transform"). For example, to reconstruct pixels of residual BPU 210, the inverse transform may multiply the values ​​of corresponding pixels of the basis pattern by their associated coefficients and add these products to generate a weighted sum. For video coding standards, both the encoder and decoder can use the same transform algorithm (and therefore the same basis pattern). Therefore, the encoder can record only the transform coefficients, and the decoder can reconstruct residual BPU 210 from the transform coefficients without receiving the basis pattern from the encoder. Compared to residual BPU 210, the transform coefficients may have fewer bits, but they can be used to reconstruct residual BPU 210 without significant quality degradation. Therefore, the residual BPU 210 is further compressed.

[0040]

[0049] The encoder can further compress the transform coefficients in the quantization stage 214. In the transform process, different basis patterns may represent different variation frequencies (e.g., brightness variation frequencies). Because the human eye is generally good at recognizing low-frequency variations, the encoder can ignore high-frequency variation information without significant quality degradation in decoding. For example, in the quantization stage 214, the encoder can generate quantized transform coefficients 216 by dividing each transform coefficient by an integer value (called a "quantization parameter") and rounding the quotient to the nearest integer. After such an operation, some transform coefficients of high-frequency basis patterns may be converted to zero, and transform coefficients of low-frequency basis patterns may be converted to smaller integers. The encoder can ignore zero-valued quantized transform coefficients 216, thereby further compressing the transform coefficients. The quantization process is also reversible, where the quantized transform coefficients 216 can be reconstructed into transform coefficients through the inverse operation of quantization (called "dequantization").

[0041]

[0050] Because the encoder ignores such division remainders in rounding operations, the quantization stage 214 may be lossy. In general, the quantization stage 214 may contribute the most information loss in the process 200A. The greater the information loss, the fewer bits the quantized transform coefficients 216 may require. To achieve different levels of information loss, the encoder may use different values ​​of the quantization parameter or other parameters of the quantization process.

[0042]

[0051] In the binary encoding stage 226, the encoder may encode the prediction data 206 and the quantized transform coefficients 216 using a binary encoding technique, such as entropy coding, variable length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or other lossless or lossy compression algorithm. In some embodiments, in addition to the prediction data 206 and the quantized transform coefficients 216, the encoder may encode other information in the binary encoding stage 226, such as the prediction mode used in the prediction stage 204, parameters of the prediction operation, the transform type in the transform stage 212, parameters of the quantization process (e.g., quantization parameters), or encoder control parameters (e.g., bitrate control parameters). The encoder may use the output data of the binary encoding stage 226 to generate a video bitstream 228. In some embodiments, the video bitstream 228 may be further packetized for network transmission.

[0043]

[0052] Referring to the reconstruction path of process 200A, in an inverse quantization stage 218, the encoder may generate reconstructed transform coefficients by performing inverse quantization on the quantized transform coefficients 216. In an inverse transform stage 220, the encoder may generate a reconstructed residual BPU 222 based on the reconstructed transform coefficients. The encoder may generate a prediction reference 224 to be used in the next iteration of process 200A by adding the reconstructed residual BPU 222 to a prediction BPU 208.

[0044]

[0053] It should be noted that other variations of process 200A may be used to encode video sequence 202. In some embodiments, the stages of process 200A may be performed by an encoder in a different order. In some embodiments, one or more stages of process 200A may be combined into a single stage. In some embodiments, a single stage of process 200A may be split into multiple stages. For example, transform stage 212 and quantization stage 214 may be combined into a single stage. In some embodiments, process 200A may include additional stages. In some embodiments, process 200A may omit one or more stages of FIG. 2A.

[0045]

[0054] 2B shows a schematic diagram of another example encoding process 200B consistent with embodiments of the present disclosure. Process 200B may be modified from process 200A. For example, process 200B may be used by an encoder compliant with a hybrid video coding standard (e.g., the H.26x family). Compared to process 200A, the forward path of process 200B further includes a mode decision stage 230 and divides the prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044. The reconstruction path of process 200B further includes a loop filter stage 232 and a buffer 234.

[0046]

[0055] In general, prediction techniques can be categorized into two types: spatial prediction and temporal prediction. Spatial prediction (e.g., intra-picture prediction or "intra-prediction") can predict a current BPU by using pixels from one or more already-encoded neighboring BPUs within the same picture. That is, the prediction reference 224 in spatial prediction may include neighboring BPUs. Spatial prediction can reduce the inherent spatial redundancy of a picture. Temporal prediction (e.g., inter-picture prediction or "inter-prediction") can predict a current BPU by using regions from one or more already-encoded pictures. That is, the prediction reference 224 in temporal prediction may include encoded pictures. Temporal prediction can reduce the inherent temporal redundancy of a picture.

[0047]

[0056] Referring to process 200B, in the forward path, the encoder performs prediction operations in a spatial prediction stage 2042 and a temporal prediction stage 2044. For example, in the spatial prediction stage 2042, the encoder may perform intra prediction. With respect to the original BPU of a picture being encoded, the prediction reference 224 may include one or more neighboring BPUs encoded (in the forward path) and reconstructed (in the reconstruction path) within the same picture. The encoder may generate the predicted BPU 208 by extrapolating the neighboring BPUs. Extrapolation techniques may include, for example, linear extrapolation or interpolation, polynomial extrapolation or interpolation, etc. In some embodiments, the encoder may perform extrapolation at the pixel level, for example, by extrapolating the value of the corresponding pixel for each pixel of the predicted BPU 208. The neighboring BPUs used for extrapolation may be located relative to the original BPU from various directions, such as vertically (e.g., above the original BPU), horizontally (e.g., to the left of the original BPU), diagonally (e.g., bottom-left, bottom-right, top-left, or top-right of the original BPU), or any direction defined in the used video coding standard. In the case of intra prediction, the prediction data 206 may include, for example, the locations (e.g., coordinates) of the used neighboring BPUs, the sizes of the used neighboring BPUs, parameters of the extrapolation, or the orientations of the used neighboring BPUs relative to the original BPU.

[0048]

[0057] As another example, in the temporal prediction stage 2044, the encoder may perform inter-prediction. With respect to the original BPU of the current picture, the prediction reference 224 may include one or more pictures (called "reference pictures") that have been encoded (in the forward path) and reconstructed (in the reconstruction path). In some embodiments, the reference pictures may be encoded and reconstructed for each BPU. For example, the encoder may generate a reconstructed BPU by adding the reconstructed residual BPU 222 to the predicted BPU 208. Once all the reconstructed BPUs of the same picture are generated, the encoder may generate the reconstructed picture as the reference picture. The encoder may perform a "motion estimation" operation to search for a matching region within a certain range (called a "search window") of the reference picture. The location of the search window in the reference picture may be determined based on the location of the original BPU in the current picture. For example, the search window may be centered at a location in the reference picture that has the same coordinates as the original BPU of the current picture, or may extend outward by a predetermined distance. When the encoder identifies a region within the search window that is similar to the original BPU (e.g., using a pel-recursive algorithm or a block-matching algorithm), the encoder can determine such a region as a matching region. The matching region may have different dimensions (e.g., smaller, equal, larger, or a different shape) than the original BPU. Because the reference picture and the current picture are temporally separated in a timeline (e.g., as shown in FIG. 1), the matching region can be considered to "move" to the location of the original BPU over time. The encoder may record the direction and distance of such movement as a "motion vector." If multiple reference pictures are used (e.g., like picture 106 in FIG. 1), the encoder can search for a matching region and determine its associated motion vector for each reference picture. In some embodiments, the encoder can assign weights to pixel values ​​of the matching region in each matching reference picture.

[0049]

[0058] Motion estimation can be used to identify various types of motion, such as, for example, translation, rotation, or zooming. In the case of inter prediction, the prediction data 206 may include, for example, the location (e.g., coordinates) of the matching region, a motion vector associated with the matching region, the number of reference pictures, or weights associated with the reference pictures.

[0050]

[0059] To generate the predicted BPU 208, the encoder may perform a "motion compensation" operation. Motion compensation can be used to reconstruct the predicted BPU 208 based on the prediction data 206 (e.g., motion vectors) and the prediction reference 224. For example, the encoder can move the matching region of the reference picture according to a motion vector that allows the encoder to predict the original BPU of the current picture. If multiple reference pictures are used (e.g., as in picture 106 of FIG. 1), the encoder can move the matching region of the reference picture according to each motion vector and average the pixel values ​​of the matching region. In some embodiments, if the encoder assigns weights to the pixel values ​​of the matching region of each matching reference picture, the encoder can add a weighted sum of the pixel values ​​of the moved matching region.

[0051]

[0060] In some embodiments, inter-prediction may be unidirectional or bidirectional. Unidirectional inter-prediction may use one or more reference pictures in the same temporal direction relative to the current picture. For example, picture 104 in FIG. 1 is a unidirectional inter-predicted picture in which a reference picture (e.g., picture 102) precedes picture 104. Bidirectional inter-prediction may use one or more reference pictures in both temporal directions relative to the current picture. For example, picture 106 in FIG. 1 is a bidirectional inter-predicted picture in which reference pictures (e.g., pictures 104 and 108) are in both temporal directions relative to picture 104.

[0052]

[0061]

[0033] Referring further to the forward path of process 200B, after spatial prediction 2042 and temporal prediction stage 2044, in mode decision stage 230, the encoder can select a prediction mode (e.g., intra-prediction or inter-prediction) for the current iteration of process 200B. For example, the encoder can perform a rate-distortion optimization technique, in which the encoder can select a prediction mode to minimize the value of a cost function depending on the bitrates of candidate prediction modes and the distortion of reconstructed reference pictures under the candidate prediction modes. Depending on the selected prediction mode, the encoder can generate a corresponding predicted BPU 208 and predicted data 206.

[0053]

[0062] In the reconstruction path of process 200B, if an intra prediction mode was selected in the forward path, after generating the prediction reference 224 (e.g., the current BPU encoded and reconstructed within the current picture), the encoder can send the prediction reference 224 directly to the spatial prediction stage 2042 for later use (e.g., for extrapolation of the next BPU of the current picture). If an inter prediction mode was selected in the forward path, after generating the prediction reference 224 (e.g., the current picture with all BPUs encoded and reconstructed), the encoder can send the prediction reference 224 to the loop filter stage 232, where the encoder can apply a loop filter to the prediction reference 224 to reduce or eliminate distortions (e.g., blocking artifacts) introduced by inter prediction. The encoder can apply various loop filter techniques in the loop filter stage 232, such as deblocking, sample adaptive offset, or adaptive loop filter. The loop-filtered reference picture may be stored in a buffer 234 (or a "decoded picture buffer") for later use (e.g., to be used as an inter-prediction reference picture for a future picture of the video sequence 202). The encoder may store one or more reference pictures in the buffer 234 for use in the temporal prediction stage 2044. In some embodiments, the encoder may encode loop filter parameters (e.g., loop filter strength) in the binary encoding stage 226 along with the quantized transform coefficients 216, the prediction data 206, and other information.

[0054]

[0063] FIG. 3A shows a schematic diagram of an example decoding process 300A consistent with embodiments of the present disclosure. Process 300A may be a decompression process corresponding to compression process 200A of FIG. 2A. In some embodiments, process 300A may be similar to the reconstruction path of process 200A. A decoder can follow process 300A to decode video bitstream 228 into video stream 304. Video stream 304 may be very similar to video sequence 202. However, due to information loss in the compression and decompression processes (e.g., quantization stage 214 of FIGS. 2A-2B), video stream 304 is generally not identical to video sequence 202. Similar to processes 200A and 200B of FIGS. 2A-2B, a decoder can perform process 300A at the level of a basic processing unit (BPU) for each picture encoded in video bitstream 228. For example, the decoder may perform process 300A in an iterative manner, where the decoder can decode one fundamental processing unit in one iteration of process 300A. In some embodiments, the decoder may perform process 300A in parallel for a region (e.g., region 114-118) of each picture encoded in video bitstream 228.

[0055]

[0064] In FIG. 3A , a decoder may send a portion of a video bitstream 228 associated with an encoded picture's fundamental processing unit (referred to as an "encoding BPU") to a binary decoding stage 302. In the binary decoding stage 302, the decoder may decode the portion into prediction data 206 and quantized transform coefficients 216. The decoder may send the quantized transform coefficients 216 to an inverse quantization stage 218 and an inverse transform stage 220 to generate a reconstructed residual BPU 222. The decoder may send the prediction data 206 to a prediction stage 204 to generate a prediction BPU 208. The decoder may generate a prediction reference 224 by adding the reconstructed residual BPU 222 to the prediction BPU 208. In some embodiments, the prediction reference 224 may be stored in a buffer (e.g., a decoded picture buffer in computer memory). The decoder may send the prediction reference 224 to the prediction stage 204 for performing a prediction operation in a next iteration of the process 300A.

[0056]

[0065] The decoder may iteratively perform process 300A to decode each encoded BPU of the encoded picture and generate a prediction reference 224 for encoding the next encoded BPU of the encoded picture. After decoding all encoded BPUs of the encoded picture, the decoder may output the picture to video stream 304 for display and proceed to decoding the next encoded picture in video bitstream 228.

[0057]

[0066] In binary decoding stage 302, the decoder may perform the inverse operation of the binary encoding technique used by the encoder (e.g., entropy coding, variable length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or other lossless compression algorithm). In some embodiments, in addition to prediction data 206 and quantized transform coefficients 216, the decoder may decode other information in binary decoding stage 302, such as, for example, a prediction mode, parameters of the prediction operation, a transform type, parameters of the quantization process (e.g., quantization parameters), or encoder control parameters (e.g., bitrate control parameters). In some embodiments, if video bitstream 228 is transmitted in packets over a network, the decoder may depacketize video bitstream 228 before sending it to binary decoding stage 302.

[0058]

[0067] 3B shows a schematic diagram of another example decoding process 300B consistent with embodiments of the present disclosure. Process 300B may be modified from process 300A. For example, process 300B may be used by a decoder compliant with a hybrid video coding standard (e.g., the H.26x family). Compared to process 300A, process 300B further divides prediction stage 204 into spatial prediction stage 2042 and temporal prediction stage 2044, and further includes loop filter stage 232 and buffer 234.

[0059]

[0068] In process 300B, for an encoding basic processing unit (referred to as the “current BPU”) of an encoded picture being decoded (referred to as the “current picture”), prediction data 206 decoded by the decoder from binary decoding stage 302 may include various types of data depending on which prediction mode was used by the encoder to encode the current BPU. For example, if intra prediction was used by the encoder to encode the current BPU, prediction data 206 may include a prediction mode indicator (e.g., a flag value) indicating intra prediction, parameters of the intra prediction operation, etc. The parameters of the intra prediction operation may include, for example, the location (e.g., coordinates) of one or more neighboring BPUs used as references, the size of the neighboring BPUs, parameters of extrapolation, or the direction of the neighboring BPUs relative to the original BPU. As another example, if inter prediction was used by the encoder to encode the current BPU, prediction data 206 may include a prediction mode indicator (e.g., a flag value) indicating inter prediction, parameters of the inter prediction operation, etc. Parameters for the inter-prediction operation may include, for example, the number of reference pictures associated with the current BPU, weights associated with each of the reference pictures, the locations (e.g., coordinates) of one or more matching regions in each reference picture, or one or more motion vectors associated with each of the matching regions.

[0060]

[0069] Based on the prediction mode indicator, the decoder can decide whether to perform spatial prediction (e.g., intra prediction) in spatial prediction stage 2042 or temporal prediction (e.g., inter prediction) in temporal prediction stage 2044. Details of performing such spatial or temporal prediction are shown in FIG. 2B and will not be repeated below. After performing such spatial or temporal prediction, the decoder can generate a prediction BPU 208. The decoder can generate a prediction reference 224 by adding the prediction BPU 208 and the reconstructed residual BPU 222, as shown in FIG. 3A.

[0061]

[0070] In process 300B, the decoder may send the prediction reference 224 to the spatial prediction stage 2042 or the temporal prediction stage 2044 for performing a prediction operation in the next iteration of process 300B. For example, if the current BPU is decoded using intra prediction in the spatial prediction stage 2042, after generating the prediction reference 224 (e.g., the decoded current BPU), the decoder may send the prediction reference 224 directly to the spatial prediction stage 2042 for later use (e.g., for extrapolation of the next BPU of the current picture). If the current BPU is decoded using inter prediction in the temporal prediction stage 2044, after generating the prediction reference 224 (e.g., the reference picture from which all BPUs are decoded), the encoder may send the prediction reference 224 to the loop filter stage 232 to reduce or eliminate distortion (e.g., blocking artifacts). The decoder may apply a loop filter to the prediction reference 224 in the manner shown in FIG. 2B . The loop filtered reference picture may be stored in a buffer 234 (e.g., a decoded picture buffer in computer memory) for later use (e.g., to be used as an inter-prediction reference picture for a future encoded picture in the video bitstream 228). The decoder may store one or more reference pictures in the buffer 234 for use in the temporal prediction stage 2044. In some embodiments, if the prediction mode indicator in the prediction data 206 indicates that inter-prediction was used to encode the current BPU, the prediction data may further include parameters of the loop filter (e.g., loop filter strength).

[0062]

[0071] FIG. 4 is a block diagram of an example apparatus 400 for encoding or decoding video, according to an embodiment of the present disclosure. As shown in FIG. 4, the apparatus 400 may include a processor 402. When the processor 402 executes the instructions described herein, the apparatus 400 can become a dedicated machine for video encoding or decoding. The processor 402 may be any type of circuitry capable of manipulating or processing information. For example, the processor 402 may include any combination of several central processing units (i.e., "CPUs"), graphics processing units (i.e., "GPUs"), neural processing units ("NPUs"), microcontroller units ("MCUs"), optical processors, programmable logic controllers, microcontrollers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), general-purpose array logic (GALs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), systems-on-chips (SoCs), or application-specific integrated circuits (ASICs), etc. In some embodiments, processor 402 may be a set of processors grouped as a single logical component. For example, as shown in FIG. 4, processor 402 may include multiple processors, including processor 402a, processor 402b, and processor 402n.

[0063]

[0072] The device 400 may also include memory 404 configured to store data (e.g., an instruction set, computer code, intermediate data, etc.). For example, as shown in FIG. 4, the stored data may include program instructions (e.g., program instructions for implementing stages of processes 200A, 200B, 300A, or 300B) and data for processing (e.g., video sequence 202, video bitstream 228, or video stream 304). The processor 402 may access the program instructions and the data for processing (e.g., via bus 410) and execute the program instructions to perform operations or manipulations on the data for processing. The memory 404 may include a high-speed random access storage device or a non-volatile storage device. In some embodiments, the memory 404 may include any combination of random access memory (RAM), read-only memory (ROM), optical disks, magnetic disks, hard drives, solid-state drives, flash drives, security digital (SD) cards, memory sticks, CompactFlash (CF) cards, etc. Memory 404 may also be a collection of memories (not shown in FIG. 4) grouped as a single logical component.

[0064]

[0073] Bus 410 may be a communication device that transfers data between components within apparatus 400, such as an internal bus (e.g., a CPU memory bus) or an external bus (e.g., a Universal Serial Bus port, a Peripheral Component Interconnect Express port).

[0065]

[0074] For the sake of clarity and simplicity, in this disclosure, the processor 402 and other data processing circuitry will be collectively referred to as "data processing circuitry." The data processing circuitry may be implemented entirely as hardware, or as a combination of software, hardware, or firmware. Furthermore, the data processing circuitry may be a single, independent module, or may be fully or partially integrated with any other components of the device 400.

[0066]

[0075] The device 400 may further include a network interface 406 to provide wired or wireless communication with a network (e.g., the Internet, an intranet, a local area network, or a mobile communications network, etc.) In some embodiments, the network interface 406 may include any combination of several network interface controllers (NICs), radio frequency (RF) modules, transponders, transceivers, modems, routers, gateways, wired network adapters, wireless network adapters, Bluetooth adapters, infrared adapters, near field communication ("NFC") adapters, cellular network chips, etc.

[0067]

[0076] In some embodiments, apparatus 400 may optionally further include a peripheral interface 408 to provide connection to one or more peripheral devices. As shown in Figure 4, the peripheral devices may include, but are not limited to, a cursor control device (e.g., a mouse, a touchpad, or a touchscreen), a keyboard, a display (e.g., a cathode ray tube display, a liquid crystal display, or a light emitting diode display), or a video input device (e.g., a camera, or an input interface coupled to a video archive), etc.

[0068]

[0077] It should be noted that a video codec (e.g., a codec performing process 200A, 200B, 300A, or 300B) may be implemented as any combination of software or hardware modules within apparatus 400. For example, some or all stages of process 200A, 200B, 300A, or 300B may be implemented as one or more software modules of apparatus 400, such as program instructions that may be loaded into memory 404. As another example, some or all stages of process 200A, 200B, 300A, or 300B may be implemented as one or more hardware modules of apparatus 400, such as dedicated data processing circuits (e.g., FPGAs, ASICs, or NPUs).

[0069]

[0078] In a first reference embodiment, the sequence parameter set (SPS) syntax element sps_max_luma_transform_size_64_flag is signaled to specify the maximum transform size. sps_max_luma_transform_size_64_flag equal to 1 specifies that the maximum transform size in luma samples is equal to 64. sps_max_luma_transform_size_64_flag equal to 0 specifies that the maximum transform size in luma samples is equal to 32. In the first reference embodiment, sps_max_luma_transform_size_64_flag is always signaled regardless of the value of the coding tree block size (CtbSizeY). However, sps_max_luma_transform_size_64_flag is not required to be signaled and can be inferred to be 0 if CtbSizeY is less than 64.

[0070]

[0079] Also, in the second reference embodiment, a slice-level residual coding selection method can be used. The following are example semantics of slice_ts_residual_coding_disabled_flag:

number

[0071]

[0080] In the second reference embodiment, slice_ts_residual_coding_disabled_flag is always signaled. However, since slice_ts_residual_coding_disabled_flag specifies the residual coding method for transform skip mode, if transform skip mode is disabled at the SPS level, it is not required to signal slice_ts_residual_coding_disabled_flag in the slice header and it can be inferred to be 0.

[0072]

[0081] The present disclosure provides methods and apparatus for reducing the coding redundancy described above.

[0073]

[0082] 5A is an example method for signaling a maximum transform size consistent with some embodiments of the present disclosure. In some embodiments, method 500A may be performed by an encoder, a decoder, and one or more software or hardware components of an apparatus (e.g., apparatus 400 of FIG. 4). For example, a processor (e.g., processor 402 of FIG. 4) may perform method 500A. In some embodiments, method 500A may be implemented by a computer program product embodied in a computer-readable medium that includes computer-executable instructions, such as program code, for execution by a computer (e.g., apparatus 400 of FIG. 4). The method may include the following steps:

[0074]

[0083] In step 501, a bitstream including a picture set is received. As explained, a basic processing unit of a color picture may include a luma component (Y) representing achromatic lightness information, one or more chroma components (e.g., Cb and Cr) representing color information, and related syntax elements (here, the luma and chroma components may have basic processing units of the same size). The luma and chroma components are sometimes referred to as "coding tree blocks" ("CTBs") in some video coding standards (e.g., H.265 / HEVC or H.266 / VVC). Any operation performed on a basic processing unit can be repeated on each of its luma and chroma components.

[0075]

[0084] In step 503, a value of the coding tree block size is determined according to the received bitstream. The value of the coding tree block size is signaled in the received bitstream. For example, the value of CtbSizeY in the exemplary semantics is determined.

[0076]

[0085] In step 505, whether to signal a flag indicating the maximum transform size for luma samples is determined based on the value of the coding tree block size. For example, the sequence parameter set (SPS) syntax element sps_max_luma_transform_size_64_flag can be used to specify the maximum transform size. sps_max_luma_transform_size_64_flag equal to 1 specifies that the maximum transform size in luma samples is equal to 64. sps_max_luma_transform_size_64_flag equal to 0 specifies that the maximum transform size in luma samples is equal to 32.

[0077]

[0086] In some embodiments, step 505 may include steps 505-1, 505-3, and 505-5 as shown in FIG. 5B.

[0078]

[0087] In step 505-1, it is determined whether the value of the coding tree block size satisfies the first condition or the second condition according to the received bitstream.

[0079]

[0088] In some embodiments, the first condition may be that the value is greater than 32, and the second condition may be that the value is less than or equal to 32. Satisfaction of the first condition may result in signaling a flag indicating the maximum transform size. Otherwise, satisfaction of the second condition may result in a decision not to signal a flag.

[0080]

[0089] At step 505-3, in response to the coding tree block size value being greater than 32, a flag is signaled.

[0081]

[0090] An example SPS syntax is set forth below in Table 1. In some example embodiments for signaling a maximum transform size, sps_max_luma_transform_size_64_flag is signaled only if CtbSizeY is greater than 32. Table 1 shows a portion of an example SPS syntax table for signaling a maximum transform size according to some disclosed embodiments. In Table 1, the row with "if (CtbSizeY > 32)" indicates a modification to the syntax used in the first reference embodiment. As explained, in the first reference embodiment, sps_max_luma_transform_size_64_flag is always signaled regardless of the value of the coding tree block size (CtbSizeY). In contrast, according to some embodiments of the present disclosure, sps_max_luma_transform_size_64_flag is not necessarily signaled. As shown in Table 1, the signaling of sps_max_luma_transform_size_64_flag is conditioned on CtbSizeY.

[0082] [Table 1]

[0083]

[0091] At step 505-5, in response to the coding tree block size value being less than or equal to 32, it is determined that no flag is signaled.

[0084]

[0092] In a signaling method consistent with Table 1, the value of sps_max_luma_transform_size_64_flag is inferred to be 0 if CtbSizeY is not greater than 32. The semantics for deriving CtbSizeY are as follows:

number

[0085]

[0093] In some embodiments, the first and second conditions may be different from those described above. In the following example, the first condition may be that the value is not equal to 32, and the second condition may be that the value is equal to 32.

[0086]

[0094] In an alternative step 505-3, a flag is signaled in response to the value of the coding tree block size not being equal to 32.

[0087]

[0095] In an alternative step 505-5, in response to the coding tree block size value being equal to 32, it is determined that no flag is signaled.

[0088]

[0096] An example syntax is described as follows: The proposed syntax changes shown in Table 1 can also be implemented using the condition "CtbSizeY != 32" instead of "CtbSizeY > 32". In this case, if CtbSizeY is not equal to 32, sps_max_luma_transform_size_64_flag is signaled, and if CtbSizeY is equal to 32, sps_max_luma_transform_size_64_flag is inferred to be 0.

[0089]

[0097] An example syntax is described as follows: The proposed syntax changes shown in Table 1 can also be implemented using the condition "CtbSizeY >= 64" instead of "CtbSizeY > 32". In this case, if CtbSizeY is greater than or equal to 64, sps_max_luma_transform_size_64_flag is signaled, and if CtbSizeY is less than 64, sps_max_luma_transform_size_64_flag is inferred to be 0. That is, sps_max_luma_transform_size_64_flag is only required to be signaled if CtbSizeY is greater than 32. If CtbSizeY is not greater than 32, sps_max_luma_transform_size_64_flag is not signaled and is inferred to be equal to 0. Alternatively, sps_max_luma_transform_size_64_flag is signaled only if CtbSizeY is greater than or equal to 64. If CtbSizeY is less than 64, sps_max_luma_transform_size_64_flag is not signaled and is inferred to be equal to 0.

[0090]

[0098] In some example embodiments for signaling the maximum transform size, instead of using CtbSizeY, the signaling of sps_max_luma_transform_size_64_flag is conditioned on sps_log2_ctu_size_minus5. As noted above, sps_log2_ctu_size_minus5+5 specifies the luma coding tree block size of each coding tree unit (CTU). A CTU may contain as many as 128x128 luma samples (plus corresponding chroma samples, depending on the chroma format). Table 2 below shows a portion of an example SPS syntax table for signaling the maximum transform size according to some disclosed embodiments. In Table 2, the row with "if (sps_log2_ctu_size_minus5 > 0)" indicates a modification to the syntax used in the first reference embodiment. As explained, in the first reference embodiment, sps_max_luma_transform_size_64_flag is always signaled regardless of the value of the coding tree block size (e.g., CtbSizeY). In contrast, according to some embodiments of the present disclosure, sps_max_luma_transform_size_64_flag is not necessarily signaled. As shown in Table 2, in some embodiments, the signaling of sps_max_luma_transform_size_64_flag is conditioned on sps_log2_ctu_size_minus5. As shown in Table 2, if sps_log2_ctu_size_minus5 is greater than 0, sps_max_luma_transform_size_64_flag is signaled, and if sps_log2_ctu_size_minus5 is 0, the value of sps_max_luma_transform_size_64_flag is inferred.

[0091]

[0099] In some embodiments, the coding tree block size value in step 501 may further include a value associated with the luma coding tree block size of each coding tree unit. The value (e.g., sps_log2_ctu_size_minus5) may be determined according to the received bitstream.

[0092]

[0100] In some embodiments, in an alternative step of step 505-1, it may be determined whether the value associated with the luma coding tree block size of each coding tree unit satisfies a first condition (e.g., greater than 0) or a second condition (e.g., equal to 0).

[0093]

[0101] In some embodiments, in an alternative step of step 505-3, a flag (e.g., sps_max_luma_transform_size_64_flag) is signaled in response to the value associated with the luma coding tree block size of each coding tree unit satisfying a first condition (e.g., greater than 0).

[0094]

[0102] In some embodiments, in an alternative step of step 505-5, it is determined that a flag (e.g., sps_max_luma_transform_size_64_flag) is not signaled in response to the value associated with the luma coding tree block size of each coding tree unit satisfying a second condition (e.g., equal to 0).

[0095] [Table 2]

[0096]

[0103] The above syntax changes shown in Table 2 can also be implemented using the condition "sps_log2_ctu_size_minus5 != 0". In this case, if sps_log2_ctu_size_minus5 is not equal to 0, sps_max_luma_transform_size_64_flag is signaled, and if sps_log2_ctu_size_minus5 is equal to 0, sps_max_luma_transform_size_64_flag is inferred to be 0.

[0097]

[0104] In some embodiments, the first condition may be that a value (e.g., sps_log2_ctu_size_minus5) is not equal to 0, as shown in the example above. In an alternative to step 505-3, a flag (e.g., sps_max_luma_transform_size_64_flag) is signaled in response to the value associated with the luma coding tree block size of each coding tree unit satisfying the first condition (e.g., sps_log2_ctu_size_minus5 != 0).

[0098]

[0105] 6 is an example method for signaling a residual coding method consistent with some embodiments of the present disclosure. In some embodiments, method 600A may be performed by one or more software or hardware components of an encoder, a decoder, and an apparatus (e.g., apparatus 400 of FIG. 4). For example, a processor (e.g., processor 402 of FIG. 4) may perform method 600A. In some embodiments, method 600A may be implemented by a computer program product embodied in a computer-readable medium that includes computer-executable instructions, such as program code, for execution by a computer (e.g., apparatus 400 of FIG. 4). The method may include the following steps:

[0099]

[0106] In step 601, a bitstream including a picture set is received. As explained, a basic processing unit of a color picture may include a luma component (Y) representing achromatic lightness information, one or more chroma components (e.g., Cb and Cr) representing color information, and related syntax elements (here, the luma and chroma components may have basic processing units of the same size). The luma and chroma components are sometimes referred to as "coding tree blocks" ("CTBs") in some video coding standards (e.g., H.265 / HEVC or H.266 / VVC). Any operation performed on a basic processing unit can be repeated on each of its luma and chroma components.

[0100]

[0107] In step 603, a value of a first flag indicating whether a transform skip mode is enabled is determined according to the received bitstream. The value of the first flag may be signaled in the received bitstream. For example, the value of sps_transform_skip_enabled_flag may be determined.

[0101]

[0108] In step 605, it is determined whether to signal a second flag indicating a residual coding method based on the value of the first flag. For example, the second flag may be a slice-level residual coding flag. The slice-level residual coding flag slice_ts_residual_coding_disabled_flag specifies the residual coding method of the transform skip mode. If the transform skip mode is disabled at the SPS level, it is not necessary to signal slice_ts_residual_coding_disabled_flag in the slice header and it can be inferred to be 0.

[0102]

[0109] In some embodiments, step 605 may include steps 605-1, 605-3, and 605-5 as shown in FIG. 6B.

[0103]

[0110] In step 605-1, it is determined whether the value of the first flag satisfies the first condition or the second condition according to the received bitstream.

[0104]

[0111] In some embodiments, the first condition may be that the value of the first flag is 1, and the second condition may be that the value of the first flag is 0. Satisfaction of the first condition may result in signaling the second flag. Otherwise, satisfaction of the second condition may result in a decision not to signal the second flag.

[0105]

[0112] At step 605-3, in response to the first flag (eg, sps_transform_skip_enabled_flag) having a value of one, a second flag (eg, slice_ts_residual_coding_disabled_flag) is signaled.

[0106]

[0113] In step 605-5, in response to the first flag (eg, sps_transform_skip_enabled_flag) having a value of 0, it is determined that the second flag (eg, slice_ts_residual_coding_disabled_flag) is not signaled.

[0107]

[0114] An exemplary SPS syntax is set forth below in Table 3. In some exemplary embodiments for signaling the residual coding method, if sps_transform_skip_enabled_flag is equal to 1, then the slice-level residual coding flag slice_ts_residual_coding_disabled_flag is signaled. If sps_transform_skip_enabled_flag is equal to 0, then the value of slice_ts_residual_coding_disabled_flag is inferred to be 0. The semantics of sps_transform_skip_enabled_flag are as follows:

number

[0108]

[0115] Table 3 shows a portion of an example slice header syntax table for signaling a residual coding method according to some disclosed embodiments. In Table 3, the row with "if (sps_transform_skip_enabled_flag)" indicates a modification to the syntax used in the second reference embodiment. As explained, in the second reference embodiment, slice_ts_residual_coding_disabled_flag is always signaled. In contrast, according to some embodiments of the present disclosure, slice_ts_residual_coding_disabled_flag is not necessarily signaled. Only if sps_transform_skip_enabled_flag is equal to 1, slice_ts_residual_coding_disabled_flag is signaled. If sps_transform_skip_enabled_flag is equal to 0, slice_ts_residual_coding_disabled_flag is not signaled and is inferred to be equal to 0. The proposed modifications can reduce the signaling overhead at the slice header level.

[0109] [Table 3]

[0110]

[0116] In some embodiments, a non-transitory computer-readable storage medium containing instructions is also provided, which can be executed by a device (such as the disclosed encoders and decoders) to perform the above-described methods. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape or other magnetic data storage media, CD-ROMs, other optical data storage media, any physical media with a pattern of holes, RAM, PROMs, and EPROMs, FLASH-EPROMs or other flash memories, NVRAMs, caches, registers, other memory chips or cartridges, and networked versions of the above. A device may include one or more processors (CPUs), input / output interfaces, network interfaces, and / or memory.

[0111]

[0117] The disclosed embodiments can be further described using the following clauses. 1. Receiving a bitstream including a picture set; determining a value of a coding tree block size according to the received bitstream; determining whether to signal a flag indicating a maximum transform size for luma samples based on the value of the coding tree block size; A video data signaling method comprising: 2. Deciding whether to signal a flag signaling a flag in response to the coding tree block size value being greater than 32; or determining, in response to the value of the coding tree block size being less than or equal to 32, that a flag is not signaled; 2. The method according to clause 1, comprising: 3. Determining whether to signal a flag signaling a flag in response to the coding tree block size value not being equal to 32; or determining, in response to the coding tree block size value being equal to 32, that a flag is not signaled; 2. The method according to clause 1, comprising: 4. The method of clause 1, wherein the coding tree block size value further includes a value associated with a luma coding tree block size of the coding tree unit. 5. Determining whether to signal a flag signaling a flag in response to the value associated with the luma coding tree block size being greater than 0; or determining, in response to the value associated with the luma coding tree block size being equal to 0, that the flag is not signaled; 5. The method according to clause 4, comprising: 6. Determining whether to signal a flag signaling a flag in response to the value associated with the luma coding tree block size not being equal to 0; or determining, in response to the value associated with the luma coding tree block size being equal to 0, that the flag is not signaled; 5. The method according to clause 4, comprising: 7. The method of any one of clauses 1 to 6, wherein the flag indicates that the maximum transform size is 64. 8. Receiving a bitstream including a picture set; determining a value of a first flag indicating whether a transform skip mode is enabled according to the received bitstream; determining whether to signal a second flag indicating a residual coding method based on the value of the first flag; A video data signaling method comprising: 9. Determining whether to signal a second flag includes: signaling a second flag in response to the first flag having a value of one; or determining, in response to the first flag having a value of 0, that the second flag is not signaled; 9. The method according to clause 8, comprising: 10. A first flag is signaled in a sequence parameter set; and 10. The method according to clauses 8 and 9, wherein the second flag is signaled in a slice header. 11. A memory for storing an instruction set; and one or more processors, the one or more processors executing an instruction set to receiving a bitstream including a picture set; determining a value of a coding tree block size according to the received bitstream; determining whether to signal a flag indicating a maximum transform size for luma samples based on the value of the coding tree block size; a video data signaling device configured to cause a device to: 12. In determining whether to signal a flag, one or more processors execute a set of instructions to: signaling a flag in response to the coding tree block size value being greater than 32; or determining, in response to the value of the coding tree block size being less than or equal to 32, that a flag is not signaled; 12. The apparatus of clause 11, further configured to cause the apparatus to: 13. In determining whether to signal a flag, one or more processors execute a set of instructions to: signaling a flag in response to the coding tree block size value not being equal to 32; or determining, in response to the coding tree block size value being equal to 32, that a flag is not signaled; 12. The apparatus of clause 11, further configured to cause the apparatus to: 14. The apparatus of clause 11, wherein the coding tree block size value further includes a value associated with a luma coding tree block size of the coding tree unit. 15. In determining whether to signal a flag, one or more processors execute a set of instructions to: signaling a flag in response to the value associated with the luma coding tree block size being greater than 0; or determining, in response to the value associated with the luma coding tree block size being equal to 0, that the flag is not signaled; 15. The apparatus of clause 14, further configured to cause the apparatus to: 16. In determining whether to signal a flag, one or more processors execute a set of instructions to: signaling a flag in response to the value associated with the luma coding tree block size not being equal to 0; or determining, in response to the value associated with the luma coding tree block size being equal to 0, that the flag is not signaled; 15. The apparatus of clause 14, further configured to cause the apparatus to: 17. The apparatus of any one of clauses 11 to 16, wherein the flag indicates that the maximum transform size is 64. 18. A memory for storing an instruction set; and one or more processors, the one or more processors executing an instruction set to receiving a bitstream including a picture set; determining a value of a first flag indicating whether a transform skip mode is enabled according to the received bitstream; determining whether to signal a second flag indicating a residual coding method based on the value of the first flag; a video data signaling device configured to cause a device to: 19. In determining whether to signal a second flag, one or more processors execute a set of instructions to: signaling a second flag in response to the first flag having a value of one; or determining, in response to the first flag having a value of 0, that the second flag is not signaled; 19. The apparatus of clause 18, further configured to cause the apparatus to: 20. A first flag is signaled in a sequence parameter set; and 20. The apparatus of clause 18 or 19, wherein the second flag is signaled in a slice header. 21. A non-transitory computer-readable medium storing a set of instructions, the set of instructions being executable by at least one processor of a computer to cause the computer to perform a video data signaling method, the method comprising: receiving a bitstream including a picture set; determining a value of a coding tree block size according to the received bitstream; determining whether to signal a flag indicating a maximum transform size for luma samples based on the value of the coding tree block size; 1. A non-transitory computer-readable medium comprising: 22. Determining whether to signal a flag comprises: signaling a flag in response to the coding tree block size value being greater than 32; or determining, in response to the value of the coding tree block size being less than or equal to 32, that a flag is not signaled; 22. The non-transitory computer-readable medium of claim 21, comprising: 23. Determining whether to signal a flag comprises: signaling a flag in response to the coding tree block size value not being equal to 32; or determining, in response to the coding tree block size value being equal to 32, that a flag is not signaled; 22. The non-transitory computer-readable medium of claim 21, comprising: 24. The non-transitory computer-readable medium of clause 21, wherein the coding tree block size value further includes a value associated with a luma coding tree block size of the coding tree unit. 25. Determining whether to signal a flag comprises: signaling a flag in response to the value associated with the luma coding tree block size being greater than 0; or determining, in response to the value associated with the luma coding tree block size being equal to 0, that the flag is not signaled; 25. The non-transitory computer-readable medium of claim 24, comprising: 26. Determining whether to signal a flag comprises: signaling a flag in response to the value associated with the luma coding tree block size not being equal to 0; or determining, in response to the value associated with the luma coding tree block size being equal to 0, that the flag is not signaled; 25. The non-transitory computer-readable medium of claim 24, comprising: 27. The non-transitory computer-readable medium of any one of clauses 21 to 26, wherein a flag indicates that the maximum transform size is 64. 28. A non-transitory computer-readable medium storing a set of instructions, the set of instructions being executable by at least one processor of a computer to cause the computer to perform a video data signaling method, the method comprising: receiving a bitstream including a picture set; determining a value of a first flag indicating whether a transform skip mode is enabled according to the received bitstream; determining whether to signal a second flag indicating a residual coding method based on the value of the first flag; 1. A non-transitory computer-readable medium comprising: 29. Determining whether to signal a second flag includes: signaling a second flag in response to the first flag having a value of one; or determining, in response to the first flag having a value of 0, that the second flag is not signaled; 29. The non-transitory computer-readable medium of clause 28, comprising: 30. A first flag is signaled in a sequence parameter set; and 30. The non-transitory computer-readable medium of clauses 28 and 29, wherein the second flag is signaled in a slice header.

[0112]

[0118] It should be noted that relational terms herein, such as "first" and "second," are used only to distinguish one entity or operation from another, and do not require or imply an actual relationship or ordering between those entities or operations. Also, the words "comprising," "having," "containing," and "including," and other similar forms, are intended to be equivalent in meaning and to be open-ended in that the term or terms following any one of these terms is not an exhaustive list of such term or terms, or limited to only the listed term or terms.

[0113]

[0119] As used herein, unless specifically stated otherwise, the term "or" encompasses all possible combinations unless impracticable. For example, if a database is described as including A or B, the database may include A, or B, or A and B, unless specifically stated otherwise or impracticable. As a second example, if a database is described as including A, B, or C, the database may include A, B, C, A and B, A and C, B and C, or A, B, and C, unless specifically stated otherwise or impracticable.

[0114]

[0120] It is understood that the above embodiments can be implemented by hardware, or software (program code), or a combination of hardware and software. If implemented by software, it can be stored in the above computer-readable medium. The software, when executed by a processor, can perform the disclosed methods. The computing units and other functional units described in this disclosure can be implemented by hardware, or software, or a combination of hardware and software. Those skilled in the art will also understand that more than one of the above modules / units can be integrated into one module / unit, and that each of the above modules / units can be further divided into multiple sub-modules / sub-units.

[0115]

[0121] In the foregoing specification, embodiments have been described with reference to numerous specific details that may vary from implementation to implementation. Certain adaptations and modifications of the described embodiments may be made. Other embodiments may become apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the above specification and examples be considered exemplary only, with the true scope and spirit of the invention being indicated by the following claims. Additionally, the order of steps depicted in the figures is intended for illustrative purposes only and is not intended to be limited to any particular order of steps. Thus, one skilled in the art will recognize that these steps may be performed in different orders while performing the same method.

[0116]

[0122] In the drawings and specification, illustrative embodiments have been disclosed. However, many variations and modifications to these embodiments may be made. Accordingly, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

determining, based on parameters signaled in a sequence parameter set (SPS) of a bitstream, a value for the size of a coding tree block associated with said SPS; determining whether to signal a flag indicating a maximum transform size for luma samples based on the value of the size of the coding tree block; Including, determining whether to signal the flag; signaling the flag in the SPS in response to the value of the size of the coding tree block being greater than 32, wherein a value of the flag is set equal to 1 if a maximum transform size for the luma samples is equal to 64 and is set equal to 0 if the maximum transform size for the luma samples is equal to 32, and the flag is not signaled in the bitstream if the value of the size of the coding tree block is less than or equal to 32.

2. The method of claim 1 , wherein the flags include sps_max_luma_transform_size_64_flag.

3. The method of claim 1 , further comprising encoding the bitstream according to the Versatile Video Coding (VVC) / H.266 standard.

4. The method of claim 1 , wherein the value of the flag is inferred to be equal to 0 if the value of the coding tree block size is less than or equal to 32.

5. The method of claim 1 , wherein the maximum transform size for the luma samples is inferred to be equal to 32 if the value of the coding tree block size is less than or equal to 32.

6. The method of claim 1 , wherein the flag is signaled in a sequence parameter set if the value of the coding tree block size is greater than 32.

7. receiving a bitstream associated with a coding tree block; determining a value for the size of the coding tree block based on parameters signaled in a sequence parameter set (SPS); determining whether the bitstream includes a flag indicating a maximum transform size for luma samples based on the value of the size of the coding tree block; determining the maximum transform size based on a value of the flag in response to the bitstream including the flag, or inferring that the maximum transform size is equal to a predetermined value in response to the bitstream not including the flag; Including, determining the maximum transform size based on the value of the flag; determining a maximum transform size for the luma samples equal to 64 if the value of the flag is equal to 1, or determining a maximum transform size for the luma samples equal to 32 if the value of the flag is equal to 0; A video data decoding method comprising:

8. The method of claim 7 , wherein the flags include sps_max_luma_transform_size_64_flag.

9. The method of claim 7 , wherein the flag is included in the SPS.

10. The method of claim 7, further comprising decoding the bitstream based on the Versatile Video Coding (VVC) / H.266 standard.

11. 8. The method of claim 7, further comprising inferring, in response to the bitstream not including the flag, that the value of the flag is equal to 0.

12. The method of claim 7 , wherein the predetermined value is equal to 32.

13. 1. A method for storing a video bitstream, the method comprising: determining parameters of a sequence parameter set (SPS) associated with a coding tree block; determining a value for the size of the coding tree block based on the parameters; generating a bitstream based on the value of the size of the coding tree block; storing the bitstream in a non-transitory computer-readable storage medium; Including, a value of the flag is equal to 1 if the maximum transform size for the luma samples is equal to 64, or a value of the flag is equal to 0 if the maximum transform size for the luma samples is equal to 32; and the bitstream does not include the flag if the value of the size of the coding tree block is equal to or less than 32.

14. The method of claim 13 , wherein the flags include sps_max_luma_transform_size_64_flag.

15. The method of claim 13, wherein the bitstream is encoded according to the Versatile Video Coding (VVC) / H.266 standard.

16. The method of claim 13 , wherein if the value of the coding tree block size is greater than 32, the flag is signaled in the SPS.

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