Management of read timing in semiconductor devices

Abstract

To provide a system, device, method and circuit for managing read timing in a semiconductor device.SOLUTION: A memory device comprises a memory array configured to store data and a circuit configuration which is connected to the memory array and reads out the stored data from the memory array. The circuit configuration acquires a start address of target data to be read out, on the basis of a read instruction and determines that the start address is within a first address group out of a plurality of address groups. The target data is read out from the memory array on the basis of a fact that each of the address groups is associated with each read rate and the start address is within the first address group.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure is directed to semiconductor devices, for example, read timing in semiconductor devices. [Background technology]

[0002] Semiconductor devices, such as memory devices, are becoming smaller and faster. Many applications require supporting higher read frequencies. However, to ensure successful reads, the read control timing settings need to be adjusted to the worst-case read performance, which may inhibit the use of higher read frequencies for higher read performance. Summary of the Invention

[0003] This disclosure describes methods, devices, systems, and techniques for managing read timing in semiconductor devices, for example, non-volatile memory devices such as flash memory devices.

[0004] One aspect of the disclosure features a semiconductor device including a memory array configured to store data and circuitry coupled to the memory array and configured to read the stored data from the memory array, wherein the circuitry is configured to: obtain, based on a read command, a starting address of target data to be read; determine that the starting address is within a first address group of a plurality of address groups, each of the plurality of address groups being associated with a respective read speed; and read the target data from the memory array based on the starting address being within the first address group.

[0005] In some implementations, each of the plurality of address groups is associated with a respective timing profile of a plurality of different timing profiles, and the circuitry is configured to determine a first timing profile associated with the first address group; and read target data from the memory array according to the first timing profile.

[0006] In some implementations, the different timing profiles are associated with different read speeds, where a first timing profile is associated with a first read speed and a second timing profile of the plurality of timing profiles is associated with a second read speed that is higher than the first read speed.

[0007] In some implementations, the timing profile includes at least one of a duration for activating a word line, a duration for activating a bit line, a duration for sensing one or more data bits from the memory array, or a duration for outputting one or more data bits.

[0008] In some implementations, the target data has a first portion and a second portion contiguous with the first portion, the first portion including a starting address, and the circuitry is configured to read the first portion at a first read rate and to read the second portion at a second read rate that is higher than the first read rate.

[0009] In some implementations, the total length of the first portion of the target data is predetermined.

[0010] In some implementations, the circuitry is configured to receive a clock signal having a clock frequency and to read the target data using the clock signal.

[0011] In some implementations, the first address group includes a set of specific addresses corresponding to a slower read speed than addresses in one or more other address groups, one or more of the specific addresses corresponding to one or more specific memory cells coupled to one or more last data bits of a word line of the memory array.

[0012] In some implementations, the particular addresses within the first group of addresses are fixed or predetermined.

[0013] In some implementations, the circuitry is configured to determine the duration for a particular address in the first address group based on one or more parameters including a clock frequency and a data density of the word line.

[0014] In some implementations, the circuitry includes a memory interface coupled to the memory array, the memory interface configured to receive an input signal for reading target data from the memory array, the input signal including a read command; and to output an output signal including the read target data.

[0015] In some implementations, the circuitry includes an address detector coupled to the memory interface and configured to obtain a starting address of the target data based on the input signal and determine that the starting address is within the first address group.

[0016] In some implementations, the circuit configuration further includes a timing profile controller coupled to the address detector and configured to determine a timing profile for reading the target data based on a signal from the address detector, the signal indicating that the starting address of the target data is within the first address group.

[0017] In some implementations, the memory interface is configured to output an output signal after one or more dummy cycles following the input signal, and the circuitry is configured to determine which group the starting address is in before the one or more dummy cycles begin. The memory interface includes a serial pin configured to perform at least one of receiving an input signal from a bus or outputting an output signal to the bus.

[0018] In some implementations, the memory interface has a plurality of serial input / output (SIO) pins, and the memory interface is configured to receive an input signal from a bus using at least one of the plurality of SIO pins and to output an output signal to the bus using the plurality of SIO pins.

[0019] In some implementations, the read instruction includes a read command and a starting address.

[0020] Another aspect of the disclosure features a system including a memory device and a controller coupled to the memory device and configured to transmit a read command to the memory device. The memory device includes a memory array configured to store data, and circuitry coupled to the memory array and configured to read the stored data from the memory array. The circuitry is configured to: obtain, based on the read command, a starting address of target data to be read; determine that the starting address is within a first address group of a plurality of address groups, each of the plurality of address groups being associated with a respective read speed; read the target data from the memory array based on the starting address being within the first address group; and output the read target data to the controller.

[0021] In some implementations, the target data has a first portion and a second portion contiguous to the first portion, the first portion including a starting address, and the circuitry is configured to read the first portion at a first read rate and to read the second portion at a second read rate that is higher than the first read rate.

[0022] Another aspect of the present disclosure features a method including obtaining a starting address of target data to be read from a memory array; determining that the starting address is within a first address group of a plurality of address groups, each of the plurality of address groups being associated with a respective read speed, the first address group being associated with a first read speed; and reading the target data from the memory array at the first read speed based on the starting address being within the first address group.

[0023] Another aspect of the present disclosure features a semiconductor device including a memory array configured to store data and circuitry coupled to the memory array and configured to read the stored data from the memory array, wherein the circuitry is configured to: obtain, based on a read command, a starting address of target data to be read; determine that the starting address is within a first address group of a plurality of address groups, where each of the plurality of address groups is associated with a respective timing profile of a plurality of different timing profiles; determine a first timing profile associated with the first address group; and read the target data from the memory array in accordance with the first timing profile.

[0024] In some implementations, the different timing profiles are associated with different read speeds, where a first timing profile is associated with a first read speed and a second timing profile of the plurality of timing profiles is associated with a second read speed that is higher than the first read speed.

[0025] In some implementations, the target data has a first portion and a second portion contiguous with the first portion, the first portion including a starting address, the first timing profile has a first timing sub-profile for the first portion of the target data and a second timing sub-profile for the second portion of the target data, the first timing sub-profile corresponding to a first read speed and the second timing sub-profile corresponding to a second read speed.

[0026] In some implementations, the total length of the first portion of the target data is predetermined, or the total time period of the first timing sub-profile is predetermined.

[0027] In some implementations, the circuitry is configured to receive a clock signal having a clock frequency and to read the target data using the clock signal.

[0028] In some implementations, a particular duration in the first timing profile corresponds to a first number of clock cycles of the clock signal, and a corresponding particular duration in the second timing profile corresponds to a second number of clock cycles of the clock signal.

[0029] In some implementations, the time period in the first timing profile is predetermined, and the circuitry is configured to determine the number of clock cycles for the time period based on the clock frequency.

[0030] In some implementations, the first address group has a set of specific addresses corresponding to a slower read speed than addresses in one or more other address groups, one or more of the specific addresses corresponding to one or more specific memory cells coupled to one or more last data bits of a word line of the memory array. In some implementations, the specific addresses in the first address group are fixed.

[0031] In some implementations, the circuitry is configured to determine a particular address within the first address group and / or a duration for a particular address based on one or more parameters including a clock frequency and a data density of the word line.

[0032] In some implementations, the timing profile includes at least one of a duration for activating a word line, a duration for activating a bit line, a duration for sensing one or more data bits from the memory array, or a duration for outputting one or more data bits.

[0033] In some implementations, the circuitry includes a memory interface coupled to the memory array, the memory interface configured to receive an input signal for reading target data from the memory array, the input signal including a read command; and to output an output signal including the read target data.

[0034] In some implementations, the circuitry includes an address detector coupled to the memory interface and configured to obtain a starting address of the target data based on the input signal and determine that the starting address is within the first address group.

[0035] In some implementations, the circuit configuration further includes a timing profile controller coupled to the address detector and configured to determine a first timing profile for reading the target data based on a signal from the address detector, the signal indicating that the starting address of the target data is within the first address group.

[0036] In some implementations, the circuitry further includes an output buffer configured to output the read target data to the memory interface.

[0037] In some implementations, the memory interface is configured to output the output signal after one or more dummy cycles following the input signal, and the circuitry is configured to determine which group the starting address is in before the one or more dummy cycles begin.

[0038] In some implementations, the circuitry is configured to determine which group the starting address is in on the ending clock cycle that receives the input signal.

[0039] In some implementations, the period of the one or more dummy cycles is fixed or determined based on determining that the starting address is within the first address group.

[0040] In some implementations, one or more dummy cycles occur between the end cycle of the input signal and the start cycle of the output signal.

[0041] In some implementations, the memory interface includes a serial pin configured to at least one of receive an input signal from a bus or provide an output signal to the bus.

[0042] In some implementations, the memory interface includes a plurality of serial input / output (SIO) pins configured to receive input signals from the bus using at least one of the plurality of SIO pins and to output output signals to the bus using the plurality of SIO pins, hi some implementations, the number of the plurality of SIO pins is two or four.

[0043] In some implementations, the memory interface is configured to multiplex multiple SIO pins to receive input signals from the bus and output signals to the bus.

[0044] In some implementations, the memory interface is configured to receive input signals from a bus through a plurality of SIO pins; and to output output signals to the bus through a plurality of SIO pins.

[0045] In some implementations, the bits of the starting address are multiplexed onto multiple SIO pins, and the bits of the data to be read are multiplexed onto multiple SIO pins.

[0046] In some implementations, the read instruction includes a read command and a starting address.

[0047] Another aspect of the disclosure features a system including a memory device and a controller coupled to the memory device and configured to transmit a read command to the memory device. The memory device includes a memory array configured to store data and circuitry coupled to the memory array and configured to read the stored data from the memory array. The circuitry is configured to: obtain, based on the read command, a starting address of target data to be read; determine that the starting address is within a first address group of a plurality of address groups, where each of the plurality of address groups is associated with a respective timing profile of a plurality of different timing profiles; determine a first timing profile associated with the first address group; read the target data from the memory array in accordance with the first timing profile; and output the read target data to the controller.

[0048] A further aspect of the present disclosure features a method including the steps of obtaining a starting address of target data to be read from a memory array; determining that the starting address is within a first address group of a plurality of address groups, where each of the plurality of address groups is associated with a respective timing profile of a plurality of different timing profiles; determining a first timing profile associated with the first address group; and reading the target data from the memory array in accordance with the first timing profile.

[0049] Implementations of the above techniques include methods, systems, circuits, computer program products, and computer-readable media. In one example, a method may include the actions described above. In another example, one such computer program product is suitably embodied in a non-transitory machine-readable medium that stores instructions executable by one or more processors. The instructions are configured to cause the one or more processors to perform the actions described above. One such computer-readable medium stores instructions that, when executed by one or more processors, cause the one or more processors to perform the actions described above.

[0050] It should be noted that in this disclosure, the term "read frequency" refers to the clock frequency of a clock signal for reading data, for example, 66 MHz, 100 MHz, 133 MHz, 160 MHz, 200 MHz, or higher. The term "read frequency" may also be referred to as "reading frequency." The read frequency for reading data from a memory device may be specified in a data sheet for the memory device. The data sheet may include one or more read frequencies. In some examples, the data sheet includes a lower read frequency and a higher read frequency. A user may select to operate a read operation using either the lower read frequency or the higher read frequency.

[0051] In this disclosure, the term "read speed" refers to how fast data is read, which is inversely related to the duration (or time period) of reading the data. The duration may be based on the read frequency of the clock signal and the number of clock cycles to read the data. The term "read speed" may also be referred to as "reading speed."

[0052] In this disclosure, the term "timing profile" refers to a profile of durations for different actions associated with a read operation. In some examples, the timing profile includes at least one of a duration for activating a word line, a duration for activating a bit line, a duration for sensing one or more data bits from a memory array, or a duration for outputting one or more data bits. Each duration may be defined by a respective number of clock cycles or a respective time period.

[0053] The details of one or more disclosed implementations are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0054] [Figure 1] FIG. 1 is a schematic diagram illustrating an example of a system according to one or more embodiments of the present disclosure.

[0055] [Figure 2] FIG. 1 is a schematic diagram illustrating an example of a memory device in accordance with one or more embodiments of the present disclosure.

[0056] [Figure 3] 1 is a schematic diagram illustrating two different example timing profiles in accordance with one or more embodiments of the present disclosure.

[0057] [Figure 4] 1 is a flowchart of an example process for managing read timing in a memory device in accordance with one or more embodiments of the present disclosure.

[0058] [Figure 5] FIG. 1 is a schematic diagram illustrating an example timing diagram with address detection for an SPI interface in accordance with one or more embodiments of the present disclosure.

[0059] [Figure 6] FIG. 10 is a schematic diagram illustrating an example timing diagram with address detection for a QPI interface having four SIO pins, in accordance with one or more embodiments of the present disclosure.

[0060] [Figure 7] FIG. 1 is a schematic diagram illustrating an example timing diagram with address detection for an SPI interface having two SIO pins, in accordance with one or more embodiments of the present disclosure.

[0061] [Figure 8] FIG. 1 is a schematic diagram illustrating an example timing diagram with address detection for an SPI interface having four SIO pins, in accordance with one or more embodiments of the present disclosure.

[0062] [Figure 9] 1 is a flowchart of an example process for managing read timing in a semiconductor device in accordance with one or more embodiments of the present disclosure.

[0063] Like reference numbers and designations in the various drawings indicate like elements. It should also be understood that the various exemplary implementations shown in the figures are illustrative representations only and are not necessarily drawn to scale. DETAILED DESCRIPTION OF THE INVENTION

[0064] Implementations of the present disclosure provide a technique for managing read timing in a semiconductor device, e.g., a non-volatile memory device such as a NOR flash memory device. The technique can ensure successful reads in the semiconductor device without adjusting the read control timing settings in the semiconductor device to the worst-case read performance (e.g., reading data starting from the end of a word line with the lowest read frequency). Instead, the technique enables the semiconductor device to detect a starting read address of data and reconfigure the corresponding read control timing settings for reading data to support a higher read frequency and achieve higher read performance, thereby avoiding the problem of an unlimited starting read address inhibiting higher read frequencies and performance.

[0065] For example, if the starting read address is detected to be within a worse read region of the semiconductor device, the technique enables the semiconductor device to first read a beginning portion of the data at a lower read speed and then switch to a higher read speed for the remaining portion of the data without consistently maintaining the lower read speed. Furthermore, if the starting read address is detected to be within a read region outside one or more worse read regions, the technique enables the semiconductor device to read the data, for example, the entire data, consistently using a higher read speed, thereby achieving higher read performance.

[0066] This technique enables high read performance to be achieved with a simple and cost-effective configuration. In some implementations, a semiconductor device includes an address detector (or address detection circuit) configured to detect a starting address of data to be read from a memory array, for example, based on a read command. The address detector may determine whether the starting address is within a first group (e.g., a group including a worst-case read region) in the semiconductor device. If the starting address is determined to be within the first group, the address detector transmits, for example, through a state machine, a first corresponding signal indicating that the starting address is within the first group to a timing profile controller that may be coupled to a sense amplifier coupled to the memory array. The timing profile controller may store different timing profiles associated with different groups of read regions. Based on the first corresponding signal, the timing profile controller may configure a first corresponding timing profile (having a lower read speed) for the first group and transmit the first corresponding timing profile to a sense amplifier that reads data according to the first corresponding timing profile. Similarly, if the starting address is determined to be within a second group (e.g., including a region other than the worst read region), the address detector may also transmit a second corresponding signal for the second group to the timing profile controller. The timing profile controller may also configure a second corresponding timing profile (e.g., having a higher read speed) for the second group and transmit the second corresponding timing profile to the sense amplifier, which reads data according to the second corresponding timing profile.

[0067] The technique may be applied to various interfaces or protocols, for example, a Serial Peripheral Interface (SPI) such as a single-bit SPI or a multi-bit SPI, or a Quad Peripheral Interface (QPI). The technique may be applied to external and / or internal clock designs. The technique may be applied to various applications using high read frequencies and / or high read performance, for example, a True Wireless Stereo (TWS) System on Chip (SoC), an Application-Specific Integrated Circuit (ASIC), and / or a Field Programmable Gate Array (FPGA). The technique may be applied to various types of semiconductor devices, for example, non-volatile memory devices such as NOR flash memory devices, NAND flash memory devices, resistive random-access memory (RRAM) devices, and phase-change random-access memory (PCRAM) devices, among others. The present technique may be applied to various memory types, such as SLC (single-level cell) devices, bi-level cell devices, TLC (triple-level cell) devices, QLC (quad-level cell) devices, or MLC (multi-level cell) devices such as PLC (penta-level cell) devices. Additionally or alternatively, the present technique may be applied to various types of devices and systems, such as Secure Digital (SD) cards, embedded multimedia cards (eMMC), or solid-state drives (SSD), embedded systems, among others. For illustrative purposes, in this disclosure, memory devices are described as examples of semiconductor devices.

[0068] 1 shows an example of a system 100. The system 100 includes a device 110 and a host device 120. The device 110 includes a device controller 112 and a memory 116. The device controller 112 includes a processor 113 and an internal memory 114. In some implementations, the device 110 includes multiple memories 116 coupled to the device controller 112. The memory 116 includes multiple blocks. The memory 116 may be a 2D memory including two-dimensional (2D) memory blocks. The memory 116 may also be a 3D memory including three-dimensional (3D) memory blocks. The memory 116 may be a semiconductor device and may be formed on a semiconductor substrate (e.g., a silicon wafer).

[0069] The host device 120 has a host controller 122 that may include at least one processor and at least one memory coupled to the at least one processor and storing programming instructions for execution by the at least one processor to perform one or more corresponding operations.

[0070] In some implementations, device 110 is a storage device. For example, device 110 may be an embedded multimedia card (eMMC), a secure digital (SD) card, a solid-state drive (SSD), or some other suitable storage. In some implementations, device 110 is a smartwatch, a digital camera, or a media player. In some implementations, device 110 is a client device coupled to host device 120. For example, device 110 is an SD card in a digital camera or media player that is host device 120.

[0071] The device controller 112 is a general-purpose microprocessor or an application-specific microcontroller. In some implementations, the device controller 112 is a memory controller for the device 110. The following sections describe various techniques based on an implementation in which the device controller 112 is a memory controller. However, the techniques described in the following sections are also applicable to implementations in which the device controller 112 is another type of controller different from a memory controller.

[0072] Processor 113 is configured to execute instructions and process data. These instructions include firmware instructions and / or other program instructions stored in secondary memory as firmware code and / or other program code, respectively. Data includes program data corresponding to firmware and / or other programs executed by the processor, among other suitable data. In some implementations, processor 113 is a general-purpose microprocessor or an application-specific microcontroller.

[0073] Processor 113 accesses instructions and data from internal memory 114. In some implementations, internal memory 114 is static random access memory (SRAM) or dynamic random access memory (DRAM). For example, in some implementations, if device 110 is an eMMC, SD card, or smartwatch, internal memory 114 is SRAM. In some implementations, if device 110 is a digital camera or media player, internal memory 114 is DRAM.

[0074] In some implementations, the internal memory is a cache memory included in device controller 112, as shown in Figure 1. Internal memory 114 stores instruction code corresponding to instructions executed by processor 113 and / or data required by processor 113 during execution. Device controller 112 transfers the instruction code and / or data from memory 116 to internal memory 114.

[0075] In some implementations, memory 116 is non-volatile memory configured for long-term storage of instructions and / or data, such as a NOR or NAND flash memory device, or any other suitable non-volatile memory device. Memory 116 may include one or more memory chips. In implementations in which memory 116 is NAND flash memory, device 110 is a flash memory device, such as a flash memory card, and device controller 112 is a NAND flash controller. For example, in some implementations, if device 110 is an eMMC or SD card, memory 116 is NAND flash memory; in some implementations, if device 110 is a digital camera, memory 116 is an SD card; and in some implementations, if device 110 is a media player, memory 116 is a hard disk. In some implementations in which memory 116 is NOR flash memory, device 110 may optionally include device controller 112. In some cases, device 110 may not include a device controller, and memory 116 may communicate directly with host device 120.

[0076] In some implementations, the system includes a controller and a semiconductor device. The controller may be coupled to the semiconductor device via an electrical connection, e.g., a wire, pin, or bus, or a wireless connection, and communicates with the semiconductor device, e.g., directly. The controller may be the host controller 122 of FIG. 1 or the device controller 112 of FIG. 1. The semiconductor device may be implemented as the memory 116 of FIG. 1. The semiconductor device may also be a memory device 200, as described in further detail in FIG. 2.

[0077] 2 is a schematic diagram illustrating an example of a memory device 200, in accordance with one or more embodiments of the present disclosure. The memory device 200 may be implemented as the memory 116 of FIG.

[0078] As shown in FIG. 2 , memory device 200 includes multiple components that may be integrated and packaged on a board, such as a silicon-based carrier board. Memory device 200 may have a memory array 210 that may include multiple memory cells. The memory cells may be serially coupled to multiple row word lines and multiple column bit lines. Each memory cell may include a memory transistor configured as a storage element (e.g., a capacitor) for storing data. The memory transistor may include a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, a floating gate transistor, a nitride read-only memory (NROM) transistor, or any suitable non-volatile memory MOS device capable of storing charge.

[0079] Memory device 200 may include an X decoder (or row decoder) 208 and, optionally, a Y decoder (or column decoder) 212. Each memory cell may be coupled to X decoder 208 via a respective word line and to Y decoder 212 via a respective bit line. Thus, each memory cell may be selected for a read or write operation through a respective word line and a respective bit line by X decoder 208 and Y decoder 212.

[0080] The memory device 200 may include a memory interface 202 (including input / output—I / O) having multiple pins configured to couple to an external device, such as the device controller 112 and / or the host device 120 of FIG. 1 . The pins may include SI / SIO0 for serial data input / serial data input and output, SO / SIO1 for serial data output / serial data input and output, SIO2 for serial data input or output, SIO3 for serial data input or output, RESET# for a hardware reset pin active low, CS# for chip select, and ECS# for an ECC correction signal, and an R / B# pin for indicating a ready or busy state of the memory device 200. ECS stands for Error Correction Code (ECC) correction signal. The memory interface 202 may also include one or more other pins, such as WP# for write protect active low and / or Hold# for a hold signal input.

[0081] In some implementations, the memory device 200 includes a data register 204, an SRAM buffer 220, an address generator 206, a synchronous clock (SCLK) input 218, a clock generator 228, mode logic 222, a state machine 224, and a high voltage (HV) generator 226.

[0082] The SCLK input 218 may be configured to receive an SCLK signal (e.g., a clock signal having a clock frequency), and the clock generator 228 may be configured to generate a corresponding clock signal for the memory device 200 based on the synchronous clock input. The corresponding clock signal may have the same clock frequency (or clock bit rate) as the SCLK signal. The clock frequency may be used by the memory device 200 as a read frequency for performing read operations or as a write frequency for performing write operations. The clock frequency may be, for example, 66 MHz, 100 MHz, 133 MHz, 160 MHz, 200 MHz, or higher. The clock frequency may be specified in a data sheet for the memory device 200. As discussed in this disclosure, for the memory device 200, the data sheet may include one or more read frequencies. In some examples, the data sheet includes a lower read frequency and a higher read frequency. A user may select either the lower read frequency or the higher read frequency for operation of the memory device 200 based on, for example, the characteristics of the read area storing the target data. Data may be sampled or transmitted at a Single Data Rate (SDR) or a Double Data Rate (DDR). In some examples, if the clock frequency is 100 MHz, data may be transmitted at 50 MHz for SDR or 100 MHz for DDR.

[0083] Mode logic 222 may be configured to determine whether there is a read or write operation and provide the result of the determination to state machine 224. Memory device 200 may also include sense amplifiers 214, which may optionally be connected to Y-decoder 212 by data lines 213, and output buffers 216 for buffering output signals from sense amplifiers 214 to memory interface 202. Sense amplifiers 214 may be part of read circuitry used when data is read from memory device 200. Sense amplifiers 214 may be configured to sense low-power signals from bit lines representing data bits (1 or 0) stored in memory cells and amplify the small voltage swings to recognizable logic levels so that the data can be properly interpreted. Sense amplifiers 214 may also communicate, e.g., bidirectionally, with state machine 224.

[0084] 1 may generate commands, such as read commands and / or write commands, that may be executed to read data from and / or write data to memory device 200, respectively. Data to be written to or read from memory array 210 may be communicated or transmitted between memory device 200 and the controller and / or other components via a data bus (e.g., a system bus), which may be a multi-bit bus. As discussed in further detail in FIGS. 5-8, the communication protocol between the controller and memory device 200 may be an SPI protocol or a QPI protocol.

[0085] In some implementations, during a read operation, memory device 200 receives a read command (or read instruction) from a controller through memory interface 202, for example, according to an SPI protocol or a QPI protocol. The read instruction may be transmitted using SDR or DDR. State machine 224 may provide control signals to HV generator 226 and sense amplifier 214. Sense amplifier 214 may also send information, such as the logic level of sensed data, back to state machine 224. HV generator 226 may provide voltages to X decoder 208 and Y decoder 212 to select a memory cell. Sense amplifier 214 may detect a low-power (voltage or current) signal from a bit line representing a data bit (1 or 0) stored in the selected memory cell and amplify the low-power signal amplitude to a recognizable logic level so that the data bit can be properly interpreted by logic external to memory device 200. Output buffer 216 may receive the amplified voltage from sense amplifier 214 and output an amplified power signal through memory interface 202 to logic external to memory device 200 .

[0086] Data can be read from a read region spanning from a starting address to an ending address. The read region can encompass multiple consecutive word lines. For example, as discussed in detail in FIG. 4 , a timing profile for reading data can include a duration for activating a word line, a duration for activating a bit line, a duration for sensing one or more data bits from the memory array, and a duration for outputting one or more data bits. If the starting address is at the end of a first word line, e.g., at one or more last bits of the first word line, after reading one or more last bits of the first word line, the memory device 200 must first activate a second consecutive word line and corresponding bit lines before reading data bits of a second word line. Because it takes time to activate the second word line and corresponding bit lines, the memory device cannot use a high read speed from the starting address on the first word line to the data bits on the second word line. Otherwise, it may cause a read error. Instead, the memory device must use a slower read speed from a starting address on the first word line to the second word line.

[0087] A read region having a starting address at the end of a word line may be considered a worse read region. There may be one or more other worse read regions for which the memory device needs to use a corresponding lower read speed or lower read frequency. In some cases, to ensure a successful read, the read speed or read frequency of the memory device needs to be matched to the lowest read speed or read frequency for the worst read region in the memory device, which may affect the read performance of the memory device.

[0088] As discussed above and in further detail below, implementations of the present disclosure provide techniques that enable a memory device to detect a starting read address of data and configure corresponding read control timing settings for reading the data to support higher read frequencies and achieve higher read performance.

[0089] For example, if the starting read address is detected to be within the worst read region of the memory device, the memory device can first read a beginning portion of the data at a lower read speed, and then switch to a higher read speed for the remaining portion of the data without consistently maintaining the lower read speed.If the starting read address is detected to be within a read region outside one or more of the worst read regions, the memory device can read the data, for example, the entire data, using a higher read speed consistently, thereby achieving high read performance.

[0090] In some implementations, memory device 200 includes address detector 232 (or address detection circuitry), as shown in FIG. 2 . In some implementations, address detector 232 is included in mode logic 222, as shown in FIG. 2 . Address detector 232 may perform one or more operations / actions according to a clock signal, for example, from clock generator 228. In some implementations, address detector 232 is external to mode logic 222. Address detector 232 may include one or more logic circuits or logic gates.

[0091] Address detector 232 may be configured to detect a starting address of data to be read from memory array 210, for example, based on a read command. For example, the read command may include a command and, e.g., immediately following the command, a starting address of the data, as shown, for example, in FIG. 5, 6, 7, or 8. Address detector 232 may receive the read command from memory interface 202. Address detector 232 may determine whether the starting address is within one or more worst read regions in memory device 200. In some implementations, memory device 200 characterizes or stores the worst read regions in a first group, e.g., group A, and regions other than the worst read regions in a second group, e.g., group B.

[0092] As described above, the worst read region may be defined as the last data bits of a word line, e.g., a predetermined number of the last data bits at the end of a word line (e.g., 3 data bits, 5 data bits, 10 data bits, or more), or a predetermined percentage of the data bits at the end of a word line (e.g., 1%, 5%, 10%, or more). The worst read region may be predetermined in the memory device or may be dynamically determined based on one or more parameters, e.g., the clock frequency (or read frequency) and / or the data density of the word line or memory array 210. Information about the worst read region (e.g., addresses ranging from the starting address to the ending address) may be stored in the memory device 200, e.g., in the address detector 232 or the mode logic 222.

[0093] The address detector 232 may determine whether the starting address of the data to be read is within the worst read region by comparing the starting address with the beginning address and the ending address. If the starting address of the data is greater than (or equal to) the beginning address of the worst read region but less than (or equal to) the ending address, the address detector 232 may determine that the starting address is within the worst read region. However, if the starting address of the data is less than the beginning address of each of the one or more worst read regions in the first group or greater than the ending address of each of the one or more worst read regions in the first group, the address detector 232 may determine that the starting address of the data is outside the first group and / or within the second group.

[0094] In some implementations, memory device 200 includes a timing profile controller 230 that can store different timing profiles associated with different groups of readout regions and associations between different timing profiles and different groups of readout regions. Timing profile controller 230 can include one or more registers or buffers for storing the timing profiles and one or more logic and / or circuits for managing the timing profiles. In some implementations, timing profile controller 230 is included in mode logic 222, for example, as shown in FIG. 2. Timing profile controller 230 can be coupled to address detector 232. In some implementations, timing profile controller 230 is included in address detector 232. In some implementations, timing profile controller 230 is included in sense amplifier 214.

[0095] The timing profile controller 230 (e.g., one or more logics and / or circuits) may be configured to determine which timing profile is for which group of readout regions based on a signal indicating which group of readout regions the starting address is in from the address detector 232 and the timing profiles stored in one or more registers or buffers. In some implementations, the timing profile controller 230 generates a specific timing profile for a specific group of readout regions or a specific readout region.

[0096] If the starting address is determined to be within the first group, the address detector 232 may transmit a first corresponding signal indicating that the starting address is within the first group to a timing profile controller 230 coupled to the sense amplifiers 214 coupled to the memory array 210. The timing profile controller 230 may configure a first corresponding timing profile (having a lower read speed) for the first group based on the first corresponding signal. The timing profile controller 230 may transmit the first corresponding timing profile to the sense amplifiers 214, which can read data according to the first corresponding timing profile. In some implementations, the timing profile controller 230 transmits the first corresponding timing profile to the state machine 224, which further transmits the first corresponding timing profile to the sense amplifiers 214. Similarly, if the starting address is determined to be within a second group (e.g., including a region other than the worst-case read region), the address detector 232 may also transmit a second corresponding signal for the second group to the timing profile controller 230. The timing profile controller 230 may also configure a second corresponding timing profile (e.g., having a higher read speed) for the second group, and the timing profile controller 230 may transmit the second corresponding timing profile to the sense amplifiers 214, which can read data according to the second corresponding timing profile.

[0097] 2, the mode logic 222 includes both the address detector 232 and the timing profile controller 230. The mode logic 222 may be coupled to the address generator 206, the clock generator 228, and the state machine 224. The sense amplifier 214 may be controlled by the state machine 224 or the mode logic 222 (e.g., via the state machine 224). In some implementations, address information of data (e.g., a date to be read from the memory array 210) received from the memory interface 202 is stored in the address generator 206. The address generator 206 may then transmit the address information of the data to the address detector 232 (e.g., within the mode logic 222). The address detector 232 may determine a starting address of the data based on the address information and may further determine whether the starting address of the data is within the first group or the second group. After address detector 232 determines which group the starting address of the data is in, address detector 232 may transmit that information to timing profile controller 230, which may determine which timing profile is for that group and for reading the data. Timing profile controller 230 may then send that timing profile to sense amplifiers 214, which may then use the timing profile to read data from memory array 210.

[0098] In some implementations, the address detector 232 is external to the mode logic 222 and is coupled to the address generator 206 and the timing profile controller 230. In some implementations, the timing profile controller 230 is external to the mode logic 222 and may be coupled to the address detector 232 and the sense amplifier 214, for example, directly or through a state machine 224.

[0099] 3 is a schematic diagram illustrating two different exemplary timing profiles according to one or more embodiments of the present disclosure. For illustrative purposes, address group A corresponds to the first group described above that includes one or more worst-read regions, and address group B corresponds to the second group described above that includes one or more regions other than the worst-read regions. The timing profile controller 230 may store or configure different timing profiles for these two groups, e.g., a first timing profile 300 for address group A and a second timing profile 350 for address group B.

[0100] 3, the timing profile includes multiple internal read timing periods. Each period may include a series of durations for reading a data bit (or one or more data bits in parallel), such as a duration for activating a word line (e.g., WL time), a duration for activating a bit line (e.g., BL time), a duration for sensing a data bit from the memory array (e.g., sensing time), and a duration for outputting a data bit (e.g., data out time). Because address group A includes one or more worst-case read regions, the read speed for the read regions in address group A may be slower or smaller than the read speed for the read regions in address group B, and therefore the durations for address group A may be longer than the corresponding durations for address group B.

[0101] 3 , for example, for the WL time, T1_A for address group A is longer than T1_B for address group B; for the BL time, T2_A for address group A is longer than T2_B for address group B; for the sense time, T3_A for address group A is longer than T3_B for address group B; and for the data-out time, T4_A for address group A is longer than T4_B for address group B. Thus, the internal read timing period 310 of the first timing profile 300 includes T1_A, T2_A, T3_A, and T4_A, while the internal read timing period 360 of the second timing profile 350 includes T1_B, T2_B, T3_B, and T4_B. The internal read timing period 360 is shorter (or smaller) than the internal read timing period 310, which indicates a faster read speed for the internal read timing period 360 than for the internal read timing period 310.

[0102] In some implementations, each duration in the timing profile is defined by the number of clock cycles of a clock signal having a clock frequency. That is, the actual time period of the duration is equal to the number of clock cycles multiplied by one period of one clock cycle (e.g., the inverse of the clock frequency). In some implementations, each duration is defined as an actual time period or a fixed time. Based on the clock frequency of the clock signal, the memory device (e.g., a timing profile controller) can calculate the number of clock cycles for each time, such as the WL time, the BL time, the sense time, and the data out time.

[0103] In some implementations, after reading a leading portion of the target data including a starting address in a worst-case read region (e.g., the last data bit of a first word line), the memory device can increase the read speed for the remaining portion of the target data. The remaining portion of the target data can include one or more worst-case read regions, e.g., the last data bit of a word line contiguous to the first word line. In some implementations, the timing profile 300 has a first timing sub-profile for the leading portion of the target data and a second timing sub-profile for the remaining portion of the target data. The first timing sub-profile can include one or more internal read timing periods 310, while the second timing sub-profile can include one or more internal read timing periods 360. That is, the target data can be read at two different read speeds, thereby avoiding speed limitations for reading the worst-case read region and increasing the read speed and improving overall read performance. In contrast, the second timing profile 350 for address group B includes the same internal read timing period 360 for reading the entire target data.

[0104] In some implementations, the total length of the leading portion of the target data having the lower read speed may be predetermined, such as 10 data bits. In some implementations, the total time period of the first timing sub-profile may be predetermined, such as 1 microsecond (μs). The total length of the leading portion and / or the total time period of the first timing sub-profile may be predetermined or may be dynamically determined by the memory device or controller (e.g., device controller 112 or host device 122 of FIG. 1 ) based on one or more parameters (e.g., clock frequency or data density).

[0105] 4 is a flowchart of an example process 400 for managing read timing in a memory device according to one or more embodiments of the present disclosure. The memory device may be memory 116 of FIG. 1 or memory device 200 of FIG. 2.

[0106] In step 402, the memory device receives a read command with an input address, for example, from a controller. The controller may be, for example, host controller 122 of FIG. 1 or device controller 112 of FIG. 1. The controller may be coupled to the memory device and may send the read command to the memory device through a memory interface of the memory device (e.g., memory interface 202 of FIG. 2). The read command may include a read command and an input address. The input address may be a starting address of target data to be read from a memory array of the memory device (e.g., memory array 210 of FIG. 2).

[0107] In step 404, the memory device detects whether the starting address of the target data is within address group A or address group B. As described above, address group A may be a group of one or more worst read regions, while group B may be a group of read regions other than the one or more worst read regions. The memory device may include an address detector (e.g., address detector 232 of FIG. 2) that can determine whether the starting address of the target data is within address group A or address group B.

[0108] If the starting address of the target data is within address group A, then in step 406, the memory device configures an internal read timing A (e.g., timing profile 300 of FIG. 3) for reading the target data. As described above, the address detector may transmit a signal to a timing profile controller (e.g., timing profile controller 230 of FIG. 2) indicating that the starting address is within address group A. The timing profile controller may configure an internal read timing A for the target data, for example, by retrieving a stored internal read timing A based on the association between the internal read timing A and address group A. The timing profile controller may transmit the internal read timing A to the sense amplifier. In step 408, the memory device (e.g., the sense amplifier) ​​reads the target data from the memory array according to the internal read timing A. In step 414, the memory device transmits the read data, for example, through the memory device to a controller.

[0109] Similarly, if the starting address of the target data is within address group B, then in step 410, the memory device (e.g., timing profile controller) configures internal read timing B (e.g., timing profile 350 of FIG. 3) for reading the target data. The timing profile controller may transmit internal read timing B to the sense amplifier. In step 412, the memory device (e.g., sense amplifier) ​​reads the target data from the memory array according to internal read timing B. In step 414, the memory device transmits the read data, for example, through the memory device to a controller.

[0110] As mentioned above, a memory interface (e.g., memory interface 202 of FIG. 2) coupled between a memory device (e.g., memory 116 of FIG. 1 or memory device 200 of FIG. 2) and a controller (e.g., host device 120 or host controller 122 or device controller 112 of FIG. 1) may be configured according to an SPI or QPI protocol, and the memory interface may include one or more serial input (SI), serial output (SO), or serial input / output (SIO) pins (e.g., SI / SIO0, SO / SIO1, SIO2, and SIO3). Techniques implemented in this disclosure may be applied to different embodiments of the memory interface, for example, as discussed in further detail in FIGS. 5-8.

[0111] FIG. 5 is a schematic diagram illustrating an example timing diagram 500 involving address detection for an SPI interface, in accordance with one or more embodiments of the present disclosure.

[0112] As shown in FIG. 5, the memory device is selected for a read operation (e.g., CS# is at a low signal level “0”). The memory device receives an SCLK signal, which may include a number of clock cycles with a clock frequency, from, for example, the SCLK input 218 of FIG. 2. A read command may be transmitted over a bus to the memory device, for example, from a controller. The read command may include a command and an input address (e.g., a starting address). The command (e.g., 0Bh having 8 bits) may be transmitted first to the memory device through the SI pin, followed by the input address (e.g., a 24-bit address). The memory device may perform address detection 510 (e.g., step 404 of FIG. 4) at the end of the input address (e.g., the last bit of the input address, such as “0”). Address detection 510 may be performed on the rising edge of a corresponding clock signal or the falling edge of a corresponding clock signal (e.g., as shown in FIG. 5). Following the input address, a number of dummy cycles (e.g., eight dummy cycles) may be transmitted over the SI pin on the bus. After the dummy cycle, the memory device transmits the read target data to the controller through the SO pin, for example, on the falling edge of the clock signal. The read target data may be output as a data packet, for example, data out 1, data out 2, as shown in Figure 5. While the SI pin is selected for data transfer, the SO pin may be maintained in a high-Z (or high-impedance) state.

[0113] FIG. 6 is a schematic diagram illustrating an example timing diagram 600 with address detection for a QPI interface having four SIO pins, in accordance with one or more embodiments of the present disclosure.

[0114] In timing diagram 600, a read command (e.g., a command with 8 bits and an input address with 24 bits) is first transmitted on the bus by four SIO pins (SIO(3:0)). Each SIO pin may be configured to transmit a 2-bit command and a 6-bit input address. The memory device performs address detection 610 (e.g., step 404 in FIG. 4) at the end of the input address (e.g., the last bit of the input address, such as A0). Address detection 610 may be performed on the rising edge of a corresponding clock signal or the falling edge of a corresponding clock signal (e.g., as shown in FIG. 6). Following the input address, a number of dummy cycles (e.g., six dummy cycles) may be transmitted through the SIO pins on the bus. After the dummy cycles, the memory device transmits the target data to be read to the controller through the SIO pins, e.g., on the falling and rising edges of the clock signal. The target data to be read may be output as a data packet, e.g., data out 1, data out 2, as shown in FIG. 6. Each data packet may include a Most Significant Bit (MSB) or high order bit (eg, H0 or H1) and a Least Significant Bit (LSB) or low order bit.

[0115] FIG. 7 is a schematic diagram illustrating an example timing diagram 700 with address detection for an SPI interface having two SIO pins, in accordance with one or more embodiments of the present disclosure.

[0116] As shown in FIG. 7 , a command may be transmitted to the memory device through an SIO pin (e.g., SIO0), while an input address (e.g., 24 bits) may be transmitted through two SIO pins simultaneously (e.g., 12 bits through the SIO0 pin and 12 bits through the SIO1 pin). The memory device may perform address detection 710 (e.g., step 404 of FIG. 4 ) at the end of the input address (e.g., the last bit of the input address, such as A0, A1, etc.). Address detection 710 may be performed on the rising edge of a corresponding clock signal or the falling edge of a corresponding clock signal (e.g., as shown in FIG. 7 ). Following the input address, a number of dummy cycles may be transmitted on the bus. The number of dummy cycles may be configurable, for example, by the memory device or the controller. After the dummy cycles, the memory device transmits the target data to be read to the controller through two SIO pins simultaneously, for example, at the falling edge of the clock signal. The target data to be read may be output as a data packet, e.g., data output 1, data output 2, as shown in FIG. 7 . For example, 8 bits of data can be transmitted by transmitting 4 bits (D0, D2, D4, D6) through the SIO0 pin and 4 bits (D1, D3, D5, D7) through the SIO1 pin.

[0117] FIG. 8 is a schematic diagram illustrating an example timing diagram 800 with address detection for an SPI interface having four SIO pins, in accordance with one or more embodiments of the present disclosure.

[0118] As shown in FIG. 8, a command and an input address may be transmitted to the memory device simultaneously through four SIO pins (e.g., SIO0, SIO1, SIO2, and SIO3). The memory device may perform address detection 810 (e.g., step 404 in FIG. 4) at the end of the input address (e.g., the last bit of the input address, such as A0, A1, A2, or A3). Address detection 810 may be performed on the rising edge of a corresponding clock signal or the falling edge of a corresponding clock signal (e.g., as shown in FIG. 8). Following the input address, a number of dummy cycles may be transmitted on the bus. The dummy cycles may include a toggle bit and a preamble bit. The number of dummy cycles may be configurable, for example, by the memory device or the controller. After the dummy cycles, the memory device transmits the target data to be read to the controller simultaneously through four SIO pins, for example, at the falling edge of the clock signal. The target data to be read may be output as a data packet.

[0119] 9 is a flowchart of an example of a process 900 for managing read timing in a semiconductor device in accordance with one or more embodiments of the present disclosure. The semiconductor device may be the memory 116 of FIG. 1 or the memory device 200 of FIG. 2. The semiconductor device may include a memory array (e.g., the memory array 210 of FIG. 2) and circuitry coupled to the memory array. The memory array may be configured to store data, and the circuitry may be configured to read the stored data from the memory array. Process 900 may be performed by a semiconductor device such as the circuitry.

[0120] The circuitry may be peripheral circuitry for a memory array. In some embodiments, the circuitry includes at least one of a memory interface (e.g., memory interface 202 of FIG. 2), an address detector (e.g., address detector 232 of FIG. 2), a timing profile controller (e.g., timing profile controller 230 of FIG. 2), or a sense amplifier (e.g., sense amplifier 214 of FIG. 2). The memory interface may be a serial peripheral interface (SPI) or a quad peripheral interface (QPI). The circuit configuration may also include one or more other components, such as a data register, such as data register 204, a buffer, such as SRAM buffer 220 of FIG. 2 and / or output buffer 216 of FIG. 2, mode logic, such as mode logic 222 of FIG. 2, a state machine, such as state machine 224 of FIG. 2, a clock generator, such as clock generator 228 of FIG. 2, an SCLK input, such as SCLK input 218 of FIG. 2, an address generator, such as address generator 206 of FIG. 2, and / or a voltage generator, such as HV generator 226 of FIG. 2.

[0121] In step 902, the circuit configuration obtains a start address of target data to be read based on a read command. The read command may include a read command and a start address, for example, as shown in FIGS. 5-8. A controller, for example, the host controller 122 in FIG. 1 or the device controller 112 in FIG. 1, may be coupled to the semiconductor device and may send the read command to the semiconductor device through the memory interface. An address detector may receive the read command from the memory interface.

[0122] In step 904, the circuitry determines that the starting address belongs to a first address group of a plurality of address groups. For example, similar to step 404 of FIG. 4, the address detector may determine whether the starting address is within the first address group, e.g., group A. The first address group may include a set of specific addresses corresponding to a lower read speed compared to addresses in one or more other address groups. For example, one or more of the specific addresses correspond to one or more specific memory cells coupled to one or more last data bits of a word line of the memory array. In some embodiments, the specific addresses in the first address group are fixed or predetermined, e.g., the last 3, 5, or 10 bits. In some embodiments, the circuitry is configured to determine the specific addresses in the first address group and / or the duration for the specific addresses based on one or more parameters including a clock frequency (e.g., of a clock signal generated by a clock generator) and a data density (e.g., of a word line).

[0123] Each of the plurality of address groups is associated with a respective timing profile from a plurality of different timing profiles. In some embodiments, for example, as shown in FIG. 3 , the timing profile may include at least one of a duration for activating a word line, a duration for activating a bit line, a duration for sensing one or more data bits from the memory array, or a duration for outputting one or more data bits. The timing profiles and / or the association between the timing profile and the address group may be stored in or determined by the timing profile controller. Different timing profiles may be associated with different read speeds, for example, as shown in FIG. 3 . A first timing profile may be associated with a first read speed, and a second timing profile may be associated with a second read speed that is higher than the first read speed.

[0124] In step 906, the circuitry reads target data from the memory array based on the starting address belonging to the first address group. In some implementations, the target data has a first portion and a second portion contiguous to the first portion, the first portion including the starting address. The total length of the first portion of the target data can be predetermined. The circuitry is configured to read the first portion at a first read rate and to read the second portion at a second read rate that is higher than the first read rate.

[0125] In some implementations, in step 908, the circuitry determines a first timing profile associated with the first address group. For example, the address detector may transmit a signal to the timing profile controller, the signal indicating that the starting address of the data belongs to the first address group. The timing profile controller may pre-store different timing profiles, such as the timing profile of FIG. 3, and select the first timing profile for the first address group based on the association between the first timing profile and the first address group. In some implementations, instead of pre-storing the first timing profile and / or the association between the first timing profile and the first address group, the timing profile controller generates the first timing profile in response to receiving a signal indicating that the starting address of the data belongs to the first address group.

[0126] In step 910, the circuitry reads target data from the memory array according to a first timing profile, for example, as described in step 414 of FIG. 4. In some implementations, the target data has a first portion and a second portion contiguous to the first portion, the first portion including a starting address. The first timing profile may have a first timing sub-profile for the first portion of the target data and a second timing sub-profile for the second portion of the target data, the first timing sub-profile corresponding to a first read speed and the second timing sub-profile corresponding to a second read speed different from the first read speed. The total length of the first portion of the target data may be predetermined, and / or the total time period of the first timing sub-profile may be predetermined.

[0127] In some implementations, the circuitry is configured to receive a clock signal having a clock frequency, for example from the SCLK input 218 of FIG. 2, and read target data using the clock signal. The clock frequency may be a read frequency. A particular duration in the first timing profile may correspond to a first number of clock cycles of the clock signal, and a corresponding particular duration in the second timing profile may correspond to a second number of clock cycles of the clock signal. The second read speed may be different from the first read speed. In some implementations, the duration in the first timing profile is predetermined, and the circuitry is configured to determine the number of clock cycles for the duration based on the clock frequency.

[0128] In some implementations, the memory interface of the circuit configuration is configured to receive an input signal for reading target data from the memory array and transmit the input signal to the address detector, the input signal including a read command, for example, as shown in Figures 2, 5, 6, 7, or 8. The memory interface may also be configured to receive target data read from the circuit configuration (e.g., output buffer 216 of Figure 2), and output an output signal including the read target data, for example, as shown in Figures 2, 5, 6, 7, or 8.

[0129] The address detector may be coupled to the memory interface and configured to obtain a starting address of the target data based on the input signal and determine that the starting address belongs to the first address group. The timing profile controller may be configured to store a plurality of timing profiles and coupled to the address detector and configured to determine a first timing profile for reading the target data based on a signal from the address detector, the signal indicating that the starting address of the target data belongs to the first address group. The circuit configuration may further include an output buffer (e.g., output buffer 216 of FIG. 2 ) configured to output the read target data to the memory interface.

[0130] In some implementations, the memory interface is configured to output an output signal after one or more dummy cycles following the input signal. The circuitry may be configured to determine which group a starting address belongs to before the one or more dummy cycles begin and / or at the end clock cycle of receiving the input signal, for example, as shown in FIG. 5, 6, 7, or 8. The period of the one or more dummy cycles may be fixed or may be determined based on determining that the starting address belongs to a first address group. The one or more dummy cycles may occur between the end cycle of the input signal and the start cycle of the output signal. The period of the one or more dummy cycles may be determined by a controller or by a semiconductor device.

[0131] In some implementations, the memory interface includes a serial pin configured to perform at least one of receiving an input signal from a bus or outputting an output signal to the bus. In some implementations, the memory interface has multiple serial input / output (SIO) pins configured to receive an input signal from the bus using at least one of the multiple SIO pins and output an output signal to the bus using the multiple SIO pins. The number of the multiple SIO pins can be two or four, for example, as shown in FIG. 6, 7, or 8. The memory interface can be configured to multiplex the multiple SIO pins to receive input signals from the bus and output output signals to the bus, for example, as shown in FIG. 6, where each SIO pin can receive a read command and one or more corresponding addresses. The memory interface can be configured to receive input signals from the bus through the multiple SIO pins and output output signals to the bus through the multiple SIO pins, where one of the multiple SIO pins can receive a read command and one or more addresses and the other SIO pins can receive (e.g., only) other addresses, for example, as shown in FIG. 7 or 8. For example, as shown in FIG. 7 or FIG. 8, the bits of the starting address may be multiplexed onto multiple SIO pins, and the bits of the data to be read may be multiplexed onto multiple SIO pins.

[0132] The disclosed examples and other examples may be implemented as one or more computer program products, e.g., one or more modules of computer program instructions encoded on a computer-readable medium for execution by or to control the operation of a data processing apparatus. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a combination of one or more of these. The term "data processing apparatus" encompasses all apparatuses, devices, and machines for processing data, including, by way of example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, an apparatus may include code that creates the execution environment for the computer program, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof.

[0133] A system may encompass all apparatus, devices, and machines for processing data, including, by way of example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, a system may include code that creates an execution environment for the computer program, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of these.

[0134] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including a stand-alone program, or modules, components, subroutines, or other units suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in part of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple coordinated files (e.g., files storing one or more modules, subprograms, or code portions). A computer program can be deployed for execution on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communications network.

[0135] The processes and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The processes and logic flows may also be performed by, and apparatus may be implemented as, special purpose logic circuitry, such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0136] Processors suitable for executing computer programs include, by way of example, both general-purpose and special-purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor receives instructions and data from a read-only memory or a random-access memory, or both. The essential elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer may also include one or more mass storage devices, such as magnetic disks, magneto-optical disks, or optical disks, for storing data, or may be operatively coupled to receive data from or transfer data to them, or both. However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data may include all types of non-volatile memory, media, and memory devices, including, by way of example, semiconductor memory devices, such as EPROMs, EEPROMs, and flash memory devices, and magnetic disks. The processor and memory may be supplemented by, or incorporated in, special-purpose logic circuitry.

[0137] While this document may describe many specific examples, these should not be construed as limitations on the scope of the claimed invention or what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, while features may be described above as acting in a particular combination, and even initially claimed as such, in some cases, one or more features from a claimed combination may be deleted from this combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination. Similarly, although acts are depicted in the figures in a particular order, this should not be understood as requiring such acts to be performed in the particular order or sequential order depicted, or to perform all of the depicted acts, to achieve desired results.

[0138] Only a few examples and implementations are disclosed. Variations, modifications, and enhancements to the described examples and implementations and other implementations may be made based on what is disclosed.

Claims

1. a memory array configured to store data; and a circuit arrangement coupled to the memory array and configured to read stored data from the memory array; The circuit configuration comprises: Obtaining a start address of target data to be read according to a read command; determining that the starting address is within a first address group of a plurality of address groups, each of the plurality of address groups being associated with a respective read speed; and reading the target data from the memory array based on the starting address being within the first address group; is configured to run the target data has a first portion and a second portion contiguous with the first portion, the first portion including the starting address; the circuitry is further configured to read the first portion at a first read rate and to read the second portion at a second read rate that is faster than the first read rate.

2. Each of the plurality of address groups is associated with a respective timing profile from among a plurality of mutually different timing profiles; The timing profile is the duration for which the word line is activated, the duration for which the bit line is activated, the duration of sensing one or more data bits from the memory array; or The duration for outputting the one or more data bits and The circuit configuration is determining a first timing profile associated with the first address group; and reading the target data from the memory array according to the first timing profile; The semiconductor device according to claim 1 , wherein the semiconductor device is configured as follows:

3. Different timing profiles are associated with different read speeds, the first timing profile is associated with a first read speed, and a second timing profile of the plurality of timing profiles is associated with a second read speed that is faster than the first read speed. The semiconductor device of claim 2 .

4. The semiconductor device of claim 1 , wherein the total length of the first portion of the target data is predetermined.

5. 10. The semiconductor device of claim 1, wherein the circuitry is configured to receive a clock signal having a clock frequency and to read the target data using the clock signal.

6. the first address group having a particular set of addresses corresponding to a slower read speed than addresses in one or more other address groups; one or more of the particular addresses correspond to one or more particular memory cells coupled to one or more last data bits of a word line of the memory array; The semiconductor device of claim 1 .

7. The semiconductor device of claim 6 , wherein the particular address within the first address group is fixed or predetermined.

8. 7. The semiconductor device of claim 6, wherein the circuitry is configured to determine at least one of the particular address in the first address group or a duration for the particular address based on one or more parameters including a clock frequency and a data density of a word line.

9. the circuitry includes a memory interface coupled to the memory array; The memory interface receiving an input signal for reading the target data from the memory array, the input signal including the read command; and outputting an output signal including the read target data; The semiconductor device of claim 1 configured to perform:

10. 10. The semiconductor device of claim 9, wherein the circuitry comprises an address detector coupled to the memory interface and configured to obtain the starting address of the target data based on the input signal and determine that the starting address is within the first address group.

11. 11. The semiconductor device of claim 10, wherein the circuitry further comprises a timing profile controller coupled to the address detector and configured to determine a timing profile from a plurality of timing profiles for reading the target data based on a signal from the address detector, the signal indicating that the starting address of the target data is within the first address group.

12. the memory interface is configured to output the output signal after one or more dummy cycles following the input signal; the circuitry is configured to determine which group the starting address is in before the one or more dummy cycles begin.

10. The semiconductor device of claim 9.

13. The memory interface receiving said input signal from a bus; or outputting the output signal to the bus; 10. The semiconductor device of claim 9, further comprising a serial pin configured to perform at least one of:

14. 10. The semiconductor device of claim 9, wherein the memory interface has a plurality of serial input / output (SIO) pins, the memory interface being configured to receive the input signal from a bus using at least one of the plurality of SIO pins and to output the output signal to the bus using the plurality of SIO pins.

15. The semiconductor device of claim 1 , wherein the read instruction includes a read command and the starting address.

16. a memory array configured to store data; and a circuit arrangement coupled to the memory array and configured to read stored data from the memory array; The circuit configuration comprises: Obtaining a start address of target data to be read according to a read command; determining that the starting address is within a first address group of a plurality of address groups, each of the plurality of address groups being associated with a respective read speed; and reading the target data from the memory array based on the starting address being within the first address group; is configured to run the first address group having a particular set of addresses corresponding to a slower read speed than addresses in one or more other address groups; one or more of the particular addresses correspond to one or more particular memory cells coupled to one or more last data bits of a word line of the memory array; The semiconductor device, wherein the circuitry is configured to determine at least one of the particular address within the first address group or a duration for the particular address based on one or more parameters including a clock frequency and a data density of a word line.

17. a memory device; and a controller coupled to the memory device and configured to transmit a read command to the memory device; wherein the memory device comprises: a memory array configured to store data; and circuitry coupled to the memory array and configured to read stored data from the memory array; The circuit configuration comprises: Obtaining a start address of target data to be read based on the read command; determining that the starting address is within a first address group of a plurality of address groups, each of the plurality of address groups being associated with a respective read speed; reading the target data from the memory array based on the starting address being within the first address group; and outputting the read target data to the controller; is configured to run the target data has a first portion and a second portion contiguous with the first portion, the first portion including the starting address; The circuitry is further configured to read the first portion at a first read rate and to read the second portion at a second read rate that is faster than the first read rate.

18. obtaining a starting address of target data to be read from the memory array; determining that the starting address is within a first address group of a plurality of address groups, each of the plurality of address groups being associated with a respective read speed, the first address group being associated with a first read speed; reading the target data from the memory array at the first read speed based on the starting address being within the first address group, the target data having a first portion and a second portion contiguous with the first portion, the first portion including the starting address; and A method comprising reading the first portion at a first read rate and reading the second portion at a second read rate that is faster than the first read rate.

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