Image sensor, ranging module

Abstract

The present technology relates to an imaging element and a distance measurement module which can reduce parasitic capacitance. The present invention comprises: first wiring which connects predetermined transistors in first adjacent pixels to each other and connects a via formed in one pixel of first adjacent pixels and connected to wiring formed in another layer; and second wiring which connects predetermined transistors in second adjacent pixels to each other and connects a via formed in a pixel adjacent to one pixel of second adjacent pixels and connected to wiring formed in another layer, wherein the first wiring is connected to redundant wiring. The present technology can be applied to, for example, a distance measurement sensor for performing distance measurement.

Description

[Technical Field]

[0001] The present technology relates to an imaging element and a ranging module, and more particularly to an imaging element and a ranging module that can achieve both reduction in cyclic errors and distribution of drive current. [Background technology]

[0002] A ToF sensor measures the distance to an object by measuring the time of flight of light. It outputs modulated light from a light source and receives the light reflected by the object. When measuring distance, the modulated light output from the light source is processed as a sine wave, but since the light actually output from the light source is a rectangular waveform, processing the rectangular wave as a sine wave causes periodic errors (hereinafter referred to as cyclic errors) in the measurement value.

[0003] For example, a technique has been disclosed in which a pseudo sine wave is generated by shifting the phase of modulated light output from a light source, thereby reducing cyclic errors (see, for example, Patent Document 1).

[0004] Furthermore, in recent years, the number of pixels in ToF sensors has tended to increase. When a large number of pixels are driven simultaneously, the driving current is concentrated, causing a strong charging and discharging current that can cause IR drop, which can prevent the pixels from being driven accurately. For this reason, technologies are being considered to prevent IR drop by distributing pixel driving to suppress peak current (see, for example, Non-Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2009 / 051499 [Non-patent literature]

[0006] [Non-Patent Document 1] Cyrus S Bamji,et al., 5.8 1Mpixel 65nm BSI 320MHz Demodulated TOF Image Sensor with 3.5um Global Shutter Pixels and Analog Binning, Microsoft Corp., 2018 IEEE International Solid-State Circuits Conference SESSION 5 / IMAGE SENSORS, February 12th 2018 [Non-patent document 2] Min-Sun Keel,et al., A 640×480 Indirect Time-of-Flight CMOS Image Sensor with 4-tap 7-μm Global-Shutter Pixel and Fixed-Pattern Phase Noise Self-Compensation Scheme, Samsung Electronics Co., Ltd.,2019 Symposium on VLSI Circuits Digest of Technical Papers Summary of the Invention [Problem to be solved by the invention]

[0007] However, the techniques in Non-Patent Documents 1 and 2 do not take cyclic errors into consideration, and no method has yet been proposed that achieves both cyclic error reduction and distribution of drive current.

[0008] The present technology has been made in view of such circumstances, and makes it possible to achieve both reduction in cyclic errors and dispersion of drive current. [Means for solving the problem]

[0009] An imaging element according to one aspect of the present technology includes: a phase shift circuit that generates phase-shifted drive pulse signals by shifting a drive pulse signal generated in response to a light emission control signal indicating the irradiation timing of a light source to a plurality of phases in a time-division manner within one frame period; and pixels that accumulate charges obtained by photoelectric conversion of light that is irradiated from the light source and reflected by a predetermined object based on the phase-shifted drive pulse signals, and output a detection signal corresponding to the accumulated charges.a first wiring that connects predetermined transistors in first adjacent pixels with a via that is formed in one of the first adjacent pixels and is connected to a wiring that is formed in another layer; and a second wiring that connects predetermined transistors in second adjacent pixels with a via that is formed in a pixel adjacent to the one of the second adjacent pixels and is connected to a wiring that is formed in another layer, wherein the first wiring To match the parasitic capacitance, a It is connected with redundant wiring.

[0010] A distance measuring module according to one aspect of the present technology includes: a light emitting unit that emits irradiation light; a phase shift circuit that generates phase-shifted drive pulse signals by shifting a drive pulse signal generated in response to a light emission control signal that indicates the irradiation timing of the light emitting unit to a plurality of phases in a time-division manner within one frame period; a light receiving element that receives light reflected by an object from the light emitting unit, The light emitted from the light emitting unit is reflected by a predetermined object. a photoelectric conversion unit that performs photoelectric conversion; and a charge obtained by the photoelectric conversion unit. based on the phase-shifted driving pulse signals a plurality of charge accumulation units that accumulate charges; a plurality of transfer units that transfer charges from the photoelectric conversion unit to each of the plurality of charge accumulation units; a first wiring that connects the transfer units in first adjacent pixels to each other and a via that is formed in one of the first adjacent pixels and connected to a wiring that is formed in another layer; and a second wiring that connects the transfer units in second adjacent pixels to each other and a via that is formed in a pixel adjacent to the one of the second adjacent pixels and connected to a wiring that is formed in another layer, wherein the first wiring To match the parasitic capacitance, a It is connected with redundant wiring.

[0011] In the imaging element according to one aspect of the present technology, a phase-shifted drive pulse signal is generated by shifting a drive pulse signal generated in response to a light emission control signal indicating the irradiation timing of the light source to a plurality of phases in a time-division manner within one frame period, light emitted from the light source is reflected by a predetermined object, and the light is photoelectrically converted into electric charges which are accumulated based on the phase-shifted drive pulse signal, and a detection signal corresponding to the accumulated electric charges is output; The pixel transistors are connected to a via formed in one of the first adjacent pixels and a wiring formed in another layer, and a second wiring is provided to connect to a via formed in a pixel adjacent to the one of the second adjacent pixels and a wiring formed in another layer, and the first wiring is provided To match the parasitic capacitance, a It is connected with redundant wiring.

[0012] In one aspect of the present technology, is beforeThe imaging device is provided.

[0013] The distance measurement module may be a standalone device or may be a module incorporated into another device. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a block diagram illustrating a schematic configuration example of a distance measurement module to which the present technology is applied. [Figure 2] FIG. 2 is a block diagram showing a detailed configuration example of a light receiving unit. [Figure 3] FIG. 2 is a diagram illustrating the operation of a pixel. [Figure 4] FIG. 2 is a diagram illustrating an example of a circuit configuration of a pixel. [Figure 5] FIG. 2 is a diagram illustrating an example of a planar configuration of a pixel. [Figure 6] FIG. 2 is a diagram illustrating an example of a cross-sectional configuration of a pixel. [Figure 7] FIG. 1 is a diagram illustrating a 2-phase method and a 4-phase method. [Figure 8] FIG. 1 is a diagram illustrating a 2-phase method and a 4-phase method. [Figure 9] FIG. 1 is a diagram illustrating a 2-phase method and a 4-phase method. [Figure 10] FIG. 2 is a block diagram showing a more detailed configuration example of a light receiving unit. [Figure 11] FIG. 10 is a diagram illustrating a phase shift process. [Figure 12] FIG. 10 is a diagram illustrating the charge accumulation time of each phase. [Figure 13] FIG. 10 is a diagram illustrating phase shift control of each block. [Figure 14] FIG. 1 is a diagram illustrating IQ mosaic driving. [Figure 15] FIG. 1 is a diagram illustrating IQ mosaic driving. [Figure 16] FIG. 10 is a diagram showing an example of IQ mosaic driving with a phase control division number of 4. [Figure 17] FIG. 10 is a diagram illustrating phase shift control of each block. [Figure 18]FIG. 10 is a diagram showing an example of IQ mosaic driving with a phase control division number of 4. [Figure 19] FIG. 10 is a diagram illustrating the effect of pseudo-sine transformation on cyclic errors. [Figure 20] FIG. 10 is a diagram for explaining wiring. [Figure 21] FIG. 10 is a diagram for explaining wiring in the wiring layer M1. [Figure 22] FIG. 10 is a diagram for explaining wiring in the wiring layer M2. [Figure 23] FIG. 10 is a diagram for explaining wiring in a wiring layer M3. [Figure 24] FIG. 10 is a diagram for explaining wiring in a wiring layer M4. [Figure 25] 10A and 10B are diagrams for explaining wiring connected to wiring in wiring layer M4. [Figure 26] FIG. 1 is a perspective view showing an example of a chip configuration of a distance measuring sensor. [Figure 27] FIG. 1 is a block diagram showing an example of the configuration of a smartphone as an electronic device equipped with a ranging module. [Figure 28] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 29] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described.

[0016] <Example of a schematic configuration of a distance measurement module> FIG. 1 is a block diagram showing a schematic configuration example of a distance measuring module to which the present technology is applied.

[0017] The distance measurement module 11 shown in FIG. 1 is a distance measurement module that performs distance measurement by the Indirect ToF method, and includes a light emitting unit 12 and a distance measurement sensor 13. The distance measurement module 11 irradiates light on an object, and receives the light (reflected light) reflected by the object from the irradiated light, thereby generating and outputting a depth map as distance information to the object. The distance measurement sensor 13 is composed of a light emission control unit 14, a light receiving unit 15, and a signal processing unit 16.

[0018] The light emitting unit 12 includes, for example, a VCSEL array in which a plurality of VCSELs (Vertical Cavity Surface Emitting Lasers) are arranged in a planar shape as a light emission source, emits light while modulating according to the timing of the light emission control signal supplied from the light emission control unit 14, and irradiates the object with the irradiation light.

[0019] The light emission control unit 14 controls the light emitting unit 12 by supplying a light emission control signal of a predetermined frequency (for example, 200 MHz, etc.) to the light emitting unit 12. In addition, the light emission control unit also supplies the light emission control signal to the light receiving unit 15 in order to drive the light receiving unit 15 in accordance with the light emission timing in the light emitting unit 12.

[0020] The light receiving unit 15, the details of which will be described later with reference to FIG. 2, is a pixel array unit 32 in which a plurality of pixels 31 are two-dimensionally arranged, and receives the reflected light from the object. Then, the light receiving unit 15 supplies pixel data composed of detection signals corresponding to the received amount of the reflected light to the signal processing unit 16 in units of pixels 31 of the pixel array unit 32.

[0021] The signal processing unit 16 calculates a depth value, which is the distance from the distance measurement module 11 to the object, based on the pixel data supplied from the light receiving unit 15 for each pixel 31 of the pixel array unit 32, generates a depth map in which the depth value is stored as the pixel value of each pixel 31, and outputs it outside the module.

[0022] <Basic Pixel Driving of Indirect ToF Method> Before describing the details of pixel driving performed by the light receiving unit 15 of the present disclosure, basic pixel driving of the Indirect ToF method (basic pixel driving) will be described.

[0023] FIG. 2 is a block diagram showing an example of a detailed configuration of the light receiving unit 15. As shown in FIG.

[0024] The light receiving unit 15 has a pixel array unit 32 in which pixels 31 are arranged two-dimensionally in a matrix in the row and column directions, and the pixels 31 generate electric charges according to the amount of light received and output detection signals according to the electric charges, and a drive control circuit 33 arranged in the peripheral area of ​​the pixel array unit 32.

[0025] The drive control circuit 33 outputs control signals (such as the distribution signal DIMIX, selection signal ADDRESS DECODE, and reset signal RST, which will be described later) for controlling the driving of the pixel 31, based on, for example, a light emission control signal supplied from the light emission control unit 14.

[0026] The pixel 31 has a photodiode 51 as a photoelectric conversion unit that generates charges according to the amount of received light, and taps 52A and 52B that detect the charges generated by the photodiode 51. In the pixel 31, charges generated in one photodiode 51 are distributed to either the tap 52A or the tap 52B. Of the charges generated in the photodiode 51, the charges distributed to the tap 52A are output as a detection signal A from a signal line 53A, and the charges distributed to the tap 52B are output as a detection signal B from a signal line 53B.

[0027] The tap 52A is composed of a transfer transistor 41A, an FD (Floating Diffusion) section 42A, a selection transistor 43A, and a reset transistor 44A. Similarly, the tap 52B is composed of a transfer transistor 41B, an FD section 42B, a selection transistor 43B, and a reset transistor 44B.

[0028] 3, the light emitter 12 outputs irradiated light that is modulated so as to repeatedly turn on and off irradiation for irradiation time T (one period = 2T), and the reflected light is received by the photodiode 51 after a delay time ΔT that corresponds to the distance to the object. Also, the distribution signal DIMIX_A controls the on / off of the transfer transistor 41A, and the distribution signal DIMIX_B controls the on / off of the transfer transistor 41B. The distribution signal DIMIX_A is a signal in phase with the irradiated light, and the distribution signal DIMIX_B has a phase that is the inverted phase of the distribution signal DIMIX_A.

[0029] 2, the charge generated by the photodiode 51 receiving reflected light is transferred to the FD section 42A while the transfer transistor 41A is on in accordance with the distribution signal DIMIX_A, and is transferred to the FD section 42B while the transfer transistor 41B is on in accordance with the distribution signal DIMIX_B. As a result, during a predetermined period in which irradiation light is periodically applied for the irradiation time T, the charge transferred via the transfer transistor 41A is sequentially accumulated in the FD section 42A, and the charge transferred via the transfer transistor 41B is sequentially accumulated in the FD section 42B.

[0030] Then, after the charge accumulation period ends, when the selection transistor 43A is turned on in accordance with the selection signal ADDRESS DECODE_A, the charge accumulated in the FD section 42A is read out via the signal line 53A, and a detection signal A corresponding to the amount of charge is output from the light-receiving section 15. Similarly, when the selection transistor 43B is turned on in accordance with the selection signal ADDRESS DECODE_B, the charge accumulated in the FD section 42B is read out via the signal line 53B, and a detection signal B corresponding to the amount of charge is output from the light-receiving section 15. Furthermore, the charge accumulated in the FD section 42A is discharged when the reset transistor 44A is turned on in accordance with the reset signal RST_A, and the charge accumulated in the FD section 42B is discharged when the reset transistor 44B is turned on in accordance with the reset signal RST_B.

[0031] In this way, the pixel 31 distributes the charge generated by the reflected light received by the photodiode 51 to the tap 52A or the tap 52B according to the delay time ΔT, and outputs the detection signal A and the detection signal B as pixel data.

[0032] The signal processing unit 16 calculates a depth value based on the detection signal A and the detection signal B supplied as pixel data from each pixel 31. The calculation of the depth value will be described later with reference to FIG. <Structure of unit pixel> Next, a specific structure of the pixels 31 arranged in a matrix in the pixel array section 32 will be described.

[0033] The pixel 31 includes a photodiode 51 (hereinafter referred to as PD51) which is a photoelectric conversion element, and is configured so that charges generated in the PD51 are distributed to a tap 52A and a tap 52B. Of the charges generated in the PD51, the charges distributed to the tap 52A are read out from a vertical signal line 53A and output as a detection signal SIG1. Meanwhile, the charges distributed to the tap 52B are read out from a vertical signal line 53B and output as a detection signal SIG2.

[0034] The tap 52A and the tap 52B have basically the same configuration. Both the tap 52A and the tap 52B realize an FD-type global shutter. In the example of Fig. 4, the tap 52A of the pixel 31 in the pixel array section 32 includes, for example, a transfer transistor (TG) 41A, a floating diffusion (FD) 42A as a charge holding section and a charge-voltage conversion section, a selection transistor (SEL) 43A, a reset transistor (RST) 44A, an amplification transistor (AMP) 45A, a feedback enable transistor (FBEN) 46A, a discharge transistor (OFG) 47, a conversion efficiency switching transistor (FDG) 48A, and an additional capacitance section 49A.

[0035] Similarly, the tap 52B is configured by a transfer transistor 41B, an FD 42B, a selection transistor 43B, a reset transistor 44B, an amplification transistor 45B, an FBEN 46B, an FDG 48B, and an additional capacitance section 49B.

[0036] As shown in FIG. 4, the reset transistor 44 may be provided for each of the FD42A and the FD42B, or may be shared by the FD42A and the FD42B.

[0037] 4, when the FD42A and FD42B are provided with reset transistors 44A and 44B, respectively, the reset timing can be controlled individually for the FD42A and FD42B, allowing for finer control.When the FD42A and FD42B are provided with a common reset transistor 44, the reset timing can be made the same for the FD42A and FD42B, simplifying control and simplifying the circuit configuration.

[0038] In the following description, a configuration in which the FD42A and the FD42B are each provided with a reset transistor 44 will be described as an example. In addition, in the following description with reference to FIG. 4, the tap 52A will be described as an example because the tap 52A and the tap 52B basically have the same configuration.

[0039] In the example shown in FIG. 4, TG41A, FD42A, SEL43A, RST44A, AMP45A, FBEN46A, and OFG47 are all N-type MOS transistors. A drive signal is supplied to each gate electrode of TG41A, FD42A, SEL43A, RST44A, AMP45A, FBEN46A, and OFG47. Each drive signal is a pulse signal that is active (i.e., on) when high and inactive (i.e., off) when low. Hereinafter, switching a drive signal to an active state will be referred to as switching the drive signal on, and switching a drive signal to an inactive state will be referred to as switching the drive signal off.

[0040] The PD 51 is a photoelectric conversion element made up of, for example, a PN junction photodiode, and functions as a photoelectric conversion unit that receives light from a subject, generates and accumulates electric charges according to the amount of received light through photoelectric conversion.

[0041] TG41A is connected between PD51 and FD42A, and functions as a transfer unit that transfers the charge stored in PD51 to FD42A in response to a drive signal applied to the gate electrode of TG41A.

[0042] The FD42A functions as a charge storage unit that temporarily stores the charge accumulated in the PD51 to realize the global shutter function. The FD42A also functions as a floating diffusion region that converts the charge transferred from the PD51 via the TG41A into an electrical signal (e.g., a voltage signal) and outputs it. The FD42A is connected to the RST44A, and is also connected to the VSL53A via the AMP45A and the SEL43A.

[0043] Furthermore, the FD 42A is also connected to an additional capacitance section 49A, which is a floating diffusion region (FD) that converts electric charges into an electrical signal, for example, a voltage signal, via an FDG 48A. Although the additional capacitance section 49A is a floating diffusion region (FD), it operates as a capacitance like the FD 42, and is therefore represented using the circuit symbol for a capacitor.

[0044] The FDG 48A is turned on and off in response to the drive signal FDG, thereby switching the connection state between the FD42A and the additional capacitance section 49A between an electrically connected state and an electrically disconnected state. The FDG 48A functions as an additional control section that controls the addition of the additional capacitance section 49A.

[0045] A drive signal FDG is supplied to the gate electrode of the FDG 48A, and when this drive signal FDG is turned on, the potential directly below the FDG 48A deepens, electrically connecting the FD42A and the additional capacitance section 49A.

[0046] On the other hand, when the drive signal FDG is turned off, the potential directly below the FDG 48A becomes shallower, electrically disconnecting the FD42A from the additional capacitance section 49A. Therefore, by turning the drive signal FDG on and off, capacitance is added to the FD42A, changing the sensitivity of the pixel. Specifically, if the change in the accumulated charge is ΔQ, the change in voltage at that time is ΔV, and the capacitance value is C, then the relationship ΔV = ΔQ / C holds.

[0047] Now, if the capacitance value of FD42A is CFD and the capacitance value of additional capacitance section 49A is CFD2, when drive signal FDG is on, the capacitance value C in the pixel region where the signal level is read out is CFD+CFD2. In contrast, when drive signal FDG is turned off, capacitance value C changes to CFD, and the voltage sensitivity to the amount of change in charge (amount of change in voltage: FD conversion efficiency) increases.

[0048] In this way, the sensitivity of the pixel 31 is appropriately changed by turning on and off the drive signal FDG. For example, when the drive signal FDG is turned on, the additional capacitance unit 49A is electrically connected to the FD42A, and therefore, part of the charge transferred from the PD 51 to the FD42A is stored not only in the FD42A but also in the additional capacitance unit 49A.

[0049] The RST44A has a drain connected to the FBEN46A and a source connected to the FD42A. The RST44A functions as a reset unit that initializes, i.e., resets, the FD42A in response to a drive signal applied to its gate electrode. As shown in FIG. 4, the drain of the RST44A forms a parasitic capacitance C_ST with the ground, and forms a parasitic capacitance C_FB with the gate electrode of the AMP45A.

[0050] The FBEN 46A functions as a reset voltage control unit that controls the reset voltage applied to the RST 44A.

[0051] OFG47 has a drain connected to a power supply VDD and a source connected to PD51. The cathode of PD51 is commonly connected to the source of OFG47 and the source of TG41A. OFG47 initializes, or resets, PD51 in response to a drive signal applied to its gate electrode. Resetting PD51 means depleting PD51.

[0052] AMP45A has a gate electrode connected to FD42A and a drain connected to a power supply VDD, and serves as the input section of a source follower circuit that reads out charges obtained by photoelectric conversion in PD 51. That is, AMP45A has its source connected to VSL53A via SEL43A, and thereby forms a source follower circuit together with a constant current source connected to one end of VSL53A.

[0053] SEL43A is connected between the source of AMP45A and VSL53A, and a selection signal is supplied to the gate electrode of SEL43A. When the selection signal is turned on, SEL43A becomes conductive, and the tap 52A of the pixel 31 in which SEL43A is provided becomes selected. When the tap 52A of the pixel 31 becomes selected, the pixel signal output from AMP45A is read out by the column signal processing unit 23 via VSL53A.

[0054] Furthermore, in the pixel array section 32, a plurality of pixel drive lines (not shown) are wired, for example, for each pixel row, and each drive signal is supplied from the vertical drive section 2 to the selected pixel 31 through the plurality of pixel drive lines.

[0055] The components constituting the tap 52B are configured and operate in the same manner as the components constituting the tap 52A described above.

[0056] The pixel circuit shown in FIG. 4 is an example of a pixel circuit that can be used in the pixel array section 32, and pixel circuits with other configurations can also be used.

[0057] <Example of pixel plane configuration> FIG. 5 shows an example of the planar configuration of the pixel 31 corresponding to the example of the circuit configuration shown in FIG.

[0058] 5, PD51 is provided in a region near the center of rectangular pixel 31. TG41A and TG41B are provided on the upper side (upper edge) of PD 51 in the figure. TG41A is the gate portion of transfer transistor 41A, and TG41B is the gate portion of transfer transistor 41B.

[0059] Each of TG41A and TG41B is provided adjacent to one of the four sides of PD 51. In the example shown in Fig. 5, TG41A and TG41B are arranged side by side in the X-axis direction on the top side of PD 51.

[0060] An FD42A-1 is provided above the TG41A and forms part of the FD42A included in the tap 52A.

[0061] The FD42A included in the tap 52A is composed of FD42A-1 and FD42A-2. These FD42A-1 and FD42A-2 are formed in different regions. FD42A-1 is formed on the upper side of TG41A in the drawing, and FD42A-2 is formed in a position apart from FD42A-1, diagonally above and to the right of FD42A-1. As will be described later, FD42A-1 and FD42A-2 are connected by wiring in the wiring layer and are configured so that they can be treated as a single region.

[0062] FDG 48A is formed above FD42A-2 in the figure. Furthermore, an additional capacitance section 49A is formed above FDG 48A in the figure. When FDG 48A is turned on, the three regions of FD42A-1, FD42A-2, and additional capacitance section 49A are connected.

[0063] The amplifier transistor 45A (gate portion thereof) included in the tap 52A is formed to the left of the TG41A in the figure. Also, the select transistor 43A (gate portion thereof) is formed above the TG41A in the figure. Furthermore, the tap 52A is also provided with an FBEN 46A, which is formed above the reset transistor 44A in the figure.

[0064] In this way, the FD42A is formed in two separate areas, FD42A-1 and FD42A-2. The RST44A is connected to the FD42A-1, and the FBEN46A is connected to this RST44A. The FDG48A is connected to the FD42A-2. In this way, by dividing the FD42A into two areas, FD42A-1 and FD42A-2, it is possible to connect the FBEN46A to one of the areas via the RST44A, and connect the FDG48A to the other.

[0065] The components that make up the tap 52B are arranged on the right side of the tap 52A in the drawing. The tap 52B has the same configuration as the tap 52A.

[0066] TG41B included in tap 52B is formed on the upper right side of PD51 in the figure. FD42B-1 is provided above TG41B in the figure. FD42B included in tap 52B is composed of FD42B-1 and FD42B-2. FD42B-1 is formed above TG41B in the figure, and FD42B-2 is formed in a position away from FD42B-1 and diagonally above and to the left of FD42B-1. As will be described later, FD42B-1 and FD42B-2 are connected by wiring in the wiring layer and configured so that they can be treated as a single area.

[0067] FDG 48B is formed above FD42B-2 in the figure. Furthermore, an additional capacitance section 49B is formed above FDG 48B in the figure. When FDG 48B is turned on, the three regions of FD42B-1, FD42B-2, and additional capacitance section 49B are connected.

[0068] The (gate portion of) amplification transistor 45B included in tap 52B is formed to the right of TG41B in the figure. Also, the (gate portion of) selection transistor 43B is formed above TG41B in the figure. Furthermore, FBEN 46B is also provided in tap 52B, and this FBEN 46B is formed above the reset transistor 44B in the figure.

[0069] A well contact 54 is provided above the PD 51. A drain transistor (OFG) 47 (the gate portion thereof) is provided below the PD 51. The drain transistor 47 is an overflow gate for preventing blooming, and is shared by the taps 52A and 52B, so one OFD 47 is formed in the pixel 31 as shown in FIG. 5 .

[0070] 5 and the following description are merely examples and are not intended to be limiting. Furthermore, although the examples shown in FIG. 5 and the following description illustrate a configuration in which the drain transistor 47 is provided, a configuration without the drain transistor 47 is also possible.

[0071] In the example shown in FIG. 5, the components constituting tap 52A and the components constituting tap 52B are arranged symmetrically with respect to a center line L1 of pixel 31 (line L1 shown by a dotted line in the figure).

[0072] That is, TG41A, FD42A-1, FD42A-2, reset transistor 44A, FBEN46A, amplifier transistor 45A, select transistor 43A, FDG48A, and additional capacitance section 49A that constitute tap 52A, and TG41B, FD42B-1, FD42B-2, reset transistor 44B, FBEN46B, amplifier transistor 45B, select transistor 43B, FDG48B, and additional capacitance section 49B that constitute tap 52B are arranged symmetrically with respect to each other.

[0073] 5, although wiring is not shown, FD42A-1 and the amplification transistor 45A are connected, and the signal amount from FD42A-1 is supplied to the amplification transistor 45A. In addition, FD42B-1 and the amplification transistor 45B are also connected, and the signal amount from FD42B-1 is supplied to the amplification transistor 45B.

[0074] As described above, by configuring them in line symmetry, the length of the wiring between FD42A-1 and the amplifier transistor 45A and the length of the wiring between FD42B-1 and the amplifier transistor 45B can be made approximately the same. In addition, by configuring the other wirings in left-right symmetry, the lengths can also be made the same.

[0075] <Example of pixel cross-sectional structure> FIG. 6 is a diagram showing an example of a cross-sectional configuration of the pixel 31 having the two taps 52 shown in FIGS.

[0076] The pixel 31 includes a semiconductor substrate 141 and a multi-layer wiring layer 142 formed on the surface side (lower side in the figure) of the semiconductor substrate 141.

[0077] The semiconductor substrate 141 is made of, for example, silicon (Si) and is formed to have a thickness of, for example, about several μm. In the semiconductor substrate 141, for example, an N-type (second conductivity type) semiconductor region 152 is formed in a P-type (first conductivity type) semiconductor region 151 in a pixel unit, thereby forming a photodiode 51 in a pixel unit. The P-type semiconductor regions 151 provided on both the front and back surfaces of the semiconductor substrate 141 also serve as hole charge accumulation regions for suppressing dark current.

[0078] 6 is the back surface of the semiconductor substrate 141, which is the light incident surface onto which light is incident. An anti-reflection film 143 is formed on the upper surface of the back surface side of the semiconductor substrate 141.

[0079] The anti-reflection film 143 has a laminated structure in which a fixed charge film and an oxide film are laminated, and for example, a high-dielectric-constant (High-k) insulating thin film formed by the ALD (Atomic Layer Deposition) method can be used. Specifically, hafnium oxide (HfO2), aluminum oxide (Al2O3), titanium oxide (TiO2), STO (Strontium Titan Oxide), etc. can be used. In the example of FIG. 6, the anti-reflection film 143 is configured by laminating a hafnium oxide film 153, an aluminum oxide film 154, and a silicon oxide film 155.

[0080] An inter-pixel light-shielding film 145 that prevents incident light from entering adjacent pixels is formed on the upper surface of the anti-reflection film 143 at a boundary 144 (hereinafter also referred to as a pixel boundary 144) between adjacent pixels 31 of the semiconductor substrate 141. The material of the inter-pixel light-shielding film 145 may be any material that blocks light, and may be, for example, a metal material such as tungsten (W), aluminum (Al), or copper (Cu).

[0081] A planarization film 146 is formed on the upper surface of the anti-reflection film 143 and the upper surface of the inter-pixel light-shielding film 145 using an insulating film such as silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON), or an organic material such as resin.

[0082] An on-chip lens 147 is formed on the upper surface of the planarization film 146 for each pixel. The on-chip lens 147 is made of a resin material such as a styrene resin, an acrylic resin, a styrene-acrylic copolymer resin, or a siloxane resin. The light collected by the on-chip lens 147 is efficiently incident on the PD 51.

[0083] Furthermore, in the pixel boundary portion 144 on the back surface side of the semiconductor substrate 141, an inter-pixel separation portion 161 is formed extending from the back surface side (the on-chip lens 147 side) of the semiconductor substrate 141 to a predetermined depth in the substrate depth direction, separating adjacent pixels. The outer periphery of the inter-pixel separation portion 161, including its bottom surface and sidewalls, is covered with a hafnium oxide film 153, which is part of the anti-reflection film 143. The inter-pixel separation portion 161 prevents incident light from penetrating into adjacent pixels 31, confining it within the pixel itself, and also prevents incident light from leaking in from adjacent pixels 31.

[0084] 6, the silicon oxide film 155, which is the uppermost layer of the anti-reflection film 143, is embedded in a trench (groove) dug from the back surface side to simultaneously form the silicon oxide film 155 and the inter-pixel isolation portion 161, so that the silicon oxide film 155, which is part of the laminated film as the anti-reflection film 143, and the inter-pixel isolation portion 161 are made of the same material, but they do not necessarily have to be the same. The material embedded in the trench (groove) dug from the back surface side as the inter-pixel isolation portion 161 may be a metal material such as tungsten (W), aluminum (Al), titanium (Ti), or titanium nitride (TiN).

[0085] Meanwhile, on the front surface side of the semiconductor substrate 141 on which the multilayer wiring layer 142 is formed, two transfer transistors TRG1 and TRG2 are formed for one PD 51 formed in each pixel 31. For example, the transfer transistor TRG1 corresponds to TG41A (FIG. 5), and the transfer transistor TRG2 corresponds to TG41B (FIG. 5).

[0086] Furthermore, floating diffusion regions FD1 and FD2 are formed of high-concentration N-type semiconductor regions (N-type diffusion regions) on the surface side of semiconductor substrate 141 as charge storage sections that temporarily store the charges transferred from PD 51. For example, floating diffusion region FD1 corresponds to FD42A (FD42A-1 or FD42A-2 (FIG. 5) that constitute FD42A), and floating diffusion region FD2 corresponds to FD42B (FD42B-1 or FD42B-2 (FIG. 5) that constitute FD42B).

[0087] The multi-layer wiring layer 142 is made up of a plurality of wiring layers M and interlayer insulating films 162 therebetween. Fig. 6 shows an example in which the multi-layer wiring layer 142 is made up of four layers, wiring layers M1 to M4.

[0088] Wirings 171 to 174 are formed in each of the multiple wiring layers M of the multilayer wiring layer 142. The wirings 171 to 174 are formed of a metal film such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), etc. Here, the wiring arranged in the wiring layer M1 is referred to as wiring 171, the wiring arranged in the wiring layer M2 is referred to as wiring 172, the wiring arranged in the wiring layer M3 is referred to as wiring 173, and the wiring arranged in the wiring layer M4 is referred to as wiring 174.

[0089] The wirings 171 to 174 arranged on the wiring layers M1 to M4 are connected at necessary locations by vias 166 provided in the vertical direction.

[0090] As described above, the pixel 31 has a back-illuminated structure in which the semiconductor substrate 141, which is a semiconductor layer, is disposed between the on-chip lens 147 and the multilayer wiring layer 142, and incident light is made incident on the PD 51 from the back side on which the on-chip lens 147 is formed.

[0091] In addition, the pixel 31 has two transfer transistors TRG1 and TRG2 for the PD51 provided in each pixel, and is configured so that the charges (electrons) generated by photoelectric conversion in the PD51 can be distributed to the floating diffusion region FD1 or FD2.

[0092] <How to calculate depth values> The following describes a method for calculating a depth value from a signal obtained by a pixel having the above-mentioned two taps. There are two methods for calculating a depth value: a 2-phase method that uses detection signals of two different phases, and a 4-phase method that uses detection signals of four different phases.

[0093] The 2-phase method and the 4-phase method will be explained.

[0094] In the 4-phase method, the light receiving unit 15 receives reflected light at light receiving timings that are shifted in phase by 0°, 90°, 180°, and 270° with respect to the irradiation timing of the irradiated light, as shown in Fig. 7. More specifically, the light receiving unit 15 receives reflected light with the phase changed in a time division manner, such that in one frame period, the light receiving unit 15 receives light with a phase of 0° relative to the irradiation timing of the irradiated light, in the next frame period, the light receiving unit 15 receives light with a phase of 90°, in the next frame period, the light receiving unit 15 receives light with a phase of 180°, and in the next frame period, the light receiving unit 15 receives light with a phase of 270°.

[0095] Unless otherwise specified, a phase of 0°, 90°, 180°, or 270° refers to the phase at tap 52A of pixel 31. Tap 52B has an inverted phase from tap 52A, so when tap 52A has a phase of 0°, 90°, 180°, or 270°, tap 52B has a phase of 180°, 270°, 0°, or 90°, respectively.

[0096] FIG. 8 is a diagram showing the exposure periods of the tap 52A of the pixel 31 at phases of 0°, 90°, 180°, and 270°, arranged so that the phase difference can be easily seen.

[0097] As shown in Figure 8, at tap 52A, the detection signal A obtained by receiving light at the same phase as the irradiated light (phase 0°) will be called detection signal A0, the detection signal A obtained by receiving light at a phase shifted by 90 degrees from the irradiated light (phase 90°) will be called detection signal A90, the detection signal A obtained by receiving light at a phase shifted by 180 degrees from the irradiated light (phase 180°) will be called detection signal A180, and the detection signal A obtained by receiving light at a phase shifted by 270 degrees from the irradiated light (phase 270°) will be called detection signal A270.

[0098] Also, although not shown in the figure, at tap 52B, the detection signal B obtained by receiving light at the same phase as the irradiated light (phase 0°) will be called detection signal B0, the detection signal B obtained by receiving light at a phase shifted 90 degrees from the irradiated light (phase 90°) will be called detection signal B90, the detection signal B obtained by receiving light at a phase shifted 180 degrees from the irradiated light (phase 180°) will be called detection signal B180, and the detection signal B obtained by receiving light at a phase shifted 270 degrees from the irradiated light (phase 270°) will be called detection signal B270.

[0099] FIG. 9 is a diagram illustrating the calculation methods of depth values ​​and reliability using the 2-phase method and the 4-phase method.

[0100] In the Indirect ToF method, the depth value d can be calculated by the following equation (1).

number

number

[0101] In the 4-phase method, I and Q in equation (2) are calculated using the following equation (3) using detection signals A0 to A270 and detection signals B0 to B270 obtained by setting the phase to 0°, 90°, 180°, and 270°. I and Q are signals obtained by converting the phase of the sine wave from polar coordinates to a Cartesian coordinate system (IQ plane), assuming that the luminance change of the irradiated light is a sine wave. I=c0-c180=(A0-B0)-(A180-B180) Q=c90-c270=(A90-B90)-(A270-B270) ·····(3)

[0102] In the 4-phase method, by taking the difference between detection signals of opposite phases at the same pixel, such as "A0-A180" or "A90-A270" in equation (3), it is possible to eliminate the characteristic variations between taps in each pixel, i.e., the sensitivity differences between taps.

[0103] On the other hand, in the 2-phase system, I and Q in equation (2) can be calculated using detection signals of two phases, phase 0° and phase 90°. That is, I and Q in equation (2) in the 2-phase system are expressed as the following equation (4). I=c0-c180=(A0-B0) Q=c90-c270=(A90-B90) ·······(4)

[0104] Although the 2-phase method cannot eliminate the characteristic variations between taps that exist in each pixel, it can calculate the depth value d to the object using only the detection signals of two phases, allowing distance measurement at twice the frame rate of the 4-phase method. The characteristic variations between taps can be adjusted using correction parameters such as gain and offset.

[0105] The reliability cnf can be calculated by the following equation (5) in both the 2Phase method and the 4Phase method.

number

[0106] In the following description, a unit in which each pixel 31 of the pixel array unit 32 outputs pixel data (detection signal) of one phase, such as 0°, 90°, 180°, or 270°, is referred to as one frame (period). In the 4-phase method, one depth map is generated by four frames consisting of four phases, and in the 2-phase method, one depth map is generated by two frames consisting of two phases.

[0107] <Problems caused by simultaneously driving all pixels> If the above-described basic pixel driving is performed for all the pixels 31 in the pixel array section 32 at the same timing, the following problems occur.

[0108] (1) IR drop The drive control circuit 33 controls the distribution of the charge generated by the photodiode 51 to either tap 52A or tap 52B using distribution signals DIMIX_A and DIMIX_B. When the pixel array unit 32 has a large number of pixels, driving all of the pixels 31 in the pixel array unit 32 at the same time can cause a large concentration of drive current, resulting in a strong charge / discharge current that causes IR drop. This can lead to the distribution signals DIMIX_A and DIMIX_B becoming dull signals, making it impossible to accurately control the distribution of charge. When the number of pixels (resolution) of the pixel array unit 32 is greater than, for example, VGA (640x480), driving all of the pixels in the pixel array unit 32 simultaneously can have a significant impact on IR drop.

[0109] (2) Deterioration of EMC / EMI Furthermore, if all the pixels 31 in the pixel array section 32 are driven at the same timing, the peak current increases, which increases the electromagnetic waves generated from the distance measurement sensor 13, deteriorating EMC (Electromagnetic Compatibility) and EMI (Electromagnetic Interference).

[0110] Therefore, it is desirable to distribute the driving of all the pixels in the pixel array section 32 and to distribute the peak current.

[0111] (3) Occurrence of a cyclic error As described above, the depth value d is calculated assuming that the brightness change of the irradiated light is a sine wave. However, since the light emitted from the light-emitting unit 12 is actually a rectangular wave as shown in Figure 3, processing the rectangular wave as a sine wave causes a periodic error (hereinafter referred to as a cyclic error) to occur in the depth value d.

[0112] The light receiving section 15 of the present disclosure distributes the driving of all pixels in the pixel array section 32, disperses peak currents, and realizes driving that reduces cyclic errors. The driving of the light receiving section 15 will be described in detail below.

[0113] <Detailed configuration example of the light receiving unit> <Example of phase control division number 2> FIG. 10 is a block diagram showing a more detailed configuration example of the light receiving section 15. As shown in FIG.

[0114] 2, the light receiving section 15 includes a pixel array section 32 in which pixels 31 are arranged two-dimensionally, and a drive control circuit 33. Note that in FIG. 10, the taps 52A and 52B of the pixels 31 shown in FIG. 2 are simplified and illustrated as "A" and "B."

[0115] In the pixel array unit 32, all the two-dimensionally arranged pixels 31 are divided into a plurality of blocks BL, with N (N>1) pixel columns being one block BL. The example in Fig. 10 shows an example where N=3 and three pixel columns are one block BL.

[0116] Each block BL of the pixel array unit 32 is further divided into one of two types of phase control units (phase control unit blocks). If the two types of phase control unit blocks are designated as blocks BL_X and BL_Y, respectively, the blocks BL_X and BL_Y are alternately arranged in the horizontal direction (row direction) as shown in FIG.

[0117] The light receiving section 15 includes a pixel array section 32, a drive control circuit 33, a pulse generating circuit 71, and a controller (control circuit) 72.

[0118] The drive control circuit 33 includes two phase shift circuits 81 and two or more block drive units 82. Note that both or either of the pulse generation circuit 71 and the controller 72 may be configured as part of the drive control circuit 33.

[0119] 10, of the two phase shift circuits 81, the phase shift circuit 81 corresponding to block BL_X is represented as phase shift circuit 81X, and the phase shift circuit 81 corresponding to block BL_Y is represented as phase shift circuit 81Y. Similarly, of the two or more block driver units 82, the block driver unit 82 corresponding to block BL_X is represented as block driver unit 82X, and the block driver unit 82 corresponding to block BL_Y is represented as block driver unit 82Y.

[0120] The pulse generating circuit 71 generates a drive pulse signal based on a light emission control signal of a predetermined frequency (for example, 200 MHz) supplied from the light emission control unit 14, and supplies the drive pulse signal to the phase shift circuits 81X and 81Y.

[0121] More specifically, the pulse generation circuit 71 generates a drive pulse signal whose frequency is synchronized with the light emission control signal from the light emission control unit 14. The pulse generation circuit 71 also shifts the phase of the frequency-synchronized drive pulse signal based on the irradiation timing of the irradiation light, as described in Fig. 10, and supplies the phase shift signals to the phase shift circuits 81X and 81Y. The drive pulse signals output from the pulse generation circuit 71 correspond to the distribution signals DIMIX_A and DIMIX_B described in Fig. 7 and other figures.

[0122] The controller 72 controls the timing of phase change of the phase shift circuits 81X and 81Y, that is, the controller 72 instructs the phase shift circuits 81X and 81Y on the timing of phase change.

[0123] The phase shift circuits 81X and 81Y perform a process of shifting the phase of the drive pulse signals supplied from the pulse generation circuit 71 as necessary, and supply the phase-shifted drive pulse signals (phase-shifted drive pulse signals) to the block driver 82. The phase shift circuits 81X and 81Y generate drive pulse signals that are shifted to a plurality of phases in a time-division manner within one frame period, thereby approximating the irradiated light irradiated as a rectangular wave to a sine wave (pseudo-sine).

[0124] Specifically, the phase shift circuits 81X and 81Y perform processing to shift the phase of the drive pulse signal supplied from the pulse generation circuit 71 by 0°, 45°, or 90° within one frame period in a predetermined order, and supply the shifted drive pulse signal to the block driver 82. In the case of a 0° shift, the drive pulse signal supplied from the pulse generation circuit 71 may be supplied to the block driver 82 as is.

[0125] The timing for changing the phase to be shifted is instructed individually to the phase shift circuits 81X and 81Y by the controller 72. The phase shift circuits 81X and 81Y change the phase to be shifted at the timing instructed by the controller 72.

[0126] The block driving unit 82X supplies the driving pulse signals supplied from the phase shift circuit 81X, i.e., the phase-shifted distribution signals DIMIX_A and DIMIX_B, to each pixel 31 of the corresponding block BL_X, and controls the distribution of the charge generated in the photodiode 51 to tap 52A or tap 52B.

[0127] The block driving unit 82Y supplies the driving pulse signals supplied from the phase shift circuit 81Y, i.e., the phase-shifted distribution signals DIMIX_A and DIMIX_B, to each pixel 31 of the corresponding block BL_Y, and controls the distribution of the charge generated in the photodiode 51 to tap 52A or tap 52B.

[0128] FIG. 11 is a diagram for explaining the phase shift processing by each of the phase shift circuits 81X and 81Y.

[0129] The vertical direction in the blocks BL_X and BL_Y in FIG. 11 represents the time axis within one frame period.

[0130] The phase shift circuit 81X starts from a phase of 0° and shifts the phase by 45° and then 90° in that order every time a predetermined time elapses, according to the timing instructed by the controller 72. After the 90° phase, the phase returns to 0°, and the phase shift process is repeated in the order of 0°, 45°, and 90° until the exposure is completed.

[0131] On the other hand, the phase shift circuit 81Y starts from a phase of 90° and shifts the phase by 0° and 45° in this order every time a predetermined time elapses, in accordance with the timing instructed by the controller 72. After the 45° phase, the phase returns to 90°, and the phase shift process is repeated in the order of 90°, 0°, and 45° until the exposure is completed.

[0132] FIG. 12 shows the charge accumulation time (integration time) for each of the phases of 0°, 45°, and 90°.

[0133] 12A, the controller 72 instructs the phase shift circuit 81 to change the phase at a timing such that the ratio of the period in which the phase shift circuit 81 generates a drive pulse signal with a phase shift of 0°, the period in which the phase shift circuit 81 generates a drive pulse signal with a phase shift of 45°, and the period in which the phase shift circuit 81 generates a drive pulse signal with a phase shift of 90° is 1:√2:1. As a result, the ratio of the charge accumulation times for the phases of 0°, 45°, and 90° is 1:√2:1.

[0134] By setting the ratio of the charge accumulation times for the 0°, 45°, and 90° phases to 1:√2:1, the waveform of the modulated wave can be made to approximate a sine wave, as shown in Fig. 12 B. By adjusting the ratio of the charge accumulation times, the amplitude of the sine wave can be adjusted.

[0135] In order to approximate the rectangular waveform light output from the light-emitting unit 12 to a sine wave, the light emission timing of the light source may be phase-shifted to make it pseudo-sine, as disclosed in Patent Document 1, but pseudo-sine can also be made by phase-shifting the light reception timing on the light-receiving side as shown in Figure 12.

[0136] FIG. 13 shows the phase shift control of each of the block BL_X and the block BL_Y.

[0137] The drive control circuit 33 divides all the pixels of the pixel array unit 32 into two phase control unit blocks of the block BL_X and the block BL_Y, and accumulates charges in the block BL_X and the block BL_Y with different phases as shown in FIG. 13. As a result, the current for driving the pixel 31 is dispersed throughout the pixel array unit 32, so that the decrease in IR drop can be suppressed, and the deterioration of EMC and EMI can also be suppressed.

[0138] Also, the phase shift circuit 81 controls the ratio of the charge accumulation times of the phases of 0°, 45°, and 90° to be 1:√2:1 based on the timing control of the controller 72, so that the modulation wave of the received light can be approximated to a sin wave, and the cyclic error can be reduced.

[0139] Since the integration results of the pixels arranged in each of the block BL_X and the block BL_Y are the same, the pixel data (detection signals A and B) output from each pixel do not require any special correction processing such as correction processing for canceling offsets in the plane (within the area) of the pixel array unit 32.

[0140] Therefore, according to the distance measurement sensor 13, it is possible to realize a drive that achieves both reduction of cyclic error and dispersion of drive current. Also, pixel data (detection signals A and B) similar to those in the case of not performing phase shift can be obtained.

[0141] <Detection by IQ mosaic> Due to the phase shift for pseudo-sin conversion by the plurality of phase shift circuits 81 and the plurality of block drive units 82 described above, and the dispersion of the drive timing in block units, the effects of dispersion of drive current and reduction of cyclic error occur.

[0142] However, as described above, in order for the distance measurement sensor 13 to output one depth map, four frames are required in the 4-phase method, and two frames are required in the 2-phase method. As the number of pixels of the distance measurement sensor 13 increases, there is also a concern that the frame rate may decrease.

[0143] Referring to FIG. 14, a modification of the 2-phase method to output one depth map per frame will be described.

[0144] In the 2-phase method, as shown on the left side of Fig. 14, in the first frame, a detection signal with a phase of 0° is acquired at the tap 52A of each pixel 31, and a detection signal with a phase of 180° is acquired at the tap 52B. Next, in the second frame, a detection signal with a phase of 90° is acquired at the tap 52A of each pixel 31, and a detection signal with a phase of 270° is acquired at the tap 52B. Then, using the four detection signals of the first and second frames, I and Q in equation (4) and the depth value d in equation (1) are calculated.

[0145] If the pixel data of each pixel 31 obtained in the first frame is referred to as I pixel data, which is an in-phase component with respect to the modulated optical wave, and the pixel data of each pixel 31 obtained in the second frame is referred to as Q pixel data, which is an orthogonal phase component with respect to the modulated optical wave, the 2Phase method is a method in which I pixel data is obtained for all pixels in the first frame, and Q pixel data is obtained for all pixels in the second frame.

[0146] In contrast to this, as shown on the right side of Figure 14, by mixing pixels 31 that acquire I pixel data (hereinafter referred to as I pixels) and pixels 31 that acquire Q pixel data (hereinafter referred to as Q pixels), it is possible to acquire detection signals for all phases of 0°, 90°, 180°, and 270° with respect to the modulated light wave in one frame, making it possible to calculate I and Q in equation (4) and find the depth value d. Driving that mixes I pixels and Q pixels in one frame in this way is called IQ mosaic driving.

[0147] 14, driving is performed so that pixels are arranged in the horizontal direction (row direction) in the order of I pixel, I pixel, Q pixel, and Q pixel. In the following explanation, the case where driving is performed so that pixels are arranged in the order of I pixel, I pixel, Q pixel, and Q pixel will be taken as an example, but the present technology can also be applied to other arrangements, for example, cases where driving is performed so that pixels are arranged in the order of I pixel, Q pixel, I pixel, and Q pixel.

[0148] In the IQ mosaic driving of FIG. 14, similar to the above-mentioned 2-phase method, it is not possible to eliminate the characteristic variations between taps that exist in each pixel.

[0149] When priority is given to eliminating the characteristic variations between the taps present in each pixel, as shown in Fig. 15, the drive control circuit 33 performs, in the first frame, the same drive as the IQ mosaic drive for one frame in Fig. 14, and in the second frame, performs IQ mosaic drive in which the phases of the taps 52A and 52B of each pixel 31 are inverted relative to the first frame. In this case, by using the pixel data for the first and second frames to find the difference between detection signals of opposite phases for the same pixel, it is possible to eliminate the characteristic variations between the taps present in each pixel, as with the 4-phase method described above, and it is possible to find the depth value d in fewer frames (two frames) than with the 4-phase method.

[0150] As a countermeasure against a decrease in frame rate due to an increase in the number of pixels in the pixel array section 32, the above-mentioned IQ mosaic driving can be adopted.

[0151] Furthermore, by combining IQ mosaic driving, phase shifting for pseudo-sinification using multiple phase shift circuits 81 and multiple block driving units 82, and distribution of drive timing on a block BL basis, the effects of shortening the frame rate, distributing the drive current, and reducing cyclic errors can be simultaneously achieved.

[0152] <Example of IQ mosaic drive with phase control division number 4> Next, IQ mosaic driving will be described in which all the pixels of the pixel array section 32 are divided into four types of phase control unit blocks, and I pixels and Q pixels are arranged in pixel column units as shown in FIG.

[0153] FIG. 16 is a diagram showing an example of a schematic configuration of the pixel array section 32 and the drive control circuit 33 when the pixel array section 32 is divided into four types of phase control unit blocks and IQ mosaic driving is performed.

[0154] The blocks BL divided into N columns in the pixel array unit 32 are divided into four types: block BL_XI, block BL_YI, block BL_XQ, and block BL_YQ. Blocks BL_XI and BL_YI are blocks BL having pixels 31 driven as I pixels, and blocks BL_XQ and BL_YQ are blocks BL having pixels 31 driven as Q pixels.

[0155] The drive control circuit 33 includes four phase shift circuits 81 and four or more block drive units 82.

[0156] Of the four phase shift circuits 81, the phase shift circuits 81 corresponding to blocks BL_XI, BL_YI, BL_XQ, and BL_YQ are represented as phase shift circuits 81XI, 81YI, 81XQ, and 81YQ, respectively. Similarly, of the four or more block driving units 82, the block driving units 82 corresponding to blocks BL_XI, BL_YI, BL_XQ, and BL_YQ are represented as block driving units 82XI, 82YI, 82XQ, and 82YQ, respectively.

[0157] FIG. 17 shows the phase shift control of each of the blocks BL_XI, BL_YI, BL_XQ, and BL_YQ.

[0158] The ratio of the charge accumulation times for the 0°, 45°, and 90° phases of each pixel 31 is 1:√2 (≈1.4):1, as in the example described above. When the phase of the I pixel is 0°, 45°, or 90°, the phase of the Q pixel is 90°, 135°, or 180°, respectively, and the phases of the I pixel and the Q pixel are orthogonal to each other.

[0159] 17, if there are three types of phase shifts for pseudo-sinusoidal conversion: 0°, 45°, and 90° (90°, 135°, and 180° for Q pixels), and the ratio of the charge accumulation times for the 0°, 45°, and 90° phases is 1:√2 (≈1.4):1, then the phases of the two blocks BL will be the same during some periods indicated by the dashed lines. In other words, the phases of the blocks BL will be different except for some periods indicated by the dashed lines, but the phases cannot be completely dispersed so that the phases of the blocks BL are different throughout the entire frame period.

[0160] Therefore, the drive control circuit 33 performs the phase shift control shown in FIG. 18, thereby making it possible to completely change the phase of each phase control unit block over the entire one frame period.

[0161] FIG. 18 is a diagram showing an example of phase shift control by IQ mosaic driving in which the pixel array section 32 is divided into four types of phase control unit blocks and the phases of the phase control unit blocks are made completely different.

[0162] The drive control circuit 33 sets five types of phase shift for pseudo-sine conversion: 0°, 22.5°, 45°, 67.5°, and 90° in increments of 22.5° (90°, 112.5°, 135°, 157.5°, and 180° for Q pixels), and performs phase shift control by setting the ratio of the charge accumulation times for the phases of 0°, 22.5°, 45°, 67.5°, and 90° to 1:2.6092:3.4071:2.6061:0.9964.

[0163] By performing such control, the phase of each phase control unit block can be set to a different state in any period. For example, in period 101 indicated by the dashed line, blocks BL_XI, BL_YI, BL_XQ, and BL_YQ are controlled to phases of 0°, 45°, 90°, and 135°, respectively, and in period 102 indicated by the dashed line, they are controlled to phases of 45°, 90°, 135°, and 180°, respectively.

[0164] FIG. 19 is a diagram showing the results of a comparison of cyclic errors between exposure control using rectangular pulses and exposure control using pseudo-sine conversion shown in FIG.

[0165] FIG. 19A is a graph showing the cyclic error (CE) in exposure control using a rectangular pulse with a duty of 50%, where the ratio of the High time is 50%.

[0166] FIG. 19B is a graph showing the cyclic error (CE) in exposure control using a rectangular pulse with a duty of 33%, where the ratio of high time is 33%.

[0167] FIG. 19C is a graph showing the cyclic error (CE) in exposure control using the pseudo-sine conversion shown in FIG.

[0168] In each of Figures 19A, 19B, and 19C, the graph on the left shows the integrated waveform obtained by integrating over one frame period, and the graph on the right shows the cyclic error (vertical axis) for each frequency (horizontal axis) obtained by FFT.

[0169] With exposure control using pseudo-sine conversion, as shown in Figure 19C, the cyclic error is almost zero for frequencies other than 200 MHz, the modulation frequency of the light source. In the graph showing the FFT results, the integer values ​​on the horizontal axis multiplied by 100 correspond to the frequency. On the other hand, with exposure control using rectangular pulses, as shown in Figure 19A and B, cyclic errors occur at frequencies other than 200 MHz, the modulation frequency of the light source, and the cyclic errors are particularly large at frequencies that are integer multiples of 200 MHz.

[0170] As described above, according to the exposure control using the pseudo-sine conversion shown in FIG. 18, the drive timing can be completely dispersed, and the cyclic error can be almost completely reduced.

[0171] <About wiring> An explanation will be given below about the wiring when performing IQ mosaic driving so as to form an array of I pixel, I pixel, Q pixel, Q pixel as shown in FIG.

[0172] 20 is a diagram for explaining wiring relating to the connection between the tap 52A and the tap 52B. More specifically, the diagram is for explaining wiring relating to the connection between the transfer transistor 41A included in the tap 52A and the signal line that supplies the distribution signal DIMIX_A to the transfer transistor 41A, and wiring relating to the connection between the transfer transistor 41B included in the tap 52B and the signal line that supplies the distribution signal DIMIX_B to the transfer transistor 41B.

[0173] 20 illustrates 16 pixels 31 arranged in a 4×4 matrix in a pixel array section 32. The arrangement of the 16 pixels shown in FIG. 20 is the same as the arrangement of the 16 pixels shown in the right diagram of FIG. 14. That is, pixels 31-1, 31-5, 31-9, and 31-13 arranged in the first column from the left in the diagram are I pixels. Furthermore, pixels 31-2, 31-6, 31-10, and 31-14 arranged in the second column from the left in the diagram are I pixels.

[0174] Furthermore, pixels 31-3, 31-7, 31-11, and 31-15 arranged in the third column from the left in the drawing are Q pixels, and pixels 31-4, 31-8, 31-12, and 31-16 arranged in the fourth column from the left in the drawing are Q pixels.

[0175] Referring to the first row located at the top of the figure, tap 52A-1 of pixel 31-1, which is an I pixel, is connected to tap 52A-2 of pixel 31-2, which is an I pixel. Tap 52A-1 and tap 52A-2 are also connected to signal line 211-1. This signal line 211-1 is formed in the column direction and is formed on pixels 31-1, 31-5, 31-9, and 31-13, which are arranged in the first column from the left in the figure.

[0176] The taps 52A-1 and 52A-2 are taps that acquire a detection signal at a phase of 0 degrees, and the signal line 211-1 is a signal line for transmitting a signal for driving the transfer transistors 41A included in the taps 52A-1 and 52A-2, respectively, at a phase of 0 degrees.

[0177] The tap 52B-1 of pixel 31-1, which is an I pixel, is connected to the tap 52B-2 of pixel 31-2, which is an I pixel. The taps 52B-1 and 52B-2 are also connected to a signal line 211-3. This signal line 211-3 is formed in the column direction and is formed on the pixels 31-3, 31-7, 31-11, and 31-15, which are arranged in the third column from the left in the figure.

[0178] Taps 52B-1 and 52B-2 are taps that acquire detection signals with a phase of 180 degrees, and signal line 211-3 is a signal line for transmitting signals for driving transfer transistors 41B included in taps 52B-1 and 52B-2, respectively, with a phase of 180 degrees.

[0179] The tap 52A-3 of pixel 31-3, which is the Q pixel, is connected to the tap 52A-4 of pixel 31-4, which is the Q pixel. The taps 52A-3 and 52A-4 are also connected to a signal line 211-2. This signal line 211-2 is formed in the column direction and is formed on the pixels 31-2, 31-6, 31-10, and 31-14, which are arranged in the second column from the left in the drawing.

[0180] The taps 52A-3 and 52A-4 are taps for acquiring detection signals with a phase of 90 degrees, and the signal line 211-2 is a signal line for transmitting signals for driving the transfer transistors 41A included in the taps 52A-3 and 52A-4, respectively, with a phase of 90 degrees.

[0181] The tap 52B-3 of pixel 31-3, which is the Q pixel, is connected to the tap 52B-4 of pixel 31-4, which is the Q pixel. The taps 52B-3 and 52B-4 are also connected to a signal line 211-4. This signal line 211-4 is formed in the column direction and is formed on pixels 31-4, 31-8, 31-12, and 31-16, which are arranged in the fourth column from the left in the drawing.

[0182] Tap 52B-3 and tap 52B-4 are taps that acquire a detection signal with a phase of 270 degrees, and signal line 211-4 is a signal line for transmitting a signal for driving the transfer transistors 41B included in tap 52B-3 and tap 52B-4, respectively, with a phase of 270 degrees.

[0183] The pixels 31 in the second row and thereafter are connected in the same manner as the pixels 31 in the first row. Wiring for such connections is formed in the wiring layer 142 (FIG. 6). The wiring in the wiring layer 142 will be described below.

[0184] <About wiring> The wiring is formed in a multilayer wiring layer 142 (FIG. 6) stacked on a semiconductor substrate 141 on which the PD 51 is formed. Fig. 21 is a plan view of the pixel 31 shown in Fig. 5 with the wiring of the wiring layer M1 added. Fig. 22 is a plan view of the pixel 31 shown in Fig. 5 with the wiring of the wiring layer M2 added.

[0185] 21, a via 311A ​​is formed below TG41A to connect TG251A to wiring formed in another wiring layer. A contact (not shown) to be connected to this via 311A ​​is also formed below TG41A.

[0186] In the above and following explanations, connection includes being physically connected, but also includes being formed so that charges and signals can be read out even if there is no physical contact.

[0187] 21, FD42A-2, FD42A-1, and AMP45A are connected by wiring 331A. Contacts 312A, 313A, and 315A are formed in FD42A-2, FD42A-1, and AMP45A, respectively, and these contacts are connected to wiring 331A.

[0188] This wiring 331A can also be used as a region that constitutes the FD42A. By increasing the wiring length of this wiring 331A, the capacity of the FD42A can be increased. Therefore, as shown in FIG. 22, a wiring 341A that constitutes part of the FD42A is also formed in the wiring layer M2. The wiring 341A is connected to the wiring 331A by a via 314A.

[0189] 21 and 22, the via 314A is formed between the TG41A and the AMP45A. To be connected to the via 314A, a wire 331A is formed in the wiring layer M1, and a wire 341A is formed in the wiring layer M2.

[0190] As described above, the wiring 341A is formed to increase the capacity of the FD42A, and is not a wiring for connection, so it can be omitted. Also, although the explanation will be continued here using an example in which the wiring 341A is formed on the wiring layer M2, the wiring 341A may be formed on a wiring layer M3 or M4 other than the wiring layer M2.

[0191] 21, a wiring 332A is formed in a region below the AMP 45A and the SEL 43A. The wiring 332A is connected to a via 316A formed in the SEL 43A and a contact 317A formed between the RST 44A and the FBEN 46A (a region corresponding to the drain of the reset transistor 44A).

[0192] In the circuit diagram shown in FIG. 7, the wiring 332A corresponds to the parasitic capacitance C_ST. Increasing the capacitance of the parasitic capacitance C_ST can further reduce KTC noise. Therefore, as a region corresponding to the parasitic capacitance C_ST, a wiring 333A is provided on the wiring layer M1 as shown in FIG. 21, and a wiring 342A is provided on the wiring layer M2 as shown in FIG. 22. The portion corresponding to the parasitic capacitance C_ST is made up of the wiring 332A, the wiring 333A, and the wiring 342A.

[0193] The wiring 332A formed in the wiring layer M1 is connected to the via 316A. The wiring 333A formed in the wiring layer M1 is connected to the via 318A. The wiring 342A formed in the wiring layer M2 is connected to the vias 316A and 318A. Therefore, the wiring 332A, the via 316A, the wiring 342A, the via 318A, and the wiring 333A are formed in a connected state, and form a parasitic capacitance C_ST.

[0194] Referring to FIG. 21, the wiring 333A is formed as a wiring extending from the region on the right side of the FD 42A-2 in the figure, passing under the well contact 54 and the PD 51, and extending to the OFD 47.

[0195] The wiring for the tap 52A is formed so as to be in a line-symmetric relationship with the wiring for the tap 52B. The wiring for the tap 52B will be described with reference to FIGS.

[0196] 21, a via 311B is formed below TG41B to connect TG251B to wiring formed in another wiring layer. A contact (not shown) to be connected to this via 311B is also formed below TG41B.

[0197] 21, FD42B-1, FD42B-2, and AMP45B are connected by wiring 331B. Contacts 312B, 313B, and 315B are formed in FD42B-1, FD42B-2, and AMP45B, respectively, and these contacts are connected to wiring 331B.

[0198] 22, a wiring 341B that constitutes a part of the FD42B is also formed in the wiring layer M2. The wiring 341B is connected to the wiring 331B by a via 314B.

[0199] 21, a wiring 332B is formed in a region below AMP45B and SEL43B. This wiring 332B is connected to a via 316B formed in SEL43B and a contact 317B formed between RST44B and FBEN46B (a region corresponding to the drain of the reset transistor 44B).

[0200] The wiring 332B formed in the wiring layer M1 is connected to the via 316B. The wiring 333B formed in the wiring layer M1 is connected to the via 318B. The wiring 342B formed in the wiring layer M2 is connected to the vias 316B and 318B. Therefore, the wiring 332B, the via 316B, the wiring 342B, the via 318B, and the wiring 333B are formed in a connected state, and form a parasitic capacitance C_ST.

[0201] Referring to FIG. 21, the wiring 333B is formed as a wiring extending from the region on the left side of the FD42B-2 in the figure, passing under the well contact 54 and the PD51, and extending to the OFD47.

[0202] In this way, the wiring for the tap 52B is formed so as to be symmetrical with the wiring for the tap 52A.

[0203] The transistors, wiring, etc. included in the tap 52A included in the pixel 31 and the transistors, wiring, etc. included in the tap 52B included in the pixel 31 are arranged so as to be line-symmetrical with respect to the center line L1 of the pixel 31.

[0204] This makes it possible to suppress variations in the lengths of, for example, wiring that contributes to noise cancellation, such as wiring 332 and wiring 333 that correspond to the parasitic capacitance C_ST, etc. This makes it possible to prevent differences in performance related to noise reduction between tap 52A and tap 52B, thereby improving distance measurement accuracy.

[0205] Fig. 23 is a diagram for explaining the wiring of the wiring layer M3, Fig. 24 is a diagram for explaining the wiring of the wiring layer M4, and Fig. 25 is a diagram for explaining the signal lines connected to the contacts provided in the wiring layer M4.

[0206] Since the wiring of the wiring layers M3 and M4 is arranged across multiple pixels 31, in Figures 23 to 25, the configuration of the pixel 31 is simplified, and only the parts necessary for explanation are shown and explained.

[0207] 23 and 24 show pixels 31-1 to 31-4 arranged in the row direction. A contact 361A-1 is formed in a region in wiring layer M3 corresponding to the region where TG45A-1 of pixel 31-1 is formed. This contact 361A-1 is connected to vias 311A ​​formed in wiring layers M1 and M2.

[0208] The via 311A ​​is provided directly below the TG45, is formed to be straight (or have a shape close to a straight line), and is configured to be connected to the contact 361A formed in the wiring layer M3. By shortening the wiring connected to the TG45, it is possible to prevent wiring capacitance (to reduce wiring capacitance).

[0209] Similarly, a contact 361B-1 is formed in a region in the wiring layer M3 corresponding to the region where TG45B-1 of pixel 31-1 is formed. This contact 361B-1 is connected to a via 311B formed in the wiring layers M1 and M2.

[0210] Similarly, a contact 361A-2 is formed in the region of wiring layer M3 corresponding to the region where TG45A-2 of pixel 31-2 is formed, and a contact 361B-2 is formed in the region of wiring layer M3 corresponding to the region where TG45B-2 is formed, and contact 361A-2 and contact 361B-2 are connected to the corresponding vias 311A ​​and 311B, respectively.

[0211] Similarly, a contact 361A-3 is formed in the region of wiring layer M3 corresponding to the region where TG45A-3 of pixel 31-3 is formed, and a contact 361B-3 is formed in the region of wiring layer M3 corresponding to the region where TG45B-3 is formed, and contact 361A-3 and contact 361B-3 are connected to the corresponding vias 311A ​​and 311B, respectively.

[0212] Similarly, a contact 361A-4 is formed in the region of wiring layer M3 corresponding to the region where TG45A-4 of pixel 31-4 is formed, and a contact 361B-4 is formed in the region of wiring layer M3 corresponding to the region where TG45B-4 is formed, and contact 361A-4 and contact 361B-4 are connected to the corresponding vias 311A ​​and 3S11B, respectively.

[0213] The wiring formed in wiring M3 is wiring that connects the taps 52 described with reference to Fig. 20. As described with reference to Fig. 20, the tap 52A-1 of pixel 31-1 and the tap 52A-2 of pixel 31-2 are connected. This connection is realized by connecting the contact 361A-1 of TG45A-1 that constitutes the tap 52A-1 of pixel 31-1 and the contact 361A-2 of TG45A-2 that constitutes the tap 52A-2 of pixel 31-2 by wiring 371 in the wiring layer M3, as shown in Fig. 23.

[0214] The wiring 371 is also connected to a via 363-1. The via 363-1 is formed in a region in the wiring layer M3 corresponding to the region in which the PD51-1 is formed. The via 363-1 is also connected to a contact 381-1 shown in FIG. 24. The contact 381-1 is connected to the signal line 211-1 as shown in FIG. 25.

[0215] 23, a contact 361B-1 of TG45B-1 constituting tap 52B-1 of pixel 31-1 and a contact 361B-2 of TG45B-2 constituting tap 52B-2 of pixel 31-2 are connected by a wiring 372. The wiring 372 is also connected to a via 363-3 formed in a region in the wiring layer M3 corresponding to the region where PD51-3 is formed.

[0216] This via 363-3 is connected to the contact 381-3 shown in Fig. 24. The contact 381-3 is connected to the signal line 211-3 as shown in Fig. 25.

[0217] 23, a contact 361A-3 of TG45A-3 constituting tap 52A-3 of pixel 31-3 and a contact 361A-4 of TG45A-4 constituting tap 52A-4 of pixel 31-4 are connected by a wiring 373. The wiring 373 is also connected to a via 363-2 formed in a region in the wiring layer M3 corresponding to the region where PD51-2 is formed.

[0218] This via 363-2 is connected to the contact 381-2 shown in Fig. 24. The contact 381-2 is connected to the signal line 211-2 as shown in Fig. 25.

[0219] 23, a contact 361B-3 of TG45B-3 constituting tap 52B-3 of pixel 31-3 and a contact 361B-4 of TG45B-4 constituting tap 52B-4 of pixel 31-4 are connected by a wiring 374. The wiring 374 is also connected to a via 363-4 formed in a region in the wiring layer M3 corresponding to the region where PD51-4 is formed.

[0220] This via 363-4 is connected to the contact 381-4 shown in Fig. 24. The contact 381-4 is connected to the signal line 211-4 as shown in Fig. 25.

[0221] Reference will be made to the signal line 211-1 shown in Fig. 25. As in the case described with reference to Fig. 20, the signal line 211-1 is a signal line that is arranged across the pixels 31-1, 31-5, 31-9, and 31-13 that are arranged in the column direction. This signal line 211-1 is also a signal line that transmits a signal that controls the transfer transistor 41A in order to obtain a detection result with a phase of 0 degrees.

[0222] As shown in Fig. 25, the signal line 211-1 is connected to a contact 381-1 provided in a region corresponding to the pixel 31-1. As shown in Fig. 24, the via 363-1 is connected to the contact 381-1. Furthermore, as shown in Fig. 23, the wiring 371 is connected to the via 363-1.

[0223] The wiring 371 is connected to a contact 361A-1, and this contact 361A-1 is connected to a via 311A ​​(FIGS. 21 and 22). Ultimately, the via 311A ​​is connected to a contact formed in TG41A (the gate of the transfer transistor 41A). Therefore, TG41A is connected to a signal line 211-1, and its driving is controlled by a signal from this signal line 211-1.

[0224] The signal lines 211-2 to 211-4 are also connected to the corresponding TG 41, and are configured so that signals for controlling driving are transmitted to the corresponding TG 41. The wiring connecting the signal lines 211-1 to 211-4 and the TG 41 is arranged as described with reference to Fig. 23. Now, refer to Fig. 23 again.

[0225] The wiring 371 connects the contact 361A-1 included in the tap 52A-1 and the contact 361A-2 included in the tap 52A-2. The wiring 371 is also connected to the via 363-1 in the tap 52A-1. The length of the wiring 371 is defined as L1.

[0226] The wiring 372 connects the contact 361B-1 included in the tap 52B-1 and the contact 361B-2 included in the tap 52B-2. The wiring 372 is also connected to the via 363-3 included in the pixel 31-3. The length of the wiring 372 is defined as L2.

[0227] The wiring 373 connects the contact 361A-3 included in the tap 52A-3 and the contact 361A-4 included in the tap 52A-4. The wiring 373 is also connected to the via 363-2 included in the pixel 31-2. The length of the wiring 373 is defined as length L3.

[0228] The wiring 374 connects the contact 361B-3 included in the tap 52B-3 and the contact 361B-4 included in the tap 52B-4. The wiring 371 is also connected to the via 363-4 in the tap 52A-4. The length of the wiring 374 is defined as L4.

[0229] Lengths L1 and L4 are approximately the same. Lengths L1 and L2 are the lengths of the wiring that connects the taps of adjacent pixels (TG45). Lengths L2 and L3 are approximately the same. Lengths L2 and L3 are the lengths of the wiring that connects the taps of adjacent pixels (TG45), and that extend further to the vias of adjacent pixels.

[0230] However, the length L1 (length L4) and the length L2 (length L3) are different lengths. The different lengths of the wiring may cause variations in the parasitic capacitance. To prevent variations in the parasitic capacitance, it may be possible to match the lengths L1 to L4.

[0231] Since the length L1 of the wiring 371 is shorter than the length L3 of the wiring 373, a redundant wiring 375 is added to the wiring 371. If the combined length of the wiring 371 and the redundant wiring 375 is length L5, this length L5 is approximately the same as the length L3 of the wiring 373.

[0232] Note that the explanation here takes as an example a case where the parasitic capacitance is adjusted by adjusting the length of the wiring. Also, the explanation is based on the assumption that if the length of the wiring is the same, the parasitic capacitance is also the same. However, the parasitic capacitance is not determined only by the length of the wiring, but is also related to factors such as the distance from other wiring and the thickness of the wiring.

[0233] Therefore, in order to more accurately match the parasitic capacitance, the combined length L5 of the wiring 371 and the redundant wiring 375 is not only set to the same length as the length L3, but other factors are also taken into consideration when setting the length of the redundant wiring 375.

[0234] The length L5 is set to be approximately the same as the parasitic capacitance of the length L3. In other words, the redundant wiring 375 is a wiring added to the wiring 371 so as to have the same parasitic capacitance as that generated by the wiring 373 of the length L3, and the length of the redundant wiring 375 is set to be the same as the parasitic capacitance generated by the wiring 373 of the length L3.

[0235] Here, the term "redundant wiring" refers to wiring for adjusting parasitic capacitance as described above, and is wiring added to a predetermined wiring. Redundant wiring is wiring formed for purposes other than connecting to contacts, vias, etc., separate from wiring formed for the purpose of connecting to contacts, vias, etc.

[0236] Similarly, because the length L4 of the wiring 374 is shorter than the length L2 of the wiring 373, a redundant wiring 376 is added to the wiring 374. The redundant wiring 376 is a wiring that is added to the wiring 374 so as to have the same parasitic capacitance as that generated by the wiring 372 having the length L2, for example, and the length of the redundant wiring 376 is set to a length that will result in the same parasitic capacitance as that generated by the wiring 372 having the length L2.

[0237] The redundant wiring 375 and the redundant wiring 376 may be provided in a layer different from the layer on which the wirings 371 to 374 are formed. For example, the redundant wiring 375 and the redundant wiring 376 may be formed in a wiring layer M2 or a wiring layer M4 different from the wiring layer M3 on which the wirings 371 to 374 are formed, and may be connected by vias.

[0238] Furthermore, the redundant wiring 375 and the redundant wiring 376 may be formed with a thickness different from that of the wirings 371 to 374. Furthermore, the redundant wiring 375 and the redundant wiring 376 may be formed with a single wire as shown in Fig. 23, or may be formed with multiple wires. Furthermore, the redundant wiring 375 and the redundant wiring 376 may be formed in a straight line as shown in Fig. 23, or may be formed in a shape other than a straight line, for example, a shape having a curve or a loop.

[0239] In the above embodiment, the transfer transistors in the tap are connected, and a redundant wiring is provided for the wiring connected to the transfer transistor. However, the present technology can also be applied to wiring for connecting transistors other than the transfer transistors in the tap.

[0240] The present invention can also be applied to image sensors other than those with a two-tap configuration. For example, the present invention can be applied to an image sensor having one transfer transistor per pixel. When applied to such an image sensor, a redundant wiring can be provided for the wiring connecting predetermined transistors in adjacent pixels.

[0241] In this way, redundant wiring is provided to match the parasitic capacitance. Therefore, it is possible to suppress variations in the parasitic capacitance. When a pixel to which this technology is applied is used as a pixel that performs distance measurement, it becomes possible to perform distance measurement with improved accuracy.

[0242] Here, examples of embodiments in which the arrangement and size of transistors are changed are given, but these arrangements and sizes are merely examples, and the present technology can be applied to arrangements and sizes other than those given here.

[0243] As mentioned above, pixels using this technology are configured so that the regions that make up the FD (floating diffusion region) are distributed across two regions, and by connecting the two regions, they can be treated as a single FD. Distributing the FD across two regions increases the degree of freedom in placement. Also, distributing the FD across two regions makes it possible to form a larger region than if the FD were provided in a single region.

[0244] In the above-described embodiment, the FD may be divided into two areas, or the FD may be divided into more than two areas.

[0245] As described above, a pixel to which this technology is applied is configured to further increase the FD capacitance by providing a conversion efficiency switching transistor (FDG) that converts the FD capacitance and an additional capacitance section. Also, by providing wiring that forms part of the FD in the stacked wiring layer, the FD capacitance can be further increased. For these reasons, a pixel to which this technology is applied can be made to have an increased FD capacitance.

[0246] Furthermore, as described above, pixels to which this technology is applied are provided with a feedback enable transistor (FBEN) and are configured so that the parasitic capacitances C_ST and C_FB can be secured through wiring, thereby reducing noise such as KTC noise.

[0247] Furthermore, as mentioned above, when this technology is applied to a pixel with a two-tap configuration, the transistors and wiring within the taps are arranged in line symmetry within the pixel, eliminating variations in wiring length. Variations in wiring length can cause differences in wiring capacitance, which can lead to problems such as inability to properly suppress noise, but applying this technology can reduce the likelihood of such problems occurring.

[0248] In addition, redundant wiring is provided to match parasitic capacitance, which can suppress variations in parasitic capacitance. When pixels incorporating this technology are used for distance measurement, it becomes possible to perform distance measurement with improved accuracy.

[0249] This technology can be applied to a continuous-wave method, which is an indirect ToF method, in which the light projected onto an object is amplitude-modulated. The photodiode 51 of the light-receiving unit 15 can be applied to distance measuring sensors with a structure that distributes charge between two charge storage units, such as a current-assisted photonic demodulator (CAPD) distance measuring sensor or a gate-type distance measuring sensor that alternately applies pulses to two gates to transfer the charge of the photodiode.

[0250] In addition, in the above-described embodiment, the pixel 31 has been described as having a two-tap structure in which the charge generated in the photodiode 51 is distributed to two taps, tap 52A or tap 52B, but the present technology can also be applied to pixel structures with other numbers of taps, such as a one-tap structure or a four-tap structure.

[0251] <Example of distance measurement sensor chip configuration> FIG. 26 is a perspective view showing an example of the chip configuration of the distance measuring sensor 13. As shown in FIG.

[0252] The distance measuring sensor 13 can be configured, for example, as shown in A of FIG. 26, by a single chip in which a sensor die 651 and a logic die 652 as multiple dies (substrates) are stacked.

[0253] The sensor die 651 includes a sensor section 661 (as a circuit), and the logic die 652 includes a logic section 662.

[0254] The sensor unit 661 includes, for example, a pixel array unit 32 and a drive control circuit 33. The logic unit 662 includes, for example, a pulse generation circuit 71, a controller 72, an AD conversion unit that converts detection signals into AD signals, a signal processing unit 16, and input / output terminals.

[0255] Furthermore, the distance measuring sensor 13 may be configured in three layers by stacking another logic die in addition to the sensor die 651 and logic die 652. Of course, it may also be configured by stacking four or more layers of dies (substrates).

[0256] Alternatively, the distance measuring sensor 13 may be configured, for example, as shown in FIG. 26B, by a first chip 671, a second chip 672, and an interposer substrate 673 on which these are mounted.

[0257] The first chip 671 is formed with, for example, a pixel array unit 32 and a drive control circuit 33. The second chip 672 is formed with a pulse generating circuit 71, a controller 72, an AD conversion unit that converts detection signals into AD signals, a signal processing unit 16, and the like.

[0258] Note that the circuit layout of the sensor die 651 and the logic die 652 in A of Fig. 26 and the circuit layout of the first chip 671 and the second chip 672 in B of Fig. 26 are merely examples and are not limited to these. For example, the signal processing unit 16 that performs processing such as generating a depth map may be provided outside the distance measurement sensor 13 (on a separate chip).

[0259] <Example of electronic device configuration> The above-described distance measuring module 11 can be mounted on electronic devices such as smartphones, tablet terminals, mobile phones, personal computers, game consoles, television sets, wearable terminals, digital still cameras, and digital video cameras.

[0260] FIG. 27 is a block diagram showing an example of the configuration of a smartphone as an electronic device equipped with a distance measuring module.

[0261] 27, a smartphone 701 includes a ranging module 702, an imaging device 703, a display 704, a speaker 705, a microphone 706, a communication module 707, a sensor unit 708, a touch panel 709, and a control unit 710, all connected via a bus 711. In addition, the control unit 710 has functions as an application processing unit 721 and an operation system processing unit 722 by the CPU executing a program.

[0262] 1 is applied to the distance measurement module 702. For example, the distance measurement module 702 is disposed on the front surface of the smartphone 701, and by measuring the distance to the user of the smartphone 701, the distance measurement module 702 can output depth values ​​of the surface shapes of the user's face, hands, fingers, etc. as the distance measurement results.

[0263] The imaging device 703 is disposed on the front surface of the smartphone 701, and captures an image of the user of the smartphone 701 by capturing an image of the user as a subject. Although not shown, the smartphone 701 may also be configured so that another imaging device 703 is disposed on the back surface thereof.

[0264] The display 704 displays an operation screen for performing processing by the application processing unit 721 and the operation system processing unit 722, images captured by the imaging device 703, etc. The speaker 705 and the microphone 706 output the voice of the other party and pick up the voice of the user when making a call using the smartphone 701, for example.

[0265] The communication module 707 performs communication via a communication network. The sensor unit 708 senses speed, acceleration, proximity, etc., and the touch panel 709 acquires touch operations by the user on the operation screen displayed on the display 704.

[0266] The application processing unit 721 performs processing for providing various services via the smartphone 701. For example, the application processing unit 721 can perform processing for creating a computer graphics face that virtually reproduces the user's facial expression based on the depth supplied from the distance measurement module 702 and displaying the face on the display 704. Furthermore, the application processing unit 721 can perform processing for creating, for example, three-dimensional shape data of any three-dimensional object based on the depth supplied from the distance measurement module 702.

[0267] The operation system processing unit 722 performs processing for realizing the basic functions and operations of the smartphone 701. For example, the operation system processing unit 722 can perform processing for authenticating the user's face and unlocking the smartphone 701 based on the depth values ​​supplied from the distance measurement module 702. The operation system processing unit 722 can also perform processing for recognizing the user's gestures based on the depth values ​​supplied from the distance measurement module 702, and processing for inputting various operations in accordance with the gestures.

[0268] The smartphone 701 configured in this manner can generate a depth map with high accuracy and speed by applying the above-described ranging module 11. This allows the smartphone 701 to detect ranging information more accurately.

[0269] <Application to moving objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0270] FIG. 28 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0271] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 28, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0272] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0273] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0274] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0275] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0276] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0277] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0278] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0279] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0280] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to passengers in the vehicle or to the outside of the vehicle. In the example of Fig. 28, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0281] FIG. 29 is a diagram showing an example of the installation position of the imaging unit 12031.

[0282] In FIG. 29, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0283] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0284] 29 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0285] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0286] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0287] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0288] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0289] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present technology.

[0290] The present technologies described in this specification can be implemented independently and singly, unless a contradiction occurs. Of course, any two or more of the present technologies can also be implemented in combination. For example, part or all of the present technologies described in any embodiment can be implemented in combination with part or all of the present technologies described in other embodiments. Furthermore, part or all of any of the present technologies described above can also be implemented in combination with other technologies not described above.

[0291] Also, for example, a configuration described as one device (or processing unit) may be divided and configured as multiple devices (or processing units). Conversely, configurations described above as multiple devices (or processing units) may be combined and configured as one device (or processing unit). Of course, configurations other than those described above may be added to the configuration of each device (or each processing unit). Furthermore, as long as the configuration and operation of the entire system are substantially the same, part of the configuration of one device (or processing unit) may be included in the configuration of another device (or other processing unit).

[0292] Furthermore, in this specification, a system refers to a collection of multiple components (devices, modules (components), etc.), regardless of whether all the components are contained in the same housing. Therefore, multiple devices housed in separate housings and connected via a network, and a single device housed in a single housing with multiple modules, are both systems.

[0293] The effects described in this specification are merely examples and are not limiting, and there may be effects other than those described in this specification.

[0294] The present technology can have the following configurations. (1) a first wiring that connects predetermined transistors in first adjacent pixels with a via that is formed in one of the first adjacent pixels and is connected to a wiring formed in another layer; a second wiring that connects predetermined transistors in second adjacent pixels with a via that is formed in a pixel adjacent to one of the second adjacent pixels and is connected to a wiring formed in another layer; Equipped with The first wiring is connected to a redundant wiring. Image sensor. (2) The layer on which the predetermined transistor is provided and the layer on which the first wiring and the second wiring are provided are different layers. The imaging element according to (1) above. (3) The via is formed in a substantially linear shape. The imaging element according to (1) or (2) above. (4) The pixel is a photoelectric conversion unit that performs photoelectric conversion; a plurality of charge accumulation units that accumulate the charges obtained by the photoelectric conversion units; a plurality of transfer units that transfer charges from the photoelectric conversion unit to each of the plurality of charge accumulation units; Equipped with The predetermined transistor is the transfer unit. The imaging device according to any one of (1) to (3). (5) The pixel is a plurality of reset units that reset each of the plurality of charge accumulation units; a plurality of reset voltage control units that control voltages applied to the plurality of reset units, respectively; a plurality of addition control units that respectively control addition of capacitance to the plurality of charge storage units; Furthermore, Each of the plurality of charge storage sections is composed of a plurality of regions. The imaging element according to (4) above. (6) a plurality of regions constituting the charge accumulation unit are provided on a substrate on which the photoelectric conversion unit is provided; a wiring layer laminated on the substrate, the wiring layer being provided with wiring connecting the plurality of regions; The first wiring and the second wiring are provided in a wiring layer different from the wiring layer. The imaging element according to (5) above. (7) The plurality of charge storage units, the plurality of transfer units, the plurality of reset units, the plurality of reset voltage control units, and the plurality of additional control units are arranged in line symmetry. The imaging element according to (5) or (6) above. (8) a phase shift circuit that generates phase-shifted drive pulse signals by shifting the drive pulse signals generated in response to a light emission control signal that indicates the irradiation timing of the light source to a plurality of phases in a time-division manner within one frame period; The pixel is The light emitted from the light source is reflected by a predetermined object, and the reflected light is photoelectrically converted into electric charges, which are accumulated based on the phase shift drive pulse signal, and a detection signal corresponding to the accumulated electric charges is output. The imaging device according to any one of (1) to (7). (9) The plurality of charge accumulation units include: a first charge accumulation unit that accumulates the charge based on the phase-shifted driving pulse signal; a second charge accumulation unit that accumulates the charges based on a signal whose phase is inverted with respect to the phase-shifted driving pulse signal; Equipped with The imaging element according to (8) above. (10) a light emitting unit that emits irradiation light; a light receiving element that receives light reflected by an object from the light emitting unit; Equipped with The light receiving element is a photoelectric conversion unit that performs photoelectric conversion; a plurality of charge accumulation units that accumulate the charges obtained by the photoelectric conversion units; a plurality of transfer units that transfer charges from the photoelectric conversion unit to each of the plurality of charge accumulation units; a first wiring that connects transfer units in first adjacent pixels with a via that is formed in one of the first adjacent pixels and is connected to a wiring formed in another layer; a second wiring that connects the transfer units in the second adjacent pixels with a via that is formed in a pixel adjacent to one of the second adjacent pixels and is connected to a wiring formed in another layer; Equipped with The first wiring is connected to a redundant wiring. Ranging module. [Explanation of symbols]

[0295] 11 ranging module, 12 light emitting section, 13 ranging sensor, 14 light emitting control section, 15 light receiving section, 16 signal processing section, 21 pixel array section, 23 column signal processing section, 26 pixel drive line, 31 pixel, 32 pixel array section, 33 drive control circuit, 41 transfer transistor, 42 FD section, 43 selection transistor, 44 reset transistor, 45 amplification transistor, 47 discharge transistor, 49 additional capacitance section, 51 photodiode, 52 tap, 53 vertical signal line, 54 well contact, 71 pulse generation circuit, 72 controller, 81 phase shift circuit, 82 block drive section, 101 period, 102 period, 141 semiconductor substrate, 142 multilayer wiring layer, 143 anti-reflection coating, 144 Pixel boundary portion, 145 inter-pixel light shielding film, 146 planarization film, 147 on-chip lens, 151 semiconductor region, 152 semiconductor region, 153 hafnium oxide film, 154 aluminum oxide film, 155 silicon oxide film, 161 inter-pixel isolation portion, 162 interlayer insulating film, 166 via, 211 via, 311 via, 312, 313 contact, 314 via, 315 contact, 316 via, 317 contact, 318 via, 331 to 333, 341 wiring, 361 contact, 363 via, 371 to 374 wiring, 375, 376 redundant wiring, 381 contact

Claims

1. a phase shift circuit that generates phase-shifted drive pulse signals by shifting a drive pulse signal generated in response to a light emission control signal that indicates the irradiation timing of a light source to a plurality of phases in a time-division manner within one frame period; a pixel that accumulates charges obtained by photoelectric conversion of light that is irradiated from the light source and reflected by a predetermined object based on the phase shift drive pulse signal, and outputs a detection signal corresponding to the accumulated charges; a first wiring that connects predetermined transistors in first adjacent pixels with a via that is formed in one of the first adjacent pixels and is connected to a wiring formed in another layer; a second wiring that connects predetermined transistors in second adjacent pixels with a via that is formed in a pixel adjacent to one of the second adjacent pixels and is connected to a wiring formed in another layer; Equipped with The first wiring is connected to a redundant wiring added to a predetermined wiring in order to match the parasitic capacitance. Image sensor.

2. The layer in which the predetermined transistor is provided and the layer in which the first wiring and the second wiring are provided are different layers. The imaging device according to claim 1 .

3. The via is formed in a substantially linear shape. The imaging device according to claim 1 .

4. The pixel is a photoelectric conversion unit that performs photoelectric conversion; a plurality of charge accumulation units that accumulate the charges obtained by the photoelectric conversion units; a plurality of transfer units that transfer charges from the photoelectric conversion unit to each of the plurality of charge accumulation units; Equipped with The predetermined transistor is the transfer unit. The imaging device according to claim 1 .

5. The pixel is a plurality of reset units that reset each of the plurality of charge accumulation units; a plurality of reset voltage control units that control voltages applied to the plurality of reset units, respectively; a plurality of addition control units that respectively control addition of capacitance to the plurality of charge storage units; Furthermore, Each of the plurality of charge storage sections is composed of a plurality of regions. The imaging device according to claim 4 .

6. a plurality of regions constituting the charge accumulation unit are provided on a substrate on which the photoelectric conversion unit is provided; a wiring layer laminated on the substrate, the wiring layer being provided with wiring connecting the plurality of regions; The first wiring and the second wiring are provided in a wiring layer different from the wiring layer. The imaging device according to claim 5 .

7. The plurality of charge storage units, the plurality of transfer units, the plurality of reset units, the plurality of reset voltage control units, and the plurality of additional control units are arranged in line symmetry. The imaging device according to claim 5 .

8. The phase shift circuit shifts the drive pulse signal to a first phase at a first timing within one frame period, and shifts the drive pulse signal to a second phase at a second timing. The imaging device according to claim 1 .

9. The plurality of charge accumulation units include: a first charge accumulation unit that accumulates the charge based on the phase-shifted driving pulse signal; a second charge accumulation unit that accumulates the charges based on a signal whose phase is inverted with respect to the phase-shifted driving pulse signal; Equipped with The imaging device according to claim 4 .

10. a light emitting unit that emits irradiation light; a phase shift circuit that generates phase-shifted drive pulse signals by shifting a drive pulse signal generated in response to a light emission control signal indicating the illumination timing of the light emitting unit to a plurality of phases in a time-division manner within one frame period; a light receiving element that receives light reflected by an object from the light emitting unit; Equipped with The light receiving element is a photoelectric conversion unit that photoelectrically converts light that is irradiated from the light emitting unit and reflected by a predetermined object; a plurality of charge accumulation units that accumulate the charges obtained by the photoelectric conversion units based on the phase shift drive pulse signals; a plurality of transfer units that transfer charges from the photoelectric conversion unit to each of the plurality of charge accumulation units; a first wiring that connects transfer units in first adjacent pixels with a via that is formed in one of the first adjacent pixels and is connected to a wiring formed in another layer; a second wiring that connects the transfer units in the second adjacent pixels with a via that is formed in a pixel adjacent to one of the second adjacent pixels and is connected to a wiring formed in another layer; Equipped with The first wiring is connected to a redundant wiring added to a predetermined wiring in order to match the parasitic capacitance. Ranging module.

Images