Test and measurement device and error detection method

Abstract

To enable error detection even in the presence of influence of sideband signals for a pattern of a main signal of a bus.SOLUTION: A logic circuit 76 in a test and measurement device determines a data sequence from a main signal of a bus received on a main acquisition channel 60 of the test and measurement device, and uses information from an auxiliary (sideband) signal of the bus on an auxiliary channel 81 or 91 of the test and measurement device based upon a protocol associated with the bus so as to perform error detection on the data sequence.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to test and measurement instruments with error detection, and more particularly to test and measurement instruments that utilize sideband signals for error detection. [Background technology]

[0002] Some test and measurement instruments, such as oscilloscopes, have error detection units that can examine a single channel input for signals, such as signals conforming to a particular protocol, in a device under test (DUT), and use a trigger function to lock onto a particular pattern in the signal (continuously capture the pattern). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-041120 [Patent Document 2] Special Publication No. 2017-532627 [Patent Document 3] Japanese Patent Application Publication No. 2019-192204 [Non-patent literature]

[0004] [Non-Patent Document 1] Transistor Technology Special, ed., "Digital Oscilloscope Usage Notes," 5-2 How Trigger Circuits Work, pp. 85-87, Figure 2 (Circuit Block Diagram), Transistor Technology Special for Freshers No. 99, CQ Publishing Co., Ltd., July 1, 2007 [Non-patent document 2] "Introduction to Triggers," Tektronix, published in June 2010. Search for "Introduction to Triggers" [online], [searched November 11, 2020], Internet<http: / / jp.tek.com / > [Non-patent document 3] "6 Series B MSO Mixed Signal Oscilloscope" introduction site, Tektronix, [online], [Retrieved November 11, 2020], Internet<https: / / jp.tek.com / oscilloscope / 6-series-mso-mixed-signal-oscilloscope> [Non-patent document 4] "Display Data Channel" article, Wikipedia (English version), [Online], [Retrieved November 12, 2020], Internet<https: / / en.wikipedia.org / wiki / Display_Data_Channel> Summary of the Invention [Problem to be solved by the invention]

[0005] This oscilloscope or other device can examine the data bit by bit for errors. This approach works well for protocols that have continuous patterns on a single channel that are independent of other signals. However, some protocols have sideband signals that interfere with tracking the pattern of the main signal (see Patent Documents 2 and 3).

[0006] Furthermore, many of these approaches use a clock extracted from the data and are unable to measure the bit error rate (BER) during certain events in the device under test, such as crosstalk occurrences or large fluctuations in power consumption.

[0007] Embodiments of the disclosed apparatus and method address shortcomings in the prior art. [Means for solving the problem]

[0008] Embodiments of the present invention effectively utilize sideband signals (auxiliary signals) to influence the tracking of the main signal pattern, including gating measurements, changing bit rates, changing patterns, and adjusting timing. Embodiments of the present invention also enable the use of discrete clocks or strobes, as well as data-derived clocks. Embodiments also enable the measurement of bit error rates (BERs) during certain device under test (DUT) events, such as crosstalk or large fluctuations in power consumption.

[0009] Aspects, features and advantages of embodiments of the present invention will become apparent from the following description of the embodiments, taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] Figure 1 shows an example of a conventional analog trigger system with error detection capabilities. [Figure 2] Figure 2 shows an example of a conventional digital trigger system with error detection capabilities. [Figure 3] Figure 3 shows an embodiment of a digital trigger system with error detection capabilities. [Figure 4] Figure 4 shows an embodiment of the pattern restriction logic block. DETAILED DESCRIPTION OF THE INVENTION

[0011] 1 shows a conventional example of an oscilloscope architecture with an analog trigger system 20 with error detection. While this description focuses on oscilloscopes as an example, it should be noted that the embodiments used herein are applicable to any test and measurement instrument that receives data patterns through a channel.

[0012] Generally, error detection occurs when a test and measurement instrument receives a signal from a device under test (DUT) on a single channel input and uses a trigger function to lock onto a specific pattern (pattern capture). The user can then examine the pattern for errors. FIG. 1 shows an acquisition channel 10 that acquires an input analog data signal from a DUT (not shown). This signal may undergo signal conditioning, including amplification provided by a preamplifier 12. The acquisition channel then converts the analog signal to digital using an analog-to-digital converter (ADC) 14. The signal is then demultiplexed by a demultiplexer 16, and the qualifying portions may then be stored in an acquisition memory 18.

[0013] The trigger system 20 also receives an input analog data signal (or, as shown in FIG. 1, a conditioned input analog data signal) via a second analog signal path. A single trigger comparator 22 (or multiple comparators) receives this input signal. The trigger comparator 22 may include multiple comparators to handle multilevel logic. These trigger comparators may also receive other input signals, such as one or more external trigger inputs. The trigger comparator 22 typically detects multiple different trigger conditions and sends them as inputs to a trigger state machine 30. The trigger state machine 30 generates an output signal that associates a portion of the input signal with a trigger event. The demultiplexer 16 receives this output signal. Examples of trigger events include edges, pulse widths, runts, glitches, and timeouts (Non-Patent Document 2).

[0014] The path from the trigger comparator 22 to the pattern lock logic block 24 is the beginning of the error detection section. This block can align patterns matching the incoming data to known bit rates and patterns. The pattern lock logic block 24 may have the ability to learn and lock onto short patterns. The pattern comparison block (pattern comparator) 26 compares the matched pattern with the captured pattern once lock is achieved, and the error counter 28 counts errors.

[0015] FIG. 2 shows another conventional example of an error detection unit 40 implemented in a test and measurement instrument with a digital trigger system. In this example, the instrument's acquisition channel similarly receives an analog input signal from the DUT via a preamplifier 42, but the digital input signal to the trigger system comes from the output of an ADC 44, which may also be coupled to acquisition logic 46, which may also have acquisition memory. Because this example instrument has a digital trigger system, a word recognizer, such as word recognizer 48, replaces the comparator 22 used in the analog trigger system example shown in FIG. 1. The word recognizer 48 compares word patterns between the received word and a reference word and detects the levels and edges of the digitized signal, i.e., the pattern of the digital channel input signal. The word recognizer 48 can be configured to output events for either of these. Trigger state machine 56 utilizes the results from word recognition unit 48, and pattern lock logic block 50, pattern comparison block (pattern comparator) 52, and error counter block 54 operate similarly to the example of Figure 1. Block 47 collectively functions as a demultiplexer for the digital signal from ADC 44. Both the systems of Figures 1 and 2 require patterns with a fixed sequence and rate to achieve pattern lock.

[0016] In contrast, the embodiment of the present invention of FIG. 3 utilizes an input signal (i.e., a sideband or auxiliary signal) from another channel (also called a sideband channel) on the received bus signal to qualify the sequence or control the sequence or bit rate used for matching. As described below for several specific scenarios, information on the sideband channel can qualify the sequence. For example, this information may control which sequence or bit rate is used for matching during the comparison process to detect errors. This information ensures that sequences that match the expected pattern have the correct timing and bit rate, thereby improving the accuracy of error detection.

[0017] The acquisition channel 60, which is the main channel of the test and measurement equipment connected to the bus, includes a preamplifier 64 and any other optional conditioning circuitry, and an ADC 66. The output signal of the ADC 66 is demultiplexed by a logic circuit 62, and the parts that meet certain conditions are sent to an acquisition memory 71, where they may be stored. In this example, the logic circuit 62 functions as a demultiplexer. The trigger state machine 72 and error detection block use the output of the word recognition block 63. As in the example of Figure 2, the error detection block includes a pattern lock logic block 65, a pattern comparison block (pattern comparator) 68, and an error counter block 70.

[0018] The embodiment of Figure 3 includes a pattern qualification logic block 76 that utilizes information from at least one sideband signal received on one or more channels other than the main channel (referred to herein as auxiliary channels or inputs). In one embodiment, a first auxiliary input 81 also includes a preamplifier 82, an ADC 84, and a demultiplexer 88 with a word recognizer 86. A second auxiliary input 91 also includes a preamplifier 90, an ADC 92, and a demultiplexer 96 with a word recognizer 94. The pattern qualification logic block 76 utilizes auxiliary inputs 81 and 91.

[0019] Some embodiments may be implemented in a mixed signal oscilloscope (MSO) (see Non-Patent Document 3). A mixed signal oscilloscope is a type of digital storage oscilloscope that displays and compares both analog and digital signals. In these embodiments, the MSO may further include a digital acquisition channel or input 101, such as shown in FIG. 3 as comparator 98 and digital sampler 100.

[0020] Note that in this description, logic 62 is also referred to as a processing element, and its individual components may be various logic elements such as comparators, word recognition, pattern restriction logic 76, etc. One or more of these individual components may be embodied in the form of a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.

[0021] 3, a clock recovery block 78 recovers a clock signal from the output signal of the ADC 66. The multiplexer 74 utilizes the recovered clock and an external clock 102, if provided. If the system uses an external clock 102, it may be derived from a sideband signal on another channel of the bus, or may be provided as an external clock signal source. As noted above, the bus may have sideband signals on channels other than the main channel 60.

[0022] Pattern qualification logic 76 receives one or more output signals from auxiliary inputs 81 and 91 and, if present, digital acquisition input 101. Pattern qualification logic 76 sends signals to error counter 70 and pattern lock logic block 65.

[0023] Figure 4 illustrates an example of pattern restriction logic 76. The embodiment illustrated in Figure 4 is only one example of pattern restriction logic 76. Those skilled in the art will appreciate that there are multiple ways to implement pattern matching logic in pattern restriction logic 76 that can operate simultaneously or sequentially.

[0024] The input signal (main signal) from the main acquisition channel and the input signal (auxiliary signal) from the auxiliary channel are used to input the captured sequence, in parallel or serial, to a pattern matching circuit 110. The pattern matching circuit 110 may include a memory bank 112, which may include a lookup table, and a timing delay element 114. The timing delay element 114 allows the timing of the input sequence to be adjusted to match the pattern. The timing delay element 114 may also be comprised of multiple timing delay elements and multiple logic stages. The output of the pattern matching circuit 110 may be input to a sequence matching circuit 111. The sequence matching circuit 111 may be user-selectable between a protocol-agnostic circuit 116 and a protocol tracking circuit 118. The input signal may be mapped to a sequence in either the matching circuit 116 or 118. If the user specifies that the bus has a specific protocol and that protocol uses sideband signals, the pattern matching circuit sends an output signal to the protocol tracking sequence matching circuit 118. If the user does not specify a specific protocol, the system uses the protocol non-specific sequence matching circuit 116. This process may still refer to a protocol, but the protocol is now non-specific. Circuits 116 and 118 may also include memory and delay elements. The results of either circuit are selected by multiplexer (MUX) 120 and output to acquisition logic and memory, allowing the bit error rate (BER) to be determined.

[0025] The simplest instantiation of a pattern-qualifying logic circuit is a single signal qualifier. An example of this is measuring the BER during a power event. An auxiliary channel is assigned as the qualifier, and the pattern-qualifying logic is configured to reject errors counted while the power supply level is below the criterion. This allows for BER testing during the power optimization process.

[0026] Another level of complexity would be to allow for a known delay between the auxiliary signal and the signal under test (main signal). The pattern qualification logic allows for a delay in the qualification process to account for skew differences between the probing and the DUT.

[0027] The pattern qualification logic embodiment shown in FIG. 4 allows multiple auxiliary signals to be combined into multiple patterns with different skews. This logic can also qualify based on complex sequences of patterns on these auxiliary signals. This logic may be used to decode signals on complex command buses, such as those used in Double Data Rate (DDR) memories like DDR Gen 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM). For example, this logic can be used to qualify and isolate only DDR read data. This logic can also be used on other command buses and packetized sideband buses.

[0028] In an exemplary embodiment, the bus protocol may be HDMI (registered trademark). HDMI has a side (auxiliary) channel called DDC (Display Data Channel) (Non-Patent Document 4). DDC is a 2The DDC bus is based on the Inter-Integrated Circuit (C) bus, which is physically built into the HDMI cable and utilizes the HDMI main high-speed differential signal. Serial packets on the DDC bus determine the bit rate at which HDMI operates. The error detector in Figure 3 can monitor the DDC channel and wait for a command to operate the main channel's high-speed serial bus at the desired data rate. The error detector then operates at this data rate until the user stops it or receives a command to change to a new data rate. These stop or change commands prevent bit error rate (BER) errors from occurring when the error detector loses lock due to a bit rate range change. This technique is important because HDMI has the ability to detect internal errors and change the data rate. Otherwise, the system would simply transition to a lower speed, leaving the user with no way to determine the number of errors, making debugging difficult.

[0029] Sideband communication for some buses is complex enough to require dedicated logic. This dedicated protocol logic can be implemented in an ASIC or FPGA as many different protocol tracking blocks. Alternatively, these blocks can be implemented as FPGA blocks reprogrammed for the current standard as required. A simple example of a unique sideband is the PCI Express (PCIe) 100MHz clock bursts that are used to change the transmitter equalizer settings to comply with the specification. Tracking these bursts of clock is unique to PCIe compliance. This requires tracking the BER for each transmitter equalization setting separately.

[0030] It should be noted that the foregoing description is merely an example of an embodiment and is not intended to limit the scope of the claims, nor should any such limitation be implied.

[0031] Aspects of the present invention may operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers, including processors that operate according to programmed instructions. The terms "controller" or "processor" herein contemplate microprocessors, microcomputers, ASICs, and dedicated hardware controllers, among others. Aspects of the present invention may be implemented in computer-usable data and computer-executable instructions, such as one or more program modules, executed by one or more computers (including a monitoring module) or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform particular tasks or implement particular abstract data formats. Computer-executable instructions may be stored in computer-readable storage media, such as hard disks, optical disks, removable storage media, solid-state memory, RAM, etc. Those skilled in the art will appreciate that the functionality of the program modules may be combined or distributed as desired in various embodiments. Furthermore, such functionality may be embodied in whole or in part in firmware or hardware equivalents, such as integrated circuits, field programmable gate arrays (FPGAs), etc. One or more aspects of the present invention may be more effectively implemented using particular data structures, and such data structures are considered within the scope of the computer-executable instructions and computer-usable data described herein.

[0032] Aspects of the disclosed technology operate in various modifications and alternative forms. Specific aspects have been shown by way of example in the drawings and have been described in detail. However, the embodiments disclosed herein are presented for purposes of clarity of explanation and are not intended to limit the scope of the disclosed general concepts to the specific examples set forth herein, unless expressly so limited. Thus, the present disclosure is intended to cover all modifications, equivalents, and alternatives of the described aspects when viewed in light of the accompanying drawings and claims.

[0033] References in the specification to embodiments, aspects, examples, etc. indicate that the described items may include particular features, structures, or characteristics. However, each disclosed aspect may or may not necessarily include such particular features, structures, or characteristics. Moreover, such phrases do not necessarily refer to the same aspect unless specifically stated otherwise. Furthermore, when a particular feature, structure, or characteristic is described in connection with a particular aspect, such feature, structure, or characteristic may also be used in connection with other disclosed aspects, regardless of whether such feature is explicitly described in connection with such other disclosed aspects.

[0034] The disclosed aspects may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As used herein, computer-readable media refers to any medium that can be accessed by a computing device. By way of example and not limitation, computer-readable media may include computer storage media and communication media.

[0035] "Computer storage media" means any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory and other memory technologies, compact disc read-only memory (CD-ROM), digital video disc (DVD) and other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage and other magnetic storage devices, and any other volatile or nonvolatile, removable or non-removable medium implemented in any technology. "Computer storage media" excludes signals themselves and transitory forms of signal transmission.

[0036] A communication medium means any medium usable for communicating computer-readable information. By way of example, and not limitation, communication media may include coaxial cable, fiber optic cable, air, or any other medium suitable for communicating electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0037] Example The following examples are provided to aid in understanding the technology disclosed in this application. Embodiments of the technology may include one or more of the examples described below, and any combination thereof.

[0038] Example 1 is a test and measurement instrument comprising an input port for receiving a bus that conducts data from a device under test, and a processing element coupled to the input port, wherein the processing element is configured to execute instructions that cause the processing element to perform the following processes: determining a data sequence from a signal (main signal) of the bus received on a main channel of the test and measurement instrument; and adjusting parameters for performing error detection on the data sequence using information based on a protocol associated with the bus from at least one other signal (auxiliary signal) of the bus received on an auxiliary channel of the test and measurement instrument.

[0039] Example 2 is the test and measurement instrument of Example 1, in which the processing element includes a pattern lock circuit, a pattern comparator, and an error counter.

[0040] A third embodiment is the test and measurement instrument of the second embodiment, wherein the processing element further includes a clock recovery circuit.

[0041] Example 4 is the test and measurement instrument of any one of Examples 1 to 3, wherein the processing element includes a trigger state machine and pattern limiting logic.

[0042] Example 5 is the test and measurement instrument of Example 4, in which the pattern limitation logic includes a pattern matching circuit and a sequence matching circuit.

[0043] Example 6 is the test and measurement instrument of Example 5, wherein the pattern matching circuitry includes at least one look-up table and a delay element.

[0044] Example 7 is the test and measurement instrument of Example 6, in which the sequence matching circuit includes a protocol-non-specific sequence matching circuit and a protocol-tracking sequence matching circuit.

[0045] Example 8 is the test and measurement instrument of any of Examples 1 to 7, wherein the auxiliary channel includes a preamplifier, an analog-to-digital converter, and a word recognition unit.

[0046] Example 9 is the test and measurement instrument of any of Examples 1 to 8, wherein the auxiliary channel includes a comparator and a digital sampler.

[0047] Example 10 is a test and measurement device according to any one of Examples 1 to 9, wherein the parameter adjustment process includes at least one of a process of selecting (gating) measurement values, a process of adjusting a bit rate, a process of changing a pattern, and a process of adjusting timing.

[0048] Example 11 is the test and measurement instrument of any of Examples 1 to 12, wherein the processing element is configured as either a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0049] Example 12 is the test and measurement device of any of Examples 1 to 12, wherein the processing element is reprogrammable for different bus protocols.

[0050] Example 13 is the test and measurement instrument of any of Examples 1 to 12, further comprising a user interface, wherein the processing element is further configured to execute instructions that cause the processing element to perform processing to detect errors in the data sequence when a protocol associated with the bus is specified by a user through the user interface.

[0051] Example 14 is the test and measurement instrument of Example 13, wherein the processing element is further configured to execute instructions that cause the processing element to perform processing to detect errors in the data sequence when a protocol associated with the bus is not specified by a user through the user interface.

[0052] Example 15 is a method for performing error detection in a test and measurement instrument, comprising: receiving a bus conducting data from a device under test at an input port of the test and measurement instrument; determining a data sequence from a signal (main signal) on the bus on a main channel of the test and measurement instrument; and utilizing information from at least one other signal (auxiliary signal) on the bus on an auxiliary channel of the test and measurement instrument to detect errors in the data sequence.

[0053] Example 16 is the method of example 15, wherein the process of utilizing information from at least one other signal includes at least one of determining a bit rate, selecting (gating) measurements, modifying a pattern, and adjusting timing in the main channel.

[0054] Example 17 is a method of either of Examples 15 and 16, wherein the process of utilizing information from at least one other signal includes a process of utilizing the other signal (auxiliary signal) in a pattern-limiting circuit within a main channel of the test and measurement instrument.

[0055] Example 18 is a method of any of Examples 15 to 17, wherein the process of utilizing information from at least one other signal includes a process of utilizing a state signal from a trigger state machine in a pattern-limiting circuit within the processing element.

[0056] Example 19 is the method of any of Examples 17 and 18, further comprising generating at least one output signal from the pattern restriction circuit.

[0057] Example 20 is the method of example 19, wherein the at least one output signal includes at least one of an output signal to a pattern lock block and an output signal to an error counter.

[0058] Although specific embodiments of the invention have been illustrated and described for purposes of illustration, it will be appreciated that various modifications can be made therein without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited except as by the appended claims. [Explanation of symbols]

[0059] 10 Acquisition Channels 12 Preamp 14 Analog-to-Digital Converter (ADC) 16 Demultiplexer 18 Acquisition Memory 20 Analog Trigger System 22 Trigger Comparator 24 Pattern Lock Logic Blocks 26 Pattern Comparison Block 28 Error Counter Block 30 Trigger State Machine 40 Error detection unit 42 Preamp 44 ADC 46 Acquisition Logic 47 Demultiplexer 48 Word Recognition Unit 50 Pattern Lock Logic Blocks 52 Pattern Comparison Block 54 Error Counter Block 56 Trigger State Machine 60 main acquisition channels 62 Logic (Processing Elements) 63 Word Recognition Unit 64 Preamp 65 Pattern Lock Logic Blocks 66 ADC 68 Pattern Comparison Block (Pattern Comparator) 70 Error Counter Block 71 Acquisition Memory 72 Trigger State Machine 74 Multiplexer 76 Pattern-limited logic blocks 78 Clock Recovery Block 81 1st auxiliary input (channel) 82 Preamp 84 ADC 86 Word Recognition Unit 88 Demultiplexer 90 Preamp 91 Second auxiliary input (channel) 92 ADC 94 Word Recognition Unit 96 Demultiplexer 98 Comparator 100 Digital Sampler 101 Digital Acquisition Inputs (Channels) 102 External Clock 110 Pattern Matching Circuit 111 Sequence Matching Circuit 112 Memory Bank 116 Protocol-nonspecific circuits 118 Protocol Tracking Circuit 120 Multiplexer

Claims

1. 1. A test and measurement device comprising: an input port for receiving a bus conducting data from a device under test; a processing element coupled to the input port; Equipped with the processing element comprises: determining a data sequence from a main signal of said bus received on a main channel of said test and measurement instrument; adjusting parameters of the data sequence of the main signal to perform error detection on the data sequence using information based on a protocol associated with the bus from at least one sideband signal of the bus received on an auxiliary channel of the test and measurement instrument; a test and measurement instrument configured to execute instructions that cause the processing element to:

2. 2. The test and measurement instrument of claim 1, wherein adjusting the parameters of the data sequence comprises at least one of filtering measurements, adjusting bit rate, changing pattern, and adjusting timing.

3. further comprising a user interface; 3. The test and measurement instrument of claim 1, wherein the processing element is further configured to execute instructions that cause the processing element to perform processing to detect errors in the data sequence when a protocol associated with the bus is specified by a user through the user interface.

4. 1. A method for performing error detection in a test and measurement instrument, comprising: receiving a bus carrying data from a device under test at an input port of the test and measurement instrument; determining a data sequence from a main signal of a bus on a main channel of the test and measurement instrument; adjusting parameters of the data sequence using information from at least one sideband signal of a bus on an auxiliary channel of the test and measurement instrument to detect errors in the data sequence of the main signal; An error detection method comprising:

5. An error detection method as claimed in claim 4, wherein the process of adjusting the parameters of the data sequence includes at least one of the following processes in the main channel: determining the bit rate, selecting the measurement values, changing the pattern, and adjusting the timing.

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