Semiconductor Devices

Abstract

To provide a semiconductor device in which a plurality of semiconductor elements is a packaged in one package, capable of reducing a parasitic inductance and a parasitic resistance.SOLUTION: A semiconductor device A1 includes: a leadframe 4 including a lead 4A, a lead 4B, and a lead 4C which are separated from one another; a semiconductor element 1 having an element obverse face 1a, in which a drain electrode 11, a source electrode 12, and a gate electrode 13 are disposed on the element obverse face 1a; and a semiconductor element 2 having an element obverse face 2a, in which a drain electrode 21, a source electrode 22, and a gate electrode 23 are disposed on the element obverse face 2a. The lead 4A is conducted to the source electrode 12 and the drain electrode 21, the lead 4B is conducted to the source electrode 22 and is adjacent to the lead 4A in an x-direction as viewed in a z-direction, and the lead 4C is conducted to the drain electrode 11 and is adjacent to the lead 4A.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device having a plurality of semiconductor elements mounted thereon. [Background technology]

[0002] Conventionally, semiconductor devices in which multiple semiconductor elements are molded in a single resin member are known. Such semiconductor devices are called system-in-packages. Patent Document 1 discloses a semiconductor device in which two switching elements and a control IC are packaged together. The control IC is a semiconductor element that controls each switching element. Each switching element performs switching operation in response to a signal from the control IC. Such semiconductor devices are mounted on a circuit board of an electronic device, for example, and used in power supply circuits such as DC / DC converters. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-218309 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, with the trend toward more energy-efficient and higher performance electronic devices, semiconductor devices are being required to reduce power consumption and improve switching response. Reducing parasitic inductance and parasitic resistance is effective in reducing power consumption and improving switching response.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device in which a plurality of semiconductor elements are packaged together, and which is designed to reduce parasitic inductance and parasitic resistance. [Means for solving the problem]

[0006] The semiconductor device provided by the present disclosure comprises a conductive member including a first conductor, a second conductor, and a third conductor spaced apart from one another; a first semiconductor element having a first main surface and a first drain electrode, a first source electrode, and a first gate electrode arranged on the first main surface; and a second semiconductor element having a second main surface and a second drain electrode, a second source electrode, and a second gate electrode arranged on the second main surface, wherein the first conductor is conductive to the first source electrode and the second drain electrode, the second conductor is conductive to the second source electrode, and, when viewed in a first direction perpendicular to the first main surface, is adjacent to each other in a second direction perpendicular to the first direction, and the third conductor is conductive to the first drain electrode, and, when viewed in the first direction, is adjacent to each of the first conductor and the second conductor. [Effects of the Invention]

[0007] According to the semiconductor device of the present disclosure, it is possible to reduce parasitic inductance and parasitic resistance in a semiconductor device in which a plurality of semiconductor elements are packaged. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a perspective view showing a semiconductor device according to a first embodiment. [Figure 2] 2 is a perspective view of FIG. 1 in which a sealing member is shown by imaginary lines. [Figure 3] 1 is a perspective view (as viewed from the bottom surface side) showing a semiconductor device according to a first embodiment. [Figure 4] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 5] FIG. 5 is a partially enlarged view of a part of the plan view of FIG. 4. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9]1 is a circuit configuration diagram showing a power conversion device according to a first embodiment. [Figure 10] 1 is a perspective view showing a power conversion device according to a first embodiment. [Figure 11] 1 is a plan view showing a power conversion device according to a first embodiment. [Figure 12] FIG. 10 is a plan view showing a power conversion device according to a second embodiment. [Figure 13] FIG. 10 is a circuit configuration diagram showing a power conversion device according to a second embodiment. [Figure 14] FIG. 10 is a plan view showing a power conversion device according to a third embodiment. [Figure 15] FIG. 11 is a plan view showing a power conversion device according to a modified example of the third embodiment. [Figure 16] FIG. 10 is a plan view showing a power conversion device according to a fourth embodiment. [Figure 17] FIG. 11 is a plan view showing a power conversion device according to a modified example of the fourth embodiment. [Figure 18] FIG. 10 is a plan view showing a power conversion device according to a fifth embodiment. [Figure 19] FIG. 10 is a plan view showing a power conversion device according to a sixth embodiment. [Figure 20] FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 19. [Figure 21] FIG. 12 is a plan view showing a power conversion device according to a seventh embodiment. [Figure 22] FIG. 13 is a plan view showing a power conversion device according to an eighth embodiment. [Figure 23] FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 22. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the accompanying drawings. Identical or similar components are designated by the same reference numerals and will not be described again.

[0010] In this disclosure, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B when viewed in a certain direction" and "an object A overlaps a part of an object B when viewed in a certain direction." Furthermore, terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not necessarily intended to assign an order to the objects.

[0011] A semiconductor device A1 according to a first embodiment will be described with reference to Figures 1 to 11. The semiconductor device A1 is used in a power conversion device such as an inverter or a converter.

[0012] 1 to 8 show the module structure of a semiconductor device A1 according to a first embodiment. In its module structure, the semiconductor device A1 includes two semiconductor elements 1 and 2, a control element 3, a lead frame 4, a plurality of wires 5A to 5L, and a sealing member 6. In the semiconductor device A1, the lead frame 4 includes a plurality of leads 4A to 4H that are separated from one another.

[0013] FIG. 1 is a perspective view showing a semiconductor device A1. FIG. 2 is a view showing the sealing member 6 in the perspective view of FIG. 1 by an imaginary line (two-dot chain line). FIG. 3 is a perspective view showing the semiconductor device A1 as seen from the bottom side. FIG. 4 is a plan view showing the semiconductor device A1 by an imaginary line (two-dot chain line). FIG. 5 is a partially enlarged view of a part of FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4.

[0014] For ease of explanation, three mutually orthogonal directions are defined as the x-direction, y-direction, and z-direction. The z-direction is the thickness direction of the semiconductor device A1. The x-direction is the left-right direction in the plan view of the semiconductor device A1 (see FIG. 4). The y-direction is the up-down direction in the plan view of the semiconductor device A1 (see FIG. 4). One of the x-directions is the x1-direction, and the other of the x-directions is the x2-direction. Similarly, one of the y-directions is the y1-direction, the other of the y-directions is the y2-direction, one of the z-directions is the z1-direction, and the other of the z-directions is the z2-direction. In the present disclosure, the z1-direction may be referred to as down, and the z2-direction as up. The z-direction corresponds to the "first direction" in the claims, the x-direction corresponds to the "second direction" in the claims, and the y-direction corresponds to the "third direction" in the claims.

[0015] The semiconductor device A1 is mounted on a circuit board of an electronic device, etc. The semiconductor device A1 has, for example, a surface-mount package structure, and in this embodiment, for example, a package format called SON (Small Outline Non-lead).

[0016] The two semiconductor elements 1 and 2 are elements that perform the electrical functions of the semiconductor device A1. Each of the semiconductor elements 1 and 2 is a switching element, and in this disclosure, is a MOSFET. Note that each of the semiconductor elements 1 and 2 is not limited to a MOSFET, and may be a field-effect transistor including a MISFET (Metal-Insulator-Semiconductor FET) or a HEMT (High Electron Mobility Transistor), a bipolar transistor, or another transistor such as an IGBT (Insulated Gate Bipolar Transistor). Furthermore, each of the semiconductor elements 1 and 2 may be an n-type MOSFET or a p-type MOSFET. Each of the semiconductor elements 1 and 2 is preferably a trench gate type, but may also be a planar gate type.

[0017] As shown in FIG. 4, each of the semiconductor elements 1 and 2 is, for example, rectangular in plan view (as viewed in the z direction). As shown in FIGS. 2 and 4, the semiconductor element 1 is mounted on a lead 4A, and the semiconductor element 2 is mounted on a lead 4B. The constituent material of each of the semiconductor elements 1 and 2 includes, for example, GaN (gallium nitride). Note that the constituent material of each of the semiconductor elements 1 and 2 is not limited to GaN, and may include, for example, SiC (silicon carbide), Si (silicon), GaAs (gallium arsenide), or Ga2O3 (gallium oxide). The semiconductor element 1 corresponds to a "first semiconductor element" set forth in the claims, and the semiconductor element 2 corresponds to a "second semiconductor element" set forth in the claims.

[0018] As shown in FIG. 6, the semiconductor element 1 has an element main surface 1a and an element back surface 1b. The element main surface 1a and the element back surface 1b are spaced apart in the z direction. The element main surface 1a faces the z2 direction, and the element back surface 1b faces the z1 direction. In this example, the element main surface 1a and the element back surface 1b are perpendicular to the z direction. The element back surface 1b faces the lead 4A. The element main surface 1a corresponds to the "first main surface" in the claims, and the element back surface 1b corresponds to the "first back surface" in the claims.

[0019] The semiconductor element 1 is a three-terminal element having three electrodes. In this embodiment, the semiconductor element 1 includes a drain electrode 11, a source electrode 12, and a gate electrode 13, as shown in FIGS. 4, 5, and 6. The drain electrode 11, the source electrode 12, and the gate electrode 13 are arranged on the element's main surface 1a, as shown in FIG. 6. The drain electrode 11 corresponds to a "first drain electrode" in the claims, the source electrode 12 corresponds to a "first source electrode" in the claims, and the gate electrode 13 corresponds to a "first gate electrode" in the claims.

[0020] As shown in FIG. 5, the drain electrode 11 includes a plurality of pad portions 111. Each pad portion 111 has a strip shape extending in a first extension direction. In the example shown in FIG. 5, each pad portion 111 extends in the y direction, which is approximately the same as the first extension direction. Each pad portion 111 is electrically connected to the drain region inside the semiconductor element 1. The pad portion 111 corresponds to a "first drain pad portion" in the claims.

[0021] As shown in FIG. 5, the source electrode 12 includes a plurality of pad portions 121. Like the pad portions 111, each pad portion 121 has a strip shape extending in the first extension direction. In the example shown in FIG. 5, each pad portion 121 extends in the y direction. Each pad portion 121 is electrically connected to the source region inside the semiconductor element 1. The pad portion 121 corresponds to a "first source pad portion" recited in the claims.

[0022] The pads 111 and 121 are arranged alternately in a first arrangement direction, which is substantially perpendicular to the first extension direction, and when the first extension direction substantially coincides with the y direction, the first arrangement direction substantially coincides with the x direction.

[0023] As shown in FIG. 5, the gate electrode 13 includes two pad portions 131 and 132. Each of the pad portions 131 and 132 is electrically connected to a gate region (channel region) inside the semiconductor element 1. The two pad portions 131 and 132 are arranged near the edge of the element main surface 1a on the y1 direction side and are spaced apart from each other in the x direction. In the example shown in FIG. 5, the pad portion 131 is arranged at a corner on the x2 direction side and the y1 direction side in a plan view. The pad portion 132 is arranged at a corner on the x1 direction side and the y1 direction side in a plan view. Both of the two pad portions 131 and 132 are at the same potential. Note that the gate electrode 13 does not necessarily have to include the pad portion 132.

[0024] The semiconductor element 1 receives a drive signal from the control element 3 and switches between a conductive state and a cut-off state (performs a switching operation) in response to the drive signal. The drive signal is input to the gate electrode 13 (pad portion 131) via the wire 5E.

[0025] As shown in FIG. 7, the semiconductor element 2 has an element main surface 2a and an element back surface 2b. The element main surface 2a and the element back surface 2b are spaced apart in the z direction. The element main surface 2a faces the z2 direction, and the element back surface 2b faces the z1 direction. In this example, the element main surface 2a and the element back surface 2b are perpendicular to the z direction. The element back surface 2b faces the lead 4B. The element main surface 2a corresponds to the "second main surface" in the claims, and the element back surface 2b corresponds to the "second back surface" in the claims.

[0026] The semiconductor element 2 is a three-terminal element having three electrodes. In this embodiment, the semiconductor element 2 includes a drain electrode 21, a source electrode 22, and a gate electrode 23, as shown in FIGS. 4, 5, and 7. The drain electrode 21, the source electrode 22, and the gate electrode 23 are arranged on the element main surface 2a, as shown in FIG. 7. The drain electrode 21 corresponds to a "second drain electrode" in the claims, the source electrode 22 corresponds to a "second source electrode" in the claims, and the gate electrode 23 corresponds to a "second gate electrode" in the claims.

[0027] As shown in FIG. 5, the drain electrode 21 includes a plurality of pad portions 211. Each pad portion 211 is strip-shaped and extends in the second extension direction. The second extension direction is inclined at an angle of 10° to 170° with respect to the first extension direction. That is, the angle between the first extension direction and the second extension direction is 10° to 170°. In the example shown in FIG. 5, each pad portion 211 extends in the x-direction, and the second extension direction and the x-direction approximately coincide with each other. That is, in the example shown in FIG. 5, the angle between the first extension direction and the second extension direction is approximately 90°. Each pad portion 211 is electrically connected to a drain region inside the semiconductor element 2. The pad portion 211 corresponds to a "second drain pad portion" in the claims.

[0028] As shown in FIG. 5, the source electrode 22 includes a plurality of pad portions 221. Like the pad portions 211, each pad portion 221 has a strip shape extending in the second extension direction. In the example shown in FIG. 5, each pad portion 221 extends in the x-direction. Each pad portion 221 is electrically connected to the source region inside the semiconductor element 2. The pad portion 221 corresponds to a "second source pad portion" recited in the claims.

[0029] The pads 211 and 221 are arranged alternately in a first arrangement direction. The second arrangement direction is a direction substantially perpendicular to the second extension direction, and when the second extension direction substantially coincides with the x direction, the second arrangement direction substantially coincides with the y direction.

[0030] As shown in FIG. 5, the gate electrode 23 includes two pad portions 231 and 232. Each of the pad portions 231 and 232 is electrically connected to a gate region (channel region) inside the semiconductor element 2. The two pad portions 231 and 232 are arranged near the edge of the element main surface 2a on the x2 direction side and are spaced apart from each other in the y direction. In the example shown in FIG. 5, the pad portion 231 is arranged at a corner on the x2 direction side and the y1 direction side in a plan view. The pad portion 232 is arranged at a corner on the x2 direction side and the y2 direction side in a plan view. Both of the two pad portions 231 and 232 are at the same potential. Note that the gate electrode 23 does not necessarily have to include the pad portion 232.

[0031] The semiconductor element 2 receives a drive signal from the control element 3 and switches between a conductive state and a cut-off state (performs a switching operation) in response to the drive signal. The drive signal is input to the gate electrode 23 (pad portion 231) via the wire 5F.

[0032] The control element 3 controls the switching operations of the two semiconductor elements 1 and 2. The control element 3 generates a drive signal for driving each of the semiconductor elements 1 and 2, and outputs the generated drive signal to each of the semiconductor elements 1 and 2. The control element 3 is, for example, an IC (integrated circuit). The control element 3 is a semiconductor element that includes a semiconductor material. As shown in FIGS. 2 and 4, the control element 3 is mounted on a lead 4D. In the example shown in FIG. 4, the control element 3 overlaps a portion of each of the semiconductor elements 1 and 2 when viewed in the y direction.

[0033] 8, the control element 3 has an element principal surface 3a and an element rear surface 3b. The element principal surface 3a and the element rear surface 3b are spaced apart in the z direction. The element principal surface 3a faces the z2 direction, and the element rear surface 3b faces the z1 direction. The element rear surface 3b faces the lead 4D.

[0034] As shown in Fig. 4, the control element 3 includes a plurality of element electrodes 31 to 38. The plurality of element electrodes 31 to 38 are arranged on the element main surface 3a. The element electrodes 31 to 38 are input terminals or output terminals of the control element 3. The arrangement of the element electrodes 31 to 38 in a plan view is not limited to the example shown in Fig. 4.

[0035] As shown in FIG. 4, the element electrode 31 is joined to one end of a wire 5J, and is electrically connected to the lead 4F via the wire 5J.

[0036] As shown in FIG. 4, one end of a wire 5H is joined to the element electrode 32, and the element electrode 32 is electrically connected to the lead 4D via the wire 5H.

[0037] As shown in FIG. 4, one end of a wire 5K is joined to the element electrode 33, and the element electrode 33 is electrically connected to the lead 4G via the wire 5K.

[0038] As shown in FIG. 4, one end of a wire 5L is joined to the element electrode 34, and the element electrode 34 is electrically connected to the lead 4H via the wire 5L.

[0039] 4, one end of a wire 5E is joined to the element electrode 35, and the element electrode 35 is electrically connected to the gate electrode 13 (pad portion 131) of the semiconductor element 1 via the wire 5E. A drive signal (first drive signal) that controls the switching operation of the semiconductor element 1 is output from the element electrode 35. The element electrode 35 corresponds to a "first element electrode" recited in the claims.

[0040] 4, one end of a wire 5F is joined to the element electrode 36, and the element electrode 36 is electrically connected to the gate electrode 23 (pad portion 231) of the semiconductor element 2 via the wire 5F. A drive signal (second drive signal) that controls the switching operation of the semiconductor element 2 is output from the element electrode 36. The element electrode 36 corresponds to a "second element electrode" recited in the claims.

[0041] As shown in FIG. 4, the element electrode 37 is connected to one end of a wire 5I, and is electrically connected to the lead 4E via the wire 5I.

[0042] As shown in FIG. 4, one end of a wire 5G is joined to the element electrode 38, and the element electrode 38 is electrically connected to the lead 4A via the wire 5G.

[0043] The lead frame 4 has two semiconductor elements 1 and 2 and a control element 3 mounted thereon. The lead frame 4, together with a plurality of wires 5A to 5L, forms a conductive path in the semiconductor device A1. The lead frame 4 is made of a conductive material. The constituent material of the lead frame 4 is, for example, a metal containing Cu (copper). However, the constituent material may be a metal other than Cu. Furthermore, the surface of the lead frame 4 may be appropriately plated. As shown in FIG. 4, the lead frame 4 includes a plurality of leads 4A to 4H that are spaced apart from one another. As shown in FIG. 3, a portion of each of the plurality of leads 4A to 4H is exposed from the sealing member 6, and this exposed portion serves as a terminal when the semiconductor device A1 is mounted on an external circuit board (for example, a circuit board B1 described below).

[0044] As shown in Fig. 4, the lead 4A carries the semiconductor element 1. One end of each of a plurality of wires 5B is joined to the lead 4A, and the lead 4A is electrically connected to the source electrode 12 of the semiconductor element 1 via the plurality of wires 5B. One end of each of a plurality of wires 5C is joined to the lead 4A, and the lead 4A is electrically connected to the drain electrode 21 of the semiconductor element 2 via the plurality of wires 5C. One end of a wire 5G is joined to the lead 4A, and the lead 4A is electrically connected to the element electrode 38 of the control element 3 via the wire 5G.

[0045] 4, the lead 4B carries the semiconductor element 2. One end of each of a plurality of wires 5D is joined to the lead 4B, and the lead 4B is electrically connected to the source electrode 22 of the semiconductor element 2 via the plurality of wires 5D.

[0046] As shown in FIG. 4, the lead 4C is joined to one end of each of a plurality of wires 5A, and is electrically connected to the drain electrode 11 of the semiconductor element 1 via the plurality of wires 5A.

[0047] 4, the lead 4D carries the control element 3. One end of a wire 5H is joined to the lead 4D, and the lead 4D is electrically connected to the element electrode 32 of the control element 3 via the wire 5H.

[0048] As shown in FIG. 4, one end of a wire 5I is joined to the lead 4E, and the lead 4E is electrically connected to the element electrode 37 of the control element 3 via the wire 5I.

[0049] As shown in FIG. 4, one end of a wire 5J is joined to the lead 4F, and the lead 4F is electrically connected to the element electrode 31 of the control element 3 via the wire 5J.

[0050] As shown in FIG. 4, one end of a wire 5K is joined to the lead 4G, and the lead 4G is electrically connected to the element electrode 33 of the control element 3 via the wire 5K.

[0051] As shown in FIG. 4, one end of a wire 5L is joined to the lead 4H, and the lead 4H is electrically connected to the element electrode 34 of the control element 3 via the wire 5L.

[0052] In the lead frame 4, the leads 4A to 4H have the following positional relationship as shown in FIG.

[0053] Lead 4A and lead 4B are adjacent to each other in the x direction in a plan view. An insulating region 49A (shown by a dot in FIG. 4 for ease of understanding) is interposed between lead 4A and lead 4B. Lead 4A and lead 4B overlap when viewed in the x direction. Insulating region 49A corresponds to a "second insulating region" described in the claims.

[0054] Lead 4A and lead 4C are adjacent to each other in the y direction in a plan view. An insulating region 49B (shown by a dot in FIG. 4 for ease of understanding) is interposed between lead 4A and lead 4C. Lead 4A and lead 4C overlap when viewed in the y direction. Insulating region 49B corresponds to the "first insulating region" described in the claims.

[0055] Lead 4B and lead 4C are adjacent to each other in the x direction in a plan view. An insulating region 49C (shown by a dot in FIG. 4 for ease of understanding) is interposed between lead 4B and lead 4C. Lead 4B and lead 4C overlap when viewed in the x direction.

[0056] The lead 4C is arranged in a first extension direction relative to the semiconductor element 1, and the lead 4A is arranged in a second extension direction relative to the semiconductor element 2.

[0057] Both lead 4A and lead 4B are disposed further in the y2 direction than lead 4D. Both lead 4A and lead 4B overlap lead 4D when viewed in the y direction, but do not overlap lead 4D when viewed in the x direction.

[0058] Lead 4E, lead 4F, lead 4G, and lead 4H each overlap lead 4D when viewed in the x direction. Lead 4E and lead 4F overlap lead 4A and lead 4C when viewed in the y direction, and lead 4G and lead 4H overlap lead 4B when viewed in the y direction. Lead 4E and lead 4G overlap when viewed in the x direction, and lead 4F and lead 4H overlap when viewed in the x direction. Lead 4D has a protrusion that protrudes in the x2 direction, and this protrusion is located between lead 4G and lead 4H in the y direction.

[0059] In the lead frame 4, leads 4C, 4A, 4E, and 4F are lined up in this order along the edge on the x1 direction side, and leads 4B, 4G, the protruding portions of lead 4D, and lead 4H are lined up in this order along the edge on the x2 direction side. Furthermore, in the lead frame 4, leads 4F, 4D, and 4H are lined up in this order along the edge on the y1 direction side, and leads 4C and 4B are lined up in this order along the edge on the y2 direction side.

[0060] In this embodiment, the lead frame 4 corresponds to the "conductive member" recited in the claims. The lead 4A corresponds to the "first conductor" recited in the claims. The lead 4B corresponds to the "second conductor" recited in the claims. The lead 4C corresponds to the "third conductor" recited in the claims. The lead 4D corresponds to the "fourth conductor" recited in the claims. The lead 4E corresponds to the "fifth conductor" recited in the claims. The lead 4F corresponds to the "sixth conductor" recited in the claims. The lead 4G corresponds to the "seventh conductor" recited in the claims. The lead 4H corresponds to the "eighth conductor" recited in the claims.

[0061] Each of the wires 5A to 5L electrically connects two spaced apart components. The wires 5A to 5L are so-called bonding wires. The wires 5A to 5L are made of a conductive material. The wires 5A to 5L may be made of a metal containing gold (Au), aluminum (Al), or copper (Cu). In the example shown in FIG. 4, the diameters (thicknesses) of the wires 5A to 5D are larger than those of the wires 5E to 5L, but they may be the same or smaller. The number of wires 5A to 5L is not limited to the number shown in FIG. 2 and may be changed as appropriate, taking into consideration the configurations (planar area, arrangement, number, etc.) of the pads 111, 121, 131, 132, 211, 221, 231, and 232 and the element electrodes 31 to 38, the diameters of the wires 5A to 5L, and the amount of current flowing through the wires 5A to 5L.

[0062] As shown in FIGS. 4 and 5, one end of each of the plurality of wires 5A is joined to the drain electrode 11 (one of the plurality of pad portions 111) of the semiconductor element 1, and the other end is joined to the lead 4C. In the example shown in FIGS. 4 and 5, three wires 5A are joined to each of the three pad portions 111. Each wire 5A electrically connects the drain electrode 11 (each pad portion 111) and the lead 4C. As shown in FIG. 4, each wire 5A overlaps the insulating region 49B in plan view.

[0063] 4 and 5, one end of each of the plurality of wires 5B is joined to the source electrode 12 (one of the plurality of pad portions 121) of the semiconductor element 1, and the other end is joined to the lead 4A. In the example shown in FIGS. 4 and 5, three wires 5B are joined to each of the two pad portions 121. Each wire 5B electrically connects the source electrode 12 (each pad portion 121) and the lead 4A.

[0064] As shown in FIGS. 4 and 5, one end of each of the plurality of wires 5C is joined to the drain electrode 21 (one of the plurality of pad portions 211) of the semiconductor element 2, and the other end is joined to the lead 4A. In the example shown in FIGS. 4 and 5, three wires 5C are joined to each of the three pad portions 211. Each wire 5C electrically connects the drain electrode 21 (each pad portion 211) and the lead 4A. As shown in FIG. 4, each wire 5C overlaps the insulating region 49A in plan view.

[0065] 4 and 5, one end of each of the plurality of wires 5D is joined to the source electrode 22 (one of the plurality of pad portions 221) of the semiconductor element 2, and the other end is joined to the lead 4B. In the example shown in FIGS. 4 and 5, three wires 5D are joined to each of the two pad portions 221. Each wire 5D electrically connects the source electrode 22 (each pad portion 221) and the lead 4B.

[0066] As shown in Fig. 4, one end of the wire 5E is joined to the element electrode 35 of the control element 3, and the other end is joined to the gate electrode 13 (pad portion 131) of the semiconductor element 1. The wire 5E electrically connects the element electrode 35 and the gate electrode 13 (pad portion 131). As shown in Fig. 4, the wire 5E overlaps only the leads 4A and 4D of the lead frame 4 in a plan view. In other words, the wire 5E does not overlap the leads 4B, 4C, 4E to 4H in a plan view.

[0067] As shown in Fig. 4, one end of the wire 5F is joined to the element electrode 36 of the control element 3, and the other end is joined to the gate electrode 23 (pad portion 231) of the semiconductor element 2. The wire 5F electrically connects the element electrode 36 and the gate electrode 23 (pad portion 231). As shown in Fig. 4, the wire 5F overlaps only the leads 4B and 4D of the lead frame 4 in a plan view. In other words, the wire 5F does not overlap the leads 4A, 4C, 4E to 4H in a plan view.

[0068] 4, one end of the wire 5G is joined to the element electrode 38 of the control element 3, and the other end is joined to the lead 4A. The wire 5G electrically connects the element electrode 38 and the lead 4A.

[0069] 4, one end of the wire 5H is joined to the element electrode 32 of the control element 3, and the other end is joined to the lead 4D. The wire 5H electrically connects the element electrode 32 and the lead 4D.

[0070] 4, one end of the wire 5I is joined to the element electrode 37 of the control element 3, and the other end is joined to the lead 4E. The wire 5I electrically connects the element electrode 37 and the lead 4E.

[0071] 4, one end of the wire 5J is joined to the element electrode 31 of the control element 3, and the other end is joined to the lead 4F. The wire 5J electrically connects the element electrode 31 and the lead 4F.

[0072] 4, one end of the wire 5K is joined to the element electrode 33 of the control element 3, and the other end is joined to the lead 4G. The wire 5K electrically connects the element electrode 33 and the lead 4G.

[0073] 4, one end of the wire 5L is joined to the element electrode 34 of the control element 3, and the other end is joined to the lead 4H. The wire 5L electrically connects the element electrode 34 and the lead 4H.

[0074] In this embodiment, wire 5A corresponds to the "first connecting member" in the claims. Wire 5B corresponds to the "second connecting member" in the claims. Wire 5C corresponds to the "third connecting member" in the claims. Wire 5D corresponds to the "fourth connecting member" in the claims. Wire 5E corresponds to the "fifth connecting member" in the claims. Wire 5F corresponds to the "sixth connecting member" in the claims.

[0075] The sealing member 6 is a protective member for the semiconductor elements 1 and 2 and the control element 3. As shown in FIG. 2, the sealing member 6 covers the semiconductor elements 1 and 2, the control element 3, part of the lead frame 4, and the plurality of wires 5A to 5L. The sealing member 6 is made of an electrically insulating resin material, such as epoxy resin. The sealing member 6 has, for example, a rectangular shape in plan view. The shape of the sealing member 6 is not limited to the example shown in FIGS. 1 to 4. As shown in FIGS. 1, 3, and 4, the sealing member 6 has a resin main surface 61, a resin back surface 62, and a plurality of resin side surfaces 631 to 634.

[0076] The resin main surface 61 and the resin back surface 62 are spaced apart in the z direction. As shown in FIG. 1, the resin main surface 61 faces the z2 direction, and as shown in FIG. 3, the resin back surface 62 faces the z1 direction. A portion of each lead 4A to 4J (a surface facing the z1 direction) is exposed from the resin back surface 62. Each of the multiple resin side surfaces 631 to 634 is sandwiched between the resin main surface 61 and the resin back surface 62 in the z direction and is connected to both. As shown in FIG. 4, the resin side surfaces 631 and 632 are spaced apart in the x direction, with the resin side surface 631 facing the x1 direction and the resin side surface 632 facing the x2 direction. As shown in FIG. 4, the resin side surfaces 633 and 634 are spaced apart in the y direction, with the resin side surface 633 facing the y1 direction and the resin side surface 634 facing the y2 direction.

[0077] Next, a power conversion device W1 including the semiconductor device A1 will be described with reference to Figures 9 to 11. In the following description, the reference potential may be referred to as the ground voltage VGND.

[0078] FIG. 9 is a circuit configuration diagram of a power conversion device W1. The power conversion device W1 shown in FIG. 9 is a synchronous rectification step-down DC / DC converter. The power conversion device W1 may have a circuit configuration that performs constant current control, constant voltage control, or constant power control. The power conversion device W1 is a power supply circuit that steps down an input voltage Vin to generate a desired output voltage Vout. The output voltage Vout is supplied to a load LO. The circuit diagram shown in FIG. 9 is an example.

[0079] As shown in Fig. 9, the power conversion device W1 includes a semiconductor device A1, two external power supplies PS1 and PS2, and a plurality of discrete components (a plurality of capacitors C11 to C14 and an inductor L1) in its circuit configuration. Also, as shown in Fig. 9, the semiconductor device A1 includes a plurality of external terminals T1 to T8, two semiconductor elements 1 and 2, and a control element 3 in its circuit configuration. Note that one or more of the plurality of discrete components may be built into the semiconductor device A1.

[0080] The external power supply PS1 generates a power supply voltage VCC for driving the control element 3. The high-potential terminal of the external power supply PS1 is connected to the external terminal T1. The low-potential terminal of the external power supply PS1 is connected to the first ground terminal GND1 and is grounded to the reference potential. A capacitor C11 is connected in parallel to the external power supply PS1. The capacitor C11 is a bypass capacitor that stabilizes the power supply voltage VCC.

[0081] The external power supply PS2 generates an input voltage Vin. The high-potential terminal of the external power supply PS2 is connected to the external terminal T3. The low-potential terminal of the external power supply PS2 is connected to the second ground terminal GND2 and is grounded to the reference potential. Note that, although the first ground terminal GND1 and the second ground terminal GND2 are both ground terminals to the same reference potential, the reference potential of the first ground terminal GND1 and the reference potential of the second ground terminal GND2 may be different. A capacitor C12 is connected in parallel to the external power supply PS2. The capacitor C12 is a bypass capacitor that stabilizes the input voltage Vin.

[0082] The inductor L1 has two terminals, one connected to the external terminal T7 and the other connected to the load LO and the capacitor C13. The capacitor C13 has a first terminal connected to the inductor L1 and a second terminal connected to the second ground terminal GND2. The inductor L1 and the capacitor C13 form an LC filter circuit. The capacitor C14 has a first terminal connected to the external terminal T7 and a second terminal connected to the external terminal T8. The capacitor C14, together with the diode D1 described below, forms a bootstrap circuit. The capacitor C14 generates a boot voltage VB.

[0083] The external terminal T1 is an input terminal for the power supply voltage VCC. The external terminal T1 is connected to a high-potential terminal of the external power supply PS1. The external terminal T1 is connected to a control element 3 (a connection terminal TC1 described later) inside the semiconductor device A1. The external terminal T1 corresponds to, for example, a lead 4F in the module structure of the semiconductor device A1.

[0084] The external terminal T2 is connected to a first ground terminal GND1 and is grounded to a reference potential. The external terminal T2 is connected to a control element 3 (a connection terminal TC2 described later) inside the semiconductor device A1. The external terminal T2 corresponds to, for example, a lead 4D in the module structure of the semiconductor device A1.

[0085] The external terminal T3 is an input terminal for the input voltage Vin. The external terminal T3 is connected to a high-potential terminal of the external power supply PS2. The external terminal T3 is connected to the drain of the semiconductor element 1 inside the semiconductor device A1. The external terminal T3 corresponds to, for example, a lead 4C in the module structure of the semiconductor device A1.

[0086] The external terminal T4 is connected to the second ground terminal GND2 and is grounded to the reference potential. The external terminal T4 is connected to the source of the semiconductor element 2 inside the semiconductor device A1. The external terminal T4 corresponds to, for example, the lead 4B in the module structure of the semiconductor device A1.

[0087] The external terminal T5 is an input terminal for a control signal SH. The control signal SH is a signal for controlling the switching operation of the semiconductor element 1. The control signal SH is, for example, a rectangular pulse wave that alternates between high and low levels. The external terminal T5 is connected to a control element 3 (a connection terminal TC3 described below) inside the semiconductor device A1. The external terminal T5 corresponds to, for example, a lead 4G in the module structure of the semiconductor device A1.

[0088] The external terminal T6 is an input terminal for a control signal SL. The control signal SL is a signal for controlling the switching operation of the semiconductor element 2. The control signal SL is, for example, a rectangular pulse wave that alternates between high and low levels. The high-level periods and low-level periods of the control signal SL and the control signal SH are inverted relative to each other. The external terminal T6 is connected to a control element 3 (connection terminal TC4 described below) inside the semiconductor device A1. The external terminal T6 corresponds to, for example, a lead 4H in the module structure of the semiconductor device A1.

[0089] The external terminal T7 is an output terminal for the output voltage VSW. The output voltage VSW is a voltage signal generated by the switching operations of the semiconductor element 1 and the semiconductor element 2. The external terminal T7 is connected to the connection point between the source of the semiconductor element 1 and the drain of the semiconductor element 2 inside the semiconductor device A1. The external terminal T7 corresponds to, for example, the lead 4A in the module structure of the semiconductor device A1.

[0090] The external terminal T8 is an input terminal for a boot voltage VB. The boot voltage VB is a voltage signal generated by a capacitor C14 and a diode D1 (described later). A second terminal of the capacitor C14 is connected to the external terminal T8. The external terminal T8 is connected to a control element 3 (a connection terminal TC7 (described later)) inside the semiconductor device A1. The external terminal T8 corresponds to, for example, a lead 4E in the module structure of the semiconductor device A1.

[0091] 9, the two semiconductor elements 1 and 2 are MOSFETs. Each of the semiconductor elements 1 and 2 switches between a conductive state (ON state) and a cut-off state (OFF state) in response to drive signals GH and GL input to its gate. The two semiconductor elements 1 and 2 form a half-bridge switching circuit, with the semiconductor element 1 being the upper arm of the switching circuit and the semiconductor element 2 being the lower arm of the switching circuit.

[0092] The drain of semiconductor element 1 is connected to external terminal T3, and the source of semiconductor element 1 is connected to the drain of semiconductor element 2. The gate of semiconductor element 1 is connected to control element 3 (connection terminal TC5 described below).

[0093] The semiconductor element 1 performs a switching operation in response to a drive signal GH (first drive signal) input to its gate from the control element 3. When the drive signal GH input to its gate is at a high level, the semiconductor element 1 is in a conductive state, and when the drive signal GH input to its gate is at a low level, the semiconductor element 1 is in a cutoff state. Note that the semiconductor element 1 is assumed to be of a normally-off type, but may also be of a normally-on type.

[0094] The drain of semiconductor element 2 is connected to the source of semiconductor element 1, and the source of semiconductor element 2 is connected to external terminal T4. The gate of semiconductor element 2 is connected to control element 3 (connection terminal TC6 described below).

[0095] The semiconductor element 2 performs a switching operation in response to a drive signal GL (second drive signal) input to its gate from the control element 3. When the drive signal GL input to its gate is at a high level, the semiconductor element 2 is in a conductive state, and when the drive signal GL input to its gate is at a low level, the semiconductor element 2 is in a cutoff state. Note that the semiconductor element 2 is assumed to be of a normally-off type, but may also be of a normally-on type.

[0096] The connection point between the source of semiconductor element 1 and the drain of semiconductor element 2 is connected to external terminal T7 and also to control element 3 (connection terminal TC8 described below). The switching operations of semiconductor element 1 and semiconductor element 2 cause an output voltage VSW to be applied to external terminal T7.

[0097] The control element 3 mainly controls the switching operations of the two semiconductor elements 1 and 2. The control element 3 generates drive signals GH and GL based on input control signals SH and SL, and inputs the generated drive signals GH and GL to the semiconductor elements 1 and 2. The control element 3 includes, in its internal circuitry, a plurality of connection terminals TC1 to TC8, two drive circuits DR1 and DR2, and a diode D1. The control element 3 is an IC in which the two drive circuits DR1 and DR2 and the diode D1 are integrated into a single chip.

[0098] The connection terminal TC1 is connected to the external terminal T1 and is an input terminal of the power supply voltage VCC in the control element 3. The connection terminal TC1 corresponds to the element electrode 31 in the module structure of the semiconductor device A1. Therefore, the power supply voltage VCC is input to the element electrode 31.

[0099] The connection terminal TC2 is connected to the external terminal T2 and is grounded to the first ground terminal GND1. The connection terminal TC2 corresponds to the element electrode 32 in the module structure of the semiconductor device A1. Therefore, the element electrode 32 is grounded to the first ground terminal GND1.

[0100] The connection terminal TC3 is connected to the external terminal T5 and is an input terminal for the control signal SH of the control element 3. The connection terminal TC3 corresponds to the element electrode 33 in the module structure of the semiconductor device A1. Therefore, the control signal SH is input to the element electrode 33.

[0101] The connection terminal TC4 is connected to the external terminal T6 and is an input terminal for the control signal SL of the control element 3. The connection terminal TC4 corresponds to the element electrode 34 in the module structure of the semiconductor device A1. Therefore, the control signal SL is input to the element electrode 34.

[0102] The connection terminal TC5 is an output terminal for the drive signal GH. The connection terminal TC5 is connected to the gate of the semiconductor element 1. The connection terminal TC5 corresponds to the element electrode 35 in the module structure of the semiconductor device A1. Therefore, the drive signal GH is output from the element electrode 35.

[0103] The connection terminal TC6 is an output terminal for the drive signal GL. The connection terminal TC6 is connected to the gate of the semiconductor element 2. The connection terminal TC6 corresponds to the element electrode 36 in the module structure of the semiconductor device A1. Therefore, the drive signal GL is output from the element electrode 36.

[0104] The connection terminal TC7 is connected to the external terminal T8, and is an input terminal for the boot voltage VB in the control element 3. The connection terminal TC7 corresponds to the element electrode 37 in the module structure of the semiconductor device A1. Therefore, the boot voltage VB is input to the element electrode 37.

[0105] The connection terminal TC8 is connected to the connection point between the semiconductor element 1 (source) and the semiconductor element 2 (drain), and is an input terminal for the output voltage VSW. The connection terminal TC8 corresponds to the element electrode 38 in the module structure of the semiconductor device A1. Therefore, the output voltage VSW is input from the element electrode 38.

[0106] The drive circuit DR1 generates a drive signal GH based on the input control signal SH. The drive signal GH is a signal for switching the semiconductor element 1, and is a signal obtained by raising the control signal SH to a level necessary for the switching operation of the semiconductor element 1. The drive circuit DR1 outputs the generated drive signal GH from the connection terminal TC5. Since the connection terminal TC5 is connected to the gate of the semiconductor element 1, the drive signal GH is input to the gate of the semiconductor element 1. The drive signal GH is a signal that sets the boot voltage VB at a high level and the source voltage of the semiconductor element 1 at a low level. The source voltage of the semiconductor element 1 is input to the drive circuit DR1 via the connection terminal TC8. The gate voltage of the semiconductor element 1 is applied based on the source voltage of the semiconductor element 1. The drive circuit DR1 may be arranged outside the control element 3.

[0107] The drive circuit DR2 generates a drive signal GL based on the input control signal SL. The drive signal GL is a signal for switching the semiconductor element 2, and is a signal obtained by raising the control signal SL to a level necessary for the switching operation of the semiconductor element 2. The drive circuit DR2 outputs the generated drive signal GL from the connection terminal TC6. Since the connection terminal TC6 is connected to the gate of the semiconductor element 2, the drive signal GL is input to the gate of the semiconductor element 2. The drive signal GL is a signal whose high level is the power supply voltage VCC and whose low level is the ground voltage VGND. The gate voltage of the semiconductor element 2 is applied based on the ground voltage VGND. The drive circuit DR2 may be arranged outside the control element 3.

[0108] The anode of the diode D1 is connected to the connection terminal TC1, and the cathode is connected to the connection terminal TC7. The diode D1 and the capacitor C14 form a bootstrap circuit. The bootstrap circuit generates a boot voltage VB and supplies it to the drive circuit DR1. The diode D1 may be disposed outside the control element 3.

[0109] Next, an example of the operation of the semiconductor device A1 will be described.

[0110] In the semiconductor device A1, when control signals SH and SL are input to the control element 3 from the external terminals T5 and T6, the control element 3 generates drive signals GH and GL. The control element 3 then inputs the drive signals GH and GL to the gates of the semiconductor elements 1 and 2. The drive signals GH and GL cause the semiconductor device A1 to alternately repeat a first period in which the semiconductor element 1 is in a conductive state and the semiconductor element 2 is in a cutoff state and a second period in which the semiconductor element 1 is in a cutoff state and the semiconductor element 2 is in a conductive state. During the first period, an input voltage Vin is applied to the external terminal T7. During the second period, the external terminal T7 is grounded to the reference potential (a ground voltage VGND is applied to the external terminal T7). Therefore, the output voltage VSW from the external terminal T7 is a pulse wave whose high level is the input voltage Vin and whose low level is the ground voltage VGND. The output voltage VSW is smoothed by the inductor L1 and the capacitor C13 and converted into a DC output voltage Vout. By operating as described above, the semiconductor device A1 transforms (steps down) the input voltage Vin to the output voltage Vout.

[0111] The first and second periods are alternately repeated at a predetermined cycle, and the step-down ratio can be changed depending on the ratio of the first and second periods in one cycle. For example, when the first period is 25% of one cycle (the second period is 75% of one cycle), the output voltage Vout is transformed to 1 / 4 of the input voltage Vin (Vout = Vin × (25 / 100)). Note that a dead time during which both semiconductor elements 1 and 2 are in a cutoff state may be provided between the first and second periods.

[0112] 10 and 11 are structural examples of the power converter W1, showing a state in which electronic components including a semiconductor device A1 are mounted on a circuit board B1. FIG. 10 is a perspective view showing the power converter W1. FIG. 11 is a plan view showing the power converter W1. In FIGS. 10 and 11, the semiconductor device A1 is shown by an imaginary line (a two-dot chain line). Note that FIGS. 10 and 11 show only a portion of the power converter W1, and do not depict all of the electronic components and wiring patterns. For example, the inductor L1 and the capacitor C13 are omitted.

[0113] The circuit board B1 is a printed circuit board such as a glass epoxy board. The circuit board B1 may be a single-sided board having one layer, a double-sided board having two layers, or a multilayer board having three or more layers. The circuit board B1 is mounted with the electronic components of the power conversion device W1. In the example shown in FIGS. 10 and 11, in addition to the semiconductor device A1, a plurality of capacitors C11, C12, and C14 are mounted on the circuit board B1. A plurality of wiring patterns 91 to 98 are formed on the circuit board B1. Each of the wiring patterns 91 to 98 is made of a metal containing copper, for example. The plurality of wiring patterns 91 to 98 are part of the wiring in the circuit diagram shown in FIG. 9. The plurality of wiring patterns 91 to 98 are spaced apart from one another.

[0114] The wiring pattern 91 is connected to the lead 4A and is electrically connected to the lead 4A. An output voltage VSW (a voltage generated by the switching operations of the semiconductor element 1 and the semiconductor element 2) is applied to the wiring pattern 91 via the lead 4A.

[0115] The wiring pattern 92 is connected to the lead 4B and is electrically connected to the lead 4B. The wiring pattern 92 is grounded to the second ground terminal GND2 (reference potential). Therefore, the lead 4B, the plurality of wires 5D, and the source electrode 22 are also grounded to the second ground terminal GND2 (reference potential).

[0116] The wiring pattern 93 is connected to the lead 4C and is electrically connected to the lead 4C. A high-potential terminal of the external power supply PS2 is connected to the wiring pattern 93, and an input voltage Vin is applied to the wiring pattern 93. The input voltage Vin applied to the wiring pattern 93 is transmitted to the lead 4C and input to the drain electrode 11 via multiple wires 5A.

[0117] The wiring pattern 94 is connected to the lead 4D and is electrically connected to the lead 4D. The wiring pattern 94 is grounded to the first ground terminal GND1 (reference potential). Therefore, the lead 4D, the wire 5H, and the element electrode 32 are also grounded to the first ground terminal GND1 (reference potential).

[0118] The wiring pattern 95 is connected to the lead 4E and is electrically connected to the lead 4E. A boot voltage VB is applied to the wiring pattern 95. The boot voltage VB input to the wiring pattern 95 is transmitted to the lead 4E and input to the element electrode 37 of the control element 3 via the wire 5I.

[0119] The wiring pattern 96 is connected to the lead 4F and is electrically connected to the lead 4F. A high-potential terminal of the external power supply PS1 is connected to the wiring pattern 96, and a power supply voltage VCC is applied to the wiring pattern 96. The power supply voltage VCC applied to the wiring pattern 96 is transmitted to the lead 4F and input to the element electrode 31 of the control element 3 via the wire 5J.

[0120] The wiring pattern 97 is connected to the lead 4G and is electrically connected to the lead 4G. A control signal SH is input to the wiring pattern 97. The control signal SH input to the wiring pattern 97 is transmitted to the lead 4G and input to the element electrode 33 of the control element 3 via the wire 5K.

[0121] The wiring pattern 98 is connected to the lead 4H and is electrically connected to the lead 4H. A control signal SL is input to the wiring pattern 98. The control signal SL input to the wiring pattern 98 is transmitted to the lead 4H and input to the element electrode 34 of the control element 3 via the wire 5L.

[0122] The wiring patterns 91 to 98 and the leads 4A to 4H are joined together by, for example, solder (not shown).

[0123] In a plan view, the capacitor C11 straddles the wiring pattern 94 and the wiring pattern 96. The capacitor C11 includes two terminals, one of which is joined to the wiring pattern 94 and the other to the wiring pattern 96. These terminals are joined by, for example, solder (not shown). The lead 4D and the lead 4F are electrically connected via the capacitor C11. As a result, the capacitor C11 is connected between the external terminal T1 and the external terminal T2 (first ground terminal GND1), as shown in the circuit diagram of FIG.

[0124] In a plan view, the capacitor C12 straddles the wiring pattern 92 and the wiring pattern 93. The capacitor C12 includes two terminals, one of which is joined to the wiring pattern 92 and the other to the wiring pattern 93. These terminals are joined by, for example, solder (not shown). The lead 4B and the lead 4C are electrically connected via the capacitor C12. As a result, the capacitor C12 is connected between the external terminal T3 and the external terminal T4 (second ground terminal GND2), as shown in the circuit diagram of FIG.

[0125] In a plan view, the capacitor C14 straddles the wiring pattern 91 and the wiring pattern 95. The capacitor C14 includes two terminals, one of which is joined to the wiring pattern 91 and the other to the wiring pattern 95. These terminals are joined by, for example, solder (not shown). The lead 4A and the lead 4E are electrically connected via the capacitor C14. As a result, the capacitor C14 is connected between the external terminal T7 and the external terminal T8, as shown in the circuit diagram of FIG. 9.

[0126] The semiconductor device A1 configured as above has the following advantages.

[0127] The semiconductor device A1 includes leads 4A, 4B, and 4C. Lead 4C is electrically connected to drain electrode 11 of semiconductor element 1, lead 4A is electrically connected to source electrode 12 of semiconductor element 1 and drain electrode 21 of semiconductor element 2, and lead 4B is electrically connected to source electrode 22 of semiconductor element 2. Leads 4A and 4B are adjacent to each other in the x-direction when viewed in the z-direction, and lead 4C is adjacent to each of leads 4A and 4B when viewed in the z-direction. This configuration allows leads 4A, 4B, and 4C to be arranged closely to each other. This shortens the wiring of the current path (power current path) that flows from lead 4C to lead 4B via drain electrode 11-source electrode 12 of semiconductor element 1, lead 4A, and drain electrode 21-source electrode 22 of semiconductor element 2. Therefore, the semiconductor device A1 can reduce parasitic inductance and parasitic resistance, thereby achieving high efficiency and energy savings.

[0128] In the semiconductor device A1, the semiconductor element 1 has a plurality of pad portions 111 (drain electrodes 11) and a plurality of pad portions 121 (source electrodes 12) extending in a first extension direction. The semiconductor element 2 has a plurality of pad portions 211 (drain electrodes 21) and a plurality of pad portions 221 (source electrodes 22) extending in a second extension direction. The second extension direction is inclined with respect to the first extension direction. The inclination angle is, for example, 10° or more and 170° or less. Assume that the first extension direction and the second extension direction are the same, and the semiconductor element 1 and the semiconductor element 2 are arranged in the same direction. In this case, if the wires 5A to 5D are wired so as to be short, the lead 4C and the lead 4B are positioned on opposite sides of the lead 4A in the extension direction. On the other hand, in the semiconductor device A1, since the lead 4B is inclined with respect to the first extension direction and the second extension direction, the lead 4B can be arranged close to the lead 4C, and therefore the wiring of the power current path can be shortened.

[0129] The semiconductor device A1 includes a lead 4A on which a semiconductor element 1 is mounted, a lead 4B on which a semiconductor element 2 is mounted, and a lead 4D on which a control element 3 is mounted. The leads 4A and 4B overlap each other when viewed in the x direction, and the lead 4D overlaps both the leads 4A and 4B when viewed in the y direction. This configuration allows the separation distance between the semiconductor element 1 and the semiconductor element 2 to be shorter than in the semiconductor device described in Patent Document 1. Specifically, in the semiconductor device described in Patent Document 1, two semiconductor elements (switching elements) are arranged on opposite sides of a control element (control IC) in a plan view. Therefore, the wiring between the two semiconductor elements needs to avoid the control element, which tends to increase the wiring distance. In contrast, the semiconductor device A1 does not have a control element 3 disposed between the semiconductor element 1 and the semiconductor element 2. This allows the wiring distance connecting the semiconductor element 1 and the semiconductor element 2 (in this embodiment, the lengths of the wires 5B and 5C and a portion of the lead 4A) to be shorter. Therefore, the semiconductor device A1 can reduce parasitic inductance and parasitic resistance, thereby achieving high efficiency and energy savings.

[0130] In the semiconductor device A1, both leads 4A and 4B are positioned further in the y2 direction than lead 4D and overlap lead 4D when viewed in the y direction. Therefore, semiconductor elements 1 and 2 can be positioned on one side in the y direction, and control element 3 can be positioned on the other side in the y direction. When power is applied to the semiconductor device A1, semiconductor elements 1 and 2 and control element 3 generate heat. The amount of heat generated by semiconductor elements 1 and 2 is greater than the amount of heat generated by control element 3. If this heat from semiconductor elements 1 and 2 is transferred to control element 3, the transferred heat may cause malfunction or performance degradation of control element 3. However, in the semiconductor device A1, by positioning leads 4A and 4B on one side in the y direction (the y2 direction side) of lead 4D, semiconductor elements 1 and 2 are separated from control element 3. This allows the semiconductor device A1 to suppress heat transfer from semiconductor elements 1 and 2 to control element 3, thereby preventing malfunction or performance degradation of control element 3.

[0131] The semiconductor device A1 includes a wire 5E, which overlaps only the leads 4A and 4D of the lead frame 4 in a plan view. With this configuration, no other leads are disposed between the semiconductor element 1 and the control element 3, making it possible to reduce the distance between the semiconductor element 1 and the control element 3. This allows the length of the wire 5E to be shortened, thereby reducing the parasitic inductance and parasitic resistance of the wire 5E. In particular, the wire 5E is a transmission line for a drive signal (drive signal GH) that controls the switching operation of the semiconductor element 1, making it possible to prevent a decrease in the responsiveness of the switching operation of the semiconductor element 1 and malfunctions of the switching operation.

[0132] The semiconductor device A1 includes a wire 5F, which overlaps only the leads 4A and 4D of the lead frame 4 in a plan view. With this configuration, no other leads are disposed between the semiconductor element 2 and the control element 3, making it possible to reduce the distance between the semiconductor element 2 and the control element 3. This allows the length of the wire 5F to be shortened, thereby reducing the parasitic inductance and parasitic resistance of the wire 5F. In particular, since the wire 5F is a transmission line for a drive signal (drive signal GL) that controls the switching operation of the semiconductor element 2, it is possible to prevent a decrease in the responsiveness of the switching operation of the semiconductor element 2 and malfunction of the switching operation.

[0133] In the first embodiment, the first ground terminal GND1 and the second ground terminal GND2 are both ground terminals connected to the same reference potential. However, the reference potential of the first ground terminal GND1 and the reference potential of the second ground terminal GND2 may be different. In the semiconductor device A1, the potential of the second ground terminal GND2 may fluctuate due to the switching operations of the semiconductor element 1 and the semiconductor element 2. If the first ground terminal GND1 and the second ground terminal GND2 are at the same potential, the potential of the first ground terminal GND1 may also fluctuate in response to fluctuations in the potential of the second ground terminal GND2. This fluctuation in the first ground terminal GND1 may cause the control element 3 to malfunction. Therefore, by making the potential of the first ground terminal GND1 different from the potential of the second ground terminal GND2, fluctuations in the potential of the first ground terminal GND1 can be suppressed even if the potential of the second ground terminal GND2 fluctuates. Therefore, in this modification, malfunction of the control element 3 can be suppressed. For example, in semiconductor device A1, lead 4D, which is grounded to the first ground terminal GND1, and lead 4B, which is grounded to the second ground terminal GND2, are spaced apart, so that it is possible to make the potentials of the first ground terminal GND1 (lead 4D) and the second ground terminal GND2 (lead 4B) different.

[0134] Next, a semiconductor device A2 according to a second embodiment will be described with reference to Fig. 12 and Fig. 13. Fig. 12 is a plan view showing a power converter W2 including the semiconductor device A2, with the sealing member 6 indicated by an imaginary line (two-dot chain line). Fig. 13 shows a circuit configuration diagram of the power converter W2.

[0135] 12 and 13, the semiconductor device A2 further includes a plurality of capacitors C21, C22, C24, C25, C26, and C27 compared to the semiconductor device A1. Moreover, the power conversion device W2 further includes a plurality of resistors R15 and R16 compared to the power conversion device W1.

[0136] The capacitor C21 includes two terminals, one of which is bonded to the lead 4D and the other to the lead 4F, as shown in FIG. 12. As a result, the leads 4D and 4F are electrically connected to each other via the wiring patterns 94, 96 and the capacitor C11, as in the first embodiment, and also via the capacitor C21. As shown in FIG. 13, the capacitor C21 is connected in parallel to the capacitor C11. The capacitor C21 is bonded, for example, with solder (not shown). The capacitor C21 is covered with a sealing member 6 and is built into the semiconductor device A2. In the example shown in FIG. 12, one capacitor C21 is provided, but multiple capacitors C21 may also be provided. In this case, each of the multiple capacitors C21 is bonded to the lead 4D and the lead 4F. The capacitance of capacitor C21 (or the combined capacitance of multiple capacitors C21 if multiple capacitors C21 are provided) is equal to or less than the capacitance of capacitor C11 (or the combined capacitance of multiple capacitors C11 if multiple capacitors C11 are provided), and the area of ​​capacitor C21 in a plan view is equal to or less than the area of ​​capacitor C11 in a plan view. Note that the configuration of capacitor C21 (capacitance, area in a plan view, etc.) is not limited to this. Capacitor C21 corresponds to a "third capacitor" in the claims.

[0137] The capacitor C22 includes two terminals, one of which is bonded to the lead 4B and the other to the lead 4C, as shown in FIG. 12. As a result, the leads 4B and 4C are electrically connected to each other via the wiring patterns 92 and 93 and the capacitor C12, as in the first embodiment, and also via the capacitor C22. As shown in FIG. 13, the capacitor C22 is connected in parallel to the capacitor C12. The capacitor C22 is bonded, for example, with solder (not shown). The capacitor C22 is covered with a sealing member 6 and is built into the semiconductor device A2. In the example shown in FIG. 12, one capacitor C22 is provided, but multiple capacitors C22 may also be provided. In this case, each of the multiple capacitors C22 is bonded to the lead 4B and the lead 4C. The capacitance of capacitor C22 (or the combined capacitance of multiple capacitors C22 if multiple capacitors C22 are provided) is equal to or less than the capacitance of capacitor C12 (or the combined capacitance of multiple capacitors C12 if multiple capacitors C12 are provided), and the area in a plan view of capacitor C22 is equal to or less than the area in a plan view of capacitor C12. Note that the configuration of capacitor C22 (capacitance, area in a plan view, etc.) is not limited to this. Capacitor C22 corresponds to the "first capacitor" recited in the claims.

[0138] The capacitor C24 includes two terminals, one of which is bonded to the lead 4A and the other to the lead 4E, as shown in FIG. 12. As a result, the lead 4A and the lead 4E are electrically connected to each other via the wiring patterns 91, 95 and the capacitor C14, as in the first embodiment, and also via the capacitor C24. The capacitor C24 is connected in parallel to the capacitor C14, as shown in FIG. 13. The capacitor C24 is bonded, for example, with solder (not shown). The capacitor C24 is covered with a sealing member 6 and is built into the semiconductor device A2. In the example shown in FIG. 12, one capacitor C24 is provided, but multiple capacitors C24 may also be provided. In this case, each of the multiple capacitors C24 is bonded to the lead 4A and the lead 4E. The capacitance of capacitor C24 (or the combined capacitance of multiple capacitors C24 if multiple capacitors C24 are provided) is equal to or less than the capacitance of capacitor C14 (or the combined capacitance of multiple capacitors C14 if multiple capacitors C14 are provided), and the area of ​​capacitor C24 in a plan view is equal to or less than the area of ​​capacitor C14 in a plan view. Note that the configuration of capacitor C24 (capacitance, area in a plan view, etc.) is not limited to this. Capacitor C24 corresponds to a "second capacitor" in the claims.

[0139] The capacitor C25 includes two terminals, one of which is bonded to the lead 4D and the other to the lead 4G, as shown in FIG. 12. This establishes electrical continuity between the lead 4D and the lead 4G via the capacitor C25. The capacitor C25 is bonded, for example, with solder (not shown). The capacitor C25 is covered with a sealing member 6 and is built into the semiconductor device A2. In the example shown in FIG. 12, one capacitor C25 is provided, but multiple capacitors C25 may also be provided. In this case, each of the multiple capacitors C25 is bonded to the lead 4D and the lead 4G. The capacitor C25 corresponds to a "fourth capacitor" in the claims.

[0140] The capacitor C26 includes two terminals, one of which is bonded to the lead 4D and the other to the lead 4H, as shown in FIG. 12. This establishes electrical continuity between the lead 4D and the lead 4H via the capacitor C26. The capacitor C26 is bonded, for example, with solder (not shown). The capacitor C26 is covered with a sealing member 6 and is built into the semiconductor device A2. In the example shown in FIG. 12, one capacitor C26 is provided, but multiple capacitors C26 may also be provided. In this case, each of the multiple capacitors C26 is bonded to the lead 4D and the lead 4H. The capacitor C26 corresponds to a "fifth capacitor" in the claims.

[0141] The capacitor C27 includes two terminals, one of which is bonded to the lead 4B and the other to the lead 4D, as shown in FIG. 12. This establishes electrical continuity between the lead 4B and the lead 4D via the capacitor C27. The capacitor C27 is bonded, for example, with solder (not shown). The capacitor C27 is covered with a sealing member 6 and is built into the semiconductor device A2. In the example shown in FIG. 12, one capacitor C27 is provided, but multiple capacitors C27 may also be provided. In this case, each of the multiple capacitors C27 is bonded to the lead 4B and the lead 4D. The capacitor C27 corresponds to a "sixth capacitor" in the claims.

[0142] The resistor R15 has two terminals, one of which is connected to the wiring pattern 97 and the other to a wiring pattern 971 spaced apart from the wiring patterns 91 to 98, as shown in FIG. 12. This establishes electrical continuity between the wiring pattern 97 and the wiring pattern 971 via the resistor R15. The resistor R15 is connected by solder (not shown), for example. As shown in FIG. 13, the resistor R15 and the capacitor C25 form an RC filter. The RC filter suppresses noise contained in the control signal SH input from the outside. An LC filter may be formed using an inductor instead of the resistor R15.

[0143] The resistor R16 has two terminals, one of which is connected to the wiring pattern 98 and the other to a wiring pattern 981 spaced apart from the wiring patterns 91 to 98, as shown in FIG. 12. This establishes electrical continuity between the wiring pattern 98 and the wiring pattern 981 via the resistor R16. The resistor R16 is connected by solder (not shown), for example. As shown in FIG. 13, the resistor R16 and the capacitor C26 form an RC filter. The RC filter suppresses noise contained in the control signal SL input from the outside. An LC filter may be formed using an inductor instead of the resistor R16.

[0144] The semiconductor device A2 configured as above has the following advantages.

[0145] In the semiconductor device A2, similar to the semiconductor device A1, the leads 4A and 4B are adjacent to each other in the x direction when viewed in the z direction, and the lead 4C is adjacent to each of the leads 4A and 4B when viewed in the z direction. This allows the semiconductor device A2, similar to the semiconductor device A1, to shorten the wiring of the power current path. Therefore, the semiconductor device A2 can reduce parasitic inductance and parasitic resistance, thereby achieving high efficiency and energy savings.

[0146] The semiconductor device A2 includes a capacitor C21. In the semiconductor device A1, the leads 4D and 4F are electrically connected via the circuit board B1 (wiring patterns 94, 96 and capacitor C11), but in the semiconductor device A2, the leads 4D and 4F are also electrically connected via the capacitor C21. With this configuration, the current path between the gate and source of the semiconductor element 2 (between the gate electrode 23 and the source electrode 22) is smaller than that of the power conversion device W1. Therefore, the semiconductor device A2 can suppress surge voltages applied to the semiconductor element 2, thereby reducing problems caused by the surge voltages.

[0147] The semiconductor device A2 includes a capacitor C22. In the semiconductor device A1, the leads 4B and 4C are electrically connected via the circuit board B1 (wiring patterns 92, 93 and capacitor C12), but in the semiconductor device A2, the leads 4B and 4C are also electrically connected via the capacitor C22. With this configuration, the power current path is smaller than that of the power converter W1. Therefore, the semiconductor device A2 can reduce the parasitic inductance and parasitic resistance in the power current path more than the semiconductor device A1, and can suppress the occurrence of surge voltages.

[0148] The semiconductor device A2 includes a capacitor C24. In the semiconductor device A1, the lead 4A and the lead 4E are electrically connected via the circuit board B1 (wiring patterns 91, 95 and capacitor C14), but in the semiconductor device A2, the lead 4A and the lead 4E are also electrically connected via the capacitor C24. With this configuration, the current path between the gate and source of the semiconductor element 1 (between the gate electrode 13 and the source electrode 12) is smaller than that of the power conversion device W2. Therefore, the semiconductor device A2 can suppress the surge voltage applied to the semiconductor element 1, thereby suppressing problems caused by the surge voltage.

[0149] The semiconductor device A2 includes a capacitor C25, and the circuit board B1 includes a resistor R15. With this configuration, the capacitor C25 and the resistor R15 form an RC filter in the power conversion device W2. As described above, the RC filter can reduce noise contained in the drive signal GH input to the semiconductor element 1. Therefore, the semiconductor device A2 can make the switching operation of the semiconductor element 1 more stable than the semiconductor device A1.

[0150] The semiconductor device A2 includes a capacitor C26, and the circuit board B1 includes a resistor R16. With this configuration, the capacitor C26 and the resistor R16 form an RC filter in the power conversion device W2. As described above, the RC filter can reduce noise contained in the drive signal GL input to the semiconductor element 1. Therefore, the semiconductor device A2 can make the switching operation of the semiconductor element 2 more stable than the semiconductor device A1.

[0151] The semiconductor device A2 includes a capacitor C27. Without the capacitor C27, connecting the leads 4B and 4D would require wiring via the circuit board B1. This would require wiring that avoids other wiring patterns, which would tend to result in long wiring. However, in the semiconductor device A2, the capacitor C27 connects the leads 4B and 4D, making it possible to shorten the current path between the leads 4B and 4D. Therefore, the semiconductor device A2 can shorten the current path between the leads 4B and 4D, thereby preventing erroneous turn-on of the semiconductor elements 1 and 2.

[0152] In addition, the semiconductor device A2 has the same effects as the semiconductor device A1 due to the parts configured in the same manner as the semiconductor device A1.

[0153] In the second embodiment, the semiconductor device A2 includes all of the capacitors C21, C22, C24, C25, C26, and C27, but it is not necessary for the semiconductor device A2 to include all of these. In other words, the semiconductor device A2 may be configured to include at least one of the capacitors C21, C22, C24, C25, C26, and C27.

[0154] In the second embodiment, the power conversion device W2 includes the capacitor C11. However, if the capacitance of the capacitor C21 of the semiconductor device A2 (if multiple capacitors C21 are included, their combined capacitance) is appropriately large, the capacitor C11 does not need to be mounted on the circuit board B1. Similarly, if the capacitance of the capacitor C22 of the semiconductor device A2 (if multiple capacitors C22 are included, their combined capacitance) is appropriately large, the capacitor C12 does not need to be mounted on the circuit board B1. Furthermore, if the capacitance of the capacitor C24 of the semiconductor device A2 (if multiple capacitors C24 are included, their combined capacitance) is appropriately large, the capacitor C14 does not need to be mounted on the circuit board B1.

[0155] Next, a semiconductor device A3 according to a third embodiment will be described with reference to Fig. 14. Fig. 14 is a plan view showing a power converter W3 including the semiconductor device A3, with the sealing member 6 indicated by an imaginary line (two-dot chain line). Note that in the semiconductor device A3 shown in Fig. 14, the number and diameter of the multiple wires 5A, 5B, 5C, and 5D are different from those of the semiconductor device A1, but these may be configured similarly to the semiconductor device A1.

[0156] The semiconductor element 1 of the semiconductor device A3 has higher performance (e.g., lower on-resistance) than the semiconductor element 2 of the semiconductor device A3, and also has higher performance (e.g., lower on-resistance) than the semiconductor element 1 of the semiconductor device A1. Also, as shown in Fig. 14, the planar area of ​​the semiconductor element 1 of the semiconductor device A3 is larger than the planar area of ​​the semiconductor element 2 of the semiconductor device A3, and is also larger than the planar area of ​​the semiconductor element 1 of the semiconductor device A1. The semiconductor element 2 of the semiconductor device A3 is the same as the semiconductor element 2 of the semiconductor device A1.

[0157] 14, the semiconductor element 1 of the semiconductor device A3 is different from the semiconductor element 1 of the semiconductor device A1 in the configuration of each electrode (drain electrode 11 and source electrode 12) of the semiconductor element 1. Specifically, the planar shapes of each pad portion 111, 121 are different.

[0158] As shown in FIG. 14, each pad portion 111 of the semiconductor device A3 is tapered. Specifically, the dimension of each pad portion 111 in the x direction decreases from the edge on the y2 direction side toward the edge on the y1 direction side in the y direction. Each pad portion 111 is approximately triangular in plan view. Like each pad portion 111, each pad portion 121 is also tapered. Specifically, the dimension of each pad portion 121 in the x direction decreases from the edge on the y1 direction side toward the edge on the y2 direction side in the y direction. Each pad portion 121 is approximately triangular in plan view. Note that in the semiconductor device A3 as well, the multiple pad portions 111, 121 each extend in the first extension direction (the y direction in FIG. 14) and are alternately arranged in the first arrangement direction (the x direction in FIG. 14).

[0159] The semiconductor device A3 configured as above has the following advantages.

[0160] In the semiconductor device A3, similar to the semiconductor device A1, the leads 4A and 4B are adjacent to each other in the x direction when viewed in the z direction, and the lead 4C is adjacent to each of the leads 4A and 4B when viewed in the z direction. This allows the semiconductor device A3 to shorten the wiring of the power current path, similar to the semiconductor device A1. Therefore, the semiconductor device A3 can reduce parasitic inductance and parasitic resistance, thereby achieving high efficiency and energy savings.

[0161] In the semiconductor device A3, the on-resistance of the semiconductor element 1 is smaller than the on-resistance of the semiconductor element 2, and is also smaller than the on-resistance of the semiconductor element 1 of the semiconductor device A1. With this configuration, the conduction loss in the semiconductor element 1 is smaller than the conduction loss in the semiconductor element 2, and is also smaller than the conduction loss in the semiconductor element 1 of the semiconductor device A1. Therefore, the semiconductor device A3 can reduce the conduction loss in the semiconductor element 1 more than the semiconductor device A1. In particular, the semiconductor device A3 is effective in reducing the conduction loss when used in a boost circuit.

[0162] In the semiconductor device A3, the area of ​​the semiconductor element 1 in a plan view is larger than the area of ​​the semiconductor element 1 in the semiconductor device A1. With this configuration, the area of ​​the element main surface 1a of the semiconductor element 1 in the semiconductor device A3 is larger than that in the semiconductor device A1, and therefore heat dissipation from the element main surface 1a can be improved. In other words, the thermal resistance of the semiconductor element 1 in the semiconductor device A3 can be reduced more than that in the semiconductor device A1.

[0163] In addition, the semiconductor device A3 has the same components as the semiconductor device A1, and thus achieves the same effects as the semiconductor device A1. In addition, the semiconductor device A3 can achieve the same effects as the semiconductor device A2 by adding multiple capacitors C21, C22, C24, C25, C26, and C27, as in the semiconductor device A2.

[0164] 15 shows a modified example of the semiconductor device A3 according to the third embodiment. In the semiconductor device A31 according to this modified example, the planar area of ​​the lead 4A is larger than that of the semiconductor device A3. Specifically, the lead 4A of the semiconductor device A31 (see FIG. 15) has, for example, an extension region ER1 (shown by dots in FIG. 15 for ease of understanding) added to it compared to the lead 4A of the semiconductor device A3 (see FIG. 14). In addition, with the addition of the extension region ER1, the lead 4B is also expanded in planar view.

[0165] According to the semiconductor device A31, the area of ​​the leads 4A in a plan view is larger than the area of ​​the leads 4A in a plan view of the semiconductor device A3. This improves the efficiency of heat conduction from the leads 4A to the wiring pattern 91 of the circuit board B1. That is, in the semiconductor device A31, heat from the semiconductor element 1 can be dissipated from both the element main surface 1a and the element back surface 1b. In particular, by making the area of ​​the leads 4A in a plan view 1.1 to 5 times the area of ​​the semiconductor element 1 in a plan view, the efficiency of heat conduction from the leads 4A to the wiring pattern 91 can be improved while preventing the semiconductor device A31 from becoming too large.

[0166] 15, in a plan view, the distance between the center of the semiconductor element 1 and the center of the control element 3 is smaller than the distance between the center of the lead 4A and the center of the control element 3. For ease of understanding, in FIG. 16, an x ​​(cross mark) is marked at the center of the semiconductor element 1 in a plan view, the center of the lead 4A in a plan view, and the center of the control element 3 in a plan view. In other words, in a plan view, the semiconductor element 1 is disposed close to the control element 3. With this configuration, the length of the wire 5E can be shortened, thereby reducing the parasitic inductance and parasitic resistance of the wire 5E.

[0167] Next, a semiconductor device A4 according to a fourth embodiment will be described with reference to Fig. 16. Fig. 16 is a plan view showing a power converter W4 including the semiconductor device A4, with the sealing member 6 indicated by an imaginary line (two-dot chain line). Note that in the semiconductor device A4 shown in Fig. 16, the number and diameter of the multiple wires 5A, 5B, 5C, and 5D differ from those of the semiconductor device A1, but these may be configured similarly to the semiconductor device A1.

[0168] The semiconductor element 2 of the semiconductor device A4 has higher performance (for example, lower on-resistance) than the semiconductor element 1 of the semiconductor device A4, and also has higher performance (for example, lower on-resistance) than the semiconductor element 2 of the semiconductor device A1. Also, as shown in Figure 16, the planar area of ​​the semiconductor element 2 of the semiconductor device A4 is larger than the planar area of ​​the semiconductor element 1 of the semiconductor device A4, and is also larger than the planar area of ​​the semiconductor element 2 of the semiconductor device A1. The semiconductor element 1 of the semiconductor device A4 is the same as the semiconductor element 1 of the semiconductor device A1.

[0169] 16, the semiconductor element 2 of the semiconductor device A4 is different from the semiconductor element 2 of the semiconductor device A1 in the configuration of each electrode (drain electrode 21 and source electrode 22) of the semiconductor element 2. Specifically, the planar shapes of each pad portion 211, 221 are different.

[0170] As shown in FIG. 16, each pad portion 211 of the semiconductor device A4 is tapered. Specifically, the dimension of each pad portion 211 in the y direction decreases from the edge on the x2 direction side toward the edge on the x1 direction side in the x direction. Each pad portion 211 is approximately triangular in plan view. Like each pad portion 211, each pad portion 221 is also tapered. Specifically, the dimension of each pad portion 221 in the y direction decreases from the edge on the x1 direction side toward the edge on the x2 direction side in the x direction. Each pad portion 221 is approximately triangular in plan view. Note that in the semiconductor device A4 as well, the multiple pad portions 211, 221 each extend in the second extension direction (the x direction in FIG. 16) and are alternately arranged in the second arrangement direction (the y direction in FIG. 16).

[0171] In the semiconductor device A4, the configuration (arrangement, planar size, shape, etc.) of each lead 4A to 4H of the lead frame 4 has been modified as appropriate. For example, the planar area of ​​the semiconductor element 2 has increased, so the size of the lead 4B on which the semiconductor element 2 is mounted has also increased. As shown in Fig. 16, the lead 4B of the semiconductor device A4 is connected from the edge on the y2 direction side to the edge on the y1 direction side of the lead frame 4, and overlaps all of the other leads 4A, 4C to 4H when viewed in the x direction.

[0172] The semiconductor device A4 configured as above has the following advantages.

[0173] In the semiconductor device A4, similar to the semiconductor device A1, the leads 4A and 4B are adjacent to each other in the x direction when viewed in the z direction, and the lead 4C is adjacent to each of the leads 4A and 4B when viewed in the z direction. This allows the semiconductor device A4 to shorten the wiring of the power current path, similar to the semiconductor device A1. Therefore, the semiconductor device A4 can reduce parasitic inductance and parasitic resistance, thereby achieving high efficiency and energy savings.

[0174] In the semiconductor device A4, the on-resistance of the semiconductor element 2 is smaller than the on-resistance of the semiconductor element 1, and is also smaller than the on-resistance of the semiconductor element 2 of the semiconductor device A1. With this configuration, the conduction loss in the semiconductor element 2 is smaller than the conduction loss in the semiconductor element 1, and is also smaller than the conduction loss in the semiconductor element 2 of the semiconductor device A1. Therefore, the semiconductor device A4 can reduce the conduction loss in the semiconductor element 2 more than the semiconductor device A1. In particular, the semiconductor device A4 is effective in reducing the conduction loss when used in a step-down circuit.

[0175] In the semiconductor device A4, the area of ​​the semiconductor element 2 in a plan view is larger than the area of ​​the semiconductor element 2 in the semiconductor device A1. With this configuration, the area of ​​the element main surface 2a of the semiconductor element 2 in the semiconductor device A4 is larger than that in the semiconductor device A1, and therefore heat dissipation from the element main surface 2a can be improved. In other words, the thermal resistance of the semiconductor element 1 in the semiconductor device A4 can be reduced more than that in the semiconductor device A1.

[0176] In addition, the semiconductor device A4 has the same effects as the semiconductor device A4 due to the parts configured similarly to the semiconductor device A1. Note that, like the semiconductor device A2, the semiconductor device A4 can achieve the same effects as the semiconductor device A2 by adding multiple capacitors C21, C22, C24, C25, C26, and C27.

[0177] 17 shows a modified example of the semiconductor device A4 according to the fourth embodiment. In the semiconductor device A41 according to this modification, the planar area of ​​the lead 4B is larger than that of the semiconductor device A4. Specifically, the lead 4B of the semiconductor device A41 (see FIG. 17) has, for example, an extension region ER2 (shown by a dot in FIG. 17 for ease of understanding) added to the lead 4B of the semiconductor device A4 (see FIG. 16).

[0178] According to the semiconductor device A41, the area of ​​the leads 4B in a plan view is larger than the area of ​​the leads 4B in a plan view of the semiconductor device A4. This improves the efficiency of heat conduction from the leads 4B to the wiring pattern 92 of the circuit board B1. That is, in the semiconductor device A41, heat from the semiconductor element 2 can be dissipated from both the element main surface 2a and the element back surface 2b. In particular, by making the area of ​​the leads 4B in a plan view 1.1 to 5 times the area of ​​the semiconductor element 2 in a plan view, the efficiency of heat conduction from the leads 4B to the wiring pattern 92 can be improved while preventing the semiconductor device A41 from becoming too large.

[0179] 17, in a plan view, the distance between the center of the semiconductor element 2 and the center of the control element 3 is smaller than the distance between the center of the lead 4B and the center of the control element 3. For ease of understanding, in FIG. 17, an x ​​(cross mark) is marked at the center of the semiconductor element 2 in a plan view, the center of the lead 4B in a plan view, and the center of the control element 3 in a plan view. In other words, in a plan view, the semiconductor element 2 is disposed close to the control element 3. With this configuration, the length of the wire 5F can be shortened, thereby reducing the parasitic inductance and parasitic resistance of the wire 5F.

[0180] Next, a semiconductor device A5 according to a fifth embodiment will be described with reference to Fig. 18. Fig. 18 is a plan view showing a power converter W5 including the semiconductor device A5, in which a sealing member 6 is indicated by an imaginary line (a two-dot chain line).

[0181] As shown in Fig. 18, the semiconductor device A5 is equipped with the semiconductor element 1 (see Fig. 14) of the semiconductor device A3 and the semiconductor element 2 (see Fig. 16) of the semiconductor device A4. That is, the semiconductor elements 1 and 2 of the semiconductor device A5 have higher performance (for example, lower on-resistance) and larger planar area than the semiconductor elements 1 and 2 of the semiconductor device A1. In the semiconductor device A5, the configuration (arrangement, planar size and shape, etc.) of the leads 4A to 4H of the lead frame 4 is appropriately modified.

[0182] In the semiconductor device A5, similar to the semiconductor device A1, the leads 4A and 4B are adjacent to each other in the x-direction when viewed in the z-direction, and the lead 4C is adjacent to each of the leads 4A and 4B when viewed in the z-direction. This allows the semiconductor device A5, similar to the semiconductor device A1, to shorten the wiring of the power current path. Therefore, the semiconductor device A5 can reduce parasitic inductance and parasitic resistance, thereby achieving high efficiency and energy savings.

[0183] The semiconductor device A5 is equipped with semiconductor elements 1 and 2 that have higher performance (lower on-resistance) than the semiconductor device A1. As a result, the semiconductor device A5 can reduce the conduction loss in each of the semiconductor elements 1 and 2 compared to the semiconductor device A1.

[0184] Next, a semiconductor device A6 according to a sixth embodiment will be described with reference to Fig. 19 and Fig. 20. Fig. 19 is a plan view showing a power converter W6 including the semiconductor device A6, with the sealing member 6 indicated by an imaginary line (two-dot chain line). Fig. 20 is a cross-sectional view taken along line XX-XX in Fig. 19.

[0185] As shown in FIG. 19, the semiconductor device A6 differs from the semiconductor device A1 in that clips 7A, 7B, 7C, and 7D are used instead of the plurality of wires 5A, 5B, 5C, and 5D.

[0186] As shown in Fig. 20, each of the clips 7A to 7D is formed by bending a plate-shaped metal member. The clips 7A to 7D are made of a material such as a metal containing Cu or a metal containing Al. Alternatively, they may be made of a clad material such as CIC (Copper-Invar-Copper). In the example shown in Fig. 20, each of the clips 7A to 7D is bent perpendicular to the upper surface of the lead frame 4, but they may also be inclined in the z direction.

[0187] The clip 7A has a comb-like shape on one side in the y direction (the y1 direction side in FIG. 19), and the comb-like portions are respectively joined to the plurality of pad portions 111. The clip 7B has a comb-like shape on one side in the y direction (the y2 direction side in FIG. 19), and the comb-like portions are respectively joined to the plurality of pad portions 121. The clip 7C has a comb-like shape on one side in the x direction (the x2 direction side in FIG. 19), and the comb-like portions are respectively joined to the plurality of pad portions 211. The clip 7D has a comb-like shape on one side in the x direction (the x1 direction side in FIG. 19), and the comb-like portions are respectively joined to the plurality of pad portions 221. The shapes of the clips 7A to 7D are not limited to the examples shown in FIGS. 19 and 20.

[0188] In the semiconductor device A6, similarly to the semiconductor device A1, the leads 4A and 4B are adjacent to each other in the x-direction when viewed in the z-direction, and the lead 4C is adjacent to each of the leads 4A and 4B when viewed in the z-direction. This allows the semiconductor device A6, similarly to the semiconductor device A1, to shorten the wiring of the power current path. Therefore, the semiconductor device A6 can reduce parasitic inductance and parasitic resistance, thereby achieving high efficiency and energy savings.

[0189] The semiconductor device A6 includes a clip 7A instead of the wire 5A. The clip 7A can reduce wiring resistance more than the wire 5A. In particular, since the clip 7A is part of the power current path described above, the semiconductor device A6 can reduce power loss in power conversion more than the semiconductor device A1. Similarly, the semiconductor device A6 includes clips 7B, 7C, and 7D instead of the wires 5B, 5C, and 5D. Each of the clips 7B, 7C, and 7D can reduce wiring resistance more than each of the wires 5B, 5C, and 5D. In particular, since each of the clips 7B, 7C, and 7D is part of the power current path described above, the semiconductor device A6 can reduce power loss in power conversion more than the semiconductor device A1.

[0190] In the sixth embodiment, each of the clips 7A to 7D has a partially bent structure, but this is not limiting. For example, each of the clips 7A to 7D may have a structure in which the thickness (dimension in the z direction) of a portion thereof is changed. In this case, each of the clips 7A to 7D has a thin portion bonded to the semiconductor element 1 or semiconductor element 2 and a thick portion bonded to one of the leads 4A, 4B, and 4C.

[0191] In the sixth embodiment, the clip 7A has a comb-like portion, and this comb-like portion is joined to a plurality of pad portions 111 (drain electrodes 11), but this is not limiting. For example, a plurality of strip-shaped clips 7A may be provided, and one clip 7A may be joined to each of the plurality of pad portions 111. The same applies to the other clips 7B to 7D.

[0192] Next, a semiconductor device A7 according to a seventh embodiment will be described with reference to Fig. 21. Fig. 21 is a plan view showing a power converter W7 including the semiconductor device A7, in which the sealing member 6 is indicated by an imaginary line (two-dot chain line).

[0193] 21, unlike the semiconductor device A1, the semiconductor device A7 has the semiconductor elements 1 and 2 flip-chip mounted. That is, the semiconductor element 1 is mounted with its element main surface 1a facing the lead frame 4, and the semiconductor element 2 is mounted with its element main surface 2a facing the lead frame 4.

[0194] The lead frame 4 of the semiconductor device A7 has leads 4A to 4C with different shapes and further includes leads 4I and 4J in order to flip-chip mount the semiconductor elements 1 and 2. As shown in Fig. 21, each of the leads 4A to 4C has a comb-like portion (hereinafter referred to as a "comb-tooth portion"). Note that the lead 4A has two comb-tooth portions.

[0195] As shown in FIG. 21 , the drain electrode 11 (plurality of pad portions 111) of the semiconductor element 1 is conductively joined to the comb-tooth portion of the lead 4C. The source electrode 12 (plurality of pad portions 121) of the semiconductor element 1 is conductively joined to one of the comb-tooth portions of the lead 4A. The gate electrode 13 (one of two pad portions 131, 132) of the semiconductor element 1 is conductively joined to the lead 4I. The drain electrode 21 (plurality of pad portions 211) of the semiconductor element 2 is conductively joined to the other comb-tooth portion of the lead 4A. The source electrode 22 (plurality of pad portions 221) of the semiconductor element 2 is conductively joined to the comb-tooth portion of the lead 4B. The gate electrode 23 (one of two pad portions 231, 232) of the semiconductor element 2 is conductively joined to the lead 4J.

[0196] 21, the wire 5E is bonded to the lead 4I. The gate electrode 13 of the semiconductor element 1 and the element electrode 35 are electrically connected via the lead 4I and the wire 5E. The wire 5F is bonded to the lead 4J. The gate electrode 23 of the semiconductor element 2 and the element electrode 36 of the control element 3 are electrically connected via the lead 4J and the wire 5F.

[0197] In the semiconductor device A7, the leads 4A and 4B are adjacent to each other in the x direction when viewed in the z direction, and the lead 4C is adjacent to each of the leads 4A and 4B when viewed in the z direction. This allows the semiconductor device A7 to shorten the wiring of the power current path, just like the semiconductor device A1. Therefore, the semiconductor device A7 can reduce parasitic inductance and parasitic resistance, thereby achieving high efficiency and energy savings.

[0198] Next, a semiconductor device A8 according to an eighth embodiment will be described with reference to Fig. 22 and Fig. 23. Fig. 22 is a plan view showing the semiconductor device A8, with the sealing member 6 indicated by an imaginary line (two-dot chain line). Fig. 23 is a cross-sectional view taken along line XXIII-XXIII in Fig. 22.

[0199] As shown in FIGS. 22 and 23, the semiconductor device A8 differs from the semiconductor device A1 in that it includes a conductive substrate 8 instead of the lead frame 4.

[0200] The conductive substrate 8 includes a base material 81 and a plurality of wiring portions 82A to 82H.

[0201] The substrate 81 is made of an insulating material. The constituent material of the substrate 81 is, for example, ceramics with excellent thermal conductivity. Examples of such ceramics include AlN (aluminum nitride), SiN (silicon nitride), and Al2O3 (aluminum oxide). The substrate 81 is, for example, in the form of a flat plate. Note that the constituent material of the substrate 81 is not limited to ceramics, and may be various resin materials used in printed circuit boards, silicon, or the like.

[0202] The wiring portions 82A to 82H are formed on a substrate 81. Each of the wiring portions 82A to 82H is made of a conductive material. The constituent material of each of the wiring portions 82A to 82H is a metal containing copper, for example. The constituent material may be aluminum instead of copper. The multiple wiring portions 82A to 82H are arranged spaced apart from one another.

[0203] The wiring portion 82A corresponds to the lead 4A. The wiring portion 82B corresponds to the lead 4B. The wiring portion 82C corresponds to the lead 4C. The wiring portion 82D corresponds to the lead 4D. The wiring portion 82E corresponds to the lead 4E. The wiring portion 82F corresponds to the lead 4F. The wiring portion 82G corresponds to the lead 4G. The wiring portion 82H corresponds to the lead 4H. The wiring portions 82A to 82H shown in FIG. 22 are arranged in the same manner as the leads 4A to 4H of the semiconductor device A1, and their positional relationships are also the same.

[0204] In this embodiment, the conductive substrate 8 corresponds to the "conductive member" recited in the claims. The wiring portion 82A corresponds to the "first conductor" recited in the claims. The wiring portion 82B corresponds to the "second conductor" recited in the claims. The wiring portion 82C corresponds to the "third conductor" recited in the claims. The wiring portion 82D corresponds to the "fourth conductor" recited in the claims. The wiring portion 82E corresponds to the "fifth conductor" recited in the claims. The wiring portion 82F corresponds to the "sixth conductor" recited in the claims. The wiring portion 82G corresponds to the "seventh conductor" recited in the claims. The wiring portion 82H corresponds to the "eighth conductor" recited in the claims.

[0205] The semiconductor device A8 includes wiring portions 82A, 82B, and 82C arranged in the same manner as the leads 4A, 4B, and 4C in the semiconductor device A1. With this configuration, the semiconductor device A8, like the semiconductor device A1, has the wiring portions 82A and 82B adjacent to each other in the x-direction when viewed in the z-direction, and the wiring portion 82C adjacent to each of the wiring portions 82A and 82B when viewed in the z-direction. This allows the semiconductor device A8, like the semiconductor device A1, to shorten the wiring of the power current path. Therefore, the semiconductor device A8 can reduce parasitic inductance and parasitic resistance, thereby achieving high efficiency and energy savings.

[0206] In the first to eighth embodiments, the semiconductor devices A1 to A8 are shown to be in a SON package, but they may be configured in other package formats. For example, they may be configured in a BGA (Ball Grid Array) package, an LGA (Land Grid Array) package, a QFP (Quad Flat Package) package, a QFN (Quad Flat Non-lead) package, or other package formats. These package formats are merely examples and are not limiting.

[0207] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0208] The semiconductor device according to the present disclosure includes embodiments relating to the following supplementary notes. [Appendix 1] a conductive member including a first conductor, a second conductor, and a third conductor spaced apart from one another; a first semiconductor element having a first main surface on which a first drain electrode, a first source electrode, and a first gate electrode are disposed; a second semiconductor element having a second main surface on which a second drain electrode, a second source electrode, and a second gate electrode are disposed; It is equipped with the first conductor is electrically connected to the first source electrode and the second drain electrode; the second conductor is electrically connected to the second source electrode, and when viewed in a first direction perpendicular to the first main surface, the second conductor is adjacent to the second source electrode in a second direction perpendicular to the first direction; the third conductor is electrically connected to the first drain electrode and is adjacent to each of the first conductor and the second conductor when viewed in the first direction; A semiconductor device characterized by: [Appendix 2] a first connection member that electrically connects the third conductor and the first drain electrode; a second connection member that electrically connects the first source electrode and the first conductor; a third connection member that electrically connects the first conductor and the second drain electrode; a fourth connection member that electrically connects the second source electrode and the second conductor; It also has the first semiconductor element is mounted on the first conductor, and the first main surface faces a side opposite to a direction facing the first conductor in the first direction; the first semiconductor element is mounted on the second conductor, and the second main surface faces in the first direction opposite to the direction facing the second conductor; 2. The semiconductor device according to claim 1. [Appendix 3] The semiconductor device described in Appendix 2, wherein the first conductor and the third conductor are adjacent to each other in a third direction perpendicular to both the first direction and the second direction when viewed in the first direction. [Appendix 4] the first connection member overlaps a first insulating region that insulates the first conductor from the third conductor when viewed in the first direction; 4. The semiconductor device according to claim 3. [Appendix 5] the third connection member overlaps a second insulating region that insulates the first conductor from the second conductor when viewed in the first direction; 5. The semiconductor device according to claim 3 or 4. [Appendix 6] the first conductor and the second conductor overlap when viewed in the second direction, the first conductor and the third conductor overlap when viewed in the third direction; The semiconductor device according to any one of Supplementary Note 3 to Supplementary Note 5. [Appendix 7] the second conductor and the third conductor overlap when viewed in the second direction; 7. The semiconductor device according to claim 6. [Appendix 8] a control element including a first element electrode and a second element electrode; a fifth connection member that electrically connects the first gate electrode and the first element electrode; a sixth connection member that electrically connects the second gate electrode and the second element electrode; It also has the control element outputs a first drive signal from the first element electrode to control a switching operation of the first semiconductor element, and outputs a second drive signal from the second element electrode to control a switching operation of the second semiconductor element; 8. The semiconductor device according to claim 3, wherein the semiconductor device is a semiconductor device having a first insulating layer. [Appendix 9] the conductive member further includes a fourth conductor spaced apart from the first conductor, the second conductor, and the third conductor and carrying the control element; the fourth conductor overlaps the first conductor and the third conductor when viewed in the third direction, and is located on the opposite side of the third conductor with the first conductor in between in the third direction. 9. The semiconductor device according to claim 8. [Appendix 10] the fifth connection member overlaps only the first conductor and the fourth conductor of the conductive member when viewed in the first direction; 10. The semiconductor device according to claim 9. [Appendix 11] the sixth connection member overlaps only the second conductor and the fourth conductor of the conductive member when viewed in the first direction; 11. The semiconductor device according to claim 9 or 10. [Appendix 12] a first capacitor having two terminals; the first capacitor has one terminal connected to the second conductor and the other terminal connected to the third conductor; 12. The semiconductor device according to claim 9, wherein the semiconductor device is a semiconductor device having a first insulating layer. [Appendix 13] a second capacitor having two terminals; the conductive member further includes a fifth conductor spaced apart from the first conductor, the second conductor, the third conductor, and the fourth conductor and conducting to the control element; the second capacitor has one terminal connected to the first conductor and the other terminal connected to the fifth conductor; 13. The semiconductor device according to claim 9, wherein the semiconductor device is a semiconductor device having a first insulating layer. [Appendix 14] a third capacitor having two terminals; the conductive member further includes a sixth conductor spaced apart from the first conductor, the second conductor, the third conductor, and the fourth conductor and conducting to the control element; the third capacitor has one terminal connected to the fourth conductor and the other terminal connected to the sixth conductor; 14. The semiconductor device according to claim 9, wherein the semiconductor device is a semiconductor device having a first insulating layer. [Appendix 15] further comprising a fourth capacitor and a fifth capacitor each having two terminals; the conductive member further includes a seventh conductor and an eighth conductor, each spaced apart from the first conductor, the second conductor, the third conductor, and the fourth conductor; the seventh conductor and the eighth conductor are spaced apart from each other and are each electrically connected to the control element; the fourth capacitor has one terminal connected to the fourth conductor and the other terminal connected to the seventh conductor; the fifth capacitor is connected to the fourth conductor and has the other terminal connected to the eighth conductor; 15. The semiconductor device according to any one of Supplementary Note 9 to Supplementary Note 14. [Appendix 16] a sixth capacitor having two terminals; the sixth capacitor has one terminal connected to the second conductor and the other terminal connected to the fourth conductor; 16. The semiconductor device according to any one of Supplementary Note 9 to Supplementary Note 15. [Appendix 17] The on-resistance of the first semiconductor element is smaller than the on-resistance of the second semiconductor element. 17. The semiconductor device according to claim 9. [Appendix 18] The on-resistance of the second semiconductor element is smaller than the on-resistance of the first semiconductor element. 17. The semiconductor device according to claim 9. [Appendix 19] When viewed in the first direction, the distance between a center of the first semiconductor element and a center of the control element is smaller than the distance between a center of the first conductor and a center of the control element. 19. The semiconductor device according to claim 9. [Appendix 20] When viewed in the first direction, the distance between the center of the second semiconductor element and the center of the control element is smaller than the distance between the center of the second conductor and the center of the control element. 19. The semiconductor device according to claim 9. [Appendix 21] the second conductor overlaps the fourth conductor when viewed in the second direction; 21. The semiconductor device according to claim 9. [Appendix 22] the first drain electrode includes a plurality of first drain pad portions each extending in a first extension direction perpendicular to the first direction; the first source electrode includes a plurality of first source pad portions each extending in the first extension direction; 22. The semiconductor device according to claim 1, wherein the plurality of first drain pad portions and the plurality of first source pad portions are arranged alternately in a first arrangement direction perpendicular to both the first direction and the first extension direction. [Appendix 23] the second drain electrode includes a plurality of second drain pad portions each extending in a second extension direction perpendicular to the first direction; the second source electrode includes a plurality of second source pad portions each extending in the second extension direction; the plurality of second drain pad portions and the plurality of second source pad portions are alternately arranged in a second arrangement direction perpendicular to both the first direction and the second extension direction, The second extension direction is inclined with respect to the first extension direction. 23. The semiconductor device according to claim 22. [Appendix 24] The inclination of the second extension direction with respect to the first extension direction is equal to or greater than 10° and equal to or less than 170°. 24. The semiconductor device according to claim 23. [Appendix 25] 25. The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element are made of gallium nitride. [Explanation of symbols]

[0209] A1 to A8, A31, A41: semiconductor device 1, 2: Semiconductor elements 1a, 2a: element main surface 1b, 2b: Back side of element 11, 21: Drain electrode 111, 211: Pad section 12, 22: Source electrode 121, 221: Pad section 13, 23: gate electrode 131, 132, 231, 232: Pad section 3: Control element 3a: Element main surface 3b: Back side of element 31 to 38: Element electrodes 4: Lead frame 4A~4J: Lead 49A, 49B, 49C: Insulation area 5A~5L: Wire 6: Sealing member 61: Resin main surface 62: Resin back 631~634: Resin side 7A~7D: Clips 8: Conductive substrate 81: Base material 82A~82H: Wiring section W1 to W7: Power conversion equipment B1: Circuit board 91~98,971,981: Wiring pattern C11 to C14, C21, C22, C24 to C27: Capacitors R15,R16:Resistor D1: Diode DR1, DR2: Drive circuit ER1, ER2: extended region GND1: 1st ground terminal GND2: 2nd ground terminal L1: Inductor LO:Load PS1,PS2: External power supply T1 to T8: External terminals TC1 to TC8: Connection terminals

Claims

1. A conductive member including a first conductor, a second conductor, and a third conductor spaced apart from one another; a first semiconductor element having a first main surface on which a first drain electrode, a first source electrode, and a first gate electrode are disposed; a second semiconductor element having a second main surface on which a second drain electrode, a second source electrode, and a second gate electrode are disposed; a first connection member that electrically connects the third conductor and the first drain electrode; a second connection member that electrically connects the first source electrode and the first conductor; a third connection member that electrically connects the first conductor and the second drain electrode; a fourth connection member that electrically connects the second source electrode and the second conductor; It is equipped with the first conductor is electrically connected to the first source electrode and the second drain electrode; the second conductor is electrically connected to the second source electrode and, when viewed in a first direction perpendicular to the first main surface, is adjacent to the first conductor in a second direction perpendicular to the first direction; the third conductor is electrically connected to the first drain electrode and is adjacent to the first conductor; the first semiconductor element and the second semiconductor element are connected in series to form a half-bridge type switching circuit, the first semiconductor element is mounted on the first conductor, and the first main surface faces a side opposite to a direction facing the first conductor in the first direction; The second semiconductor element is mounted on the second conductor, and the second main surface faces in the first direction opposite to the direction facing the second conductor.

2. the third connection member has a joint portion joined to the first conductor, The semiconductor device according to claim 1 , wherein the junction is joined to a region of the first conductor between the first semiconductor element and the second semiconductor element.

3. 3. The semiconductor device according to claim 1, wherein the first connection member overlaps a first insulating region that insulates the first conductor from the third conductor when viewed in the first direction.

4. 3 . The semiconductor device according to claim 1 , wherein the third connection member overlaps a second insulating region that insulates the first conductor from the second conductor when viewed in the first direction.

5. The semiconductor device according to claim 1 , wherein the second conductor and the third conductor overlap when viewed in the second direction.

6. a control element including a first element electrode and a second element electrode; a fifth connection member that electrically connects the first gate electrode and the first element electrode; a sixth connection member that electrically connects the second gate electrode and the second element electrode; It also has 6. The semiconductor device according to claim 1, wherein the control element outputs a first drive signal from the first element electrode to control the switching operation of the first semiconductor element, and outputs a second drive signal from the second element electrode to control the switching operation of the second semiconductor element.

7. the conductive member further includes a fourth conductor spaced apart from the first conductor, the second conductor, and the third conductor and carrying the control element; 7. The semiconductor device of claim 6, wherein the fourth conductor overlaps the first conductor when viewed in a third direction perpendicular to both the first direction and the second direction, and is positioned further in the third direction than the first conductor when viewed in the second direction.

8. The semiconductor device according to claim 7 , wherein the fourth conductor is positioned further in the third direction than the second conductor when viewed in the second direction.

9. The semiconductor device according to claim 8 , wherein each of the first conductor and the second conductor does not overlap with the fourth conductor when viewed in the second direction.

10. 10 . The semiconductor device according to claim 7 , wherein the fifth connection member overlaps only the first conductor and the fourth conductor of the conductive member when viewed in the first direction.

11. 11 . The semiconductor device according to claim 7 , wherein the sixth connection member overlaps only the second conductor and the fourth conductor of the conductive member when viewed in the first direction.

12. 12. The semiconductor device according to claim 7, wherein an on-resistance of the first semiconductor element is smaller than an on-resistance of the second semiconductor element.

13. 12. The semiconductor device according to claim 7, wherein an on-resistance of the second semiconductor element is smaller than an on-resistance of the first semiconductor element.

14. the first drain electrode includes a plurality of first drain pad portions each extending in a first extension direction perpendicular to the first direction; the first source electrode includes a plurality of first source pad portions each extending in the first extension direction; 14. The semiconductor device according to claim 1, wherein the plurality of first drain pad portions and the plurality of first source pad portions are alternately arranged in a first arrangement direction perpendicular to both the first direction and the first extension direction.

15. the second drain electrode includes a plurality of second drain pad portions each extending in a second extension direction perpendicular to the first direction; the second source electrode includes a plurality of second source pad portions each extending in the second extension direction; 15. The semiconductor device according to claim 14, wherein the plurality of second drain pad portions and the plurality of second source pad portions are alternately arranged in a second arrangement direction perpendicular to both the first direction and the second extension direction.

16. 16. The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element are made of gallium nitride.

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