Microcontroller

Abstract

The invention relates to a secure microcontroller (1) for controlling devices in a motor vehicle, the secure microcontroller (1) comprising a semiconductor substrate, a number of memory elements, at least one internal bus (2), at least one 8 / 16 / 32 / 64 bit microcontroller core, one or more data interfaces, and at least one true random number generator (15) based on quantum processes. The memory elements, the data interface, the generator based on quantum processes (15) and the microcontroller core (16) are connected to the internal bus (2). The generator based on quantum processes (15) generates and supplies random numbers on request of the microcontroller core (16). The microcontroller core (16) uses the program from one or more of the memory elements and the random number to generate a key. The microcontroller core (16) uses the program from one or more of the memory elements and the key to encrypt or decrypt data to be exchanged with devices external to the secure microcontroller (1) via the data interface. The semiconductor substrate incorporates the subsystems of the safety microcontroller (1) described herein.

Description

[Technical Field]

[0001] This PCT application claims priority from German Patent Application No. 102021128005.2, dated October 27, 2021, German Patent Application No. 102021130107.6, dated November 18, 2021, German Patent Application No. 102022110713.2, dated May 2, 2022, German Patent Application No. 102022125574.3, dated October 4, 2022, German Patent Application No. 102022125617.0, dated October 5, 2022, and German Patent Application No. 102022125768.1, dated October 6, 2022, the contents of which are incorporated by reference as constituting the subject matter of the present application.

[0002] The invention relates in particular to a microcontroller equipped with at least one true random number generator (English: Quantum Random Number Generator - QRNG) based on quantum processes, in particular as a cryptographic random number generator. [Background technology]

[0003] The automotive and other related industries are increasingly exposed to a wide variety of piracy threats. Counterfeiters replicate spare parts and products from the relevant industrial manufacturers, often using their brand names. A further risk is hacker attacks that affect data exchange within or with products, for example during car-to-car or car-to-x communication or data communication within vehicle components. Protection against hacker attacks is particularly important in autonomous systems and their external data communications.

[0004] In such systems, the entropy properties of currently employed random number generators for data encryption are often insufficient. In the background art, true random number generators (Quantum Random Number Generators, QRNGs) based on quantum processes are known, but they are difficult to integrate and have low quantum yields.

[0005] Details of the data signal processing unit with a microcontroller and a random number generator based on quantum processes are described, for example, in: [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 10,802,800 [Non-patent literature]

[0007] [Non-Patent Document 1] “Session key”, Wikipedia, the free encyclopedia, edited on October 1, 2020, URL: https: / / en.wikipedia.org / w / index.php?title=Session_key&oldid=981281879 [accessed May 31, 2022] [Non-patent document 2] “Integrated circuit”, Wikipedia, the free encyclopedia, edited on October 12, 2021, URL: https: / / en.wikipedia.org / w / index.php?title=Integrated_circuit&oldid=1049603915 [accessed May 31, 2022] [Non-patent document 3] “BIOS”, Wikipedia, the free encyclopedia, edited on October 24, 2021, URL: https: / / en.wikipedia.org / w / index.php?title=BIOS&oldid=1051566527 [accessed May 31, 2022] [Non-patent document 4] BURRI, S. et al., “SPADs for Quantum Random Number Generators and beyond”, 19th Asia-South Pacific Design Automation Conference (ASP-DAC), January 20-23, 2014, Singapore, IEEE, pp. 788-794, DOI: 10.1109 / ASPDAC.2014.6742986 [Non-Patent Document 5] Fabio Acerbi, Nicola Massari, Leonardo Gasparini, Alessandro Tomasi, Nicola Zorzi, Giorgio Fontana, Lorenzo Pavesi, Alberto Gola, “Structures and Methods for fully-integrated Quantum Random Number Generators”, IEEE Journal of selected topics in quantum electronics, Vol. 16, No. 3, May / June 2020 Summary of the Invention [Problem to be solved by the invention]

[0008] The present invention aims to provide an apparatus and method for generating truly random numbers based on photon processes. [Means for solving the problem]

[0009] In order to achieve the above object, the present invention proposes a microcontroller for controlling a device in a motor vehicle, the microcontroller comprising: a semiconductor substrate; a plurality of storage elements; at least one internal bus; At least a microcontroller core and one or more data interfaces; and at least one quantum process-based true random number generator; the storage element is connected to the internal bus; the data interface is connected to the internal bus; the quantum process-based generator is connected to the internal bus; the microcontroller core is connected to the internal bus; said quantum process based generator generating random numbers specifically in response to the requirements of said microcontroller core; the quantum process-based generator provides the random numbers; the microcontroller core generates a key using a program from one or more of the storage elements and the random number; the microcontroller core uses the program from one or more of the storage elements and the key to encrypt and decrypt data communicated internally or with external devices via the data interface; the semiconductor substrate integrally contains the safety microcontroller subsystems described herein; the quantum process-based generator having at least one first SPAD diode as a light source for the optical quantum signal; the quantum process-based generator has at least one second SPAD diode as a photodetector for receiving the photon signal; the quantum process-based generator having at least one processing circuit; the quantum process-based generator having at least one optical fiber for optically coupling the at least one first SPAD diode to the at least one second SPAD diode; the quantum-based generator having operating circuitry to provide electrical energy to the at least one first SPAD diode to generate light; The quantum-based generator has processing circuitry to detect a signal of the at least one second SPAD diode, form a random number from the signal of the at least one second SPAD diode, and provide the random number to the microcontroller core.

[0010] An essential feature of the microcontroller of the present invention is a quantum process-based generator (quantum process-based entropy source) for truly random number generation. This generator is based on photonic processes and on a combination of stimulated and spontaneous photon emission in at least one second or receiving SPAD diode. This receiving SPAD diode is connected via an optical fiber to at least one first or transmitting SPAD diode. Both SPAD diodes operate in Geiger mode.

[0011] An innovative feature is the formation of an optical fiber as at least a part or portion of one or more dielectric layers constituting a metallization stack as an insulating layer, the metallization stack being formed on a semiconductor material on which the first and second SPAD diodes are integrated. Alternatively, the optical fiber may connect two semiconductor substrates on which at least one first SPAD diode and at least one second SPAD diode are respectively formed. However, a preferred embodiment of the microcontroller comprises a semiconductor substrate on which all SPAD diodes are integrated and on which the optical fiber is disposed.

[0012] The spontaneous and stimulated photon emissions of the second SPAD diode cause its emission signal to have very narrow pulses (hereinafter referred to as spikes) of different heights. Thus, the emission signal has a first spike resulting from a single photon emission. When spontaneous photon emission coincides with stimulated photon emission, a second spike higher than the first spike occurs in the emission signal of the second SPAD diode. Because this combination of photon emissions is highly random and based on quantum processes, evaluating the time series of occurrences of the second spikes is suitable for generating truly random numbers therefrom.

[0013] In this regard, in a useful aspect of the present invention, the emission signal of the at least one second SPAD diode has a first spike and a second spike that is larger than the first spike, the first and second spikes are each larger than a pre-determinable reference value, the first spike is generated by spontaneous photon emission of the at least one second SPAD diode without simultaneous occurrence of stimulated photon emission of the at least one second SPAD diode, and the second spike is generated by simultaneous occurrence of spontaneous photon emission and photon emission of the at least one second SPAD diode stimulated by receiving a photon from the at least one first SPAD diode, and the processing circuitry of the quantum process based generator generates a first logic value or a second logic value as a bit for generating the random number by comparing a time interval of the second spike with a threshold value or by comparing time intervals of the second spikes with each other.

[0014] According to a variant of the present invention, the processing circuit generates the first logical value or the second logical value by comparing the time interval between two spikes with a threshold, and the processing circuit outputs the first logical value as a bit of the random number if the time interval is smaller than the threshold, and outputs the second logical value as a bit of the random number if the time interval is greater than the threshold, thereby generating the true random number.

[0015] According to a second variant of the generation of the true random number, the processing circuit generates the first logical value or the second logical value by comparing the time intervals of the second spikes of different pairs of second spikes, and the processing circuit may output the first logical value as a bit for generating the random number if the time interval of the last second spike is smaller than, for example, the time interval between the second to last second spike and the third to last second spike or the time interval between another pair of preceding second spikes, and may output the second logical value as a bit for generating the random number if the time interval of the last second spike is larger than, for example, the time interval between the second to last second spike and the third to last second spike or the time interval between another pair of preceding second spikes.

[0016] In both of the above-described variations of true random number generation, if an equality is detected in the comparison of the time interval with a threshold (Variation 1) or the comparison of time intervals with each other (Mode 2), this result is discarded for use as a random number. Alternatively, the result of the comparison that is equal can be used, but in that case, the first or second logical value must be determined purely randomly.

[0017] For completeness' sake, let us consider that a third spike in the emission signal may occur in the second or receiving SPAD diode, having a height approximately three times that of the first spike. Such an event occurs when the photon emission stimulated by the reception of a photon in the first SPAD diode coincides with the spontaneous and stimulated photon emission of the second SPAD diode. Advantageously, this "triple spike" is not used. Therefore, in this regard, when examining the emission signal of each second SPAD diode, the signal is compared with a predetermined reference value range within which it must fall in order to be evaluated for the generation of truly random numbers.

[0018] In order to parallelize the generation of the individual bits of the true random number, it is advantageous to provide multiple pairs of first and second SPAD diodes, in which case the emission signal of the second SPAD diode can be supplied to the processing circuitry, which uses the emission signal of each second SPAD diode to output a different one of the bits for generating the random number.

[0019] To continuously generate the individual bits of a truly random number, essentially a pair of one first and one second SPAD diode is sufficient, with the processing circuitry continuously outputting the logic values ​​of the bits used to generate the random number.

[0020] In another variation of the optical coupling of the first and second SPAD diodes, there is provided a single first SPAD diode and a plurality of second SPAD diodes optically coupled to the single SPAD diode, the emission signal of the second SPAD diode can be supplied to the processing circuitry, and the processing circuit can use the emission signal of each second SPAD diode to output another one of the bits for generating the random number.

[0021] Advantageously, an error detection unit and a pseudorandom number generator may be provided to detect functional errors and to generate random numbers even in the event of an error. If the error detection unit detects an error in the functioning of a component involved in the photon-based process of the quantum-process-based generator or in its processing circuit, the processing circuit of the quantum-process-based generator switches from outputting bits for generating random numbers using the emission signal of the at least one second SPAD diode to outputting bits for generating pseudorandom numbers generated by the pseudorandom number generator. It may be useful for the error detection unit to output an error signal upon detecting an error, which is in particular representative of the type and / or cause of the error. It is advantageous for the error detection unit to detect not only the presence of an error, but also the type of error that has occurred. The reaction of the quantum-based generator to such an outcome depends on the application and may, for example, mean that a self-test is performed. However, if an error occurs in the quantum-based generator, it is preferable to switch to the pseudorandom number generator and generate pseudorandom numbers, for example, based on the last bit generated by the quantum-based generator before the error was detected.

[0022] The sources of errors include the following: - Abnormalities in the supply voltage to individual components of the microcontroller Generation of false signals in the first and / or second SPAD diodes - Anomalies in the optical fiber and / or when coupling the first and / or second SPAD diodes to the optical fiber Circuit failures in the analog and / or digital components of the microcontroller and quantum random number generator The false entropy of random numbers that can be generated by testing, as described, for example, in David Johnston, “Random Number Generators - Principles and Practices”, Chapters 8 and 9, 2018, Walter De Gruyter GmbH, Berlin / Boston, ISBN 978-1-5015-1530-2

[0023] Variations of the microcontroller with the error detection unit and pseudorandom number generator described above can also be implemented using a microcontroller with a different quantum-based generator than the one described above, for which separate protection is claimed for the subject matter of this aspect.

[0024] In a useful embodiment of the present invention, the storage element may comprise one or more read-write memories RAM, one or more writable non-volatile memories (specifically EEPROM memories, flash memories and / or one-time programmable (OTP) memories), one or more pure read-only memories and / or one or more non-volatile manufacturer memories (specifically one or more manufacturer ROMs, one or more manufacturer EEPROMs and / or one or more manufacturer flash memories).

[0025] In a preferred embodiment of the present invention, the manufacturer ROM may include boot software.

[0026] In another preferred embodiment of the present invention, a manufacturer memory firewall may be provided between the manufacturer memory and the internal bus.

[0027] In a preferred aspect of the present invention, the microcontroller Basic clock generator, a clock generation circuit, Reset circuit, a current supply or Vcc circuit with a voltage regulator to provide the operating voltage; ground circuit, Input / output circuits and / or may comprise one or more processing modules; the processing module communicating with the internal bus; The processing module: CRC module (Cyclic Redundancy Check), a clock generation module; a module having a DES accelerator and / or an AES accelerator; one or more timer modules; Safety monitoring control circuit and The data interface may include one or more modules, specifically, a Universal Asynchronous Receiver Transmitter.

[0028] In another useful embodiment of the present invention, the semiconductor substrate having a surface; the semiconductor substrate having semiconductor material below the surface; the surface of the semiconductor substrate having a metallization stack; the metallization stack comprises an electrically insulating layer disposed on the surface of the semiconductor substrate, typically a structured, optically transparent electrically insulating layer; at least a portion of the transparent, electrically insulating layer constitutes the at least one optical fiber; the first SPAD diode emits photons from the semiconductor material of the semiconductor substrate into the optical fiber (50); The at least one optical fiber may carry such photons to the second SPAD diode.

[0029] In a preferred embodiment of the invention, the optical fiber may illuminate the second SPAD diode such that light re-enters the semiconductor material of the semiconductor substrate from within the optical fiber and there reaches the device portion of the second SPAD diode.

[0030] In another preferred embodiment of the present invention, the at least one operating circuit at least temporarily supplies electrical energy to the at least one first SPAD diode; the at least one first SPAD diode, when supplied with sufficient electrical energy, provides photons to the at least one optical fiber; the at least one optical fiber conveying such photons to the second SPAD diode; The at least one optical fiber may emit such photons to the second SPAD diode.

[0031] In a useful embodiment of the present invention, the one data bus interface may be a wired automotive data bus interface, or one or more of the plurality of data bus interfaces may be a wired automotive data bus interface.

[0032] In another useful aspect of the present invention, the one or more wired automotive data bus interfaces are: CAN data bus interface, CAN-FD data bus interface, FlexRay data bus interface, PSI5 data bus interface, DSI3 data bus interface, LIN data bus interface, Ethernet data bus interface, LIN data bus interface and / or It may also be configured as a MELIBUS data bus interface.

[0033] In a preferred aspect of the present invention, the one data bus interface may be a wireless data bus interface, or one or more of the plurality of data interfaces may be wireless data bus interfaces.

[0034] In another useful aspect of the invention, the one or more wireless data bus interfaces: WLAN interface, Mobile communication interface and / or It may also be configured as a Bluetooth interface.

[0035] In a preferred aspect of the present invention, the one data bus interface may be a wired data bus interface, or one or more of the plurality of data interfaces may be wired data bus interfaces.

[0036] In another preferred aspect of the present invention, the one or more wired data bus interfaces are: KNX data bus interface, EIB data bus interface, DALI® data bus interface and / or It may also be configured as a PROFIBUS data bus interface. [Effects of the Invention]

[0037] A key advantage of the present invention is that, rather than using the semiconductor material in which the optically coupled SPAD diodes are integrated for photon transport, one or more dielectric layers near the surface of the semiconductor material, i.e., insulating layers of a metallization stack, are used for transport. This significantly increases the "yield" of photons reaching the receiving SPAD diode. This means that more events can be observed at the receiving SPAD diode in a shorter time, which can be used to generate random numbers based on longer quantum processes in a very short time, or to generate multiple quantum-process-based random numbers in a very short time. This improves the effectiveness of generating random numbers based on quantum processes that are secure against so-called post-quantum cryptography (PQC) or quantum-safe cryptography.

[0038] The present invention will be described in detail below using various embodiments with reference to the drawings. [Brief explanation of the drawings]

[0039] [Figure 1]FIG. 1 is a block diagram illustrating an example of a safety microcontroller 1. [Figure 2] 2 shows an example of a flow diagram for product protection using a first safety microcontroller (IC1) and a second safety microcontroller (IC2) according to the present invention, where the first safety microcontroller (IC1) and the second safety microcontroller (IC2) exchange data that is encrypted using random numbers preferably generated by one or more quantum process-based true random number generators 15. [Figure 3] FIG. 3 shows how a SPAD diode is integrated into a semiconductor material. [Figure 4] FIG. 4 illustrates the combination of a first SPAD diode with a second SPAD diode, both of which are integrated into a semiconductor material and optically coupled by an optical fiber disposed on the semiconductor material as part of a metallization stack, i.e., as part or a portion of an insulating layer of the metallization stack. [Figure 5] FIG. 5 illustrates the combination of a first SPAD diode with a second SPAD diode, both of which are integrated into a semiconductor material and optically coupled by an optical fiber disposed on the semiconductor material as part of a metallization stack, i.e., as part or a portion of an insulating layer of the metallization stack. [Figure 6] FIG. 6 illustrates a quantum-based entropy source consisting of at least one transmitting SPAD diode and at least one receiving SPAD diode in combination with an optical fiber optically coupling them and having an evaluation operating circuit. [Figure 7] FIG. 7 is a diagram in which a monitoring circuit is added to the same configuration as FIG. [Figure 8] FIG. 8 is a flow diagram illustrating an entropy extraction method according to one embodiment of the present invention. [Figure 9]FIG. 9 shows a typical output signal of a receiving SPAD diode. [Figure 10] FIG. 10 is a diagram illustrating the steps of a method for generating quantum random numbers using a photon-based process according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0040] The drawings illustrate in simplified form the principal parts of the proposed apparatus and method. For purposes of illustration, a specific example constructed in accordance with the teachings of the present invention will now be described with reference to the accompanying drawings.

[0041] The embodiments of the present invention in the following specification and drawings are merely examples and are not limited to the specific examples or elements described. Various examples can be derived by modifying, combining, or changing some elements. Furthermore, a person skilled in the art can derive examples or elements not literally described from the specification or drawings.

[0042] The integrated circuit according to the present invention preferably comprises a secure microcontroller 1, i.e., a microcontroller for securely encrypting data. FIG. 1 is a block circuit diagram illustrating an example of the secure microcontroller 1. The secure microcontroller 1 comprises, for example, a number of storage elements connected to an internal bus 2. The storage elements may comprise, for example, one or more read-write memories RAM 3, and / or one or more writable non-volatile memories, such as EEPROM memory 4, flash memory 4, and / or OTP memory 4. The secure microcontroller 1 also preferably comprises one or more purely read-only non-volatile memories 5, such as ROM. Furthermore, the secure microcontroller 1 preferably comprises one or more writable and / or non-writable non-volatile manufacturer memories 6, which typically contain reference data important for subsequent testing of the microcontroller or other electronic devices. In the case of non-writable manufacturer memories 6, the manufacturer memories 6 may be manufacturer ROMs. The manufacturer ROM 6 preferably contains boot software. The secure microcontroller 1 comprises one or more cryptographic accelerators 7, such as, for example, a DES accelerator and / or an AES accelerator 7, which accelerate cryptographic calculations and are connected to the internal bus 2. For example, at least one manufacturer memory firewall 8 is preferably provided between the manufacturer memory 6 and the internal bus 2. A microcontroller core 16 accesses these memories via the data bus 2. The secure microcontroller 1 comprises, for example, a processing module which communicates with the microcontroller core 16 via the internal bus 2.The processing modules of the microcontroller 1 preferably comprise at least one of the following modules: a CRC module (Cyclic Redundancy Check) 11, a clock generation module 12, one or more timer modules 13, a safety monitoring control circuit 14, one or more quantum-based true random number generators 15 (English: Quantum Random Number Generators: QRNG), an 8 / 16 / 32 / 64-bit microcontroller core 16, and one or more data interfaces 17, in particular one or more Universal Asynchronous Receiver Transmitters (UARTs) for supporting high-speed continuous data. Other circuit components of the safety microcontroller 1 include, for example, one or more basic clock generation circuits 21 (CLK) and / or one or more clock generation modules 12, a reset circuit 22, a current supply or Vcc circuit 23 with a voltage regulator for providing the operating voltage, a ground circuit 24, and an input / output circuit 25.

[0043] The safety microcontroller 1 is preferably configured to perform secure authentication, so that in addition to the authentication code the safety microcontroller 1 stores further data such as one or more life and expiry data, and / or logistic data, and / or commercial data, and / or website and email addresses, and / or image data, as well as instruction sets for the vehicle controls with which the microcontroller core 16 communicates via the data interface. The safety microcontroller 1 may also store application data.

[0044] The first integrated circuit preferably comprises a secure microcontroller 1 that is configured to facilitate secure authentication of the product, for example.

[0045] 2 shows an example of a method for fabricating a circuit for a product having a secure microcontroller 1 according to the present invention. The method includes, for example, a step of writing a product ID into a second integrated circuit of the product (block 250). According to the present application, the second integrated circuit preferably comprises a second secure microcontroller 1. The method includes, for example, a step of writing an authentication code corresponding to the product ID into the memory of the first integrated circuit of the first secure microcontroller 1 (block 211). According to the present application, the first integrated circuit of the product also preferably comprises a secure microcontroller 1. The method includes, for example, a step of writing a different product ID and a different corresponding authentication code into the memory of each integrated circuit of each secure microcontroller 1. It is also possible to write a different product ID and a different corresponding authentication code into the memory of each integrated circuit of each secure microcontroller 1 for each product (block 221), so that each product has a unique product ID and a unique authentication code. This last-mentioned step results, for example, in a secure and unique authentication code for each product.

[0046] Some features described herein, for example, enable secure authentication of a circuit or product while also facilitating cost-effective, consistent production of the circuit or product. For example, the second integrated circuit is preferably configured to perform secure authentication. In various examples, various host devices, such as automobiles, smartphones, web servers, or any data processing device, can authenticate the circuit or product. In one example, an interface is established between the host device and the circuit via a control computer in the automobile. In another example, a first integrated circuit of the circuit is configured to store additional data, such as product-related code or product configuration information. The host device can access, modify, or process such additional data only after secure authentication via the first integrated circuit, for example. The first integrated circuit is configured to provide or allow access to the additional data only after authentication, for example. For example, little or no product adjustment is required for use in different automobile series.

[0047] The internal data bus 2 (see FIG. 1) can have multiple data buses 2 for multiple microcontroller cores 16, allowing access to the various sub-devices of the safety microcontroller 1 independently, time-shifted and / or overlapping, or simultaneously. However, typically the safety microcontroller 1 will only have one internal data bus 2 and one microcontroller core 16. The microcontroller core 16 is preferably an Advanced Risk Maschine (AMR) processor or the like, and is preferably an 8-bit, 16-bit, 32-bit, or 64-bit microcontroller computer core.

[0048] The secure microcontroller 1 preferably includes one or more read-write memories RAM3. These may be, for example, static RAMs and / or magnetoresistive and / or ferroelectric memories. Alternatively, the memory may be a dynamic read-write memory such as a DRAM, which requires periodic reading and rewriting in a refresh cycle. The secure microcontroller 1 according to the present invention may have access logic that periodically performs refresh operations to access the memory. However, DRAMs generally open up opportunities for attack and often have potential vulnerabilities. The microcontroller core 16 preferably has access to the read-write memories RAM3 via the internal data bus 2.

[0049] The secure microcontroller 1 preferably comprises one or more writable non-volatile memories 4, which are preferably accessible by the microcontroller core 16 using an internal data bus 2. The non-volatile memories may include, for example, an EEPROM memory 4, a flash memory 4 or an OTP memory 4, where OTP stands for "One Time Programmable" in English.

[0050] Possible attacks include erasing the non-volatile memory 4 by radiation, such as X-rays and / or ionizing radiation and / or heating of the memory cells. In response, the secure microcontroller 1 preferably includes one or more security monitoring control circuits 14 that monitor the data integrity of the memory cells of the erasable memory 4. At least two check bits are provided for each data word, preferably 8 bits long, i.e., one byte, and the memory cells preferably have redundancy so that at least one check bit always has the content 1 and the other check bit always has the content 0. For example, the first check bit can be a parity bit for the byte, and the second check bit can be the inverse of the parity bit. In this case, an attack, such as an ionizing radiation attack, would reset both check bits to the same value. The one or more security monitoring control circuits 14 detect this discrepancy and block further access from the secure microcontroller 1.

[0051] Each bit of the memory of the safety microcontroller 1 is preferably designed to be doubled, whereby each logical data bit is realized as a pair consisting of a first physical data bit having a first internal logic value and a second physical data bit having a second internal logic value. In this case, the second internal logic value is typically the logical inverse of the first internal logic value. One or more safety monitoring control circuits 14 preferably monitor that this is always the case. The one or more safety monitoring control circuits 14 detect deviations and preferably block, for example, the microcontroller core 16 from executing further programs or particular program portions and / or block access to data when deviations occur.

[0052] The safety microcontroller 1 preferably comprises one or more reset circuits 22 (see FIG. 1 ). Each reset circuit 22 resets the safety microcontroller 1 and / or a subsystem of the safety microcontroller 1 to a predetermined state upon predetermined or configurable reset conditions and / or combinations and / or time sequences of such reset conditions. For example, these conditions may be signaling of one or more safety monitoring control circuits 14. These conditions may also be changes in the potential and / or values ​​of the operating voltages of the safety microcontroller. Such conditions may also relate to the integrity of the enclosure of the safety microcontroller 1.

[0053] The safety microcontroller 1 preferably includes a detector for detecting the opening of the housing of the safety microcontroller 1. Here, this can be, for example, a wire surrounding or covering the safety microcontroller 1 or at least partially covering the safety microcontroller 1 as a textile mesh or woven fabric. Alternatively, it can be a network of wires covering the safety microcontroller 1, specifically dedicated to detecting attacks. For example, the safety microcontroller 1 can include a first input / output, whereby current can be supplied to the wire and taken off again at a second input / output. If the current flow stops, an attack is indicated, which is detected by one or more safety monitoring control circuits 14 and communicated to, for example, the microcontroller core 16 of the safety microcontroller 1 according to the invention. In case of such predicted damage to the integrity of the housing, for example, one or more of the one or more safety monitoring control circuits 14 can block write and / or read access to the memory contents of the memory of the safety microcontroller 1, erase such contents, set them to a predetermined value, overwrite them with meaningless data, or otherwise handle the situation. The memory of the safety microcontroller 1 preferably comprises one or more pure read-only non-volatile memories 5, such as ROM. The ROM 6 of the safety microcontroller 1 preferably contains data and / or program instructions set by the designer.

[0054] The safety microcontroller 1 (see, e.g., FIG. 1 ) preferably includes one or more writable and / or non-writable non-volatile manufacturer memories 6 in which a semiconductor manufacturer or other supplier can store manufacturing and security data, such as a serial number. The semiconductor manufacturer preferably blocks access to the writable and / or non-writable non-volatile manufacturer memories 6 after final manufacturing testing. The writable and / or non-writable manufacturer memories 6 are preferably accessible using a manufacturer password. A dual-key approach is often effective. In such cases, a customer (downstream of the semiconductor manufacturer) stores a customer password in a customer block register that can also block access using a password. The semiconductor manufacturer preferably has access to all memory areas of the safety microcontroller 1 using only the customer and manufacturer passwords. The semiconductor manufacturer preferably provides an analysis password that causes one or more of the one or more safety monitoring control circuits 14 to erase the customer content, typically using a reset circuit 22, and make all memory areas of the safety microcontroller 1 accessible for error analysis. In the case of a non-writable manufacturer memory, the manufacturer memory 6 can be, for example, a manufacturer ROM, the contents of which are set, for example, during manufacture of the semiconductor circuit of the secure microcontroller.

[0055] The secure microcontroller 1 is typically configured to receive and / or transmit data and / or program code portions and / or instructions encrypted by cryptographic methods stored in its memory and executed by the microcontroller core 16. Some of these methods require significant computational power. Therefore, it has been found useful to have one or more specialized hardware accelerators (preferably one or more crypto accelerators 7) execute certain program portions of these cryptographic methods on behalf of the microcontroller core 16, preferably accelerating these program portions with specially synthesized hardware logic, rather than having the microcontroller core 16 execute these program portions as sub-steps of the cryptographic methods. For this purpose, the secure microcontroller 1 preferably includes, for example, a DES accelerator for the Data Encryption Standard (DES) algorithm and / or an AES accelerator 7 for the execution of the Advanced Encryption Standard (AES) algorithm. The microcontroller core 16 typically communicates with these hardware accelerators 7 via the internal data bus 2. The microcontroller core 16 preferably includes a redundant clock system, allowing it to detect accesses to the clock system. One or more of the one or more safety monitoring control circuits 14 can monitor the consistency of the logical content of the preferred multiple redundant clock systems to detect attacks and errors. Access to the manufacturer memory by the microcontroller core 16 and the test logic of the safety microcontroller 1 is preferably prevented by one or more manufacturer memory firewalls 8, which, as described above, can preferably be defeated by a manufacturer password. To minimize the success rate of an attack, the number of incorrect entries is preferably very limited.

[0056] The safety microcontroller preferably comprises one or more CRC modules (Cyclic Redundancy Check) 11, which in the case of a transmitting operation generate CRC data for continuous data communication, as adopted in most data protocols, in order to detect erroneous data transmissions, and in the case of a receiving operation, allow for the confirmation of correct reception of the data message. The safety microcontroller 1 preferably comprises one or more clock generation modules 12 (English: Clock Driver, CLK) which generate one or more clocks for operating the circuits of the safety microcontroller. The one or more clock generation modules (English: Clock Driver, CLK) 12 preferably generate redundant clocks to allow the detection of attacks on the clock system. The safety microcontroller 1 typically comprises one or more timer modules 13, which are necessary, for example, to detect timeouts. The safety microcontroller 1 preferably comprises one or more watchdog timers which monitor the execution of various program parts. These watchdog timers can be part of one or more safety monitoring control circuits 14.

[0057] According to the present invention (see, e.g., FIG. 1 ), the secure microcontroller 1 includes at least one quantum-process-based generator 15. Quantum-based processes have the advantage of being based on true randomness. In the 1970s, physicist Bell disproved the theory of "hidden parameters." That is, there is no hidden cause for the randomness of quantum mechanical events, such as the emission of photons. The microcontroller core 16 can be, for example, an 8-bit microcontroller core, a 16-bit microcontroller core, a 32-bit microcontroller core, a 64-bit microcontroller core, or a 128-bit microcontroller core. The secure microcontroller 1 can include one or more 8 / 16 / 32 / 64 / 128-bit microcontroller cores 16, preferably accessible to other subsystems via one or more internal data buses 2. The secure microcontroller 1 preferably includes one or more data interfaces 17, such as one or more Universal Asynchronous Receiver Transmitters (UARTs) for supporting continuous high-speed data. The safety microcontroller 1 preferably comprises one or more basic clock generators 21 (CLK), which preferably supply the basic clock 12 to one or more clock generation modules (English: Clock Driver, CLK), respectively. The basic clock generators 21 (CLK) are preferably oscillators. The safety microcontroller 1 also preferably comprises one or more current supply or Vcc circuits 23 with voltage regulators, which provide the operating voltage for the safety microcontroller 1. The safety microcontroller 1 also preferably comprises one or more ground circuits 24 (i.e., circuits inserted into the ground line or "grounded" circuits, in the simplest case, wiring) with reverse polarity protection and protection circuits against manipulation of the potential of the semiconductor substrate, for example. For example, it is useful if one or more of the ground circuits 24 have reverse polarity protection.For example, it is useful if one or more of the ground circuits 24 and / or one or more of the current supply or Vcc circuits 23 interact so that modulation of the power consumption and / or internal resistance and / or voltage drop across the supply voltage terminals of the safety microcontroller does not, at least temporarily, affect the operation and / or state of the safety microcontroller.

[0058] For controlling and / or communicating with and / or monitoring other devices, it is generally useful for the safety microcontroller to have one or more input / output circuits 25, typically configured as digital inputs and / or digital outputs, preferably also tri-stateable. The safety microcontroller 1 may have an analog-to-digital converter, allowing the safety microcontroller 1 to monitor internal and external analog values, such as operating voltages. In some cases, the safety microcontroller 1 may be provided with a driver stage, for example, to drive actuators. The actuators may be motors and / or other resistive and / or inductive and / or capacitive loads. Such driver stages may include, for example, half-bridges and / or H-bridges. It is also conceivable to use the driver stage as a power supply for lighting, such as LEDs.

[0059] Thus, according to the present invention (see, for example, FIG. 1 ), a safety microcontroller 1 for controlling devices in a motor vehicle is proposed, the safety microcontroller 1 comprising a semiconductor substrate. The safety microcontroller 1 is preferably fabricated in CMOS, bipolar, or BiCMOS circuit technology. The safety microcontroller preferably comprises a plurality of storage elements, one or more internal data buses 2, one or more 8 / 16 / 32 / 64-bit microcontroller cores 16, one or more data interfaces, and one or more quantum process-based generators 15. The quantum process-based generators 15 differentiate the proposed safety microcontroller 1 from prior art generators based on so-called true random number generators, which generate random numbers with poor von Neumann entropy and are therefore "less random."

[0060] The internal data bus 2 can have multiple data buses. A storage element of the secure microcontroller 1 is typically connected to the internal data bus 2. A data interface is also typically connected to the internal data bus 2. One or more quantum process-based generators 15 are preferably also connected to the internal data bus 2. One or more microcontroller cores 16 are also preferably connected to the internal data bus 2. The one or more quantum process-based generators 15 typically generate one or more random numbers in response to requests from the microcontroller cores 16. The random numbers have particularly good entropy compared to the random numbers of true random number generators of the background art. Preferably, one or more of the microcontroller cores 16 generate one or more keys using a program from one or more of its storage elements and one or more of the generated random numbers. Typically, one or more microcontroller cores 16 use respective programs from one or more of their storage elements to encrypt and / or decrypt data that they communicate with devices external to the secure microcontroller, typically via one or more data interfaces, with respective ones of a plurality of keys. Typically, a semiconductor substrate carries substantially all of the sub-devices of the secure microcontroller 1 together.

[0061] In a first development of the safety microcontroller 1 (see FIG. 1 ), the storage elements of the safety microcontroller 1 comprise one or more read-write memories RAM 3, one or more writable non-volatile memories 4 (in particular EEPROM memories 4, flash memories 4 and / or OTP memories 4), one or more purely read-only memories and / or one or more non-volatile manufacturer memories. The one or more manufacturer memories can for example comprise one or more manufacturer ROMs 6, one or more manufacturer EEPROMs and / or one or more manufacturer flash memories.

[0062] In a second development, the manufacturer memory, in particular the manufacturer ROM 6, comprises boot software for the secure start-up of the safety microcontroller.

[0063] In a third development (see FIG. 1), the secure microcontroller 1 is provided with a manufacturer memory firewall 8 between the manufacturer memory 6 and the internal bus 2, which prevents unauthorized access to the manufacturer memory.

[0064] In a fourth development (see FIG. 1 ), the secure microcontroller 1 comprises one or more of the following components: a basic clock generator 21 (CLK), a clock generation circuit 12, a reset circuit 22, a current supply or Vcc circuit 23 with a voltage regulator for providing different operating voltages, a ground circuit 24, an input / output circuit 25, and one or more processing modules, where the processing modules communicate with an internal data bus 2 and, typically, with a microcontroller core 16. The processing modules preferably comprise one or more of the following components: a CRC module (Cyclic Redundancy Check) 11, a clock generation module 12, cryptographic accelerators, in particular a DES accelerator and / or an AES accelerator 7, one or more timer modules 13, one or more secure monitoring control circuits 14, one or more data interfaces, in particular one or more Universal Asynchronous Receiver Transmitters (UARTs) 17 (see FIG. 1 ).

[0065] In a fourth development of the safety microcontroller 1 (see FIGS. 4 and 5), the safety microcontroller 1 comprises at least one first SPAD diode 44 and at least one second SPAD diode 45, at least one optical fiber 50, at least one processing circuit, and at least one operating circuit. The circuit-technical integration of a SPAD diode (e.g., SPAD diode 44 or 45) is shown again in FIG. 3. In the fourth development according to FIG. 4, the quantum process-based generator 15 (see FIG. 1) comprises at least a first SPAD diode 44 as a light quantum signal source and a second SPAD diode 45 as a light quantum signal detector. In this fourth development, the quantum process-based generator 15 also comprises at least a processing circuit and an optical fiber 50. In this fourth development, the at least one optical fiber 50 optically couples the at least one first SPAD diode 44 to the at least one second SPAD diode 45. The operating circuit supplies electrical energy to the first SPAD diode 44 so that it emits photons. The emission of photons occurs when a sufficient bias voltage is applied to the first SPAD diode 44. In this fourth development, the processing circuit detects the (output) signal of the second SPAD diode 45 and generates a random number therefrom.

[0066] 4, optical fiber 50 is comprised of a single electrically insulating layer disposed on surface 46 of semiconductor substrate 40, whereas FIG. 5 illustrates an embodiment in which optical fiber 50 is comprised of, for example, two optically transparent, electrically insulating insulating layers 34', 34".

[0067] The processing circuitry then preferably provides the random numbers thus generated to one or more of the one or more microcontroller cores 16 via internal data bus 2 (FIG. 1). Aspects of this processing circuitry are described below in connection with FIGS. 6-9.

[0068] In a sixth development of the invention (see FIGS. 4 and 5 ), the semiconductor substrate has a surface 46. Typically, the semiconductor substrate comprises a semiconductor material below the surface 46. In particular, when using conventional semiconductor circuit manufacturing processes such as CMOS, bipolar or BiCMOS processes, a metallization stack 34 consisting of structured metal layers and an insulating layer electrically insulating them is provided on the surface 46 of the semiconductor substrate, with at least one of these insulating layers 34 at least partially or partially constituting the optical fiber 50. Here, the structured metal layers typically constitute conductive paths electrically separated from one another by the insulating layer. The metallization stack therefore typically comprises a structured, optically transparent, electrically insulating insulating layer 34, for example made of silicon oxide, provided on the surface 46 of the semiconductor substrate. Preferably, at least a part of this insulating layer 34 on the surface 46 of the semiconductor substrate (i.e., part of the insulating layer in the horizontal and / or vertical extension) constitutes the optical fiber 50. A portion of the metallization stack above the insulating layer 34 is shown schematically in FIGS. 4 and 5. The first SPAD diode 44 typically emits light 47 from the semiconductor material of the semiconductor substrate into the optical fiber 50. That is, in contrast to the background art, the first SPAD diode 44 typically emits upward, perpendicular to the surface 46, rather than laterally to the semiconductor substrate, where attenuation is higher. This allows the device to directly couple more photons from the first SPAD diode 44 to the second SPAD diode 45. The optical fiber 50 transports the photons 48 from the first SPAD diode 44 through the optical fiber 50 to the second SPAD diode 45 with almost no loss compared to the background art. The light (photons) are then reflected by the bottom surface of the metallization stack 43. The optical fiber 50 illuminates the photons 48 of the first SPAD diode 44 onto the second SPAD diode 45 such that light 49 from within the optical fiber 50 re-enters the semiconductor material of the semiconductor substrate at the surface 46, where it reaches the device portion of the second SPAD diode 44. The second SPAD diode 45 then generates an output signal in response to the illumination of the photons 48 (of the light 49), from which a random number is generated based on a quantum process as described below.

[0069] Typically, at least one operating circuit provides, at least temporarily, electrical energy to at least one first SPAD diode 44. When the at least one first SPAD diode 44 receives sufficient electrical energy, it provides photons 47 to at least one optical fiber 50, which then transports these photons 48. The at least one optical fiber 50 then transmits the photons 48 as photons 49 to the second SPAD diode 45, generally "from above." This photon transport from the first SPAD diode 44 to the second SPAD diode 45 has a very high quantum efficiency, since, due to low attenuation in the optical fiber 50, far fewer photons are lost than in background art configurations using highly absorbing semiconductor substrates. Therefore, in the configuration shown here, a pair consisting of one first SPAD diode 44 and one second SPAD diode 45 is sufficient (although, of course, multiple pairs of SPAD diodes can be used in accordance with the present invention). In the background art, multiple SPAD diodes are always used on both the transmitting and receiving sides.

[0070] FIG. 5 shows two or more dielectric layers, i.e., optically transparent insulating layers 34′, 34″, directly adjacent to each other in at least some areas and not separated by a metallization layer in these areas, constituting an optical fiber 50′. In this embodiment, the contacts 51 and 52 of the SPAD diodes 44 and 45 are positioned in pairs, located on either side of the central area of ​​the optical fiber 50′, so that in the portion of the insulating layers 34′, 34″ that are adjacent to each other on the plane 53, the optical fiber transports photons 47 of the SPAD diode 44, as shown at 48, through both insulating layers 34′, 34″, not necessarily only the top layer, until it reaches the SPAD diode 45 at 49. Advantageously, the contacts 51, 52 also function as reflectors and “inject” the photons into the SPAD diode 45. In this regard, the contacts 51, 52 of the SPAD diode 44 also function as reflectors and “divert” the photons 47 generated by the SPAD diode 44 back to the SPAD diode 45.

[0071] In a further development of the safety microcontroller 1 according to the invention, at least one of the one or more data interfaces is a wired vehicle data bus interface, which can be, for example, a CAN data bus interface, a CAN-FD data bus interface, a FlexRay data bus interface, a PSI5 data bus interface, a DSI3 data bus interface, a LIN data bus interface, an Ethernet data bus interface, a LIN data bus interface or a MELIBUS data bus interface.

[0072] In a further development of the safe microcontroller 1 according to the invention, the at least one data interface is a wireless data bus interface, which can be, for example, a WLAN interface or a Bluetooth interface.

[0073] In a further development of the safety microcontroller 1 according to the invention, the at least one data interface is a wired data bus interface. A wireless data bus interface can be, for example, a KNX data bus interface, an EIB data bus interface, a DALI data bus interface or a PROFIBUS data bus interface.

[0074] Figure 6 shows a simplified block diagram of a quantum-based random number generator QRNG 400 according to one embodiment of the present invention. The digital circuitry of the illustrated device is preferably clocked by a common clock. The configuration includes an entropy source 401 based on a quantum process, a preferably broadband high-frequency amplifier 402, an analog-to-digital converter 403 having, for example, 14-bit resolution and a sampling rate of, for example, 125 MS / s, and a field-programmable gate array (FPGA) 404.

[0075] The entropy source 401 includes a 2D array of single-photon avalanche diodes (SPADs) 401.1 and 401.3. These SPAD diodes operate in Geiger mode with a supply voltage exceeding their breakdown voltage. Each SPAD diode is connected in series with a quenching resistor 401.4. The quenching resistor 401.4 prevents thermal destruction of the diode in the event of a charge avalanche. The current signal of the SPAD diode is measured via a shunt resistor, which may be the quenching resistor or an additional resistor. In the example of FIG. 6, the array of SPAD diodes includes, for example, four (active or transmitting) SPAD diodes 401.1 and twelve (passive or receiving) SPAD diodes 401.3, which are connected to the SPAD diodes 401.1 via optical fiber 401.2, as previously described for optical fiber 50 in FIGS. 4 and 5. The active SPAD diode 401.1 emits light. The SPAD diode 401.1 corresponds to the first SPAD diode 44 in FIGS. 4 and 5. The active SPAD 401.1 is preferably arranged in an array of SPAD diodes. The proposed arrangement operates the active SPAD diode 401.1 well above its breakdown voltage by providing it with a high supply voltage. This increases the dark count rate and the number of spontaneously emitted photons 47. The optical fiber 401.2 transports some of these photons as photons 48 to the passive SPAD diode 401.3. The optical fiber 401.2 corresponds, for example, to the optical fiber 50 in FIGS. 4 and 5. Each passive SPAD diode 401.3 corresponds, for example, to the second SPAD diode 45 in FIGS. 4 and 5. The proposed arrangement provides a high supply voltage to the passive SPAD diode 401.3, operating it just above its breakdown voltage, and the passive SPAD diode 401.3 is preferably arranged in a ring around the active SPAD diode 401.2.The passive SPAD diode 401.3 detects photons arriving via the optical fiber 401.2 and generates a voltage signal in response to the arriving photons, for example by causing a current to flow through a shunt resistor.

[0076] The voltage signal 405 of the entropy source 401 is preferably applied to a high frequency amplifier 402, e.g., a 40 dB broadband amplifier. The high frequency amplifier 402 preferably has a bandwidth of 30 to 4000 MHz and a 1 dB compression point of 20 dBm. The voltage amplitude of the entropy source 401 voltage signal 405 typically varies in the sub-millivolt range. The high frequency amplifier 402 amplifies the voltage amplitude of the entropy source 401 voltage signal 405 to, e.g., 50 to 150 mV.

[0077] The amplifier output signal 406 of the high-frequency amplifier 402 is converted from analog to digital by an ADC 403 and then transmitted to, for example, an FPGA 404. Naturally, other discrete or ASIC-based approaches are also possible. In this regard, the FPGA is merely one of many different approaches for implementing the technical teachings presented in this embodiment. The FPGA 404 preferably includes a microcontroller, such as a Xilinx Zynq7010 with a dual-core Arm Cortex-A9 MPCore processor. This FPGA 404 is part of the SPAD evaluation circuit of this embodiment, which further includes, in the example of FIGS. 4 and 5 , a 14-bit ADC 403 with a sampling rate of, for example, 125 megasamples / s and a bandwidth of, for example, 50 MHz. The amplified voltage signal is supplied to the input of the high-frequency amplifier 402 as the amplifier output signal 406. The ADC 403 samples the amplifier output signal 406 of the high-frequency amplifier 402. The ADC 403 transmits, for example, the calculated sample value of the amplifier output signal 406 of the high frequency amplifier 402 to the built-in FPGA 404 of the measurement board as a digital value with a bit width of, for example, 14 bits.

[0078] The device, shown in simplified block circuit diagram form in FIG. 6, includes a comparator 404.2, a time to digital converter (TDC) 404.3, an entropy extractor 404.4, and a state machine 404.8.

[0079] The comparator 404.2 compares the 14-bit digital value 407 of the ADC 403 with a reference value 404.1, which is a threshold value. If the output value of the ADC 403 is greater than the reference value 404.1, a 1-bit output pulse with a duration of 2 clock cycles is generated as the output signal 409 of the comparator 404.2. The output signal 409 of the comparator 404.2 is supplied to a time-to-digital converter 404.3. The time-to-digital converter 404.3 preferably has a 32-bit counter that increases in accordance with the SPAD evaluation circuit. The bit width of the counter can vary depending on the application. This clock may have a frequency of, for example, 125 MHz. The 1-bit output signal of the comparator 404.2 preferably resets the measurement value of the counter. The time-to-digital converter 404.3 transmits the current measurement value, i.e., the measurement value immediately before the reset, to its output 410. The count result has a resolution of 1 / 125 MHz = 8 nanoseconds, for example, at a 125 MHz clock. The output 410 of the time-to-digital converter (TDC) 404.3 conveys the count result (also called raw data RD), e.g., 32 bits, of the time-to-digital converter 404.3 to the entropy extractor 404.4. The entropy extractor 404.4 converts the raw data RD of the signal at the output 410 of the time-to-digital converter (TDC) 404.3, which is random in its composition and order, into a 1-bit random number RN411 at the output of the entropy extractor 404.4. The output 411 of the entropy extractor 404.4 is connected to the input of the finite state machine (FSM) 404.8.

[0080] FSM 404.8 is responsible for receiving data from entropy extractor 404.4 and generating a QRNG random number therefrom. FSM 404.8 stores this QRNG random number in memory RAM 404.9 of FPGA 404. If the write operation is successful, FSM 404.8 sets finish flag 404.10. Finish flag 404.10 is not set at system startup. Microcontroller 404.11, e.g., a Dual-Core Arm Cortex-A9 MPCore, accesses blocks in RAM 404.9 and reads random numbers from RAM 404.9. Thus, microcontroller 404.11 is, e.g., a microcontroller core according to the present invention.

[0081] FIG. 7 shows an example of an extended FPGA design with the capability to monitor the signal used for the random number RN at the output 411 of the entropy extractor 404.4 and an additional backup system in case of potential errors during the generation of the random number based on the QRNG.

[0082] The device according to Fig. 7 is extended with respect to an additional watchdog 404.5, a linear feedback shift register 404.6, which is an example of a PRN generator, a signal multiplexer 404.7 and a voltage motor 413. The microcontroller 404.11 together with these components can also be provided externally.

[0083] Here, the output 411 of the entropy extractor 404.4 is connected to a watchdog 404.5 and a signal multiplexer 404.7. The watchdog 404.5 monitors the validity of the 1-bit random number RN at the output 411 of the entropy extractor 404.4. The watchdog 404.5 detects at least three specified error cases. To do so, the watchdog 404.5 provides, for example, the last valid random number as a seed S output signal 412 to the linear feedback shift register 404.6. When an error occurs, the watchdog sets an error bit in an error register ER (not shown) of the microcontroller 404.11. The error bit that the watchdog 404.5 sets in the error register of the microcontroller 404.11 preferably depends on the type of error case. The watchdog 404.5 is also connected to a voltage monitor 413 via one or more input / output signal lines 414, which are preferably digital.

[0084] Voltage monitor 413 monitors, for example, the operating voltage of entropy source 401. If the operating voltage of one of the circuits of SPAD diodes 401.1 and 401.3 becomes too low, falling below a lower SPAD operating voltage threshold, or too high, exceeding an upper SPAD operating voltage threshold, voltage monitor 413 detects this voltage deviation. If such a voltage deviation occurs, voltage monitor 413 communicates this to watchdog 404.5 or directly to microcontroller 404.11. If communicating to watchdog 404.5, watchdog 404.5 can generate an interrupt signal for microcontroller 404.11, for example. For example, watchdog 404.5 can generate such an interrupt to microcontroller 404.11 or another subsystem of the application system if there is an error in the supply voltage of entropy source 401, high frequency amplifier 402, or another device portion of quantum random number generator QRNG 400.

[0085] If watchdog 404.5 detects an error, quantum random number generator 400 switches to a fail-safe state such that watchdog 404.5 sets select signal 416 of signal multiplexer 404.7, which in turn provides the pseudorandom number PRN generated by linear feedback shift register 404.6, in the form of a stream of pseudorandom bits, to the input of FSM 404.8 via pseudorandom signal line 417, instead of the output 411 of entropy extractor 404.4, as a replacement for the potentially erroneous 1-bit random number RN at output 411 of entropy extractor 404.4.

[0086] The linear feedback shift register 404.6 is connected to the output 412 of the watchdog 404.5 and receives the seed S output signal 412 from the watchdog 404.5. The watchdog 404.5 activates the linear feedback shift register 404.6 (see connection 418) in the event of an error. The linear feedback shift register 404.6 then generates the pseudorandom number PRN. The seed S of the watchdog output signal 412 preferably includes, for example, 16 immediately preceding valid random numbers (e.g., 1 bit each). The watchdog 404.5 preferably provides these immediately preceding valid random numbers to the input of the linear feedback shift register 404.6. Thus, to generate the pseudorandom number PRN for the pseudorandom number signal line 417, the seed S serves as a random and secure PQC starting value for the generator polynomial of the feedback of the linear feedback shift register 404.6. In this case, the generator polynomial and the degree of the generator polynomial are preferably freely selectable.

[0087] The signal at the output 411 of the entropy extractor 404.4, which contains the 1-bit random number RN of the entropy extractor 404.4, and the signal at the pseudorandom number signal line 417, which contains the pseudorandom number PRN of the linear feedback shift register 404.6, are each connected to an input of a signal multiplexer 404.7. The signal multiplexer 404.7 routes one of its two input signals to the FSM 404.8 depending on the value of the selection signal SEL 416. In some applications, multiplexers with more than two inputs and more complex control signals may be used. Therefore, the number of inputs to the signal multiplexer 404.7 is typically two or more.

[0088] FSM 404.8 also receives random data RN or pseudo-random numbers PRN from the output of signal multiplexer 404.7 and writes them to memory RAM 404.9 of FPGA 404. If the write operation is successful, FSM 404.8 again sets finish flag 404.10. Microcontroller 404.11 can then access memory 404.9 RAM to read the random numbers and use them for, for example, encryption, authentication, signing, etc.

[0089] FIG. 8 shows a flow diagram 500 of an entropy extraction method, such as may be performed by the entropy extractor 404.4 of the QRNG 400 of FIGS. 6 and 7. In this method, in a first step 501, two values ​​of the output 410 of the time-to-digital converter 404.3 are determined and stored in the shift register of the entropy extractor 404.4. Once the two values ​​are stored in the shift register of the entropy extractor 404.4, in a second step 502, the entropy extractor 404.4 compares the two values. Thus, the two values ​​in the shift register of the entropy extractor 404.4 comprise a first value and a second value, both determined by the time-to-digital converter 404 using two different measurements of the respective times between two signal pulses exceeding the reference value 404.1. In a third step 503, the entropy extractor 404.4 determines the two values. If the first value is less than the second value and the difference between Value 1 and Value 2 is greater than the minimum difference ε, entropy extractor 404.4 sets the value of its output 411 to a first logical value. If the first value is greater than the second value and the difference between the first and second values ​​is greater than the minimum difference ε, entropy extractor 404.4 sets its output to a second logical value different from the first logical value.

[0090] If the difference between the first and second values ​​is less than the minimum difference ε, the entropy extraction discards the first and second values. In such a case, the entropy extraction method preferably causes the watchdog (in the device of FIG. 7) to increment the error counter by a first error counter increment. The first error counter increment may be negative. Conversely, if the difference between the first and second values ​​is greater than the minimum difference ε, the entropy extraction device 404.4 may decrement the watchdog's error counter by a second error counter increment. The second error counter increment may be equal to the first error counter increment. Typically, the first and second error counter increments have the same sign. The microcontroller 404.11 is preferably capable of setting the error counter increment, the error counter start value, and the error counter threshold. If the error counter exceeds the error counter threshold, the watchdog 404.5 preferably signals the microcontroller 404.11 by interrupt or other signaling, indicating the existence of a critical error condition. The microcontroller 404.11 then typically initiates a self-test program to test various parts of the quantum random number generator 400 according to FIG. 7. To this end, the microcontroller preferably places the analog-to-digital converter 403 in a state that allows the microcontroller 404.11 to write a test value to the analog-to-digital converter's output register, and the subsequent signal chain preferably processes this test value as if it were a true sample value. Since the test value is known, the correct reaction of the remaining system, e.g., the increment of the error counter in the watchdog 404.5, can be monitored and determined by the microcontroller 404.11. Therefore, the microcontroller 404.11 preferably monitors and reads the logic state of every possible memory node of the FPGA 404.

[0091] If a value is less than the minimum value, which is within the dead time of the SPAD diode, it is preferable to discard such a value and increment the error counter by the first error increment. The entropy extractor 404.4 then waits for the next value to be calculated by the time-to-digital converter 404.3.

[0092] Once the random bits have been so extracted, the method starts over.

[0093] If the error counter exceeds or reaches the error counter threshold, an error may have occurred, for example, a time-to-digital converter providing a constant value.

[0094] Thus, the device can detect malfunctions in the voltage supply of the entropy source or other parts of the device. For testing purposes, microcontroller 404.11 can also monitor ADC 403, record the voltage and current across quantum random number generator 400, and compare the values ​​thus determined with expected ranges within which these values ​​should fall. Microcontroller 404.11 can also record the digital values ​​within quantum random number generator 400. For example, for testing purposes, microcontroller 404.11 can set reference value 404.1 low enough that time-to-digital converter 404.3 is substantially controlled by signal noise at its input. The value of time-to-digital converter 404.3 should then meet the expected statistical values ​​within the tolerance band. If not, an error exists.

[0095] The watchdog 404.5 can monitor the entropy of the random numbers provided. If the average entropy of the bits deviates by more than a tolerable entropy deviation, e.g., 50%, over the entropy measurement time, the watchdog determines an error and increments an error counter. The watchdog then preferably disables the use of random bits at the output 411 of the entropy extractor 404.4 to prevent the transmission of plaintext. "Plaintext" refers to information that is poorly encrypted and therefore can be understood by a third party through statistical methods or directly. In other words, even in a working subsystem, it is conceivable that a logical "forever 1" or a logical "forever 0" may be accidentally generated. Therefore, it is useful to limit the maximum length of the bit string at the output of the entropy extractor to a value programmable by the microcontroller 404.11.

[0096] In this way, essentially, the quantum random number generator 400 described above can detect the following errors and catch them at a lower level of safety by fail-safe using a linear feedback shift register 404.6 or another PRN generator: - Abnormal supply voltage SPAD diodes 401.1 and 401.3 generate false signals A malfunction in optical fiber 401.2 and / or a malfunction in the connection of SPAD diodes 401.1 and 401.3 to optical fiber 401.2 Circuit failure in the FPGA 404, i.e., the digital component of the quantum random number generator 400 The false entropy of a random number supply that can be produced by testing a 1-bit random number RN, as described, for example, in David Johnston, “Random Number Generators - Principles and Practices”, Chapters 8 and 9, 2018, Walter De Gruyter GmbH, Berlin / Boston, ISBN 978-1-5015-1530-2.

[0097] It is conceivable to employ a second complete quantum random number generator 400 in place of the linear feedback shift register 404.6 and use the signal at the output of its entropy extractor 404.4 as a fail-safe instead of the signal on the pseudorandom signal line 417.

[0098] FIG. 9 shows an example of an oscillogram of the voltage signal 405 at the output of the entropy source 401. As can be seen from the figure, a first spike having a first height class 601 and a second spike having a second height class 602 are generated. Since the variance of the first height class 601 of the first spike and the variance of the second height class 602 of the second spike are small, the two height classes 601 and 602 can be clearly separated by the cut level 603. The cut level 603 corresponds to the value set by the microcontroller 404.11 as the reference value 404.1. For the occurrence of a spike (second spike) caused by the simultaneous occurrence of spontaneous and stimulated photon emission from the second SPAD diode or one of the plurality of second SPAD diodes and a spike (first spike) caused only by spontaneous photon emission from the second SPAD diode or one of the plurality of second SPAD diodes, please refer to the description of the test above.

[0099] 10 is a schematic diagram of a proposed quantum random number generation method 3700. The method 3700 begins at step 3710 with generating a random single-photon current (47, 48, 49, 401.2) using one or more first SPAD diodes (401.1, 44). The method 3700 continues at step 3720 with transmitting the random single-photon current (47, 48, 49, 401.2) to one or more second SPAD diodes (401.3, 45) using optical fibers (44, 401.2) that are different from the semiconductor substrates (49, 48). Next, a step 3730 is performed of converting the random single-photon current (47, 48, 49, 401.2) into a detection signal, preferably in the form of a voltage signal 405 of an entropy source 401 comprising a first SPAD diode 401.1, an optical fiber 401.2, and a second SPAD diode 401.3. Then, a step 3740 is performed of conditioning, in particular amplifying, filtering, and / or analog-to-digital converting, the detection signal into a conditioned detection signal, in particular a 14-bit digital value 407 in an analog-to-digital converter 403. Thereafter, a step 3750 is performed of separating conditioned detection signal pulses resulting from the combined emissions of the first SPAD diode 401.1 and the second SPAD diode 401.3 from conditioned detection signal pulses resulting from spontaneous emission alone, in particular by comparing the conditioned detection signal with a threshold value in a comparator (see 404.2 in FIGS. 6 and 7) and generating a corresponding output signal 409 of the comparator 404.2. This is followed by step 3760 of calculating a first time interval between a first pulse and a second pulse of a first pair of two consecutive photons generated by the spontaneous photon emission of the first SPAD diode 401.1 combining with the stimulated photon emission of the second SPAD diode 401.3, and calculating a second time interval between a third pulse and a fourth pulse of a second pair of two consecutive adjusted detection signal pulses generated by the combination of the same type of emissions of the first SPAD diode 401.1 and the second SPAD diode 401.3, in order to calculate, in particular, a first value of the output 410 of the time-to-digital converter 404.3 and a second value of the output 410 of the time-to-digital converter 404.3.Then, based on this, step 3670 is performed to calculate the bit value of the random bit by comparing the value of the first time interval with the value of the second time interval. In the final step 3680, it is verified whether the calculated number of random bits n is smaller than the number of random bits m of the desired quantum random number. If not, the above steps are repeated. Otherwise, the quantum random number generation process is completed.

[0100] <Advantages> The secure microcontroller disclosed herein has improved entropy in at least one random number generator thereof, which makes encryption obtained using the microcontroller more efficient and quantum-safe compared to background art, although the advantages of the present invention are not limited thereto.

[0101] The above description is not intended to be complete and is not limited to the examples shown. Various modifications of the examples described herein can be understood and implemented by those skilled in the art using the drawings, the description, and the claims. The singular indefinite article "ein" or "eine" and its conjugations do not exclude a plurality, and the recitation of a specific number of elements does not exclude the possibility that more or fewer elements may be present. A single unit may fulfill the function of multiple elements described herein, and conversely, multiple elements may fulfill the function of one unit. Many alternatives, equivalents, modifications, and combinations are possible without departing from the scope of the present application.

[0102] Unless otherwise specified, all features of the present invention can be freely combined. This applies throughout the present application. Features shown in the drawings can also be freely combined with other features as features of the present invention unless otherwise specified. In this regard, it is not explicitly intended to limit the combination of individual features of the embodiments with other features of the embodiments. Furthermore, material features of an apparatus can be read as method features, and method features can be read as material features of an apparatus. Therefore, such readings are automatically considered to be disclosed.

[0103] In the above detailed description, reference is made to the accompanying drawings. The examples in the specification and drawings are merely examples and are not limited to the specific examples or elements described. By changing, combining, or modifying some elements, various examples can be derived from the above specification, drawings, and / or claims. Furthermore, a person skilled in the art can derive examples or elements not literally described from the specification and / or drawings.

[0104] The present invention has been described above using a microcontroller for an automobile. However, based on this disclosure, it will be apparent to those skilled in the art that its application is not limited to either the patent application from which priority is derived or this international application. Rather, the microcontroller of the present invention can be employed in any device involved in PQC secure encryption and / or PQR signature of data, as well as editing and processing of data for security reasons. PQR encryption can preferably be achieved by one of the following methods:

[0105] BIKE1-L1-CPA, BIKE1-L3-CPA, BIKE1-L1-FO, BIKE1-L3-FO, Kyber512, Kyber768, Kyber1024, Kyber512-90s, K yber768-90s, Kyber1024-90s, LEDAcryptKEM-LT12, LEDAcrypt-KEM-LT32, LEDAcryptKEM-LT52, NewHope-512- CCA, NewHope-1024-CCA, NTRU-HPS-2048-509, NTRU-HPS-2048-677, NTRU-HPS-4096-821, NTRU-HRSS-701, Lig htSaber-KEM, Saber-KEM, FireSaber-KEM, BabyBear, BabyBearEphem, MamaBear, MamaBearEphem, PapaBear, Pa paBearEphem, FrodoKEM-640-AES, FrodoKEM-640-SHAKE, FrodoKEM-976-AES, FrodoKEM-976-SHAKE, FrodoKEM -1344-AES, FrodoKEM-1344-SHAKE, SIDH-p434, SIDH-p503, SIDH-p610, SIDH-p751, SIDH-p434-compressed, SI DH-p503-compressed, SIDH-p610-compressed, SIDH-p751-compressed, SIKE-p434, SIKE-p503, SIKE-p610', SIKE-p751, SIKE-p434-compressed, SIKE-p503-compressed, SIKE-p610-compressed, SIKE-p751-compressed.

[0106] The PQR signature can preferably be realized by one of the following methods.

[0107] DILITHIUM_2、DILITHIUM_3、DILITHIUM_4、MQDSS-31-48、MQDSS-31-64、SPHINCS+-Haraka-128f-robust、SPHINCS+-Haraka-128f-simple、SPHINCS+-Haraka-128s-robust、SPHINCS+-Haraka-128s-simple、SPHINCS+-Haraka-192f-robust、SPHINCS+-Haraka-192f-simple、SPHINCS+-Haraka-192s-robust、SPHINCS+-Haraka-192s-simple、SPHINCS+-Haraka-256f-robust、SPHINCS+-Haraka-256f-simple、SPHINCS+-Haraka-256s-robust、SPHINCS+-Haraka-256s-simple、SPHINCS+-SHA256-128f-robust、SPHINCS+-SHA256-128f-simple、SPHINCS+-SHA256-128s-robust、SPHINCS+-SHA256-128s-simple、SPHINCS+-SHA256-192f-robust、SPHINCS+-SHA256-192f-simple、SPHINCS+-SHA256-192s-robust、SPHINCS+-SHA256-192s-simple、SPHINCS+-SHA256-256f-robust、SPHINCS+-SHA256-256f-simple、SPHINCS+-SHA256-256s-robust、SPHINCS+-SHA256-256s-simple、SPHINCS+-SHAKE256-128f-robust、SPHINCS+-SHAKE256-128f-simple、SPHINCS+-SHAKE256-128s-robust、SPHINCS+-SHAKE256-128s-simple、SPHINCS+-SHAKE256-192f-robust、SPHINCS+-SHAKE256-192f-simple、SPHINCS+-SHAKE256-192s-robust、SPHINCS+-SHAKE256-192s-simple、SPHINCS+-SHAKE256-256f-robust, SPHINCS+-SHAKE256-256f-simple, SPHINCS+-SHAKE256-256s-robust, SPHINCS+-SHAKE256-256s-simple, picnic_L1_F S,picnic_L1_UR,picnic_L3_FS,picnic_L3_UR,picnic_L5_FS,picnic_L5_UR,picnic2_L1_FS,picnic2_L3_FS,picnic2_L5_FS,qTesla-pI,qTesla-p-III. ,

[0108] For example, the concepts of the present invention can be used to generate addresses in communication bus systems where devices are automatically addressed by the bus master, either within the bus master or within each addressed device. Thus, the present invention can be used beyond cryptography to generate PQC secure codes. PQC stands for "post-quantum cryptography," a subfield of cryptography, specifically quantum-safe cryptography, which, unlike many currently used asymmetric cryptosystems, deals with cryptographic primitives that are nearly impossible to decode even using quantum computers (see Wikipedia definition). Different codes can also be used to better distinguish signals transmitted from essentially any designed system, separating them from each other and from adjacent systems that may interfere with them technically. For example, when designing ultrasonic measurement devices for the automotive field, it can be useful to be able to distinguish individual received signals based on their origin, i.e., the source that emitted the signal.

[0109] <Features of the invention> The following list of inventions summarizes the features of the invention and their developments. In the application of technical doctrine, features can be combined unless this combination leads to a contradiction in fact. In this respect, the dependencies and reference numerals given here merely exemplify particularly preferred embodiments.

[0110] 1) A safety microcontroller 1 for controlling devices in a motor vehicle, a semiconductor substrate; A plurality of memory elements at least one internal bus 2; At least one 8 / 16 / 32 / 64-bit microcontroller core 16 and one or more data interfaces; at least one quantum process based generator 15; the storage element is connected to the internal bus 2; the data interface is connected to the internal bus 2; the quantum process-based generator 15 is connected to the internal bus 2; the microcontroller core 16 is connected to the internal bus 2; the quantum process based generator 15 generates random numbers in response to requests from the microcontroller core 16; the microcontroller core 16 generates a key using the program from one or more of the storage elements and the random number; the microcontroller core 16 uses the program from one or more of the storage elements and the key to encrypt and decrypt data transmitted to and from devices external to the secure microcontroller via the data interface; the semiconductor substrate integrally includes the subsystems of the safety microcontroller 1; A secure microcontroller, wherein the sub-devices of the secure microcontroller 1 include the memory element, the internal bus 2, the at least one 8 / 16 / 32 / 64-bit microcontroller core 16, the data interface, and the quantum process-based generator 15.

[0111] 2) The safety microcontroller 1 according to item 1), wherein the storage elements comprise one or more read-write memories RAM3, one or more writable non-volatile memories (specifically, EEPROM memories 4, flash memories 4 and / or OTP memories 4), one or more pure read-only memories and / or one or more non-volatile manufacturer memories (specifically, one or more manufacturer ROMs 6, one or more manufacturer EEPROMs and / or one or more manufacturer flash memories).

[0112] 3) The safety microcontroller 1 according to item 2), wherein the manufacturer ROM 6 has boot software.

[0113] 4) The safety microcontroller 1 according to item 2) or 3), comprising a manufacturer memory firewall 8 between the manufacturer memory 6 and the internal bus 2.

[0114] 5) Basic clock generator 21 (CLK); clock generation circuit 12, reset circuit 22, a current supply or Vcc circuit with a voltage regulator to provide the operating voltage; ground circuit 24, Input / output circuit 25 and / or one or more components of one or more processing modules; the processing module communicates with the internal bus 2; The processing module: CRC module (Cyclic Redundancy Check) 11, a clock generation module 12; a module having a DES accelerator and / or an AES accelerator 7, one or more timer modules 13; safety monitoring control circuit 14, The safety microcontroller 1 according to one or more of items 1) to 4) has one or more modules of a data interface, in particular a Universal Asynchronous Receiver Transmitter (UART) 17.

[0115] 6) at least one first SPAD diode 44; and at least one second SPAD diode 45; at least one optical fiber 50; at least one processing circuit; at least one operating circuit; the quantum process-based generator 15 comprises at least the first SPAD diode 44 as a light source for a light quantum signal; the quantum process-based generator 15 comprises at least the second SPAD diode 45 as a photodetector for the optical quantum signal; said quantum process-based generator 15 having at least said processing circuitry; the quantum process-based generator 15 comprises at least the optical fiber; the at least one optical fiber 50 optically couples the at least one first SPAD diode 44 to the at least one second SPAD diode 45; the operating circuit provides electrical energy to the first SPAD diode 44 so that the first SPAD diode emits light 44; A safety microcontroller 1 described in one or more of items 1) to 5) wherein the processing circuit detects the signal of the second SPAD diode 45, forms a random number therefrom and supplies it to the microcontroller core 16.

[0116] 7) the semiconductor substrate has a surface 46; the semiconductor substrate having semiconductor material below the surface 46; the surface 46 of the semiconductor substrate having a metallization stack; the metallization stack typically having a structured, optically transparent, electrically insulating layer 34; At least a portion of the typically structured and transparent electrically insulating layer on the surface 46 constitutes the optical fiber 50; the first SPAD diode 44 radiates from the semiconductor material of the semiconductor substrate into the optical fiber 50; The safety microcontroller 1 described in item 6) wherein the optical fiber 50 illuminates the second SPAD diode 44 so that light from inside the optical fiber 50 re-enters the semiconductor material of the semiconductor substrate from the surface and there reaches the device portion of the second SPAD diode 44.

[0117] 8) the at least one operating circuit at least temporarily supplies electrical energy to the at least one first SPAD diode 44; the at least one first SPAD diode 44, when supplied with sufficient electrical energy, provides photons to the at least one optical fiber 50; The safety microcontroller 1 according to items 6) and / or 7), wherein the at least one optical fiber 50 emits such photons to the second SPAD diode 45.

[0118] 9) Among the one or more data interfaces, one data interface is a wired automotive data bus interface; The wired automotive data bus interface is particularly CAN data bus interface, CAN-FD data bus interface, FlexRay data bus interface, PSI5 data bus interface, DSI3 data bus interface, LIN data bus interface, Ethernet data bus interface, LIN data bus interface and / or Item 1. A safety microcontroller 1 according to one or more of the preceding items, having a MELIBUS data bus interface.

[0119] 10) Among the one or more data interfaces, one data interface is a wireless data bus interface; The wireless data bus interface is particularly WLAN interface and / or Item 1. A safety microcontroller 1 according to one or more of the preceding items, having a Bluetooth interface.

[0120] 11) Among the one or more data interfaces, one data interface is a wired data bus interface; The wireless data bus interface is particularly KNX data bus interface, EIB data bus interface, DALI® data bus interface and / or The safety microcontroller 1 according to one or more of the above items is a PROFIBUS data bus interface.

[0121] 12) An apparatus comprising: the device comprises an integrated circuit 4 having a first processor 10-1 and a non-volatile memory 16; the apparatus comprises a first memory; the non-volatile memory stores at least one security code; the first memory stores data; the data in the first memory is in a first format and cryptographically protected; the integrated circuit is configured to authenticate data read from the first memory during a transfer of the data from the first memory; the device comprises a quantum random number generator 28; the integrated circuit and the quantum random number generator 28 are fabricated in a semiconductor crystal; the semiconductor crystal has a surface 46; the semiconductor crystal has semiconductor material below the surface 46; the surface 46 of the semiconductor crystal has a metallization stack; the metallization stack typically having a structured, optically transparent, electrically insulating layer 34; At least a portion of the typically structured and transparent electrically insulating layer 34 on the surface 46 constitutes the optical fiber 50; the first SPAD diode 44 emits a photon 47 from the semiconductor material of the semiconductor substrate into the optical fiber 50; the at least one optical fiber 50 conveys such photons 48 to the second SPAD diode 45; the optical fiber 50 illuminates the second SPAD diode 45 such that the light 49 from within the optical fiber 50 re-enters the semiconductor material of the semiconductor substrate from the surface 46 and there reaches the device portion of the second SPAD diode 45; The apparatus, wherein the first SPAD diode (44), the second SPAD diode (45) and the optical fiber (50) are part of the quantum random number generator (28).

[0122] 13) The device comprises at least one operating circuit; the at least one operating circuit at least temporarily supplies electrical energy to the at least one first SPAD diode 44; the at least one first SPAD diode 44, when supplied with sufficient electrical energy, provides photons 47 to the at least one optical fiber 50; the at least one optical fiber 50 conveys such photons 48 to the second SPAD diode 45; The device according to item 12), wherein the at least one optical fiber 50 emits such photons 49 to a second SPAD diode 45.

[0123] 14) the quantum random number generator 28 has at least the first SPAD diode 44 as a light source for the photon signal; the quantum random number generator 28 has at least the second SPAD diode 45 as a photodetector for the photon signal; the quantum random number generator 28 has at least one processing circuit; the quantum random number generator 28 includes at least the optical fiber 50; the at least one optical fiber 50 optically couples the at least one first SPAD diode 44 to the at least one second SPAD diode 45; the operating circuit provides electrical energy to the first SPAD diode 44 so that the first SPAD diode emits light 44; Item 13) The apparatus according to item 13), wherein the processing circuit detects the signal of the second SPAD diode 45, forms a random number therefrom, and supplies it to the data processor 10 or another device part.

[0124] 15) The first memory is provided outside the integrated circuit; the apparatus comprises a second memory for storing data; the second memory is provided outside the integrated circuit; the apparatus is configured to transfer data from the first memory through the integrated circuit to the second memory, thereby allowing the data processor to access the data from the second memory; The integrated circuit, authenticating the data read from the first memory using a security code stored in the non-volatile memory during data transfer from the first memory to the second memory; if the data is authenticated, applying cryptographic protection in a second format to the authenticated data using a security code stored in the non-volatile memory; The device according to any one of items 12) to 14), configured to store the data protected in the second format in the second memory.

[0125] 16) An apparatus according to any one of items 12) to 15), wherein the first memory comprises a read-only memory.

[0126] 17) The device described in any one of items 15) and 16), wherein the second memory comprises a random access memory.

[0127] 18) An apparatus as described in any one of items 15) to 17), wherein the cryptographic protection applied to the data in the first memory is different from the cryptographic protection applied to the data in the second memory.

[0128] 19) The integrated circuit has a memory for storing data to be processed by the data processor; 19. The device according to any one of items 12) to 18), wherein the device is configured to store a portion of the authenticated data set in the memory and the remainder in the second memory.

[0129] 20) An apparatus described in any one of items 15) to 19), wherein the first memory is configured to store data in a first data format and the second memory is configured to store data in a different second data format.

[0130] 21) The data stored in the first memory is protected by a first authentication technique; The device according to item 20), wherein the device is configured to protect the data in the second memory by a different second authentication technique.

[0131] 22) The data in the first memory is stored in at least one data set, the or each data set being cryptographically protected as a set; 22. The apparatus of any one of items 15) to 21), wherein the apparatus is configured to store in the second memory words or groups of words of an authenticated data set, each word or group of words being separately cryptographically protected.

[0132] 23) The device is reading the word or group of words from the second memory; authenticating the read word or group of words using a security code stored in the nonvolatile memory; Item 22) The device according to item 22), configured to process the read and authenticated word or words in the data processor.

[0133] 24) The integrated circuit includes a hash computer; the data processor and the hash computer a) for each word or group of words, calculating a hash function in response to a security code stored in said non-volatile memory, and associating said hash with said word or group of words and storing said hash in said second memory; b) reading the stored word or group from said second memory, re-calculating a hash function for said read word or group of words using said security code, and comparing said re-calculated hash with said stored hash; c) The device according to item 23), arranged to cause the data processing facility to process the retrieved word or the retrieved words only if the recalculated hash and the stored hash are in a specific relationship.

[0134] 25) The apparatus according to item 24), wherein the hash computer is a circuit in the integrated circuit.

[0135] 26) The device described in any one of items 12) to 25), wherein the non-volatile memory of the integrated circuit is a one-time programmable memory.

[0136] 27) An apparatus according to any one of items 12) to 26), wherein the or each data set stored in the first memory is cryptographically protected by a corresponding digital signature.

[0137] 28) An apparatus described in any one of items 12) to 28), wherein the or each data set stored in the first memory is cryptographically protected by a corresponding digital signature using at least one random number of the quantum random number generator.

[0138] 29) The device described in item 27) or 28), wherein a security code generated by the device at least in part using at least one random number from the quantum random number generator (28) is stored in the non-volatile memory of the integrated circuit.

[0139] 30) An apparatus described in any one of items 27) to 29), wherein the apparatus is configured to authenticate the digital signature of the data set by referring to a security code stored in the non-volatile memory of the integrated circuit.

[0140] 31) A data processing device, the data processing device comprises an integrated circuit; the integrated circuit includes a data processor; the integrated circuit has a non-volatile memory; the non-volatile memory stores at least one security code; the integrated circuit includes a hash computer; the integrated circuit has an interface at a boundary of the integrated circuit; the integrated circuit includes a quantum random number generator; the integrated circuit and the quantum random number generator are fabricated in a semiconductor crystal; the semiconductor crystal has a surface 46; the semiconductor crystal having semiconductor material below the surface 46; the surface 46 of the semiconductor crystal has a metallization stack; the metallization stack typically having a structured, optically transparent, electrically insulating layer 34; At least a portion of the typically structured, transparent, electrically insulating layer 34 on the surface 36 constitutes the optical fiber 50; the first SPAD diode 44 emits a photon 47 from the semiconductor material of the semiconductor substrate into the optical fiber 50; the at least one optical fiber 50 conveys such photons 48 to the second SPAD diode 45; the optical fiber 50 illuminates the second SPAD diode 45 such that the light 49 from within the fiber 50 re-enters the semiconductor material of the semiconductor substrate at the surface 46, where it reaches the device portion of the second SPAD diode 45; A data processing device in which the first SPAD diode 44, the second SPAD diode 45 and the optical fiber 50 are part of the quantum random number generator 28.

[0141] 32) A data processing device according to item 31), wherein the data processor and / or another device part of the data processing device encrypts or decrypts data using at least one random number from the quantum random number generator.

[0142] 33) The data processing device comprises a memory; The memory stores data for use by the processor; 32) A data processing device according to item 31) or 32), wherein the memory is coupled to the data processor to receive words from the data processor and to provide words to the data processor.

[0143] 34) The memory is external to the integrated circuit; A data processing device described in any one of items 31) to 33), wherein the memory is connected to the data processor via the interface at the boundary of the integrated circuit, thereby receiving words from the data processor and supplying words to the data processor.

[0144] 35) The data processor and the hash computer are: a) for each word, computing a hash function in response to a security code stored in said non-volatile memory, and storing said hash in association with said word; b) reading the stored words from said memory, and for each read word, recalculating the hash function using said security code and comparing said recalculated hash value with said stored hash value; c) A data processing device according to any one of items 31) to 34), configured to cause the data processing facility to process the read word only if the recalculated hash and the stored hash have a predetermined relationship.

[0145] 36) An integrated circuit having data processing means and non-volatile memory means for storing at least one security code; a first means for storing data; a quantum random number generator 28 that is part of the integrated circuit, the data is cryptographically protected in a first format by at least one authentication code; the quantum random number generator comprises a first SPAD diode 44 and a second SPAD diode 45, the first SPAD diode 44 and the second SPAD diode 45 being coupled or connectable to each other via an optical fiber 50 fabricated on the surface of the integrated circuit outside the semiconductor substrate of the integrated circuit; The device uses at least one random number from the quantum random number generator 28 at least temporarily for encrypting or decrypting the date or the authentication code.

[0146] 37) The device comprises a second device for storing data, in particular external to the integrated circuit; the apparatus comprising means for transferring data from the first memory to the second memory via the integrated circuit, so that the data processor can access the data from the second memory; the apparatus comprising means for authenticating the data read from the first memory during transfer using a security code stored in the non-volatile memory; the apparatus comprising means for, when the data is authenticated, applying cryptographic protection having at least one authentication code to the authenticated data in a second format using a security code stored in the non-volatile memory; Item 36) The apparatus according to item 36), further comprising means for storing the protected data in the second memory in the second format.

[0147] 38) The device comprises a quantum random number generator 400; The quantum random number generator is, as a device part, a first SPAD diode 404.1; a second SPAD diode 404.3; an optical fiber 404.2 optically connecting the first SPAD diode 404.1 and the second SPAD diode 404.3; an amplifier 403 and / or a filter; an analog-to-digital converter 403; a comparator 404.2; a time-to-digital converter 404.3; An apparatus as described in any one of items 12) to 37), in particular having an entropy extraction device 404.4 for converting the output value of the time-to-digital converter 403 into a first and a second value and generating random bits therefrom.

[0148] 39) The apparatus described in item 27), wherein the apparatus comprises a watchdog 404.5 that monitors the apparatus portion of the quantum random number generator 400.

[0149] 40) An apparatus according to any one of items 38) and 39), wherein the apparatus comprises a voltage monitor 413 that detects and monitors the analog value of the analog signal.

[0150] 41) A device according to any one of items 38) to 40), wherein the device comprises a pseudorandom number generator 404.6, in particular in the form of a linear feedback shift register 404.6.

[0151] 42) An apparatus according to any one of items 38) to 41), wherein the apparatus comprises a signal multiplexer which, in an error case, switches from the signal of the output 411 of the entropy extraction apparatus to the signal of the preliminary random number generator or the preliminary pseudorandom number generator 404.6.

[0152] 43) An apparatus described in any one of items 38) to 42), in which in an error case the starting value of the pseudorandom number generator 404.6 depends on random bits of the quantum random number generator 400 that were correctly generated in the past.

[0153] 44) generating a pulse sequence having pulses of a first height class 601 and pulses of a second height class 602 at random intervals using at least two SPAD diodes; Separating pulses of said first height class 601 from pulses of said second height class 602 by means of a cutting level 603, 404.1; a step 501 of detecting a first value of a time interval between a first pulse of the second height class 602 and a second pulse of the second height class 602 different from the first pulse; Detecting 501 a second value of a time interval between a third pulse of the second height class 602 different from the first pulse and a fourth pulse of the second height class 602 different from the first pulse, the second pulse, and the third pulse; a step 502 of comparing the first value with the second value; a step 503 of outputting a first logic value as the random bit if the first value is greater than the second value; and if the first value is smaller than the second value, outputting as the random bit a second logical value different from the first logical value.

[0154] 45) A method 3700 for generating quantum random numbers QZ having m random bits, comprising: generating 3710 a random single-photon current 47, 48, 49, 401.2 from the single photons using one or more first SPAD diodes 401.1, 44; transmitting 3720 the random single-photon current 47, 48, 49, 401.2 to one or more second SPAD diodes 401.3, 45 using an optical fiber 50, 401.2 different from the semiconductor substrate 39, 38; converting 3730 the random single-photon current 47, 48, 49, 401.2 into a detection signal using the one or more second SPAD diodes 401.3, 45; adjusting 3740 the detection signal to an adjusted detection signal; a step 3750 of comparing the adjusted detection signal with a threshold 404.1 to separate pulses of the adjusted detection signal caused by a combination of an emission of a first SPAD diode 401.1 of the one or more first SPAD diodes 401.1,44 and an emission of a second SPAD diode 401.3,45 of the one or more second SPAD diodes 401.3,45 from pulses of the adjusted detection signal caused by spontaneous emission of the second SPAD diode 401.3,45; calculating 3760 a first time interval between a first pulse and a second pulse of a first pair of two consecutive pulses of the adjusted detection signal caused by the combined emissions of the first SPAD diode 401.1,44 and the second SPAD diode 401.3,45; and calculating 3760 a second time interval between a third pulse and a fourth pulse of a second pair of two consecutive pulses of the adjusted detection signal caused by the combined emissions of the first SPAD diode 401.1,44 and the second SPAD diode 401.3,45; calculating 3670 a bit value for a random bit by comparing the value of the first time interval with the value of the second time interval; A method 3700 comprising the steps of repeating steps 3710 to 3770 if the calculated number of random bits 3680n is smaller than the desired number m of random bits of the quantum random number QZ to be generated, and terminating the quantum random number generation process if the calculated number of random bits 3680n is greater than or equal to the desired number m of random bits of the quantum random number QZ to be generated.

[0155] 46) An integrated circuit having data processing means and non-volatile memory means for storing at least one security code; a first means for storing data; a quantum random number generator 28 that is part of the integrated circuit, the data is cryptographically protected in a first format by at least one authentication code; the quantum random number generator comprises a first SPAD diode 44 and a second SPAD diode 45, the first SPAD diode 44 and the second SPAD diode 45 being coupled or connectable to each other via an optical fiber 50 fabricated on the surface of the integrated circuit outside the semiconductor substrate of the integrated circuit; The device uses at least one random number from the quantum random number generator 28 at least temporarily for encrypting or decrypting the date or the authentication code.

[0156] 47) The device comprises a second device for storing data, in particular external to the integrated circuit; the apparatus comprising means for transferring data from the first memory to the second memory via the integrated circuit, so that the data processor can access the data from the second memory; the apparatus comprising means for authenticating the data read from the first memory during transfer using a security code stored in the non-volatile memory; the apparatus comprising means for, when the data is authenticated, applying cryptographic protection having at least one authentication code to the authenticated data in a second format using a security code stored in the non-volatile memory; Item 46) The apparatus according to item 46), further comprising means for storing the protected data in the second memory in the second format.

[0157] 48) The device comprises a quantum random number generator 400; The quantum random number generator is, as a device part, a first SPAD diode 404.1; a second SPAD diode 404.3; and an optical fiber 404.2 optically connecting the first SPAD diode 404.1 and the second SPAD diode 404.3; an amplifier 403 and / or a filter; an analog-to-digital converter 403; a comparator 404.2; a time-to-digital converter 404.3; The apparatus according to item 46) or 47), further comprising an entropy extraction device 404.4 for converting the output value of the time-to-digital converter 403 into a first and second value, from which random bits for the random number are generated.

[0158] 49) The apparatus described in item 48), wherein the apparatus comprises a watchdog 404.5 that monitors the apparatus portion of the quantum random number generator 400.

[0159] 50) The device according to items 48) and 49), wherein the device comprises a voltage monitor 413 that detects and monitors the analog value of the analog signal.

[0160] 51) A device according to any one of items 48) to 50), wherein the device comprises a random or pseudo-random number generator 404.6, in particular in the form of a linear feedback shift register 404.6.

[0161] 52) An apparatus described in any one of items 48) to 51), wherein the apparatus comprises a signal multiplexer which, in an error case, switches from the signal of the output 411 of the entropy extraction apparatus to the signal of the preliminary random number generator or the preliminary pseudorandom number generator 404.6.

[0162] 53) An apparatus described in any one of items 48) to 52), in which in an error case the starting value of the pseudorandom number generator 404.6 depends on random bits of the quantum random number generator 400 that were correctly generated in the past.

[0163] 54) generating a pulse sequence having pulses of a first height class 601 and pulses of a second height class 602 at random intervals using at least two SPAD diodes; separating pulses of said first height class 601 from pulses of said second height class 602 by means of a cutting level 603, 404.1; a step 501 of detecting a first value of a time interval between a first pulse of the second height class 602 and a second pulse of the second height class 602 different from the first pulse; Detecting 501 a second value of a time interval between a third pulse of the second height class 602 different from the first pulse and a fourth pulse of the second height class 602 different from the first pulse, the second pulse, and the third pulse; a step 502 of comparing the first value with the second value; a step 503 of outputting a first logic value as the random bit if the first value is greater than the second value; and if the first value is smaller than the second value, outputting as the random bit a second logical value different from the first logical value.

[0164] 55) A method 3700 for generating quantum random numbers QZ having m random bits, comprising: generating 3710 a random single-photon current 47, 48, 49, 401.2 from the single photons using one or more first SPAD diodes 401.1, 54; transmitting 3720 the random single-photon current 47, 48, 49, 401.2 to one or more second SPAD diodes 401.3, 45 using an optical fiber 50, 401.2; converting 3730 the random single-photon current 47, 48, 49, 401.2 into a detection signal using the one or more second SPAD diodes 401.3, 45; adjusting 3740 the detection signal to an adjusted detection signal; a step 3750 of comparing the adjusted detection signal with a threshold 404.1 to separate pulses of the adjusted detection signal caused by a combination of an emission of a first SPAD diode 401.1 of the one or more first SPAD diodes 401.1,44 and an emission of a second SPAD diode 401.3,45 of the one or more second SPAD diodes 401.3,45 from pulses of the adjusted detection signal caused by spontaneous emission of the second SPAD diode 401.3,45; calculating 3760 a first time interval between a first pulse and a second pulse of a first pair of two consecutive pulses of the adjusted detection signal caused by the combined emissions of the first SPAD diode 401.1,44 and the second SPAD diode 401.3,45; and calculating 3760 a second time interval between a third pulse and a fourth pulse of a second pair of two consecutive pulses of the adjusted detection signal caused by the combined emissions of the first SPAD diode 401.1,44 and the second SPAD diode 401.3,45; calculating 3670 a bit value for a random bit by comparing the value of the first time interval with the value of the second time interval; A method 3700 comprising the steps of repeating steps 3710 to 3770 if the calculated number of random bits 3680n is smaller than the desired number m of random bits of the quantum random number QZ to be generated, and terminating the quantum random number generation process if the calculated number of random bits 3680n is greater than or equal to the desired number m of random bits of the quantum random number QZ to be generated.

[0165] 56) A quantum random number QZ generator One or more first SPAD diodes 401.1, 44 that generate (3710) random single-photon currents 47, 48, 49, 401.2 based on photon processes from single photons; one or more second SPAD diodes 401.3,45; an optical fiber 50, 401.2 distinct from the semiconductor substrate 39, 38, the optical fiber 50, 401.2 transmitting (3720) the random single-photon current 47, 48, 49, 401.2 to the one or more second SPAD diodes 401.3, 45; the one or more second SPAD diodes 401.3, 45 convert (3730) the random single-photon currents 47, 48, 49, 401.2 into a detection signal; A signal processor, specifically an amplifier 402, conditions (3740) the detected signal into a conditioned detected signal; a comparator 404.02 or equivalent device compares the adjusted detection signal with a threshold 404.1 to separate (3750) pulses of the adjusted detection signal resulting from a combined emission of a first SPAD diode 401.1 of the one or more first SPAD diodes 401.1,44 and a second SPAD diode 401.3,45 of the one or more second SPAD diodes 401.3,45 from pulses of the adjusted detection signal resulting from spontaneous emission of the second SPAD diode 401.3,45; a time-to-digital converter 404.3 calculates (3760) a first time interval between a first pulse and a second pulse of a first pair of two consecutive pulses of the adjusted detection signal caused by the combined emissions of the first SPAD diode 401.1,44 and the second SPAD diode 401.3,45; and calculates a second time interval between a third pulse and a fourth pulse of a second pair of two consecutive pulses of the adjusted detection signal caused by the combined emissions of the first SPAD diode 401.1,44 and the second SPAD diode 401.3,45; an entropy extractor 404.4 calculates (3670) a bit value for the random bit by comparing the value of the first time interval with the value of the second time interval; An apparatus in which a finite automaton 404.8 generates quantum random numbers QZ417 from the bit data stream of the random bits 411. [Explanation of symbols]

[0166] 1 Safety Microcontroller 2. One or more internal data buses 3. One or more read-write RAMs 4. One or more writable non-volatile memories, which may include, for example, EEPROM memory, flash memory, or OTP memory. 5 One or more pure read-only non-volatile memories such as ROM 6. One or more writable and / or non-writable non-volatile manufacturer memories. In the case of non-writable manufacturer memories, this manufacturer memory may be, for example, a manufacturer ROM. 7 One or more cryptographic accelerators, such as a DES accelerator and / or an AES accelerator 8 One or more manufacturer memory firewalls 11 One or more CRC modules (Cyclic Redundancy Check) 12 One or more clock generation modules (English: Clock Driver, CLK) 13 Timer Module 14 One or more safety monitoring control circuits 15 Generators based on quantum processes 16 microcontroller cores 17 Data interface, specifically one or more Universal Asynchronous Receiver Transmitters (UARTs) to support continuous high-speed data 21 One or more basic clock generators (CLK) 22 One or more reset circuits 23 One or more current supplies or Vcc circuits with voltage regulators to provide the operating voltage for the safety microcontroller 24 One or more ground circuits 25 One or more input / output circuits 30 Typical SPAD diode used as the sensor element in a single-photon detector 31 Typical SPAD diode shallow trench isolation STI 32 Anode contact of a typical SPAD diode 33 Cathode contact of a typical SPAD diode. The cathode contact of a typical SPAD diode is preferably made from indium tin oxide (ITO) or another transparent conductive material. 34 Insulating layer 34' Insulation layer 34” insulation layer 35 A highly doped first junction region of a first conductivity type. In CMOS technology using p-doped wafer material, for example, n-doped in the semiconductor substrate material of the SPAD diode. + It can be a doped region 36 a first doped well of second conductivity type. In CMOS technology using p-doped wafer material, for example, a lightly doped region in the semiconductor substrate material of the SPAD diode 1820, i.e., p -- It can be a doped region 37 A second doped well of a second conductivity type. In CMOS technology using p-doped wafer material, for example, a lightly doped region in the semiconductor substrate material of the SPAD diode, i.e., p - It can be a doped region 38 Epitaxial layer of second conductivity type. In CMOS technology using p-doped wafer material, this can be, for example, a p-doped epitaxial layer in the semiconductor substrate material of the SPAD diode. 39 A substrate of a monocrystalline semiconductor wafer having a second conductivity type. In CMOS technology using p-doped wafer material, this may be, for example, a p-doped monocrystalline semiconductor wafer. 40 a second doped well of a second conductivity type below the anode contact. In CMOS technology using p-doped wafer material, for example, a p-doped well in the semiconductor substrate material of the SPAD diode. - It can be a doped region 41 a highly doped second junction region of a second conductivity type. In CMOS technology using p-doped wafer material, for example, a p-doped second junction region of the semiconductor substrate material of the SPAD diode 1820. + It can be a doped region 42 Insulators such as oxides 43 Metallic cover for optical fiber 44 a first SPAD diode, which serves, at least temporarily, as a light source for irradiating a second SPAD diode with photons from the first SPAD diode; 45 Second SPAD diode. The second SPAD diode functions, for example, at least temporarily, as a photodetector of the light from the first SPAD diode. 46 Surface of wafer in this application 47 The light of the first SPAD diode is emitted vertically and upwards, perpendicular to the surface. 48 A portion of the light emitted perpendicularly from the first SPAD diode into the optical fiber that is carried horizontally within the optical fiber 49 Light emitted from a first SPAD diode as vertical light into an optical fiber, and then horizontally conveyed from the optical fiber to a second SPAD diode, and the light of the first SPAD diode is emitted from the optical fiber to the second SPAD diode in a direction perpendicular to the surface, vertically downward. 50. An optical fiber for carrying photons from the first SPAD diode to the second SPAD diode. This optical fiber typically consists of a cladding oxide or other optically transparent insulating layer over the circuitry of a SPAD diode. 50' An optical fiber for carrying photons from the first SPAD diode to the second SPAD diode. This optical fiber may consist of a cladding oxide or other optically transparent insulating layer over the circuitry of a typical SPAD diode. Alternatively, it may consist of two stacked optically transparent insulating layers (e.g., a metallization stack). 51 Contacts 52 Contacts 53 Plane between two electrically insulating insulating layers of optical fiber 400 Quantum Random Number Generator QRNG 401 Entropy Source 401.1 One or more first SPAD diodes 401.2 Optical Fiber 401.3 One or more second SPAD diodes 402 High Frequency Amplifier 403 Analog-to-Digital Converter (ADC) 404 Measurement board with FPGA 404.1 Constants 404.2 Comparators 404.3 Time-to-digital converter 404.4 Entropy Extractor 404.4 404.5 Watchdog 404.6 Linear Feedback Shift Register. For generating pseudorandom bit sequences, the feedback is preferably a simple primitive polynomial. 404.7 Signal Multiplexer 404.8 Finite Automata 404.9 RAM 404.10 Finish Flag 404.11 Microcontroller 405 Voltage signal of entropy source 401 406 Amplifier output signal 406 of high frequency amplifier 402 407 Digital 14-bit value 407 from analog-to-digital converter 403. Other bit widths are possible. 408 Signal with constant 404.1 409 Output signal of comparator 404.2 409 410 Output of time-to-digital converter 404.3 411 Entropy Extraction 404.4 Output 412 Seed S 413 Voltage Monitor 414 Signal Line 416 Selection Signal 417 Pseudorandom Signal Line 418 Random Data Words 419 Internal data bus of quantum random number generator 400. Preferably internal data bus of control device 4. 420 Quantum Random Number Generator 400 Watchdog 404, 5 and Fuse 1 Controller 4 Interrupt Signal 500 Flowchart of Entropy Extraction Method 500 501 A first step 501 of calculating a first value of the output 410 of the time-to-digital converter 404.3 and a second value of the output 410 of the time-to-digital converter 404.3 and storing them in a shift register of the entropy extractor 404.4 502 a second step of comparing the first value with a second value 503 a third step of determining the first value and the second value and generating random bits; 601 First Spike 602 Second Spike 603 Cutting Level A method for generating quantum random numbers QZ with 3700 m random bits 3710 generating random single-photon currents (57, 58, 59, 401.2) using one or more first SPAD diodes (401.1, 54); 3720 transmitting the random single-photon current (57, 58, 59, 401.2) to one or more second SPAD diodes (401.3, 55) using an optical fiber (44, 401.2) different from the semiconductor substrate (49, 48). 3730 Converting from the random single-photon current (57, 58, 59, 401.2) to a detection signal in the form of a voltage signal 405 of an entropy source 401. The entropy source 401 preferably comprises a first SPAD diode 401.1, an optical fiber 401.2 and a second SPAD diode 401.3. 3740 conditioning, specifically amplifying, filtering and / or analog-to-digital converting, the detected signal into a conditioned detected signal, specifically a digital 14-bit value 407 in an analog-to-digital converter 403. 3750 separating pulses of the conditioned detection signal caused by the combined emissions of the first SPAD diode 401.1 and the second SPAD diode 401.3 from pulses of the conditioned detection signal caused by spontaneous emissions by comparing the conditioned detection signal with a threshold value, in particular in comparator 404.2, and generating a corresponding output signal 409 of comparator 404.2. 3760 calculating a first time interval between a first pulse and a second pulse of a first pair of two consecutive pulses of the adjusted detection signal generated by the combined emissions of the first SPAD diode 401.1 and the second SPAD diode 401.3 and calculating a second time interval between a third pulse and a fourth pulse of a second pair of two consecutive pulses of the adjusted detection signal generated by the combined emissions of the first SPAD diode 401.1 and the second SPAD diode 401.3, in particular to calculate a first value of the output 410 of the time-to-digital converter 404.3 and a second value of the output 410 of the time-to-digital converter 404.3. 3670 calculating a bit value of the random bit by comparing the value of the first time interval with the value of the second time interval. 3680. If the number n of random bits calculated up to this step is smaller than the desired number m of random bits of the desired quantum random number, repeat the above steps. Otherwise, end the process of generating quantum random numbers having m random bits.

Claims

1. A microcontroller (1) for controlling devices in a motor vehicle, comprising: a semiconductor substrate; a plurality of storage elements; At least one internal bus (2); at least a microcontroller core (16); one or more data interfaces; and at least one quantum process-based generator (15) for truly random numbers, The storage element is connected to the internal bus (2), The data interface is connected to the internal bus (2), The quantum process-based generator (15) is connected to the internal bus (2), The microcontroller core (16) is connected to the internal bus (2), The quantum process-based generator (15) generates random numbers in response to requests from the microcontroller core (16); The quantum process-based generator (15) supplies the random numbers; the microcontroller core (16) generates a key using the program from one or more of the storage elements and the random number; the microcontroller core (16) uses the program from one or more of the storage elements and the key to encrypt and decrypt data communicated internally or with external devices via the data interface; The semiconductor substrate integrally includes a sub-device of the microcontroller (1), the quantum process-based generator (15) has at least one first SPAD diode (44) as a light source for the optical quantum signal; the quantum process-based generator (15) has at least one second SPAD diode (45) as a photodetector for receiving the photon signal; the quantum process-based generator (15) has at least one processing circuit; the quantum process-based generator (15) has at least one optical fiber (50) for optically coupling the at least one first SPAD diode (44) to the at least one second SPAD diode (45); the quantum process-based generator (15) has an operating circuit for supplying electrical energy to the at least one first SPAD diode (44) for emitting light (47); the quantum process-based generator (15) has processing circuitry for detecting a signal of the at least one second SPAD diode (45), forming a random number from the signal of the at least one second SPAD diode (45), and providing the random number to the microcontroller core (16); the semiconductor substrate having a surface (46); the semiconductor substrate having semiconductor material below the surface (46); the surface (46) of the semiconductor substrate has a metallization stack; the metallization stack comprises an electrically insulating layer (34) disposed on the surface (46) of the semiconductor substrate, the electrically insulating layer (34) being structured and optically transparent; At least a portion of the transparent electrically insulating layer (34) constitutes the at least one optical fiber (50); the first SPAD diode (44) emits photons (47) from the semiconductor material of the semiconductor substrate into the optical fiber (50); The at least one optical fiber (50) conveys such photons (48) to the second SPAD diode (45).

2. The emission signal of the at least one second SPAD diode (45) has a first spike (601) and a second spike (602) greater than the first spike (601), the first and second spikes (601, 602) being greater than pre-determinable reference values ​​(404.1, 603), respectively, and the first spike (601) is generated by spontaneous photon emission of the at least one second SPAD diode (45) without simultaneous occurrence of stimulated photon emission of the at least one second SPAD diode (45), and the spontaneous photon emission and the at least 2. The microcontroller of claim 1, wherein the second spike (602) occurs due to a simultaneous occurrence of a photon emission of the at least one second SPAD diode (45) induced by receiving a photon of another first SPAD diode (44), and the processing circuit of the quantum process-based generator (15) generates a first logic value or a second logic value as a bit for generating the random number by comparing a time interval of the second spike (602) with a threshold value or by comparing time intervals of the second spikes (602) with each other.

3. 3. The microcontroller of claim 2, wherein the processing circuit generates the first logic value or the second logic value by comparing the time interval between two of the second spikes (602) with a threshold, and the processing circuit outputs the first logic value as a bit of the random number if the time interval is smaller than the threshold, and outputs the second logic value as a bit of the random number if the time interval is greater than the threshold.

4. 3. The microcontroller of claim 2, wherein the processing circuit generates the first logic value or the second logic value by comparing time intervals between the second spikes (602) of different pairs, and the processing circuit outputs the first logic value as a bit for generating the random number if the time interval between the last second spike (602) is smaller than the time interval between the second to last second spike (602) and the third to last second spike (602) or the time interval between another pair of preceding second spikes (602), and outputs the second logic value as a bit for generating the random number if the time interval between the last second spike (602) is larger than the time interval between the second to last second spike (602) and the third to last second spike (602) or the time interval between another pair of preceding second spikes (602).

5. 5. The microcontroller according to claim 2, further comprising a plurality of pairs of the first SPAD diode (44) and the second SPAD diode (45), wherein the emission signal of the second SPAD diode (45) can be supplied to the processing circuit, and the processing circuit uses the emission signal of each of the second SPAD diodes (45) to output another one of the bits for generating the random number.

6. 5. The microcontroller according to claim 2, further comprising a pair of the first SPAD diode (44) and the second SPAD diode (45), wherein the processing circuit continuously outputs the logic values ​​of the bits for generating the random number.

7. 5. The microcontroller of claim 2, further comprising a single first SPAD diode (44) and a plurality of second SPAD diodes (45) optically coupled to the single first SPAD diode (44), wherein the emission signal of the second SPAD diode (45) can be supplied to the processing circuit, and the processing circuit uses the emission signal of each of the second SPAD diodes (45) to output another one of the bits for generating the random number.

8. 5. The microcontroller according to claim 2, further comprising an error detection unit and a pseudo-random number generator, wherein if the error detection unit detects an error in the functioning of components involved in the photon process of the quantum process-based generator (15) or an error in the processing circuitry, the processing circuitry of the quantum process-based generator (15) switches from outputting bits for generating the random numbers using the emission signal of the at least one second SPAD diode (45) to outputting bits for generating pseudo-random numbers generated by the pseudo-random number generator.

9. 9. The microcontroller according to claim 8, wherein the error detection unit, upon detecting an error, outputs an error signal which indicates, inter alia, the type and / or cause of the error.

10. said storage element comprises one or more read-write memories RAM (3), one or more writable non-volatile memories, one or more pure read-only memories and / or one or more non-volatile manufacturer memories, the non-volatile memory is an EEPROM memory (4), a flash memory (4) and / or a one-time programmable (OTP) memory (4); 5. The microcontroller according to any one of claims 1 to 4, characterized in that the non-volatile manufacturer memories are one or more manufacturer ROMs (6), one or more manufacturer EEPROMs and / or one or more manufacturer flash memories.

11. Microcontroller according to claim 10, characterized in that the manufacturer ROM (6) contains boot software.

12. 11. The microcontroller of claim 10, further comprising a manufacturer memory firewall (8) between the manufacturer ROM (6) and the internal bus (2).

13. A basic clock generator (21) (CLK), a clock generation circuit (12); A reset circuit (22), a current supply or Vcc circuit (23) with a voltage regulator to provide the operating voltage; grounding circuit (24), Input / output circuitry (25) and / or one or more components of one or more processing modules; The processing module communicates with the internal bus (2); The processing module: CRC module (Cyclic Redundancy Check) (11), a clock generation module (12); a module comprising a DES accelerator and / or an AES accelerator (7), one or more timer modules (13), A safety monitoring control circuit (14) and 5. Microcontroller according to any one of claims 1 to 4, characterized in that it comprises one or more modules of the type Universal Asynchronous Receiver Transmitter (UART) (17).

14. 14. The microcontroller of claim 13, wherein the optical fiber (50) illuminates the second SPAD diode (45) such that light (49) re-enters the semiconductor material of the semiconductor substrate from within the optical fiber (50) and there reaches a device portion of the second SPAD diode (45).

15. the operating circuit at least temporarily supplies electrical energy to the at least one first SPAD diode (44); the at least one first SPAD diode (44), when supplied with sufficient electrical energy, provides photons (47) to the at least one optical fiber (50); the at least one optical fiber (50) conveys such photons (48) to the second SPAD diode (45); 5. The microcontroller of claim 1, wherein said at least one optical fiber (50) emits such photons (48) to said second SPAD diode (45).

16. 5. The microcontroller according to claim 1, wherein the data bus interface is a wired automotive data bus interface, or wherein one or more of the plurality of data bus interfaces are wired automotive data bus interfaces.

17. one or more of said wired automotive data bus interfaces; CAN data bus interface, CAN-FD data bus interface, FlexRay data bus interface, PSI5 data bus interface, DSI3 data bus interface, LIN data bus interface, Ethernet data bus interface, LIN data bus interface and / or 17. The microcontroller according to claim 16, characterized in that it is formed as a MELIBUS data bus interface.

18. 5. The microcontroller according to claim 1, wherein the data bus interface is a wireless data bus interface, or one or more of the plurality of data interfaces is a wireless data bus interface.

19. one or more of said wireless data bus interfaces; WLAN interface, Mobile communication interface and / or 19. The microcontroller according to claim 18, characterized in that it is formed as a Bluetooth interface.

20. 5. The microcontroller according to claim 1, wherein one data bus interface is a wired data bus interface, or one or more of the multiple data interfaces are wired data bus interfaces.

21. One or more of the wired data bus interfaces: KNX data bus interface, EIB data bus interface, DALI® data bus interface and / or 21. The microcontroller of claim 20, configured as a PROFIBUS data bus interface.

Images