Memory System

Abstract

To provide a memory system that reduces power consumption when a plurality of links are utilized.SOLUTION: A memory system includes a first controller 13-1, a second controller 13-2, and a third controller 14. The first controller sets a first link between a first host and the memory system to either an operating state or a low power consumption state. A second controller sets a second link between a second host and the memory system to either the operating state or the low power consumption state. The third controller sends a busy signal to the first controller and the second controller when a packet is expected to be transmitted over either the first link or the second link. If the first link is in the low power consumption state and no packet containing data to be transmitted to the third controller has been received over the first link, the first controller maintains the first link in the low power consumption state by disabling the busy signal.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to a memory system. [Background technology]

[0002] The PCI Express (PCIe) (registered trademark) standard is known as one of the interface standards for connecting an information processing device and a device. An interface conforming to the PCIe standard connects the information processing device and the device via a transmission path called a link. Data is transmitted over the link using packets. Data transmitted using packets includes, for example, a request from the information processing device to the device, a response from the device to the information processing device, or user data.

[0003] The PCIe standard defines a feature called Active State Power Management (ASPM) that allows the link to be set to a low-power state even while the device is in operation.

[0004] If there is no packet transmission over the link for a specific period of time, the device uses the ASPM function to transition the link from a normal operating state to a low power consumption state. In the PCIe standard, the normal operating state is defined as, for example, link power state L0. The low power consumption state is defined as, for example, link power state L1.

[0005] When a link returns from a low-power consumption state to a normal operating state, a delay of, for example, several microseconds (μs) occurs. This delay can degrade the performance of packet transmissions over the link. Therefore, when packet transmissions over the link are expected, the device controls to prevent the link from transitioning to a low-power consumption state.

[0006] A device may also have multiple PCIe interface ports. For example, a device with two ports can transmit packets to two information processing devices via two links. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] U.S. Patent No. 10,503,239 [Patent Document 2] U.S. Patent No. 10,503,239 [Patent Document 3] US Patent Application Publication No. 2006 / 0277344 [Patent Document 4] Japanese Patent Application Laid-Open No. 2013-118630 [Patent Document 5] U.S. Patent No. 7,539,883 Summary of the Invention [Problem to be solved by the invention]

[0008] One embodiment provides a memory system that can reduce power consumption when multiple links for packet transmission are utilized. [Means for solving the problem]

[0009] According to an embodiment, a memory system is connectable to each of multiple hosts via a serial interface. The memory system includes a nonvolatile memory, a first controller, a second controller, and a third controller. The first controller sets a first link between the first host and the memory system to either an operating state or a low-power state that consumes less power than the operating state. The second controller sets a second link between the second host and the memory system to either the operating state or the low-power state. The third controller processes requests to the nonvolatile memory using data contained in packets received via the first link and the second link. When the third controller expects transmission of a packet via either the first link or the second link, it sends a busy signal to the first controller and the second controller. When the first link is in the low-power state and a packet containing data to be transmitted to the third controller has not been received via the first link, the first controller maintains the first link in the low-power state by disabling the busy signal. When the first link is in an operating state and a packet containing data to be transmitted to the third controller is not received via the first link, the first controller transitions the first link to a low power consumption state in response to the absence of a packet being transmitted via the first link for a first period by disabling the busy signal. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. [Figure 2] FIG. 10 is a diagram showing an example of an operation in which a link with a host is maintained in a normal operating state (link power state L0) in a memory system according to a first comparative example. [Figure 3] FIG. 11 is a diagram showing an example of an operation in which links with two hosts are maintained in a normal operating state in a memory system according to a second comparative example. [Figure 4] FIG. 2 is a block diagram showing an example of a configuration for controlling a link power state in the memory system of the embodiment. [Figure 5] 10 is a diagram showing an example of an operation in which one link transitions from a low power consumption state to a normal operation state, while the other link is maintained in a low power consumption state (link power state L1) in the memory system of the embodiment. FIG. [Figure 6] 10 is a diagram showing an example of an operation in which one link is maintained in a normal operation state and the other link transitions from the normal operation state to a low power consumption state in the memory system of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described with reference to the drawings.

[0012] First, referring to FIG. 1, the configuration of an information processing system 1 including a memory system according to an embodiment will be described. The information processing system 1 includes a first host device 2-1, a second host device 2-2, and a memory system 3. Hereinafter, the first host device 2-1 will be referred to as the first host 2-1. The second host device 2-2 will be referred to as the second host 2-2. Furthermore, when there is no need to distinguish between the first host 2-1 and the second host 2-2, they will be referred to as the host 2. Note that the information processing system 1 may include three or more hosts 2.

[0013] Each of the first host 2-1 and the second host 2-2 may be a storage server that stores a large amount of diverse user data in the memory system 3, or may be a personal computer.

[0014] The memory system 3 is a semiconductor storage device configured to write user data to a nonvolatile memory such as a NAND flash memory and read the user data from the nonvolatile memory. The memory system 3 is also called a storage device. The memory system 3 is realized as, for example, a solid-state drive (SSD).

[0015] The memory system 3 can be used as storage for the first host 2-1 and the second host 2-2. The memory system 3 is connected to each of the first host 2-1 and the second host 2-2.

[0016] The interfaces for connecting the first host 2-1 and the second host 2-2 to the memory system 3 comply with standards such as PCI Express (PCIe) (registered trademark) and NVM Express (NVMe) (registered trademark).

[0017] The first host 2-1 includes a PCIe PHY 21-1. The second host 2-2 includes a PCIe PHY 21-2. The PCIe PHYs 21-1 and 21-2 are circuits corresponding to the physical layer defined by the PCIe standard. The PCIe PHYs 21-1 and 21-2 have a physical connection format that complies with the PCIe standard.

[0018] The memory system 3 includes, for example, a controller 4, a NAND flash memory 5, and a dynamic random access memory (DRAM) 6.

[0019] The NAND flash memory 5 includes one or more memory chips. Each memory chip includes multiple blocks. A block functions as the smallest unit of a data erase operation. A block is sometimes referred to as an "erase block" or a "physical block." Each of the multiple blocks includes multiple pages. Each of the multiple pages includes multiple memory cells connected to a single word line. A page functions as a unit of a data write operation and a data read operation. Note that a word line may also function as a unit of a data write operation and a data read operation.

[0020] There is an upper limit to the number of program / erase cycles (P / E cycles) for each block, called the maximum number of P / E cycles. One P / E cycle for a block includes an erase operation to erase all memory cells in the block, and a write operation to write data to each page of the block.

[0021] The DRAM 6 is a volatile memory. A RAM such as the DRAM 6 is provided with, for example, a storage area for firmware (FW) and a cache area for a logical-physical address conversion table.

[0022] The controller 4 can be realized by a circuit such as an SoC. The controller 4 may have an SRAM built in. In this case, the memory system 3 does not need to be provided with a DRAM 6. Alternatively, the DRAM 6 may be built in the controller 4. The controller 4 functions as a memory controller configured to control the NAND flash memory 5.

[0023] The controller 4 may function as a flash translation layer (FTL) configured to perform data management and block management of the NAND flash memory 5. The data management performed by the FTL includes (1) management of mapping information indicating the correspondence between each logical address and each physical address of the NAND flash memory 5, and (2) processing for concealing the difference between page-based data read / write operations and block-based data erase operations. The block management includes management of bad blocks, wear leveling, and garbage collection.

[0024] The logical address is used by the host 2 to address a storage area in the memory system 3. The logical address is, for example, a logical block address (LBA).

[0025] The management of the mapping between each logical address and each physical address is performed using, for example, a logical-physical address conversion table. The controller 4 uses the logical-physical address conversion table to manage the mapping between each logical address and each physical address in specific management size units. A physical address corresponding to a certain logical address indicates a physical storage location in the NAND flash memory 5 where user data of this logical address is written. The logical-physical address conversion table may be loaded from the NAND flash memory 5 to the DRAM 6 when the memory system 3 is started up.

[0026] Data can be written to one page only once per P / E cycle. Therefore, the controller 4 writes updated user data corresponding to a certain logical address to a different physical storage location, rather than to the physical storage location where the previous user data corresponding to this logical address is stored. The controller 4 then invalidates the previous user data by updating the logical-physical address translation table so as to associate this logical address with this different physical storage location.

[0027] The controller 4 includes, for example, a host interface (host I / F) 11, a CPU 15, a NAND interface (NAND I / F) 16, and a DRAM interface (DRAM I / F) 17. The host I / F 11, the CPU 15, the NAND I / F 16, and the DRAM I / F 17 may be connected via a bus 10.

[0028] The CPU 15 is a processor configured to control the host I / F 11, the NAND I / F 16, and the DRAM I / F 17. The CPU 15 performs various processes by executing the FW loaded from the NAND flash memory 5 to the DRAM 6. The FW is a control program including a group of instructions for causing the CPU 15 to perform various processes. The CPU 15 can execute command processing and the like for processing various commands from the host 2. The operation of the CPU 15 is controlled by the FW executed by the CPU 15.

[0029] The NAND I / F 16 electrically connects the controller 4 and the NAND flash memory 5. The NAND I / F 16 supports interface standards such as Toggle DDR and Open NAND Flash Interface (ONFI).

[0030] The NAND I / F 16 functions as a NAND control circuit configured to control the NAND flash memory 5. The NAND I / F 16 may be connected to multiple memory chips in the NAND flash memory 5 via multiple channels (Ch). By driving multiple memory chips in parallel, it is possible to widen the bandwidth of access to the entire NAND flash memory 5.

[0031] The DRAM I / F 17 functions as a DRAM control circuit configured to control access to the DRAM 6 .

[0032] The host I / F 11 is a circuit that functions as an interface for communication between the memory system 3 and each of the multiple hosts 2-1 and 2-2. The host I / F 11 includes a circuit for receiving packets from each of the first host 2-1 and the second host 2-2. The packets are, for example, packets that comply with the PCIe standard. The received packets include various commands, for example, input / output (I / O) commands and various control commands.

[0033] The host I / F 11 also includes a circuit for transmitting packets to each of the first host 2-1 and the second host 2-2. The transmitted packets include, for example, a response to a command and user data.

[0034] The host I / F 11 includes, for example, PCIe PHYs 12-1 and 12-2, PCIe link controllers 13-1 and 13-2, and an NVMe controller 14.

[0035] The PCIe PHYs 12-1 and 12-2 are circuits corresponding to the physical layer defined by the PCIe standard, and have a physical connection format that complies with the PCIe standard, for example.

[0036] The PCIe PHY 12-1 is connected to, for example, the PCIe PHY 21-1 of the first host 2-1 via a serial interface. This serial interface includes a link 31 (hereinafter referred to as the first link 31) that can interconnect the PCIe PHY 12-1 and the PCIe PHY 21-1. The PCIe PHY 12-1 and the PCIe PHY 21-1 perform an interface operation to physically transmit and receive data via the first link 31.

[0037] The PCIe PHY 12-2 is connected to, for example, the PCIe PHY 21-2 of the second host 2-2 via a serial interface. This serial interface includes a link 32 (hereinafter referred to as the second link 32) that can interconnect the PCIe PHY 12-2 and the PCIe PHY 21-2. The PCIe PHY 12-2 and the PCIe PHY 21-2 perform an interface operation to physically transmit and receive data via the second link 32. Data is transmitted in the form of packets via each of the first link 31 and the second link 32.

[0038] The PCIe link controller 13-1 is a circuit that manages the first link 31 and performs processing for exchanging data between the PCIe PHY 12-1 and the NVMe controller 14. More specifically, the PCIe link controller 13-1 receives packets from the first host 2-1 via the first link 31 and the PCIe PHY 12-1. The PCIe link controller 13-1 processes the packets to, for example, acquire data to be sent to the NVMe controller 14. The PCIe link controller 13-1 sends the acquired data to the NVMe controller 14. The data to be sent to the NVMe controller 14 is, for example, data related to access to the NAND flash memory 5. More specifically, the data to be sent to the NVMe controller 14 is, for example, a write request, a read request, and a Vendor Defined Message (VDM) for the NAND flash memory 5.

[0039] The PCIe link controller 13-2 is a circuit that manages the second link 32 and performs processing for exchanging data between the PCIe PHY 12-2 and the NVMe controller 14. More specifically, the PCIe link controller 13-2 receives packets from the second host 2-2 via the second link 32 and the PCIe PHY 12-2. The PCIe link controller 13-2 processes the packets to obtain, for example, data to be sent to the NVMe controller 14. The PCIe link controller 13-2 sends the obtained data to the NVMe controller 14.

[0040] The NVMe controller 14 is a circuit that processes transactions such as write requests, read requests, or VDMs for the NAND flash memory 5. The NVMe controller 14 performs the following operations: an operation according to a request included in data received via the PCIe PHY 12-1 and the PCIe link controller 13-1; an operation according to a request included in data received via the PCIe PHY 12-2 and the PCIe link controller 13-2; an operation for transmitting data including a response to the request via the PCIe PHY 12-1 and the PCIe link controller 13-1; and an operation for transmitting data including a response to the request via the PCIe PHY 12-2 and the PCIe link controller 13-2. The operations performed by the NVMe controller 14 comply with, for example, the NVMe standard.

[0041] In this way, PCIe PHY 12-1, PCIe link controller 13-1, and NVMe controller 14 control data transfer between the first host 2-1 and the memory system 3. Furthermore, PCIe PHY 12-2, PCIe link controller 13-2, and NVMe controller 14 control data transfer between the second host 2-2 and the memory system 3. That is, the memory system 3 includes a port (hereinafter also referred to as port 0) for data transfer with the first host 2-1, and a port (hereinafter also referred to as port 1) for data transfer with the second host 2-2.

[0042] The functions of the various units in the controller 4 may be realized by dedicated hardware in the controller 4, or may be realized by the CPU 15 executing the FW.

[0043] Here, the link power states set for a link will be described. The link power state is a power state set for a link. The link power state is set, for example, by the ASPM function defined in the PCIe standard. The ASPM function is a function that can set a link to a low power consumption state even when a device (for example, memory system 3) is in an operating state. The link power states include, for example, link power state L0 and link power state L1. Link power state L0 is a normal operating state (active state). Link power state L1 is a low power consumption state (inactive state). Link power state L1 is also called ASPM L1.

[0044] When a link that has transitioned to link power state L1 returns to link power state L0, a delay of, for example, several microseconds (exit latency) occurs. This delay can degrade the performance of packet transmission over the link. Therefore, when a device predicts packet transmission over the link, it performs control to prevent the link from transitioning to link power state L1.

[0045] An example of control of the link power state will be described using first and second comparative examples.

[0046] (First Comparative Example) The memory system according to the first comparative example performs data transmission with one host.

[0047] FIG. 2 shows an example of an operation in which the link 31A with the host 2A is maintained in the link power state L0 (normal operating state) in the memory system 3A of the first comparative example.

[0048] The memory system 3A has one port for connecting to one host 2A. Specifically, the memory system 3A includes a PCIe PHY 12A, a PCIe link controller 13A, and an NVMe controller 14A.

[0049] The PCIe PHY 12A is connected to the PCIe PHY 21A of the host 2A via a serial interface. This serial interface includes a link 31A that can interconnect the PCIe PHY 12A and the PCIe PHY 21A.

[0050] The PCIe link controller 13A manages a link 31A between the PCIe PHY 12A and the PCIe PHY 21A, and performs processing for exchanging data between the PCIe PHY 12A and the NVMe controller 14A.

[0051] The NVMe controller 14A performs an operation according to a command contained in data received via the PCIe PHY 12A and the PCIe link controller 13A, and an operation for transmitting data including a response to the command via the PCIe PHY 12A and the PCIe link controller 13A.

[0052] In this way, the PCIe PHY 12A, the PCIe link controller 13A, and the NVMe controller 14A control data transmission between the host 2A and the memory system 3A.

[0053] Here, a configuration for controlling the link power state in the memory system 3A will be described.

[0054] The PCIe link controller 13A includes an ASPM L1 timer / controller 131A.

[0055] The ASPM L1 timer / controller 131A is a circuit having an ASPM function. The ASPM L1 timer / controller 131A controls the link power state of the link 31A using the ASPM function. More specifically, when the link 31A is set to the link power state L0, the ASPM L1 timer / controller 131A can function as a timer that measures the time during which no packets are transmitted via the link 31A. If the measured time exceeds a threshold (i.e., if the timer expires), the ASPM L1 timer / controller 131A transitions the link 31A from the link power state L0 to the link power state L1. This causes the link 31A to enter a low power consumption state.

[0056] When the NVMe controller 14A predicts the transmission of a packet via the link 31A, it sends a busy signal to the ASPM L1 timer / controller 131A. The busy signal indicates that the NVMe controller 14A is busy. The NVMe controller 14A in the busy state predicts the transmission of a packet via the link 31A.

[0057] If a busy signal is sent by the NVMe controller 14A while the link 31A is set to the link power state L1, the ASPM L1 timer / controller 131A transitions the link 31A to the link power state L0. Furthermore, while the link 31A is set to the link power state L0 and a busy signal is sent by the NVMe controller 14A (i.e., while the busy signal is active), the ASPM L1 timer / controller 131A does not measure the time during which no packet transmission is performed via the link 31A. Therefore, while a busy signal is sent by the NVMe controller 14A, the ASPM L1 timer / controller 131A does not transition the link 31A from the link power state L0 to the link power state L1.

[0058] Due to the operation of the ASPM L1 timer / controller 131A in response to such a busy signal, when packet transmission via link 31A is predicted, link 31A does not transition from link power state L0 to link power state L1. Therefore, in the operation of the ASPM L1 timer / controller 131A while receiving a busy signal, link 31A set to link power state L0 does not transition to link power state L1, and link 31A set to link power state L1 does not return to link power state L0. Therefore, no delay occurs due to the transition from link power state L1 to link power state L0. Therefore, when packet transmission via link 31A is predicted, degradation in performance of packet transmission via link 31A can be prevented.

[0059] (Second Comparative Example) The memory system according to the second comparative example performs data transmission with each of two hosts.

[0060] FIG. 3 shows an example of operation in which both the link 31B with the host 2-1B and the link 31B with the host 2-2B are maintained in the link power state L0 (normal operating state) in a memory system 3B according to the second comparative example.

[0061] The memory system 3B has two ports for connecting to two hosts 2-1B and 2-2B, respectively. Specifically, the memory system 3B includes PCIe PHYs 12-1B and 12-2B, PCIe link controllers 13-1B and 13-2B, and an NVMe controller 14B.

[0062] The PCIe PHY 12-1B is connected to the PCIe PHY 21-1B of the host 2-1B via a serial interface. This serial interface includes a link 31B (hereinafter referred to as a first link 31B) that can interconnect the PCIe PHY 12-1B and the PCIe PHY 21-1B.

[0063] The PCIe PHY 12-2B is connected to the PCIe PHY 21-2B of the host 2-2B via a serial interface. This serial interface includes a link 32B (hereinafter referred to as a second link 32B) that can interconnect the PCIe PHY 12-2B and the PCIe PHY 21-2B.

[0064] The PCIe link controller 13-1B manages the first link 31B and performs processing for exchanging data between the PCIe PHY 12-1B and the NVMe controller 14B.

[0065] The PCIe link controller 13-2B manages the second link 32B and performs processing for exchanging data between the PCIe PHY 12-2B and the NVMe controller 14B.

[0066] The NVMe controller 14B performs an operation according to a command included in data received via either the PCIe PHY 12-1B and the PCIe link controller 13-1B, or the PCIe PHY 12-2B and the PCIe link controller 13-2B, and an operation for transmitting data including a response to the command via either the PCIe PHY 12-1B and the PCIe link controller 13-1B, or the PCIe PHY 12-2B and the PCIe link controller 13-2B.

[0067] In this manner, PCIe PHY 12-1B, PCIe link controller 13-1B, and NVMe controller 14B control data transmission between host 2-1B and memory system 3B. PCIe PHY 12-2B, PCIe link controller 13-2B, and NVMe controller 14B control data transmission between host 2-2B and memory system 3B.

[0068] Here, a configuration for controlling the link power state in the memory system 3B will be described.

[0069] The PCIe link controller 13-1B includes an ASPM L1 timer / controller 131-1B.

[0070] The ASPM L1 timer / controller 131-1B is a circuit having an ASPM function that controls the link power state of the first link 31B. More specifically, when the first link 31B is set to link power state L0, the ASPM L1 timer / controller 131-1B can function as a timer that measures the time during which no packets are transmitted via the first link 31B. If the measured time exceeds a threshold, the ASPM L1 timer / controller 131-1B transitions the link power state of the first link 31B from link power state L0 to link power state L1. This causes the first link 31B to enter a low power consumption state.

[0071] The PCIe link controller 13-2B includes an ASPM L1 timer / controller 131-2B, which controls the link power state of the second link 32B in the same manner as the ASPM L1 timer / controller 131-1B.

[0072] When NVMe controller 14B expects to transmit a packet via link 31B or 32B, it sends a busy signal to both ASPM L1 timer / controller 131-1B and ASPM L1 timer / controller 131-2B. The busy signal indicates that NVMe controller 14B is busy. When NVMe controller 14B is busy, it expects to transmit a packet via link 31B or 32B.

[0073] If a busy signal is sent by the NVMe controller 14B while the first link 31B is set to link power state L1, the ASPM L1 timer / controller 131-1B transitions the first link 31B to link power state L0. Furthermore, while the first link 31B is set to link power state L0 and a busy signal is sent by the NVMe controller 14B, the ASPM L1 timer / controller 131-1B does not measure the time during which no packet transmission is performed via the first link 31B. Therefore, while a busy signal is sent by the NVMe controller 14B, the ASPM L1 timer / controller 131-1B does not transition the first link 31B from link power state L0 to link power state L1.

[0074] If a busy signal is sent by the NVMe controller 14B while the second link 32B is set to the link power state L1, the ASPM L1 timer / controller 131-2B transitions the second link 32B to the link power state L0. Furthermore, while the second link 32B is set to the link power state L0 and a busy signal is sent by the NVMe controller 14B, the ASPM L1 timer / controller 131-2B does not measure the time during which no packet transmission is performed via the second link 32B. Therefore, while a busy signal is sent by the NVMe controller 14B, the ASPM L1 timer / controller 131-2B does not transition the second link 32B from the link power state L0 to the link power state L1.

[0075] The operation of the ASPM L1 timer / controllers 131-1B and 131-2B in response to such a busy signal prevents both links 31B and 32B from transitioning from link power state L0 to link power state L1 when packet transmission via link 31B or 32B is predicted. Therefore, the operation of the ASPM L1 timer / controller 131-1B in response to the busy signal does not cause link 31B, which has been set to link power state L0, to transition to link power state L1 and then back to link power state L0. Furthermore, the operation of the ASPM L1 timer / controller 131-2B in response to the busy signal does not cause link 32B, which has been set to link power state L0, to transition to link power state L1 and then back to link power state L0. Therefore, no delay occurs due to the transition from link power state L1 to link power state L0. This prevents performance degradation in packet transmission via link 31B or 32B when packet transmission via link 31B or 32B is predicted.

[0076] The NVMe controller 14B is configured not to determine whether the packet transmission predicted to occur will be via the first link 31B or the second link 32B. Therefore, the NVMe controller 14B sends a busy signal to both the ASPM L1 timer / controller 131-1B and the ASPM L1 timer / controller 131-2B, even if the packet transmission predicted to occur will be via either the first link 31B or the second link 32B.

[0077] Because a busy signal is sent to both ASPM L1 timer / controller 131-1B and ASPM L1 timer / controller 131-2B, in memory system 3B, if a packet transmission that is expected to occur is via one of two links 31B and 32B but not via the other link, neither one link nor the other link will transition from link power state L0 to link power state L1.

[0078] For example, if the packet transmission predicted to occur is via the first link 31B and not via the second link 32B, the operation of the ASPM L1 timer / controller 131-2B in response to the busy signal prevents the second link 32B from transitioning from the link power state L0 to the link power state L1 even though no packets are to be transmitted via the second link 32B for a specific period of time. As a result, the reduction in power consumption that would be achieved by transitioning the second link 32B to the link power state L1 is not achieved.

[0079] In contrast, in the memory system 3 of this embodiment, each of the two PCIe link controllers 13-1 and 13-2 is provided with a circuit (hereinafter referred to as a busy signal control circuit) that enables or disables a busy signal sent from the NVMe controller 14 depending on whether a packet containing data transmitted from each of the two hosts 2-1 and 2-2 to the NVMe controller 14 has been detected. In the memory system 3, the link power states of each of the two links 31 and 32 are controlled based on the busy signal enabled or disabled by the busy signal control circuit. As a result, in the memory system 3, if a packet transmission predicted to occur is via one of the two links 31 and 32 but not via the other link, the other link can transition from link power state L0 to link power state L1. Therefore, by transitioning the other link to link power state L1, power consumption can be reduced.

[0080] An example of a configuration for controlling the link power state in the memory system 3 of this embodiment will be specifically described with reference to FIG.

[0081] The PCIe link controller 13-1 includes an ASPM L1 timer / controller 131-1 and a busy signal control circuit 132-1, and the PCIe link controller 13-2 includes an ASPM L1 timer / controller 131-2 and a busy signal control circuit 132-2.

[0082] The NVMe controller 14 sends a busy signal to the PCIe link controllers 13-1 and 13-2 when it expects to transmit a packet via either the links 31 and 32. Sending a busy signal is also referred to as activating the busy signal. Not sending a busy signal is also referred to as inactivating the busy signal. For example, the NVMe controller 14 sends a busy signal when it has not completed processing all requests received from the hosts 2-1 and 2-2 (for example, when it has not returned all responses to the requests). The busy signal sent by the NVMe controller 14 is received by the busy signal control circuits 132-1 and 132-2, not the ASPM L1 timer / controllers 131-1 and 131-2. The busy signal indicates that the NVMe controller 14 is busy. An NVMe controller 14 in a busy state expects to transmit a packet via either the links 31 and 32.

[0083] For example, when the NVMe controller 14 receives from the PCIe link controller 13-1 data contained in a packet transmitted from the first host 2-1 via the first link 31, or when the NVMe controller 14 receives from the PCIe link controller 13-2 data contained in a packet transmitted from the second host 2-2 via the second link 32, the NVMe controller 14 predicts transmission of the packet via either the link 31 or the link 32. Note that the NVMe controller 14 does not determine whether the packet transmission predicted to occur will be via the first link 31 or the second link 32.

[0084] The NVMe controller 14 does not send a busy signal to either the PCIe link controller 13-1 or the PCIe link controller 13-2 when neither packet transmission via link 31 nor packet transmission via link 32 is predicted. For example, when the NVMe controller 14 has completed processing all requests received from the hosts 2-1 and 2-2 (for example, when all responses to the requests have been returned), the NVMe controller 14 stops sending the busy signal. In other words, it changes the busy signal from active to inactive.

[0085] The busy signal control circuit 132-1 is a circuit that enables or disables the busy signal sent by the NVMe controller 14 depending on whether a packet containing data transmitted from the first host 2-1 to the NVMe controller 14 via the first link 31 is detected. Hereinafter, a packet containing data transmitted from either the first host 2-1 or the second host 2-2 to the NVMe controller 14 is also referred to as a target packet.

[0086] The busy signal control circuit 132-1 detects a target packet. More specifically, when the PCIe link controller 13-1 receives a packet via the first link 31 and the PCIe PHY 12-1, the busy signal control circuit 132-1 determines, for example, whether the packet includes data to be sent to the NVMe controller 14. If the packet includes data to be sent to the NVMe controller 14, the busy signal control circuit 132-1 detects the packet as a target packet.

[0087] Alternatively, when the PCIe link controller 13-1 receives a packet, the busy signal control circuit 132-1 may determine whether the packet includes data related to access to the NAND flash memory 5. In this case, the busy signal control circuit 132-1 detects the packet including data related to access to the NAND flash memory 5 as the target packet.

[0088] The data related to access to the NAND flash memory 5 is, for example, data of a type that will later cause packet transmission via the first link 31. The data of a type that will later cause packet transmission via the first link 31 is, for example, a write request, a read request, or a VDM for the NAND flash memory 5. The busy signal control circuit 132-1 may detect, as the target packet, a packet that includes data of a type that will later cause packet transmission via the first link 31. In this case, the busy signal control circuit 132-1 can enable the busy signal only if packet transmission via the first link 31 will later occur.

[0089] When the busy signal control circuit 132-1 detects a target packet, it activates the busy signal. In other words, when the target packet is detected, the busy signal control circuit 132-1 sends the busy signal sent by the NVMe controller 14 to the ASPM L1 timer / controller 131-1 as is.

[0090] More specifically, the busy signal control circuit 132-1 operates to enable the busy signal when the busy signal sent by the NVMe controller 14 changes from inactive to active after detecting the target packet. Also, when the busy signal control circuit 132-1 detects the target packet, it operates to enable the busy signal even if the busy signal sent by the NVMe controller 14 is already active. Thereafter, if the busy signal changes from active to inactive, the busy signal control circuit 132-1 resets its state. The busy signal control circuit 132-1, whose state has been reset, operates to disable the busy signal.

[0091] On the other hand, if a target packet is not detected, the busy signal control circuit 132-1 disables the busy signal. In other words, if a target packet is not detected, the busy signal control circuit 132-1 does not send the busy signal sent by the NVMe controller 14 to the ASPM L1 timer / controller 131-1.

[0092] The ASPM L1 timer / controller 131-1 is a circuit having an ASPM function, and controls the link power state of the first link 31 by using the ASPM function.

[0093] Specifically, when the first link 31 is set to link power state L0, the ASPM L1 timer / controller 131-1 can function as a timer that measures the time during which no packets are transmitted via the first link 31. If the measured time exceeds a threshold, the ASPM L1 timer / controller 131-1 transitions the first link 31 from link power state L0 to link power state L1. This puts the first link 31 into a low power consumption state.

[0094] Note that putting the first link 31 into a low power consumption state includes at least a part of the configuration within the memory system 3 that manages and controls the first link 31 operating in a low power consumption state. Putting the first link 31 into a normal operation state also includes the configuration within the memory system 3 that manages and controls the first link 31 operating in a normal operation state. The configuration within the memory system 3 that manages and controls the first link 31 is, for example, PCIe PHY 12-1 and PCIe link controller 13-1.

[0095] If the ASPM L1 timer / controller 131-1 receives a busy signal from the busy signal control circuit 132-1 while the first link 31 is set to the link power state L1, the ASPM L1 timer / controller 131-1 transitions the first link 31 to the link power state L0. Note that if the ASPM L1 timer / controller 131-1 does not receive a busy signal while the first link 31 is set to the link power state L1, the first link 31 is maintained in the link power state L1. The ASPM L1 timer / controller 131-1 does not receive a busy signal if the NVMe controller 14 is not sending a busy signal or if the busy control circuit 132-1 disables the busy signal sent by the NVMe controller 14.

[0096] While the first link 31 is set to link power state L0 and receives a busy signal from the busy signal control circuit 132-1, the ASPM L1 timer / controller 131-1 does not measure the time during which no packet transmission is performed via the first link 31. Therefore, while the busy signal is being sent by the busy signal control circuit 132-1, the ASPM L1 timer / controller 131-1 does not transition the first link 31 from link power state L0 to link power state L1.

[0097] The ASPM L1 timer / controller 131-1 measures the time during which no packets are transmitted through the first link 31 while the first link 31 is set to the link power state L0 and no busy signal is received from the busy signal control circuit 132-1. If the measured time exceeds a threshold, the ASPM L1 timer / controller 131-1 transitions the first link 31 from the link power state L0 to the link power state L1. As a result, not only when the NVMe controller 14 is not transmitting a busy signal, but also when the busy signal control circuit 132-1 disables the busy signal transmitted by the NVMe controller 14, the ASPM L1 timer / controller 131-1 can transition the first link 31 to the link power state L1 if the time during which no packets are transmitted through the first link 31 continues exceeds the threshold.

[0098] Therefore, when the busy signal control circuit 132-1 has not detected a target packet, that is, when the packet transmission predicted to occur is via the second link 32 and not via the first link 31, it is possible to extend the period during which the first link 31 is in the link power state L1 and increase the possibility that the first link 31 will transition to the link power state L1. This makes it possible to reduce power consumption when multiple links 31 and 32 are used.

[0099] The operation of the busy signal control circuit 132-2 and ASPM L1 timer / controller 131-2 in the PCIe link controller 13-2 and the NVMe controller 14 with respect to the second link 32 is similar to the operation of the busy signal control circuit 132-1 and ASPM L1 timer / controller 131-1 in the PCIe link controller 13-1 and the NVMe controller 14 with respect to the first link 31.

[0100] A specific example of how the link power states of the two links 31 and 32 in the memory system 3 are controlled will be described with reference to FIGS.

[0101] 5 shows an example of an operation in which the first link 31 (port 0) transitions from link power state L1 to link power state L0, and the second link 32 (port 1) is maintained in link power state L1. At the start of this operation, both the first link 31 and the second link 32 are set to link power state L1 ((1) in FIG. 5). At this start, the busy signal sent by the NVMe controller 14 may be active or inactive.

[0102] The first host 2-1 executes a transition sequence for transitioning the first link 31 to the link power state L0 in response to the occurrence of data to be transmitted to the memory system 3 ((2) in FIG. 5). This transition sequence includes a training process for making the first link 31 available, such as synchronizing clock signals between the first host 2-1 and the memory system 3.

[0103] As a result of the transition sequence being executed, the PCIe link controller 13-1 transitions the first link 31 to the link power state L0 ((3) in FIG. 5).

[0104] After the first link 31 transitions to the link power state L0, the first host 2-1 transmits a packet containing data to be transmitted to the memory system 3 via the first link 31 to the memory system 3 ((4) in Figure 5).

[0105] The PCIe link controller 13-1 receives a packet via the PCIe PHY 12-1. The PCIe link controller 13-1 processes the received packet to obtain, for example, data to be sent to the NVMe controller 14. The PCIe link controller 13-1 sends the obtained data to the NVMe controller 14.

[0106] The busy signal control circuit 132-1 detects a packet (target packet) containing data transmitted from the first host 2-1 to the NVMe controller 14 via the first link 31 ((5) in FIG. 5). For example, when a packet received by the PCIe link controller 13-1 contains data to be sent to the NVMe controller 14, the busy signal control circuit 132-1 detects the packet as a target packet.

[0107] The NVMe controller 14 receives the data in the packet sent by the PCIe link controller 13-1. Based on the received data, the NVMe controller 14 determines whether transmission of the packet via link 31 or 32 is predicted. Here, it is assumed that transmission of the packet via link 31 or 32 is predicted. In this case, the NVMe controller 14 activates the busy signal ((6) in FIG. 5). Note that if the busy signal was already active, the NVMe controller 14 maintains the busy signal active. The active busy signal is received by the busy signal control circuit 132-1 and the busy signal control circuit 132-2.

[0108] Having detected the target packet, the busy signal control circuit 132-1 enables the busy signal received from the NVMe controller 14 ((7-1) in FIG. 5). In other words, the busy signal control circuit 132-1 sends a busy signal to the ASPM L1 timer / controller 131-1.

[0109] Since the ASPM L1 timer / controller 131-1 receives the busy signal, it keeps the first link 31 in the link power state L0 ((8-1) in FIG. 5).

[0110] In this way, the busy signal control circuit 132-1 enables the busy signal when it detects a target packet, so the first link 31 does not transition to link power state L1 due to the operation of the ASPM L1 timer / controller 131-1. Therefore, it is possible to prevent a delay caused by returning the first link 31 from link power state L1 to link power state L0.

[0111] On the other hand, since the busy signal control circuit 132-2 has not detected the target packet, it invalidates the busy signal received from the NVMe controller 14 ((7-2) in FIG. 5). In other words, the busy signal control circuit 132-2 does not send a busy signal to the ASPM L1 timer / controller 131-2.

[0112] Since the ASPM L1 timer / controller 131-2 has not received a busy signal, it maintains the second link 32 in the link power state L1 ((8-2) in FIG. 5).

[0113] In this way, the busy signal control circuit 132-2 disables the busy signal when it does not detect a target packet, and therefore the second link 32 does not transition to the link power state L0 due to the operation of the ASPM L1 timer / controller 131-2. In other words, the second link 32 is maintained in the link power state L1. This prevents the second link 32 from transitioning to the link power state L0 due to the NVMe controller 14 predicting packet transmission via the link 31 or 32 sending a busy signal. Therefore, the period during which the second link 32 is maintained in the link power state L1 can be extended compared to when the busy signal control circuit 132-2 that disables the busy signal is not provided. This reduces power consumption.

[0114] 6 shows an example of an operation in which the first link 31 is maintained in the link power state L0, and the second link 32 transitions from the link power state L0 to the link power state L1. At the start of this operation, both the first link 31 and the second link 32 are set to the link power state L0, and the busy signal sent by the NVMe controller 14 is inactive ((1) in FIG. 6).

[0115] The first host 2-1 transmits a packet containing data to be transmitted to the memory system 3 via the first link 31 to the memory system 3 ((2) in FIG. 6).

[0116] The PCIe link controller 13-1 receives a packet via the PCIe PHY 12-1. The PCIe link controller 13-1 processes the received packet to obtain, for example, data to be sent to the NVMe controller 14. The PCIe link controller 13-1 sends the obtained data to the NVMe controller 14.

[0117] The busy signal control circuit 132-1 detects a packet (target packet) containing data transmitted from the first host 2-1 to the NVMe controller 14 via the first link 31 ((3) in FIG. 6). For example, when a packet received by the PCIe link controller 13-1 contains data to be sent to the NVMe controller 14, the busy signal control circuit 132-1 detects the packet as a target packet.

[0118] The NVMe controller 14 receives data in the packet sent by the PCIe link controller 13-1. Based on the received data, the NVMe controller 14 determines whether transmission of the packet via link 31 or 32 is predicted. Here, it is assumed that transmission of the packet via link 31 or 32 is predicted. In this case, the NVMe controller 14 activates a busy signal ((4) in FIG. 6). The activated busy signal is received by the busy signal control circuits 132-1 and 132-2.

[0119] Having detected the target packet, the busy signal control circuit 132-1 enables the busy signal received from the NVMe controller 14 ((5-1) in FIG. 6). In other words, the busy signal control circuit 132-1 sends a busy signal to the ASPM L1 timer / controller 131-1.

[0120] Since the ASPM L1 timer / controller 131-1 receives the busy signal, it keeps the first link 31 in the link power state L0 ((6-1) in FIG. 6).

[0121] In this way, the busy signal control circuit 132-1 enables the busy signal when it detects a target packet, so the first link 31 does not transition to link power state L1 due to the operation of the ASPM L1 timer / controller 131-1. Therefore, it is possible to prevent a delay caused by returning the first link 31 from link power state L1 to link power state L0.

[0122] On the other hand, since the busy signal control circuit 132-2 has not detected the target packet, it invalidates the busy signal received from the NVMe controller 14 ((5-2) in FIG. 6). In other words, the busy signal control circuit 132-2 does not send a busy signal to the ASPM L1 timer / controller 131-2.

[0123] Because the ASPM L1 timer / controller 131-2 has not received a busy signal, it continues to measure the time during which no packets are transmitted via the second link 32. If the measured time exceeds a threshold, the ASPM L1 timer / controller 131-2 transitions the second link 32 from link power state L0 to link power state L1 ((6-2) in FIG. 6).

[0124] In this way, the busy signal control circuit 132-2 disables the busy signal when a target packet is not detected, and therefore the ASPM L1 timer / controller 131-2 can transition the second link 32 to the link power state L1. In other words, even when the NVMe controller 14 predicts packet transmission via the link 31 or 32 and sends a busy signal, the ASPM L1 timer / controller 131-2 can transition the second link 32 to the link power state L1. Therefore, compared to when the busy signal control circuit 132-2 that disables the busy signal is not provided, the second link 32 is more likely to transition to the link power state L1, thereby reducing power consumption.

[0125] As described above, this embodiment can reduce power consumption when multiple links are used for packet transmission. The PCIe link controller 13-1 sets the first link 31 between the first host 2-1 and the memory system 3 to either an active state or a low-power consumption state that consumes less power than the active state. The PCIe link controller 13-2 sets the second link 32 between the second host 2-2 and the memory system 3 to either an active state or a low-power consumption state. The NVMe controller 14 processes requests to a non-volatile memory (e.g., a NAND flash memory 5) using data contained in packets received via the first link 31 and the second link 32. When packet transmission via either the first link 31 or the second link 32 is predicted, the NVMe controller 14 sends a busy signal to the PCIe link controllers 13-1 and 13-2. When the first link 31 is in a low power consumption state and a packet containing data to be transmitted to the NVMe controller 14 is not received via the first link 31, the PCIe link controller 13-1 maintains the first link 31 in the low power consumption state by disabling the busy signal. When the first link 31 is in an operating state and a packet containing data to be transmitted to the NVMe controller 14 is not received via the first link 31, the PCIe link controller 13-1 transitions the first link 31 to the low power consumption state in response to the absence of a packet transmitted via the first link 31 for a first period by disabling the busy signal.

[0126] With the above configuration, for example, when packet transmission via the second link 32 is predicted, even if the NVMe controller 14 sends a busy signal to the PCIe link controller 13-1 to set the second link 32 to an operating state, the PCIe link controller 13-1 (more specifically, the busy signal control circuit 132-1) disables the busy signal. This makes it possible to extend the period during which the first link 31 is in a low power consumption state and increase the likelihood that the first link 31 will transition to a low power consumption state. This makes it possible to reduce power consumption when multiple links are used for packet transmission.

[0127] Each of the various functions described in this embodiment may be realized by a circuit (processing circuit). An example of a processing circuit includes a programmed processor, such as a central processing unit (CPU). This processor performs each of the described functions by executing a computer program (a set of instructions) stored in a memory. This processor may be a microprocessor including electrical circuits. Examples of processing circuits also include digital signal processors (DSPs), application specific integrated circuits (ASICs), microcontrollers, controllers, and other electrical circuit components. Each of the components other than the CPU described in this embodiment may also be realized by a processing circuit.

[0128] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0129] 1...information processing system, 2-1...first host, 2-2...second host, 21-1, 21-2...PCIe PHY, 3...memory system, 4...controller, 5...NAND flash memory, 6...DRAM, 11...host I / F, 12-1, 12-2...PCIe PHY, 13-1, 13-2...PCIe link controller, 14...NVMe controller, 15...CPU, 16...NAND I / F, 17...DRAM I / F, 131-1, 131-2...ASPM L1 timer / controller, 132-1, 132-2...busy signal control circuit, 31...first link, 32...second link.

Claims

1. A memory system connectable to a plurality of hosts via a serial interface, a non-volatile memory; a first controller that sets a first link between a first host and the memory system to either an operating state or a low power consumption state in which power consumption is lower than that of the operating state; a second controller that sets a second link between a second host and the memory system to either the operating state or the low power consumption state; processing requests to the non-volatile memory using data contained in packets received via the first link and the second link; a third controller that sends a busy signal to the first controller and the second controller when a packet transmission via either the first link or the second link is expected; Equipped with The first controller maintaining the first link in the low power consumption state by disabling the busy signal when the first link is in the low power consumption state and no packets containing data to be transmitted to the third controller are received over the first link; When the first link is in the operating state and a packet including data to be transmitted to the third controller is not received via the first link, the first link transitions to the low power consumption state in response to no packet being transmitted via the first link for a first period by disabling the busy signal. Memory system.

2. The second controller transitioning the second link from the low power consumption state to the operating state in response to the busy signal when the second link is in the low power consumption state and a packet including data to be transmitted to the third controller is received via the second link; 10. The memory system of claim 1.

3. The second controller, when the second link is in the operational state and a packet including data to be transmitted to the third controller is received via the second link, activates the busy signal to maintain the second link in the operational state.

3. The memory system according to claim 1.

4. When the first link is in the operating state and the third controller has finished sending the busy signal, the first controller transitions the first link to the low power consumption state in response to the absence of a packet transmitted via the first link for the first period.

4. The memory system according to claim 1.

5. The first controller includes circuitry that enables the busy signal when a packet containing data to be transmitted to the third controller is received over the first link and disables the busy signal when a packet containing data to be transmitted to the third controller is not received over the first link.

5. The memory system according to claim 1.

6. When the first controller receives a packet including first data to be transmitted to the third controller via the first link, the first controller sends the first data to the third controller; When the second controller receives a packet including second data to be transmitted to the third controller via the second link, the second controller sends the second data to the third controller; The third controller transmits the busy signal to the first controller and the second controller in response to receiving either the first data or the second data.

6. The memory system according to claim 1.

7. The third controller sending the busy signal to the first controller and the second controller when responses to all requests received from the first host or the second host have not been returned to the first host or the second host; When responses to all requests received from the first host or the second host have been returned to the first host or the second host, the sending of the busy signal to the first controller and the second controller is terminated.

7. The memory system of claim 6.

8. Each of the first data and the second data includes one of a write request, a read request, and a Vendor Defined Message (VDM) for the nonvolatile memory.

8. The memory system according to claim 6 or claim 7.

9. 9. The memory system according to claim 1, wherein the serial interface is a serial interface conforming to the PCI Express standard.

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