Output Circuit

Abstract

To provide an output circuit capable of suppressing stress for a transistor while suppressing an occurrence of malfunction.SOLUTION: In a pulse output circuit having a function of outputting a pulse signal and having a transistor for controlling whether or not the pulse signal is set to a high level, a potential of one of a source and a drain of the transistor is set to be higher than a low-level potential of a clock signal and be higher than a high-level potential while the pulse signal output from the pulse output circuit is at a low level. Thereby, stress on the transistor is suppressed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a pulse output circuit. Further, the present invention relates to a display device. The invention relates to electronic devices. [Background technology]

[0002] In recent years, in order to simplify the manufacturing process, all transistors have been made to be of the same conductivity type. Development of circuits that can be used in this way (also called unipolar circuits) is underway.

[0003] An example of the unipolar circuit is a pulse output circuit that constitutes a shift register.

[0004] For example, in Patent Document 1, the pulse of a clock signal is used to generate the pulse of a pulse signal. A shift register having multiple stages of pulse output circuits is disclosed. By using bootstrap, the output pulse width is adjusted to the amplitude of the clock signal. A shift register that suppresses the reduction in amplitude of a signal is disclosed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-335153 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the configuration of a conventional pulse output circuit, if the amplitude of the clock signal is large, the This causes a problem that the transistor deteriorates and the electrical characteristics of the transistor change.

[0007] For example, in the shift register of Patent Document 1, the pulse signal output from the pulse output circuit is This is a transformer that controls whether to set the output pulse signal to high level when the The potential of the gate of a transistor (for example, the transistor 15 in FIG. 1(B) of Patent Document 1) is equal to the potential VS S for a certain period of time. At this time, the source or In this case, the drain potential changes repeatedly, which puts stress on the transistor. This causes the transistors to deteriorate. Since the stress is applied for a very long time, the transistor is easily deteriorated and the electrical The characteristics change progressively.

[0008] In order to suppress the influence of the above-mentioned stress on the transistor, for example, However, there are some problems with the output pulse signal. If the channel length of the transistor that controls whether to set the signal to high level is increased, for example, Parasitic capacitance and other factors can cause delays in the output pulse signal, increasing the likelihood of malfunction. Other problems such as this may arise.

[0009] In view of the above problem, one aspect of the present invention is to provide a pulse signal output device that suppresses the occurrence of malfunctions. This reduces the stress on the transistor that controls whether the signal is set to a high level. One of the challenges is to: [Means for solving the problem]

[0010] In one aspect of the present invention, during a period in which a pulse signal output from a pulse output circuit is at a low level, The source and drain of a transistor that controls whether or not the pulse signal is set to a high level The potential of one of the inputs is set lower than the high level potential of the clock signal. This aims to reduce stress on transistors.

[0011] One aspect of the present invention is a method for generating a pulse signal in accordance with a set signal, a reset signal, and a clock signal. The potential of one of the source and drain is changed in accordance with a clock signal. a first transistor, one of the source and drain of which is the source and drain of the second transistor; The potential of the other of the source and drain is the potential of the pulse signal. a second transistor whose gate potential changes in response to a set signal and a reset signal; A first potential is applied to one of the source and the drain, and a second potential is applied to the other of the source and the drain. It is electrically connected to the other of the source and drain of the transistor and turns on and off depending on the potential of the gate. By turning on or off the pulse signal, it is possible to control whether or not to set the pulse signal to a low level. a third transistor having a second potential applied to one of its source and drain, The other of the drain and the drain is electrically connected to the gate of the first transistor, and the potential of the gate is set to the A fourth transistor whose source and drain change according to a start signal and a reset signal. The potential of one of the two electrodes changes in response to a set signal and a reset signal, and the potential of the other electrode changes in response to a set signal and a reset signal. It is electrically connected to the gate of the first transistor, and the potential of the gate changes according to the set signal. and a fifth transistor having the same conductivity type. The second potential is higher than the low level potential of the clock signal and is higher than the high level potential of the clock signal. The potential difference between the second potential and the low-level potential of the clock signal is , the threshold voltage of the first transistor is greater than the pulse output circuit. [Effects of the Invention]

[0012] According to one aspect of the present invention, a transistor for controlling whether or not to set an output pulse signal to a high level is provided. The stress on the transistor can be reduced without increasing the channel length of the transistor. Therefore, deterioration of the transistor can be suppressed, and fluctuations in electrical characteristics can be suppressed. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 2 is a diagram for explaining an example of a pulse output circuit. [Figure 2] FIG. 2 is a diagram for explaining an example of a pulse output circuit. [Figure 3] FIG. 2 is a diagram for explaining an example of a pulse output circuit. [Figure 4] FIG. 2 is a diagram for explaining an example of a pulse output circuit. [Figure 5] FIG. 2 is a diagram for explaining an example of a pulse output circuit. [Figure 6] FIG. 2 is a diagram for explaining an example of a pulse output circuit. [Figure 7] 1A and 1B illustrate examples of display devices. [Figure 8] 1A and 1B illustrate examples of display devices. [Figure 9] 1A and 1B illustrate examples of display devices. [Figure 10] 1A and 1B illustrate examples of display devices. [Figure 11] 1A to 1C are diagrams illustrating examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0014] An example of an embodiment of the present invention will be described. It is easy for a person skilled in the art to modify the content of the embodiment without modifying it. For example, the present invention is not limited to the description of the following embodiments.

[0015] The contents of each embodiment can be combined with each other as appropriate. The contents of the above can be substituted for each other as appropriate.

[0016] In addition, ordinal numbers such as 1st and 2nd are used to avoid confusion between components. The number is not limited to ordinal numbers.

[0017] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. refers to the state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This includes cases where the angle is between 85° and 95°.

[0018] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0019] (Embodiment 1) In this embodiment, an example of a pulse output circuit will be described.

[0020] FIG. 1 is a diagram illustrating an example of a pulse output circuit according to the present embodiment. As shown in FIG. 1A, the circuit SR receives a set signal S, a reset signal R, and It has the function of generating a pulse signal (output signal OUT) in accordance with the clock signal CK. A plurality of types of clock signals may be input to the pulse output circuit SR.

[0021] Furthermore, the pulse output circuit SR shown in FIG. 1(A) is a transistor as shown in FIG. 1(B). For example, transistors 11 to 15 Each of the transistors 11 to 15 has the same conductivity type. Conduction is controlled according to one or more of a signal S, a reset signal R, and a clock signal CK. The pulse output circuit SR shown in FIG. Other elements may also be provided.

[0022] The potential of one of the source and drain of the transistor 11 changes in accordance with the clock signal CK. The transistor 11 controls the high level potential of the pulse signal (output signal OUT). For example, the transistor 11 outputs a pulse signal (output signal OUT) to the first It has a function of controlling whether to set the first high level or not, and whether to set the second high level or not. At this time, the second high level potential is lower than the first high level potential.

[0023] The phrase "potential changes according to a signal" means that "a signal is directly input and the potential changes according to the signal." For example, the switch is turned on in response to a signal. "When the potential changes due to the capacitance being increased," or "When the potential changes due to the capacitance being increased due to the capacitance being increased," "When the potential changes" is also included in "when the potential changes according to a signal."

[0024] Furthermore, the "potential according to the signal" is not limited to only the "potential having the same value as the potential of the signal." For example, the value of the signal potential that has changed due to a voltage drop is also included in the "potential according to the signal."

[0025] One of the source and drain of transistor 12 is connected to the source and drain of transistor 11. The potential of the other terminal becomes the potential of the pulse signal (output signal OUT). Furthermore, the potential of the gate of the transistor 12 is set according to the set signal S and the reset signal R. The transistor 12 sets the pulse signal (output signal OUT) to a high level. It has a function to control whether or not

[0026] A potential VSS is applied to one of the source and drain of the transistor 13, and a potential VSS is applied to the other of the source and drain of the transistor 13. The other of the source and drain of the transistor 12 is electrically connected. The potential of the gate of the clock 13 changes in accordance with the set signal S and the reset signal R. The potential of the gate of the transistor 13 is controlled by a clock signal different from the clock signal CK. The transistor 13 is turned on or off depending on the potential of the gate. This enables the function to control whether or not the pulse signal (output signal OUT) is set to low level. do.

[0027] A potential Va is applied to one of the source and drain of the transistor 14, and the other is applied to the The potential of the gate of the transistor 14 is electrically connected to the gate of the transistor 11. changes according to the set signal S and the reset signal R, or changes according to the clock signal CK The transistor 14 sets the potential of the gate of the transistor 11 to a value corresponding to the potential Va. It has the function of controlling whether or not

[0028] Note that the "value according to the potential" is not limited to "the same value as the potential". For example, Any change from the above potential value due to a drop is also included in the "value according to potential."

[0029] The potential of one of the source and drain of the transistor 15 is set by the set signal S and the reset signal The other one is electrically connected to the gate of transistor 11. The potential of the gate of the transistor 15 changes in accordance with the set signal S. The transistor 15 It has a function of controlling whether the gate of the transistor 11 is in a floating state or not.

[0030] The transistors 11 to 15 each have a channel forming region made of, for example, silicon. A transistor containing a semiconductor with a wider band gap than that of a semiconductor with a wider band gap can be applied. As the semiconductor, for example, an oxide semiconductor can be used. However, the present invention is not limited to this. For example, a transistor containing a semiconductor having an element of group 14 (such as silicon) is called a transistor 1. In this case, a semiconductor having a group 14 element may be used for the transistors 1 to 15. The material may be crystalline, polycrystalline, or amorphous.

[0031] Examples of the oxide semiconductor include In-based metal oxides, Zn-based metal oxides, and In-Zn-based Metal oxides or In-Ga-Zn based metal oxides can be used. a-Zn-based metal oxides containing other metal elements in place of part or all of the Ga contained in the oxides Metal oxides may also be used.

[0032] The structure of the oxide semiconductor film will be described below.

[0033] Oxide semiconductor films are roughly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. Physical semiconductor film, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor film, etc.

[0034] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not contain a crystalline component. The film is a compound semiconductor film. It does not have any crystalline parts even in the microscopic areas, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor film.

[0035] The microcrystalline oxide semiconductor film is made up of, for example, microcrystals (nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor film has a lower atomic number than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film has a higher order of molecular arrangement than the amorphous oxide semiconductor film. The defect level density is also low.

[0036] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so large that it fits inside a cube with a side length of less than 100 nm. The crystals contained in the S film are cubic with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than the microcrystalline oxide semiconductor film. The CAAC-OS film has a low density of recessed states. .

[0037] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a crystalline microscope, clear boundaries between the crystals, i.e., crystal boundaries, are clearly visible. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0038] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) It can be confirmed that the metal atoms are arranged in layers in the crystalline part. Each layer has a surface on which the CAAC-OS film is formed (also referred to as a surface on which the CAAC-OS film is formed) or an uneven surface on which the CAAC-OS film is formed. The shape reflects this and is aligned parallel to the surface on which the CAAC-OS film is formed or the top surface.

[0039] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (planar TEM). When observed, it was found that the metal atoms were arranged in triangular or hexagonal shapes in the crystals. However, there is no regularity in the arrangement of metal atoms between different crystal parts. stomach.

[0040] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It turns out that there are.

[0041] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0042] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0043] From the above, it is concluded that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. Although it is regular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0044] The crystalline part is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed or the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0045] The crystallinity of the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The area near the surface may have a higher degree of crystallinity than the area near the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region where the impurities are added changes, resulting in partial In some cases, regions of different crystallinity may be formed.

[0046] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0047] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0048] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminated film having two or more kinds of films.

[0049] This completes the description of the structure of the oxide semiconductor film.

[0050] Furthermore, a configuration example of the pulse output circuit according to this embodiment will be described with reference to FIG.

[0051] The pulse output circuit shown in Figure 2(A) outputs a set signal LIN corresponding to the set signal S, a reset signal a reset signal RIN corresponding to the reset signal R, clock signals CK1 to CK3, It also has the function of generating and outputting a pulse signal (output signal OUT) according to the initialization signal RES. It should be noted that the initialization signal RES does not necessarily have to be used.

[0052] The pulse output circuit shown in FIG. 2A includes transistors 61 to 76.

[0053] A potential VDD is applied to one of the source and drain of the transistor 61. The gate of the transistor 61 receives a set signal LIN.

[0054] The potential VSS is applied to one of the source and drain of the transistor 62, and the other is applied to the It is electrically connected to the other of the source and drain of the transistor 61 .

[0055] One of the source and drain of transistor 63 is connected to the source and drain of transistor 61. Furthermore, the gate of the transistor 63 is electrically connected to the other terminal of the set signal L. IN is input. The transistor 63 corresponds to the transistor 15 shown in FIG. .

[0056] One of the source and drain of transistor 64 is connected to the source and drain of transistor 61. Furthermore, the gate of the transistor 64 is electrically connected to the other terminal of the Given.

[0057] It should be noted that the transistor 64 does not necessarily have to be provided.

[0058] The clock signal CK1 is input to one of the source and drain of the transistor 65. Furthermore, the gate of the transistor 65 is connected to the other of the source and drain of the transistor 63. The transistor 65 corresponds to the transistor 11 shown in FIG. do.

[0059] One of the source and drain of transistor 66 is connected to the source and drain of transistor 65. The potential of the other terminal becomes the potential of the pulse signal (output signal OUT). The transistor 66 corresponds to the transistor 12 shown in FIG.

[0060] Furthermore, between the gate of transistor 65 and the other of the source and drain of transistor 66 A capacitance C1 is formed between the first and second terminals. However, it is not always necessary to form the capacitance C1.

[0061] Also, between the gate of the transistor 66 and the other of the source and drain of the transistor 66 A capacitance C2 is formed. Note that the gate of the transistor 66 and the other of the source and drain The parasitic capacitance between the capacitor C1 and the capacitor C2 may be used as the capacitance C2. good.

[0062] The potential VSS is applied to one of the source and drain of the transistor 67, and the other is applied to the The transistor 67 is electrically connected to the other of the source and drain of the transistor 66. , corresponds to the transistor 13 shown in FIG.

[0063] The clock signal CK1 is input to one of the source and drain of the transistor 68. Furthermore, the gate of the transistor 68 is connected to the other of the source and drain of the transistor 63. are electrically connected.

[0064] One of the source and drain of transistor 69 is connected to the source and drain of transistor 68. The potential of the other terminal is the potential of the pulse signal (output signal SROUT). Furthermore, the gate of transistor 69 is connected to the source and drain of transistor 64. It is electrically connected to the other.

[0065] Furthermore, between the gate of transistor 68 and the other of the source and drain of transistor 69 A capacitance C3 is formed between the first and second terminals 11 and 12. It should be noted that the capacitance C3 does not necessarily have to be formed.

[0066] Also, between the gate of the transistor 69 and the other of the source and drain of the transistor 69 A capacitance C4 is formed. The gate of the transistor 69 and the other of the source and drain The parasitic capacitance between the capacitor C1 and the capacitor C2 may be used as the capacitor C4. good.

[0067] The potential VSS is applied to one of the source and drain of the transistor 70, and the potential VSS is applied to the other of the source and drain of the transistor 70. The transistor 69 is electrically connected to the other of the source and drain. The gate of transistor 70 is electrically connected to the gate of transistor 62 .

[0068] Note that the transistors 68 to 70 do not necessarily have to be provided.

[0069] A potential Va is applied to one of the source and drain of the transistor 71, and the other is applied to the The gate of the transistor 65 and the gate of the transistor 68 are electrically connected to each other. The potential of the gate of the transistor 71 is set by a set signal LIN, a reset signal RIN, and an initialization signal RES, clock signal CK2, and clock signal CK3. Transistor 7 1 corresponds to the transistor 14 shown in FIG.

[0070] A potential VDD is applied to one of the source and drain of the transistor 72, and a potential VDD is applied to the other of the source and drain of the transistor 72. It is electrically connected to the gate of the transistor 67 and the gate of the transistor 70. The gate of the transistor 72 receives the reset signal RIN.

[0071] A potential VDD is applied to one of the source and drain of the transistor 73, and a potential VDD is applied to the other of the source and drain of the transistor 73. It is electrically connected to the gate of the transistor 67 and the gate of the transistor 70. The gate of the transistor 72 receives the initialization signal RES.

[0072] The potential VSS is applied to one of the source and drain of the transistor 74, and the potential VSS is applied to the other of the source and drain of the transistor 74. It is electrically connected to the gate of the transistor 67 and the gate of the transistor 70. The gate of the transistor 74 receives the set signal LIN.

[0073] A potential VDD is applied to one of the source and drain of the transistor 75. The gate of the transistor 75 receives the clock signal CK3.

[0074] One of the source and drain of transistor 76 is connected to the source and drain of transistor 75. The other is electrically connected to the gate of transistor 67 and the other is electrically connected to the gate of transistor 70. Furthermore, the gate of transistor 76 is electrically connected to the gate of clock signal CK2 is entered.

[0075] The potential VSS is applied to one of the pair of electrodes of the capacitor C5, and the potential VSS is applied to the other of the pair of electrodes of the transistor 71. The capacitor C5 is electrically connected to the gate. Furthermore, the capacitor C5 may not be provided.

[0076] The transistors 61 to 76 are, for example, transistors having the above oxide in the channel formation region. A transistor including a semiconductor can be applied.

[0077] Next, as an example of a method for driving the pulse output circuit according to this embodiment, the pulse shown in FIG. An example of a method for driving the output circuit will be described with reference to the timing chart in FIG. Here, as an example, each of the transistors 61 to 76 is an N-channel The potential VDD is a positive potential, the potential VSS is a negative potential, and the value of the potential Va is The explanation will be given assuming that the set signal LIN and reset signal RIN and the high-level potential of the clock signals CK1 to CK3 are V The low level potential is the same as the potential VSS. The threshold voltage of the transistor 65 is the same as that of the transistor 68. The threshold voltage of the transistor 66 is the same as that of the transistor 69. The potential difference between the potential Va and the low level potential of the clock signal CK1 is equal to the threshold voltage of the transistor 65. Also, before the period T1, a pulse of the initialization signal RES is input. , transistor 73 is turned on, and transistors 67, 70, and The pulse output circuit may be initialized by turning on the inverter 71. The connection point between the gate of the transistor 66 and other elements is a node NA, and the gate of the transistor 67 is a The connection point between the gate and other elements is a node NB, and the gate of transistor 65 and other elements The connection point between the source and drain of the transistor 65 and the other of the source and drain of the transistor 65 is a node NC. The connection point with one of the source and drain of the resistor 66 is designated as a node ND.

[0078] In this specification, the potential VSS is a voltage of at least 2V necessary for operating the circuit. The higher of the two power supply potentials is The potential is VDD.

[0079] In the example of the method for driving the pulse output circuit shown in FIG. 2A, the sensor The bit signal LIN goes high, and the transistors 72 and 74 are turned on. Also, since the reset signal RIN is at a low level, the transistor 72 is in an off state. In addition, since the clock signals CK1 to CK3 are at a low level, Transistor 75 and transistor 76 are turned off.

[0080] At this time, the potential of the node NC rises to a value equivalent to the potential VDD, and the transistors 65 and 66 The transistor 68 is turned on, and the potential of the node ND becomes the low level of the clock signal CK1. Furthermore, the transistor 63 is turned off. The potential of NA rises to a value equivalent to the potential VDD, and the transistors 66 and 69 In addition, the transistor 64 is turned off. Therefore, the pulse output shown in FIG. The power circuit is in a set state.

[0081] Next, during the period T2, the set signal LIN remains at a high level, so the transistor The transistor 61 and the transistor 74 remain on. Also, the reset signal RIN, clock signal CK2, and clock signal CK3 are Since it remains at a low level, transistors 72, 75, and 76 remains in the off state.

[0082] At this time, the transistors 62, 67, 70, and 71 Furthermore, transistors 65 and 66 remain in the on state. The capacitance C1 and the capacitance C2 cause a capacitive coupling between the node NA and the node N When the potential of C is higher than the sum of the potential VDD and the threshold voltage (Vth65) of the transistor 65, The voltage rises to a very high value, i.e., VDD + Vth65 + Vx (Vx is an arbitrary value). As a result, the potential of the output signal OUT becomes equal to the high level potential of the clock signal CK1. Also, the transistors 68 and 69 remain on, and the output signal S The potential of ROUT becomes equal to the high level potential of the clock signal CK1.

[0083] Next, in a period T3, the set signal LIN goes low, and the transistors 61 and 62 The transistor 72 and the transistor 74 are turned off. The clock signal CK2 goes high and the transistor 76 is turned on. Also, the reset signal RIN and the clock signal CK3 are at low level. As a result, transistors 72 and 75 remain off.

[0084] At this time, the transistors 62, 67, 70, and 71 The gates and drains of transistors 66 and 69 remain in the off state. The voltage between the input and the output is maintained at VDD+Vx, and the potential of the output signal OUT and the output signal SROUT remains at the same value as the high level potential of the clock signal CK1. OUT, the output signal SROUT remains at a high level.

[0085] Next, during a period T4, the reset signal RIN goes high, and the transistor 72 The clock signal CK1 goes to the low level. Because K2 remains high, transistor 76 remains high. The clock signal CK3 goes high, turning on the transistor 75. Since the set signal LIN remains at a low level, the transistors 61 and 63 , transistor 74 remains off.

[0086] At this time, the potential of the node NB becomes equal to the potential VDD, and the transistor 62, the transistor The transistor 67, the transistor 70, and the transistor 71 are turned on. The potential of the transistor 65 becomes a value corresponding to the potential Va, and the transistor 68 is turned on. Furthermore, the potential of the node NA becomes a value corresponding to the potential VSS, and the transistor Therefore, the potential of the node ND is The output signal OUT and the output signal CK1 have a value corresponding to the low level potential. The potential of SROUT becomes a value according to the low level potential of the clock signal CK1, and the output signal OUT, the output signal SROUT goes low. This causes the pulse shown in FIG. The output circuit is in a reset state.

[0087] Next, during a period T5, the reset signal RIN remains at a high level, so that the transistor The transistor 72 remains on. Also, the clock signal CK2 goes low. The transistor 76 is turned off. Also, since the clock signal CK3 remains at a high level, Therefore, the transistor 75 remains in the on state. Since the signal CK1 remains low, the transistors 61, 63, and The resistor 74 remains in the off state.

[0088] At this time, the potential of the node NB remains at a value corresponding to the potential VDD, and the transistor 62, The transistors 67, 70, and 71 remain on. , the potential of the node NC remains equal to the potential Va, and the transistor 65 The transistor 68 remains in the ON state. Also, the potential of the node NA remains at a value equivalent to the potential VSS. Therefore, the transistors 66 and 69 remain in the off state. The potential of the output node ND becomes equal to the low level potential of the clock signal CK1. The potentials of the output signal OUT and the output signal SROUT are the same as the low level potential of the clock signal CK1. The output signals OUT and SROUT become low level.

[0089] Next, during a period T6, the reset signal RIN goes low, and the transistor 72 The clock signal CK1 goes to the high level. The clock signal C K3 goes low, turning off the transistor 75. Furthermore, the set signal LI N, since the clock signal CK2 remains at a low level, the transistor 61, Transistor 63 and transistor 74 remain in the off state.

[0090] At this time, the potential of the node NB remains at the same value as the potential VDD, so that the transistor 6 2. Transistors 67, 70, and 71 remain on. Furthermore, since the potential of the node NC remains at the same value as the potential Va, the transistors 65 and 66 The transistor 68 remains in the on state. Also, when the potential of the node NA becomes equal to the potential VSS, Since the value remains the same, the transistors 66 and 69 remain in the off state. In addition, the potential of the gate of the transistor 65 is a potential Va which is lower than the potential VDD. The potential of the node ND becomes Va-Vth65. This is because the potential of the clock signal CK1 becomes low. The potential is higher than the high-level potential and lower than the high-level potential. The potential of the signal SROUT becomes equal to the low level of the clock signal CK1. As shown in the period T6, when the output signal OUT and the output signal SROUT are at a low level, The potential of the node ND is higher than the potential VSS and the low level potential of the clock signal CK1. The potential alternates between Va and Vth65, which is lower than the high level potential. Compared to the case where the potential of the drain of the transistor 66 alternates between the potential VDD and the potential VSS, , the stress on the transistor can be suppressed.

[0091] This concludes the description of the pulse output circuit shown in FIG.

[0092] The configuration of the pulse output circuit according to this embodiment is not limited to the above configuration, and may be other configurations. You can also do this.

[0093] For example, the pulse output circuit shown in FIG. 3(A) is a transformer of the pulse output circuit shown in FIG. 2(B). The gate of the transistor 62 is electrically connected to the other of the source and drain of the transistor 72. Instead, the reset signal RIN is input to the gate of the transistor 62. When the pulse output circuit is reset, the potential of the node NA is set to the same potential as the VSS. This can speed up the speed at which values ​​such as

[0094] As shown in FIG. 3B, the transistor 64 of the pulse output circuit shown in FIG. Transistor 68, transistor 69, transistor 70, transistor 73, transistor The transistor 75 and the transistor 76 do not necessarily have to be provided.

[0095] As shown in FIG. 4, each of the transistors 62 to 76 is provided with a backgate. By providing a gate and controlling the potential of the back gate, the transistors 62 to 64 are For example, the threshold voltage of the N-channel transistor 76 may be controlled by Applying a negative potential to the gate shifts the threshold voltage of the N-channel transistor in the positive direction. In the pulse output circuit shown in FIG. transistor 64, transistor 72, transistor 73, transistor 75, and transistor 7 A potential BG1 is applied to each of the back gates of the transistors 62 and 6. The back gates of transistors 63, 65 to 71, and 74 The potential BG1 and the potential BG2 are applied to each of the gates. When potentials are used, the value of potential BG2 is preferably lower than that of potential BG1. If the threshold voltage of the transistor to which 1 is supplied is too high, the pulse output circuit may malfunction. Because it's easy to happen.

[0096] In the configuration shown in FIG. 3(A) or 3(B), a backgate is also provided to the transistor. A port may be provided.

[0097] Furthermore, an example of a shift register including multiple stages of the pulse output circuit shown in FIG. 5 for further explanation.

[0098] The shift register 30 shown in FIG. 5A includes a plurality of stages of pulse output circuits (pulse output circuits 31 5A, the pulse output circuit 31 includes a pulse output circuit 31_1 to a pulse output circuit 31_N (N is a natural number of 2 or more). As an example, we will show the case where N=4 or more.

[0099] Each of the pulse output circuits 31_1 to 31_N is a pulse output circuit shown in FIG. The pulse output circuits 31_1 to 31_N correspond to the pulse output circuits shown in FIG. As shown in (B), the set signal LIN, the reset signal RIN, the initialization signal RES, The output signal OUT is generated according to the clock signal CK1, the clock signal CK2, and the clock signal CK3. , and has the function of generating and outputting a plurality of pulse signals as the output signal SROUT.

[0100] A start pulse signal SP is input to the pulse output circuit 31_1 as a set signal LIN. Furthermore, a set signal is supplied to the pulse output circuit 31_K (K is a natural number between 2 and N). LIN is a pulse signal (output signal SROU T) is entered.

[0101] The pulse output circuit 31_M (M is a natural number equal to or smaller than N-1) receives a pulse as a reset signal RIN. The pulse signal (output signal SROUT) output from the pulse output circuit 31_M+2 is input. do.

[0102] Furthermore, the pulse output circuit 31_1 receives the clock signal CLK1 as the clock signal CK1. is input as clock signal CK2, and clock signal CLK2 is input as clock signal CK3. The clock signal CLK3 is input as CK3. As a standard, every third pulse output circuit receives the clock signal CK1 as the clock signal CLK 1 is input, clock signal CLK2 is input as clock signal CK2, and clock signal The clock signal CLK3 is input as the signal CK3.

[0103] Furthermore, the pulse output circuit 31_2 receives the clock signal CLK2 as the clock signal CK1. is input, the clock signal CLK3 is input as the clock signal CK2, and the clock signal The clock signal CLK4 is input as CK3. As a standard, every third pulse output circuit receives the clock signal CK1 as the clock signal CLK 2 is input, clock signal CLK3 is input as clock signal CK2, and clock signal The clock signal CLK4 is input as the signal CK3.

[0104] Furthermore, the pulse output circuit 31_3 receives the clock signal CLK3 as the clock signal CK1. is input, the clock signal CLK4 is input as the clock signal CK2, and the clock signal The clock signal CLK1 is input as CK3. As a standard, every third pulse output circuit receives the clock signal CK1 as the clock signal CLK 3 is input, clock signal CLK4 is input as clock signal CK2, and clock signal The clock signal CLK1 is input as the signal CK3.

[0105] The clock signal CLK4 is input to the pulse output circuit 31_4 as the clock signal CK1. The clock signal CLK1 is input as the clock signal CK2, and the clock signal CK3 is input as the clock signal CK4. The clock signal CLK2 is input as a reference. The clock signal CLK4 is input as the clock signal CK1 to every third pulse output circuit. The clock signal CLK1 is input as the clock signal CK2, and the clock signal CK3 In FIG. 5A, as an example, a clock signal CLK2 is input as a pulse The clock signal CK1, the clock signal CK2, and the clock signal CK3 are input to the output circuit 31_N+2. The clock signal CK3 is input to the pulse output circuit 31_4 as the clock signal CK1, the clock The clock signals CK2 and CK3 are assumed to be the same.

[0106] Furthermore, the configurations of the pulse output circuit 31_N+1 and the pulse output circuit 31_N+2 are is a configuration of the pulse output circuit shown in FIG. 2A without the transistor 72. The pulse signal output from the pulse output circuit 31_N+1 (output signal SROUT_N+1 ) is input to the pulse output circuit 31_N-1 as a reset signal RIN. The pulse signal (output signal SROUT_N+2) output from the pulse output circuit 31_N+2 is The reset signal RIN is input to the pulse output circuit 31_N. 31_N+1 and the pulse output circuit 31_N+2 are not provided, and a pulse signal generated separately is output as a pulse The signal may be input to the pulse output circuit 31_N-1 and the pulse output circuit 31_N. The force signal OUT_N+1 and the output signal OUT_N+2 do not have to be output.

[0107] Furthermore, each of the pulse output circuits 31_1 to 31_N+2 has an initial As the initialization signal RES, the initialization signal INI_RES is input.

[0108] Next, regarding an example of a method for driving the shift register 30 shown in FIG. 5(A), the timing of FIG. 5(C) will be explained. Here, as an example, the potential VDD is a positive potential. In this example, the potential VSS is a negative potential and the potential Va is (VDD+VSS) / 2. As an example, a set signal LIN, a reset signal RIN, and a clock signal CL The high level potential of the clock signals K1 to CLK4 is the same as the potential VDD. The potential of the bell is assumed to be the same as the potential VSS. 1 to CLK4 has a duty ratio of 50%. Assume that clock signal CLK2 is delayed by 1 / 4 cycle from clock signal CLK1. Assume that clock signal CLK3 is delayed by 1 / 4 cycle from clock signal CLK2. Assume that the signal CLK4 is delayed by 1 / 4 cycle from the clock signal CLK3. , the pulse width of the start pulse signal SP is The pulse width is the same as that of CLK4. Also, each pulse output circuit is set. Before that, input the initialization signal INI_RES pulse to initialize the pulse output circuit. do.

[0109] As shown in FIG. 5(C), the shift register 30 shown in FIG. 5(A) starts at time T11. When the pulse signal SP goes high, the clock signal CLK1 goes high at time T12. Furthermore, the shift register 30 receives the clock signals CLK1 to CLK2. In accordance with the signal CLK4, the pulses of the output signals SROUT_1 to SROUT_N are sequentially Next, pulses of the output signals OUT_1 to OUT_N are output in sequence.

[0110] This concludes the description of the example of the method for driving the shift register 30 shown in FIG.

[0111] A protection circuit may be provided in the shift register 30 shown in FIG. The shift register 30 shown in FIG. 5(A) is a shift register shown in FIG. 5(A) in which an initialization signal signal INI_RES, clock signals CLK1 to CLK4, and a start pulse signal In this configuration, a protection circuit 32 is electrically connected to the wiring for inputting the signal SP.

[0112] The shift register 30 shown in FIG. 6(B) is different from the shift register 30 shown in FIG. 6(A). A protection circuit 33 is connected to the wiring for outputting the output signals OUT_1 to OUT_N. It is an electrically connected configuration.

[0113] 5A and the protection circuit 32 shown in FIG. 6A and the protection circuit 33 shown in FIG. A protection circuit 33 shown in B) may be provided.

[0114] The protection circuits 32 and 33 are connected to the wiring when a potential outside a certain range is applied. When the protection circuit 32 is turned on, the protection circuit 32 makes the wiring and another power supply line conductive. The path 33 is formed using, for example, a diode.

[0115] As shown in Figure 6, by providing a protection circuit, the shift register can be protected from electrostatic discharge. It can improve electrical resistance to overvoltage caused by electrostatic discharge (ESD).

[0116] As described with reference to FIGS. 1 to 6, in an example of the pulse output circuit according to this embodiment, In the period when the output pulse signal is at a low level, the transistor 11 is turned on. The potential of one of the source and drain of the transistor 12 is set to the clock signal This makes the potential lower than the high level. Since this can suppress the deterioration of the transistor, it is possible to suppress the deterioration of the transistor.

[0117] (Embodiment 2) In this embodiment, an example of a display device using the pulse output circuit according to the first embodiment is shown. 7 to 10.

[0118] The display device shown in FIG. 7A includes a pixel portion 201 and a driver circuit portion 202. The pixel portion 201 and the driver circuit portion 202 are arranged in a pixel array.

[0119] The pixel section 201 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driving circuit section 202 includes a gate driver 221, a source driver 222, a The device is equipped with a driver circuit such as driver 223.

[0120] The gate driver 221 includes a shift register having multiple stages of the pulse output circuits shown in the first embodiment. For example, a gate driver 221 is a pulse signal output from the shift register, and the scanning lines GL_1 to GL_ It should be noted that a plurality of gate drivers 221 are provided to control the potential of the plurality of gates. The scanning lines GL_1 to GL_X may be divided and controlled by the gate driver 221.

[0121] An image signal is input to the source driver 223. The source driver 223 receives the image signal The source driver has a function of generating a data signal to be written to the pixel circuit 211 based on the The driver 223 has a function of controlling the potentials of the data lines DL_1 to DL_Y.

[0122] The source driver 223 is configured using, for example, a plurality of analog switches. The image signal driver 223 sequentially turns on a plurality of analog switches. The signal can be output as a data signal by time-dividing the signal. In this case, the shift register may be configured as a source driver 223. A shift register having multiple stages of the pulse output circuit shown in embodiment 1 (for example, the shift register shown in FIG. 5(A)) A resistor 30 can be used.

[0123] Each of the plurality of pixel circuits 211 receives a pulse signal via one of the plurality of scanning lines GL. A data signal is input via one of the plurality of data lines DL. 1, the data of the data signal is written and held by the gate driver 221. For example, the pixel circuit 211 in the mth row and nth column is controlled by the scanning line GL_m (m is an integer less than or equal to X). A pulse signal is input from the gate driver 221 via the gate driver 221, and the potential of the scanning line GL_m is In response to the data, the source driver 223 outputs the data via the data line DL_n (n is a natural number equal to or smaller than Y). A data signal is input.

[0124] Each of the plurality of pixel circuits 211 includes, for example, a liquid crystal element 2 as shown in FIG. 30, a transistor 231_1, and a capacitive element 233_1.

[0125] The potential of one of the pair of electrodes of the liquid crystal element 230 is set appropriately according to the specifications of the pixel circuit 211. The orientation state of the liquid crystal element 230 is set by the written data. A common potential ( A common potential may be applied to the pair of liquid crystal elements 230 for each pixel circuit 211 in each row. One of the electrodes may be given a different potential.

[0126] For example, a display method of a display device having a liquid crystal element is TN (Twisted Nematic) atic) mode, IPS (In Plane Switching) mode, STN ( Super Twisted Nematic) mode, VA(Vertical Al ignment) mode, ASM (Axially Symmetric Alignment) mode d Micro-cell mode, OCB (Optically Compensated ed Birefringence mode, FLC (Ferroelectric L Liquid Crystal mode, AFLC (AntiFerroelectric) Liquid Crystal mode, MVA (Multi-Domain Ver. tical Alignment) mode, PVA(Patterned Vertic) mode al Alignment) mode, FFS (Fringe Field Switch) ing) mode or TBA (Transverse Bend Alignment) Modes etc. may also be used.

[0127] In addition, a liquid crystal element may be constructed using a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. Liquid crystals that exhibit a blue phase have a short response time of 1 msec or less and are optically isotropic. Therefore, alignment treatment is not required and viewing angle dependency is small.

[0128] In the pixel circuit 211 in the mth row and the nth column, the source and drain of the transistor 231_1 One is electrically connected to the data line DL_n, and the other is the other of the pair of electrodes of the liquid crystal element 230. The gate of the transistor 231_1 is electrically connected to the scanning line GL_m. The transistor 231_1 is electrically connected to the It has a function of controlling the writing of data of the data signal.

[0129] One of a pair of electrodes of the capacitor 233_1 is electrically connected to the potential supply line VL, and the other is The potential supply line VL is electrically connected to the other of the pair of electrodes of the liquid crystal element 230. The value of the capacitance is set appropriately according to the specifications of the pixel circuit 211. It functions as a storage capacitor that holds the data stored in it.

[0130] In a display device including the pixel circuit 211 of FIG. 7(B-1), each The pixel circuits 211 in the row are sequentially selected, and the transistors 231_1 are turned on to supply the data signal Write the data.

[0131] In the pixel circuit 211 in which the data is written, the transistor 231_1 is turned off. By repeating this process for each row, an image can be displayed.

[0132] The pixel circuit shown in FIG. 7B-2 includes a transistor 231_2 and a capacitor 233_ 2, a transistor 234, and a light-emitting element (also referred to as EL) 235.

[0133] One of the source and drain of the transistor 231_2 is electrically connected to the data line DL_n. Furthermore, the gate of the transistor 231_2 is electrically connected to the gate signal line GL_m. is connected to.

[0134] The transistor 231_2 is turned on or off to transmit the data of the data signal. It has the function of controlling the writing of data.

[0135] One of a pair of electrodes of the capacitor 233_2 is electrically connected to the power supply line VL_a, and the other is , is electrically connected to the other of the source and drain of the transistor 231_2.

[0136] The capacitor 233_2 functions as a storage capacitor for storing written data.

[0137] One of the source and drain of the transistor 234 is electrically connected to the power supply line VL_a. Furthermore, the gate of the transistor 234 is connected to the source and drain of the transistor 231_2. The other terminal is electrically connected to the other terminal.

[0138] One of the anode and the cathode of the light emitting element 235 is electrically connected to the power supply line VL_b, The other end is electrically connected to the other of the source and drain of the transistor 234 .

[0139] The light emitting element 235 may be, for example, an organic electroluminescence element. Cut.

[0140] A potential VDD is applied to one of the power supply lines VL_a and VL_b, and a potential VDD is applied to the other. , a potential VSS is applied.

[0141] In a display device including the pixel circuit 211 of FIG. 7(B-2), each The pixel circuits 211 in the row are sequentially selected, the transistors 231_2 are turned on, and the data signal Write the data.

[0142] In the pixel circuit 211 in which the data is written, the transistor 231_2 is turned off. Furthermore, the transistor 234 is turned on in response to the potential of the written data signal. The amount of current flowing between the source and drain of the light emitting element 235 is controlled, and the light emitting element 235 By repeating this process for each row, an image can be displayed.

[0143] Furthermore, the display device shown in FIG. 7A is driven in a manner that allows it to operate in a low power consumption mode. An example of the method will be described with reference to the timing chart of FIG. 2, the case where the shift register shown in Embodiment 1 is used as the gate driver 221 will be described. do.

[0144] The operation of the display device shown in FIG. 7A is divided into a normal mode and a low power consumption mode.

[0145] The operation in the normal mode will be described. At this time, as shown in the period 311 of FIG. A start pulse signal SP, a power supply voltage PWR, and clock signals CLK1 to CLK3 When CLK4 is input to the shift register, the shift register In accordance with the pulse, the pulses of the output signals SROUT_1 to SROUT_N are output in sequence. The pulses of the output signals OUT_1 to OUT_N are output in sequence. The voltage PWR is a power supply voltage consisting of potential VDD and potential VSS, and a voltage The power supply voltages are as follows:

[0146] Next, the operation when switching from normal mode to low power consumption mode will be described. As shown in period 312 of FIG. 8, the power supply voltage PWR for the shift register, the clock signal The output of clock signals CLK1 to CLK4 and the start pulse signal SP is stopped.

[0147] At this time, first, the input of the start pulse signal SP to the shift register is stopped, and then The input of the clock signals CLK1 to CLK4 is stopped in sequence, and then the power supply voltage P It is preferable to stop the input to WR. This will prevent the shift register from malfunctioning. Cut.

[0148] Power supply voltage PWR for the shift register, clock signals CLK1 to CLK 4, and when the input of the start pulse signal SP is stopped, the output signals SROUT_1 to SROUT_2 are The output of the pulses of the output signal SROUT_N stops, and the output signals OUT_1 to OUT The output of the N pulse stops, and the display device enters a low power consumption mode.

[0149] When the shift register is subsequently returned to the normal mode, as shown in the period 313 of FIG. The start pulse signal SP for the shift register, the clock signal CLK1 to the clock Then, the input of the clock signal CLK4 and the power supply voltage PWR is resumed.

[0150] At this time, first restart the input of the power supply voltage PWR to the shift register, then restart the clock The input of the signals CLK1 to CLK4 is resumed, and then the start pulse signal SP At this time, the input of the clock signals CLK1 to CLK4 is resumed. After setting the potential of the wiring to which the clock signals CLK1 to CLK It is preferable to restart the input of signal CLK4 in sequence.

[0151] A start pulse signal SP for the shift register, a clock signal CLK1 to a clock signal When the input of the CLK4 signal and the power supply voltage PWR is resumed, the shift register The pulses of the output signals SROUT_1 to SROUT_N change in accordance with the pulses of the pulse signal SP. The pulses of the output signals OUT_1 to OUT_N are output in sequence. Therefore, the display device returns to the normal mode.

[0152] The above is a description of an example of the display device.

[0153] As described with reference to FIG. 8, in an example of the display device according to the present embodiment, Therefore, for example, the operation of the driver circuit having the shift register can be stopped. By using a transistor with low off-state current as a transistor, it is possible to reduce the off-state current of some or all pixels when displaying an image. If the circuit does not need to rewrite the data signal, the driver circuit stops operating and the By increasing the interval, power consumption can be reduced.

[0154] As shown in FIG. 9, the gate driver 221 and the pixel circuit 211 (the gate signal line G A protection circuit 225 may be connected to the source driver 223 and the pixel circuit 211. A protection circuit 225 may be connected between the data signal line DL and the When a potential outside a certain range is applied to the wiring to which it is connected, the wiring is electrically connected to another power supply line. The protection circuit 225 is configured using, for example, a diode.

[0155] As shown in Figure 9, by providing a protection circuit, it is possible to protect against overvoltage caused by ESD, etc. This can improve the resistance of the display device to light.

[0156] As described with reference to FIGS. 1 to 9, in an example of the display device according to the present embodiment, A driving circuit such as a gate driver or a source driver is used by using the pulse output circuit shown in form 1. In the above-mentioned driving circuit, the stress on the transistor is small, so that the display This can improve the reliability of the system.

[0157] Furthermore, a structural example of the display device according to this embodiment will be described with reference to FIG.

[0158] The display device shown in FIG. 10(A) is a vertical electric field type liquid crystal display device.

[0159] The conductive layers 703a and 703b are provided on one surface of the substrate 700 with the insulating layer 701 sandwiched therebetween. .

[0160] The conductive layer 703a is provided in the driver circuit section 202. The conductive layer 703a is It functions as the gate of the transistor.

[0161] The conductive layer 703b is provided in the pixel portion 201. The conductive layer 703b is a transistor of the pixel circuit. It functions as a gate for the star.

[0162] The insulating layer 704 is provided on the conductive layers 703a and 703b. As a gate insulating layer for a transistor in a circuit and a transistor in a pixel circuit It has the following functions.

[0163] The semiconductor layer 705a overlaps with the conductive layer 703a with the insulating layer 704 sandwiched therebetween. a is a layer where the channel of the driver circuit transistor is formed (also called a channel formation layer), It has the function of

[0164] The semiconductor layer 705b overlaps with the conductive layer 703b with the insulating layer 704 sandwiched therebetween. The layer b functions as a channel formation layer of a transistor in a pixel circuit.

[0165] The conductive layer 706a is electrically connected to the semiconductor layer 705a. The gate electrode functions as one of the source and drain of the transistor.

[0166] The conductive layer 706b is electrically connected to the semiconductor layer 705a. The gate has a function as the other of the source and drain of the transistor.

[0167] The conductive layer 706c is electrically connected to the semiconductor layer 705b. The gate electrode functions as one of the source and drain of the transistor in the path.

[0168] The conductive layer 706d is electrically connected to the semiconductor layer 705b. The gate has a function as the other of the source and drain of the transistor.

[0169] The insulating layer 707 is formed on the semiconductor layers 705a and 705b and on the conductive layers 706a to 706c. The insulating layer 707 is provided on the conductive layer 706d. It functions as a protective insulating layer.

[0170] An insulating layer 708 is provided on the insulating layer 707. The insulating layer 708 functions as a planarizing layer. By providing the insulating layer 708, the insulating layer 708 can be insulated from the conductive layer below the insulating layer 708. The occurrence of parasitic capacitance between the layer 708 and the conductive layers above it can be suppressed.

[0171] The conductive layer 709a and the conductive layer 709b1 are provided on the insulating layer 708.

[0172] The conductive layer 709a overlaps with the semiconductor layer 705a with the insulating layer 707 and the insulating layer 708 interposed therebetween. The conductive layer 709a functions as a gate of a transistor in the driver circuit. The conductive layer 709a may function as a back gate of a transistor in the driver circuit. For example, in the case of an N-channel transistor, by applying a negative potential to the back gate, In this case, the threshold voltage of the transistor can be shifted in the positive direction. The gate may be grounded.

[0173] The conductive layer 709b1 functions as one of a pair of electrodes of a capacitor in a pixel circuit. do.

[0174] The insulating layer 710 is provided on the surface of the insulating layer 708 and on the conductive layer 709b1. By removing the portion of the edge layer 710 that will be formed over the transistors of the driving circuit, Since the hydrogen and water in the insulating layer 708 can be released to the outside, the insulating layer 708 can be The insulating layer 710 functions as a protective insulating layer. The insulating layer 710 also functions as a dielectric layer for the capacitor element of the pixel circuit.

[0175] The conductive layer 711 is provided on the insulating layer 710, and the insulating layers 707, 708, and An opening through layer 710 electrically connects to conductive layer 706d. The conductive layer 711 overlaps with the conductive layer 709b1 with the insulating layer 710 interposed therebetween. The pixel circuit includes a liquid crystal element and a capacitor element. It has the function of the other.

[0176] The coloring layer 722 is provided on a part of one surface of the substrate 720. It functions as a filter.

[0177] The insulating layer 723 is provided on one surface of the substrate 720 with the colored layer 722 sandwiched therebetween. has a function as a planarizing layer.

[0178] The conductive layer 721 is provided on one surface of the insulating layer 723. The conductive layer 721 is a layer for forming a liquid crystal layer of the pixel circuit. The conductive layer 721 functions as the other of the pair of electrodes of the element. A border layer may also be provided.

[0179] The liquid crystal layer 750 is provided between the conductive layer 711 and the conductive layer 721 using a sealant 751. In addition, the insulating layer 707 and the insulating layer 710 are not covered with the insulating layer 707 except for the portions located under the sealing material 751. You may remove it.

[0180] Furthermore, the display device shown in FIG. 10(B) is a display device of the horizontal electric field type (FFS mode). 10A, the display device has an additional conductive layer 703c and a conductive layer 70 9b1, and conductive layer 712, instead of conductive layer 711. The display device shown in FIG. 10A is different from the display device shown in FIG. 10A in that it has a liquid crystal layer 760 instead of the liquid crystal layer 750. For the same parts as those of the display device shown in FIG. 10(A), the description of the display device shown in FIG. 10(A) will be cited as appropriate.

[0181] The conductive layer 703c is provided on the insulating layer 701. At this time, the conductive layer 706d is provided on the insulating layer 701. The conductive layer 703c overlaps with the layer 704 sandwiched therebetween.

[0182] The conductive layer 709b2 is provided on the insulating layer 708. The conductive layer 709b2 is a The conductive layer 709b2 functions as one of a pair of electrodes of the liquid crystal element. The pixel circuit has a function as one of a pair of electrodes of a capacitor element of the pixel circuit.

[0183] The conductive layer 712 is provided on the insulating layer 710, and the insulating layers 707, 708, and An opening through layer 710 electrically connects to conductive layer 706d. The conductive layer 712 has a comb-tooth portion, and each of the combs of the comb-tooth portion sandwiches the insulating layer 710 between them. The conductive layer 712 overlaps with the other of the pair of electrodes of the liquid crystal element of the pixel circuit. Furthermore, the conductive layer 712 functions as a pair of electrodes included in a capacitor of a pixel circuit. It functions as the other side of the pole.

[0184] The liquid crystal layer 760 is provided on the conductive layer 711 and the conductive layer 712 by the sealing material 751. .

[0185] In addition, in FIGS. 10A and 10B, the transistor is a channel etch type transistor. However, the present invention is not limited to this, and may be applied to, for example, a channel stop type transistor. Alternatively, a top-gate transistor may be used.

[0186] Furthermore, each component of the display device shown in FIGS. 10(A) and 10(B) will be described. Each layer may have a laminated structure.

[0187] The substrates 700 and 720 may be, for example, glass substrates or plastic substrates. do.

[0188] The insulating layer 701 may be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride. Silicon oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide Layers containing materials such as aluminum or hafnium oxide can be applied.

[0189] The conductive layers 703a to 703c may be made of, for example, molybdenum, titanium, chromium, tantalum, Magnesium, silver, tungsten, aluminum, copper, neodymium, scandium, etc. A layer containing a metallic material can be applied.

[0190] The insulating layer 704 may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride. Silicon oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide A layer containing a material such as aluminum or hafnium oxide can be applied. For example, insulating layer 70 As the layer 4, a stack of a silicon nitride layer and a silicon oxynitride layer can be applied. The silicon nitride layer may be a laminate of a plurality of silicon nitride layers having different compositions. An oxide layer may be used as the edge layer 704. The oxide layer may be, for example, In:Ga For example, an oxide layer having an atomic ratio of Zn=1:3:2 can be used.

[0191] The semiconductor layer 705a and the semiconductor layer 705b may be, for example, an oxide semiconductor layer. can.

[0192] As shown in the first embodiment, the oxide semiconductor may be, for example, an In-based metal oxide, a Zn In-Zn based metal oxide, In-Ga-Zn based metal oxide, etc. are used. In addition, a part or all of the Ga contained in the In-Ga-Zn-based metal oxide can be Alternatively, a metal oxide containing other metal elements may be used. For example, the oxide semiconductor may be polycrystalline or single crystalline. The oxide semiconductor may be amorphous.

[0193] The other metal element may be, for example, a metal element that can bond with more oxygen atoms than gallium. For example, titanium, zirconium, hafnium, germanium, and tin can be used. One or more of these elements may be used. Cr, cerium, praseodymium, neodymium, samarium, europium, gadolinium, Rubium, dysprosium, holmium, erbium, thulium, ytterbium, and These metal elements can be used as stabilizers. The amount of these metal elements added is determined based on the amount of metal oxides that are semiconductors. It can bond with oxygen atoms more than gallium. By using a metal element and supplying oxygen to the metal oxide, the acid in the metal oxide can be It is possible to reduce elementary defects.

[0194] Furthermore, for example, a first oxide semiconductor layer having an atomic ratio of In:Ga:Zn=1:1:1, a second oxide semiconductor layer having an atomic ratio of n:Ga:Zn=3:1:2, and an In:Ga:Z The third oxide semiconductor layer having an atomic ratio of n=1:1:1 is stacked to form the semiconductor layer 705a and The semiconductor layer 705a and the semiconductor layer 705b may be formed by the above-described lamination. By configuring the 05b, for example, the field effect mobility of a transistor can be increased. do.

[0195] The transistor including the oxide semiconductor has a wide band gap, so it is possible to prevent leakage current due to thermal excitation. The current is small. Furthermore, the effective mass of the hole is large, more than 10, and the tunnel barrier height is 2.8 eV or more, which is high. This reduces the tunnel current. Furthermore, the carriers in the semiconductor layer Therefore, the off-state current can be reduced. For example, the off-state current at room temperature (25°C) is 1 × 10 per μm of channel width -19 A (100zA) or less. More preferably, 1 x10 -22 A (100yA) or less. The lower the off-state current of a transistor, the better. However, the lower limit of the off-state current of a transistor is approximately 1×10 -30 It is estimated to be A / μm The semiconductor layer 705a and the semiconductor layer 705b are not limited to the oxide semiconductor layer. A semiconductor layer containing an element of group 14 (such as silicon) may be used as 5b. The semiconductor layer containing silicon may be a single crystal silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer. A corn layer or the like can be used.

[0196] For example, impurities such as hydrogen or water are removed as much as possible, and oxygen is supplied to fill the oxygen vacancies as much as possible. By reducing the amount of the oxide semiconductor as much as possible, a transistor including the oxide semiconductor can be manufactured. In the channel formation region, the amount of hydrogen, known as donor impurities, is measured using secondary ion mass spectrometry. (also known as SIMS) measurement value is 1×10 19 / cm 3 Less than 1 × 10 18 / cm 3 It is preferable to reduce it to the following:

[0197] By using a highly purified oxide semiconductor layer in a field-effect transistor, The carrier density of the layer is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than , and more preferably 1 × 10 11 / cm 3 In this way, the carrier density can be reduced to less than By eliminating this, the off-state current of the field-effect transistor per 1 μm of channel width can be reduced by 1× 10 -19 A (100zA) or less, more preferably 1×10 -22 A (100yA) or less The lower the off-state current of a field-effect transistor, the better. The lower limit of the off-state current of an effect transistor is approximately 1×10 -30 A / μm do.

[0198] Note that the oxide semiconductor may be a CAAC-OS.

[0199] For example, an oxide semiconductor layer which is a CAAC-OS film can be formed by a sputtering method. At this time, sputtering is performed using a polycrystalline oxide semiconductor sputtering target. When the ions collide with the sputtering target, The crystalline region included in the target is cleaved from the ab plane, forming a flat plate with a plane parallel to the ab plane. Or, it may peel off as pellet-shaped sputtering particles. The sputtering particles reach the substrate while maintaining the The crystalline state of the target is transferred to the substrate, forming a CAAC-OS.

[0200] In addition, it is preferable to apply the following conditions to form the CAAC-OS.

[0201] For example, by forming CAAC-OS with reduced impurity concentration, the acid For example, the impurities (hydrogen, It is preferable to reduce impurities in the deposition gas (such as water, carbon dioxide, and nitrogen). For example, the film forming gas has a dew point of -80°C or less, preferably - It is preferable to use a deposition gas having a temperature of 100° C. or less.

[0202] It is also preferable to increase the substrate temperature during film formation. When the plate-shaped sputtering particles reach the substrate, the migration of the sputtering particles The sputtering occurs, and the flat surface can be turned to allow the sputtering particles to adhere to the substrate. For example, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably 200°C or higher and 500°C or lower. An oxide semiconductor film is formed at a temperature of 0.degree. C. or lower to form an oxide semiconductor layer.

[0203] In addition, the oxygen ratio in the deposition gas is increased, and the power is optimized to suppress plasma damage during deposition. For example, the oxygen ratio in the deposition gas is preferably 30% by volume or more. is preferably 100% by volume.

[0204] The conductive layers 706a to 706d can be formed of, for example, molybdenum, titanium, chromium, or titanium. Ta, magnesium, silver, tungsten, aluminum, copper, neodymium, scandium, Alternatively, a layer containing a metallic material such as ruthenium can be applied.

[0205] The insulating layer 707 may be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride. Silicon oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide Layers containing materials such as aluminum or hafnium oxide can be applied.

[0206] The insulating layer 708 may be made of, for example, an organic insulating material or an inorganic insulating material. For example, the insulating layer 708 may be made of an acrylic resin.

[0207] The conductive layer 709a, the conductive layer 709b1, and the conductive layer 709b2 may be, for example, a conductor. A layer of a metal oxide that has the function of transmitting light can be applied. For example, indium oxide Zinc oxide or indium tin oxide can be used.

[0208] For the insulating layer 710, for example, a material applicable to the insulating layer 704 can be used.

[0209] The conductive layers 711, 712, and 721 may be made of, for example, a light-transmitting metal oxide. For example, a layer of indium oxide, zinc oxide, or indium tin oxide can be applied. can be applied.

[0210] The color layer 722 transmits light having one of the colors red (R), green (G), and blue (B), for example. The coloring layer 722 may be a layer containing a dye or a pigment.

[0211] The insulating layer 723 may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride. Silicon oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide A layer containing a material such as aluminum or hafnium oxide can be applied. A layer of material that can be applied to the substrate may also be used.

[0212] The liquid crystal layer 750 may be, for example, a TN liquid crystal, an OCB liquid crystal, an STN liquid crystal, a VA liquid crystal, or an ECB type. Use of a layer containing liquid crystal, GH liquid crystal, polymer dispersed liquid crystal, discotic liquid crystal, or the like can be done.

[0213] The liquid crystal layer 760 may be, for example, a layer containing liquid crystal that exhibits a blue phase.

[0214] The layer containing the liquid crystal exhibiting a blue phase may be formed by, for example, using a liquid crystal exhibiting a blue phase, a chiral agent, a liquid crystal monomer, or the like. The blue phase is formed by a liquid crystal composition containing a non-liquid crystal monomer and a polymerization initiator. The liquid crystal shown in Fig. 1 has a short response time and is optically isotropic, so no alignment treatment is required and the viewing angle is Therefore, by using a liquid crystal that exhibits a blue phase, the operation of the liquid crystal display device can be improved. can be done faster.

[0215] The above is the description of the structural example of the display device shown in FIG.

[0216] As described with reference to FIG. 10, in an example of the display device according to the present embodiment, a pixel circuit and The driver circuit is provided on the same substrate. This allows the wiring for connecting the pixel circuit and the driver circuit to be The number of can be reduced.

[0217] (Embodiment 3) In this embodiment, an example of an electronic device including a panel using the display device of the second embodiment will be described. This will be described with reference to FIG.

[0218] The electronic device shown in FIG. 11A is an example of a portable information terminal.

[0219] The electronic device shown in FIG. 11A includes a housing 1011 and a panel 10 provided in the housing 1011. 12, a button 1013, and a speaker 1014.

[0220] The housing 1011 is provided with a connection terminal for connecting to an external device and operation buttons. It's fine.

[0221] Furthermore, the panel 1012 may be configured using the display device of the second embodiment.

[0222] Furthermore, the panel 1012 may be configured using a touch panel. The touch panel can be, for example, an optical touch panel. Touch panels, capacitive touch panels, resistive touch panels, etc. can be applied.

[0223] The button 1013 is provided on the housing 1011. For example, the button 1013 may be a power button. If so, pressing the button 1013 can control the on state of the electronic device.

[0224] The speaker 1014 is provided in the housing 1011. The speaker 1014 outputs sound. do.

[0225] A microphone may be provided in the housing 1011. By doing so, for example, the electronic device shown in FIG. 7(A) can function as a telephone. .

[0226] The electronic device shown in FIG. 11(A) is, for example, a telephone, an electronic book, a personal computer, and and functions as one or more gaming machines.

[0227] The electronic device shown in FIG. 11B is an example of a foldable information terminal.

[0228] The electronic device shown in FIG. 11B includes a housing 1021a, a housing 1021b, and a housing 1021a. a panel 1022a provided on the housing 1021b, a panel 1022b provided on the housing 1021b, and a shaft a section 1023, a button 1024, a connection terminal 1025, a recording medium insertion section 1026, and a switch. It is equipped with a speaker 1027.

[0229] The housing 1021 a and the housing 1021 b are connected by a shaft portion 1023 .

[0230] Furthermore, even if the panels 1022a and 1022b are constructed using the display device of the second embodiment, good.

[0231] Furthermore, the panels 1022a and 1022b may be configured using a touch panel. This allows touch detection on the panels 1022a and 1022b. Examples of touch panels include optical touch panels, capacitive touch panels, and resistive touch panels. Chipanel etc. can be applied.

[0232] The electronic device shown in FIG. 11B has a shaft 1023, and therefore, the panel 1022a and the panel 1022b can be folded facing each other.

[0233] The button 1024 is provided on the housing 1021b. For example, if the button 1024 is a power button, pressing the button 1024 By doing so, the on state of the electronic device can be controlled.

[0234] The connection terminal 1025 is provided on the housing 1021a. In addition, the connection terminal 1025 may be provided between the housing 1021a and the housing 1021b. A plurality of connection terminals 1025 may be provided on one or both of the terminals 21b. This is a terminal for connecting the electronic device shown in FIG. 1 to other devices.

[0235] The recording medium insertion section 1026 is provided in the housing 1021a. The recording medium insertion section 1026 may be provided in the housing 1021a. For example, a plurality of recording medium inserting portions may be provided on one or both of the housings 1021a and 1021b. By inserting a card-type recording medium into the card slot, the data on the card-type recording medium can be read by the electronic device. Data can be read from the electronic device or written to the card-type recording medium.

[0236] The speaker 1027 is provided in the housing 1021b. A speaker 1027 may be provided on the housing 1021a.

[0237] A microphone may be provided in the housing 1021a or the housing 1021b. By providing a microphone in the housing 1021b, the electronic device shown in FIG. It can function as a telephone.

[0238] The electronic device shown in FIG. 11(B) is, for example, a telephone, an electronic book, a personal computer, and and functions as one or more gaming machines.

[0239] The electronic device shown in FIG. 11C is an example of a stationary information terminal. The electronic device includes a housing 1031, a panel 1032 provided on the housing 1031, and a button 10 33 and a speaker 1034.

[0240] Furthermore, the panel 1032 may be configured using the display device of the second embodiment.

[0241] Furthermore, the panel 1032 may be configured using a touch panel. 032, touch detection can be performed. Touch panels, capacitive touch panels, resistive touch panels, etc. can be applied.

[0242] A panel similar to the panel 1032 may be provided on the deck portion 1035 of the housing 1031 .

[0243] Furthermore, the housing 1031 is provided with a ticket output section for outputting tickets, a coin insertion section, a bill insertion section, etc. It may be provided.

[0244] The button 1033 is provided on the housing 1031. For example, the button 1033 may be a power button. If present, pressing the button 1033 can control the on state of the electronic device.

[0245] The speaker 1034 is provided in the housing 1031. The speaker 1034 outputs sound. do.

[0246] The electronic device shown in FIG. 11(C) is, for example, an automatic teller machine, a machine for ordering tickets, etc. Functions as an information communication terminal (also called a multimedia station) or a gaming machine It has.

[0247] FIG. 11(D) is an example of a stationary information terminal. The electronic device shown in FIG. 11(D) is a body 1041, a panel 1042 provided on the housing 1041, and a support for supporting the housing 1041. It includes a holder 1043, a button 1044, a connection terminal 1045, and a speaker 1046. can.

[0248] The housing 1041 may be provided with a connection terminal for connecting to an external device.

[0249] Furthermore, the panel 1042 may be configured using the display device of the second embodiment.

[0250] Furthermore, the panel 1042 may be configured using a touch panel. The touch panel can detect touches on the touch panel 042. Touch panels, capacitive touch panels, resistive touch panels, etc. can be applied.

[0251] The button 1044 is provided on the housing 1041. For example, the button 1044 may be a power button. If present, pressing button 1044 can control the on state of the electronic device.

[0252] The connection terminal 1045 is provided on the housing 1041. The connection terminal 1045 is shown in FIG. For example, the connection terminal 1045 is a terminal for connecting the electronic device shown in FIG. When the electronic device shown in FIG. 11(D) is connected to a personal computer, An image corresponding to a data signal input from a computer can be displayed on the panel 1042. For example, the panel 1042 of the electronic device shown in FIG. 11(D) may be connected to the panel of another electronic device. If the screen size is larger than the other electronic device, the image displayed on the other electronic device can be enlarged, and multiple people can use the screen at the same time. Sometimes it's easier to see.

[0253] The speaker 1046 is provided in the housing 1041. The speaker 1046 outputs sound. do.

[0254] The electronic device shown in FIG. 11(D) is, for example, an output monitor, a personal computer, and a television. It functions as one or more of the vision devices.

[0255] The above is a description of the example of the electronic device shown in FIG.

[0256] As described with reference to FIG. 11, in the electronic device according to the present embodiment, the panel By providing a panel using the display device of mode 2, it is possible to provide a highly reliable electronic device. . [Explanation of symbols]

[0257] 11 Transistor 12 transistors 13 Transistor 14 Transistor 15 transistors 31 Pulse output circuit 32 Protection circuit 33 Protection circuit 61 Transistor 62 transistors 63 Transistor 64 transistors 65 transistors 66 transistors 67 Transistor 68 transistors 69 Transistor 70 transistors 71 Transistor 72 transistors 73 Transistor 74 transistors 75 transistors 76 transistors 201 Pixel section 202 Drive circuit section 211 Pixel circuit 221 Gate Driver 223 Source Driver 225 Protection circuit 230 Liquid crystal element 231_1 Transistor 231_2 Transistor 233_1 Capacitor element 233_2 Capacitor element 234 transistor 235 Light-emitting element 311 period 312 period 313 period 700 boards 701 Insulation layer 703a conductive layer 703b conductive layer 703c conductive layer 704 Insulation layer 705a Semiconductor layer 705b Semiconductor layer 706a conductive layer 706b Conductive layer 706c conductive layer 706d Conductive layer 707 Insulation Layer 708 Insulation Layer 709a conductive layer 709b1 Conductive layer 709b2 conductive layer 710 Insulation Layer 711 Conductive layer 712 Conductive layer 720 board 721 Conductive Layer 722 Colored layer 723 Insulation Layer 750 LCD layer 751 Sealing material 760 LCD layer 1011 Case 1012 Panel 1013 Button 1014 Speaker 1021a housing 1021b housing Panel 1022a 1022b Panel 1023 Shaft 1024 buttons 1025 connection terminal 1026 Recording medium insertion section 1027 Speaker 1031 Case 1032 Panel 1033 Button 1034 Speaker 1035 Deck section 1041 Housing 1042 Panel 1043 Support stand 1044 buttons 1045 connection terminal 1046 Speaker

Claims

[Claim 1] having first to sixth transistors of the same conductivity type; the first to sixth transistors each have a back gate; one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor; the other of the source and the drain of the first transistor is electrically connected to a wiring to which a clock signal is supplied; the other of the source and the drain of the second transistor is electrically connected to the one of the source and the drain of the third transistor; the other of the source and the drain of the second transistor is electrically connected to a wiring to which an output signal is output; the other of the source and the drain of the third transistor is electrically connected to a wiring to which a first potential is supplied; one of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor; the other of the source and the drain of the fourth transistor is electrically connected to a wiring to which a second potential is supplied; one of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is electrically connected to a wiring to which a third potential is supplied; a gate of the fifth transistor electrically connected to a gate of the third transistor; one of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is electrically connected to a wiring to which the first potential is supplied; a gate of the sixth transistor electrically connected to a gate of the third transistor; back gates of the first to sixth transistors are electrically connected to a wiring to which a fourth potential is supplied; When the fifth transistor is in an on state, the fourth transistor is in an off state; An output circuit in which, when the sixth transistor is in an on state, the second transistor is in an off state.

Images