Device

Abstract

To provide a matrix operation accelerator which maximizes performance and area / power efficiency.SOLUTION: A matrix operation accelerator includes first and second vector registers having a first data element width for storing source matrix data elements, a third vector register which is at least twice the first data element width for storing multiple multiply accumulate matrix data elements, and an operand routing circuit which executes a plurality of multiply operations corresponding to a single matrix instruction on a plurality of processing lanes and broadcasts first source matrix data elements to the processing lanes in accordance with the matrix instruction. The matrix operation accelerator generates a result matrix data element by accumulating different data elements in the source matrix data elements in each processing lanes.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates generally to computer processor architectures, and more particularly to apparatus, systems, and methods for executing instructions to perform matrix operations using matrix operation accelerator circuitry. [Background technology]

[0002] A processor, or set of processors, executes instructions from an instruction set, e.g., an instruction set architecture (ISA). An instruction set is a portion of a computer architecture that is relevant to programming and generally includes native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). Note that, as used herein, the term instruction may refer to macroinstructions, e.g., instructions provided to a processor for execution, or microinstructions, e.g., instructions resulting from a decoder of a processor decoding a macroinstruction. [Brief explanation of the drawings]

[0003] The present disclosure is illustrated by way of example, and not limitation, in the figures of the accompanying drawings, in which like reference symbols indicate similar elements and in which:

[0004] [Figure 1A] FIG. 1 illustrates an embodiment of a configured tile according to an embodiment of the present disclosure.

[0005] [Figure 1B] FIG. 1 illustrates an embodiment of a configured tile according to an embodiment of the present disclosure.

[0006] [Figure 2] 1A-1C illustrate several examples of matrix storage according to embodiments of the present disclosure.

[0007] [Figure 3]FIG. 1 illustrates an embodiment of a system utilizing a matrix (tile) operation accelerator in accordance with an embodiment of the present disclosure.

[0008] [Figure 4] FIG. 1 illustrates one embodiment of how memory is shared using a matrix operation accelerator. [Figure 5] FIG. 1 illustrates one embodiment of how memory is shared using a matrix operation accelerator.

[0009] [Figure 6] FIG. 1 illustrates one embodiment of a matrix multiply-accumulate operation using tiles (“TMMA”).

[0010] [Figure 7] FIG. 1 illustrates one embodiment of a subset of executions of iterations of a chained fused multiply-accumulate instruction.

[0011] [Figure 8] FIG. 1 illustrates one embodiment of a subset of executions of iterations of a chained fused multiply-accumulate instruction.

[0012] [Figure 9] FIG. 1 illustrates one embodiment of a subset of executions of iterations of a chained fused multiply-accumulate instruction.

[0013] [Figure 10] FIG. 1 illustrates one embodiment of a subset of executions of iterations of a chained fused multiply-accumulate instruction.

[0014] [Figure 11] FIG. 1 illustrates a power-of-two sized SIMD implementation in which the accumulator uses a larger input size than the input to the multiplier, according to one embodiment.

[0015] [Figure 12] FIG. 1 illustrates an embodiment of a system utilizing a matrix operation circuit.

[0016] [Figure 13] FIG. 1 illustrates one embodiment of a processor core pipeline that supports matrix operations using tiles.

[0017] [Figure 14] FIG. 1 illustrates one embodiment of a processor core pipeline that supports matrix operations using tiles.

[0018] [Figure 15] FIG. 1 illustrates an example of a matrix represented in row-major format and column-major format.

[0019] [Figure 16] FIG. 10 is a diagram illustrating an example of the use of matrices (tiles).

[0020] [Figure 17] FIG. 1 illustrates one embodiment of how matrices (tiles) are used.

[0021] [Figure 18] FIG. 1 illustrates support for configuring the use of tiles, according to one embodiment.

[0022] [Figure 19] FIG. 1 illustrates one embodiment of a description of matrices (tiles) to be supported.

[0023] [Figure 20A] FIG. 10 illustrates an example of a register. [Figure 20B] FIG. 10 illustrates an example of a register. [Figure 20C] FIG. 10 illustrates an example of a register. [Figure 20D] FIG. 10 illustrates an example of a register.

[0024] [Figure 21] FIG. 1 illustrates an embodiment of a system utilizing a matrix (tile) operation accelerator, in accordance with embodiments of the present disclosure.

[0025] [Figure 22] FIG. 2 illustrates a matrix operation accelerator circuit including a two-dimensional grid of processing element circuits, according to an embodiment of the present disclosure.

[0026] [Figure 23] FIG. 2 illustrates a dispatch circuit of a matrix operation accelerator circuit according to an embodiment of the present disclosure.

[0027] [Figure 24] FIG. 2 illustrates a scheduling circuit of a dispatch circuit of a matrix operation accelerator circuit according to an embodiment of the present disclosure.

[0028] [Figure 25] FIG. 10 illustrates a scheduling circuit of a dispatch circuit of a matrix operation accelerator circuit that is switchable from a baseline scheduling mode to a scheduling mode that reuses input matrices, according to an embodiment of the present disclosure.

[0029] [Figure 26] FIG. 2 illustrates a dispatch circuit of a matrix operation accelerator circuit for multiple paths, according to an embodiment of the present disclosure.

[0030] [Figure 27] FIG. 1 illustrates a scheduling circuit of a dispatch circuit of a matrix operation accelerator circuit for multiple paths, according to an embodiment of the present disclosure.

[0031] [Figure 28] FIG. 10 illustrates pseudocode for a matrix operation circuit according to an embodiment of the present disclosure.

[0032] [Figure 29] FIG. 1 illustrates a method for processing a matrix operation instruction according to an embodiment of the present disclosure.

[0033] [Figure 30A]FIG. 2 is a block diagram illustrating a generic vector friendly instruction format and its class A instruction templates, according to an embodiment of the present disclosure.

[0034] [Figure 30B] FIG. 2 is a block diagram illustrating a generic vector friendly instruction format and its class B instruction templates, according to an embodiment of the present disclosure.

[0035] [Figure 31A] FIG. 30C is a block diagram illustrating fields for the generic vector friendly instruction format in FIGS. 30A and 30B in accordance with an embodiment of the present disclosure.

[0036] [Figure 31B] FIG. 31B is a block diagram illustrating the fields that make up the full opcode field of the vector-specific instruction format in FIG. 31A according to one embodiment of the present disclosure.

[0037] [Figure 31C] FIG. 31B is a block diagram illustrating the fields that make up the register index field of the vector-specific instruction format in FIG. 31A in accordance with one embodiment of the present disclosure.

[0038] [Figure 31D] FIG. 31B is a block diagram illustrating the fields that make up the extended operation field 3050 of the vector-specific instruction format in FIG. 31A according to one embodiment of the present disclosure.

[0039] [Figure 32] FIG. 2 is a block diagram of a register architecture according to one embodiment of the present disclosure.

[0040] [Figure 33A] 1A-1C are block diagrams illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline, in accordance with embodiments of the present disclosure.

[0041] [Figure 33B] 1 is a block diagram illustrating both an exemplary embodiment in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor, in accordance with embodiments of the present disclosure. FIG.

[0042] [Figure 34A] 1 is a block diagram of a single processor core with its connection to an on-die interconnect network and its local subset of a level 2 (L2) cache, according to an embodiment of the present disclosure.

[0043] [Figure 34B] FIG. 34B is an expanded view of a portion of the processor core in FIG. 34A according to an embodiment of the present disclosure.

[0044] [Figure 35] 1 is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics, according to an embodiment of the present disclosure.

[0045] [Figure 36] FIG. 1 is a block diagram of a system according to one embodiment of the present disclosure.

[0046] [Figure 37] FIG. 2 is a block diagram of a more specific exemplary system according to one embodiment of the present disclosure.

[0047] [Figure 38] FIG. 2 is a block diagram of a second, more specific, exemplary system according to one embodiment of the present disclosure.

[0048] [Figure 39] FIG. 1 is a block diagram of a system on a chip (SoC) according to one embodiment of the present disclosure.

[0049] [Figure 40]1 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set, according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0050] In the following description, numerous specific details are set forth. However, it should be understood that the embodiments may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0051] References herein to "one embodiment," "embodiment," "exemplary embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but that not all embodiments necessarily include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is believed to be within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0052] Matrices can become increasingly important in many computing tasks, such as machine learning and other large-scale data processing. Deep learning is a type of machine learning algorithm. Deep learning architectures, such as deep neural networks, can be applied to fields including computer vision, speech recognition, natural language processing, voice recognition, social network filtering, machine translation, bioinformatics, and drug design.

[0053] Inference and training, two tools used in deep learning, can use low-precision arithmetic. Maximizing the throughput of deep learning algorithms and computations can help meet the needs of deep learning processors, such as those running deep learning in data centers.

[0054] Matrix-matrix multiplication (also known as GEMM or generalized matrix multiplication) is a compute-heavy operation on certain processors. Specialized hardware for matrix multiplication (e.g., GEMM) is a good option for improving the computational performance (and energy efficiency) of certain applications, such as deep learning. Some of these applications, including deep learning, can operate without loss of precision for input data elements with a relatively small number of bits, as long as the output elements have enough bits (e.g., more than the input).

[0055] On certain processors, working with matrices is difficult and / or instruction-intensive. For example, matrix rows may be placed into multiple packed data (e.g., SIMD or vector) registers and then processed individually. For example, the addition of two 8x2 (e.g., row x column) matrices may require loading and may be aggregated into four packed data registers depending on the data size. The first addition is then performed on the packed data registers corresponding to the first row of each matrix, and the second addition is performed on the packed data registers corresponding to the second row of each matrix. The resulting packed data registers are then distributed across memory. While this scenario may be acceptable for small matrices, it is often unacceptable for large matrices.

[0056] [explanation] Described herein are mechanisms for supporting matrix operations in computer hardware such as central processing units (CPUs), graphics processing units (GPUs), and accelerators. Matrix operations utilize two-dimensional (2-D) data structures that represent one or more packed regions of memory, such as registers. Throughout this description, these 2-D data structures are referred to as tiles. Note that a matrix may be smaller than a tile (using less than an entire tile) or may utilize multiple tiles (the matrix is ​​larger than the size of any tile). Throughout the description, matrix (tile) language is used to refer to operations performed using tiles that affect a matrix, and whether or not that matrix is ​​larger than any tile is generally irrelevant.

[0057] Each tile may be operated on by various operations as detailed herein, including, but not limited to, matrix (tile) multiplication, tile addition, tile subtraction, tile diagonal, tile zero, tile transform, tile dot product, tile broadcast, tile row broadcast, tile column broadcast, tile multiply, tile multiply accumulate, tile move, etc. Additionally, supporting operators such as the use of scale and / or bias may be used with these operations, and in support of future non-numeric applications, e.g., OpenCL "local memory," data compression / decompression, etc. Instructions for performing matrix operations (e.g., TILEPARTIALDOTPRODUCT) instructions are also described herein.

[0058] Portions of storage (memory (non-volatile and volatile), registers, cache, etc.) are arranged in tiles of various horizontal and vertical dimensions. For example, a tile may have a horizontal dimension of 4 (e.g., a matrix with 4 rows) and a vertical dimension of 8 (e.g., a matrix with 8 columns). Typically, the horizontal dimension is related to the element size (e.g., 2, 4, 8, 16, 32, 64, 128 bits, etc.). Multiple data types (single precision floating point, double precision floating point, integer, etc.) may be supported.

[0059] [Example of using configured tiles] In some embodiments, tile parameters are configurable. For example, a given tile may be configured to provide tile options. Example tile options include, but are not limited to, the number of rows in the tile, the number of columns in the tile, whether the tile is enabled, and whether the tile is made up of pairs of equally sized tiles.

[0060] 1A illustrates one embodiment of configured tiles. As illustrated, 4 kB of application memory 102 stores four 1 kB tiles: tile t0 (104), tile t1 (106), tile t2 (108), and tile t3 (110). In this example, the four tiles are not configured in pairs, and each has elements arranged in rows and columns. Tile t0 (104) and tile t1 (106) have K rows and N columns of 4-byte elements (e.g., single-precision data), where K equals 8 and N=32. Tile t2 (108) and tile t3 (110) have K rows and N / 2 columns of 8-byte elements (e.g., double-precision data). Because double-precision operands are twice as wide as single-precision operands, this configuration aligns with a palette providing at least four names for a total storage capacity of at least 4 kB used to provide tile options. In operation, these tiles can be loaded from and stored to memory using load and store operations. Depending on the instruction encoding scheme used, the amount of available application memory, as well as the size, number, and configuration of the available tiles, will vary.

[0061] FIG. 1B illustrates one embodiment of configured tiles. As illustrated, 4 kB application memory 122 stores two pairs of 1 kB tiles: tile t4L (124) and tile t4R (126), and the second pair is tile t5L (128) and tile t5R (130). As illustrated, these tile pairs are divided into left and right tiles. In other embodiments, the tile pairs are divided into even and odd tiles. In this example, four tiles each have elements arranged in rows and columns. Tiles t4L (124) and t4R (126) have K rows and N columns of 4-byte elements (e.g., single-precision floating-point data), where K equals 8 and N equals 32. Tiles t5L (128) and t5R (130) have K rows and N / 2 columns of 8-byte elements (e.g., double-precision floating-point data). Because double-precision operands are twice as wide as single-precision operands, this configuration is consistent with a palette providing at least two names for a total storage capacity of at least 4 kB used to provide tile options. The four tiles in FIG. 1A use four names, naming each 1 kB tile, while the two paired tiles in FIG. 1B can use two names to specify the paired tile. In some embodiments, tile instructions accept the names of the paired tiles as operands. In operation, these tiles can be loaded from and stored to memory using load and store operations. Depending on the instruction encoding scheme used, the amount of available application memory, as well as the size, number, and configuration of the available tiles, will vary.

[0062] In some embodiments, tile parameters are definable. For example, a "palette" is used to provide tile options. Exemplary options include, but are not limited to, the number of tile names, the number of bytes in a row of storage, the number of rows and columns in a tile, etc. For example, the maximum "height" (number of rows) of a tile may be defined as follows:

[0063] Maximum number of tile rows = Design memory capacity / ([Number of palette names] x [Number of bytes per row]).

[0064] This allows applications to be written in a way that uses fixed names but takes advantage of different storage sizes between implementations.

[0065] Tile configuration is performed using the tile configuration ("TILECONFIG") instruction, which defines a particular tile usage with a selected palette. This declaration includes the number of tile names to be used, the desired number of rows and columns per name (tile), and, in some embodiments, the desired data type for each tile. In some embodiments, a consistency check is performed during execution of the TILECONFIG instruction to determine that the instruction complies with the constraints of the palette entries.

[0066] [Example tile storage types] Figure 2 shows some examples of matrix storage. In (A), tiles are stored in memory. As shown, each "row" consists of four packed data elements. To obtain the next "row," a stride value is used. Note that rows may be stored contiguously in memory. Strided memory access allows access from one row to the next when the tile storage does not map to the row width of the underlying memory array.

[0067] Tiles load from and store to memory are typically strided accesses to packed rows of data from application memory. The exemplary TILELOAD and TILESTORE instructions, or other instruction references to application memory as TILE operands in load operation instructions, are restartable in some embodiments to handle (up to) 2× row page faults, unmasked floating-point exceptions, and / or per-instruction interrupts.

[0068] In (B), matrices are stored in tiles made up of multiple registers, such as packed data registers (Single Instruction Multiple Data (SIMD) registers or vector registers). In this example, the tiles are overlaid on three physical registers. Typically, contiguous registers are used, but this does not have to be the case.

[0069] In (C), matrices are stored in tiles in non-register storage accessible to fused multiply-accumulate (FMA) circuitry used in the tiled operations. This storage may be internal to the FMA or adjacent to it. Furthermore, in some embodiments described below, the storage may be for data elements rather than entire rows or tiles.

[0070] Support parameters for the TMMA architecture are reported via CPUID. In some embodiments, the list of information includes maximum height and maximum SIMD dimensions. To configure the TMMA architecture, the per-tile dimensions, per-tile element size, and palette identifier must be specified. This configuration is done by executing the TILECONFIG instruction.

[0071] Successful execution of the TILECONFIG instruction enables subsequent TILE operations. The TILERELEASEALL instruction clears the tile configuration and disables TILE operations (until the next TILECONFIG instruction is executed). In some embodiments, XSAVE, XSTORE, etc. are used in context switching that uses tiles. In some embodiments, two XCR0 bits are used in XSAVE, one bit for TILECONFIG metadata and the other bit corresponds to the actual tile payload data.

[0072] TILECONFIG not only configures tile usage, but also sets a state variable that indicates the program is in a region of code with the configured tiles. An implementation can list restrictions on other instructions that can be used with the tile region, such as not using an existing register set.

[0073] Exiting a tile region is typically done with the TILERELEASEALL command, which takes no parameters and quickly invalidates all tiles (indicating that data no longer needs to be saved or restored) and clears any internal state associated with being in the tile region.

[0074] In some embodiments, the tile operation zeros out all rows and all columns beyond the dimensions specified by the tile configuration. For example, the tile operation zeros out any data beyond the number of configured columns (given the element size) as each row is written. For example, in a tile consisting of 64-byte rows and 10 rows and 12 columns, an operation writing an FP32 element will write 12x4 bytes of output / result data to each of the first 10 rows and zero out the remaining 4x4 bytes of each row. The tile operation completely zeros out any rows after the first 10 configured rows. Using a 1K tile with 64-byte rows results in 16 rows, so the last 6 rows in this example would also be zeroed.

[0075] In some embodiments, a context restore instruction (e.g., XRSTOR) forces data beyond the rows configured for a tile to be held as zero when loading data. If there is no valid configuration, all rows are zeroed. XRSTOR of tile data may load unnecessary data into columns beyond the configured columns. Because there is no element width associated with the tile configuration, it should not be possible for XRSTOR to clear beyond the configured number of columns.

[0076] A context save (e.g., XSAVE) exposes the entire TILE storage area when writing it to memory. If XRSTOR loads unnecessary data at the right edge of a tile, that data is saved by XSAVE. XSAVE writes zeros to rows beyond the specified number per tile.

[0077] In some embodiments, tile instructions are restartable. Operations that access memory allow restart after a page fault. Computation instructions that process floating-point operations also allow unmasked floating-point exceptions, with exception masking controlled by control and / or status registers.

[0078] To support instruction restart after these events, these instructions store information in the start register, which is detailed below.

[0079] [Matrix (tile) calculation system] [Example Hardware Support] FIG. 3 illustrates one embodiment of a system utilizing a matrix (tile) operations accelerator. In this diagram, a host processor / processing system 301 communicates commands 311 (e.g., arithmetic or matrix manipulation operations, or matrix manipulation operations such as load and store operations) to a matrix operations accelerator 307. However, this is shown this way for illustrative purposes only. As will be described in more detail later, this accelerator 307 may be part of a processing core. Typically, commands 311, which are tile manipulation operator instructions, refer to tiles in register-register ("reg-reg") format or register-memory ("reg-mem") format. Other commands, such as TILESTORE, TILELOAD, and TILECONFIG, do not perform data operations on tiles. The commands may be decoded instructions (e.g., micro-ops) or macro-instructions for the accelerator 307 to process.

[0080] In this example, a coherent memory interface 303 is coupled to the host processor / processing system 301 and the matrix operation accelerator 307, so that they can share memory. FIGS. 4 and 5 illustrate different embodiments of how memory is shared using a matrix operation accelerator. As shown in FIG. 4, the host processor 401 and the matrix operation accelerator circuit 405 share the same memory 403. FIG. 5 illustrates an embodiment in which the host processor 501 and the matrix operation accelerator 505 do not share memory but can access each other's memory. For example, the processor 501 can access the tile memory 507 and also utilize its own host memory 503 as usual. Similarly, the matrix operation accelerator 505 can access the host memory 503 but more typically utilizes its own memory 507. Note that these memories may be different types of memories.

[0081] In some embodiments, tiles are supported using overlays on physical registers. For example, a tile may utilize sixteen 1024-bit registers, thirty-two 512-bit registers, etc., depending on the implementation. In some embodiments, matrix operations utilize two-dimensional (2-D) data structures that represent one or more packed regions of memory, such as registers. Throughout this description, these 2-D data structures are referred to as tiles or tile registers.

[0082] In some embodiments, the matrix operation accelerator 307 includes multiple FMAs 309 coupled to data buffers 305 (in some implementations, one or more of these data buffers 305 are stored in a grid of FMAs as shown). The data buffers 305 buffer tiles loaded from memory (e.g., using a tile load instruction or a tile store instruction) and / or tiles to be stored in memory. The data buffers may be, for example, multiple registers. Typically, these FMAs are arranged as a grid 309 of chained FMAs that can read and write tiles. In this example, the matrix operation accelerator 307 performs a matrix multiplication operation using tiles T0, T1, and T2. The FMA grid 309 accommodates at least one of these tiles. In some embodiments, all tiles involved in the operation are stored in the FMA grid 309. In other embodiments, only a subset is stored in the FMA grid 309. As shown, T1 is accommodated, and T0 and T2 are not. Note that A, B, and C refer to the matrix of these tiles, which may or may not occupy the entire space of the tile.

[0083] FIG. 6 illustrates one embodiment of a matrix multiply-accumulate operation using tiles (“TMMA”).

[0084] In a particular embodiment, the number of rows in the matrix (tile A 601) corresponds to the number of serial (chained) FMAs, including the computational latency. One implementation freely recycles on a lower height grid, but the computation remains the same.

[0085] The source / destination vectors come from a tile with N rows (tile C 605), and the FMA's grid 611 performs N vector-matrix operations resulting in a complete instruction that performs the matrix multiplication for the tile. Tile B 603 is another vector source, feeding the FMA with "broadcast" terms at each stage.

[0086] In operation, in some embodiments, the elements of matrix B (stored in tile B 603) are spread across a rectangular grid of FMAs. Matrix B (stored in tile A 601) has its row elements transformed to match the column dimensions of the rectangular grid of FMAs. At each FMA in the grid, the elements of A and B are multiplied and added to the incoming summand (from the top of the figure), and the output sum is passed to the next row (or final output) of the FMA.

[0087] The latency of a single stage is proportional to K (the row height of matrix B), and a dependent TMMA typically has enough source-destination rows (within a single tile or across tiles) to hide that latency. An implementation may also divide the SIMD (packed data element) dimension M (the row height of matrix A) across time stages, but this simply changes the constant by which K is multiplied. When a program specifies K smaller than the maximum enumerated by the TMMA, an implementation is free to implement this with "masking" or "early out".

[0088] The overall latency of TMMA is proportional to N x K. The repeat rate is proportional to N. The number of MACs per TMMA instruction is N x K x M.

[0089] 7 illustrates one embodiment of a subset of the execution of an iteration of a chained-fused multiply-accumulate instruction. Specifically, this diagram illustrates the execution circuitry for iterations of one packed data element position in the destination. In this embodiment, the chained-fused multiply-accumulate is operating on a signed source, and the accumulator is twice the input data size.

[0090] The first signed source (Source 1 (701)) and the second signed source (Source 2 (703)) each have four packed data elements. Each of these packed data elements stores signed data, such as floating-point data. The third signed source (Source 3 (709)) has two packed data elements, each of which stores signed data. The size of the first and second signed sources 701 and 703 is half the size of the third signed source (initial value or previous result) 709. For example, the first and second signed sources 701 and 703 could have 32-bit packed data elements (e.g., single-precision floating-point), and the third signed source 709 could have 64-bit packed data elements (e.g., double-precision floating-point).

[0091] In this figure, only the two most significant packed data element positions of the first and second signed sources 701 and 703, and the most significant packed data element position of the third signed source 709, are shown. Of course, other packed data element positions would also be processed.

[0092] As shown, packed data elements are processed in pairs. For example, data in the most significant packed data element positions of the first and second signed sources 701 and 703 are multiplied using multiplier circuit 705, and data from the second most significant packed data element positions of the first and second signed sources 701 and 703 are multiplied using multiplier circuit 707. In some embodiments, these multiplier circuits 705 and 707 are reused for other packed data element positions. In other embodiments, additional multiplier circuits are used so that packed data elements are processed in parallel. In some contexts, the parallel execution is performed using lanes that are the size of the third signed source 709. The results of each multiplication are added using adder circuit 711.

[0093] The result of the addition of the results of the multiplication is added (using a different adder 713 or the same adder 711) to the data from the most significant packed data element position of signed source 3 (709).

[0094] Finally, the result of the second addition is stored in signed destination 715 at a packed data element location corresponding to the packed data element location used from third signed source 709, or passed to the next iteration, if any. In some embodiments, a write mask (bit) is applied to this storage such that if the corresponding write mask is set, a store occurs, and if not, no store occurs.

[0095] 8 illustrates one embodiment of a subset of the execution of an iteration of a chained-fused multiply-accumulate instruction. Specifically, this diagram illustrates the execution circuitry for iterations of one packed data element position in the destination. In this embodiment, the chained-fused multiply-accumulate is operating on a signed source, and the accumulator is twice the input data size.

[0096] The first signed source (Source 1 (801)) and the second signed source (Source 2 (803)) each have four packed data elements. Each of these packed data elements stores signed data, such as integer data. The third signed source (Source 3 (809)) has two packed data elements, each of which stores signed data. The size of the first and second signed sources 801 and 803 is half the size of the third signed source 809. For example, the first and second signed sources 801 and 803 may have 32-bit packed data elements (e.g., single-precision floating point), and the third signed source 809 may have 64-bit packed data elements (e.g., double-precision floating point).

[0097] This diagram shows only the two most significant packed data element positions of the first and second signed sources 801 and 803, and the most significant packed data element position of the third signed source 809. Of course, other packed data element positions would also be processed.

[0098] As shown, packed data elements are processed in pairs. For example, data in the most significant packed data element positions of the first and second signed sources 801 and 803 are multiplied using multiplier circuit 805, and data from the second most significant packed data element positions of the first and second signed sources 801 and 803 are multiplied using multiplier circuit 807. In some embodiments, these multiplier circuits 805 and 807 are reused for other packed data element positions. In other embodiments, additional multiplier circuits are used so that packed data elements are processed in parallel. In some contexts, parallel execution is performed using lanes that are the size of the third signed source (initial value or previous iteration result) 809. The result of each multiplication is added to the third signed source 809 using add / saturate circuit 813.

[0099] The add / saturate (accumulator) circuit 813 preserves the signs of the operands when addition results in a value that is too large. Specifically, saturation evaluation is performed on the infinite precision result between the multiway addition and the write to the destination or the next iteration. When the accumulator 813 is floating point and the input terms are integers, the sum of products and floating point accumulator input values ​​are converted to infinite precision values ​​(fixed point numbers of several hundred bits) and an addition of the multiplication result and the third input is performed, with one rounding to the actual accumulator type.

[0100] Unsigned saturation means that the output value is restricted to the maximum unsigned number (all ones) for the element width. Signed saturation means that the value is restricted to be in the range between the most negative and most positive number for the element width (e.g., for bytes, the range is -128 (=-2^7) to 127 (=2^7-1)).

[0101] The result of the addition and saturation check is stored in signed result 815 at a packed data element location corresponding to the packed data element location used from third signed source 809, or passed to the next iteration, if any. In some embodiments, a write mask (bit) is applied to this storage such that if the corresponding write mask is set, a save occurs, and if not set, no save occurs.

[0102] 9 illustrates one embodiment of a subset of the execution of an iteration of a chained-fused multiply-accumulate instruction. Specifically, this diagram illustrates the execution circuitry for iterations of one packed data element location in the destination. In this embodiment, the chained-fused multiply-accumulate operates on signed and unsigned sources, and the accumulator is four times the input data size.

[0103] The first signed source (Source 1 (901)) and the second unsigned source (Source 2 (903)) each have four packed data elements. Each of these packed data elements has data, such as floating-point data or integer data. The third signed source (Initial Value or Result 915) has packed data elements that store signed data. The first and second signed sources 901 and 903 are one-quarter the size of the third signed source 915. For example, the first and second sources 901 and 903 may have 16-bit packed data elements (e.g., words), and the third signed source 915 may have 64-bit packed data elements (e.g., double-precision floating-point or 64-bit integers).

[0104] This diagram shows the four most significant packed data element positions of the first and second sources 901 and 903, as well as the most significant packed data element position of the third signed source 915. Of course, other packed data element positions, if any, would also be processed.

[0105] As shown, packed data elements are processed in quadruplets. For example, data in the most significant packed data element positions of the first and second sources 901 and 903 are multiplied using multiplier circuit 905, data from the second most significant packed data element positions of the first and second sources 901 and 903 is multiplied using multiplier circuit 907, data from the third most significant packed data element positions of the first and second sources 901 and 903 is multiplied using multiplier circuit 909, and data from the least significant packed data element positions of the first and second sources 901 and 903 is multiplied using multiplier circuit 911. In some embodiments, signed packed data elements of the first source 901 are sign-extended and unsigned packed data elements of the second source 903 are zero-extended prior to multiplication.

[0106] In some embodiments, these multiplier circuits 905-911 are reused for other packed data element positions. In other embodiments, additional multiplier circuits are used so that packed data elements are processed in parallel. In some contexts, parallel execution is performed using lanes that are the size of the third signed source 915. The results of each multiplication are added using adder circuit 913.

[0107] The result of the addition of the multiplication results is added (using a different adder 917 or the same adder 913) to the data from the most significant packed data element position of signed source 3 (915).

[0108] Finally, the result 919 of the second addition is stored in the signed destination at the packed data element location corresponding to the packed data element location used from the third signed source 915, or passed to the next iteration. In some embodiments, a write mask (bit) is applied to this storage such that if the corresponding write mask is set, a store occurs, and if not, no store occurs.

[0109] 10 illustrates one embodiment of a subset of the execution of an iteration of a chained-fused multiply-accumulate instruction. Specifically, this diagram illustrates the execution circuitry for iterations of one packed data element location in the destination. In this embodiment, the chained-fused multiply-accumulate operates on signed and unsigned sources, and the accumulator is four times the input data size.

[0110] The first signed source 1001 and the second unsigned source 1003 each have four packed data elements. Each of these packed data elements stores data such as floating-point data or integer data. The third signed source 1015 (initial value or previous result) has packed data elements that store signed data. The size of the first and second sources is one-quarter of the size of the third signed source 1015 (initial value or previous result). For example, the first and second sources may have 16-bit packed data elements (e.g., words), and the third signed source 1015 (initial value or previous result) may have 64-bit packed data elements (e.g., double-precision floating-point or 64-bit integer).

[0111] This diagram shows the four most significant packed data element positions of a first signed source 1001 and a second unsigned source 1003, as well as the most significant packed data element position of a third signed source 1015. Of course, other packed data element positions, if any, would also be processed.

[0112] As shown, packed data elements are processed in quadruplets. For example, data in the most significant packed data element positions of the first signed source 1001 and the second unsigned source 1003 are multiplied using multiplier circuit 1005, data from the second most significant packed data element positions of the first signed source 1001 and the second unsigned source 1003 are multiplied using multiplier circuit 1007, data from the third most significant packed data element positions of the first signed source 1001 and the second unsigned source 1003 are multiplied using multiplier circuit 1009, and data from the least significant packed data element positions of the first signed source 1001 and the second unsigned source 1003 are multiplied using multiplier circuit 1011. In some embodiments, the signed packed data elements of the first signed source 1001 are sign-extended and the unsigned packed data elements of the second unsigned source 1003 are zero-extended prior to multiplication.

[0113] In some embodiments, these multiplier circuits 1005-1011 are reused for other packed data element positions. In other embodiments, additional multiplier circuits are used so that packed data elements are processed in parallel. In some contexts, parallel execution is performed using lanes that are the size of the third signed source 1015 (initial value or previous result). The result of the addition of the multiplication results is added to the data from the most significant packed data element position of the third signed source 1015 (initial value or previous result) using an adder / saturator 1013 circuit.

[0114] The add / saturate (accumulator) circuit 1013 preserves the signs of the operands when the addition results in a value that is too large or too small for signed saturation. Specifically, saturation evaluation is performed on the infinite precision result between the multiway addition and the write to the destination. When the accumulator 1013 is floating point and the input terms are integers, the sum of products and floating point accumulator input values ​​are converted to infinite precision values ​​(fixed point numbers of several hundred bits) and an addition of the multiplication result and a third input is performed, with one rounding to the actual accumulator type.

[0115] The result 1019 of the addition and saturation check is stored in the signed destination at a packed data element location corresponding to the packed data element location used from the third signed source 1015 (initial value or previous result) or passed to the next iteration. In some embodiments, a write mask (bit) is applied to this storage such that if the corresponding write mask is set, a store occurs, and if not set, no store occurs.

[0116] Figure 11 illustrates a power-of-two sized SIMD implementation in which the accumulator uses a larger input size than the input to the multiplier, according to one embodiment. Note that the source value (to the multiplier) and the accumulator value can be signed or unsigned. For an accumulator with double input size (in other words, the accumulator input value is twice the size of the source's packed data element size), table 1101 shows various configurations. For a byte-sized source, the accumulator uses a word or half-precision floating-point (HPFP) value that is 16 bits in size. For a word-sized source, the accumulator uses a 32-bit integer or single-precision floating-point (SPFP) value that is 32 bits in size. For a SPFP or 32-bit integer sized source, the accumulator uses a 64-bit integer or double-precision floating-point (DPFP) value that is 64 bits in size.

[0117] For accumulators with four times the input size (in other words, the accumulator input value is four times the size of the source's packed data element size), table 1103 shows various configurations. For byte-sized sources, the accumulator uses 32-bit integer or single-precision floating-point (SPFP) values ​​that are 32 bits in size. For word-sized sources, in some embodiments, the accumulator uses 64-bit integer or double-precision floating-point (DPFP) values ​​that are 64 bits in size.

[0118] For an accumulator with an 8x input size (in other words, where the accumulator input values ​​are 8 times the size of the source's packed data element size), table 1105 shows one configuration: For a byte-sized source, the accumulator uses 64-bit integers.

[0119] As alluded to above, the matrix operation circuitry may be included in the core or may be an external accelerator. Figure 12 illustrates one embodiment of a system utilizing matrix operation circuitry. In this diagram, multiple entities are coupled with a ring interconnect 1245.

[0120] Multiple cores, namely core 0 (1201), core 1 (1203), core 2 (1205), and core N (1207), provide non-tile-based instruction support. In some embodiments, matrix operation circuitry 1251 is provided within core 1203, while in other embodiments, matrix operation circuitry 1211 and 1213 are accessible over ring interconnect 1245.

[0121] Furthermore, one or more memory controllers 1223-1225 are provided to communicate with the memories 1233 and 1231 in place of the core and / or matrix operation circuitry.

[0122] FIG. 13 illustrates one embodiment of a processor core pipeline that supports matrix operations using tiles. A branch prediction and decode circuit 1303 performs instruction branch prediction, instruction decoding, and / or both from instructions stored in instruction storage 1301. For example, instructions detailed herein may be stored in the instruction storage. In some implementations, a separate circuit is used for branch prediction, and in some embodiments, at least some instructions are decoded into one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals using microcode 1305. The branch prediction and decode circuit 1303 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc.

[0123] The branch prediction and decode circuit 1303, in some embodiments, is coupled to an allocate / rename 1307 circuit, which is coupled to a scheduler circuit 1309. In some embodiments, these circuits provide register renaming, register allocation, and / or scheduling functionality by performing one or more of: 1) renaming logical operand values ​​to physical operand values ​​(e.g., in some embodiments, a register alias table), 2) assigning status bits and flags to decoded instructions, and 3) scheduling decoded instructions from an instruction pool for execution on execution circuitry (e.g., in some embodiments using a reservation station).

[0124] Scheduler circuit 1309 represents any number of various schedulers, including reservation stations, central instruction windows, etc. Scheduler circuit 1309 is coupled to or includes physical register files 1315. Each of physical register files 1315 represents one or more physical register files, the different files storing one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), tiles, etc. In one embodiment, physical register file 1315 comprises vector register circuitry, write mask register circuitry, and scalar register circuitry. These register circuits can provide architectural vector registers, vector mask registers, and general-purpose registers. The physical register file 1315 is overlapped with the retirement circuitry 1317 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using a reorder buffer and retirement register file, using a future file, a history buffer, and a retirement register file, using a register map and a pool of registers, etc.). The retirement circuitry 1317 and the physical register file 1315 are coupled to the execution circuitry 1311.

[0125] While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may also be used in in-order architectures. The illustrated processor embodiment may also include separate instruction and data cache units and a shared L2 cache unit, although alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and / or processor. Alternatively, all of the cache may be external to the core and / or processor.

[0126] Execution circuitry 1311 is a set of one or more execution circuits, including scalar circuitry 1321, vector / SIMD circuitry 1323, and matrix operation circuitry 1327, as well as memory access circuitry 1325 for accessing cache 1313. The execution circuits perform various operations (e.g., shift, add, subtract, multiply) on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). Some embodiments may include multiple execution units dedicated to a particular function or set of functions, while other embodiments may include only one execution unit or multiple execution units that all perform all functions. Scalar circuitry 1321 performs scalar operations, vector / SIMD circuitry 1323 performs vector / SIMD operations, and matrix operation circuitry 1327 performs matrix (tiled) operations as detailed herein.

[0127] By way of example, an exemplary register renaming, out-of-order issue / execution core architecture may implement a pipeline as follows: 1) The instruction fetch circuit performs the fetch and length decode stages; 2) The branch and decode circuit 1303 performs the decode stage; 3) The allocate / rename 1307 circuit performs the allocate and rename stages; 4) The scheduler circuit 1309 performs the schedule stage; 5) The physical register file and memory unit (coupled to or included in the scheduler circuit 1309 and the allocate / rename 1307 circuit) perform the register read / memory read stage, and the execution circuit 1311 performs the execute stage; 6) The memory unit and physical register file unit perform the writeback / memory write stage; 7) Various units may be involved in the exception handling stage; and 8) The retirement unit and physical register file unit perform the commit stage.

[0128] The core may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions), the MIPS instruction set from MIPS Technologies of Sunnyvale, California, the ARM instruction set (with optional additional extensions such as NEON) from ARM Holdings of Sunnyvale, California), including the instructions described herein. In one embodiment, core 1390 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), which allows operations used by many multimedia applications to be performed using packed data.

[0129] It will be appreciated that a core may support multithreading (execution of two or more parallel sets of operations or threads) in a variety of ways, including time-slice multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that the physical core is simultaneously multithreading), or a combination thereof (e.g., time-slice fetch and decode followed by simultaneous multithreading, such as in Intel® Hyper-Threading Technology).

[0130] FIG. 14 illustrates one embodiment of a processor core pipeline that supports matrix operations using tiles. Branch prediction and decode circuitry 1403 performs instruction branch prediction, instruction decoding, and / or both from instructions stored in instruction storage 1401. For example, the instructions detailed herein may be stored in the instruction storage. In some implementations, a separate circuit is used for branch prediction, and in some embodiments, at least some instructions are decoded into one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals using microcode 1405. Branch prediction and decode circuitry 1403 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc.

[0131] The branch prediction and decode circuitry 1403, in some embodiments, is coupled to an allocate / rename circuitry 1407, which is coupled to a scheduler circuitry 1409. In some embodiments, these circuits provide register renaming, register allocation, and / or scheduling functionality by performing one or more of: 1) renaming logical operand values ​​to physical operand values ​​(e.g., in some embodiments, a register alias table), 2) assigning status bits and flags to decoded instructions, and 3) scheduling decoded instructions from an instruction pool for execution on execution circuitry (e.g., in some embodiments using a reservation station).

[0132] The scheduler circuit 1409 represents any number of various schedulers, including reservation stations, central instruction windows, etc. The scheduler circuit 1409 of the scheduler unit is coupled to or includes physical register files 1415. Each of the physical register files 1415 represents one or more physical register files, with the different files storing one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), tiles, etc. In one embodiment, the physical register file 1415 comprises vector register circuitry, write mask register circuitry, and scalar register circuitry. These register circuits can provide architectural vector registers, vector mask registers, and general-purpose registers. The physical register file 1415 is overlaid with the retirement circuitry 1417 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using a reorder buffer and retirement register file, using a future file, a history buffer, and a retirement register file, using a register map and a pool of registers, etc.). The retirement circuitry 1417 and the physical register file 1415 are coupled to the execution circuitry 1411.

[0133] While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may also be used in in-order architectures. The illustrated processor embodiment may also include separate instruction and data cache units and a shared L2 cache unit, although alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and / or processor. Alternatively, all of the cache may be external to the core and / or processor.

[0134] The execution circuitry 1411 includes a set of one or more execution circuits 1427 and a set of one or more memory access circuits 1425 for accessing the cache 1413. The execution circuits 1427 perform the matrix (tile) operations detailed herein.

[0135] By way of example, an exemplary register renaming, out-of-order issue / execution core architecture may implement a pipeline as follows: 1) The instruction fetch circuit performs the fetch and length decode stages; 2) The branch and decode circuit 1403 performs the decode stage; 3) The allocate / rename 1407 circuit performs the allocate and rename stages; 4) The scheduler circuit 1409 performs the schedule stage; 5) The physical register file and memory unit (coupled to or included in the scheduler circuit 1409 and the relocate / rename 1407 circuit) perform the register read / memory read stage, and the execution circuit 1411 performs the execute stage; 6) The memory unit and physical register file unit perform the writeback / memory write stage; 7) Various units may be involved in the exception handling stage; and 8) The retirement unit and physical register file unit perform the commit stage.

[0136] The core may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions), the MIPS instruction set from MIPS Technologies of Sunnyvale, California, or the ARM instruction set (with optional additional extensions such as NEON) from ARM Holdings of Sunnyvale, California), including the instructions described herein. In one embodiment, core 1490 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), which allows operations used by many multimedia applications to be performed using packed data.

[0137] It will be appreciated that a core may support multithreading (execution of two or more parallel sets of operations or threads) in a variety of ways, including time-slice multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that the physical core is simultaneously multithreading), or a combination thereof (e.g., time-slice fetch and decode followed by simultaneous multithreading, such as in Intel® Hyper-Threading Technology).

[0138] Layout Throughout this description, data will be represented using a row-major data layout. Column-major users should interpret the terms according to their orientation. Figure 15 shows an example of a matrix represented in row-major and column-major formats. As shown, matrix A is a 2x3 matrix. When this matrix is ​​stored in row-major format, the data elements in the rows are contiguous. When this matrix is ​​stored in column-major format, the data elements in the columns are contiguous. A T ×B T =(BA) T is a well-known property of matrices, and the superscript T denotes a transformation. If we read the column-major data as row-major data, the matrix looks like a transformation matrix.

[0139] In some embodiments, row-major semantics is utilized in hardware, and column-major data is swapped with the operand order resulting in a result that is a transform of the matrix, but for a subsequent column-major read from memory it is the correct untransformed matrix.

[0140] For example, if there are two column-major matrices to be multiplied,

number

[0141] The input matrix should be stored in linear memory (column-major) as follows:

number

[0142] If we read those matrices row-major with dimensions 2x3 and 3x2, they should look like this:

number

[0143] Exchange order and matrix multiplication.

number

[0144] After the transformation matrix is ​​output, it can be stored in row-major order.

number

[0145] Used in subsequent column-major calculations, it is the correct untransformed matrix.

number

[0146] [Illustrative Use] Figure 16 shows an example of matrix (tile) usage. In this example, matrix C 1601 contains two tiles, matrix A 1603 contains one tile, and matrix B 1605 contains two tiles. This figure shows an example of the inner loop of an algorithm that computes matrix multiplication. In this example, two result tiles tmm0 and tmm1 from matrix C 1601 are used to accumulate intermediate results. One tile (tmm2) from matrix A 1603 is reused twice, as it is multiplied with two tiles from matrix B 1605. Pointers load a new A matrix (tile) and two new B matrices (tiles) from the directions indicated by the arrows. An outer loop, not shown, adjusts the pointers for the C tiles.

[0147] The illustrated example code includes the use of tile configuration instructions, which are executed to configure tile usage, load tiles, perform a loop to process tiles, store tiles in memory, and free tile usage.

[0148] Figure 17 illustrates one embodiment of matrix (tile) usage. At 1701, tile usage is configured. For example, a TILECONFIG instruction is executed to configure tile usage, including setting the number of rows and columns per tile. Typically, at least one matrix (tile) is loaded from memory at 1703. At least one matrix (tile) operation is performed using the matrix (tile) at 1705. At least one matrix (tile) is stored to memory at 1707, and a context switch can occur at 1709.

[0149] [Example Configuration] [Tile Configuration Hardware Support] As mentioned above, tile usage typically needs to be configured before use. For example, it may not be necessary to fully use all rows and columns. In some embodiments, not configuring these rows and columns not only saves power, but the configuration may also be used to determine whether an operation will generate an error. For example, a matrix multiplication of the form (N×M)×(L×N) typically will not work if M and L are not the same.

[0150] Before using tiles to use matrices, in some embodiments, tile support should be configured. For example, the number of rows and columns per tile, the tiles to be used, etc. The TILECONFIG instruction is an improvement to the computer itself, as it provides support for configuring the computer to use a matrix accelerator (either as part of a processor core or as an external device). Specifically, executing the TILECONFIG instruction retrieves configuration from memory and applies it to the matrix (tile) settings within the matrix accelerator.

[0151] [Tile Usage Configuration] Figure 18 shows support for configuring the use of tiles, according to one embodiment. Memory 1801 contains tile descriptions 1803 of the matrices (tiles) to be supported.

[0152] The instruction execution resources 1811 of the processor / core 1805 store aspects of the tile description 1803 in a tile configuration 1817. The tile configuration 1817 includes a palette table 1813 to detail which tiles for the palette are configured (the number of rows and columns in each tile) and marking that matrix support is in use. Specifically, the instruction execution resources 1811 are configured to use the tiles specified by the tile configuration 1817. The instruction execution resources 1811 may also include machine-specific or configuration registers to indicate tile usage. Further values, such as in-use and starting values, are also set. The tile configuration 1817 utilizes registers 1819 to store tile usage and configuration information.

[0153] Figure 19 shows one embodiment of a description of the matrices (tiles) to be supported. This is the description to be stored when the STTILECFG instruction is executed. In this example, each field is one byte. Byte [0] stores the palette ID 1901. The palette ID is used to index, by palette ID, into a palette table 1813 which stores the number of bytes in the tile and the number of bytes per row for the tile associated with this ID as defined by the configuration.

[0154] Byte 1 stores the value to be stored in the "startRow" register 1903, and byte 2 stores the value to be stored in the register that is startP 1905. These instructions store information in these registers to support instruction restart after these events. Instructions store information in these registers to support instruction restart after break events, such as those detailed above. The startRow value indicates the row to be used for restart. The startP value indicates the location within the row for the store operation when a pair is used, and in some embodiments indicates the bottom half of the row (in the lower tile of the pair) or the top half of the row (in the upper tile of the pair). Typically, the row (column) location is not necessary.

[0155] With the exception of TILECONFIG and STTILECFG, successful execution of a matrix (tile) instruction sets both startRow and startP to zero.

[0156] Whenever an interrupted matrix (tile) instruction is not resumed, it is the software's responsibility to zero the startRow and startP values. For example, an unmasked floating-point exception handler may decide to terminate operations in software and change the program counter value to another instruction, usually the next instruction. In this case, the software exception handler must zero the startRow and startP values ​​in the exception presented to it by the operating system before resuming the program. The operating system then reloads those values ​​using the restore instruction.

[0157] Byte 3 stores an indication 1907 of the tile pair (1b per tile).

[0158] Bytes 16-17 store the number of rows 1913 and columns 1915 for tile 0, bytes 18-19 store the number of rows and columns for tile 1, etc. In other words, each two-byte group specifies the number of rows and columns for a tile. If two-byte groups are not used to specify tile parameters, they should have the value zero. Specifying tile parameters for more tiles than the implementation or palette limits results in a failure. Unconfigured tiles are set to an initial state of 0 rows and 0 columns.

[0159] Finally, the in-memory construct typically ends with a trailing representation, such as several consecutive bytes of all zeros.

[0160] [Example Tile and Tile Configuration Storage] 20A-20D show examples of registers 1819. FIG. 20A shows multiple registers 1819. As shown, each tile (TMM0 2001...TMMN 2003) has a separate register, with each register storing the row and column size for that particular tile. StartP 2011 and StartRow 2013 are stored in separate registers. One or more status registers 2015 are set to indicate that a tile is configured for use (e.g., TILES_CONFIGURED=1).

[0161] 20B shows multiple registers 1819. As shown, each tile has separate registers for its rows and columns. For example, TMM0 Row Configuration 2021, TMM0 Column Configuration 2023, StartP 2011, and StartRow 2013 are stored in separate registers. One or more status registers 2015 are set to indicate that the tile is configured for use (e.g., TILES_CONFIGURED=1).

[0162] Figure 20C shows a single register 1819. As shown, this register stores the tile configuration (rows and columns per tile) 2031, StartP 2011, and StartRow 2013 stored in a single register as a packed data register. One or more status registers 2015 are set to indicate that the tiles are configured for use (e.g., TILES_CONFIGURED=1).

[0163] Figure 20D shows multiple registers 1819. As shown, a single register stores the tile configuration (rows and columns per tile) 2031. StartP and StartRow are stored in separate registers 2011 and 2013. One or more status registers 2015 are set to indicate that the tiles are configured for use (e.g., TILES_CONFIGURED=1).

[0164] Where the starting registers are shown separately, other combinations are envisioned, such as combining them into a single register.

[0165] Scheduling for Systolic Arrays As mentioned above, hardware for generalized matrix multiplication (also known as GEMM) is a good option for improving the computational peaks (and energy efficiency) of certain applications, such as deep learning. The computationally intensive requirements of deep neural network (DNN)-based applications can lead to the use of hardware (e.g., accelerators) that employ a large number (e.g., hundreds) of processing elements, such as fused multiply-accumulate (FMA) circuits. However, (e.g., DNN) accelerators can be optimized for the highly regular data flow pattern of dense matrix multiplication. In certain embodiments, the accelerator uses a systolic array implementation to maximize performance and area / power efficiency. The systolic array may include a dense two-dimensional array optimized for the highly regular data flow.

[0166] In particular hardware, decoding and executing the instruction causes configurable systolic array hardware (e.g., a matrix operation accelerator circuit) to compute C=A×B+C, where A, B, and C are each two-dimensional matrices. For each element of C, the hardware computes the dot product of one row of the input matrix A with one column of matrix B.

[0167] In a particular embodiment, the matrix operations accelerator circuit takes as inputs matrix A (of type M×K, where M and K are integers), matrix B (of type K×N, where M and K are integers), and matrix C (of type M×N, where M and N are integers), and then performs an operation (e.g., a fused multiply-accumulate) on each element to generate a result that is stored in a matrix (e.g., converted back into matrix C of type M×N, where M and N are integers). In one embodiment, M, K, and N are 16 or less. In a particular embodiment, the matrix operations accelerator circuit performs the following operations (e.g., on floating-point numbers):

number

[0168] FIG. 21 illustrates one embodiment of a system utilizing a matrix (tile) operations accelerator 2107 according to embodiments of the present disclosure. In a particular embodiment, a host processor / processing system 2101 (e.g., a hardware processor core, e.g., processor core 3390 in FIG. 33B ) communicates commands (e.g., matrix operation operations such as arithmetic or matrix operation operations, load operations, and / or store operations) to the matrix operations accelerator 2107. However, this is shown so for illustrative purposes only. As detailed herein, the accelerator 2107 may be part of a processing core. Commands that are tile operation operator instructions may reference tiles in register-register (“reg-reg”) format or register-memory (“reg-mem”) format. In a particular embodiment, other commands, such as TILESTORE, TILELOAD, and TILECONFIG, do not perform data operations on tiles. The commands may be decoded instructions (e.g., micro-ops) or macro-instructions for the accelerator 2107 to process. In one embodiment, the hardware processor core sends micro-ops to the matrix (tile) operation accelerator 2107 in response to a matrix operation instruction being executed by the hardware processor core.

[0169] In one embodiment, a reservation station (RS) circuit 2111 sends commands (e.g., micro-ops) to the matrix operations accelerator 2107. In a particular embodiment, the matrix operations accelerator 2107 is a tile matrix unit (TMU). In a particular embodiment, the matrix operations accelerator 2107 includes a matrix accelerator controller circuit 2113. In one embodiment, the matrix accelerator controller (e.g., circuit 2113) controls the manipulation and flow of data into, out of, and / or within the matrix operations accelerator 2107. The matrix operations accelerator 2107 (e.g., matrix accelerator controller circuit 2113) may include a dispatch circuit 2115 to control the dispatching of requests (e.g., commands) received from, for example, the host processor / processing system 2101 to one or more components of the matrix operations accelerator 2107. An example of a dispatch circuit is described below with reference to FIG. 23.

[0170] The illustrated matrix operations accelerator 2107 comprises a data buffer (e.g., registers) 2105. In a particular embodiment, the data buffer (e.g., registers) 2105 is configurable to store each matrix in a first plurality of registers (e.g., tiles) representing, for example, a first two-dimensional matrix (e.g., a tile marked as T0 in storage 2105 that stores matrix A), a second two-dimensional matrix (e.g., a tile marked as T1 in storage 2105 that stores matrix B), a third two-dimensional matrix (e.g., a tile marked as T3 in storage 2105 that stores matrix C), etc. The system (e.g., host processor / processing system 2101) may comprise a (e.g., coherent) memory interface 2103 (e.g., a data cache unit) to transmit and receive data (e.g., as opposed to commands) between the host processor / processing system 2101 (e.g., an out-of-order (OoO) core) and the matrix operations accelerator 2107.

[0171] In a particular embodiment, the matrix operation accelerator 2107 performs operations using a grid of processing elements 2109 (e.g., fused multiply-accumulate (FMA) circuits). In one embodiment, the dispatch circuit 2115 controls the transmission of data (e.g., one or more values ​​from a tile) from the data buffer 2105 (e.g., registers forming a tile) to the grid of processing elements 2109 (e.g., a grid of FMA circuits). In a particular embodiment, the grid of processing elements 2109 is a two-dimensional grid of processing elements, e.g., the two-dimensional grid of processing element circuitry 2200 in FIG. 22.

[0172] 22 illustrates one embodiment of a matrix operation accelerator circuit 2200 including a two-dimensional grid of processing element circuits 2206-1 through 2206-4. In a particular embodiment, data storage 2205 (e.g., a register file) comprises a plurality of registers, e.g., having respective sets of registers (e.g., tiles) representing a first input two-dimensional matrix (A), a second input two-dimensional matrix (B), and a third input two-dimensional matrix (C), and result storage. In one embodiment, the output two-dimensional matrix results are stored in registers forming the third input two-dimensional matrix (C), e.g., overwritten after the values ​​of input two-dimensional matrix (C) are utilized by the matrix operation accelerator circuit 2200. The illustrated matrix operation accelerator circuit 2200 comprises a plurality of routing / buffer circuits 2204-1 through 2204-4 for routing and storing input values ​​(e.g., from matrix A and matrix B) to the processing elements according to the operation to be performed.

[0173] It should be noted that diagrams herein may not show all data communication couplings (e.g., connections). Those skilled in the art will understand that this is done so as not to obscure certain details within the diagrams. Note that a double-headed arrow in a diagram may not require two-way communication; for example, a double-headed arrow may indicate one-way communication (e.g., to or from the component or device). Combinations of any or all of the communication paths may be used in certain embodiments herein. A single line may include multiple paths within it, e.g., multiple channels. For example, line 2210 may include multiple paths (e.g., “X” paths, where X is any positive integer), e.g., one path for values ​​from matrix A and one path for values ​​from matrix B.

[0174] In particular embodiments, upon a request to perform an operation (e.g., by decoding and executing an instruction that results in the operation), matrix operation accelerator circuit 2200 sends values ​​from matrix A and matrix B to respective routing circuits. For example, the operation may be to multiply matrix A by matrix B and then add each result to a corresponding value from matrix C. In one embodiment, first routing circuit 2204-1 receives a first value A[0][0] (the value from row index 0 and column index 0) from matrix A[row][column] and broadcasts that value to each processing element 2206-1 in that row to a first input of each of the processing elements 2206-1, receives a set of values ​​from the first row of matrix B, and sends those values ​​to a second input of each of the processing elements 2206-1 (e.g., so that processing element 2212 receives the value from B[0][0], processing element 2214 receives the value from B[0][1], etc.). In one embodiment, processing element 2212 provides the result of the multiplication of A[0][0]×B[0][0] at output 2216, and processing element 2214 provides the result of the multiplication of A[0][0]×B[0][1] at output 2218. The outputs (e.g., outputs 2216 and 2218) are sent to routing / buffer circuit 2 (2204-2).

[0175] In one embodiment, the second routing / buffer circuit 2204-2 receives a second value A[0][1] (the value from row index 0 and column index 1) from matrix A[row][column] and broadcasts that value to each first input of processing element 2206-2 for each processing element 2206-2 in that row, receives a set of values ​​from a second row of matrix B and sends those values ​​to each second input of each processing element 2206-2 (e.g., so that processing element 2222 receives a value from B[1][0], processing element 2224 receives a value from B[1][1], etc.), and receives each output from the output of processing element 2206-1 in the row above. In one embodiment, processing element 2222 provides the result of the A[0][1]×B[1][0] multiplication at output 2226, added to output 2216 (A[0][0]×B[0][0]), and processing element 2224 provides the result of the A[0][1]×B[1][1] multiplication at output 2228, added to output 2218 (A[0][0]×B[0][1]). In particular embodiments, this fused multiply-accumulate operation continues through each row of processing elements 2206-3 through 2206-4 to generate output 2230 and output 2232 from processing element 2206-4. Note that four is one example of the number of rows of processing elements (e.g., and the rows and columns of matrices A, B, and C, respectively), and that any number of rows may be present. Upon reaching the end of a row of processing elements for matrix operations accelerator circuit 2200, bias adder circuit 2208 adds each element from matrix C from input 2234 (e.g., a set of parallel input ports) (e.g., each element from the first row of matrix C) and stores the result in each element of matrix C (e.g., in each element position of the first row of matrix C) via output 2236 (e.g., a set of parallel output ports). For example, the first element from the first row of matrix C is added to the result from output 2230 and the result is stored back in the first element position of the first row of matrix C, and the second element from the first row of matrix C is added to the result from output 2232 and the result is stored back in the second element position of the first row of matrix C. This can be repeated for each row of matrix A to produce a full multiplication of matrix A by matrix B (e.g., and adding a bias from matrix C to each result).

[0176] Thus, particular embodiments of the circuit use, for example, a two-dimensional (2D) array of processing elements (PEs) (e.g., FMA units) along with several input and output buffers and local control logic circuits. In one embodiment, each PE gets some of its inputs from a data store, such as a register file, and other inputs from other PEs, with the bottom-of-the-row PE sending its output back to the data store. Thus, in these embodiments, the PEs form a pipeline. A user may generally intend to perform a series of operations on a large set of data elements (e.g., more data elements than PEs). To do so, elements may input at the top of the array to start the pipeline and incrementally move data down the pipeline (providing additional inputs at various stages of the pipeline, if appropriate).

[0177] In one embodiment, each instance of a processing element is a fused multiply-accumulate (FMA) circuit comprising a multiplier circuit (e.g., taking a first input a, a second input b, and generating a result output) and an adder circuit (e.g., adding the result output from the multiplier circuit as a first input with a third input c and generating a result). Control of the dispatch of operations and / or data to the two-dimensional grid of processing element circuits (e.g., FMA circuits) may be performed by a dispatch circuit.

[0178] FIG. 23 illustrates a dispatch circuit 2300 of a matrix operations accelerator circuit according to an embodiment of the present disclosure. In one embodiment, the dispatch circuit 2300 is part of the dispatch circuit 2115 in FIG. 21. In a particular embodiment, the dispatch circuit 2300 selects one of a number of pending operations (e.g., micro operations (micro-ops)) using a multiplexer 2302 and sends the selected operation at output 2304 to an operation circuit (e.g., the FMA grid 2109 in FIG. 21 or the PE circuit in FIG. 22). In FIG. 23, pending operations are received at input 2306 into a queue 2308. The input 2306 may be from a reservation station (e.g., the RS circuit 2111 in FIG. 21).

[0179] In one embodiment, the dispatch circuitry receives operation requests (e.g., one for each instruction or one for each set of micro-ops for a single instruction) from the out-of-order reservation station circuitry and executes the operations sequentially, assuming that, for example, two consecutive operations (e.g., instructions) can be executed one after the other in the matrix operation accelerator circuitry (e.g., its pipeline) without dependency constraints (e.g., where dependencies between consecutive matrix operations are handled by a dispatch queue, while the out-of-order circuitry handles dependencies between the matrix operations and the A and B tiles). In one embodiment, the RS circuitry dispatches the next operation (e.g., a micro-op (μop)) to the matrix operation accelerator circuitry after the dependencies are resolved. The queue 2308 as shown has eight slots, although it should be understood that a single slot or any number of slots may be used.

[0180] In particular embodiments, entries in queue 2308 store information to identify operations to be performed by utilized input tiles and / or output tiles and / or grids (e.g., FMA grid 2109 in FIG. 21 ) in a data buffer (e.g., data buffer 2105 or data buffer 2205). In one embodiment, each entry in queue 2308 stores a value (or an indicator of the value) of a valid bit (v), an operation (e.g., μop) opcode, tile dimensions (e.g., M, K, N), a control (e.g., a zero control), and a tile ID value (e.g., the values ​​of the A, B, and C tile locations in the data buffer). The main head may be a pointer to the start of the current operation dispatched to the matrix operations accelerator circuit (e.g., the first micro-op of multiple micro-ops for a single instruction). The main tail may be a pointer to the end of the current operation dispatched to the matrix operations accelerator circuit (e.g., the last micro-op of multiple micro-ops for a single instruction). The valid bit (v) may be used, for example, to mark an operation (e.g., a micro-op) as completed when the operations required for that operation have been completed by the matrix operation accelerator circuitry.

[0181] In particular embodiments, the scheduling circuit 2310 is included to select an operation (e.g., a head of multiple micro-operations) and send it to an operation circuit (e.g., the FMA grid 2109 in FIG. 21 or the PE circuit in FIG. 22) to, for example, initiate an operation for the selected operation.

[0182] 24 illustrates a scheduling circuit 2400 of a dispatch circuit of a matrix operation accelerator circuit according to an embodiment of the present disclosure. As described above, the operations (e.g., micro operations) may be:

number

[0183] Optionally, an override dispatch control unit 2410 may be used, for example, to assert zero in a mode that does not override the dispatch of operations, and to assert one (thus causing zero to be output from output 2402) in a mode that overrides the dispatch of operations.

[0184] In one embodiment, the trigger for selecting the next operation (e.g., micro-op) to be executed by the matrix operation accelerator circuit (e.g., the operation circuit (e.g., the FMA grid 2109 in FIG. 21 or the PE circuit in FIG. 22)) is given by MAX{4,M,K}, where M is the number of rows in the A matrix, K is the number of columns in the A matrix (or the number of rows in the B matrix), and 4 is a lower bound on the number of cycles of execution (e.g., of a micro-op). Note that in particular embodiments, the scheduling circuit waits at least K cycles (e.g., allows fetching of only one B row per cycle) (e.g., if there is only one bus for loading B tiles into the operation circuit (e.g., the FMA grid 2109 in FIG. 21 or the PE circuit in FIG. 22)). In particular of these embodiments, K sets the number of accumulations, which is the number of rows in the B matrix; therefore, the B-bus is occupied for the next K cycles, and no new micro-ops can be dispatched during this time. In certain of these embodiments, M sets the number of cycles that a row of the A matrix will use the A-bus, e.g., so that the next micro-op can be dispatched only after both the M counter and the K counter have been zeroed. Also, a minimum number of cycles (e.g., four) between successive dispatches may be desirable, e.g., where the C matrix is ​​read in cycle 1, accumulated with the multiplication result (e.g., A×B) in cycle 2, written back to the data buffer in cycle 3, and one more cycle before it can be read again in cycle 4. This assumes that the above steps occur in a single cycle. In other embodiments, the steps may take more than one cycle each.

[0185] In particular embodiments, when an operation (e.g., a micro operation) is selected and / or dispatched to an operation circuit (e.g., FMA grid 2109 in FIG. 21 or PE circuit in FIG. 22) for execution, the scheduling circuit 2400 clears a valid bit in the corresponding queue (e.g., queue 2308 in FIG. 23) and / or updates its head pointer in the corresponding queue (e.g., queue 2308 in FIG. 23) (e.g., to make the next operation available for selection decision).

[0186] 25 illustrates a scheduling circuit 2500 of a dispatch circuit of a matrix operation accelerator circuit that is switchable from a baseline scheduling mode to a scheduling mode that reuses input matrices, according to an embodiment of the present disclosure. The input matrices in these embodiments refer to input "B" matrices (e.g., tiles), but this is merely exemplary and other matrices (e.g., tiles) may be scheduled similarly.

[0187] The scheduling circuit 2500 comprises an input 2502 that receives a value that identifies the next operation (e.g., a micro-op) to be executed in the matrix operation accelerator circuit, specifically the next operation to be selected and / or dispatched to an operation circuit (e.g., the FMA grid 2109 in FIG. 21 or the PE circuit in FIG. 22) for execution. In one embodiment, the input 2502 receives the output 2304 from FIG. 23.

[0188] In particular embodiments, input 2502 identifies the next operation (e.g., and corresponding input / output tile) to be dispatched by scheduling circuit 2500. In particular of these embodiments, input 2502 includes an identification (ID) value representing a tile (e.g., a set of registers forming a tile in data buffer (e.g., register) 2105 in FIG. 21). Scheduling circuit 2500 includes storage 2504 that identifies the current tile being processed by the matrix operation accelerator circuit; specifically, storage 2504 may identify the current tile whose data has been loaded into (or is being loaded from / to) the operation circuit (e.g., FMA grid 2109 in FIG. 21 or buffer circuit in FIG. 22). In one embodiment, scheduling circuit 2500 includes storage 2506 of a valid tile (e.g., tile B) to indicate whether the identification value in storage 2504 is a valid value or an invalid value (e.g., the hardware is loading a different tile, and therefore a different identification value).

[0189] The scheduling circuit 2500 includes a comparison circuit 2508 for comparing (i) the current tile (e.g., Tile B) being loaded into the computation circuit (e.g., FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22) with (ii) the next tile (e.g., Next Tile B) to be loaded into the computation circuit (e.g., FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22). In one embodiment, this comparison is performed by comparing an identification value provided by the scheduling circuit for each tile, e.g., an identification value provided upon the tile's entry into a data buffer (e.g., data buffer 2105 in FIG. 21) of the matrix computation accelerator, e.g., where the identification value is provided to each tile before the tile's value is input into the computation circuit (e.g., FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22).

[0190] In a particular embodiment, comparison circuit 2508 compares (i) the input tile (e.g., its ID value in data buffer 2105 in FIG. 21) from input 2502 for the next operation (e.g., “new tile B”) with (ii) the current tile (e.g., tile B) currently loaded into the operation circuit (e.g., currently loaded into FMA grid 2109 in FIG. 21 or buffer circuit in FIG. 22), e.g., the ID value in data buffer 2105 in FIG. 21 for the tile currently loaded into FMA grid 2109 in FIG. 21. In one embodiment, comparison circuit 2508 compares the ID value of the current tile in use with the ID value of the next tile to be used in the operation circuit, and, if they are equal, asserts a value (e.g., 1) indicating that they are equal. In one embodiment, the comparison circuit 2508 compares the ID value of the current tile in use from storage 2504 with the ID value of the next tile to be used in the calculation circuit, and if they are equal, asserts a value (e.g., 1) indicating they are equal if storage 2506 also indicates that the identification value in storage 2504 is a valid value, for example, or asserts a different value (e.g., zero) if they are not.

[0191] In particular embodiments, if (i) the current tile (e.g., tile B) being loaded into the calculation circuit (e.g., into the FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22) is equal to (ii) the next tile (e.g., next tile B) to be loaded into the calculation circuit (e.g., the FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22), then a same tile (e.g., same tile B) value (e.g., 1) is asserted to cause a switch (e.g., via output 2510) to a scheduling mode that reuses the input matrix, e.g., reuses tile B already stored within the calculation circuit (e.g., in the FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22), e.g., without reloading from a data buffer (e.g., data buffer 2105 in FIG. 21) separate from the calculation circuit.

[0192] In particular embodiments, the comparison circuit 2508 outputs a first value (e.g., 1) at output 2510 if (i) the current tile (e.g., Tile B) being loaded into the operation circuit (e.g., FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22) is equal to (ii) the next tile (e.g., Next Tile B) to be loaded into the operation circuit. The output 2510 may then be input to a NOT logic gate 2512, whose output and the output of the K counter 2516 to an AND logic gate 2514 (e.g., which has an output of 1 only if all inputs are 1) may be input to an OR logic gate 2522.

[0193] In a particular embodiment, the scheduling circuit 2500 includes a K counter 2516 that asserts a value of 1 for K while counting down the number of cycles that a resource (e.g., a bus) is occupied to load the B-tile into the matrix operation accelerator circuit, and then asserts a value of 0 upon completion (e.g., when the counter K reaches a predetermined value), and a K counter 2516 that asserts a value of 1 for M while counting down the number of cycles that a resource (e.g., a bus) is occupied to load the A-tile into the matrix operation accelerator circuit, and then asserts a value of 0 upon completion (e.g., when the counter K reaches a predetermined value). , a predetermined value in counter M), and a minimum cycles counter 2520 that counts down the minimum number of cycles between dispatches of operations (e.g., micro operations) to output 2526 (e.g., a dispatch is a 1 asserted on output 2526), ​​asserting a value of 1 while counting down the minimum number of cycles, and then asserting zero when complete (e.g., 4 cycles as an example, but any single or multiple cycles may be selected). In one embodiment, OR logic gate 2522 asserts 1 if either of its inputs is 1, and NOT logic gate 2524 inverts the output of OR logic gate 2522. As an example, each counter counts down to a trigger threshold (e.g., zero) (thus AND logic gate 2514 outputs a zero when K counter 2516 asserts a zero) and then asserts a zero to its respective line to OR logic gate 2522 (e.g., until a dispatch occurs to 2526), ​​so that NOT logic gate 2524 outputs a one if (i) counters 2516, 2518, and 2520 all assert zero, or (ii) output 2510 is one in agreement with counters 2518 and 2520 asserting zero. After each dispatch, the counters may be reset to their original (e.g., non-zero) values ​​(e.g., set by the dimensions of the A and B tiles).In one embodiment, when the K counter 2516, the M counter 2518, and the minimum cycle counter 2520 assert zero to the OR logic gate 2528 on their respective lines, the OR logic gate 2528 outputs zero to the NOT logic gate 2530, which then outputs a one (rather than a zero) as a reset, causing the storage 2506 of a valid tile (e.g., tile B) to indicate that the identification value in storage 2504 is an invalid value (e.g., the hardware is loading another tile into the arithmetic circuitry).

[0194] Optionally, an override dispatch control 2532 may be used, for example, to assert zero in a mode that does not override the dispatch of operations, and to assert one in a mode that overrides the dispatch of operations (thus not outputting zero from output 2526).

[0195] As described above, the scheduling circuitry may select between (i) a first (e.g., throughput-efficient) scheduling mode that reuses input matrices, e.g., reusing tiles already stored in the computation circuitry (e.g., in the FMA grid 2109 in FIG. 21 or the buffer circuitry in FIG. 22), for example, without reloading from a data buffer separate from the computation circuitry (e.g., data buffer 2105 in FIG. 21), and (ii) a second scheduling mode that does not reuse tiles already stored in the computation circuitry.

[0196] In one embodiment, the trigger for selecting the next operation (e.g., micro-op) to be executed by the matrix operation accelerator circuit (e.g., the operation circuit (e.g., FMA grid 2109 in FIG. 21 or the PE circuit in FIG. 22)) is given by (i) MAX{4,M} in the first (e.g., throughput-efficient) scheduling mode, and (ii) MAX{4,M,K} in the second scheduling mode, where M is the number of rows of the A matrix, K is the number of columns of the A matrix, and 4 is a lower bound on the number of cycles of execution (e.g., of a micro-op). Note that in a particular embodiment, the scheduling circuit waits at least K cycles (e.g., allowing for the fetching of only one B row per cycle) (e.g., when there is only one bus for loading B tiles into the operation circuit (e.g., FMA grid 2109 in FIG. 21 or the PE circuit in FIG. 22)). In certain of these embodiments, K sets the number of accumulations, which is the number of rows in the B matrix; therefore, the B-bus is occupied for the next K cycles, and no new micro-ops can be dispatched during this time. In certain of these embodiments, M sets the number of cycles that a row of the A matrix will use the A-bus, e.g., so that the next micro-op can only be dispatched after both the M counter and the K counter are zeroed. Also, a minimum number of cycles (e.g., four) between successive dispatches may be desirable, e.g., where the C-matrix is ​​read in cycle 1, accumulated with the multiplication result (e.g., A×B) in cycle 2, written back to the data buffer in cycle 3, and there is one more cycle before it can be read again in cycle 4. This assumes that the above steps occur in a single cycle. In other embodiments, the steps may each take more than one cycle. In certain embodiments, tile B is the B matrix in the following:

number

number

[0197] In a particular embodiment, in performing matrix operations on M, K, and N, the transfer of the B matrix occurs over K (e.g., up to 16) cycles (e.g., B-transition period), and during the B-transition period, the next operation (e.g.,

number

[0198] In particular embodiments, when data from a data buffer (e.g., data buffer 2105 in FIG. 21) is stored in the operation circuitry (e.g., in FMA grid 2109 in FIG. 21 or buffer circuitry in FIG. 22), the data buffer may be reclaimed, e.g., deallocated from use, and then reallocated to store a matrix (e.g., a new tile B) for a different operation (e.g., a different instruction). In particular embodiments, reclamation, when in a first (e.g., throughput-efficient) scheduling mode, reuses input matrices, e.g., reuses tiles already stored in the operation circuitry (e.g., in FMA grid 2109 in FIG. 21 or buffer circuitry in FIG. 22).

[0199] In one embodiment, in a first (e.g., throughput-efficient) scheduling mode that reuses input matrices, the scheduling circuit prevents reclamation of a buffer (e.g., a buffer for matrix B in the arithmetic circuit) between execution of a previous operation (e.g., a single instruction) and a next operation (e.g., a single instruction), and / or in a second scheduling mode that does not reuse input matrices, the scheduling circuit enables reclamation of a buffer (e.g., a buffer for matrix B in the arithmetic circuit) between execution of a previous operation (e.g., a single instruction) and a next operation (e.g., a single instruction). In one embodiment, in the second scheduling mode that does not reuse input matrices, the scheduling circuit initiates reclamation of a buffer (e.g., a buffer for matrix B in the arithmetic circuit) between execution of a previous operation (e.g., an instruction) and a next operation (e.g., an instruction). The matrix operation accelerator circuit (e.g., a controller circuit) may assign an identification value to each of a plurality of registers representing the input two-dimensional matrix, and the check whether the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores an immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix may be performed by comparing the identification values ​​of the corresponding input two-dimensional matrices from the previous operation (e.g., instruction) and the next operation (e.g., instruction). The matrix operation accelerator circuit (e.g., a controller circuit) may assign the same ID value to matrices having the same values. The matrix operation accelerator circuit (e.g., a controller circuit) may assign different ID values ​​to matrices having different values. For example, a first operation (e.g., an instruction) may have a first value assigned to the input two-dimensional matrix, and a second operation (e.g., an instruction) may be assigned the same value if the input two-dimensional matrix is ​​the same as that in the first operation, or a different value if the input two-dimensional matrix is ​​different.

[0200] In particular embodiments, when an operation (e.g., a micro-op) is selected and / or dispatched to an operation circuit (e.g., the FMA grid 2109 in FIG. 21 or the PE circuit in FIG. 22) for execution, the scheduling circuit 2500 clears a valid bit in the corresponding queue (e.g., the queue 2308 in FIG. 23) and / or updates its head pointer in the corresponding queue (e.g., the queue 2308 in FIG. 23) (e.g., to make the next operation available for selection decision). In one embodiment, reuse of B-buffer data is only possible if the operation of loading a B value into the B-buffer is still ongoing when a second operation with a "potential for reuse" arrives. At this time, the second operation is checked for continuity with the first operation, such that the second operation uses the reused value only if continuity with the first operation is found. For example, if the first operation using the to-be-reused B value has not completed, the B buffer cannot be reclaimed and can therefore be used by the second operation (e.g., as long as there is continuity).

[0201] In particular embodiments, the first (e.g., throughput-efficient) scheduling mode that reuses input matrices is used to enhance the performance of (e.g., floating-point) FP matrix operation accelerator circuits. It should be understood that the scheduling disclosed herein is not limited to matrix operation accelerator circuit designs and is extendable to other variable latency microarchitectures with inheritance restrictions. Furthermore, the scheduling disclosed herein is extendable to cases where the FMA circuit assumes one-cycle latency.

[0202] In particular embodiments, the matrix may have dimensions larger than the available hardware (e.g., the computation circuitry (e.g., FMA grid 2109 in FIG. 21 or PE circuitry in FIG. 22). Certain embodiments herein utilize multiple (e.g., three) counters for scheduling (e.g., dispatching of operations (e.g., micro-ops)), i.e., K to address unit limitations.even , K. odd , and M c And B K×N and a mechanism for checking for matrix reuse. Additionally, certain embodiments herein implement a secondary queue for processing operations (e.g., micro-ops) where, for example, a dimension (e.g., K) is larger than the available hardware (e.g., K>8), where these operations (e.g., micro-ops) are dispatched with high priority for a second round in the computation circuitry (e.g., FMA grid 2109 in FIG. 21 or PE circuitry in FIG. 22).

[0203] In one embodiment, the scheduling circuit schedules the first row B0∈B for M cycles. K×N and the matrix A M×K, and broadcasts each of the M elements in the first column of the FMA grid. In a particular embodiment, after one or more cycles (e.g., two cycles), the next FMA array (e.g., row or column) of the FMA grid is occupied for M cycles to compute the second partial FMA operation. In a particular embodiment, this sequential pipelining mode is performed until K partial FMA operations have been computed through the K FMA arrays. In one embodiment, FMA grid utilization is limited by three major limitations: (1) the number of rows in the destination, (2) the bandwidth of the B-bus (e.g., 512 bits per cycle), and (3) the number of FMA arrays (e.g., rows or columns). As an example of (1), if M<a given value (e.g., 16), after M cycles, the first FMA array is available and free, so after M cycles the next operation (e.g., micro-op) can be sent for execution. For example, if M=12, the first FMA array is used during the first 12 cycles. However, the first result of the destination WB is calculated in 16 cycles, which means that in this example, the next operation (e.g., a micro-op) can be dispatched before the first operation (e.g., a micro-op) is completed. As an example of (2), the FMA grid can perform a single B K×N In one embodiment, the adders of the FMA circuit have a given number (e.g., two) cycle latency, meaning that they are required to transmit up to a B-Bus threshold (e.g., 512 bits) once every two cycles. Thus, particular embodiments perform two operations (e.g., micro-ops) simultaneously, keeping the B-Bus busy every cycle. Additionally, particular embodiments store B-Bus data in a buffer for reuse across successive instructions. K×NIt holds the rows of a matrix. As an example of (3), an FMA grid architecture supports up to a given number (e.g., 16) of partial product sums (e.g., K≦16), while the FMA grid contains fewer than a given number (e.g., 8) of FMA arrays (e.g., rows or columns). If K≦8, the result is ready after 16 cycles, but if K>8, an alternative solution is needed.

[0204] 26 illustrates a dispatch circuit 2600 of a matrix operation accelerator circuit for multiple paths according to an embodiment of the present disclosure. The dispatch circuit 2600 includes two queues: a main queue 2610 and a second path queue 2612. In one embodiment, the main queue 2610 holds information important for the execution of operations in an operation circuit (e.g., the FMA grid 2109 in FIG. 21 or the PE circuit in FIG. 22).

[0205] In one embodiment, the second path queue 2612 holds operations (e.g., micro-ops) (e.g., K>8) that are eligible for the second pass in the operation circuit (e.g., FMA grid 2109 in FIG. 21 or PE circuit in FIG. 22) and addresses (3) above. In one embodiment, all operations (e.g., micro-ops) inserted into the second path queue 2612 are held for 16 cycles before being dispatched again to the second path. In embodiments where the operation circuit (e.g., FMA grid 2109 in FIG. 21 or PE circuit in FIG. 22) is limited to a smaller number of FMA circuits (e.g., 8), a second pass is required. The second pass can resume after at least 16 cycles (e.g., 16 cycles = 8 FMA units × 2-cycle ADD latency). Note that this division is possible by the following, which also shows the terms calculated in the first and second paths:

number

[0206] In one embodiment, when dispatching an operation (e.g., a micro op) from the main queue 2610 (e.g., as an instance of the dispatch circuit 2300), its number of accumulations is verified (e.g., K > 8 is checked). In a particular embodiment, if (K < a threshold (e.g., 8)), the operation (e.g., the micro op) is sent directly to the operation circuit (e.g., the FMA grid 2109 in FIG. 21 or the PE circuit in FIG. 22), for example, without being copied to the second pass queue 2612; and / or if (K > a threshold (e.g., 8)), the operation (e.g., the micro op) continues to send the operation to the operation circuit (e.g., the FMA grid 2109 in FIG. 21 or the PE circuit in FIG. 22), for example, while also being copied to the second pass queue 2612. In one embodiment, in the second pass queue 2612, K is updated to be the remainder of the accumulations to be performed (e.g., K - 8). In one embodiment, every operation (e.g., micro op) inserted into the second path queue 2612 triggers a (e.g., 16) cycle counter. In one embodiment, when the counter completes a count (e.g., 16 cycles), its corresponding operation (e.g., micro op) is eligible to be sent to the operation circuitry (e.g., FMA grid 2109 in FIG. 21 or PE circuitry in FIG. 22) for the second execution portion. In one embodiment, operations (e.g., micro ops) in the second path queue 2612 are older and therefore have priority for dispatch when ready. The following can be used for queue selection:

number

[0207] 27 illustrates a scheduling circuit 2700 of a dispatch circuit of a matrix operation accelerator circuit for multiple passes, according to an embodiment of the present disclosure. The input matrices in these embodiments refer to input "B" matrices (e.g., tiles), but this is merely exemplary and other matrices (e.g., tiles) may be scheduled similarly.

[0208] The scheduling circuit 2700 comprises an input 2702 that receives a value that identifies the next operation (e.g., a micro-op) to be executed in the matrix operations accelerator circuit, specifically the next operation to be selected and / or dispatched to an operations circuit (e.g., the FMA grid 2109 in FIG. 21 or the PE circuit in FIG. 22) for execution. In one embodiment, the input 2702 receives the output 2304 from FIG. 23.

[0209] In particular embodiments, input 2702 identifies the next operation (e.g., and corresponding input / output tile) to be dispatched by scheduling circuit 2700. In particular of these embodiments, input 2702 includes an identification (ID) value representing a tile (e.g., a set of registers forming a tile in data buffer (e.g., register) 2105 in FIG. 21). Scheduling circuit 2700 includes storage 2704 that identifies the current tile being processed by the matrix operation accelerator circuit; specifically, storage 2704 may identify the current tile whose data has been loaded into (or is being loaded from / to) the operation circuit (e.g., FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22). In one embodiment, scheduling circuit 2700 includes storage 2706 of a valid tile (e.g., tile B) to indicate whether the identification value in storage 2704 is a valid value or an invalid value (e.g., the hardware is loading a different tile, and therefore a different identification value).

[0210] The scheduling circuit 2700 includes a comparison circuit 2708 for comparing (i) the current tile (e.g., Tile B) being loaded into the computation circuit (e.g., FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22) with (ii) the next tile (e.g., Next Tile B) to be loaded into the computation circuit (e.g., FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22). In one embodiment, this comparison is performed by comparing an identification value provided by the scheduling circuit for each tile, e.g., an identification value provided upon the tile's entry into a data buffer (e.g., data buffer 2105 in FIG. 21) of the matrix computation accelerator, e.g., where the identification value is provided to each tile before the tile's value is input into the computation circuit (e.g., FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22).

[0211] In a particular embodiment, comparison circuit 2708 compares (i) the input tile (e.g., its ID value in data buffer 2105 in FIG. 21) from input 2702 for the next operation (e.g., “new tile B”) with (ii) the current tile (e.g., tile B) currently loaded into the operation circuit (e.g., currently loaded into FMA grid 2109 in FIG. 21 or buffer circuit in FIG. 22), e.g., the ID value in data buffer 2105 in FIG. 21 for the tile currently loaded into FMA grid 2109 in FIG. 21. In one embodiment, comparison circuit 2708 compares the ID value of the current tile in use with the ID value of the next tile to be used in the operation circuit, and, if they are equal, asserts a value (e.g., 1) indicating that they are equal. In one embodiment, the comparison circuit 2708 compares the ID value of the current tile in use from storage 2704 with the ID value of the next tile to be used in the calculation circuit, and if they are equal, asserts a value (e.g., 1) indicating they are equal if storage 2706 also indicates that the identification value in storage 2704 is a valid value, for example, or asserts a different value (e.g., zero) if they are not.

[0212] In particular embodiments, if (i) the current tile (e.g., tile B) being loaded into the calculation circuit (e.g., into the FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22) is equal to (ii) the next tile (e.g., next tile B) to be loaded into the calculation circuit (e.g., into the FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22), then a same tile (e.g., same tile B) value (e.g., 1) is asserted to cause a switch (e.g., via output 2710) to a scheduling mode that reuses the input matrix, e.g., reuses tile B already stored within the calculation circuit (e.g., in the FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22), without reloading it from a data buffer (e.g., data buffer 2105 in FIG. 21) separate from the calculation circuit.

[0213] In particular embodiments, the comparison circuit 2708 outputs a first value (e.g., 1) at output 2710 if (i) the current tile (e.g., tile B) being loaded into the computation circuit (e.g., FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22) is equal to (ii) the next tile (e.g., next tile B) to be loaded into the computation circuit. The output 2710 may then be input to an OR logic gate 2726 along with an input from a NOT logic gate 2724. The OR logic gate 2726 may then be connected to an OR logic gate 2726. 27. The output from AND logic gate 2730 is sent to a first input of AND logic gate 2730. The other input of AND logic gate 2730 is coupled to NOT logic gate 2728, which is coupled to M counter 2718. In a particular embodiment, output 2732 of AND logic gate 2730, if 1, causes the next operation (e.g., a micro operation) to be dispatched. In contrast to FIG. 25, FIG. 27 includes counter 2716A for even K and counter 2716B for odd K, with both counters being fed to AND logic gate 2730. 20. In one embodiment, K even counter 2716A asserts a value of 1 for K even while counting down the number of cycles that the resource (e.g., bus) for loading the B tiles into the matrix operation accelerator circuitry is occupied, and then asserts a value of 0 when complete (e.g., when counter K even reaches a predetermined value), and K odd counter 2716B counts down the number of cycles that the resource (e.g., bus) for loading the B tiles into the matrix operation accelerator circuitry is occupied. An M counter 2718 asserts a value of 1 for M while counting down the number of cycles that a resource (e.g., a bus) is occupied to load the A tile into the matrix operation accelerator circuit, and then asserts a value of 0 when completed (e.g., when a predetermined value is reached in counter M). After each dispatch, the counter may be reset to its original (e.g., non-zero) value.

[0214] In one embodiment, Figure 27 specifies the trigger for the next operation to be sent to an operation circuit (e.g., FMA grid 2109 in Figure 21 or buffer circuit in Figure 22) as follows: even cycles are tracked by K even counter 2716A, odd cycles are tracked by K odd counter 2716B, and any operation (e.g., micro op) that is dispatched updates the corresponding K even counter or K odd counter, and any operation (e.g., micro op) that is dispatched also updates the M counter, e.g., B K×N Matrix reuse is checked.

[0215] In one embodiment, if (((K-even==0) OR (K-odd==0) OR (SAME-B==1)) AND (M<=1)), then dispatch the next operation (e.g., a micro operation).

[0216] In one embodiment, the dispatch state represents the case where one of the B-bus cycles (e.g., either an even or odd cycle) is available (e.g., its corresponding counter is zero), the first FMA0 is available (e.g., the M counter is zero or one), and the next operation (e.g., a micro operation) in either the main queue 2610 or the second path queue 2612 is sent to the operation circuit for execution (e.g., to the FMA grid 2109 in FIG. 21 or the buffer circuit in FIG. 22).

[0217] In particular embodiments, if a trigger occurs when the M counter == 0, A and B should be sent to the TMM in the same cycle, and / or if the M counter == 1, the B-bus should be sent to the TMM one cycle before the A-bus. Note that particular embodiments assume a multiple (e.g., 2) cycle latency for execution of the FMA circuit (e.g., PE); if the FMA circuit (e.g., PE) has a single cycle latency, scheduling including, for example, tile reuse is possible.

[0218] Below is an example of specifying scheduling: In one embodiment, a tile (eg, tile B) reuse mechanism is used in conjunction with:

[0219] Example 1.1 Given three numbers, a, b, and c, define the fused multiply-accumulate (FMA) operation as the addition of c to the product of a and b, i.e.

number

[0220] Example 1.2 Three matrices, namely A M×K , B K×N , and C M×N Matrix multiplication MM(M,K,N) is given as a new matrix

number

number

[0221] Certain embodiments herein impose an architectural constraint that M, N, K≦a threshold (eg, 16).

[0222] Example 1.3 A matrix queue MQ is an ordered set of matrix multiplication operations, i.e., MQ = {MM1, MM2, ...}. This set represents the ready matrix multiplication operations in RS.

[0223] Example 1.4 The big matrix queue BMQ is an ordered set of matrix multiplication operations, i.e., BMQ = {MM1, MM2, ...}. This queue is used for matrix multiplication operations with K > 8, which, due to restriction 3, require additional rounds in the matrix multiplication unit. Each element in this queue has an internal counter and becomes ready 16 cycles after insertion. This structure implements two additional update methods: ready for update and checking whether the top of the queue MM is ready.

[0224] In one embodiment, each of matrix multiplication (MM) operation parameters M, K, N and operands A, B, and C is defined as an MM element property, e.g., MM.K. Given a matrix multiplication MM and its operands A, B, and C, a scheduler may synchronize the initial cycle operations of these operands through the Dispatch_A, Dispatch_B, and Dispatch_C functions, which receive the initial cycle as an input parameter. Then, having specified the starting cycle for the operation, the scheduler may continue executing the remainder of the MM operation according to the operating mode. Specifically, starting with the input cycle of Dispatch_A, in the first (e.g., FMA_0) array, broadcast element a_(i,0) (where i = 0...M) in each resulting cycle, then in the second (e.g., FMA_1) array, continue broadcasting element a_(i,1) (where i = 0...M) in cycle +2, and so on. In one embodiment, the MM.C operand is inserted into the FMA_0 array through Dispatch_C two cycles after the insertion of A, because this is when the FMA multiplication operation is completed. In one embodiment, Dispatch_B inserts the entire B_i row into FMA_i every two cycles, where i = 0...K, respectively. Note that, according to some embodiments, loading one matrix row per cycle is a system constraint. Indeed, based on this constraint, the scheduler may divide the timeline into even and odd cycles and insert MM operations into these classified cycles. Then, if one of these cycles is free for insertion through the M, K_even, and K_odd counters that are updated every cycle, it is racked. If MM.K > 8, a particular embodiment splits the MM(M,K,N) operation into two operations: MM(M,8,N) and MM(M,K-8,N).In one embodiment, the MM(M,8,N) operation includes the first eight FMA operations of MM(M,K,N), which, when inserted, are sent for execution in rapid succession, where MM(M,K-8,N) is enqueued (e.g., in the main queue 2610 in FIG. 26) and waits for at least a threshold number (e.g., 16) cycles of operation (until MM(M,8,N) has finished calculating the result of the first line), and then, when executed, the result of this MM(M,8,N) is inserted as the C input of the matrix MM(M,K-8,N).

[0225] FIG. 28 illustrates pseudocode 2800 for a matrix operation circuit, according to an embodiment of the present disclosure.

[0226] 29 illustrates a method 2900 for processing a matrix operation instruction according to an embodiment of the present disclosure. A processor (e.g., or processor core) may perform method 2900 in response to receiving a request to execute an instruction from software, for example. The processor (e.g., or processor core) may offload certain operations to a matrix operation accelerator circuit.The method 2900 is shown as fetching 2902 an instruction having a first field identifying a first input two-dimensional matrix, a second field identifying a second input two-dimensional matrix, and a field identifying result storage, and decoding the instruction using a decoder of a hardware processor core into a decoded instruction, where the hardware processor core is coupled to a matrix operations accelerator circuit including a two-dimensional grid of fused multiply-accumulate circuits, the matrix operations accelerator circuit storing a first plurality of registers representing the first input two-dimensional matrix and a second plurality of registers representing a result storage. a second plurality of registers representing an input two-dimensional matrix of tile A (2904), retrieve data associated with a first field (e.g., tile A), a second field (e.g., tile B) (and optionally a third field (e.g., tile C)) (2906), (optionally) schedule the decoded instructions for execution (2908), and execute the decoded instructions to load the first input two-dimensional matrix from the first plurality of registers into a first buffer of the two-dimensional grid of the fused multiply-accumulate circuit, and checking whether the second buffer stores an immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix; if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores an immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from the execution of the previous instruction, preventing reclamation of the second buffer between the execution of the previous instruction and the decoded single instruction; performing an operation on the first input two-dimensional matrix from the first buffer and the immediately preceding input two-dimensional matrix from the second buffer to generate a result; storing the result in a result storage; If the second buffer of the two-dimensional grid of the accumulation circuit does not store a immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from execution of a previous instruction, processing a matrix operation (e.g., FMA) instruction by loading the second input two-dimensional matrix into a second buffer of the two-dimensional grid of the fused multiply-accumulate circuit, performing an operation on the first input two-dimensional matrix from the first buffer and the second input two-dimensional matrix from the second buffer to generate a result, storing the result in result storage (2910), and committing (2912) the result of the executed instruction.

[0227] Exemplary architectures, systems, etc. that may be used above are described in detail below.

[0228] At least some embodiments of the disclosed technology can be described with reference to the following examples. Example 1. A matrix operation accelerator circuit containing a two-dimensional grid of fused multiply-accumulate circuits; a first plurality of registers coupled to the matrix operation accelerator circuit, the first plurality of registers representing a first input two-dimensional matrix; a second plurality of registers coupled to the matrix operation accelerator circuit and representing a second input two-dimensional matrix; a decoder of a hardware processor core coupled to the matrix operation accelerator circuit for decoding a single instruction into a decoded single instruction, the single instruction including a field identifying a result storage; an execution circuit of the hardware processor core, loading the first input two-dimensional matrix from the first plurality of registers into a first buffer of a two-dimensional grid of the fused multiply-accumulate circuit; checking whether a second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores a previous input two-dimensional matrix that is identical to the second input two-dimensional matrix; if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores, from execution of a previous instruction, the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix; preventing reclamation of the second buffer between execution of the previous instruction and the decoded single instruction; performing an operation on the first input two-dimensional matrix from the first buffer and the immediately preceding input two-dimensional matrix from the second buffer to generate a result; storing the results in the result storage; if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit does not store the immediately preceding input two-dimensional matrix from execution of the previous instruction that is identical to the second input two-dimensional matrix; loading the second input two-dimensional matrix into the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit; performing an operation on the first input two-dimensional matrix from the first buffer and the second input two-dimensional matrix from the second buffer to generate a result; storing the results in the results storage; an execution circuit for executing the single decoded instruction, An apparatus comprising: Example 2. The apparatus of Example 1, wherein if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit does not store the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from execution of the previous instruction, the matrix operation accelerator circuit initiates reclamation of the second buffer between execution of the previous instruction and the decoded single instruction. Example 3. The apparatus of Example 1, wherein the matrix operation accelerator circuit assigns an identification value to each of a plurality of registers representing an input two-dimensional matrix, and wherein the checking whether the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix includes comparing the identification values ​​of corresponding input two-dimensional matrices from the previous instruction and the single instruction. Example 4. The apparatus of Example 3, wherein the matrix operation accelerator circuit assigns different identification values ​​to the second plurality of registers to store an input two-dimensional matrix for a next instruction. Example 5. The apparatus of Example 1, wherein the matrix operation accelerator circuit does not load the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit during execution of the decoded single instruction if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from execution of the previous instruction. Example 6. The apparatus of Example 1, wherein said result storage is a third plurality of registers representing at least one output two-dimensional matrix formed by execution of said decoded single instruction. Example 7. The apparatus of Example 1, wherein said operation includes transmitting each output of each of a first suitable subset of fused multiply-accumulate circuits of said two-dimensional grid downstream to each input of each of a second suitable subset of fused multiply-accumulate circuits of said two-dimensional grid to form said result. Example 8. The apparatus of Example 7, wherein a first suitable subset of the fused multiply-accumulate circuits is one of rows or columns of a two-dimensional grid of the fused multiply-accumulate circuits, and a second suitable subset of the fused multiply-accumulate circuits is the other of the rows or columns of the two-dimensional grid of the fused multiply-accumulate circuits. Example 9. Decoding, with a decoder of a hardware processor core, a single instruction into a decoded single instruction, the hardware processor core being coupled to a matrix operation accelerator circuit including a two-dimensional grid of fused multiply-accumulate circuits, the matrix operation accelerator circuit being coupled to a first plurality of registers representing a first input two-dimensional matrix and a second plurality of registers representing a second input two-dimensional matrix, the single instruction comprising a field identifying result storage; loading the first input two-dimensional matrix from the first plurality of registers into a first buffer of a two-dimensional grid of the fused multiply-accumulate circuit; checking whether a second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores a previous input two-dimensional matrix that is identical to the second input two-dimensional matrix; if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores, from execution of a previous instruction, the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix; preventing reclamation of the second buffer between execution of the previous instruction and the decoded single instruction; performing an operation on the first input two-dimensional matrix from the first buffer and the immediately preceding input two-dimensional matrix from the second buffer to generate a result; storing the results in the result storage; if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit does not store the immediately preceding input two-dimensional matrix from execution of the previous instruction that is identical to the second input two-dimensional matrix; loading the second input two-dimensional matrix into the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit; performing an operation on the first input two-dimensional matrix from the first buffer and the second input two-dimensional matrix from the second buffer to generate a result; storing the results in the results storage; executing the decoded single instruction using execution circuitry of the hardware processor core, such that A method comprising: Example 10. The method of Example 9, further comprising initiating reclamation of the second buffer between execution of the previous instruction and the decoded single instruction if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit does not store the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from execution of the previous instruction. Example 11. The method of Example 9, further comprising assigning an identification value to each of a plurality of registers representing an input two-dimensional matrix, and wherein said checking whether said second buffer of said two-dimensional grid of said fused multiply-accumulate circuit stores said immediately preceding input two-dimensional matrix that is identical to said second input two-dimensional matrix comprises comparing respective identification values ​​of corresponding input two-dimensional matrices from said previous instruction and said single instruction. Example 12. The method of Example 11, further comprising assigning different identification values ​​to the second plurality of registers to store an input two-dimensional matrix for a subsequent instruction. Example 13. The method of Example 9, further comprising: not loading the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit during execution of the decoded single instruction if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from execution of the previous instruction. Example 14. The method of Example 9, wherein the result storage is a third plurality of registers representing at least one output two-dimensional matrix formed by execution of the decoded single instruction. Example 15. The method of Example 9, wherein the operation includes transmitting each output of each of a first suitable subset of fused multiply-accumulate circuits of the two-dimensional grid downstream to each input of each of a second suitable subset of fused multiply-accumulate circuits of the two-dimensional grid to form the result. Example 16. The method of Example 15, wherein a first suitable subset of the fused multiply-accumulate circuits is one of rows or columns of a two-dimensional grid of the fused multiply-accumulate circuits, and a second suitable subset of the fused multiply-accumulate circuits is the other of the rows or the columns of the two-dimensional grid of the fused multiply-accumulate circuits. Example 17. A non-transitory machine-readable medium storing code that, when executed by a machine, causes said machine to perform a method, said method comprising: decoding, using a decoder of a hardware processor core, a single instruction into a decoded single instruction, the hardware processor core being coupled to a matrix operation accelerator circuit including a two-dimensional grid of fused multiply-accumulate circuits, the matrix operation accelerator circuit being coupled to a first plurality of registers representing a first input two-dimensional matrix and a second plurality of registers representing a second input two-dimensional matrix, the single instruction comprising a field identifying result storage; loading the first input two-dimensional matrix from the first plurality of registers into a first buffer of a two-dimensional grid of the fused multiply-accumulate circuit; checking whether a second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores a previous input two-dimensional matrix that is identical to the second input two-dimensional matrix; if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores, from execution of a previous instruction, the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix; preventing reclamation of the second buffer between execution of the previous instruction and the decoded single instruction; performing an operation on the first input two-dimensional matrix from the first buffer and the immediately preceding input two-dimensional matrix from the second buffer to generate a result; storing the results in the result storage; if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit does not store the immediately preceding input two-dimensional matrix from execution of the previous instruction that is identical to the second input two-dimensional matrix; loading the second input two-dimensional matrix into the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit; performing an operation on the first input two-dimensional matrix from the first buffer and the second input two-dimensional matrix from the second buffer to generate a result; storing the results in the results storage; executing the decoded single instruction using execution circuitry of the hardware processor core, such that a non-transitory machine-readable medium, including Example 18. The non-transitory machine-readable medium of Example 17, further comprising: if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit does not store the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from execution of the previous instruction, initiating reclamation of the second buffer between execution of the previous instruction and the decoded single instruction. Example 19. The non-transitory machine-readable medium of Example 17, further comprising assigning an identification value to each of a plurality of registers representing an input two-dimensional matrix, and wherein said checking whether said second buffer of a two-dimensional grid of said fused multiply-accumulate circuit stores said immediately preceding input two-dimensional matrix that is identical to said second input two-dimensional matrix comprises comparing respective identification values ​​of corresponding input two-dimensional matrices from said previous instruction and said single instruction. Example 20. The non-transitory machine-readable medium of Example 19, further comprising assigning different identification values ​​to the second plurality of registers to store an input two-dimensional matrix for a subsequent instruction. Example 21. The non-transitory machine-readable medium of Example 17, further comprising: not loading the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit during execution of the decoded single instruction if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from execution of the previous instruction. Example 22. The non-transitory machine-readable medium of example 17, wherein the result storage is a third plurality of registers representing at least one output two-dimensional matrix formed by execution of the decoded single instruction. Example 23. The non-transitory machine-readable medium of Example 17, wherein the operation includes transmitting each output of each of a first suitable subset of fused multiply-accumulate circuits of the two-dimensional grid downstream to each input of each of a second suitable subset of fused multiply-accumulate circuits of the two-dimensional grid to form the result. Example 24. The non-transitory machine-readable medium of Example 23, wherein a first suitable subset of the fused multiply-accumulate circuits is one of rows or columns of a two-dimensional grid of the fused multiply-accumulate circuits, and a second suitable subset of the fused multiply-accumulate circuits is the other of the rows or columns of the two-dimensional grid of the fused multiply-accumulate circuits.

[0229] In yet another embodiment, an apparatus comprises a data storage device storing code that, when executed by a hardware processor, causes the hardware processor to perform any method disclosed herein. The apparatus may be the same as described in the detailed description. The method may be the same as described in the detailed description.

[0230] Detailed Example System, Processor, and Emulation Examples of hardware, software, etc. for executing the instructions described above are detailed herein. For example, the description below details aspects of instruction execution, including various pipeline stages such as fetching, decoding, scheduling, executing, and retiring.

[0231] [Instruction Set] An instruction set may include one or more instruction formats. A given instruction format may define, among other things, various fields (e.g., number of bits, bit positions) that specify the operation to be performed (e.g., opcode) and the operands on which the operation is to be performed, and / or other data fields (e.g., masks). Some instruction formats are further classified by the definition of instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are usually in the same order, but at least some have different bit positions because fewer fields are included) and / or such that given fields are interpreted differently. Thus, each instruction of the ISA is expressed using a given instruction format (and a given one of that instruction format's instruction templates, if defined) and includes fields for specifying the operation and operands. For example, an exemplary ADD instruction has an instruction format that includes a particular opcode, an opcode field that specifies the opcode, and an operand field that selects the operands (source1 / destination and source2), such that occurrences of this ADD instruction in an instruction stream include particular content in the operand field that selects the particular operand. A set of SIMD extensions called Advanced Vector Extensions (AVX) (AVX1 and AVX2), which use the Vector Extension (VEX) coding scheme, has been released and / or published (e.g., see Intel® 64 and IA-32 Architecture Software Developer's Manual, November 2018, and Intel® Architecture Instruction Set Extensions Programming Reference, October 2018).

[0232] [Example instruction format] Embodiments of the instructions described herein may be embodied in different formats. Further, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instructions may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

[0233] [General-purpose vector instruction format] A vector friendly instruction format is an instruction format that is suitable for vector instructions (e.g., there are certain fields that are specific to vector operations). Although embodiments are described in which both vector and scalar operations are supported by the vector friendly instruction format, alternative embodiments use only vector operations with the vector friendly instruction format.

[0234] Figures 30A and 30B are block diagrams illustrating a generic vector instruction format and its class A instruction templates according to an embodiment of the present disclosure. Figure 30A is a block diagram illustrating a generic vector instruction format and its class A instruction templates according to an embodiment of the present disclosure, and Figure 30B is a block diagram illustrating a generic vector instruction format and its class B instruction templates according to an embodiment of the present disclosure. Specifically, generic vector instruction format 3000 defines class A and class B instruction templates, both of which include no memory access 3005 instruction templates and memory access 3020 instruction templates. The term generic in the context of the vector instruction format refers to an instruction format that is not tied to any particular instruction set.

[0235] In embodiments of the present disclosure, the vector-friendly instruction format supports vector operand lengths (or sizes) of 64 bytes with 32-bit (4 bytes) or 64-bit (8 byte) data element widths (or sizes) (thus a 64-byte vector consists of either 16 double-word sized elements or alternatively 8 quad-word sized elements), vector operand lengths (or sizes) of 64 bytes with 16-bit (2 bytes) or 8-bit (1 byte) data element widths (or sizes), and vector operand lengths (or sizes) of 32-bit (4 bytes), 64-bit (8 bytes), 16-bit (2 bytes), or 8-bit (1 byte) Although described as supporting vector operand lengths (or sizes) of 32 bytes having data element widths (or sizes) and vector operand lengths (or sizes) of 16 bytes having 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte) or 8-bit (1-byte) data element widths (or sizes), alternative embodiments may support greater, fewer and / or different vector operand sizes (e.g., 256-byte vector operands) having greater, fewer or different data element widths (e.g., 128-bit (16-byte) data element widths).

[0236] The class A instruction templates in Figure 30A include 1) a no memory access, full round control type operation 3010 instruction template and a no memory access, data transform type operation 3015 instruction template shown in the no memory access 3005 instruction templates, and 2) a memory access, temporary 3025 instruction template and a memory access, non-temporal 3030 instruction template shown in the memory access 3020 instruction templates. The class B instruction templates in Figure 30B include 1) a no memory access, write mask control, partial round control type operation 3012 instruction template and a no memory access, write mask control, VSIZE type operation 3017 instruction template shown in the no memory access 3005 instruction templates, and 2) a memory access, write mask control 3027 instruction template shown in the memory access 3020 instruction templates.

[0237] The generic vector friendly instruction format 3000 includes the fields listed below in the order shown in Figures 30A and 30B.

[0238] Format field 3040: A particular value (the instruction format identifier value) in this field uniquely identifies the vector friendly instruction format and therefore the occurrence of an instruction in the vector friendly instruction format in an instruction stream. As such, this field is optional in the sense that it is not needed for instruction sets that have only a generic vector friendly instruction format.

[0239] Basic operation field 3042: its contents distinguish between different basic operations.

[0240] Register index field 3044: its contents specify the location of the source and destination operands, whether in registers or in memory, either directly or through address generation. These contain a sufficient number of bits to select N registers from a P x Q (e.g., 32 x 512, 16 x 128, 32 x 1024, 64 x 1024) register file. In one embodiment, N may be up to three source and one destination register, although alternative embodiments may support more or fewer source and destination registers (e.g., up to two sources may be supported, one of which may also function as a destination, up to three sources may be supported, one of which may also function as a destination, up to two sources and one destination).

[0241] Qualifier field 3046: its content distinguishes occurrences of instructions in the generic vector instruction format that specify memory access from instructions that do not, i.e., distinguishes between no-memory access 3005 instruction templates and memory access 3020 instruction templates. Memory access operations read and / or write to the memory hierarchy (possibly using values ​​in registers to specify source and / or destination addresses), while non-memory access operations do not (e.g., the source and destination are registers). In one embodiment, this field also selects between three different ways of performing memory address calculations, although alternative embodiments may support more, fewer, or different ways of performing memory address calculations.

[0242] Extended Operation Field 3050: Its contents distinguish which of a variety of different operations should be performed in addition to the basic operations. This field is context specific. In one embodiment of the present disclosure, this field is divided into a class field 3068, an alpha field 3052, and a beta field 3054. The extended operation field 3050 allows common groups of operations to be performed in a single instruction rather than two, three, or four instructions.

[0243] Scale field 3060: its contents allow scaling of the contents of the index field for memory address generation (eg, for address generation using 2 scale x index + base).

[0244] Displacement field 3062A: its contents are used as part of memory address generation (e.g., for address generation using 2 scale x index + base + displacement).

[0245] Displacement factor field 3062B (note that the juxtaposition of displacement field 3062A directly above displacement factor field 3062B indicates that one or the other is used): its contents are used as part of address generation; it specifies the displacement factor to be scaled by the size (N) of the memory access. N is the number of bytes in the memory access (e.g., for address generation using 2 scale × index + base + scaled displacement). Since redundant low-order bits are ignored, the contents of the displacement factor field are multiplied by the total size (N) of the memory operands to generate the final displacement to be used in calculating the effective address. The value of N is determined by the processor hardware at run time based on the full opcode field 3074 and data operation field 3054C (described later in this specification). The displacement field 3062A and displacement factor field 3062B are optional in the sense that they are not used for non-memory access 3005 instruction templates and / or different embodiments may implement only one or neither of the two.

[0246] Data element width field 3064 - its content distinguishes which of multiple data element widths should be used (in some embodiments for all instructions, in other embodiments for only some instructions). This field is optional in the sense that it is not needed if only one data element width is supported and / or if the data element width is supported using some aspect of the opcode.

[0247] Write mask field 3070 - its content controls, for each data element position, whether that data element position in the destination vector operand reflects the result of the basic and extended operations. While class A instruction templates support merging-write masking, class B instruction templates support both merging-write masking and zeroing-write masking. When merging, the vector mask allows any set of elements in the destination to be protected from updates during the execution of any operation (specified by the basic and extended operations). In another embodiment, it preserves the old value of each element in the destination whose corresponding mask bit is 0. In contrast, when zeroing, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified in the basic and extended operations). In one embodiment, an element in the destination is set to 0 if its corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the range of elements, from the first element to the last element, that are modified), although the modified elements need not be contiguous. Thus, the write mask field 3070 allows for partial vector operations, including loads, stores, arithmetic, logic, etc. While embodiments of the present disclosure are described in which the contents of the write mask field 3070 select one of multiple write mask registers containing the write mask to be used (and thus the contents of the write mask field 3070 indirectly identify the masking to be performed), alternative embodiments allow the contents of the mask write field 3070 to instead or in addition directly specify the masking to be performed.

[0248] Immediate field 3072: its contents allow specification of an immediate value. This field is optional in the sense that it is not present in implementations of the generic vector-oriented format that do not support immediate values, and is not present in instructions that do not use immediate values.

[0249] Class field 3068: its contents distinguish between different classes of instructions. With reference to Figures 30A and 30B, the contents of this field select between class A and class B instructions. In Figures 30A and 30B, rounded rectangles are used to indicate that a particular value is present in the field (e.g., class A 3068A and class B 3068B of class field 3068 in Figures 30A and 30B, respectively).

[0250] [Class A instruction template] For class A no memory access 3005 instruction templates, the alpha field 3052 is interpreted as an RS field 3052A, whose content distinguishes which of the different extended operation types is to be performed (e.g., round 3052A.1 and data transform 3052A.2 are specified for the no memory access, round type operation 3010 and no memory access, data transform type operation 3015 instruction templates, respectively), and the beta field 3054 distinguishes which of the specified types of operation is to be performed. The scale field 3060, displacement field 3062A, and displacement scale field 3062B are not present in the no memory access 3005 instruction templates.

[0251] [Non-memory access instruction template - full round control type operation] In the no memory access full round control type operation 3010 instruction template, the beta field 3054 is interpreted as a round control field 3054A, the contents of which provide static rounding. In the described embodiment of the disclosure, the round control field 3054A includes a suppress all floating-point exceptions (SAE) field 3056 and a round operation control field 3058; alternative embodiments may support both of these concepts and encode them in the same field, or may only have one or the other of these concepts / fields (e.g., only have the round operation control field 3058).

[0252] SAE field 3056: its content distinguishes whether exception event reporting should be disabled. When the content of SAE field 3056 indicates that suppression is enabled, the given instruction will not report any kind of floating-point exception flags and will not cause any floating-point exception handlers to be invoked.

[0253] Round operation control field 3058: its content distinguishes which of a group of rounding operations to perform (e.g., round up, round down, round towards zero, and round to nearest). Thus, the round operation control field 3058 allows the rounding mode to be changed on a per-instruction basis. In one embodiment of the present disclosure in which the processor includes a control register for specifying the rounding mode, the content of the round operation control field 3058 overrides that register value.

[0254] [Non-memory access instruction template - Data conversion type operation] In the no memory access data transform type operation 3015 instruction template, the beta field 3054 is interpreted as a data transform field 3054B, whose content distinguishes which of a number of data transforms should be performed (e.g., no data transform, swizzle, broadcast).

[0255] For memory access 3020 instruction templates of class A, the alpha field 3052 is interpreted as an eviction hint field 3052B, whose content distinguishes which of the eviction hints should be used (in Figure 30A, temporal 3052B.1 and non-temporal 3052B.2 are specified for the memory access, temporal 3025 instruction template and the memory access, non-temporal 3030 instruction template, respectively), while the beta field 3054 is interpreted as a data manipulation field 3054C, whose content distinguishes which of a number of data manipulation operations (also known as primitives) should be performed (e.g., no operation, broadcast, upconversion of source, and downconversion of destination). The memory access 3020 instruction templates include a scale field 3060, and optionally a displacement field 3062A or a displacement scale field 3062B.

[0256] Vector memory instructions perform vector loads from and stores to memory with conversion support. Like regular vector instructions, vector memory instructions transfer data to and from memory element by data element, with the elements actually transferred being dictated by the contents of the vector mask selected as the write mask.

[0257] [Memory Access Instruction Template - Temporary] Transient data is data that is likely to be reused quickly enough to benefit from caching. However, this is a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

[0258] [Memory Access Instruction Template - Non-temporal] Non-transient data is data that is unlikely to be reused quickly enough to benefit from caching in the first level cache and should be prioritized for eviction. However, this is a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

[0259] [Class B instruction template] For class B instruction templates, the alpha field 3052 is interpreted as a write mask control (Z) field 3052C, whose content distinguishes whether the write masking controlled by the write mask field 3070 should be merging or zeroing.

[0260] For class B no-memory access 3005 instruction templates, part of the beta field 3054 is interpreted as an RL field 3057A, whose content distinguishes which of different extended operation types is to be performed (e.g., round 3057A.1 and vector length (VSIZE) 3057A.2 are specified for the no-memory access, writemask control, partial round control type operation 3012 instruction template and the no-memory access, writemask control, VSIZE type operation 3017 instruction template, respectively), and the remainder of the beta field 3054 distinguishes which of the specified types of operation is to be performed. In no-memory access 3005 instruction templates, the scale field 3060, displacement field 3062A and displacement scale field 3062B are not present.

[0261] For the no memory access, write mask control, partial round control type operation 3010 instruction template, the remainder of the beta field 3054 is interpreted as the round operation field 3059A and exception event reporting is disabled (the given instruction will not report any kind of floating point exception flags or raise any floating point exception handlers).

[0262] Round operation control field 3059A: Similar to the round operation control field 3058, its content distinguishes which of a group of rounding operations to perform (e.g., round up, round down, round towards zero, and round to nearest). Thus, the round operation control field 3059A allows the rounding mode to be changed on a per-instruction basis. In one embodiment of the present disclosure in which the processor includes a control register for specifying the rounding mode, the content of the round operation control field 3059A overrides that register value.

[0263] In the non-memory access, write mask control, VSIZE type operation 3017 instruction template, the remainder of the beta field 3054 is interpreted as a vector length field 3059B, the contents of which distinguish which of a number of data vector lengths should be executed (e.g., 128, 256, or 512 bytes).

[0264] For class B memory access 3020 instruction templates, part of the beta field 3054 is interpreted as a broadcast field 3057B, the content of which distinguishes whether a broadcast-type data manipulation operation is to be performed, and the remainder of the beta field 3054 is interpreted as a vector length field 3059B. The memory access 3020 instruction templates include a scale field 3060 and, optionally, a displacement field 3062A or a displacement scale field 3062B.

[0265] For the generic vector friendly instruction format 3000, the full opcode field 3074 is shown to include a format field 3040, a base operation field 3042, and a data element width field 3064. While one embodiment is shown in which the full opcode field 3074 includes all of these fields, in embodiments that do not support all of these fields, the full opcode field 3074 includes less than all of these fields. The full opcode field 3074 provides an operation code (opcode).

[0266] The extended operation field 3050, data element width field 3064, and write mask field 3070 allow these features to be specified on a per-instruction basis in the generic vector friendly instruction format.

[0267] The combination of the write mask field and the data element width field creates a typed instruction in that it allows masks to be applied based on different data element widths.

[0268] The various instruction templates found within Class A and Class B are useful in various situations. In some embodiments of the present disclosure, different processors or different cores within a processor may support only Class A, only Class B, or both classes. For example, a high-performance, general-purpose, out-of-order core intended for general-purpose computing may support only Class B, a core intended primarily for graphics and / or scientific (throughput) computing may support only Class A, and a core intended for both may support both (of course, a core having some combination of templates and instructions from both classes is within the scope of the present disclosure, but not all templates and instructions from both classes). Also, a single processor may include multiple cores, all of which support the same class, or different cores therein may support different classes. For example, in a processor with separate graphics and general-purpose cores, one of the graphics cores intended primarily for graphics and / or scientific computing may support only Class A, while one or more of the general-purpose cores may be a high-performance, general-purpose core with out-of-order execution and register renaming intended for general-purpose computing that supports only Class B. Another processor that does not have a separate graphics core may include another general-purpose in-order or out-of-order core that supports both Class A and Class B. Of course, multiple functions from one class may be implemented in other classes in different embodiments of the present disclosure. A program written in a high-level language may be converted (e.g., just-in-time or statically compiled) into a variety of different executable formats, including 1) a format that has only instructions of classes supported by the target processor for execution, or 2) a format that has alternative routines written using different combinations of instructions from all classes, with control flow code that selects which routine to execute based on the instructions supported by the processor currently executing the code.

[0269] [Example vector-specific instruction formats] Figures 31A-31D are block diagrams illustrating an exemplary vector-specific instruction format according to an embodiment of the present disclosure. Figures 31A-31D illustrate a vector-specific instruction format 3100 that is specific in the sense that it specifies the location, size, interpretation, and field order, as well as values ​​for some of these fields. The vector-specific instruction format 3100 may be used to extend the x86 instruction set, and thus some fields are similar or identical to those used in the existing x86 instruction set and its extensions (e.g., AVX). This format remains consistent with the prefix encoding field, real opcode byte field, MOD R / M field, SIB field, displacement field, and immediate field of the existing x86 instruction set with extensions. The fields from Figures 30A and 30B are shown to map to fields in Figures 31A-31D.

[0270] While embodiments of the present disclosure are described with reference to the specific vector instruction format 3100 in the context of the generic vector instruction format 3000 for illustrative purposes, it should be understood that the present disclosure is not limited to the specific vector instruction format 3100 except as recited in the claims. For example, while the generic vector instruction format 3000 contemplates a variety of possible sizes for various fields, the specific vector instruction format 3100 is illustrated as having fields of specific sizes. As a specific example, while the data element width field 3064 is shown in the specific vector instruction format 3100 as a one-bit field, the present disclosure is not so limited (i.e., the generic vector instruction format 3000 contemplates data element width fields 3064 of other sizes).

[0271] The generic vector friendly instruction format 3000 includes the following fields, listed below in the order shown in Figure 31A:

[0272] EVEX Prefix (bytes 0-3) 3102: Encoded in 4-byte format.

[0273] Format field 3040 (EVEX byte 0, bits [7:0]): The first byte (EVEX byte 0) is the format field 3040, which contains 0x62 (a unique value used to distinguish vector friendly instruction formats in one embodiment of the present disclosure).

[0274] The second through fourth bytes (EVEX bytes 1-3) contain multiple bit fields that provide specific functions.

[0275] REX field 3105 (EVEX byte 1, bits [7-5]): Consists of the EVEX.R bit field (EVEX byte 1, bit [7] - R), the EVEX.X bit field (EVEX byte 1, bit [6] - X), and the EVEX.B bit field (EVEX byte 1, bit [5] - B). The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as the corresponding VEX bit fields and are encoded using one's complement format; i.e., ZMM0 is encoded as 1111B, ZMM15 is encoded as 0000B. Other fields in the instruction encode the lower three bits of the register index (rrr, xxx, and bbb) as known in the art, whereby Rrrr, Xxxx, and Bbbb may be formed by adding EVEX.R, EVEX.X, and EVEX.B.

[0276] REX' field 3010: This is the first part of the REX' field 3010, the EVEX.R' bit field (EVEX byte 1, bit [4] - R') used to encode either the upper 16 or lower 16 of the extended 32-register set. In one embodiment of the present disclosure, this bit is stored in a bit-reversed format with the others shown below to distinguish it (in the familiar x86 32-bit mode) from the BOUND instruction, whose real opcode byte is 62, but does not accept a value of 11 in the MOD field in the MOD R / M field (described below). Alternative embodiments of the present disclosure use a value of 1 to encode the lower 16 registers that do not store this bit and the other bits in the reversed format shown below. In other words, R'Rrrr is formed by combining EVEX.R', EVEX.R, and other RRRs from other fields.

[0277] Opcode map field 3115 (EVEX byte 1, bits [3:0]-mmmm): its contents encode the suggested leading opcode byte (0F, 0F38, or 0F3).

[0278] Data Element Width field 3064 (EVEX byte 2, bit [7] - W): represented by the symbol EVEX.W. EVEX.W is used to specify the granularity (size) of the data type (either 32-bit data elements or 64-bit data elements).

[0279] EVEX.vvvv 3120 (EVEX byte 2, bits [6:3]—vvvv)—The role of EVEX.vvvv may include: 1) EVEX.vvvv encodes the first source register operand specified in inverted (one's complement) format and is valid for instructions with two or more source operands; 2) EVEX.vvvv encodes the destination register operand specified in one's complement format for certain vector shifts; or 3) EVEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. Thus, EVEX.vvvv field 3120 encodes the four least significant bits of the first source register specifier stored in inverted (one's complement) format. Depending on the instruction, additional different EVEX bit fields are used to extend the size of the specifier to 32 registers.

[0280] EVEX.U3068 Class field (EVEX byte 2, bit [2] - U): If EVEX.U=0, this indicates class A or EVEX.U0. If EVEX.U=1, this indicates class B or EVEX.U1.

[0281] Prefix encoding field 3125 (EVEX byte 2, bits [1:0]-pp): Provides additional bits to the basic operation field. In addition to providing support for legacy SSE instructions in EVEX prefix format, this also has the benefit of compacting SIMD prefixes (instead of requiring one byte to represent the SIMD prefix, the EVEX prefix only requires two bits). In one embodiment, to support legacy SSE instructions that use SIMD prefixes (66H, F2H, F3H) in both the legacy and EVEX prefix formats, these legacy SIMD prefixes are encoded in the SIMD prefix encoding field and expanded to the legacy SIMD prefix at runtime before being provided to the PLA in the decode circuitry (so the PLA can execute both the legacy and EVEX formats of these legacy instructions without modification). Although newer instructions can directly use the contents of the EVEX prefix encoding field as an opcode extension, certain embodiments extend it as well for consistency, but allow different meanings to be specified by these legacy SIMD prefixes. Alternative embodiments may redesign the PLA to support 2-bit SIMD prefix encodings and thus not require the extension.

[0282] Alpha field 3052 (EVEX byte 3, bit [7]; also known as EH, EVEX.EH, EVEX.rs, EVEX.RL, EVEX.WriteMaskControl and EVEX.N, also denoted with an α): As previously mentioned, this field is context specific.

[0283] Beta field 3054 (EVEX byte 3, bits [6:4] - SSS; also known as EVEX.s2-0, EVEX.r2-0, EVEX.rr1, EVEX.LL0, EVEX.LLB, and denoted with βββ): As previously mentioned, this field is context specific.

[0284] REX' field 3010: This is the remainder of the REX' field, the EVEX.V' bit field (EVEX byte 3, bit [3] - V'), which can be used to encode either the top 16 or bottom 16 of the extended 32 register set. This bit is stored in bit-reversed format. A value of 1 is used to encode the bottom 16 registers. In other words, combining EVEX.V' and EVEX.vvvv forms V'VVVV.

[0285] Write mask field 3070 (EVEX byte 3, bits [2:0]-kkk): As previously mentioned, its contents specify the index of a register within the write mask register. In one embodiment of the present disclosure, the particular value EVEX.kkk=000 has special behavior that indicates that no write mask is used for a particular instruction (this can be implemented in various ways, including a write mask that is hardwired into everything, or using hardware to bypass the masking hardware).

[0286] The real opcode field 3130 (byte 4) is also known as the opcode byte. Part of the opcode is specified in this field.

[0287] MOD R / M field 3140 (byte 5) includes MOD field 3142, Reg field 3144, and R / M field 3146. As previously mentioned, the contents of MOD field 3142 distinguish between memory access and non-memory access operations. The role of Reg field 3144 can be summarized in two situations: to encode either a destination register operand or a source register operand, or to be treated as an opcode extension and not used to encode any instruction operand. The role of R / M field 3146 may include: to encode an instruction operand that references a memory address, or to encode either a destination register operand or a source register operand.

[0288] Scale, Index, Base (SIB) Byte (Byte 6): As mentioned above, the contents of the scale field 3060 are used in memory address generation. SIB.xxx 3154 and SIB.bbb 3156: The contents of these fields have already been mentioned in relation to the register indices Xxxx and Bbbb.

[0289] Displacement field 3062A (bytes 7-10): If the MOD field 3142 contains 10, then bytes 7-10 are the displacement field 3062A, which functions the same as the legacy 32-bit displacement (disp32), and operates at byte granularity.

[0290] Displacement Factor Field 3062B (Byte 7): When the MOD field 3142 contains 01, byte 7 is the displacement factor field 3062B. The location of this field is the same as that of the 8-bit displacement (disp8) in the legacy x86 instruction set, which operates at byte granularity. Because disp8 is sign-extended, disp8 can only address between -128 and 127 byte offsets. For a 64-byte cache line, disp8 uses 8 bits that can only be set to four practically useful values: -128, -64, 0, and 64. Often, a wider range is needed, so disp32 is used, but disp32 requires 4 bytes. In contrast to disp8 and disp32, the displacement factor field 3062B is a reinterpretation of disp8. When using the displacement factor field 3062B, the actual displacement is determined by the contents of the displacement factor field multiplied by the size of the memory operand access (N). This type of displacement is referred to as disp8 × N. This reduces the average instruction length (a single byte used for displacement, but with a much wider range). Such a compressed displacement is based on the assumption that the effective displacement is a multiple of the granularity of the memory access, and therefore the redundant low-order bits of the address offset do not need to be encoded. In other words, the displacement factor field 3062B replaces the 8-bit displacement of the legacy x86 instruction set. Therefore, the displacement factor field 3062B is encoded the same as the 8-bit displacement of the x86 instruction set, except that disp8 is overloaded to disp8×N (hence, no change in the ModRM / SIB encoding rules). In other words, there is no change in the encoding rules or encoding length, only in the interpretation of the displacement value by the hardware (the displacement needs to be scaled by the size of the memory operand to get the address offset in bytes). The immediate field 3072 operates as described above.

[0291] [Full Opcode Field] 31B is a block diagram illustrating the fields of a specific vector instruction format 3100 that create a full opcode field 3074, according to one embodiment of the present disclosure. Specifically, the full opcode field 3074 includes a format field 3040, a base operation field 3042, and a data element width (W) field 3064. The base operation field 3042 includes a prefix encoding field 3125, an opcode map field 3115, and a real opcode field 3130.

[0292] [Register index field] 31C is a block diagram illustrating the fields of the specific vector instruction format 3100 that create the register index field 3044, in accordance with one embodiment of the present disclosure. Specifically, the register index field 3044 includes a REX field 3105, a REX′ field 3110, a MODR / M.reg field 3144, a MODR / Mr / m field 3146, a VVVV field 3120, a xxx field 3154, and a bbb field 3156.

[0293] Extended computed field Figure 31D is a block diagram illustrating the fields of a specific vector instruction format 3100 that create an extended operation field 3050, according to one embodiment of the present disclosure. When the class (U) field 3068 contains a 0, it represents EVEX.U0 (Class A 3068A), and when it contains a 1, it represents EVEX.U1 (Class B 3068B). When U=0 and the MOD field 3142 contains 11 (indicating a non-memory access operation), the alpha field 3052 (EVEX byte 3, bit [7] - EH) is interpreted as the RS field 3052A. When the RS field 3052A contains a 1 (round 3052A.1), the beta field 3054 (EVEX byte 3, bits [6:4] - SSS) is interpreted as the round control field 3054A. The round control field 3054A includes a 1-bit SAE field 3056 and a 2-bit round operation field 3058. If RS field 3052A contains 0 (data translation 3052A.2), then beta field 3054 (EVEX byte 3, bits [6:4] - SSS) is interpreted as a 3-bit data translation field 3054B. If U=0 and MOD field 3142 contains 00, 01, or 10 (signifying a memory access operation), then alpha field 3052 (EVEX byte 3, bit [7] - EH) is interpreted as an eviction hint (EH) field 3052B and beta field 3054 (EVEX byte 3, bits [6:4] - SSS) is interpreted as a 3-bit data manipulation field 3054C.

[0294] When U=1, the alpha field 3052 (EVEX byte 3, bit [7] - EH) is interpreted as the write mask control (Z) field 3052C. If U=1 and the MOD field 3142 contains 11 (indicating a non-memory access operation), part of the beta field 3054 (EVEX byte 3, bit [4] - S0) is interpreted as the RL field 3057A, and if it contains 1 (round 3057A.1), the rest of the beta field 3054 (EVEX byte 3, bits [6-5] - S 2-1) is interpreted as the round operation field 3059A, and if the RL field 3057A contains 0 (VSIZE3057.A2), the remainder of the beta field 3054 (EVEX byte 3, bits [6-5] - S 2-1 ) is the vector length field 3059B (EVEX byte 3, bits [6-5] - L 1-0 ). When U=1 and the MOD field 3142 contains 00, 01, or 10 (indicating a memory access operation), the beta field 3054 (EVEX byte 3, bits [6:4] - SSS) is interpreted as the vector length field 3059B (EVEX byte 3, bits [6-5] - L 1-0 ) and broadcast field 3057B (EVEX byte 3, bit [4]-B).

[0295] [Example Register Architecture] Figure 32 is a block diagram of a register architecture 3200 according to one embodiment of the present disclosure. In the illustrated embodiment, there are 32 vector registers 3210 that are 512 bits wide. These registers are referenced as zmm0-zmm31. The lower 256 bits of the lower 16 zmm registers are overlaid onto registers ymm0-16. The lower 128 bits of the lower 16 zmm registers (the lower 128 bits of the ymm registers) are overlaid onto registers xmm0-15. The vector-specific instruction format 3100 operates on these overlaid register files as shown in the following table: [Table 1]

[0296] In other words, the vector length field 3059B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the previous length, and instruction templates without a vector length field 3059B operate on the maximum vector length. Furthermore, in one embodiment, the class B instruction templates of the specific vector friendly instruction format 3100 operate on packed or scalar single-precision / double-precision floating-point data, and packed or scalar integer data. Scalar operations are operations performed on the lowest data element position in a zmm / ymm / xmm register. The higher data element positions either remain the same as they were before the instruction or are zeroed out depending on the embodiment.

[0297] Write Mask Registers 3215: In the illustrated embodiment, there are eight write mask registers (k0-k7), each 64 bits in size. In an alternative embodiment, the write mask registers 3215 are 16 bits in size. As previously mentioned, in one embodiment of the present disclosure, vector mask register k0 cannot be used as a write mask; if an encoding that would normally indicate k0 is used for a write mask, selecting a hardwired write mask of 0xFFFF effectively disables write masking for that instruction.

[0298] General-purpose registers 3225: In the illustrated embodiment, there are sixteen 64-bit general-purpose registers that are used with existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0299] Scalar floating-point stack register file (x87 stack) 3245, to which MMX packed integer flat register file 3250 is aliased: in the illustrated embodiment, the x87 stack is an 8-element stack used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set extensions. MMX registers are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between MMX and XMM registers.

[0300] Alternative embodiments of the present disclosure may use wider or narrower registers. Additionally, alternative embodiments of the present disclosure may use more, fewer, or different register files and registers.

[0301] [Exemplary Core Architectures, Processors, and Computer Architectures] Processor cores may be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) general-purpose in-order cores for general-purpose computing, 2) high-performance general-purpose out-of-order cores for general-purpose computing, and 3) specialized cores primarily for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) CPUs that include one or more general-purpose in-order cores for general-purpose computing and / or one or more general-purpose out-of-order cores for general-purpose computing, and 2) co-processors that include one or more specialized cores primarily for graphics and / or scientific (throughput). Such different processors result in different computer system architectures, which may include: 1) coprocessors on a separate chip from the CPU, 2) coprocessors on a separate die in the same package as the CPU, 3) coprocessors on the same die as the CPU (in which case such coprocessors may be referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or dedicated cores), and 4) systems-on-chips that may include the described CPU, the above-mentioned coprocessors, and additional functionality on the same die (which may be referred to as application cores or application processors). Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.

[0302] [Example Core Architecture] [In-order and out-of-order core block diagram] Figure 33A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline, according to an embodiment of the present disclosure. Figure 33B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core included in a processor, according to an embodiment of the present disclosure. The solid lined boxes in Figures 33A and 33B indicate the in-order pipeline and in-order core, with the optional addition of dashed lined boxes indicating the register renaming, out-of-order issue / execution pipeline and core. The out-of-order aspects will be described assuming that the in-order aspects are a subset of the out-of-order aspects.

[0303] In FIG. 33A , processor pipeline 3300 includes a fetch stage 3302, a length decode stage 3304, a decode stage 3306, an allocation stage 3308, a renaming stage 3310, a scheduling (also known as dispatch or issue) stage 3312, a register read / memory read stage 3314, an execution stage 3316, a writeback / memory write stage 3318, an exception handling stage 3322, and a commit stage 3324.

[0304] 33B shows a processor core 3390 including a front end unit 3330 coupled to an execution engine unit 3350, both of which are coupled to a memory unit 3370. Core 3390 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, core 3390 may be a special-purpose core such as, for example, a network or communications core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, or a graphics core.

[0305] The front-end unit 3330 includes a branch prediction unit 3332 coupled to an instruction cache unit 3334, which is coupled to an instruction translation lookaside buffer (TLB) 3336, which is coupled to an instruction fetch unit 3338, which is coupled to a decode unit 3340. The decode unit 3340 (e.g., decode circuitry) decodes instructions (e.g., macroinstructions) and may generate as output one or more micro-ops, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from, or otherwise reflect, or are derived from, the original instruction. The decode unit 3340 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, a lookup table, a hardware implementation, a programmable logic array (PLA), a microcode read-only memory (ROM), etc. In one embodiment, core 3390 includes a microcode ROM or other medium that stores microcode for particular macro instructions (e.g., in decode unit 3340 or otherwise within front end unit 3330). Decode unit 3340 is coupled to rename / allocator unit 3352 within execution engine unit 3350.

[0306] The execution engine unit 3350 includes a rename / allocator unit 3352 coupled to a retirement unit 3354 and a set of one or more scheduler units 3356. The scheduler units 3356 represent any number of different schedulers, including reservation stations, central instruction windows, etc. The scheduler units 3356 are coupled to physical register file units 3358. Each of the physical register file units 3358 represents one or more physical register files, each different physical register file storing one or more different data types, such as, for example, scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer, which is the address of the next instruction to be executed), etc. In one embodiment, the physical register file units 3358 have a vector register unit, a write mask register unit, and a scalar register unit. These register units may provide the vector registers, vector mask registers, and general-purpose registers of the architecture. The physical register files unit 3358 is overlaid with the retirement unit 3354 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer and retirement register file, using a future file, a history buffer and retirement register file, using a register map and pool of registers, etc.). The retirement unit 3354 and the physical register files unit 3358 are coupled to the execution cluster 3360. The execution cluster 3360 includes a set of one or more execution units 3362 (e.g., execution circuits) and a set of one or more memory access units 3364. The execution units 3362 may perform various operations (e.g., shift, add, subtract, multiply) on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point).Some embodiments may include multiple execution units dedicated to a particular function or set of functions, while other embodiments may include only one execution unit or multiple execution units that all perform all functions. Since particular embodiments create separate pipelines for particular types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline each have their own scheduler unit, physical register file unit, and / or execution cluster, and particular embodiments are implemented with a separate memory access pipeline in which only the execution cluster of this pipeline has memory access unit 3364), scheduler unit 3356, physical register file unit 3358, and execution cluster 3360 are sometimes shown as multiple. It should also be understood that when separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, while the rest may be in-order.

[0307] The set of memory access units 3364 is coupled to a memory unit 3370, which includes a data TLB unit 3372 coupled to a data cache unit 3374 that is coupled to a level 2 (L2) cache unit 3376. In an exemplary embodiment, the memory access units 3364 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 3372 in the memory unit 3370. The instruction cache unit 3334 is further coupled to a level 2 (L2) cache unit 3376 in the memory unit 3370. The L2 cache unit 3376 is coupled to one or more other levels of cache and ultimately to main memory.

[0308] By way of example, an exemplary register renaming, out-of-order issue / execution core architecture may implement pipeline 3300 as follows: 1) instruction fetch 3338 performs fetch and length decode stages 3302 and 3304; 2) decode unit 3340 performs decode stage 3306; 3) rename / allocator unit 3352 performs allocation stage 3308 and renaming stage 3310; 4) scheduler unit 3356 performs schedule stage 3312; 5) physical register file unit 3358 and memory unit 3370 perform register read / memory read stage 3314 and execution cluster 3360 performs execution stage 3316; 6) memory unit 3370 and physical register file unit 3358 perform writeback / memory write stage 3318; 7) various units may be associated with exception handling stage 3322; and 8) retirement unit 3354 and physical register file unit 3358 perform commit stage 3324.

[0309] Core 3390 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions), the MIPS instruction set from MIPS Technologies of Sunnyvale, California, or the ARM instruction set (with optional additional extensions such as NEON) from ARM Holdings of Sunnyvale, California), including the instructions described herein. In one embodiment, core 3390 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), which allows operations used by many multimedia applications to be performed using packed data.

[0310] It will be appreciated that a core may support multithreading (executing two or more parallel sets of operations or threads) in various ways, including time-sliced ​​multithreading, simultaneous multithreading (where a single physical core provides a logical core for each thread that the physical core is simultaneously multithreading), or a combination thereof (e.g., time-sliced ​​fetch and decode followed by simultaneous multithreading, such as in Intel® Hyper-Threading Technology).

[0311] While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. The illustrated processor embodiment also includes separate instruction cache unit 3334 and data cache unit 3374, as well as a shared L2 cache unit 3376, although alternative embodiments may have a single internal cache, such as a level 1 (L1) internal cache or multiple levels of internal cache, for both instructions and data. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and / or processor. Alternatively, all of the cache may be external to the core and / or processor.

[0312] [Specific Exemplary In-Order Core Architecture] 34A and 34B show block diagrams of a more specific exemplary in-order core architecture, where a core would be one of several logic blocks (including other cores of the same and / or different types) within a chip. The logic block communicates with some fixed-function logic, memory I / O interfaces, and other necessary I / O logic, depending on the application, through a high-bandwidth interconnection network (e.g., a ring network).

[0313] FIG. 34A is a block diagram of a single processor core with its connection to an on-die interconnect network 3402 and its local subset of a level 2 (L2) cache 3404, in accordance with an embodiment of the present disclosure. In one embodiment, an instruction decode unit 3400 supports the x86 instruction set with the packed data instruction set extension. An L1 cache 3406 allows low-latency accesses to cache memory into the scalar and vector units. In one embodiment (to simplify the design), the scalar unit 3408 and the vector unit 3410 use separate register sets (scalar registers 3412 and vector registers 3414, respectively), and data transferred between them is written to memory and then read back from the level 1 (L1) cache 3406; however, alternative embodiments of the present disclosure may use different approaches (e.g., using a single register set or including a communication path that allows data to be transferred between the two register files without being written or read back).

[0314] The local subset of L2 cache 3404 is part of a global L2 cache that is divided into separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset of L2 cache 3404. Data read by a processor core is stored in its L2 cache subset 3404 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 3404 and is flushed from other subsets as needed. The ring network ensures coherency of shared data. The ring network is bidirectional, allowing agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. Each ring data path is 1012 bits wide per direction.

[0315] Figure 34B is an expanded view of a portion of the processor core in Figure 34A according to an embodiment of the present disclosure. Figure 34B includes an L1 data cache 3406A, which is part of the L1 cache 3404, and further details regarding the vector unit 3410 and vector registers 3414. Specifically, the vector unit 3410 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 3428) that executes one or more integer, single-precision floating-point, and double-precision floating-point instructions. The VPU supports swizzling of register inputs using swizzle unit 3420, numeric conversion using numeric conversion units 3422A-B, and duplication of memory inputs using duplication unit 3424. A write mask register 3426 allows for predicating resulting vector writes.

[0316] 35 is a block diagram of a processor 3500 that may have more than one core, may have an integrated memory controller, and may have integrated graphics, according to an embodiment of the present disclosure. The solid lined box in FIG. 35 illustrates a processor 3500 with a single core 3502A, a system agent 3510, a set of one or more bus controller units 3516, and an optional additional dashed lined box illustrates an alternative processor 3500 with multiple cores 3502A-N, a set of one or more integrated memory controller units 3514 within the system agent unit 3510, and dedicated logic 3508.

[0317] Accordingly, different implementations of processor 3500 may include: 1) a CPU in which special purpose logic 3508 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores) and cores 3502A-N are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a coprocessor in which cores 3502A-N are multiple special purpose cores primarily intended for graphics and / or scientific (throughput); and 3) a coprocessor in which cores 3502A-N are multiple general purpose in-order cores. Thus, processor 3500 may be a general purpose processor, coprocessor, or special purpose processor, such as a network or communications processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), high throughput multiple integrated core (MIC) coprocessor (containing 30 or more cores), embedded processor, etc. The processor may be implemented on one or more chips. The processor 3500 may be part of and / or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

[0318] The memory hierarchy includes one or more levels of cache within the core, a set or set of shared cache units 3506, and an external memory (not shown) coupled to a set of integrated memory controller units 3514. The set of shared cache units 3506 may include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other level caches, a last level cache (LLC), and / or combinations thereof. In one embodiment, a ring-based interconnect unit 3512 interconnects the integrated graphics logic 3508, the set of shared cache units 3506, and the system agent unit 3510 / integrated memory controller unit 3514, although alternative embodiments may use any number of known techniques to interconnect such units. In one embodiment, coherency is maintained between one or more cache units 3506 and the cores 3502A-N.

[0319] In some embodiments, one or more of the cores 3502A-N are capable of multithreading. The system agent 3510 includes those components that coordinate and operate the cores 3502A-N. The system agent unit 3510 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or may include the logic and components necessary to coordinate the power state of the cores 3502A-N and the integrated graphics logic 3508. The display unit is for driving one or more externally connected displays.

[0320] The cores 3502A-N may be homogeneous or heterogeneous with respect to architectural instruction sets, i.e., two or more of the cores 3502A-N may be capable of executing the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

[0321] [Example Computer Architecture] 36-39 are block diagrams of exemplary computer architectures. Other system designs and configurations known in the art are also suitable for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, mobile phones, portable media players, handheld devices, and various other electronic devices. In general, a wide variety of systems or electronic devices capable of incorporating the processors and / or other execution logic disclosed herein are generally suitable.

[0322] 36, a block diagram of a system 3600 according to one embodiment of the present disclosure is shown. The system 3600 may include one or more processors 3610, 3615, which are coupled to a controller hub 3620. In one embodiment, the controller hub 3620 includes a graphics memory controller hub (GMCH) 3690 and an input / output hub (IOH) 3650 (which may be on separate chips). The GMCH 3690 includes a memory and graphics controller, to which a memory 3640 and a coprocessor 3645 are coupled. The IOH 3650 couples input / output (I / O) devices 3660 to the GMCH 3690. Alternatively, one or both of the memory and graphics controller are integrated within the processor (as described herein), and the memory 3640 and coprocessor 3645 are coupled directly to the processor 3610 and the controller hub 3620 in a single chip with the IOH 3650. The memory 3640 may include, for example, matrix acceleration code 3640A that stores code that, when executed, causes the processor to perform any of the methods of this disclosure.

[0323] An additional processor 3615 of an optional nature is indicated in Figure 36 using dashed lines. Each processor 3610, 3615 may include one or more of the processing cores described herein and may be some version of processor 3500.

[0324] The memory 3640 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. In at least one embodiment, the controller hub 3620 communicates with the processors 3610, 3615 via a multi-drop bus such as a front side bus (FSB), a point-to-point interface such as a quick path interconnect (QPI), or similar connection 3695.

[0325] In one embodiment, coprocessor 3645 is a special-purpose processor, such as a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc. In one embodiment, controller hub 3620 may include an integrated graphics accelerator.

[0326] There may be a wide range of differences between the physical resources 3610, 3615 with respect to a wide range of value criteria, including architectural characteristics, microarchitectural characteristics, thermal characteristics, power consumption characteristics, and the like.

[0327] In one embodiment, processor 3610 executes instructions that control general types of data processing operations. Coprocessor instructions may be embedded within the instructions. Processor 3610 recognizes these coprocessor instructions as types of instructions that should be executed by an attached coprocessor 3645. Accordingly, processor 3610 issues these coprocessor instructions (or control signals representing the coprocessor instructions) over a coprocessor bus or other interconnection to coprocessor 3645. Coprocessor 3645 accepts and executes the received coprocessor instructions.

[0328] Referring now to Figure 37, a block diagram of a first, more specific exemplary system 3700 is shown, in accordance with one embodiment of the present disclosure. As shown in Figure 37, multiprocessor system 3700 is a point-to-point interconnect system and includes a first processor 3770 and a second processor 3780 coupled via a point-to-point interconnect 3750. Each of processors 3770 and 3780 may be some version of processor 3500. In one embodiment of the present disclosure, processors 3770 and 3780 are processors 3610 and 3615, respectively, and coprocessor 3738 is coprocessor 3645. In another embodiment, processors 3770 and 3780 are processor 3610 and coprocessor 3645, respectively.

[0329] Processors 3770 and 3780 are shown to include integrated memory controller (IMC) units 3772 and 3782, respectively. Processor 3770 also includes point-to-point (PP) interfaces 3776 and 3778 as part of its bus controller unit, and similarly, second processor 3780 includes PP interfaces 3786 and 3788. Processors 3770, 3780 may exchange information using PP interface circuits 3778, 3788 via point-to-point (PP) interface 3750. As shown in FIG. 37 , IMCs 3772 and 3782 couple the processors to their respective memories, i.e., memory 3732 and memory 3734. These memories may be portions of main memory locally attached to the respective processors.

[0330] Processors 3770, 3780 may each exchange information with chipset 3790 using point-to-point interface circuits 3776, 3794, 3786, 3798 via respective PP interfaces 3752, 3754. Chipset 3790 may optionally exchange information with coprocessor 3738 via high performance interface 3739. In one embodiment, coprocessor 3738 is a special purpose processor, such as, for example, a high throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc.

[0331] A shared cache (not shown) may be included either external to the processor or both processors and may be further connected to the processors via the PP interconnect so that when the processors are placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0332] Chipset 3790 may be coupled to a first bus 3716 via an interface 3796. In one embodiment, first bus 3716 may be a bus such as a Peripheral Component Interconnect (PCI) bus, or a PCI Express bus or another third generation I / O interconnect bus, although the scope of the disclosure is not so limited.

[0333] As shown in FIG. 37 , various I / O devices 3714 may be coupled to the first bus 3716, along with a bus bridge 3718 coupling the first bus 3716 to a second bus 3720. In one embodiment, one or more additional processors 3715 are coupled to the first bus 3716. The additional processors may be coprocessors, high-throughput MIC processors, accelerators for GPGPUs (e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processors. In one embodiment, the second bus 3720 may be a low pin count (LPC) bus. In one embodiment, various devices may be coupled to the second bus 3720, including, for example, a keyboard and / or mouse 3722, a communication device 3727, and a storage unit 3728, such as a disk drive or other mass storage device, which may contain instructions / code and data 3730. Additionally, audio I / O 3724 may be coupled to the second bus 3720. Note that other architectures are possible, for example, instead of the point-to-point architecture of Figure 37, the system may implement a multi-drop bus architecture or other such architecture.

[0334] Referring now to Figure 38, a block diagram of a second, more specific exemplary system 3800 is shown, according to one embodiment of the present disclosure. Like elements in Figures 37 and 38 are labeled with like reference numerals, and certain aspects of Figure 37 have been omitted from Figure 38 to avoid obscuring other aspects of Figure 38.

[0335] Figure 38 shows that processors 3770, 3780 may include integrated memory and may also include I / O control logic ("CL") 3772 and 3782, respectively. Thus, CL 3772, 3782 include integrated memory controller units and include I / O control logic. Figure 38 shows that not only are memory 3732, 3734 coupled to CL 3772, 3782, but I / O devices 3814 are also coupled to control logic 3772, 3782. Legacy I / O devices 3815 are coupled to chipset 3790.

[0336] Referring now to FIG. 39, a block diagram of an SoC 3900 according to one embodiment of the present disclosure is shown. Similar elements to those in FIG. 35 are labeled with similar reference numerals. Also, dashed boxes indicate optional functionality on a more advanced SoC. In FIG. 39, an interconnect unit 3902 is coupled to an application processor 3910 including a set of one or more cores 3502A-N and a shared cache unit 3506, a system agent unit 3510, a bus controller unit 3516, an integrated memory controller unit 3514, a set or one or more coprocessors 3920 that may include integrated graphics logic, an image processor, an audio processor, and a video processor, a static random access memory (SRAM) unit 3930, a direct memory access (DMA) unit 3932, and a display unit 3940 for coupling to one or more external displays. In one embodiment, the coprocessor 3920 includes a special-purpose processor, such as a network or communications processor, a compression engine, a GPGPU, a high-throughput MIC processor, or an embedded processor.

[0337] Embodiments (e.g., mechanisms) disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the present disclosure may be implemented as a computer program or program code running on a programmable system having at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0338] 37 may be applied to input instructions to perform the functions described herein and to generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0339] The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. Indeed, the mechanisms described herein are not limited in scope to any particular programming language. In either case, the language may be a compiled or interpreted language.

[0340] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium that represent various logic within a processor, which, when read by a machine, cause the machine to assemble logic to perform the techniques described herein. Such representations, known as "IP cores," may be stored on tangible machine-readable media and supplied to various customers or manufacturing facilities for loading into manufacturing machines that actually create the logic or processor.

[0341] Such machine-readable storage media may include, but are not limited to, non-transitory, tangible configurations of articles manufactured or formed by a machine or device, including storage media such as hard disks, floppy disks, optical disks, compact disk-read only memory (CD-ROM), compact disk-rewriteable (CD-RW), and any other type of disk, including magneto-optical disks, read-only memory (ROM), random access memory (RAM), such as dynamic random access memory (DRAM), static random access memory (SRAM), semiconductor devices, such as erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM), magnetic or optical cards, or any other type of medium suitable for storing electronic instructions.

[0342] Accordingly, embodiments of the present disclosure also include non-transitory, tangible, machine-readable media that include instructions or design data, such as hardware description languages ​​(HDLs), that define features of the structures, circuits, devices, processors, and / or systems described herein. Such embodiments may also be referred to as program products.

[0343] [Emulation (including binary conversion, code morphing, etc.)] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may translate, morph, emulate, or otherwise convert (e.g., using static binary translation, dynamic binary translation including dynamic compilation) the instructions into one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on-processor, off-processor, or partially on-processor and partially off-processor.

[0344] Figure 40 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set, according to an embodiment of the present disclosure. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 40 shows that a program in a high-level language 4002 may be compiled using an x86 compiler 4004 to generate x86 binary code 4006 that may be natively executed by a processor 4016 having at least one x86 instruction set core. Processor with at least one x86 instruction set core 4016 represents any processor capable of performing substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of an Intel x86 instruction set core, or (2) object code versions of applications or other software intended to run on an Intel processor with at least one x86 instruction set core, to achieve substantially the same results. x86 compiler 4004 represents a compiler operable to generate x86 binary code 4006 (e.g., object code) executable on processor with at least one x86 instruction set core 4016, with or without additional linking steps.Similarly, FIG. 40 shows that a program in high-level language 4002 may be compiled using an alternative instruction set compiler 4008 to generate alternative instruction set binary code 4010, which may be natively executed by a processor 4014 that does not have at least one x86 instruction set core (e.g., a processor that executes the MIPS instruction set from MIPS Technologies of Sunnyvale, California, and / or has a core that executes the ARM instruction set from ARM Holdings of Sunnyvale, California). An instruction converter 4012 is used to convert x86 binary code 4006 into code that can be natively executed by a processor 4014 that does not have an x86 instruction set core. This converted code is unlikely to be identical to alternative instruction set binary code 4010 because an instruction converter capable of this conversion would be difficult to manufacture. However, the converted code implements common operations and is composed of instructions from the alternative instruction set. Thus, instruction converter 4012 represents software, firmware, hardware, or a combination thereof that enables a processor or other electronic device that does not have an x86 instruction set processor or core to execute x86 binary code 4006, via emulation, simulation, or any other process. (Item 1) A matrix operation accelerator circuit including a two-dimensional grid of fused multiply-accumulate circuits; a first plurality of registers coupled to the matrix operation accelerator circuit, the first plurality of registers representing a first input two-dimensional matrix; a second plurality of registers coupled to the matrix operation accelerator circuit and representing a second input two-dimensional matrix; a decoder of a hardware processor core coupled to the matrix operation accelerator circuit for decoding a single instruction into a decoded single instruction, the single instruction including a field identifying a result storage; an execution circuit in the hardware processor core that executes the decoded single instruction to: loading the first input two-dimensional matrix from the first plurality of registers into a first buffer of a two-dimensional grid of the fused multiply-accumulate circuit; checking whether a second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores a previous input two-dimensional matrix that is identical to the second input two-dimensional matrix; if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores, from execution of a previous instruction, the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix; preventing reclamation of the second buffer between execution of the previous instruction and the decoded single instruction; performing an operation on the first input two-dimensional matrix from the first buffer and the immediately preceding input two-dimensional matrix from the second buffer to generate a result; storing the results in the result storage; if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit does not store the immediately preceding input two-dimensional matrix from execution of the previous instruction that is identical to the second input two-dimensional matrix; loading the second input two-dimensional matrix into the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit; performing an operation on the first input two-dimensional matrix from the first buffer and the second input two-dimensional matrix from the second buffer to generate a result; an execution circuit that stores the result in the result storage; An apparatus comprising: (Item 2) The device described in Item 1, wherein if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit does not store the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from the execution of the previous instruction, the matrix operation accelerator circuit initiates reclamation of the second buffer between the execution of the previous instruction and the decoded single instruction. (Item 3) The matrix operation accelerator circuit assigns an identification value to each of a plurality of registers representing an input two-dimensional matrix, and the check whether the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix includes comparing the respective identification values ​​of the corresponding input two-dimensional matrices from the previous instruction and the single instruction. (Item 4) The device described in Item 3, wherein the matrix operation accelerator circuit assigns different identification values ​​to the second plurality of registers so as to store an input two-dimensional matrix for a next instruction. (Item 5) The device described in Item 1, wherein if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from execution of the previous instruction, the matrix operation accelerator circuit does not load the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit during execution of the decoded single instruction. (Item 6) The device described in Item 1, wherein the result storage is a third plurality of registers representing at least one output two-dimensional matrix formed by execution of the decoded single instruction. (Item 7) The apparatus described in Item 1, wherein the operation includes transmitting each output of each first appropriate subset of fused multiply-accumulate circuits of the two-dimensional grid downstream to each input of each second appropriate subset of fused multiply-accumulate circuits of the two-dimensional grid to form the result. (Item 8) The apparatus described in Item 7, wherein a first suitable subset of the fused multiply-accumulate circuits is one of the rows or columns of a two-dimensional grid of the fused multiply-accumulate circuits, and a second suitable subset of the fused multiply-accumulate circuits is the other of the rows or columns of the two-dimensional grid of the fused multiply-accumulate circuits. 9. A method for decoding a single instruction into a decoded single instruction using a decoder of a hardware processor core, the hardware processor core being coupled to a matrix operation accelerator circuit including a two-dimensional grid of fused multiply-accumulate circuits, the matrix operation accelerator circuit being coupled to a first plurality of registers representing a first input two-dimensional matrix and a second plurality of registers representing a second input two-dimensional matrix, the single instruction including a field identifying a result storage; executing the decoded single instruction using execution circuitry of the hardware processor core; loading the first input two-dimensional matrix from the first plurality of registers into a first buffer of a two-dimensional grid of the fused multiply-accumulate circuit; checking whether a second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores a previous input two-dimensional matrix that is identical to the second input two-dimensional matrix; if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores, from execution of a previous instruction, the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix; preventing reclamation of the second buffer between execution of the previous instruction and the decoded single instruction; performing an operation on the first input two-dimensional matrix from the first buffer and the immediately preceding input two-dimensional matrix from the second buffer to generate a result; storing the results in the result storage; if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit does not store the immediately preceding input two-dimensional matrix from execution of the previous instruction that is identical to the second input two-dimensional matrix; loading the second input two-dimensional matrix into the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit; performing an operation on the first input two-dimensional matrix from the first buffer and the second input two-dimensional matrix from the second buffer to generate a result; storing the results in the results storage; A method comprising: (Item 10) The method described in Item 9 further includes a step of initiating reclamation of the second buffer between execution of the previous instruction and the decoded single instruction if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit does not store the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from execution of the previous instruction. (Item 11) The method described in Item 9 further includes a step of assigning an identification value to each of a plurality of registers representing an input two-dimensional matrix, and the check whether the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix includes a step of comparing the respective identification values ​​of the corresponding input two-dimensional matrices from the previous instruction and the single instruction. (Item 12) The method of item 11, further comprising the step of assigning different identification values ​​to the second plurality of registers so as to store an input two-dimensional matrix for a next instruction. (Item 13) The method described in Item 9 further includes a step of not loading the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit during execution of the decoded single instruction if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from execution of the previous instruction. (Item 14) The method of item 9, wherein the result storage is a third plurality of registers representing at least one output two-dimensional matrix formed by execution of the decoded single instruction. (Item 15) The method described in Item 9, wherein the operation includes sending each output of each first appropriate subset of fused multiply-accumulate circuits of the two-dimensional grid downstream to each input of each second appropriate subset of fused multiply-accumulate circuits of the two-dimensional grid to form the result. (Item 16) The method described in Item 15, wherein a first suitable subset of the fused multiply-accumulate circuits is one of the rows or columns of a two-dimensional grid of the fused multiply-accumulate circuits, and a second suitable subset of the fused multiply-accumulate circuits is the other of the rows or columns of the two-dimensional grid of the fused multiply-accumulate circuits. (Item 17) A non-transitory machine-readable medium storing code that, when executed by a machine, causes the machine to perform a method, the method comprising: decoding, using a decoder of a hardware processor core, a single instruction into a decoded single instruction, the hardware processor core being coupled to a matrix operation accelerator circuit including a two-dimensional grid of fused multiply-accumulate circuits, the matrix operation accelerator circuit being coupled to a first plurality of registers representing a first input two-dimensional matrix and a second plurality of registers representing a second input two-dimensional matrix, the single instruction comprising a field identifying result storage; executing the decoded single instruction using execution circuitry of the hardware processor core; loading the first input two-dimensional matrix from the first plurality of registers into a first buffer of a two-dimensional grid of the fused multiply-accumulate circuit; checking whether a second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores a previous input two-dimensional matrix that is identical to the second input two-dimensional matrix; if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores, from execution of a previous instruction, the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix; preventing reclamation of the second buffer between execution of the previous instruction and the decoded single instruction; performing an operation on the first input two-dimensional matrix from the first buffer and the immediately preceding input two-dimensional matrix from the second buffer to generate a result; storing the results in the result storage; if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit does not store the immediately preceding input two-dimensional matrix from execution of the previous instruction that is identical to the second input two-dimensional matrix; loading the second input two-dimensional matrix into the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit; performing an operation on the first input two-dimensional matrix from the first buffer and the second input two-dimensional matrix from the second buffer to generate a result; storing the results in the results storage; a non-transitory machine-readable medium, including (Item 18) The non-transitory machine-readable medium described in Item 17, further comprising a step of initiating reclamation of the second buffer between execution of the previous instruction and the decoded single instruction if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit does not store the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from execution of the previous instruction. (Item 19) A non-transitory machine-readable medium as described in Item 17, further comprising a step of assigning an identification value to each of a plurality of registers representing an input two-dimensional matrix, and wherein the check as to whether the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix comprises a step of comparing the respective identification values ​​of the corresponding input two-dimensional matrices from the previous instruction and the single instruction. (Item 20) The non-transitory machine-readable medium described in Item 19, further comprising a step of assigning different identification values ​​to the second plurality of registers so as to store an input two-dimensional matrix for a next instruction. (Item 21) The non-transitory machine-readable medium described in Item 17, further comprising a step of not loading the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit during execution of the decoded single instruction if the second buffer of the two-dimensional grid of the fused multiply-accumulate circuit stores the immediately preceding input two-dimensional matrix that is identical to the second input two-dimensional matrix from execution of the previous instruction. (Item 22) The non-transitory machine-readable medium described in Item 17, wherein the result storage is a third plurality of registers representing at least one output two-dimensional matrix formed by execution of the decoded single instruction. (Item 23) A non-transitory machine-readable medium as described in Item 17, wherein the operation includes transmitting each output of each first appropriate subset of fused multiply-accumulate circuits of the two-dimensional grid downstream to each input of each second appropriate subset of fused multiply-accumulate circuits of the two-dimensional grid to form the result. (Item 24) A non-transitory machine-readable medium as described in Item 23, wherein a first suitable subset of the fused multiply-accumulate circuits is one of the rows or columns of a two-dimensional grid of the fused multiply-accumulate circuits, and a second suitable subset of the fused multiply-accumulate circuits is the other of the rows or columns of the two-dimensional grid of the fused multiply-accumulate circuits.

Claims

1. a first one or more vector registers for storing a first plurality of source matrix data elements; a second one or more vector registers for storing a second plurality of source matrix data elements, each source matrix data element of the first plurality of source matrix data elements and the second plurality of source matrix data elements having a first data element width; a third one or more vector registers for storing a plurality of accumulation matrix data elements, each accumulation matrix data element of the plurality of accumulation matrix data elements having a second data element width that is at least twice the first data element width; a matrix processing circuit operable with a plurality of processing lanes to execute a single matrix instruction to perform a corresponding plurality of multiplications in the plurality of processing lanes; an operand routing circuit for broadcasting a first source matrix data element of the first plurality of source matrix data elements to two or more processing lanes of the plurality of processing lanes in accordance with the single matrix instruction, wherein in each processing lane of the two or more processing lanes, the matrix processing circuit performs a corresponding multiplication of the first source matrix data element with a different data element of the second plurality of source matrix data elements to generate a corresponding product, the corresponding product being added to a corresponding accumulation matrix data element, and one or more other products of multiplications of respective data elements of the first plurality of source matrix data elements and the second plurality of source matrix data elements to generate a corresponding result matrix data element having the second data element width; and local buffer storage for storing at least a subset of the first plurality of source matrix data elements and the second plurality of source matrix data elements during execution of the single matrix instruction. Device.

2. Each processing lane has a processing lane width equal to the second data element width.

10. The apparatus of claim 1.

3. the first plurality of source matrix data elements and the second plurality of source matrix data elements comprise 16-bit floating point data elements; The accumulation matrix data elements include 32-bit floating-point data elements.

3. The device according to claim 1 or 2.

4. One or more matrix data elements in the subset of the first plurality of source matrix data elements or the second plurality of source matrix data elements are reused in multiple operations by the matrix processing circuitry.

4. An apparatus according to any one of claims 1 to 3.

5. The local buffer storage stores the subset of the first plurality of source matrix data elements and the subset of the second plurality of source matrix data elements.

4. An apparatus according to any one of claims 1 to 3.

6. the matrix processing circuit performs a matrix operation on the subset of the first plurality of source matrix data elements and the subset of the second plurality of source matrix data elements, stores corresponding result data elements in the local buffer storage, and combines the corresponding result data elements with subsequent result data elements of a subsequent matrix operation.

5. The apparatus of claim 4.

7. The matrix processing circuit prevents reclamation of at least a portion of the local buffer storage.

7. An apparatus according to any one of claims 1 to 6.

8. The matrix processing circuit includes a two-dimensional grid of processing elements arranged in the plurality of processing lanes.

8. An apparatus according to any one of claims 1 to 7.

9. further comprising an integrated circuit (IC); The IC has the first one or more vector registers, the second one or more vector registers, the third one or more vector registers, the matrix processing circuitry, and the operand routing circuitry.

9. An apparatus according to any one of claims 1 to 8.

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