Register reading method, device and equipment for cross-chip communication system
By generating and encapsulating read instructions through a cross-chip communication system, and reading register data across chips, the problem of the joint test working group interface being unable to read data across chips was solved, and efficient cross-chip data acquisition was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAMEN UNISOC TECH CO LTD
- Filing Date
- 2025-11-21
- Publication Date
- 2026-04-21
AI Technical Summary
In existing technologies, the joint test working group interface cannot enable register reading between different chips, and in particular, it cannot effectively acquire data across chips under complex conditions.
By generating a read instruction, the first peripheral bus is used to send it to the first transceiver device. The read instruction and multiple preset signals are encapsulated and sent to the second transceiver device for parsing. Finally, the data is read on the second peripheral bus and the data packet is returned to the first processor for parsing, thus realizing cross-chip register reading.
It enables cross-chip register reading under complex conditions, improves reading efficiency, supports data retransmission and dynamic baud rate switching, and simplifies the hardware architecture design of cross-chip communication systems.
Smart Images
Figure CN121900987A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of register reading technology, and in particular to a register reading method, apparatus and device for a cross-chip communication system. Background Technology
[0002] Register read is the process by which the processor quickly retrieves data from its internal registers. Registers are high-speed storage units located inside the processor, composed of flip-flops, and can temporarily store binary data. When the processor needs data, it triggers a read operation via control signals, outputting the data stored in the register to the processor's internal bus.
[0003] In related technologies, traditional register reading methods mostly rely on joint test workgroup interfaces and read registers on a single chip through transceiver devices. However, in complex situations, joint test workgroup interfaces cannot achieve register reading between different chips. Therefore, there is an urgent need for a method that can achieve cross-chip register reading. Summary of the Invention
[0004] This application provides a register reading method, apparatus, and device for cross-chip communication systems to solve the problem that joint test working group interfaces cannot achieve register reading between different chips under complex conditions.
[0005] In a first aspect, this application provides a register reading method for a cross-chip communication system, the cross-chip communication system comprising: a first chip and a second chip; the first chip comprising: a first processor, a first transceiver device, and a first peripheral bus; the second chip comprising: a second processor, a second transceiver device, and a second peripheral bus; the method comprising:
[0006] When it is necessary to read the registers under the second transceiver device, a read instruction is generated and sent to the first transceiver device through the first peripheral bus;
[0007] The first transceiver device is controlled to encapsulate the read instruction and multiple preset signals to obtain an encapsulated read instruction, and the encapsulated read instruction is sent to the second transceiver device, so that the second processor controls the second transceiver device to parse the encapsulated read instruction to obtain the read instruction, and sends the read instruction to the second peripheral bus, so that the second processor controls the second peripheral bus to read the registers connected to the second peripheral bus according to the read instruction to obtain multiple read data, and returns the multiple read data to the second transceiver device, so that the second processor controls the second transceiver device to encapsulate the multiple read data to obtain a read response data packet;
[0008] The first transceiver device is controlled to receive the read response data packet and parse the read response data packet to obtain the parsed read data;
[0009] The parsed read data is received through the first peripheral bus to complete the reading of the registers under the second transceiver device.
[0010] In one possible design, the first transceiver device includes a first master terminal, a first slave terminal, a first data transmit pin, and a first data input pin. Correspondingly, sending the read instruction to the first transceiver device via the first peripheral bus includes: sending the read instruction to the first slave terminal of the first transceiver device via the first peripheral bus. Correspondingly, controlling the first transceiver device to encapsulate the read instruction and multiple preset signals to obtain an encapsulated read instruction, and sending the encapsulated read instruction to the second transceiver device, includes: controlling the first slave terminal to encapsulate the read instruction and multiple preset signals to obtain an encapsulated read instruction, and sending the encapsulated read instruction to the second transceiver device via the first data transmit pin. Correspondingly, controlling the first transceiver device to receive the read response data packet and parse the read response data packet to obtain parsed read data includes: controlling the first master terminal to receive the read response data packet via the first data input pin and parse the read response data packet to obtain parsed read data.
[0011] In one possible design, the method further includes: when it is necessary to write to the registers of the second transceiver device, generating a write instruction and sending the write instruction to the first transceiver device via the first peripheral bus; controlling the first transceiver device to encapsulate the write instruction and multiple preset signals to obtain an encapsulated read instruction, and sending the encapsulated write instruction to the second transceiver device, so that the second processor controls the second transceiver device to parse the encapsulated write instruction to obtain the write instruction, and sending the write instruction to the second peripheral bus ... and The second processor controls the second peripheral bus to write to the registers mounted on the second peripheral bus according to the write instruction, thereby obtaining multiple write data. The processor then returns the multiple write data to the second transceiver device, causing the second processor to control the second transceiver device to encapsulate the multiple write data to obtain a write response data packet. The processor then controls the first transceiver device to receive the write response data packet and parse it to obtain parsed write data. Finally, the processor receives the parsed write data through the first peripheral bus to complete the writing to the registers of the second transceiver device.
[0012] In one possible design, sending the write instruction to the first transceiver device via the first peripheral bus includes: sending the write instruction to a first slave device on the first transceiver device via the first peripheral bus; correspondingly, controlling the first transceiver device to encapsulate the write instruction and multiple preset signals to obtain an encapsulated read instruction, and sending the encapsulated write instruction to the second transceiver device includes: controlling the first slave device to encapsulate the write instruction and multiple preset signals to obtain an encapsulated write instruction, and sending the encapsulated write instruction to the second transceiver device via the first data transmission pin; correspondingly, controlling the first transceiver device to receive the write response data packet and parse the write response data packet to obtain parsed write data includes: controlling the first master device to receive the write response data packet via the first data input pin and parse the write response data packet to obtain parsed write data.
[0013] Secondly, this application provides a register reading method for a cross-chip communication system, the cross-chip communication system comprising: a first chip and a second chip; the first chip comprising: a first processor, a first transceiver device, and a first peripheral bus; the second chip comprising: a second processor, a second transceiver device, and a second peripheral bus; the method comprising:
[0014] The processor controls the second transceiver device to receive an encapsulated read instruction sent by the first transceiver device. The encapsulated read instruction is obtained by the first processor controlling the first transceiver device to encapsulate the read instruction and multiple preset signals. The read instruction is sent by the first processor controlling the first peripheral bus to the first transceiver device. The read instruction is generated by the first processor when it needs to read the registers under the second transceiver device.
[0015] The second transceiver device is controlled to parse the encapsulated read instruction to obtain the read instruction, and then send the read instruction to the second peripheral bus;
[0016] Control the second peripheral bus, read the registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and return the multiple read data to the second transceiver device;
[0017] The second transceiver device is controlled to encapsulate the plurality of read data to obtain read response data packets, and the read response data packets are sent to the first transceiver device, so that the first processor controls the first transceiver device to parse the read response data packets to obtain parsed read data, and sends the parsed read data to the first processor through the first peripheral bus to complete the reading of the registers of the second transceiver device.
[0018] In one possible design, the second transceiver device includes a second master terminal, a second slave terminal, a second data transmit pin, and a second data input pin. Accordingly, controlling the second transceiver device to receive the encapsulated read instruction sent by the first transceiver device includes: controlling the second data input pin on the second transceiver device to receive the encapsulated read instruction sent by the first transceiver device. Accordingly, controlling the second transceiver device to parse the encapsulated read instruction to obtain the read instruction, and sending the read instruction to the second peripheral bus, includes: controlling the second master terminal to parse the encapsulated read instruction through the second data input pin to obtain the read instruction, and sending the read instruction to the second peripheral bus. The step of controlling the second peripheral bus to read registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and returning the multiple read data to the second transceiver device, includes: controlling the second peripheral bus to read registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and returning the multiple read data to the second host; correspondingly, the step of controlling the second transceiver device to encapsulate the multiple read data to obtain read response data packets, and sending the read response data packets to the first transceiver device, includes: controlling the second host to encapsulate the multiple read data to obtain read response data packets, and returning the read response data packets to the first transceiver device through the second data transmission pin.
[0019] Thirdly, this application provides a register reading device for a cross-chip communication system, the cross-chip communication system comprising: a first chip and a second chip; the first chip comprising: a first processor, a first transceiver device, and a first peripheral bus; the second chip comprising: a second processor, a second transceiver device, and a second peripheral bus, the device comprising:
[0020] The first transmitting module is used to generate a read instruction when it is necessary to read the registers under the second transceiver device, and send the read instruction to the first transceiver device through the first peripheral bus;
[0021] A first control module is configured to control the first transceiver device to encapsulate the read instruction and multiple preset signals to obtain an encapsulated read instruction, and send the encapsulated read instruction to the second transceiver device, so that the second processor controls the second transceiver device to parse the encapsulated read instruction to obtain the read instruction, and send the read instruction to the second peripheral bus, so that the second processor controls the second peripheral bus to read the registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and return the multiple read data to the second transceiver device, so that the second processor controls the second transceiver device to encapsulate the multiple read data to obtain a read response data packet;
[0022] The second control module is used to control the first transceiver device to receive the read response data packet and parse the read response data packet to obtain the parsed read data;
[0023] The first receiving module is used to receive the parsed read data through the first peripheral bus to complete the reading of the registers of the second transceiver device.
[0024] Fourthly, this application provides a register reading device for a cross-chip communication system, the cross-chip communication system comprising: a first chip and a second chip; the first chip comprising: a first processor, a first transceiver device, and a first peripheral bus; the second chip comprising: a second processor, a second transceiver device, and a second peripheral bus, the device comprising:
[0025] The first control module is used to control the second transceiver device and receive the encapsulated read instruction sent by the first transceiver device. The encapsulated read instruction is obtained by the first processor controlling the first transceiver device to encapsulate the read instruction and multiple preset signals. The read instruction is sent by the first processor controlling the first peripheral bus to the first transceiver device. The read instruction is generated by the first processor when it needs to read the registers under the second transceiver device.
[0026] The second control module is used to control the second transceiver device to parse the encapsulated read instruction to obtain the read instruction, and send the read instruction to the second peripheral bus;
[0027] The third control module is used to control the second peripheral bus, read the registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and return the multiple read data to the second transceiver device;
[0028] The fourth control module is used to control the second transceiver device to encapsulate the plurality of read data to obtain read response data packets, and send the read response data packets to the first transceiver device, so that the first processor controls the first transceiver device to parse the read response data packets to obtain parsed read data, and send the parsed read data to the first processor through the first peripheral bus to complete the reading of the lower register of the second transceiver device.
[0029] Fifthly, this application provides an electronic device, comprising: at least one processor and a memory;
[0030] The memory stores computer-executed instructions;
[0031] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the register reading method of the cross-chip communication system as described in the first aspect and various possible designs of the first aspect, as well as the register reading method of the cross-chip communication system as described in the second aspect and various possible designs of the second aspect.
[0032] Sixthly, this application provides a computer storage medium storing computer execution instructions, which, when executed by a processor, implement the register reading method for a cross-chip communication system as described in the first aspect and various possible designs of the first aspect, as well as the register reading method for a cross-chip communication system as described in the second aspect and various possible designs of the second aspect.
[0033] The register reading method, apparatus, and device for a cross-chip communication system provided in this application send a pre-generated read instruction to a first transceiver device via a first peripheral bus; control the first transceiver device to encapsulate the read instruction and multiple preset signals to obtain an encapsulated read instruction, and send the encapsulated read instruction to a second transceiver device, so that a second processor controls the second transceiver device to parse the encapsulated read instruction to obtain a read instruction, and send the read instruction to the second peripheral bus, so that the second processor controls the second peripheral bus to read the registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and return the multiple read data to the second transceiver device, so that the second processor controls the second transceiver device to encapsulate the multiple read data to obtain a read response data packet; control the first transceiver device to receive the read response data packet, and parse the read response data packet to obtain parsed read data; receive the parsed read data via the first peripheral bus, and realize cross-chip register reading in complex situations through a cross-chip communication system. Attached Figure Description
[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0035] Figure 1 This is a schematic diagram illustrating an application scenario of the register reading method for a cross-chip communication system provided in this application embodiment;
[0036] Figure 2 Flowchart of a register reading method for a cross-chip communication system provided in this application embodiment Figure 1 ;
[0037] Figure 3 Flowchart of a register reading method for a cross-chip communication system provided in this application embodiment Figure 2 ;
[0038] Figure 4 Schematic diagram of the register reading device for a cross-chip communication system provided in this application embodiment Figure 1 ;
[0039] Figure 5 Schematic diagram of the register reading device for a cross-chip communication system provided in this application embodiment Figure 2 ;
[0040] Figure 6A schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application;
[0041] Figure 7 This is a schematic diagram of the structure of the instruction or response data provided in the embodiments of this application. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0043] Register reading is the process by which the processor quickly retrieves data from its internal registers. Registers are high-speed storage units located within the processor, composed of flip-flops, and can temporarily store binary data. When the processor needs data, it triggers a read operation via control signals, outputting the data stored in the register to the processor's internal bus. Traditional register reading methods mostly rely on joint test workgroup interfaces and read registers on a single chip using transceiver devices. However, in complex situations, joint test workgroup interfaces cannot enable register reading between different chips. Therefore, a method for cross-chip register reading is urgently needed.
[0044] To address the aforementioned technical problems, this application proposes the following technical concept: Considering the read instruction generated by the first processor, the inventors encapsulate the read instruction and multiple preset signals using a first transceiver device to obtain an encapsulated read instruction. This encapsulated read instruction is then sent to a second transceiver device. The second transceiver device parses the encapsulated read instruction to obtain a new read instruction. The read instruction is then used to read registers mounted on the second peripheral bus corresponding to the second transceiver device, resulting in multiple read data. These multiple read data are then packaged to obtain a read response data packet, which is sent to the first transceiver device for parsing to obtain the parsed read data. Finally, the parsed read data is returned to the first processor, thus enabling cross-chip register reading.
[0045] Figure 1 This is a schematic diagram illustrating an application scenario of the register reading method for a cross-chip communication system provided in this application embodiment.
[0046] like Figure 1As shown, the cross-chip communication system in this scenario includes: a first chip 10 and a second chip 20; the first chip 10 includes: a first processor 101, a first transceiver device 102 and a first peripheral bus 103; the second chip 20 includes: a second processor 201, a second transceiver device 202 and a second peripheral bus 203.
[0047] The first processor 101 is communicatively connected to the first transceiver device 102 via the first peripheral bus 103; the second processor 201 is communicatively connected to the second transceiver device 202 via the second peripheral bus 203; and the first transceiver device 102 is communicatively connected to the second transceiver device 202.
[0048] The first peripheral bus 103 can be a single first peripheral bus 103 or multiple first peripheral buses 103; the second peripheral bus 203 can be a single second peripheral bus 203 or multiple second peripheral buses 203.
[0049] In addition, one or more registers are connected to the first peripheral bus 103; one or more registers are connected to the second peripheral bus 203.
[0050] In addition, the first transceiver device 102 includes: a first master terminal 1021, a first slave terminal 1022, a first data transmission pin 1023, and a first data input pin 1024.
[0051] The first host terminal 1021 and the first slave terminal 1022 are respectively connected to the first peripheral bus 103 for communication; the first data transmission pin 1023 and the first data input pin 1024 are respectively connected to the second transceiver device 202 for communication.
[0052] In addition, the second transceiver device 202 includes: a second master terminal 2021, a second slave terminal 2022, a second data transmission pin 2023, and a second data input pin 2024.
[0053] The second host terminal 2021 and the second slave terminal 2022 are respectively connected to the second peripheral bus 203; the second data transmission pin 2023 is connected to the first data input pin 1024; and the second data input pin 2024 is connected to the first data transmission pin 1023. A detailed description of the embodiments follows.
[0054] Figure 2 Flowchart of a register reading method for a cross-chip communication system provided in this application embodiment Figure 1 The execution entity in this embodiment can be Figure 1The first processor in the illustrated embodiment is not particularly limited in this embodiment. Figure 2 As shown, the method includes:
[0055] S201: When it is necessary to read the registers under the second transceiver device, a read instruction is generated and sent to the first transceiver device through the first peripheral bus.
[0056] In this embodiment, the second transceiver device can be an APB2 UART device or other devices.
[0057] Among them, the APB2 UART device is a UART (Universal Asynchronous Receiver / Transmitter) interface device based on APB2 (Advanced Peripheral Bus 2), which is mainly used to implement serial communication functions in embedded systems.
[0058] For example, the APB2 UART device is specifically an APB2 UART Device.
[0059] In this embodiment, the register is a core hardware unit used to control and implement serial communication functions, allowing the processor or bus interface to perform read and write operations, thereby configuring the UART's working mode, managing data transmission, and handling interrupts.
[0060] In this embodiment, the first peripheral bus can be an APB bus or other buses.
[0061] Among them, the APB bus, or Advanced Peripheral Bus, is a low-speed peripheral bus protocol in the bus architecture, mainly used to connect low-power, low-bandwidth peripherals in system-on-a-chip.
[0062] In this embodiment, the first transceiver device can be an APB2 UART device or other devices.
[0063] For example, the APB2 UART device is specifically an APB2 UART Module.
[0064] In this embodiment, the first transceiver device includes a first master terminal, a first slave terminal, a first data transmission pin, and a first data input pin; correspondingly, sending the read command to the first transceiver device via the first peripheral bus in step S201 specifically means sending the read command to the first slave terminal of the first transceiver device via the first peripheral bus.
[0065] For example, the first host is called the master, which usually refers to a component or device that plays a leading, controlling or coordinating role in the system.
[0066] For example, the first slave is the subordinate of the master, referring to a device or role that passively receives instructions and performs tasks during communication or task execution.
[0067] In this embodiment, the first data transmission pin can be TXD or other pins.
[0068] TXD, or Transmit Data, is typically used as a transmit data line or transmit pin.
[0069] In this embodiment, the first data input pin can be RXD or other pins.
[0070] Among them, RXD, which stands for Receive external Data, is usually used as a pin or signal terminal for receiving data and is generally used in pairs with TXD.
[0071] In this embodiment, read and write instructions can be, but are not limited to, 2-bit combinations, for example, 2'b10.
[0072] S202: Control the first transceiver device to encapsulate the read instruction and multiple preset signals to obtain the encapsulated read instruction, and send the encapsulated read instruction to the second transceiver device, so that the second processor controls the second transceiver device to parse the encapsulated read instruction to obtain the read instruction, and send the read instruction to the second peripheral bus, so that the second processor controls the second peripheral bus to read the registers connected to the second peripheral bus according to the read instruction to obtain multiple read data, and return the multiple read data to the second transceiver device, so that the second processor controls the second transceiver device to encapsulate the multiple read data to obtain a read reply data packet.
[0073] In this embodiment, the preset signal can be PCLK, PRESETn, PADDR[31:0], PPROT[2:0], PSELx, PENABLE, PWRITE, PWDATA[31:0], PSTRB[3:0], PREADY, PRDATA[31:0], or PSLVERR.
[0074] PCLK is the clock signal to the bus, and its signal description is: system clock, data is valid on the rising edge.
[0075] PRESETn is a reset signal to the bus. The signal description is: reset signal, active low. This signal can be directly connected to the system bus reset.
[0076] The direction of PADDR[31:0] is from the bus to the slave. The signal description is: APB bus address, maximum 32 bits.
[0077] The direction of PPROT[2:0] is from the bus to the slave. The signal description is: protection type signal, used to indicate the protection level of data transmission and command transmission. Three different levels can be set: normal, privileged and secure. The later the level, the higher the protection level.
[0078] PSELx is directed from the bus to the slave. The signal is described as follows: Slave selection signal. The bus generates this signal to indicate which slave device is selected. Only the selected slave will generate valid data transmissions such as write and read data.
[0079] The direction of PENABLE is from the bus to the slave. The signal description is: enable signal, used to indicate the second cycle of an APB transmission.
[0080] The direction of PWRITE is from the bus to the Slave. The signal description is as follows: This signal is used to indicate APB read and write operations. "1" indicates a write operation and "0" indicates a read operation.
[0081] The direction of PWDATA[31:0] is from the bus to the slave. The signal description is: write data. It is only valid when PWRITE is high. It can be 8-bit, 16-bit, or 32-bit.
[0082] The PSTRB[3:0] direction is from the bus to the Slave. The signal description is: optional, write byte enable, used to indicate which bytes of data are valid in the write data. The Slave will only write the valid bytes to the corresponding address.
[0083] The direction of PREADY is from Slave to bus. The signal description is: Ready signal, which is used to indicate whether the Slave is ready.
[0084] The direction of PRDATA[31:0] is from Slave to bus. The signal description is: read data. It is only valid when PWRITE is low. The data returned by Slave after receiving the read operation can be 8 bits, 16 bits, or 32 bits.
[0085] The direction of PSLVERR is from Slave to bus. Signal description: Optional. This signal is used to report errors occurring on the Slave and is active high. Some APB2 systems do not support this function on the following Slaves and treat the bus termination as a constant value "0".
[0086] Specifically, in step S202, controlling the first transceiver device to encapsulate the read command and multiple preset signals to obtain the encapsulated read command, and then sending the encapsulated read command to the second transceiver device, specifically:
[0087] The first slave device is controlled to encapsulate the read command and multiple preset signals to obtain the encapsulated read command, and then sends the encapsulated read command to the second transceiver device through the first data transmission pin.
[0088] For example, the preset signals are PADDR and PPROT.
[0089] Where PADDR is the read address and PPROT is the transfer security type.
[0090] In this embodiment, the UART in the transceiver device is typically configured to transmit 8 bits of data at a time, which is then encapsulated and transmitted in several UART segments. The data to be transmitted includes, but is not limited to: read / write instructions, the start bit of each UART transmission group, padding bits for each transmission, PADDR, PWDATA, PPROT, PLSVERR, PRDATA, etc.
[0091] Since UART transmissions typically do not allow all 0s or all 1s, the usual practice is to insert a meaningless bit at the beginning of each UART data transmission group. If the remaining 7 bits of the current UART transmission group are all 1s, this bit is set to 0; otherwise, it is set to 1. Furthermore, after determining the read instruction and multiple preset signals, it is also necessary to determine the padding bits for any remaining bits that are less than 8 bits. Therefore, an example of the encapsulated read instruction can be seen... Figure 7 A structural diagram of the corresponding instructions or responses and their corresponding data.
[0092] In this embodiment, the second processor can be a CPU or other processors.
[0093] For example, multiple read data are read response commands, PSLVERR, PRDATA, etc.
[0094] In this example, the read response command is 2'b11, where PSLVERR is the error message and PRDATA is the data to be read.
[0095] In this embodiment, the format of the read response data packet is the same as that of the encapsulated read instruction, as shown in the example. Figure 7 A structural diagram of the corresponding instructions or responses and their corresponding data.
[0096] S203: Control the first transceiver device to receive the read reply data packet and parse the read reply data packet to obtain the parsed read data.
[0097] Specifically, the first host terminal is controlled to receive read response data packets through the first data input pin, and the read response data packets are parsed to obtain the parsed read data.
[0098] In addition, the parsed read data needs to be converted into APB signal format for transmission on the APB bus.
[0099] S204: Receive the parsed read data through the first peripheral bus to complete the reading of the registers under the second transceiver device.
[0100] In addition, steps a~d are included after step S204:
[0101] Step a: When it is necessary to write to the registers of the second transceiver device, a write instruction is generated and sent to the first transceiver device through the first peripheral bus.
[0102] For example, the write command is 2'b00.
[0103] Specifically, in step a, the write command is sent to the first transceiver device via the first peripheral bus, which means: the write command is sent to the first slave end of the first transceiver device via the first peripheral bus.
[0104] Step b: Control the first transceiver device to encapsulate the write instruction and multiple preset signals to obtain the encapsulated read instruction, and send the encapsulated write instruction to the second transceiver device, so that the second processor controls the second transceiver device to parse the encapsulated write instruction to obtain the write instruction, and send the write instruction to the second peripheral bus, so that the second processor controls the second peripheral bus to write to the registers connected to the second peripheral bus according to the write instruction to obtain multiple write data, and return the multiple write data to the second transceiver device, so that the second processor controls the second transceiver device to encapsulate the multiple write data to obtain a write reply data packet.
[0105] Specifically, in step b, the first transceiver device is controlled to encapsulate the write command and multiple preset signals to obtain the encapsulated read command, and the encapsulated write command is sent to the second transceiver device. Specifically, the first slave device is controlled to encapsulate the write command and multiple preset signals to obtain the encapsulated write command, and the encapsulated write command is sent to the second transceiver device through the first data transmission pin.
[0106] For example, the preset signals are PADDR, PPORT, and PWDATA.
[0107] Where PADDR is the write address; PPORT is the transfer security type; and PWDATA is the data to be written.
[0108] For example, the format of the encapsulated read instruction is the same as that of the encapsulated read instruction, as shown in the example. Figure 7 A structural diagram of the corresponding instructions or responses and their corresponding data.
[0109] For example, multiple write data include write reply commands and PSLVERR, etc.
[0110] The example of a write reply command is 2'b01, and PSLVERR represents the error message.
[0111] Step c: Control the first transceiver device to receive the write reply data packet, and parse the write reply data packet to obtain the parsed write data.
[0112] Specifically, the first host terminal is controlled to receive write response data packets through the first data input pin, and the write response data packets are parsed to obtain the parsed write data.
[0113] In addition, the parsed write data needs to be converted into APB signal format for transmission on the APB bus.
[0114] Step d: Receive the parsed write data through the first peripheral bus to complete the writing to the registers of the second transceiver device.
[0115] In summary, the register reading method for a cross-chip communication system provided in this embodiment sends a pre-generated read instruction to a first transceiver device via a first peripheral bus; controls the first transceiver device to encapsulate the read instruction and multiple preset signals to obtain an encapsulated read instruction, and sends the encapsulated read instruction to a second transceiver device, so that a second processor controls the second transceiver device to parse the encapsulated read instruction to obtain a read instruction, and sends the read instruction to the second peripheral bus, so that the second processor controls the second peripheral bus to read the registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and returns the multiple read data to the second transceiver device, so that the second processor controls the second transceiver device to encapsulate the multiple read data to obtain a read response data packet; controls the first transceiver device to receive the read response data packet, and parses the read response data packet to obtain parsed read data; receives the parsed read data via the first peripheral bus, and realizes cross-chip register reading in complex situations through a cross-chip communication system.
[0116] In addition, the register reading method for the cross-chip communication system provided in this embodiment automatically realizes cross-chip register reading through the cross-chip communication system, thereby improving the register reading efficiency.
[0117] In addition, the register reading method of the cross-chip communication system provided in this embodiment can read or rewrite the internal registers of the chip by communicating with the host computer through the serial port of the cross-chip communication system when it is necessary to modify, view or rewrite the internal register configuration of the chip.
[0118] In addition, the register reading method for cross-chip communication systems provided in this embodiment can read or rewrite the registers of other subsystems in each module when it is necessary to view or modify the register configuration between different subsystems inside the chip, and under software initialization conditions, it can achieve the required configuration without the need for tools.
[0119] In addition, the register reading method for cross-chip communication systems provided in this embodiment achieves a pure hardware architecture by combining APB and UART, without the need for software development or adaptation. The cross-chip communication system can automatically encapsulate and uncapture packets, and the register reading is efficient and convenient. It also supports functions such as data retransmission and dynamic baud rate switching.
[0120] In addition, the register reading method for the cross-chip communication system provided in this embodiment is based on the combination of APB and UART, but is not limited to the form of APB and UART. It can also be used in the form of axi2uart or ahb2uart in the future.
[0121] Figure 3 Flowchart of a register reading method for a cross-chip communication system provided in this application embodiment Figure 2 The execution entity in this embodiment can be... Figure 1 The second processor in the illustrated embodiment is not particularly limited in this embodiment. Figure 3 As shown, the method includes:
[0122] S301: Control the second transceiver device to receive the encapsulated read instruction sent by the first transceiver device. The encapsulated read instruction is obtained by the first processor controlling the first transceiver device to encapsulate the read instruction and multiple preset signals. The read instruction is sent by the first processor controlling the first peripheral bus to the first transceiver device. The read instruction is generated by the first processor when it needs to read the registers under the second transceiver device.
[0123] In this embodiment, the relevant discussions regarding the second transceiver device, the read instruction, the first transceiver device, the first peripheral bus, and the registers have been described in detail in step S201, and will not be repeated here.
[0124] In this embodiment, the relevant discussion on the encapsulated read instructions has been described in detail in step S202, and will not be repeated here.
[0125] In this embodiment, the second transceiver device includes a second master end, a second slave end, a second data transmission pin, and a second data input pin. Accordingly, controlling the second transceiver device to receive the encapsulated read instruction sent by the first transceiver device in step S301 specifically involves controlling the second data input pin on the second transceiver device to receive the encapsulated read instruction sent by the first transceiver device.
[0126] For example, the second host is called the master, which usually refers to a component or device that plays a leading, controlling or coordinating role in the system.
[0127] For example, the second slave is the subordinate of the master, referring to a device or role that passively receives instructions and performs tasks during communication or task execution.
[0128] In this embodiment, the second data transmission pin can be TXD or other pins.
[0129] In this embodiment, the second data input pin can be RXD or other pins.
[0130] S302: Controls the second transceiver device to parse the encapsulated read command to obtain the read command, and sends the read command to the second peripheral bus.
[0131] Specifically, the second host terminal is controlled to parse the packaged read instruction through the second data input pin to obtain the read instruction, and then send the read instruction to the second peripheral bus.
[0132] S303: Controls the second peripheral bus, reads the registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and returns the multiple read data to the second transceiver device.
[0133] Specifically, the system controls the second peripheral bus, reads the registers mounted on the second peripheral bus according to the read instruction, obtains multiple read data, and returns the multiple read data to the second host.
[0134] In this embodiment, the discussion regarding multiple read data has been explained in detail in step S202, and will not be repeated here.
[0135] S304: Control the second transceiver device to encapsulate multiple read data packets to obtain read response data packets, and send the read response data packets to the first transceiver device so that the first processor controls the first transceiver device to parse the read response data packets to obtain the parsed read data, and send the parsed read data to the first processor through the first peripheral bus to complete the reading of the registers of the second transceiver device.
[0136] In this embodiment, the discussion regarding reading the reply data packet has been explained in detail in step S202, and will not be repeated here.
[0137] Specifically, in step S304, the second transceiver device is controlled to encapsulate multiple read data to obtain a read response data packet, and the read response data packet is sent to the first transceiver device. Specifically, the second host is controlled to encapsulate multiple read data to obtain a read response data packet, and the read response data packet is returned to the first transceiver device through the second data transmission pin.
[0138] In summary, the register reading method for a cross-chip communication system provided in this embodiment achieves cross-chip register reading in complex situations by controlling a second transceiver device to receive a packaged read instruction sent by a first transceiver device, controlling the second transceiver device to parse the packaged read instruction to obtain a read instruction, and sending the read instruction to a second peripheral bus; controlling the second peripheral bus to read registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and returning the multiple read data to the second transceiver device; controlling the second transceiver device to encapsulate the multiple read data to obtain a read response data packet, and sending the read response data packet to the first transceiver device, so that the first processor controls the first transceiver device to parse the read response data packet to obtain parsed read data, and sending the parsed read data to the first processor through the first peripheral bus.
[0139] Figure 4 Schematic diagram of the register reading device for a cross-chip communication system provided in this application embodiment Figure 1 .like Figure 4 As shown, the register reading device of the cross-chip communication system includes: a first transmitting module 401, a first control module 402, a second control module 403, and a first receiving module 404.
[0140] The first transmitting module 401 is used to generate a read instruction when it is necessary to read the registers under the second transceiver device, and send the read instruction to the first transceiver device through the first peripheral bus.
[0141] The first control module 402 is used to control the first transceiver device to encapsulate the read instruction and multiple preset signals to obtain the encapsulated read instruction, and send the encapsulated read instruction to the second transceiver device so that the second processor controls the second transceiver device to parse the encapsulated read instruction to obtain the read instruction, and send the read instruction to the second peripheral bus so that the second processor controls the second peripheral bus to read the registers connected to the second peripheral bus according to the read instruction to obtain multiple read data, and return the multiple read data to the second transceiver device so that the second processor controls the second transceiver device to encapsulate the multiple read data to obtain a read reply data packet;
[0142] The second control module 403 is used to control the first transceiver device to receive read reply data packets and parse the read reply data packets to obtain the parsed read data;
[0143] The first receiving module 404 is used to receive the parsed read data through the first peripheral bus to complete the reading of the registers under the second transceiver device.
[0144] In one possible implementation, the first transceiver device includes a first master unit, a first slave unit, a first data transmission pin, and a first data input pin. Correspondingly, the first transmission module 401 is specifically used to: send a read command to the first slave unit of the first transceiver device via a first peripheral bus. Correspondingly, the first control module 402 is specifically used to: control the first slave unit to encapsulate the read command and multiple preset signals to obtain the encapsulated read command, and send the encapsulated read command to the second transceiver device via the first data transmission pin. Correspondingly, the second control module 403 is specifically used to: control the first master unit to receive a read response data packet via the first data input pin, and parse the read response data packet to obtain the parsed read data.
[0145] In one possible implementation, the device further includes:
[0146] The second transmitting module is used to generate a write command when it is necessary to write to the registers under the second transceiver device, and send the write command to the first transceiver device through the first peripheral bus.
[0147] The third control module is used to control the first transceiver device to encapsulate the write instruction and multiple preset signals to obtain the encapsulated read instruction, and send the encapsulated write instruction to the second transceiver device so that the second processor controls the second transceiver device to parse the encapsulated write instruction to obtain the write instruction, and send the write instruction to the second peripheral bus so that the second processor controls the second peripheral bus to write to the registers connected to the second peripheral bus according to the write instruction to obtain multiple write data, and return the multiple write data to the second transceiver device so that the second processor controls the second transceiver device to encapsulate the multiple write data to obtain a write reply data packet;
[0148] The fourth control module is used to control the first transceiver device to receive write reply data packets and parse the write reply data packets to obtain the parsed write data;
[0149] The second receiving module is used to receive the parsed write data through the first peripheral bus to complete the writing to the registers of the second transceiver device.
[0150] In one possible implementation, the second transmitting module is specifically used to: send a write command to the first slave terminal of the first transceiver device via the first peripheral bus; correspondingly, the third control module is specifically used to: control the first slave terminal to encapsulate the write command and multiple preset signals to obtain the encapsulated write command, and send the encapsulated write command to the second transceiver device via the first data transmission pin; correspondingly, the fourth control module is specifically used to: control the first master terminal to receive the write reply data packet via the first data input pin, and parse the write reply data packet to obtain the parsed write data.
[0151] The apparatus provided in this embodiment can be used to execute the technical solutions of the above method embodiments. Its implementation principle and technical effects are similar, and will not be described again here.
[0152] Figure 5 Schematic diagram of the register reading device for a cross-chip communication system provided in this application embodiment Figure 2 .like Figure 5 As shown, the register reading device of the cross-chip communication system includes: a first control module 501, a second control module 502, a third control module 503 and a fourth control module 504.
[0153] The first control module 501 is used to control the second transceiver device and receive the encapsulated read instruction sent by the first transceiver device. The encapsulated read instruction is obtained by the first processor controlling the first transceiver device to encapsulate the read instruction and multiple preset signals. The read instruction is sent by the first processor controlling the first peripheral bus to the first transceiver device. The read instruction is generated by the first processor when it needs to read the registers under the second transceiver device.
[0154] The second control module 502 is used to control the second transceiver device, parse the encapsulated read command to obtain the read command, and send the read command to the second peripheral bus;
[0155] The third control module 503 is used to control the second peripheral bus, read the registers mounted on the second peripheral bus according to the read instruction, obtain multiple read data, and return the multiple read data to the second transceiver device.
[0156] The fourth control module 504 is used to control the second transceiver device to encapsulate multiple read data into packets to obtain read response data packets, and send the read response data packets to the first transceiver device so that the first processor controls the first transceiver device to parse the read response data packets to obtain parsed read data, and send the parsed read data to the first processor through the first peripheral bus to complete the reading of the registers of the second transceiver device.
[0157] In one possible implementation, the second transceiver device includes a second master unit, a second slave unit, a second data transmit pin, and a second data input pin. Correspondingly, the first control module 501 is specifically used to: control the second data input pin on the second transceiver device to receive the encapsulated read command sent by the first transceiver device; correspondingly, the second control module 502 is specifically used to: control the second master unit to parse the encapsulated read command through the second data input pin to obtain the read command, and send the read command to the second peripheral bus; correspondingly, the third control module 503 is specifically used to: control the second peripheral bus to read the registers mounted on the second peripheral bus according to the read command to obtain multiple read data, and return the multiple read data to the second master unit; correspondingly, the fourth control module 504 is specifically used to: control the second master unit to encapsulate the multiple read data to obtain a read reply data packet, and return the read reply data packet to the first transceiver device through the second data transmit pin.
[0158] The apparatus provided in this embodiment can be used to execute the technical solutions of the above method embodiments. Its implementation principle and technical effects are similar, and will not be described again here.
[0159] Figure 6 This is a schematic diagram of the hardware structure of the electronic device provided in an embodiment of this application. Figure 6 As shown, the electronic device of this embodiment includes: a processor 601 and a memory 602; the memory stores computer-executable instructions; at least one processor executes the computer-executable instructions stored in the memory, causing at least one processor to execute the register read method of the cross-chip communication system as described above.
[0160] Alternatively, the memory 602 can be either standalone or integrated with the processor 601.
[0161] When the memory 602 is set up independently, the electronic device also includes a bus 603 for connecting the memory 602 and the processor 601.
[0162] This application also provides a computer storage medium storing computer execution instructions. When the processor executes the computer execution instructions, the register reading method of the cross-chip communication system described above is implemented.
[0163] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the register reading method of the cross-chip communication system described above.
[0164] This application also provides a chip, which includes at least one processor and an interface circuit. The interface circuit is connected to at least one processor, and the processor executes a register read method for a cross-chip communication system by running program instructions.
[0165] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.
[0166] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to implement the solution of this embodiment according to actual needs.
[0167] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit composed of the above modules can be implemented in hardware or in the form of hardware plus software functional units.
[0168] The integrated modules described above, implemented as software functional modules, can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods of the various embodiments of this application.
[0169] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor.
[0170] The memory may include high-speed RAM, and may also include non-volatile storage (NVM), such as at least one disk storage device, and may also be a USB flash drive, external hard drive, read-only memory, disk or optical disc, etc.
[0171] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0172] The aforementioned storage media can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as Static Random-Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage media can be any available medium accessible to general-purpose or special-purpose computers.
[0173] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. Both the processor and the storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and storage medium can exist as discrete components in an electronic device or host device.
[0174] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.
[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A register reading method for a cross-chip communication system, characterized in that, The cross-chip communication system includes: a first chip and a second chip; the first chip includes: a first processor, a first transceiver device, and a first peripheral bus; the second chip includes: a second processor, a second transceiver device, and a second peripheral bus; the method includes: When it is necessary to read the registers under the second transceiver device, a read instruction is generated and sent to the first transceiver device through the first peripheral bus; The first transceiver device is controlled to encapsulate the read instruction and multiple preset signals to obtain an encapsulated read instruction, and the encapsulated read instruction is sent to the second transceiver device, so that the second processor controls the second transceiver device to parse the encapsulated read instruction to obtain the read instruction, and sends the read instruction to the second peripheral bus, so that the second processor controls the second peripheral bus to read the registers connected to the second peripheral bus according to the read instruction to obtain multiple read data, and returns the multiple read data to the second transceiver device, so that the second processor controls the second transceiver device to encapsulate the multiple read data to obtain a read response data packet; The first transceiver device is controlled to receive the read response data packet and parse the read response data packet to obtain the parsed read data; The parsed read data is received through the first peripheral bus to complete the reading of the registers under the second transceiver device.
2. The method according to claim 1, characterized in that, The first transceiver device includes a first master terminal, a first slave terminal, a first data transmission pin, and a first data input pin; Accordingly, sending the read command to the first transceiver device via the first peripheral bus includes: The read command is sent to the first slave device of the first transceiver device via the first peripheral bus; Accordingly, controlling the first transceiver device to encapsulate the read command and multiple preset signals to obtain an encapsulated read command, and sending the encapsulated read command to the second transceiver device, includes: The first slave device is controlled to encapsulate the read instruction and multiple preset signals to obtain the encapsulated read instruction, and then the encapsulated read instruction is sent to the second transceiver device through the first data transmission pin; Accordingly, controlling the first transceiver device to receive the read response data packet and parse the read response data packet to obtain the parsed read data includes: The first host terminal is controlled to receive the read response data packet through the first data input pin, and the read response data packet is parsed to obtain the parsed read data.
3. The method according to claim 2, characterized in that, Also includes: When it is necessary to write to the registers under the second transceiver device, a write instruction is generated and sent to the first transceiver device through the first peripheral bus. The first transceiver device is controlled to encapsulate the write instruction and multiple preset signals to obtain an encapsulated read instruction, and the encapsulated write instruction is sent to the second transceiver device, so that the second processor controls the second transceiver device to parse the encapsulated write instruction to obtain the write instruction, and sends the write instruction to the second peripheral bus, so that the second processor controls the second peripheral bus to write to the registers connected to the second peripheral bus according to the write instruction to obtain multiple write data, and returns the multiple write data to the second transceiver device, so that the second processor controls the second transceiver device to encapsulate the multiple write data to obtain a write reply data packet; The first transceiver device is controlled to receive the write response data packet and parse the write response data packet to obtain the parsed write data; The parsed write data is received through the first peripheral bus to complete the writing to the register of the second transceiver device.
4. The method according to claim 3, characterized in that, Sending the write command to the first transceiver device via the first peripheral bus includes: The write command is sent to the first slave device of the first transceiver device via the first peripheral bus; Accordingly, controlling the first transceiver device to encapsulate the write instruction and multiple preset signals to obtain an encapsulated read instruction, and sending the encapsulated write instruction to the second transceiver device, includes: The first slave device is controlled to encapsulate the write instruction and multiple preset signals to obtain the encapsulated write instruction, and then the encapsulated write instruction is sent to the second transceiver device through the first data transmission pin. Accordingly, controlling the first transceiver device to receive the write response data packet and parse the write response data packet to obtain the parsed write data includes: The first host terminal is controlled to receive the write response data packet through the first data input pin, and the write response data packet is parsed to obtain the parsed write data.
5. A register reading method for a cross-chip communication system, characterized in that, The cross-chip communication system includes: a first chip and a second chip; the first chip includes: a first processor, a first transceiver device, and a first peripheral bus; the second chip includes: a second processor, a second transceiver device, and a second peripheral bus; the method includes: The processor controls the second transceiver device to receive an encapsulated read instruction sent by the first transceiver device. The encapsulated read instruction is obtained by the first processor controlling the first transceiver device to encapsulate the read instruction and multiple preset signals. The read instruction is sent by the first processor controlling the first peripheral bus to the first transceiver device. The read instruction is generated by the first processor when it needs to read the registers under the second transceiver device. The second transceiver device is controlled to parse the encapsulated read instruction to obtain the read instruction, and then send the read instruction to the second peripheral bus; Control the second peripheral bus, read the registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and return the multiple read data to the second transceiver device; The second transceiver device is controlled to encapsulate the plurality of read data to obtain read response data packets, and the read response data packets are sent to the first transceiver device, so that the first processor controls the first transceiver device to parse the read response data packets to obtain parsed read data, and sends the parsed read data to the first processor through the first peripheral bus to complete the reading of the registers of the second transceiver device.
6. The method according to claim 5, characterized in that, The second transceiver device includes a second master terminal, a second slave terminal, a second data transmission pin, and a second data input pin; Accordingly, controlling the second transceiver device to receive the encapsulated read instruction sent by the first transceiver device includes: Control the second data input pin on the second transceiver device to receive the encapsulated read command sent by the first transceiver device; Accordingly, controlling the second transceiver device to parse the encapsulated read instruction to obtain the read instruction, and sending the read instruction to the second peripheral bus, includes: The second host terminal is controlled to parse the packaged read instruction through the second data input pin to obtain the read instruction, and then send the read instruction to the second peripheral bus; Accordingly, controlling the second peripheral bus, reading the registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and returning the multiple read data to the second transceiver device, includes: Control the second peripheral bus, read the registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and return the multiple read data to the second host. Accordingly, controlling the second transceiver device to encapsulate the plurality of read data into packets to obtain read response data packets, and sending the read response data packets to the first transceiver device, includes: The second host terminal is controlled to encapsulate the multiple read data to obtain read response data packets, and the read response data packets are returned to the first transceiver device through the second data transmission pin.
7. A register reading device for a cross-chip communication system, characterized in that, The cross-chip communication system includes: a first chip and a second chip; the first chip includes: a first processor, a first transceiver device, and a first peripheral bus; the second chip includes: a second processor, a second transceiver device, and a second peripheral bus; the device includes: The first transmitting module is used to generate a read instruction when it is necessary to read the registers under the second transceiver device, and send the read instruction to the first transceiver device through the first peripheral bus; A first control module is configured to control the first transceiver device to encapsulate the read instruction and multiple preset signals to obtain an encapsulated read instruction, and send the encapsulated read instruction to the second transceiver device, so that the second processor controls the second transceiver device to parse the encapsulated read instruction to obtain the read instruction, and send the read instruction to the second peripheral bus, so that the second processor controls the second peripheral bus to read the registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and return the multiple read data to the second transceiver device, so that the second processor controls the second transceiver device to encapsulate the multiple read data to obtain a read response data packet; The second control module is used to control the first transceiver device to receive the read response data packet and parse the read response data packet to obtain the parsed read data; The first receiving module is used to receive the parsed read data through the first peripheral bus to complete the reading of the registers of the second transceiver device.
8. A register reading device for a cross-chip communication system, characterized in that, The cross-chip communication system includes: a first chip and a second chip; the first chip includes: a first processor, a first transceiver device, and a first peripheral bus; the second chip includes: a second processor, a second transceiver device, and a second peripheral bus; the device includes: The first control module is used to control the second transceiver device and receive the encapsulated read instruction sent by the first transceiver device. The encapsulated read instruction is obtained by the first processor controlling the first transceiver device to encapsulate the read instruction and multiple preset signals. The read instruction is sent by the first processor controlling the first peripheral bus to the first transceiver device. The read instruction is generated by the first processor when it needs to read the registers under the second transceiver device. The second control module is used to control the second transceiver device to parse the encapsulated read instruction to obtain the read instruction, and send the read instruction to the second peripheral bus; The third control module is used to control the second peripheral bus, read the registers mounted on the second peripheral bus according to the read instruction to obtain multiple read data, and return the multiple read data to the second transceiver device; The fourth control module is used to control the second transceiver device to encapsulate the plurality of read data to obtain read response data packets, and send the read response data packets to the first transceiver device, so that the first processor controls the first transceiver device to parse the read response data packets to obtain parsed read data, and send the parsed read data to the first processor through the first peripheral bus to complete the reading of the lower register of the second transceiver device.
9. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes the computer execution instructions stored in the memory, causing the at least one processor to perform the register read method of the cross-chip communication system as described in any one of claims 1 to 4, or the register read method of the cross-chip communication system as described in claim 5 or 6.
10. A computer storage medium, characterized in that, The computer storage medium stores computer execution instructions. When the processor executes the computer execution instructions, it implements the register reading method of the cross-chip communication system as described in any one of claims 1 to 4, or the register reading method of the cross-chip communication system as described in claim 5 or 6.