Register placement systems, methods, and electronic devices

Abstract

This application provides a register allocation system, method, and electronic device, and relates to the technical field of computers. The register allocation system includes a display processing device, a memory, and a hardware automatic control unit. The display processing device includes a plurality of registers. The memory pre-stores at least one allocation instruction for specifying a target register to be allocated in the display processing device. The hardware automatic control unit is connected to a register allocation interface in the display processing device, receives a startup instruction including a storage address of the allocation instruction, retrieves and analyzes the allocation instruction from the memory based on the startup instruction, and allocates the target register in the display processing device based on the analyzed allocation instruction. By using the hardware automatic control unit to allocate registers instead of the conventional method of allocating registers by a CPU, the burden on CPU bandwidth can be minimized.

Description

Technical Field

[0001] This application relates to the technical field of computers, and more specifically, to a register configuration system, method, and electronic device.

Background Art

[0002] With the increasing demand for various high-definition displays, the overall algorithm unit of a display processing unit (DPU) and its processing process are becoming increasingly complex. Along with this, various control processes are also becoming more complex. In addition, the number of registers arranged by software has increased significantly, and the interaction between software and hardware has become more frequent. Due to such new problems, it has become difficult and unrealistic to realize various control and arrangement processes only by the conventional CPU (Central Processing Unit) control method in the prior art. In other words, such an operation method cannot meet the actual performance requirements.

Summary of the Invention

[0003] This application provides a register configuration system, method, and electronic device to solve the problem that the realization of various control and arrangement processes by the conventional CPU control method in the prior art cannot meet the actual performance requirements.

[0004] In a first embodiment, the present application provides a register placement system. This register placement system includes a display processing device, a memory, and a hardware automatic control unit, wherein the display processing device includes a plurality of registers, the memory pre-stores at least one placement instruction for specifying a target register to be placed in the display processing device, and the hardware automatic control unit is connected to the register placement interface in the display processing device, receives a startup instruction including the storage address of the placement instruction, retrieves and analyzes the placement instruction from the memory based on the startup instruction, and places the target register in the display processing device based on the analyzed placement instruction.

[0005] In the embodiment of the present invention, register placement is performed by a hardware automatic control unit instead of the conventional CPU-based register placement method. This minimizes the bandwidth burden on the CPU for GPU placement, and even when the number of registers to be placed increases, the present invention enables registration placement, thereby optimizing the display processing process.

[0006] In relation to the technical proposal according to the first embodiment described above, in some possible embodiments, the hardware automatic control unit is connected to the interactive interface of each data path of the display processing device, with different data paths containing different registers, and the hardware automatic control unit sends a placement start command to the data path indicating the start of placement of the target register, and further receives a placement status signal returned from the data path indicating whether all registers contained in the data path have been placed.

[0007] In the embodiment of the present invention, the hardware automatic control unit can determine the arrangement of registers in each data path of the display processing unit through data interaction with each data path of the display processing unit, making it easier for the hardware automatic control unit to determine whether there is a data path necessary for the arrangement of registers.

[0008] In relation to the technical proposal according to the first embodiment described above, in some possible embodiments, the display processing device includes a plurality of data paths, and the hardware automatic control unit records the placement status of registers included in each data path, which indicates whether or not the registers are placed, in accordance with the placement status signals returned from each data path.

[0009] In the embodiment of the present invention, the hardware automatic control unit records the arrangement of registers included in each data path, which makes it easier to determine which data path's registers to arrange thereafter.

[0010] In relation to the technical proposal according to the first aspect described above, in some possible embodiments, the register placement system further includes a central processing unit connected to the hardware automatic control unit and transmitting the startup command to the hardware automatic control unit.

[0011] In relation to the technical proposal according to the first embodiment described above, in some possible embodiments, the hardware automatic control unit transmits its internal state to the central processing unit, the central processing unit determines whether the hardware automatic control unit is abnormal based on the received state of the hardware automatic control unit, and if the hardware automatic control unit is abnormal, transmits an interrupt command to the hardware automatic control unit to instruct it to stop operating.

[0012] In the embodiment of the present invention, the central processing unit monitors the internal state of the hardware automatic control unit and, if the hardware automatic control unit is abnormal, can send an interrupt command to the hardware automatic control unit to stop its operation. This prevents situations such as register placement errors caused by abnormalities in the hardware automatic control unit and improves the reliability of the register placement system.

[0013] In relation to the technical proposal according to the first aspect described above, in some possible embodiments, the placement instruction includes an instruction type, a number of consecutively addressed target registers, the offset address of the first target register, an instruction body, and an instruction end flag.

[0014] In relation to the technical proposal according to the first embodiment described above, in several possible embodiments, the instruction body contains a method for calculating the actual placement address of each target register, the hardware automatic control unit analyzes the placement instruction according to the instruction type, obtains the number of target registers, the offset address of the first target register, the instruction body, and the instruction end flag, determines the actual placement address of each target register based on the number of consecutive target registers, the offset address of the first target register, and the calculation method in the instruction body, and places each target register based on its actual placement address.

[0015] In the embodiment of the present invention, the instruction body contains a method for calculating the actual placement address of each target register. Therefore, the address of the target register to be placed can be calculated based on the number of consecutive target registers and the offset address of the first target register. This enables the placement of multiple registers with a single instruction, reduces the number of placement instructions transmitted, and improves placement efficiency.

[0016] In relation to the technical proposal according to the first aspect described above, in some possible embodiments, a method for calculating the total number of consecutively addressed target registers is further described in the instruction body, and the hardware automatic control unit determines the total number of consecutively addressed target registers in accordance with the number of consecutively addressed target registers and the method for calculating the total number of target registers, and determines the actual placement address of each target register based on the total number of consecutively addressed target registers, the offset address of the first target register and the instruction body.

[0017] In the embodiment of the present invention, since the length of the field for recording the number of consecutive target registers in the placement instruction is limited, if there are many consecutive target registers, the total number of consecutive target registers can be calculated by describing the method for calculating the total number of consecutive target registers in the instruction body. Since it is not necessary to divide the instruction into multiple placement instructions, the number of placement instructions sent is reduced, and placement efficiency is improved.

[0018] In a second embodiment, the present application provides a register placement method applicable to a hardware automatic control unit in a register placement system described in the first embodiment and / or an implementable embodiment relating to the first embodiment, and includes the steps of: receiving a start instruction; obtaining and analyzing the placement instruction from the memory based on the start instruction; and placing a target register in the display processing device based on the analyzed placement instruction.

[0019] In a third embodiment, the present application provides an electronic device which includes a register arrangement system described in the first embodiment and / or an implementable embodiment relating to the first embodiment.

[0020] The beneficial effect of this invention is that, instead of the conventional CPU-based register placement method, the hardware automatic control unit handles the placement of registers in the display processing device, thereby minimizing the CPU bandwidth burden. Even when the number of registers to be placed increases, this invention enables the placement of registers, resulting in optimization of the display processing process.

[0021] To more clearly explain the technical concept of the embodiments of this application, the drawings necessary for describing the embodiments are briefly described below. The following drawings only show some embodiments of this application and do not limit the scope. A person skilled in the art can obtain other relevant drawings based on these drawings without employing inventive ability. [Brief explanation of the drawing]

[0022] [Figure 1] It is a structural block diagram of a first register arrangement system according to an embodiment of the present application. [Figure 2] It is a structural schematic diagram of the connection between a hardware automatic control unit and a display processing device according to an embodiment of the present application. [Figure 3] It is a schematic diagram of an instruction end flag according to an embodiment of the present application. [Figure 4] It is a structural schematic diagram of a first arrangement instruction according to an embodiment of the present application. [Figure 5] It is a structural schematic diagram of a second arrangement instruction according to an embodiment of the present application. [Figure 6] It is a structural schematic diagram of a third arrangement instruction according to an embodiment of the present application. [Figure 7] It is a structural schematic diagram of a fourth arrangement instruction according to an embodiment of the present application. [Figure 8] It is a structural block diagram of a second register arrangement system according to an embodiment of the present application. [Figure 9] It is a flowchart of a register arrangement method according to an embodiment of the present application.

Embodiments for Carrying Out the Invention

[0023] Hereinafter, the technical solution according to the embodiment of the present application will be described with reference to the drawings using the embodiments of the present application.

[0024] Furthermore, similar reference numerals indicate similar things in drawings, so if defined in one drawing, it is unnecessary to define or interpret them further in other drawings. Also, in this application, relational terms such as "first" and "second" may be used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any factual relationship or order between such entities or actions. Furthermore, terms such as "have" and "include" and any variations thereof are intended to cover non-exclusive inclusion. Thus, a process, method, article or apparatus that includes a set of elements is not necessarily limited to these elements and may include other elements not specified, or elements specific to these processes, methods, articles or apparatus.

[0025] The technical proposal relating to this application will be described in detail below with reference to the drawings.

[0026] Figure 1 is a schematic structural diagram of a register placement system 100 according to an embodiment of the present invention. This register placement system 100 includes a display processing device 110, a memory 130, and a hardware automatic control unit 120.

[0027] The display processing device 110 includes multiple registers.

[0028] Optionally, the display processing device 110 includes at least one data path, and if the display processing device 110 includes multiple data paths, different registers are included in different data paths.

[0029] The display processing device 110 may be any conventional type of display processing device 110, and the specific type of display processing device 110 is not limited here.

[0030] Memory 130 pre-stores at least one placement instruction for specifying the target register to be placed in the display processing device 110.

[0031] The memory 130 may be any conventional type of memory 130, and may be various media capable of storing program code, such as a USB disk, a portable hard disk, a read-only memory 130 (ROM), a random access memory 130 (RAM), a magnetic disk, or an optical disk. The specific type of memory 130 is not limited here.

[0032] The hardware automatic control unit 120 is connected to the register placement interface in the display processing unit 110. The hardware automatic control unit 120 receives a startup instruction that includes the storage address of the placement instruction, retrieves and analyzes the placement instruction from the memory 130 based on the startup instruction, and places the target register in the display processing unit 110 based on the analyzed placement instruction.

[0033] The hardware automatic control unit 120 may, but is not limited to, PDMA (Programming Direct Memory Access).

[0034] Figure 2 shows a specific method for connecting a hardware automatic control unit 120 and a display processing device according to one embodiment.

[0035] Here, the hardware automatic control unit 120 is connected to the pre-processor, crossbar, post-processor, and output interface of the display processing device 110, as shown in Figure 2. The hardware automatic control unit 120 realizes the placement of registers in the display processing device 110 by sending instructions to at least one of the pre-processor, crossbar, post-processor, and output interface. The hardware automatic control unit 120 obtains start instructions and placement instructions via the bus interface shown in Figure 2.

[0036] Conventionally, the CPU sends instructions to the display processing unit, which then sends the instructions from the CPU to the preprocessor, crossbar, postprocessor, and output interface to arrange the registers in the display processing unit. In contrast, with this invention, the transmission of data by the display processing unit is unnecessary, thus improving the efficiency of register arrangement.

[0037] Optionally, the hardware automatic control unit 120 may be provided independently or may be provided inside the display processing device 110.

[0038] In one embodiment, the placement instruction includes a register address. This facilitates the subsequent determination and placement of the target register by the hardware automatic control unit 120 according to this register address.

[0039] For the purpose of analyzing placement instructions by the hardware automatic control unit 120, the placement instructions may optionally include instruction types.

[0040] Here, the instruction type may represent the type of placement instruction, such as a 16-bit instruction or a 32-bit instruction. The examples provided here are for illustrative purposes only and do not limit the scope of this invention.

[0041] In one embodiment, multiple placement instructions may be stored in memory 130 as an instruction list. In this case, an instruction termination flag is also included in the placement instructions to distinguish between different placement instructions.

[0042] The instruction end flag is usually located at the end of a placement instruction. Reading the instruction end flag confirms that all the contents of the current placement instruction have been read.

[0043] The instruction termination flag may be a string of characters or binary code, and the specific implementation method of the instruction termination flag is not limited here.

[0044] Optionally, in certain specific cases, it is necessary for multiple different display areas to be activated multiple times within a single frame. Due to the high demand for timeliness, this multiple activation operation needs to be fully automated by automatic triggering by the hardware automatic control unit 120 and handshake interactions with different hardware blocks of the display processing device 110. For this reason, a flag indicating that the end of the image area configuration data has been reached may be added to the instruction end flag.

[0045] When the hardware automatic control unit 120 reads a flag indicating that it has reached the end of the configuration data for this image region, it automatically jumps to the shifted position of the next image region (a shifted memory position, that is, the position of the memory area determined by the shifted address of the image region and the size of the image region) according to this flag, and controls the operation process such as analysis, placement, and execution of the next placement instruction.

[0046] Figure 3 shows one way to implement the instruction termination flag. `Next section size` represents the size of the next image region, and `Next section address offset` represents the offset address of the next image region. By reading `Next section size` and `Next section address offset`, the displacement position of the next image region can be identified, allowing for a jump.

[0047] Here, the LSB (Least Significant Bit) is the bit position that represents the smallest value in binary. The MSB (Most Significant Bit) is the bit position that represents the largest value in binary. Generally, the MSB is located at the leftmost position in binary, and the LSB is located at the rightmost position in binary.

[0048] The examples provided here are merely for the purpose of facilitating understanding and do not limit the scope of this application.

[0049] Optionally, any data exceeding the instruction end flag may be treated as invalid data.

[0050] In one embodiment, in order to reduce the number of placement instructions, the register address in a placement instruction can be represented by the number of consecutive target registers, the offset address of the first target register, and the instruction body.

[0051] Optionally, the instruction body may store information other than register addresses, such as register placement instructions or the number of registers. The content included in the instruction body is not limited here.

[0052] Optionally, the instruction body may include a description of how to calculate the actual location address of each target register.

[0053] In one embodiment, a placement instruction includes an instruction type, the number of consecutive target registers, the offset address of the first target register, the instruction body, and an instruction end flag.

[0054] Here, the specific roles and principles of the instruction type, the number of consecutive target registers, the offset address of the first target register, the instruction body, and the instruction termination flag are the same as described above, so we will omit the explanation.

[0055] Figure 4 shows the structure of a placement instruction. Instruction is the instruction type, Length is the number of consecutive target registers at the address, Address is the offset address of the first target register, Configure data is the instruction body, End of frame flag is the instruction end flag, and Invalid data is invalid data.

[0056] Optionally, if the instruction body contains a method for calculating the actual placement address of each target register, the hardware automatic control unit 120 analyzes the placement instruction according to the instruction type and obtains the number of target registers, the offset address of the first target register, the instruction body, and the instruction end flag. Then, based on the number of consecutive target registers, the offset address of the first target register, and the calculation method in the instruction body, it determines the actual placement address of each target register and places each target register based on its actual placement address.

[0057] The specific process by which the hardware automatic control unit 120 determines the target register address in response to a placement instruction will be explained using the placement instruction shown in Figure 5 as an example.

[0058] As shown in Figure 5, Length=3 means there are three consecutive target registers. Address is the offset address of the first target register. The instruction body states "Register offset base on Address," which indicates the offset amount of these three consecutive registers based on the offset address of the first target register. Therefore, the actual offset amount of the first target register is Address + Register offset base on Address. Subsequently, the actual placement address of the first target register is obtained based on the sum of the pre-set base address and the actual offset amount of the first target register.

[0059] Since the three target registers are consecutive, adding 1 to the actual location address of the first target register gives the actual location address of the second target register. Adding 2 to the actual location address of the first target register gives the actual location address of the third target register.

[0060] The examples provided here are merely for the purpose of facilitating understanding and do not limit the scope of this application.

[0061] In placement instructions, the length of the field used to record the number of consecutive target register addresses is limited. Therefore, if there are too many consecutive target registers, the field used to record the number of consecutive target register addresses in the placement instruction may not be fully displayed.

[0062] In this case, the instruction body may further describe a method for calculating the total number of consecutively addressed target registers. In this case, the hardware automatic control unit 120 determines the total number of consecutively addressed target registers according to the number of consecutively addressed target registers and the method for calculating the total number of target registers, and determines the actual placement address of each target register based on the total number of consecutively addressed target registers, the offset address of the first target register, and the instruction body.

[0063] Here, the method for calculating the number of consecutive target registers and the total number of target registers is as follows: The instruction body contains a second number of consecutive target registers, and by adding this second number of consecutive target registers to the number of consecutive target registers specified in the placement instruction, the total number of consecutive target registers is obtained.

[0064] The deployment command shown in Figure 6 will be used as an example for further explanation.

[0065] Here, "Length=M" means that there are M target registers with consecutive addresses, where M is a positive integer. "Register number=M+N" means that the total number of target registers with consecutive addresses is M+N, where N is a positive integer. The other contents shown in Figure 6 are based on the same principles as those described in Figure 5 above, so their explanation is omitted.

[0066] The examples provided here are merely for the purpose of facilitating understanding and do not limit the scope of this application.

[0067] Furthermore, the specific methods for implementing the placement instructions shown in this application are not limited to the examples described above.

[0068] Optionally, if there are multiple non-consecutive target registers, the instruction body may specify the offset amount for each target register.

[0069] At this time, for each target register, the actual placement address of each target register is obtained based on the offset amount of that target register, the offset address of the first target register, and a pre-set reference address.

[0070] Optionally, the instruction body may specify the number of non-consecutive target registers.

[0071] The deployment command shown in Figure 7 will be used as an example for further explanation.

[0072] As shown in Figure 7, Length=1 means there is one contiguous target register. Address is the offset address of the first target register. "Register number=3" in the instruction body means there are three non-contiguous target registers. "Offset of the 1st register", "Offset of the 2nd register", and "Offset of the 3rd register" indicate the offset amounts of these three non-contiguous registers, based on the offset address of the first target register.

[0073] Therefore, the actual offset amount of the first target register is Address + Offset of the 1st register. Then, the actual placement address of the first target register is obtained based on the sum of the pre-set reference address and the actual offset amount of the first target register.

[0074] Similarly, the actual offset amount for the second target register is Address + Offset of the 2nd register. The actual offset amount for the third target register is Address + Offset of the 3rd register.

[0075] In Figure 7, "Configure data" in the instruction body represents the configuration data.

[0076] The examples provided here are merely for the purpose of facilitating understanding and do not limit the scope of this application.

[0077] In one embodiment, the hardware automatic control unit 120 is connected to the interactive interface of each data path of the display processing device 110, where different data paths contain different registers.

[0078] The hardware automatic control unit 120 sends a placement start command to the data path to indicate the start of placement of the target register, and also receives a placement status signal from the data path indicating whether all registers included in the data path have been placed.

[0079] Here, the placement status signal may be either a reply completion signal or a placement incomplete signal.

[0080] The "Placement Incomplete" signal may include information such as the number of an unplaced register or a memory address.

[0081] Optionally, if the display processing unit 110 includes multiple data paths, the hardware automatic control unit 120 records the registration status of the registers included in each data path, indicating whether or not the registers have been registered, in accordance with the registration status signals returned from each data path. By recording the registration status of the registers included in each data path, the hardware automatic control unit 120 makes it easier to determine which data path's registers to register in the future.

[0082] In one embodiment, if the display processing device 110 includes multiple data paths, the hardware automatic control unit 120 records information about the target registers in the positioned display processing device 110.

[0083] For example, information such as the offset address or actual placement address of the target register may be recorded. This example is merely for the sake of clarity and is not limiting to the present invention; it is sufficient that the recorded information uniquely represents the target register.

[0084] Based on the recorded information, it is possible to identify target registers that have not yet been placed in each data path, making it easier to decide which data path's registers to place next.

[0085] In one embodiment, as shown in Figure 8, the register arrangement system 100 further includes a central processing unit 140.

[0086] Here, the central processing unit 140 is connected to the hardware automatic control unit 120 and sends a start command to the hardware automatic control unit 120.

[0087] The startup command instructs the hardware automatic control unit 120 to start up and begin placing registers.

[0088] Optionally, the hardware automatic control unit 120 transmits its internal state to the central processing unit 140.

[0089] In response, the central processing unit 140 determines whether the hardware automatic control unit 120 is malfunctioning based on the status of the received hardware automatic control unit 120. If the hardware automatic control unit 120 is malfunctioning, it sends an interrupt command to the hardware automatic control unit 120 to instruct it to stop operating.

[0090] The central processing unit 140 monitors the internal state of the hardware automatic control unit 120 and, if the hardware automatic control unit 120 is malfunctioning, can send an interrupt command to stop the operation of the hardware automatic control unit 120. This prevents situations such as register placement errors caused by malfunctions in the hardware automatic control unit 120 and improves the reliability of the register placement system 100.

[0091] The central processing unit 1410 may be any type of central processing unit (CPU), and the specific type of the central processing unit 140 is not limited.

[0092] Based on a similar technical concept, the present invention further provides a register placement method which is applied to the hardware automatic control unit 120 in the above-described register placement system 100. As shown in Figure 9, the following describes the steps included therein with reference to Figure 9.

[0093] S100: Receives a start command.

[0094] Here, the invocation instruction includes the memory address of the placement instruction.

[0095] Optionally, the start command may be sent from the central processing unit to the hardware automatic control unit.

[0096] S200: Based on the boot instruction, it retrieves and analyzes the placement instruction from memory.

[0097] Upon receiving a startup instruction, the system can obtain a placement instruction based on the memory address contained in the startup instruction. By analyzing the placement instruction, the actual placement address of the target register can be obtained, and the target register is then placed based on this actual placement address.

[0098] Here, the placement instruction and the specific implementation method for analyzing the placement instruction to obtain the actual placement address of the target register have already been clearly explained above, so we will omit the explanation.

[0099] S300: Based on the analyzed placement instructions, the target register in the display processing unit is placed.

[0100] By analyzing the placement instruction, the actual placement address of the target register can be obtained, and then the target register is placed based on this actual placement address.

[0101] Here, the specific method and logic for arranging the target registers are well known to those skilled in the art, so we will omit the explanation.

[0102] The register placement method according to the embodiment of the present application has the same implementation principles and technical effects as the embodiment of the register placement system described above. For the sake of simplicity, for matters not mentioned in the embodiment of the method, the corresponding descriptions in the embodiment of the register placement system described above can be referenced.

[0103] Based on a similar technical concept, the present invention further provides an electronic device which includes the above-described register arrangement system.

[0104] The specific implementation method and principles of the register placement system have already been clearly explained above, so we will omit further explanation here.

[0105] This electronic device may be an electronic device that requires the arrangement of registers in a display processing device such as a computer or server, and does not limit the specific type of electronic device.

[0106] The foregoing description is merely a preferred embodiment of the present application and does not limit it. Those skilled in the art may have various modifications and changes to the present application. Any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and principles of the present application are included within the scope of protection of the present application.

Claims

1. A display processing device including multiple registers, The display processing device includes a memory that pre-stores multiple placement instructions for specifying a target register where the configuration data of the image area is to be placed, The system includes a hardware automatic control unit connected to the register placement interface of the display processing device, which receives a startup instruction including the storage address of the placement instruction, retrieves and analyzes the placement instruction from the memory based on the startup instruction, and places the configuration data included in the placement instruction into the target register of the display processing device based on the analyzed placement instruction. The placement instruction includes an instruction end flag indicating that the end of the configuration data included in the placement instruction has been reached, and the instruction end flag includes the offset address of the next image region. The hardware automatic control unit terminates the analysis of the current placement instruction and performs the analysis of the next placement instruction according to the instruction termination flag. A register placement system characterized by the following:

2. The hardware automatic control unit is connected to the interactive interface of each data path of the display processing device, and different data paths contain different registers. The hardware automatic control unit sends a placement start command to the data path, which indicates the start of placement of the target register, and further receives a placement status signal returned from the data path, which indicates whether all registers included in the data path have been placed. The register placement system according to feature 1.

3. The display processing device includes a plurality of data paths, The hardware automatic control unit records the placement status of the registers included in each data path, which indicates whether or not the registers have been placed, in accordance with the placement status signal returned from each data path. The register placement system according to claim 2, characterized in that it is the same as described in claim 2.

4. It further includes a central processing unit connected to the hardware automatic control unit and which transmits the startup command to the hardware automatic control unit. The register placement system according to feature 1.

5. The hardware automatic control unit transmits its internal state to the central processing unit, The central processing unit determines whether the hardware automatic control unit is malfunctioning based on the received status of the hardware automatic control unit, and if the hardware automatic control unit is malfunctioning, it sends an interrupt command to the hardware automatic control unit to instruct it to stop operating. The register placement system according to feature 4.

6. The placement instruction includes an instruction type, the number of consecutive target registers, the offset address of the first target register, and the instruction body. The register placement system according to feature 1.

7. The instruction body contains a method for calculating the actual location address of each target register. The hardware automatic control unit analyzes the placement instruction according to the instruction type, obtains the number of target registers, the offset address of the first target register, the instruction body, and the instruction end flag, determines the actual placement address of each target register based on the number of consecutive target registers, the offset address of the first target register, and the calculation method in the instruction body, and places the configuration data in each target register based on the actual placement address of each target register. The register arrangement system described in claim 6.

8. The instruction body further describes a method for calculating the total number of consecutive target registers. The hardware automatic control unit determines the total number of consecutive target registers based on the number of consecutive target registers and the method for calculating the total number of target registers, and determines the actual placement address of each target register based on the total number of consecutive target registers, the offset address of the first target register, and the instruction body. The register placement system according to feature 7.

9. Applicable to a hardware automatic control unit in a register placement system according to any one of claims 1 to 8, The steps include receiving a start command and The steps include: obtaining the placement instruction from the memory based on the startup instruction and analyzing it; The step of placing the configuration data in the target register in the display processing device based on the analyzed placement instruction includes: A register arrangement method characterized by the following.

10. An electronic device characterized by including a register arrangement system according to any one of claims 1 to 8.

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