Capacitor manufacturing method

Abstract

To suppress the degradation of electrical characteristics of capacitors.SOLUTION: A capacitor has a substrate 10, a first electrode 14 provided on the substrate, a dielectric film 16 provided on the first electrode, a second electrode 18 provided on the dielectric film, a third electrode 20 in contact with the second electrode in at least some first region 50 of the lower surface, and an organic insulating film 26 covering the upper part of the dielectric film, the upper part of the second electrode and the third electrode, and the organic insulating film is not provided between the bottom surface of the third electrode and the second electrode in the direction normal to the top surface of the substrate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention provides Capacitor manufacturing method Regarding. [Background technology]

[0002] A capacitor is known in which a first electrode, a dielectric film, and a second electrode are stacked on a substrate. It is also known to form a third electrode used as wiring on the second electrode (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-6620 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when an organic insulator film is formed so as to cover the capacitor, stress from the organic insulator film may cause the third electrode to peel off or the breakdown voltage of the capacitor to decrease.

[0005] The present disclosure has been made in view of the above-mentioned problems, and aims to suppress the deterioration of the electrical characteristics of a capacitor. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a capacitor comprising: a substrate; a first electrode provided on the substrate; a dielectric film provided on the first electrode; a second electrode provided on the dielectric film; a third electrode contacting the second electrode in at least a first region of the lower surface; and an organic insulator film covering an upper portion of the dielectric film, an upper portion of the second electrode, and the third electrode, wherein the organic insulator film is not provided between the lower surface of the third electrode and the second electrode in the normal direction to the upper surface of the substrate.

[0007] One embodiment of the present disclosure is a method for manufacturing a capacitor, including the steps of: forming a first electrode on a substrate; forming a dielectric film on the first electrode; forming a second electrode on the dielectric film; forming a first mask layer having a first opening on the second electrode; forming a seed layer on the inner surface of the first opening and on the first mask layer; forming a second mask layer on the seed layer, the second mask layer having a second opening that is included in the first opening and has an opening area smaller than that of the first opening in a planar view; forming a plating layer in the second opening; removing the second mask layer; forming a third electrode from the seed layer and the plating layer by removing the seed layer using the plating layer as a mask; and forming an organic insulator film on the substrate to cover the third electrode. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to suppress the deterioration of the electrical characteristics of the capacitor. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view of a capacitor in accordance with a first embodiment. [Figure 2] FIG. 2 is a plan view of the capacitor in accordance with the first embodiment. [Figure 3A] FIG. 3A is a cross-sectional view illustrating a method for manufacturing a capacitor according to the first embodiment. [Figure 3B] FIG. 3B is a cross-sectional view illustrating a method for manufacturing the capacitor according to the first embodiment. [Figure 4A] FIG. 4A is a cross-sectional view illustrating a method for manufacturing a capacitor according to the first embodiment. [Figure 4B] FIG. 4B is a cross-sectional view illustrating a method for manufacturing the capacitor according to the first embodiment. [Figure 5A] FIG. 5A is a cross-sectional view illustrating a method for manufacturing a capacitor according to the first embodiment. [Figure 5B] FIG. 5B is a cross-sectional view illustrating a method for manufacturing the capacitor according to the first embodiment. [Figure 6A] FIG. 6A is a cross-sectional view illustrating a method for manufacturing a capacitor according to the first embodiment. [Figure 6B] FIG. 6B is a cross-sectional view illustrating a method for manufacturing the capacitor according to the first embodiment. [Figure 7A] FIG. 7A is a cross-sectional view illustrating a method for manufacturing the capacitor according to the first embodiment. [Figure 7B] FIG. 7B is a cross-sectional view illustrating a method for manufacturing the capacitor according to the first embodiment. [Figure 8A] FIG. 8A is a cross-sectional view illustrating a method for manufacturing the capacitor according to the first embodiment. [Figure 8B] FIG. 8B is a cross-sectional view illustrating a method for manufacturing the capacitor in accordance with the first embodiment. [Figure 9A] FIG. 9A is a cross-sectional view illustrating a method for manufacturing the capacitor in accordance with the first embodiment. [Figure 9B] FIG. 9B is a cross-sectional view illustrating a method for manufacturing the capacitor in accordance with the first embodiment. [Figure 10A] FIG. 10A is a cross-sectional view illustrating a method for manufacturing the capacitor according to the first embodiment. [Figure 10B] FIG. 10B is a cross-sectional view illustrating a method for manufacturing the capacitor according to the first embodiment. [Figure 11A] FIG. 11A is a cross-sectional view showing a method for manufacturing a capacitor according to Comparative Example 1. FIG. [Figure 11B] FIG. 11B is a cross-sectional view showing a method for manufacturing a capacitor according to Comparative Example 1. [Figure 12A] FIG. 12A is a cross-sectional view showing a method for manufacturing a capacitor according to Comparative Example 1. FIG. [Figure 12B] FIG. 12B is a cross-sectional view showing a method for manufacturing a capacitor according to Comparative Example 1. [Figure 13A] FIG. 13A is a cross-sectional view showing a method for manufacturing a capacitor according to Comparative Example 1. FIG. [Figure 13B] FIG. 13B is a cross-sectional view showing a method for manufacturing a capacitor according to Comparative Example 1. [Figure 14A] FIG. 14A is a cross-sectional view showing a method for manufacturing a capacitor according to Comparative Example 2. As shown in FIG. [Figure 14B] FIG. 14B is a cross-sectional view showing a method for manufacturing a capacitor according to Comparative Example 2. [Figure 15A] FIG. 15A is a cross-sectional view showing a method for manufacturing a capacitor according to Comparative Example 2. As shown in FIG. [Figure 15B] FIG. 15B is a cross-sectional view showing a method for manufacturing a capacitor according to Comparative Example 2. [Figure 16] FIG. 16 is a cross-sectional view showing a method for manufacturing a capacitor according to Comparative Example 2. [Figure 17] FIG. 17 is a cross-sectional view of a capacitor according to a first modification of the first embodiment. [Figure 18] FIG. 18 is a cross-sectional view of a capacitor according to a second modification of the first embodiment. [Figure 19A] FIG. 19A is a cross-sectional view illustrating a method for manufacturing a capacitor according to a third modification of the first embodiment. [Figure 19B] FIG. 19B is a cross-sectional view illustrating a method for manufacturing a capacitor according to Modification 3 of Example 1. [Figure 20A] FIG. 20A is a cross-sectional view illustrating a method for manufacturing a capacitor according to a fourth modification of the first embodiment. [Figure 20B] FIG. 20B is a cross-sectional view illustrating a method for manufacturing a capacitor according to the fourth modification of the first embodiment. [Figure 21A] FIG. 21A is a cross-sectional view illustrating a method for manufacturing a capacitor according to a fourth modification of the first embodiment. [Figure 21B] FIG. 21B is a cross-sectional view illustrating a method for manufacturing a capacitor according to the fourth modification of the first embodiment. [Figure 22A] FIG. 22A is a cross-sectional view illustrating a method for manufacturing a capacitor according to a fifth modification of the first embodiment. [Figure 22B] FIG. 22B is a cross-sectional view illustrating a method for manufacturing a capacitor according to Modification 5 of Example 1. [Figure 23A] FIG. 23A is a cross-sectional view illustrating a method for manufacturing a capacitor according to a sixth modification of the first embodiment. [Figure 23B] FIG. 23B is a cross-sectional view illustrating a method for manufacturing a capacitor according to Modification 6 of Example 1. [Figure 24A] FIG. 24A is a cross-sectional view illustrating a method for manufacturing a capacitor according to a seventh modification of the first embodiment. [Figure 24B] FIG. 24B is a cross-sectional view illustrating a method for manufacturing a capacitor according to Modification 7 of Example 1. DETAILED DESCRIPTION OF THE INVENTION

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a capacitor comprising: a substrate; a first electrode provided on the substrate; a dielectric film provided on the first electrode; a second electrode provided on the dielectric film; a third electrode in contact with the second electrode in at least a first region of a lower surface of the capacitor; and an organic insulator film covering an upper portion of the dielectric film, an upper portion of the second electrode, and the third electrode, wherein the organic insulator film is not provided between the lower surface of the third electrode and the second electrode in the normal direction to the upper surface of the substrate. Because the organic insulator film is not provided between the lower surface of the third electrode and the second electrode, deterioration of the electrical characteristics of the capacitor due to stress in the organic insulator film can be suppressed. (2) It is preferable that the third electrode has an inorganic insulator film provided on the second electrode and having an opening in the first region, the first region of the lower surface of the third electrode contacts the second electrode through the opening, and the second region of the lower surface of the third electrode surrounding the first region contacts the inorganic insulator film outside the opening. (3) The third electrode preferably includes a seed layer provided on the second electrode and a plating layer provided on the seed layer. (4) It is preferable that a recess be provided in a third region of the upper surface of the inorganic insulating film that surrounds the third electrode. (5) It is preferable that the organic insulator film is not provided between the second electrode and a portion of the lower surface of the third electrode that is parallel to the upper surface of the substrate in the normal direction. (6) It is preferable that the third electrode comprises a first layer provided on the second electrode and a second layer provided on the first layer and having a resistivity lower than that of the first layer, and that the organic insulator film is not provided between the first layer and the second electrode in the normal direction. (7) One embodiment of the present disclosure is a method for manufacturing a capacitor, including the steps of: forming a first electrode on a substrate; forming a dielectric film on the first electrode; forming a second electrode on the dielectric film; forming a first mask layer having a first opening on the second electrode; forming a seed layer on an inner surface of the first opening and on the first mask layer; forming a second mask layer on the seed layer, the second mask layer having a second opening that is included in the first opening and has an opening area smaller than that of the first opening in a plan view; forming a plating layer in the second opening; removing the second mask layer; removing the seed layer using the plating layer as a mask to form a third electrode made of the seed layer and the plating layer; and forming an organic insulator film on the substrate to cover the third electrode, thereby suppressing deterioration of the electrical characteristics of the capacitor. (8) The step of forming the organic insulator film preferably includes a step of forming the organic insulator film so that the organic insulator film is not formed between the lower surface of the third electrode and the second electrode in the normal direction to the upper surface of the substrate. (9) It is preferable that the method includes a step of forming an inorganic insulator film having a third opening on the second electrode before forming the first mask layer, and the step of forming the second mask layer includes a step of forming the second mask layer having the second opening, which includes the third opening in a planar view and has an opening area larger than or equal to the opening area of ​​the third opening.

[0011] [Details of the embodiments of the present disclosure] Specific examples of capacitors and manufacturing methods thereof according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0012] [Example 1] FIG. 1 is a cross-sectional view of a capacitor according to Example 1. FIG. 2 is a plan view of the capacitor according to Example 1. FIG. 1 is a cross-sectional view taken along line AA in FIG. 2. FIG. 2 mainly illustrates a first electrode 14, a second electrode 18, a third electrode 20, and a region 50. The direction normal to the upper surface of the substrate 10 is the Z direction, and directions parallel to the upper surface of the substrate 10 are the X direction and the Y direction.

[0013] As shown in Fig. 1, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. The semiconductor layer 10b is, for example, a GaN-based semiconductor layer or a GaAs-based semiconductor layer. When the semiconductor layer 10b is a GaN-based semiconductor layer, the substrate 10a is, for example, a SiC substrate, a sapphire substrate, a silicon substrate, or a GaN substrate, and the semiconductor layer 10b includes a layer made of GaN, AlN, InN, or a mixed crystal thereof. When the semiconductor layer 10b is a GaAs-based semiconductor layer, the substrate 10a is, for example, a GaAs substrate, and the semiconductor layer 10b includes a layer made of GaAs, AlAs, InAs, or a mixed crystal thereof. The semiconductor layer 10b in the region where the capacitor is provided is passivated by ion implantation or the like. A transistor using the semiconductor layer 10b may be provided on the substrate 10, and the capacitor and transistor may be integrated on the same substrate 10 to form an MMIC (Monolithic Microwave Integrated Circuit). The substrate 10 does not necessarily have to be provided with the semiconductor layer 10b, and active elements such as transistors may not be provided on the substrate 10.

[0014] An insulator film 12 is provided on a substrate 10. The insulator film 12 is, for example, an inorganic insulator film such as a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film, or an organic insulator film such as polyimide or a BCB (Benzocyclobutene) resin. The thickness of the insulator film 12 is, for example, 100 nm to 1200 nm. A first electrode 14 is provided on the insulator film 12 on the substrate 10. A dielectric film 16 is provided on the first electrode 14. A second electrode 18 is provided on the dielectric film 16. The first electrode 14, the dielectric film 16, and the second electrode 18 form an MIM (Metal Insulator Metal) capacitor 60.

[0015] The distance between the first electrode 14 and the second electrode 18 via the dielectric film 16 is approximately uniform within the manufacturing tolerance. In a plan view seen from above in the Z direction (the normal direction to the upper surface of the substrate 10), the outer periphery of the first electrode 14 is located outside the outer periphery of the second electrode 18. The outer periphery of the dielectric film 16 is located outside the outer periphery of the first electrode 14. The first electrode 14 and the second electrode 18 are, for example, metal films including an adhesive film and a low-resistance film provided on the adhesive film. The adhesive film is, for example, a Ti film, a WSi film, a TiW film, a TiWN film, or a TiN film. The low-resistance film is made of a material with a lower resistivity than the adhesive film, for example, an Au film. The thickness of the adhesive film is, for example, 3 nm to 300 nm. The adhesive film may not be provided. The thickness of the low-resistance film is, for example, 50 nm to 400 nm. The dielectric film 16 is, for example, an inorganic insulator film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film. From the viewpoint of increasing the dielectric constant, a silicon nitride film is preferable for the dielectric film 16. The thickness of the dielectric film 16 is, for example, 50 nm to 400 nm. The thickness of the dielectric film 16 is set in consideration of the capacitance value and withstand voltage of the MIM capacitor 60.

[0016] An inorganic insulator film 22 is provided to cover the second electrode 18. The inorganic insulator film 22 is, for example, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film, and from the viewpoint of protecting the MIM capacitor 60, the inorganic insulator film 22 is preferably a silicon nitride film. The inorganic insulator film 22 has a thickness of, for example, 50 nm to 400 nm. In a region 50, an opening 23 is provided in the inorganic insulator film 22. A third electrode 20 is provided on the second electrode 18. In a region 50 corresponding to the central region of the lower surface of the third electrode 20, the lower surface of the third electrode 20 contacts the second electrode 18 via the opening 23. In a region 52 outside the region 50, the lower surface of the third electrode 20 contacts the inorganic insulator film 22. The combined region of regions 50 and 52 is region 54. A region 56 larger than region 54 is provided. In a region 55 of region 56 other than the third electrode 20, a recess 23a is formed in the upper surface of the inorganic insulator film 22. The second electrode 18 is provided in the region 51 .

[0017] The third electrode 20 includes, from the second electrode 18 side, a seed layer 20d and a plating layer 20c provided on the seed layer 20d. The seed layer 20d is, for example, a metal layer including an adhesion layer 20a and a low-resistance layer 20b provided on the adhesion layer 20a. The adhesion layer 20a is, for example, a Ti film, a WSi film, a TiW film, a TiWN film, or a TiN film. The low-resistance layer 20b is made of a material having a lower resistivity than the adhesion layer 20a, for example, an Au film. The thickness of the adhesion layer 20a is, for example, 3 nm to 400 nm. The adhesion layer 20a does not necessarily have to be provided. The thickness of the low-resistance layer 20b is, for example, 50 nm to 200 nm. The plating layer 20c is a metal film made of the same material as the low-resistance layer 20b, for example, an Au film. The thickness of the plating layer 20c is, for example, 1 μm to 6 μm.

[0018] An inorganic insulator film 24 is provided so as to cover the inorganic insulator film 22 and the third electrode 20. The inorganic insulator film 24 is, for example, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film. From the viewpoint of protective function, it is preferable to use a silicon nitride film as the inorganic insulator film 24. The thickness of the inorganic insulator film 24 is, for example, 30 nm to 800 nm. The inorganic insulator film 24 does not have to be provided. An organic insulator film 26 is provided so as to cover the inorganic insulator film 24. The organic insulator film 26 is, for example, a resin film such as polyimide or BCB resin. The thickness of the organic insulator film 26 is, for example, 1 μm to 10 μm.

[0019] As shown in FIG. 2, the first electrode 14 is provided on the -Y side of the region where the MIM capacitor 60 is provided. On the -Y side of the MIM capacitor 60, an electrode 21 is provided on the upper surface of the first electrode 14. The electrode 21 contacts the first electrode 14 in a region 50a. The electrode 21 includes the same seed layer 20d and plating layer 20c as the third electrode 20, and is formed simultaneously with the third electrode 20. The third electrode 20, which is in contact with the second electrode 18, is provided on the +Y side of the region where the MIM capacitor 60 is provided. The third electrode 20 functions as wiring electrically connecting to the second electrode 18, and the electrode 21 functions as wiring electrically connecting to the first electrode 14.

[0020] The widths of regions 50, 54, and 56 are defined as L1, L2, and L3, respectively. If the width of second electrode 18 is defined as L4, width L3 is smaller than width L4, width L2 is equal to or smaller than width L3, and width L1 is equal to or smaller than width L2. Preferably, width L2 is smaller than width L3, and width L1 is smaller than width L2. As shown in FIG. 2, when the planar size of first electrode 14 is larger than the planar size of second electrode 18 when viewed from the positive side to the negative side in the Z direction, width L4 of second electrode 18 is designed based on the target capacitance value of MIM capacitor 60 and is, for example, 10 μm to 1 mm. Width L1 of region 50 is, for example, 1 μm to 10 μm smaller than width L4. Width L2 of region 54 is, for example, 0 μm to 5 μm larger than width L1. Width L3 of region 56 is, for example, 0 μm to 5 μm larger than width L2.

[0021] [Manufacturing method of Example 1] 3A to 10B are cross-sectional views showing a method for manufacturing a capacitor according to Example 1. As shown in FIG. 3A, an insulating film 12 is formed on a substrate 10. A first electrode 14 is formed on the insulating film 12. The first electrode 14 is formed using a sputtering method or a vacuum deposition method, and is patterned into a desired shape using an etching method or a lift-off method. As shown in FIG. 3B, a dielectric film 16 is formed on the insulating film 12 so as to cover the first electrode 14. The dielectric film 16 is formed using, for example, a CVD (Chemical Vapor Deposition) method.

[0022] As shown in FIG. 4A, a second electrode 18 is formed on the dielectric film 16. The second electrode 18 is formed by, for example, vacuum deposition and lift-off. The first electrode 14, the dielectric film 16, and the second electrode 18 form an MIM capacitor 60. As shown in FIG. 4B, an inorganic insulator film 22 is formed so as to cover the dielectric film 16 and the second electrode 18. The inorganic insulator film 22 is formed by, for example, CVD. The dielectric film 16 and the inorganic insulator film 22 are patterned into a desired shape by etching.

[0023] As shown in FIG. 5A, a mask layer 40 having an opening 41 is formed on the inorganic insulator film 22. The mask layer 40 is, for example, a photoresist and is formed using photolithography. The opening 41 is provided in a region 50, and the width of the opening 41 along the X direction is L1. As shown in FIG. 5B, the inorganic insulator film 22 is removed using an etching method with the mask layer 40 as a mask. As a result, an opening 23 is formed in the inorganic insulator film 22. The opening 23 is provided in the region 50, and the width of the opening 23 along the X direction is L1.

[0024] As shown in FIG. 6A, the mask layer 40 is removed. As shown in FIG. 6B, a mask layer 42 having an opening 43 is formed on the inorganic insulator film 22. The mask layer 42 is, for example, a photoresist and is formed using photolithography. The opening 43 is provided in the region 56, and the width of the opening 43 along the X direction is L3. The opening 43 is formed so as to include the opening 23 and is larger than the opening 23.

[0025] As shown in FIG. 7A, a seed layer 20d is formed on the inner surface of the opening 43 and on the mask layer 42. The seed layer 20d is formed using, for example, a sputtering method. In region 50, the seed layer 20d contacts the upper surface of the second electrode 18. In the region 56 other than region 50, the seed layer 20d contacts the upper surface of the inorganic insulator film 22. As shown in FIG. 7B, a mask layer 44 having an opening 45 is formed on the seed layer 20d. The mask layer 44 is, for example, a photoresist and is formed using a photolithography method. The opening 45 is provided in region 54, and the width of the opening 45 along the X direction is L2. The opening 45 is formed to include the opening 23 and to be contained within the opening 43. The opening 45 is larger than the opening 23 but smaller than the opening 43. In region 52 surrounding region 50, the seed layer 20d contacts the inorganic insulator film 22.

[0026] As shown in Fig. 8A, a plating layer 20c is formed in the opening 45. The plating layer 20c is formed, for example, by electrolytic plating, in which a current is supplied from the seed layer 20d. The plating layer 20c is formed in the region 54. As shown in Fig. 8B, the mask layer 44 is removed.

[0027] As shown in FIG. 9A, the seed layer 20d is removed using the plating layer 20c as a mask. The seed layer 20d is removed using an etching method such as ion milling, in which ions 48, such as argon ions, are irradiated onto the seed layer 20d. As a result, the seed layer 20d formed outside of region 54 is removed, and a third electrode 20 consisting of the seed layer 20d and the plating layer 20c is formed. In region 52 of region 54 other than region 50, the third electrode 20 contacts the inorganic insulator film 22. In region 55 of region 56 other than region 54, a recess 23a is formed in the upper surface of the inorganic insulator film 22. The recess 23a is formed by scraping off the upper surface of the inorganic insulator film 22 when the seed layer 20d is removed. As shown in FIG. 9B, the mask layer 42 is removed.

[0028] As shown in FIG. 10A, an inorganic insulator film 24 is formed on the substrate 10 so as to cover the inorganic insulator film 22 and the third electrode 20. The inorganic insulator film 24 is formed by, for example, a CVD method. As shown in FIG. 10B, an organic insulator film 26 is formed on the inorganic insulator film 24. The organic insulator film 26 is formed by applying a resin containing an organic solvent and performing a heat treatment. The heat treatment is performed at a temperature of, for example, 250°C to 350°C. This hardens the resin, and the organic insulator film 26 is formed. In this way, the capacitor according to Example 1 is manufactured.

[0029] In Example 1, region 54 is larger than region 50, and region 56 is larger than region 54. As a result, the lower surface of third electrode 20 contacts second electrode 18 in region 50 and contacts inorganic insulator film 22 in region 52. No organic insulator film 26 is provided between region 50 or the lower surface of third electrode 20 represented by width L1 along the X direction and second electrode 18.

[0030] [Comparative Example 1] 11A to 13B are cross-sectional views showing a method for manufacturing a capacitor according to Comparative Example 1. As shown in FIG. 11A, the same steps as those shown in FIGS. 3A to 5B of Example 1 are performed. An opening 23 defined by an opening 41 in a mask layer 40 is formed in an inorganic insulator film 22. The opening 23 is provided in a region 50, and the width of the opening 23 is L1 along the X direction. As shown in FIG. 11B, a mask layer 42 having an opening 43 is formed on the inorganic insulator film 22 and the second electrode 18. The opening 43 is larger than the opening 23. The opening 43 is provided in a region 54, and the width of the opening 43 is L3 along the X direction.

[0031] As shown in Fig. 12A, a seed layer 20d is formed on the inner surface of the opening 43 and on the mask layer 42. As shown in Fig. 12B, a mask layer 44 having an opening 45 is formed. The opening 45 is larger than the opening 43. The opening 45 is provided in the region 58, and the width of the opening 45 is L5 along the X direction. A plating layer 20c is formed in the opening 45.

[0032] As shown in FIG. 13A, mask layer 44 is removed. Seed layer 20d is removed using plating layer 20c as a mask. Mask layer 42 is removed. Overhangs of third electrode 20 are formed in region 57 of region 58 other than region 54. As shown in FIG. 13B, inorganic insulator film 24 is formed to cover inorganic insulator film 22 and third electrode 20. Organic insulator film 26 is formed on inorganic insulator film 24. Inorganic insulator film 24 and organic insulator film 26 are also formed between the underside of the overhangs of third electrode 20 in region 57 and second electrode 18. In this way, the capacitor of Comparative Example 1 can be manufactured.

[0033] In Comparative Example 1, as shown in FIG. 11B, a mask layer 42 having an opening 43 is formed, and then a seed layer 20d is formed as shown in FIG. 12A. This is because if the seed layer 20d is formed without forming the mask layer 42, the seed layer 20d remaining in the steps on the upper surface of the inorganic insulator film 22 will peel off after the seed layer 20d is removed, causing defects. Details will be described in Modification 3 of Example 1. As shown in FIG. 12B, a mask layer 44 having an opening 45 larger than the opening 43 is formed, and a plating layer 20c is formed in the opening 45. As shown in FIG. 13A, the seed layer 20d is removed using the plating layer 20c as a mask. Because the upper surface of the mask layer 42 is relatively flat, no steps are formed and the seed layer 20d does not remain. Even if steps are formed on the upper surface of the mask layer 42 and the seed layer 20d remains, the remaining seed layer 20d can be removed by removing the mask layer 42.

[0034] However, the width L5 of region 58 is greater than the width L3 of region 54. Therefore, as shown in FIG. 13B , an overhang of the third electrode 20 is formed in region 57. The organic insulator film 26 has a higher stress than the inorganic insulator film 22. Furthermore, the inorganic insulator film 22 is sufficiently thin compared to the height of the overhang of the third electrode 20, and the thickness of the organic insulator film 26 along the Z direction in region 57 below the overhang of the third electrode 20 is often greater than the total thickness of the inorganic insulator film 22. Therefore, as shown by arrow 62 in FIG. 13B , stress 62 of the organic insulator film 26 between the third electrode 20 and the second electrode 18 in region 57 is applied to the third electrode 20 along the X direction as shown by arrow 62. In particular, when the organic insulator film 26 is heat-treated, the organic insulator film 26 shrinks, increasing stress 62. This may cause the third electrode 20 to peel off from the second electrode 18. Furthermore, the stress 62 may reduce the breakdown voltage of the MIM capacitor 60, or may cause the electrical characteristics to deteriorate during use.

[0035] Comparative Example 2 14A to 16 are cross-sectional views showing a method for manufacturing a capacitor according to Comparative Example 2. As shown in FIG. 14A, an organic insulator film 26a is formed on an inorganic insulator film 22. A mask layer 46 having an opening 47 is formed on the organic insulator film 26a. The mask layer 46 is an inorganic insulator film such as a silicon nitride film. Using the mask layer 46 as a mask, an opening 27 is formed in the organic insulator film 26a. As shown in FIG. 14B, using the organic insulator film 26a as a mask, an opening 23 is formed in the inorganic insulator film 22. A seed layer 20d is formed on the inner surfaces of the openings 27 and 23 and on the organic insulator film 26a.

[0036] As shown in FIG. 15A, a mask layer 44 having an opening 45 is formed on the seed layer 20d. The opening 45 is provided in a region 58, and the width of the opening 45 along the X direction is L5. A plating layer 20c is formed in the opening 45. As shown in FIG. 15B, the mask layer 44 is removed, and the seed layer 20d is removed using the plating layer 20c as a mask. An overhang of the third electrode 20 is formed in a region 57 of the region 58 other than the region 50.

[0037] 16, an inorganic insulator film 24 is formed so as to cover the organic insulator film 26a and the third electrode 20. An organic insulator film 26b is formed on the inorganic insulator film 24. In this way, the capacitor according to Comparative Example 2 can be manufactured.

[0038] In Comparative Example 2, in region 57, organic insulator film 26a is also formed between the lower surface of third electrode 20 and second electrode 18 in the Z direction. As indicated by arrow 62, stress 62 of organic insulator film 26 between third electrode 20 and second electrode 18 is applied to third electrode 20 along the X direction as indicated by arrow 62. This may cause third electrode 20 to peel off from second electrode 18. Furthermore, the withstand voltage of MIM capacitor 60 may decrease, or its electrical characteristics may deteriorate with use.

[0039] According to Example 1, as shown in FIG. 1 , the bottom surface of the third electrode 20 in the negative direction along the Z direction contacts the second electrode 18 in region 50. The organic insulator film 26 is provided to cover the upper portion of the dielectric film 16, the upper portion of the second electrode 18, and the third electrode 20. However, the organic insulator film 26 is not provided between the lower surface of the third electrode 20 and the second electrode 18 in the Z direction (the normal direction to the upper surface of the substrate 10), including region 50 and its surrounding region 52. That is, the organic insulator film 26 is not provided vertically below (in the negative Z direction) the lower surface of the third electrode 20. This prevents peeling of the third electrode 20 due to stress 62 caused by the organic insulator film 26 provided under the eaves of the third electrode 20, as in Comparative Examples 1 and 2 of FIGS. 13B and 16 . Furthermore, it is possible to prevent a decrease in the breakdown voltage of the MIM capacitor 60 or deterioration of its electrical characteristics due to use. In this way, the deterioration of the electrical characteristics of the capacitor caused by the stress 62 of the organic insulator film 26 can be suppressed.

[0040] [Modification 1 of Example 1] FIG. 17 is a cross-sectional view of a capacitor according to Modification 1 of Example 1. As shown in FIG. 17, a third electrode 20 is provided within an opening 23 in an inorganic insulator film 22. The entire lower surface of the third electrode 20 is in contact with the second electrode 18, but is not in contact with the upper surface of the inorganic insulator film 22. The second electrode 18 can be formed using, for example, electroless plating or vacuum deposition. The other configurations are the same as in Example 1, and a description thereof will be omitted. As in Modification 1 of Example 1, the entire lower surface of the third electrode 20 may be in contact with the second electrode 18. In this way, it is sufficient that at least a partial region 50 of the lower surface of the third electrode 20 is in contact with the upper surface of the second electrode 18.

[0041] [Modification 2 of Example 1] FIG. 18 is a cross-sectional view of a capacitor according to Modification 2 of Example 1. As shown in FIG. 18, the side surface of the third electrode 20 is inclined with respect to the Z direction. The inclination angle of the side surface of the third electrode 20 with respect to the Z direction is θ. The inclination angle θ is, for example, −30° to 30°, with the positive direction in the Z direction being 0°. The other configurations are the same as those of Example 1, and therefore a description thereof will be omitted. Even if the side surface of the third electrode 20 is inclined as in Modification 2 of Example 1, if the organic insulator film 26 is not provided between the lower surface of the third electrode 20 and the second electrode 18, deterioration of electrical characteristics due to stress in the organic insulator film 26 can be suppressed. When the side surface of the third electrode 20 is inclined, the side surface of the third electrode 20 can be said to be the lower surface of the third electrode 20. In such a case, it is sufficient that the organic insulator film 26 is not provided between the second electrode 18 and a portion of the lower surface of the third electrode 20 parallel to the upper surface of the substrate 10 in the Z direction.

[0042] When the third electrode 20 is used as wiring, the third electrode 20 is made thick. The third electrode 20 is thicker than the second electrode 18, for example. The thickness of the third electrode 20 is greater than the total thickness of the first electrode 14, the dielectric film 16, and the second electrode 18, and is, for example, 1 μm or more. A typical method for forming such a thick third electrode 20 is electrolytic plating. For this reason, a capacitor is manufactured as shown in FIGS. 3A to 10B of Example 1.

[0043] [Modification 3 of Example 1] Modification 3 of Example 1 will be described to explain the reason for providing the mask layer 42 in Example 1. FIGS. 19A and 19B are cross-sectional views showing a method for manufacturing a capacitor according to Modification 3 of Example 1. As shown in FIG. 19A, the steps of FIGS. 3A to 6A of Example 1 are performed, and in FIG. 6B, the mask layer 42 is not formed, and a seed layer 20d is formed. As in FIGS. 7B and 8A, a plating layer 20c is formed. As in FIG. 8B, the mask layer 44 is removed. In Modification 3 of Example 1, the mask layer 42 as shown in FIG. 6B of Example 1 is not formed. Therefore, the seed layer 20d comes into contact with the inorganic insulator film 22. The upper surface of the inorganic insulator film 22 has steps corresponding to the ends of the first electrode 14 and the second electrode 18. The seed layer 20d is also formed on the steps on the upper surface of the inorganic insulator film 22.

[0044] 19B, when the seed layer 20d is etched using the plating layer 20c as a mask, the seed layer 64 remains on the steps on the upper surface of the inorganic insulator film 22. Thereafter, the inorganic insulator film 24 and the organic insulator film 26 are formed in the same manner as in FIG. 10A and FIG. 10B of Example 1. The other steps are the same as in Example 1, and therefore will not be described again.

[0045] In the third modification of the first embodiment, the remaining seed layer 64 may peel off in a subsequent process, potentially causing defects. In the first embodiment, the upper surface of the mask layer 42 is relatively flat, as shown in FIG. 6B, and therefore no steps are formed on the upper surface of the mask layer 42. Therefore, as shown in FIG. 9A, the seed layer 20d does not remain on the steps on the upper surface of the inorganic insulator film 22. Even if steps are formed on the upper surface of the mask layer 42 and the seed layer 20d remains, the remaining seed layer 20d can be removed by removing the mask layer 42. Furthermore, by sloping the side surfaces of the openings 43 in the mask layer 42 so that the upper portions of the openings 43 are larger than the lower portions, the seed layer 20d is less likely to remain on the side surfaces of the mask layer 42.

[0046] In Example 1, as shown in FIGS. 3A to 4A, a first electrode 14, a dielectric film 16, and a second electrode 18 are formed on a substrate 10. As shown in FIG. 6B, a mask layer 42 (first mask layer) having an opening 43 (first opening) is formed on the second electrode 18. As shown in FIG. 7A, a seed layer 20d is formed on the inner surface of the opening 43 and on the mask layer 42. As shown in FIG. 7B, a mask layer 44 (second mask layer) having an opening 45 (second opening) that is included in the opening 43 but has a smaller opening area than the opening 43 in a plan view is formed on the seed layer 20d. As shown in FIG. 8A, a plating layer 20c is formed in the opening 45. As shown in FIG. 8B, the mask layer 44 is removed. As shown in FIG. 9A, the seed layer 20d is removed using the plating layer 20c as a mask, thereby forming a third electrode 20 by the seed layer 20d and the plating layer 20c. As shown in FIG. 10B, an organic insulator film 26 is formed on the substrate 10 so as to cover the third electrode 20. As described above, the third electrode 20 can be formed using electrolytic plating, allowing the third electrode 20 to be thick. Furthermore, when the organic insulator film 26 is formed, the organic insulator film 26 is not formed between the lower surface of the third electrode 20 and the second electrode 18 in the Z direction. This makes it possible to suppress deterioration of the electrical characteristics of the capacitor due to the stress 62 of the organic insulator film 26. Furthermore, it is possible to suppress defects caused by the seed layer 64 remaining on the steps on the upper surface of the inorganic insulator film 22, as in Modification 3 of Example 1.

[0047] 4B to 6A, before forming the mask layer 42, an inorganic insulator film 22 having an opening 23 (third opening) is formed on the second electrode 18. As shown in FIG. 6B, a mask layer 42 is formed having an opening 43 that includes the opening 23 and has an opening area that is equal to or larger than the opening area of ​​the opening 23. By providing the inorganic insulator film 22 in this manner, it is possible to prevent the upper surface of the second electrode 18 in the region 55 from being scraped off when the seed layer 20d is etched in FIG. 9A.

[0048] 1 , an inorganic insulator film 22 having an opening 23 in a region 50 is provided on a second electrode 18. Region 50 of the lower surface of third electrode 20 contacts second electrode 18 via opening 23, and region 52 of the lower surface of third electrode 20 surrounding region 50 contacts inorganic insulator film 22 outside opening 23.

[0049] Furthermore, since the third electrode 20 is formed by electrolytic plating, the third electrode 20 has a structure including a seed layer 20d provided on the second electrode 18 and a plating layer 20c provided on the seed layer 20d. In such a structure, it is preferable to provide an inorganic insulator film 22 so that the upper surface of the second electrode 18 is not scraped when the seed layer 20d is removed.

[0050] 9A , when the seed layer 20d is etched, a recess 23a is formed in a region 55 (third region) on the upper surface of the inorganic insulator film 22 that surrounds the third electrode 20. If the outer periphery of the region 55 is located outside the outer periphery of the second electrode 18, the seed layer 64 remains on a step on the upper surface of the inorganic insulator film 22 located at the end of the second electrode 18. Therefore, it is preferable that the outer periphery of the region 55 is located inside the outer periphery of the second electrode 18.

[0051] The seed layer 20d is provided with an adhesion layer 20a and a low-resistance layer 20b having a resistivity lower than that of the adhesion layer 20a. As a result, the third electrode 20 includes an adhesion layer 20a (first layer) provided on the second electrode 18, and a low-resistance layer 20b and a plating layer 20c (second layer) provided on the adhesion layer 20a and having a resistivity lower than that of the adhesion layer 20a. In this structure, the organic insulator film 26 is not provided between the adhesion layer 20a and the second electrode 18 in the Z direction. This makes it possible to suppress deterioration of the electrical characteristics of the capacitor due to stress 62 of the organic insulator film 26.

[0052] [Modification 4 of Example 1] 20A to 21B are cross-sectional views showing a method for manufacturing a capacitor according to Modification 4 of Example 1. As shown in FIG. 20A, a seed layer 20d is formed on a mask layer 42 having an opening 43 and within the opening 43. The width L3 of the opening 43 in the mask layer 42 along the X direction is smaller than that shown in FIG. 7A of Example 1. As shown in FIG. 20B, the width L2 of an opening 45 in the mask layer 44 formed on the seed layer 20d along the X direction is slightly smaller than the width L3 of the opening 43 along the X direction. A plating layer 20c is formed within the opening 43. Because the widths L3 and L2 are approximately the same, the plating layer 20c is formed on the seed layer 20d formed on the side surface of the opening 43 at the periphery of the opening 45.

[0053] As shown in FIG. 21A, after removing the mask layer 44, the seed layer 20d is etched using the plating layer 20c as a mask. At this time, at least a portion of the seed layer 20d formed on the side surface of the opening 43 is etched, causing a step 66 in the seed layer 20d. As shown in FIG. 21B, an inorganic insulator film 24 and an organic insulator film 26 are formed. In this way, a capacitor according to the fourth modification of the first embodiment is manufactured. The other steps are the same as those of the first embodiment, and therefore a description thereof will be omitted.

[0054] In FIG. 20B , even if the width L3 of the opening 43 along the X direction and the width L2 of the opening 45 along the X direction are the same, if the openings 43 and 45 are aligned, the organic insulator film 26 is not provided between the lower surface of the third electrode 20 and the second electrode 18. However, considering misalignment between the openings 43 and 45, the width L2 is preferably smaller than the width L3. If the difference between the widths L2 and L3 is small, a step 66 will be formed in the seed layer 20d, as in Variation 4 of Example 1 ( FIGS. 21A and 21B ). To prevent the formation of the step 66, the width L2 of the opening 45 along the X direction is preferably smaller than the width L3 of the opening 43 along the X direction by at least two times the thickness of the seed layer 20d, and more preferably at least five times smaller. Furthermore, considering the alignment accuracy between the openings 45 and 43, the width L2 is preferably larger than the width L3 by at least 1 μm, and more preferably by at least 2 μm.

[0055] [Modification 5 of Example 1] 22A and 22B are cross-sectional views showing a method for manufacturing a capacitor according to Modification 5 of Example 1. As shown in FIG. 22A, an organic insulator film 26a having an opening 27 is provided in place of the mask layer 42 shown in FIG. 20A of Modification 4 of Example 1. The opening 27 is provided in a region 56 along the X direction, and the width of the opening 27 along the X direction is L3. As shown in FIG. 22B, a third electrode 20 is formed in the same manner as in Modification 4 of Example 1, and an inorganic insulator film 24 and an organic insulator film 26b are formed on the organic insulator film 26a and the third electrode 20. The other steps are the same as those in Example 1 and Modification 4 of Example 1, and therefore description thereof will be omitted.

[0056] Example 1 Variations As in Example 5, the organic insulating film 26a may be used instead of the mask layer 42, and the organic insulating film 26a may be left without being removed.

[0057] [Modification 6 of Example 1] 23A and 23B are cross-sectional views showing a method for manufacturing a capacitor according to Modification 6 of Example 1. As shown in FIG. 23A, width L2 of opening 45 in the X direction is slightly larger than width L1 of opening 23 in the X direction. The negative side end of opening 45 in the X direction substantially coincides with the negative side end of opening 23 in the X direction. The +X side end of opening 45 is located outside the +X side end of opening 23. In FIG. 23A, region 52 is located closer to region 50 in the X direction than region 50. + 23B, a capacitor according to Modification 6 of Example 1 is manufactured by carrying out the steps of FIGS. 8B to 10B of Example 1. The other steps are the same as those of Example 1, and therefore a description thereof will be omitted.

[0058] 23A, width L2 may be the same as width L1. However, if misalignment occurs between opening 45 and opening 23, a region will result in opening 23 being located outside opening 45. In this case, as shown in FIG. 9A, when seed layer 20d is etched using plating layer 20c as a mask, the upper surface of second electrode 18 will be scraped off. Therefore, width L2 is preferably larger than width L1. From the perspective of the alignment accuracy between openings 45 and 23, width L1 is preferably smaller than width L2 by 1 μm or more, and more preferably smaller by 2 μm or more.

[0059] [Seventh Modification of the First Embodiment] 24A and 24B are cross-sectional views showing a method for manufacturing a capacitor according to Modification 7 of Example 1. As shown in FIG. 24A, width L2 of opening 45 along the X direction is slightly smaller than width L3 of opening 43 along the X direction. The negative end of opening 45 in the X direction substantially coincides with the negative end of opening 43 in the X direction. The positive end of opening 45 in the X direction is located more inward than the positive end of opening 43 in the X direction. As shown in FIG. 24B, a capacitor according to Modification 7 of Example 1 is manufactured by performing the steps of FIGS. 8B to 10B of Example 1. Figure 24B In this example, the region 55 exists only on the positive side of the region 54 in the X direction. The other steps are the same as those in the first embodiment, and therefore a description thereof will be omitted.

[0060] 24A, width L2 may be the same as width L3. However, if misalignment occurs between opening 45 and opening 43, a region will result in opening 43 being positioned outside opening 45. In this case, organic insulator film 26 will be formed between the lower surface of third electrode 20 and second electrode 18. Therefore, width L3 is preferably larger than width L2. From the viewpoint of the alignment accuracy between openings 45 and 43, width L3 is preferably larger than width L2 by 1 μm or more, and more preferably by 2 μm or more.

[0061] In the first embodiment and its modified examples, the second electrode 18 may be formed as two layers as in Patent Document 1. This makes it possible to suppress a decrease in the breakdown voltage of the capacitor caused by splashes formed when the second electrode 18 is formed by vacuum deposition.

[0062] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0063] 10, 10a board 10b Semiconductor layer 12 Insulator film 14 1st electrode 16 Dielectric film 18 2nd electrode 20 3rd electrode 20a Adhesion layer 20b low resistance layer 20c plating layer 20d seed layer 21 electrodes 22, 24 Inorganic insulating film 23 Opening (3rd Opening) 23a Recess 26, 26a, 26b Organic insulator film 27, 41, 47 aperture 40, 46 Mask layer 42 Mask layer (first mask layer) 43 Opening (1st opening) 44 Mask layer (second mask layer) 45 opening (second opening) 50 areas (1st area) 52 area (second area) 55 area (3rd area) 50a, 51, 54, 56~58 area 60 MIM capacitors 62 Stress 64 seed layer 66 steps

Claims

1. forming a first electrode on a substrate; forming a dielectric film on the first electrode; forming a second electrode on the dielectric film; forming a first mask layer having a first opening on the second electrode; forming a seed layer on the inner surface of the first opening and on the first mask layer; forming a second mask layer on the seed layer, the second mask layer having a second opening that is included in the first opening and has an opening area smaller than that of the first opening in a plan view; forming a plating layer in the second opening; and removing the second mask layer; removing the seed layer using the plating layer as a mask to form a third electrode made of the seed layer and the plating layer; forming an organic insulator film on the substrate so as to cover the third electrode; A method for manufacturing a capacitor comprising:

2. 2. The method for manufacturing a capacitor according to claim 1, wherein the step of forming the organic insulator film includes a step of forming the organic insulator film so that the organic insulator film is not formed between the lower surface of the third electrode and the second electrode in a direction normal to the upper surface of the substrate.

3. forming an inorganic insulator film having a third opening on the second electrode before forming the first mask layer; 3. The method for manufacturing a capacitor according to claim 1, wherein the step of forming the second mask layer includes a step of forming the second mask layer having the second opening, which includes the third opening in a planar view and has an opening area larger than or equal to the opening area of ​​the third opening.

Images