Rate matching method and rate matching device

Abstract

The present application relates to a method for transmitting a bit sequence to be encoded, the method comprising the steps of: a transmitter obtaining a bit sequence to be encoded; the transmitter performing polar encoding on the bit sequence to be encoded to obtain a first bit sequence, the first bit sequence having a length N; the transmitter performing first rate matching on the first bit sequence to obtain a second bit sequence, the second bit sequence having a length E1; the transmitter transmitting the second bit sequence; and the transmitter performing rate matching on the bit sequence to be encoded to obtain a third bit sequence. and a transmitter performing second rate matching on the third bit sequence to obtain a fourth bit sequence, the fourth bit sequence having a length E2, the second rate matching being determined based on a relationship between f(E1) and E2, the value of f(E1) being determined based on E1. The present invention provides a rate matching method including the steps of: performing polar encoding on a third bit sequence, the third bit sequence having a length of 2*N, the transmitter performing second rate matching on the third bit sequence to obtain a fourth bit sequence, the fourth bit sequence having a length E2, the second rate matching being determined based on a relationship between f(E1) and E2, the value of f(E1) being determined based on E1; and transmitting the fourth bit sequence, where N, E1, and E2 are positive integers.

Description

[Technical Field]

[0001] This application claims priority to Chinese Patent Application No. 202111522959.8, entitled "Rate Matching Method and Rate Matching Apparatus," filed with the State Intellectual Property Office of China on December 13, 2021, which is incorporated herein by reference in its entirety.

[0002] TECHNICAL FIELD Embodiments of the present application relate to the field of communication technology, and in particular to a rate matching method and a rate matching device. [Background technology]

[0003] Channel coding / decoding (forward error correction) is one of the key technologies in communication systems and is crucial for improving system sensitivity and preventing interference. Polar coding has been theoretically proven to be the first channel coding scheme that can achieve Shannon capacity with low coding / decoding complexity and perform much better than other competing channel coding schemes in scenarios with short code lengths or low code rates. In the 5th generation (5G) communication system, Polar coding has been selected as the coding scheme for the control channel.

[0004] In communication applications that are not sensitive to system latency, hybrid automatic repeat request (HARQ) is a common transmission method used to improve system throughput. For polar-code HARQ transmission methods, an efficient solution is incremental redundancy HARQ (IR-HARQ), which is usually classified as HARQ-II (HARQ-II). In IR-HARQ, when there is no rate matching (i.e., no puncturing or shortening is required), stable performance can be achieved by selecting the number and position of bits that need to be copied based on the reliability sequence. However, in practical systems, the number of resources for initial transmission and the number of resources for retransmission are not necessarily equal, and the number of bits obtained after encoding for retransmission is less than the number of bits obtained after encoding for initial transmission. In this case, a rate matching scheme must be designed to ensure stable performance. Otherwise, performance will be impaired due to defective pixels due to unexpected copy numbers and unexpected copy positions based on long sequences. Therefore, how to design an appropriate rate matching method for IR-HARQ becomes an urgent problem that needs to be solved. Summary of the Invention

[0005] The embodiments of the present application provide a rate matching method and a rate matching device that ensure stable performance of IR-HARQ. [Means for solving the problem]

[0006] According to a first aspect of the present application, there is provided a rate matching method, which includes:

[0007] a transmitter obtaining a bit sequence to be encoded; a transmitter performing polar encoding on the bit sequence to be encoded to obtain a first bit sequence, the first bit sequence having a length N; a transmitter performing first rate matching on the first bit sequence to obtain a second bit sequence, the second bit sequence having a length E1; and a transmitter transmitting the second bit sequence. The method includes the steps of: a transmitter performing polar encoding based on the bit sequence to be encoded to obtain a third bit sequence, wherein the length of the third bit sequence is 2*N; a transmitter performing second rate matching on the third bit sequence to obtain a fourth bit sequence, wherein the length of the fourth bit sequence is E2, the second rate matching is determined based on a relationship between f(E1) and E2, and the value of f(E1) is determined based on E1; and a transmitter transmitting the fourth bit sequence, wherein N, E1, and E2 are positive integers.

[0008] The first aspect relates to a rate matching mechanism that can be applied to the transmitter side in IR-HARQ, where a rate matching method is designed for each of an initial transmission bit sequence and a retransmission bit sequence to fill the gap in the prior art that there is no rate matching method for IR-HARQ. Furthermore, the rate matching method designed for the retransmission bit sequence is determined based on the relationship between the initial transmission bit sequence and the retransmission bit sequence, and a flexible rate matching method is designed for different correspondence relationships between different numbers of retransmission bits and different numbers of initial transmission bits, so that the rate matching can accurately adapt to actual situations and ensure that the performance of IR-HARQ is always stable and excellent.

[0009] In one possible embodiment, f(E1)=a*E1+b, where a is a constant greater than 0 and less than or equal to 1, and b is a constant with an absolute value less than E1.

[0010] In one possible embodiment, f(E1)=a*E1+b, where a and b are constants, and f(E1) is less than or equal to E1.

[0011] In one possible implementation, if E2 is greater than or equal to f(E1), the second rate matching is performed based on the fifth bit sequence, or if E2 is less than f(E1), the second rate matching includes puncturing all bits in the fifth bit sequence whose sequence numbers fall within [0, N / 2-1] and performing third rate matching on all bits in the fifth bit sequence whose sequence numbers fall within [N / 2, N-1], wherein the fifth bit sequence consists of all bits in the third bit sequence whose sequence numbers fall within [0, N-1].

[0012] In this embodiment, the fifth bit sequence is the first half of the third bit sequence, i.e., the fifth bit sequence consists of all bits whose sequence numbers fall within [0,N-1] in the third bit sequence. If E2 is equal to or greater than f(E1), the second rate matching is performed based on the mother code length N. If E2 is less than f(E1), the second rate matching is performed based on half the mother code length, i.e., N / 2.

[0013] In one possible embodiment, when E2 is greater than or equal to f(E1): If E2 is less than N, the second rate matching is bit-reversal shortening, or if E2 is greater than N, the second rate matching is repetition, or If E2 is less than f(E1): If E2 is less than N / 2, the third rate matching is bit reversal shortening, or if E2 is greater than N / 2, the third rate matching is repetition; f(E1) is E1-N / 16.

[0014] In this embodiment, the rate matching rule used when f(E1) is E1-N / 16, i.e., the rate matching rule used when a=1 and b=-N / 16, is described.

[0015] In one possible embodiment, when E2 is greater than or equal to f(E1), the second rate matching includes bit reversal shortening on the fifth bit sequence followed by puncturing in natural order, or If E2 is less than f(E1), The third rate matching is bit-reversal shortening, f(E1) is E1 / 2.

[0016] In this possible implementation, the rate matching rule used when f(E1) is E1 / 2, ie, when a=1 / 2 and b=0, is described.

[0017] In one possible embodiment, N is determined based on E1. Specifically,

number

[0018] In one possible implementation, the first rate matching is bit-reversal shortening.

[0019] In some embodiments, the rate matching scheme is designed as bit-reversal shortening. In bit-reversal shortening, shortening positions are evenly distributed, so that the reliability order between bit positions is well maintained. Therefore, stable performance is achieved in scenarios with various code lengths and code rates.

[0020] According to a second aspect of the present application, there is provided a rate matching method, which includes:

[0021] The method includes the steps of: a receiver obtaining a first sequence, the length of the first sequence being E1 and the mother code length corresponding to the first sequence being N; a receiver rate-dematching the first sequence based on a first rate-matching scheme and then decoding the rate-dematched first sequence; a receiver obtaining a second sequence, the length of the second sequence being E2; a receiver rate-dematching a third sequence based on the first rate-matching scheme and a second rate-matching scheme and then decoding the rate-dematched third sequence, the third sequence consisting of the first sequence and the second sequence and the mother code length corresponding to the third sequence being 2*N; wherein the second rate-matching is determined based on a relationship between f(E1) and E2, the value of f(E1) being determined based on E1, and N, E1, and E2 are positive integers.

[0022] Correspondingly, a second aspect relates to a rate matching mechanism that can be applied to the receiver side of IR-HARQ, where a first sequence corresponds to a second bit sequence, i.e., an initial transmission bit sequence, of the transmitter, and a second sequence corresponds to a fourth bit sequence, i.e., a retransmission bit sequence, of the transmitter, to fill the gap in the prior art in that there is no rate matching method for IR-HARQ. Furthermore, the rate matching method designed for the retransmission bit sequence is determined based on the relationship between the initial transmission bit sequence and the retransmission bit sequence, and a flexible rate matching method is designed for different correspondence relationships between different numbers of retransmission bits and different numbers of initial transmission bits, so that the rate matching can accurately adapt to actual situations and ensure that the performance of IR-HARQ is always stable and excellent.

[0023] In one possible embodiment, f(E1)=a*E1+b, where a is a constant greater than 0 and less than or equal to 1, and b is a constant with an absolute value less than E1.

[0024] In one possible embodiment, f(E1)=a*E1+b, where a and b are constants, and f(E1) is less than or equal to E1.

[0025] In one possible implementation, if E2 is greater than or equal to f(E1), the second rate matching is performed based on the fifth bit sequence, or if E2 is less than f(E1), the second rate matching includes puncturing all bits in the fifth bit sequence whose sequence numbers fall within [0, N / 2-1] and performing third rate matching on all bits in the fifth bit sequence whose sequence numbers fall within [N / 2, N-1], wherein the fifth bit sequence consists of all bits in the third bit sequence whose sequence numbers fall within [0, N-1].

[0026] In this embodiment, the fifth bit sequence is the first half of the third bit sequence, i.e., the fifth bit sequence consists of all bits whose sequence numbers fall within [0,N-1] in the third bit sequence. If E2 is equal to or greater than f(E1), the second rate matching is performed based on the mother code length N. If E2 is less than f(E1), the second rate matching is performed based on half the mother code length, i.e., N / 2.

[0027] In one possible embodiment, when E2 is greater than or equal to f(E1): If E2 is less than N, the second rate matching is bit-reversal shortening, or if E2 is greater than N, the second rate matching is repetition, or If E2 is less than f(E1): If E2 is less than N / 2, the third rate matching is bit reversal shortening, or if E2 is greater than N / 2, the third rate matching is repetition; f(E1) is E1-N / 16.

[0028] In this possible implementation, the rate matching rule used when f(E1) is E1-N / 16, i.e., the rate matching rule used when a=1 and b=-N / 16, is described.

[0029] In one possible embodiment, when E2 is greater than or equal to f(E1), the second rate matching includes bit reversal shortening on the fifth bit sequence followed by puncturing in natural order, or If E2 is less than f(E1), The third rate matching is bit-reversal shortening, f(E1) is E1 / 2.

[0030] In this possible implementation, the rate matching rule used when f(E1) is E1 / 2, ie, when a=1 / 2 and b=0, is described.

[0031] In one possible embodiment, N is determined based on E1. Specifically,

number

[0032] In one possible implementation, the first rate matching is bit-reversal shortening.

[0033] In some embodiments, the rate matching scheme can be designed as bit-reversal shortening. In bit-reversal shortening, shortening positions are evenly distributed, so that the reliability order between bit positions is well maintained. Therefore, stable performance is achieved in scenarios with various code lengths and code rates.

[0034] According to a third aspect of the present application, there is provided a rate matching apparatus for use in a transmitter, the apparatus including a transceiver unit and a processing unit. The transceiver unit obtains a bit sequence to be encoded, the processing unit performs polar encoding on the bit sequence to be encoded to obtain a first bit sequence, the first bit sequence having a length N, the processing unit performs first rate matching on the first bit sequence to obtain a second bit sequence, the second bit sequence having a length E1, the transceiver unit transmits the second bit sequence, the processing unit performs polar encoding based on the bit sequence to be encoded to obtain a third bit sequence, the third bit sequence having a length 2*N, the processing unit performs second rate matching on the third bit sequence to obtain a fourth bit sequence, the fourth bit sequence having a length E2, the second rate matching is determined based on a relationship between f(E1) and E2, the value of f(E1) is determined based on E1, and the transceiver unit transmits the fourth bit sequence, N, E1, and E2 are positive integers.

[0035] In one possible embodiment, f(E1)=a*E1+b, where a is a constant greater than 0 and less than or equal to 1, and b is a constant with an absolute value less than E1.

[0036] In one possible embodiment, f(E1)=a*E1+b, where a and b are constants, and f(E1) is less than or equal to E1.

[0037] In one possible implementation, if E2 is greater than or equal to f(E1), the second rate matching is performed based on the fifth bit sequence, or if E2 is less than f(E1), the second rate matching includes puncturing all bits in the fifth bit sequence whose sequence numbers fall within [0, N / 2-1] and performing third rate matching on all bits in the fifth bit sequence whose sequence numbers fall within [N / 2, N-1], wherein the fifth bit sequence consists of all bits in the third bit sequence whose sequence numbers fall within [0, N-1].

[0038] In this embodiment, the fifth bit sequence is the first half of the third bit sequence, i.e., the fifth bit sequence consists of all bits whose sequence numbers fall within [0,N-1] in the third bit sequence. If E2 is equal to or greater than f(E1), the second rate matching is performed based on the mother code length N. If E2 is less than f(E1), the second rate matching is performed based on half the mother code length, i.e., N / 2.

[0039] In one possible embodiment, when E2 is greater than or equal to f(E1): If E2 is less than N, the second rate matching is bit-reversal shortening, or if E2 is greater than N, the second rate matching is repetition, or If E2 is less than f(E1): If E2 is less than N / 2, the third rate matching is bit reversal shortening, or if E2 is greater than N / 2, the third rate matching is repetition; f(E1) is E1-N / 16.

[0040] In this embodiment, the rate matching rule used when f(E1) is E1-N / 16, i.e., the rate matching rule used when a=1 and b=-N / 16, is described.

[0041] In one possible embodiment, when E2 is greater than or equal to f(E1), the second rate matching includes bit reversal shortening on the fifth bit sequence followed by puncturing in natural order, or If E2 is less than f(E1), The third rate matching is bit-reversal shortening, f(E1) is E1 / 2.

[0042] In this possible implementation, the rate matching rule used when f(E1) is E1 / 2, ie, when a=1 / 2 and b=0, is described.

[0043] In one possible embodiment, N is determined based on E1. Specifically,

number

[0044] In one possible implementation, the first rate matching is bit-reversal shortening.

[0045] According to a fourth aspect of the present application, there is provided a rate matching apparatus for use in a receiver, the apparatus including a transceiver unit and a processing unit. The transceiver unit obtains a first sequence, the length of which is E1, and the mother code length corresponding to the first sequence is N; the processing unit rate-dematches the first sequence based on a first rate-matching scheme and then decodes the rate-dematched first sequence; the transceiver unit obtains a second sequence, the length of which is E2; the processing unit rate-dematches a third sequence based on the first rate-matching scheme and a second rate-matching scheme and then decodes the rate-dematched third sequence, the third sequence consisting of the first sequence and the second sequence, and the mother code length corresponding to the third sequence is 2*N; the second rate-matching is determined based on a relationship between f(E1) and E2, the value of f(E1) is determined based on E1, and N, E1, and E2 are positive integers.

[0046] In one possible embodiment, f(E1)=a*E1+b, where a is a constant greater than 0 and less than or equal to 1, and b i is a constant whose absolute value is less than E1.

[0047] In one possible embodiment, f(E1)=a*E1+b, where a and b are constants, and f(E1) is less than or equal to E1.

[0048] In one possible implementation, if E2 is greater than or equal to f(E1), the second rate matching is performed based on the fifth bit sequence, or if E2 is less than f(E1), the second rate matching includes puncturing all bits in the fifth bit sequence whose sequence numbers fall within [0, N / 2-1] and performing third rate matching on all bits in the fifth bit sequence whose sequence numbers fall within [N / 2, N-1], wherein the fifth bit sequence consists of all bits in the third bit sequence whose sequence numbers fall within [0, N-1].

[0049] In this embodiment, the fifth bit sequence is the first half of the third bit sequence, i.e., the fifth bit sequence consists of all bits whose sequence numbers fall within [0,N-1] in the third bit sequence. If E2 is equal to or greater than f(E1), the second rate matching is performed based on the mother code length N. If E2 is less than f(E1), the second rate matching is performed based on half the mother code length, i.e., N / 2.

[0050] In one possible embodiment, when E2 is greater than or equal to f(E1): If E2 is less than N, the second rate matching is bit-reversal shortening, or if E2 is greater than N, the second rate matching is repetition, or If E2 is less than f(E1): If E2 is less than N / 2, the third rate matching is bit reversal shortening, or if E2 is greater than N / 2, the third rate matching is repetition; f(E1) is E1-N / 16.

[0051] In this possible implementation, the rate matching rule used when f(E1) is E1-N / 16, i.e., the rate matching rule used when a=1 and b=-N / 16, is described.

[0052] In one possible embodiment, when E2 is greater than or equal to f(E1), the second rate matching includes bit reversal shortening on the fifth bit sequence followed by puncturing in natural order, or If E2 is less than f(E1), The third rate matching is bit-reversal shortening, f(E1) is E1 / 2.

[0053] In this possible implementation, the rate matching rule used when f(E1) is E1 / 2, ie, when a=1 / 2 and b=0, is described.

[0054] In one possible embodiment, N is determined based on E1. Specifically,

number

[0055] In one possible implementation, the first rate matching is bit-reversal shortening.

[0056] According to a fifth aspect of an embodiment of the present application, there is provided a communication device, the communication device including a processor and a memory, the memory storing a computer program, the processor being configured to invoke and execute the computer program stored in the memory to enable the processor to implement any implementation of the first aspect.

[0057] According to a sixth aspect of an embodiment of the present application, there is provided a communication device, the communication device including a processor and a memory, the memory storing a computer program, the processor being configured to invoke and execute the computer program stored in the memory to enable the processor to implement any implementation of the second aspect.

[0058] According to a seventh aspect of an embodiment of the present application, there is provided a communication device, the communication device including a logic circuit and an input / output interface.

[0059] The input / output interface is configured to input a bit sequence to be encoded, the input / output interface is further configured to output a second bit sequence and a fourth bit sequence, and the logic circuit is configured to implement any implementation of the first aspect.

[0060] According to an eighth aspect of an embodiment of the present application, there is provided a communication device, the communication device including a logic circuit and an input / output interface.

[0061] The input / output interface is configured to input the first sequence and the second sequence, and the logic circuit is configured to perform any implementation of the first aspect.

[0062] According to a ninth aspect of an embodiment of the present application, there is provided a computer program product comprising instructions, which, when executed on a computer, perform any of the first and second aspects.

[0063] According to a tenth aspect of the present application, there is provided a computer-readable storage medium, the computer-readable storage medium including computer instructions, which, when executed on a computer, perform any of the first and second aspects.

[0064] According to an eleventh aspect of an embodiment of the present application, there is provided a chip device, the chip device including a processor coupled to a memory and configured to invoke a program stored in the memory to enable the processor to perform any implementation of the first aspect and the second aspect.

[0065] According to a twelfth aspect of the present application, there is provided a communication system, the communication system including an apparatus according to the third aspect and an apparatus according to the fourth aspect.

[0066] For technical effects that can be achieved in the third to twelfth aspects, please refer to the technical effects in the first or second aspect, and details will not be described here. [Brief explanation of the drawings]

[0067] [Figure 1] 1 is a schematic diagram of a communication system according to an embodiment of the present application; [Figure 2] FIG. 1 is a schematic diagram of encoding and decoding of a polar code according to an embodiment of the present application; [Figure 3] FIG. 1 is a schematic diagram of IF-HARQ according to an embodiment of the present application; [Figure 4] 1 is a schematic diagram of IR-HARQ according to an embodiment of the present application; [Figure 5] 1 is a schematic flowchart of a rate matching method according to an embodiment of the present application; [Figure 6] FIG. 1 is a schematic operation diagram of a rate matching method designed based on an IR-HARQ structure according to an embodiment of the present application; [Figure 7] FIG. 1 is a schematic diagram of an example of bit-reversal shortening according to an embodiment of the present application; [Figure 8] FIG. 1 is a schematic diagram of rate matching corresponding to the case where f(E1) is expressed as E1-N / 16 according to an embodiment of the present application. [Figure 9] FIG. 1 is a schematic diagram of rate matching corresponding to the case where f(E1) is expressed as E1 / 2 according to an embodiment of the present application. [Figure 10] 1 is a schematic diagram of a rate matching device according to an embodiment of the present application; [Figure 11] FIG. 10 is a schematic diagram of another rate matching device according to an embodiment of the present application; [Figure 12] FIG. 10 is a schematic diagram of another rate matching device according to an embodiment of the present application; [Figure 13] FIG. 1 is a performance simulation diagram according to an embodiment of the present application. [Figure 14A] FIG. 10 is another performance simulation diagram according to an embodiment of the present application. [Figure 14B] FIG. 10 is another performance simulation diagram according to an embodiment of the present application. [Figure 14C] FIG. 10 is another performance simulation diagram according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0068] The present application provides a rate matching method and a rate matching device that ensures stable performance of IR-HARQ.

[0069] In the specification and accompanying drawings of this application, terms such as “first,” “second,” etc. are used to distinguish between different objects or between different processes of the same object, and are not used to describe a particular order of the objects. Furthermore, the terms “include” and “have,” as well as any variations thereof, in the description of this application are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, and may optionally further include other unlisted steps or units, or may optionally further include other steps or units inherent to the process, method, product, or device. In the embodiments of this application, “multiple” includes two or more, and “system” and “network” are interchangeable. In the embodiments of this application, words such as “example” and “for example” are used to denote providing an example, illustration, or explanation. Any embodiment or design solution described as an “example” or “for example” in the embodiments of this application should not be described as preferred or having more advantages than another embodiment or design solution. Specifically, the use of words such as "example" or "for example" is intended to concretely present the relevant concept.

[0070] The communication method provided in the embodiments of the present application is applicable to various communication systems, such as a satellite communication system, an internet of things (IoT) narrow band internet of things (NB-IoT) system, a global system for mobile communications (GSM), an enhanced data rate for GSM evolution (EDGE) system, a wideband code division multiple access (WCDMA) system, a code division multiple access 2000 (CDMA2000) system, a time division-synchronization code division multiple access (TD-SCDMA) system, a long term evolution (LTE) system, a fifth generation (5G) communication system, such as 5G new radio (NR) and three scenarios of a 5G mobile communication system, namely enhanced mobile broadband (EMB). The present application may be applied to a broadband (eMBB), an ultra-reliable low latency communications (uRLLC), and a massive machine type communications (mMTC), a device-to-device (D2D) communication system, a machine-to-machine (M2M) communication system, a vehicular internet communication system, or another communication system or a future communication system, which is not particularly limited in the embodiments of the present application.

[0071] The following describes the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. The terms used in the embodiments of the present application are only used to describe specific embodiments of the present application, and are not intended to limit the present application.

[0072] To facilitate understanding of the embodiments of the present application, an application scenario used in the embodiments of the present application will be described by using the network architecture shown in FIG. 1. This network architecture may be used in the various communication systems described above. The communication system shown in FIG. 1 includes a network device and a terminal. In the present application, both the transmitter and the receiver may be network devices or terminals. This is not a limitation in the present application. The network device and the terminal may perform wireless communication by using resources. In the embodiments of the present application, the types and numbers of network devices and terminal devices are not limited. As shown in FIG. 1(a), there may be one or more terminal devices. As shown in FIG. 1(b), there may be one or more network devices. The resources here may include one or more of time domain resources, frequency domain resources, code domain resources, and spatial domain resources. In addition, the present application is applicable to a system in which terminals communicate with each other and a system in which network devices communicate with each other.

[0073] A terminal is a device that provides a voice and / or data connection to a user. Specifically, a terminal includes a device that provides a voice connection to a user, a device that provides a data connection to a user, or a device that provides a voice and data connection to a user. For example, a terminal may include a handheld device with wireless connectivity or a processing device connected to a wireless modem. A terminal device communicates with a core network via a radio access network (RAN) and may exchange voice or data with the RAN, or exchange voice and data with the RAN. A terminal device may include a user equipment (UE), a wireless terminal device, a mobile terminal device, a device-to-device (D2D) terminal device, a vehicle-to-everything (V2X) terminal device, a machine-to-machine / machine-type communications (M2M / MTC) terminal device, an internet of things (IoT) terminal device, a light terminal device (light UE), a subscriber unit, a subscriber station, a mobile station, a remote station, an access point (AP), a remote terminal, an access terminal, a user terminal, a user agent, a user device, etc. For example, a terminal device may include a mobile phone (also called a "cellular" phone), a computer with a mobile terminal device, or a portable, pocket-sized, handheld, or computer-embedded mobile device.For example, a terminal device may be a device such as a personal communication service (PCS) telephone, a cordless telephone, a session initiation protocol (SIP) telephone, a wireless local loop (WLL) station, or a personal digital assistant (PDA). Terminal devices also include limited devices, such as devices with low power consumption, limited storage capabilities, or limited computing capabilities. For example, terminal devices include information sensing devices such as barcodes, radio frequency identification (RFID), sensors, global positioning systems (GPS), or laser scanners.

[0074] By way of example and not limitation, in the embodiments of the present application, the terminal may alternatively be a wearable device. A wearable device, also referred to as a wearable intelligent device or an intelligent wearable device, is a collective term for wearable devices, such as glasses, gloves, watches, clothes, and shoes, that are intelligently designed and developed for everyday wear using wearable technology. A wearable device is a portable device that is worn directly on the body or integrated into a user's clothing or accessories. A wearable device is not simply a hardware device, but is used to implement powerful functions through software support, data exchange, and cloud interaction. In a broad sense, wearable intelligent devices include, for example, fully-featured large devices, such as smart watches and smart glasses, that can perform all or part of their functions independently of a smartphone, as well as devices such as various smart bands, smart helmets, or smart jewelry for monitoring physical signs, which provide only one type of application function and must be used in combination with another device, such as a smartphone.

[0075] When the various terminals described above are located in a vehicle (e.g., arranged or installed in a vehicle), all the terminals may be considered as in-vehicle terminals. For example, an in-vehicle terminal device may also be referred to as an on-board unit (OBU).

[0076] In the embodiment of the present application, the terminal may further include a relay. Alternatively, it is understood that any device capable of performing data communication with a base station may be considered as a terminal device.

[0077] In the embodiments of the present application, the device configured to perform the functions of the terminal may be a terminal, or may be a device capable of supporting a terminal device in performing the functions, such as a chip system. The device may be installed in a terminal. In the embodiments of the present application, the chip system may include a chip, or may include a chip and another discrete device. In the technical solutions provided in the embodiments of the present application, the technical solutions provided in the embodiments of the present application will be described by using an example in which the device configured to perform the functions of the terminal is a terminal device.

[0078] The network device may include, for example, an access network (AN) device, such as a base station (e.g., an access point), that communicates with wireless terminal devices over an air interface within one or more cells in the access network. Alternatively, the network device may be, for example, a road side unit (RSU) in vehicle-to-everything (V2X) technology. The base station may be configured to convert received radio frames to and from IP packets to function as a router between the terminal device and the rest of the access network. The rest of the access network may include an IP network. The RSU may be a fixed infrastructure entity supporting V2X applications or may exchange messages with another entity supporting V2X applications. The network device may further coordinate attribute management of the air interface. For example, the network device may include an evolved Node B (eNB or e-Node B, evolutionary Node B) in a long term evolution (LTE) system or a long term evolution-advanced (LTE-A), a next generation Node B (gNB) in a 5th generation (5G) NR system (abbreviated as NR system), a centralized unit (CU) and a distributed unit (DU) in a cloud radio access network (Cloud RAN) system, or an apparatus having the function of a network device in a future communication system. This is not limited to the embodiments of the present application.

[0079] The network device may further include a core network device, for example, an access and mobility management function (AMF) or a user plane function (UPF).

[0080] Alternatively, the network device may be a device having the functionality of a network device in Device to Device (D2D) communication, Machine to Machine (M2M) communication, Internet of Vehicles, unmanned aerial systems, or satellite communication systems.

[0081] It should be noted that the above only lists some communication methods between network elements. Other network elements may communicate with each other through some connection methods. Details in the embodiments of the present application will not be described here.

[0082] The system architectures and service scenarios described in the embodiments of the present application are intended to more clearly explain the technical solutions in the embodiments of the present application, and do not constitute limitations on the technical solutions provided in the embodiments of the present application. Those skilled in the art will know that with the evolution of network architectures and the emergence of new service scenarios, the technical solutions provided in the embodiments of the present application can also be applied to similar technical problems.

[0083] To facilitate understanding of the embodiments of the present application, the following explains and describes some terms in the embodiments of the present application to facilitate understanding by those skilled in the art.

[0084] 1.Polar code Polar codes are linear block codes. The generator matrix for Polar codes is G N The encoding process of the polar code is

number

number

number

number

number

number

number

number

number

[0085] In addition to the generator matrix representation, polar codes may also be represented using encoding / decoding diagrams. Figure 2 shows the encoding / decoding diagram for a polar code with code length N=8 and information length K=4. Each "butterfly plot" represents one polarization of two bits, i.e.

number

[0086] 2. Hybrid automatic repeat request (HARQ). In communication applications that are not sensitive to system latency, HARQ is a common transmission method used to improve system throughput rates. When transmitting an information block, the transmitter encodes the information block and then transmits the information block over a channel. If the receiver decodes the received signal and finds that the transmission has failed (e.g., the cyclic redundancy check fails), the receiver sends a negative acknowledgment (NACK) message to the transmitter via a feedback link, and the transmitter retransmits the information block. This process continues until the receiver successfully decodes the information block. In this case, the receiver sends an acknowledgment (ACK) message to the transmitter to complete the transmission of the information block. To obtain the highest possible link throughput rate, the receiver buffers all received signals and decodes them together with the new received signals.

[0087] 3. Chase combining hybrid automatic repeat request (CC-HARQ) The classical HARQ solution 1 is CC-HARQ, i.e., HARQ-I (HARQ-I). In this solution, the transmitter transmits the same coded data every time a retransmission is performed, and the receiver directly adds all received signals and then performs decoding. As the number of retransmissions increases, the energy of the combined received signal gradually increases, and the decoding performance is enhanced. However, in this method, only the energy gain of retransmission can be obtained, and there is no coding gain of retransmission.

[0088] 4. Incremental freezing hybrid automatic repeat request (IF-HARQ) The existing HARQ transmission method in the polar code field is called IF-HARQ. As shown in Figure 3, during each retransmission, the transmitter selects some information bits with the lowest reliability from the sequence number set of the previous transmission based on the reliability of each polar channel calculated by methods such as density evolution / Gaussian approximation or by using the nested reliability sequence when the polar code is constructed, and then polar-encodes and transmits them again. The receiver performs successive cancellation decoding based on the received signal, i.e., first decodes the last received information data and applies the decoding results to the previous received data as frozen bits until the first received data is successfully decoded. This solution can bring about coding gain by re-encoding.

[0089] As the number of retransmissions increases, the code rate gradually decreases, and the coding gain of IF-HARQ also decreases. At very low code rates, the coding gain may even be negative (lower than that of CC-HARQ). Furthermore, if the codewords of the retransmissions are incorrectly decoded due to the channel environment, and these erroneous information bits are used as freezing bits for the initial transmission, the decoding of the initial transmission may be adversely affected.

[0090] From another perspective, in IF-HARQ, a short code is transmitted for each transmission. If strong noise or interference is received during transmission, correct decoding cannot be performed, resulting in erroneous propagation. That is, a lack of coupling occurs between codeword bits, and the reliability of the currently decoded subblock cannot be strengthened by decoding adjacent codewords, and the gain brought by increasing the code length cannot be obtained. This causes a loss of coding gain. Therefore, simply using IF-HARQ in a retransmission solution for polar codes is not appropriate.

[0091] 5. Incremental redundancy hybrid automatic repeat request (IR-HARQ) Another type of HARQ in the polar code field is called IR-HARQ, which is usually classified as HARQ-II (HARQ-II). The basic idea of ​​this solution is to combine the initial transmission codeword and the retransmission codeword into a long code for decoding by using the nesting feature of polar codes. During the initial transmission, the transmitter performs CRC encoding on the information data and encodes the information data into a short polar codeword with the corresponding code rate. During each retransmission, the polar code length and kernel are extended based on the retransmission length, the extended part is searched for a subchannel whose reliability is higher than that of the initial transmission part, the subchannel is used as a new information bit, the unreliable information bit in the corresponding initial transmission part is converted into a redundant information bit, the value of the redundant information bit is assigned to the new information bit, a "one-to-one" check relationship between the redundant information bit and the new information bit is established, and polar encoding is performed to generate incremental redundant bits. The receiver combines all received signals into a long codeword based on the encoder structure and then sends the codeword to the decoder for decoding. During decoding, the redundant information bits are used as check bits, so that the value of the check bits can be determined based on the decoding result of the new information bits. As the number of retransmissions increases, the number of received redundant bits gradually increases, and the code rate of the long code obtained after combining gradually decreases. Therefore, the decoding performance is enhanced. In addition to the energy gain, this method can also bring additional coding gain by increasing the redundant bits.

[0092] The encoding process of information bits and codeword bits for the first transmission and the second transmission in IR-HARQ may be expressed by using the following equations:

number

[0093] where for the first transmission, the information side vector is denoted as u1 (including information bits and frozen bits) and the codeword bit vector is c1, and for the second transmission, the information side vector is denoted as u2 (including information bits and frozen bits, the transmitted information bits are exactly the same as some of the information bits in u1, hence the operation is called "copy") and the codeword bit vector is c2+c1, where "+" is binary addition, i.e., exclusive OR operation.

[0094] However, since IR-HARQ does not perform rate matching, IR-HARQ does not have stable performance and may have defects due to defective pixels (the performance of IR-HARQ is inferior to that of CC-HARQ).

[0095] From the above description, it can be seen that CC-HARQ and IF-HARQ have drawbacks. When CC-HARQ and IF-HARQ are directly applied to polar code fields, the performance is not sufficiently ideal. IR-HARQ is a well-known, efficient retransmission scheme, but currently, there is no rate matching method for IR-HARQ. In IR-HARQ, when rate matching is not required (i.e., puncturing or shortening is not required), stable performance can be achieved by selecting the number and position of bits to be copied based on the reliability sequence. However, in a practical system, the number of resources for initial transmission and the number of resources for retransmission are not necessarily equal, and the number of bits obtained after encoding for retransmission is less than the number of bits obtained after encoding for initial transmission. In this case, a rate matching scheme needs to be introduced and designed to achieve stable performance. Otherwise, performance will be impaired due to defective pixels due to unexpected copy numbers and unexpected copy positions based on long sequences.

[0096] Considering this, in the technical solution of this application, a corresponding rate matching scheme is designed for IR-HARQ to ensure the stability of retransmission.

[0097] Below, the technical solutions of the present application are described with reference to specific embodiments.

[0098] Figure 5 is a schematic flow chart of a rate matching method according to an embodiment of the present application. Figure 6 is a schematic operation diagram of a corresponding rate matching method designed based on the IR-HARQ structure.

[0099] S501: A transmitter obtains a bit sequence to be encoded.

[0100] S502: The transmitter performs polar encoding on the bit sequence to be encoded to obtain a first bit sequence.

[0101] Note that the first bit sequence may be referred to as the mother code of the initial transmission bit sequence, and the length of the first bit sequence is N.

[0102] S503: The transmitter performs first rate matching on the first bit sequence to obtain a second bit sequence.

[0103] It should be noted that the second bit sequence may be referred to as the initial transmission bit sequence, and the length of the second bit sequence is E1, ie, the number of initial transmission bits is E1.

[0104] In one possible implementation, the first rate matching may be a bit-reversal shortening or bit-reversal shortening based rate matching method, or may be an existing rate matching method in an existing standard.

[0105] For ease of understanding, Figure 7 is used as an example in this specification to explain bit-reversal shortening. As shown in Figure 7, the mother code length is 16 bits. If the encoding length is set to 12 bits, four bit positions need to be shortened. The sequence number of each bit position is expressed as a sequence number within [1, 15]. In this case, the four bit positions with the highest sequence numbers are the bit positions corresponding to sequence numbers 12, 13, 14, and 15, respectively, i.e., the four bit positions with the lowest reliability rankings, and the corresponding binary representations of the bit positions are [12 (1100), 13 (1101), 14 (1110), 15 (1111)]. The binary representations of the four bits can be reversed to obtain [3 (0011), 11 (1011), 7 (0111), 15 (1111)]. That is, after the bit-reversal operation is performed, the positions that need to be finally shortened are the bit positions corresponding to sequence numbers 3, 11, 7, and 15. We can see that the shortened positions of the sequences obtained after bit-reversal shortening are evenly distributed, and the reliability order among bit positions is well preserved. Therefore, stable performance is achieved in scenarios with various code lengths and rates.

[0106] In addition to using the bit-reversal shortening rate matching method for the first bit sequence, the rate matching scheme specified in the existing new radio (NR) protocol may also be used. Specifically, the polar code is equally divided into 32 groups, each with N / 32 bits, and the positions to be punctured or shortened are selected for each group, i.e., based on the priority of the designated sequence. If the number of remaining bits to be punctured or shortened is insufficient to form one group, the remaining bits to be punctured or shortened are selected sequentially from the group. The positions to be shortened are selected symmetrically to the positions to be punctured, i.e., from back to front.

[0107] S504: The transmitter transmits a second bit sequence to the receiver.

[0108] Correspondingly, there is S504a: The receiver obtains the first sequence.

[0109] Note that the first sequence received by the receiver is related to the second bit sequence sent by the transmitter, and the length of the first sequence is E1.

[0110] S504b: The receiver rate-dematches the first sequence based on a first rate-matching scheme, and then decodes the rate-dematched first sequence.

[0111] It should be noted that the operation of the receiver corresponds to that of the transmitter. The difference is that the transmitter performs encoding and the receiver performs decoding. Therefore, the decoding method of the receiver is also based on the first rate matching, and the details will not be described here.

[0112] S505: The transmitter performs polar encoding on the bit sequence to be encoded to obtain a third bit sequence.

[0113] It should be noted that the third bit sequence in this specification may be referred to as a combination of the bit sequence to be retransmitted and the first bit sequence, and the length of the third bit sequence is 2*N, i.e., twice the length of the initial transmission mother code.

[0114] S506: The transmitter performs second rate matching on the third bit sequence to obtain a fourth bit sequence.

[0115] The fourth bit sequence may be referred to as a retransmission bit sequence, and it should be noted that the length of the fourth bit sequence is E2. The second rate matching is determined based on the relationship between f(E1) and E2, and the value of f(E1) is determined based on E1.

[0116] S507: The transmitter sends the fourth bit sequence to the receiver.

[0117] Correspondingly, there is S507a: The receiver obtains the second sequence.

[0118] Note that the second sequence received by the receiver is related to the fourth bit sequence sent by the transmitter, and the length of the second sequence is E2.

[0119] S507b: The receiver rate de-matches the third sequence based on the first rate matching scheme and the second rate matching scheme, and then decodes the de-matched third sequence, where the third sequence consists of the first sequence and the second sequence.

[0120] It should be noted that the operation of the receiver corresponds to that of the transmitter. The difference is that the transmitter performs encoding and the receiver performs decoding. Therefore, the decoding method of the receiver is also performed based on the first rate matching and the second rate matching method. Details will not be described here.

[0121] In the above method, a rate matching mechanism that can be applied to the transmitter side in IR-HARQ is designed, and a rate matching method is designed for each of the initial transmission bit sequence and the retransmission bit sequence to fill the gap in the prior art that there is no rate matching method for IR-HARQ. Furthermore, the rate matching method designed for the retransmission bit sequence is determined based on the relationship between the initial transmission bit sequence and the retransmission bit sequence, and a flexible rate matching method is designed for different correspondence relationships between different numbers of retransmission bits and different numbers of initial transmission bits, so that the rate matching can accurately respond to actual situations and ensure that the performance of IR-HARQ is always stable and excellent.

[0122] In one possible implementation, the second rate matching being determined based on the relationship between E1 and E2 can be specifically reflected as the second rate matching being determined based on the relationship between f(E1) and E2, where f(E1) is a function of E1.

[0123] In one possible implementation, the second rate matching is determined based on the relationship between f(E1,R) and E2, where f(E1,R) is a function of E1 and R, R=K / E1 is the transmission code rate, K is the number of bits to be coded, and K is a positive integer.

[0124] In one possible implementation, f(E1) may be expressed as a*E1+b, where a is a constant greater than 0 and less than or equal to 1, and b is a constant whose absolute value is less than E1.

[0125] In one possible implementation, if E2 is greater than or equal to f(E1), the second rate matching is performed based on the fifth bit sequence; or If E2 is less than f(E1), the second rate matching includes puncturing all bits in the fifth bit sequence whose sequence numbers fall within [0, N / 2-1], and performing third rate matching on all bits in the fifth bit sequence whose sequence numbers fall within [N / 2, N-1].

[0126] In this embodiment, the fifth bit sequence is the first half of the third bit sequence, i.e., the fifth bit sequence consists of all bits whose sequence numbers fall within [0,N-1] in the third bit sequence. If E2 is equal to or greater than f(E1), the second rate matching is performed based on the mother code length N. If E2 is less than f(E1), the second rate matching is performed based on half the mother code length, i.e., N / 2.

[0127] In one possible embodiment, f(E1) is expressed as E1-N / 16. The specific retransmission rate matching rule in this embodiment is as follows:

[0128] If E2 is greater than or equal to E1-N / 16:

[0129] (1) If E2 is less than N, the second rate matching is bit reversal shortening, i.e., the transmitter performs bit reversal shortening on the bit sequence to be retransmitted until the length of the retransmitted bit sequence finally transmitted is E2.

[0130] (2) If E2 is greater than or equal to N, the second rate matching is iterative, i.e., the transmitter performs an iterative operation on the bit sequence to be retransmitted until the length of the retransmission bit sequence finally transmitted is E2.

[0131] If E2 is less than E1-N / 16:

[0132] (1) If E2 is less than N / 2, the third rate matching is bit reversal shortening, i.e., the transmitter performs bit reversal shortening on the bit sequence to be retransmitted until the length of the retransmission bit sequence finally transmitted is E2.

[0133] (2) If E2 is less than N / 2, the third rate matching is iterative, i.e., the transmitter performs iterative operations on the bit sequence to be retransmitted until the length of the retransmission bit sequence finally transmitted is E2.

[0134] For ease of understanding, FIG. 8 is used as an example in this specification for further explanation. Assume that the length E1 of the initial transmission bit sequence is 14 bits, and the mother code length N corresponding to the initial transmission bit sequence is 16 bits. Therefore, two bit positions need to be shortened. Based on bit-reversal shortening, the sequence number of each bit position is expressed as a sequence number within [1, 15]. In this case, the two bit positions with the largest sequence numbers are the bit positions corresponding to sequence numbers 14 and 15, respectively, and the corresponding binary representations of the bit positions are [14 (1110), 15 (1111)]. The binary representations of four bits can be reversed to obtain [7 (0111), 15 (1111)]. That is, after the bit-reversal operation, the positions that ultimately need to be shortened are the bit positions corresponding to sequence numbers 7 and 15. In FIG. 8, the initial transmission bit sequence and the retransmission bit sequence are combined into a long code. Therefore, the mother code length N is added to all bit positions in the initial transmission bit sequence. In this case, the shortened bit positions are changed to the bit positions corresponding to sequence numbers 23 and 31.

[0135] After the initial transmission bit sequence is determined, rate matching for retransmission is performed as follows. Assume that the length E2 of the retransmission bit sequence is 13 bits. In this case, f(E1) = E1 - N / 16 = 12, and the condition that E2 is greater than or equal to E1 - N / 16 is met. Therefore, the rate matching method shown in Figure 8(a) is used. Furthermore, the condition that E2 is less than N is met. Therefore, the retransmission portion is shortened to 13 bits based on bit reversal. From the bit reversal shortening method described above, it can be seen that the shortened bit positions are [7 (0111), 11 (1011), 15 (1111)], i.e., the positions that ultimately need to be shortened are the bit positions corresponding to sequence numbers 7, 11, and 15. Assume that the length E2 of the retransmission bit sequence is 4 bits. In this case, the condition that E2 is less than E1 - N / 16 is met. Therefore, the rate matching method shown in Figure 8(b) is used. Furthermore, the condition that E2 is less than N / 2 is met. Therefore, the bit positions in the retransmission part where the sequence number falls in [0,7] are fixed puncture positions, and the remaining N / 2 bit positions, i.e., the bit positions where the sequence number falls in [8,15], are shortened to 4 bits according to the bit reversal shortening method. From the bit reversal shortening method described above, it can be seen that the bit positions that are finally shortened are the bit positions corresponding to sequence numbers 9, 11, 13, and 15.

[0136] The above is just one example where f(E1)=a*E1+b, i.e., where a is 1 and b is -N / 16. In other possible implementations, a may be any value greater than 0 and less than or equal to 1, such as 7 / 8, 5 / 6, or 3 / 4. Also, b may be any number whose absolute value is less than E1.

[0137] In one possible embodiment, f(E1) is expressed as E1 / 2. The specific retransmission rate matching rule in this embodiment is as follows:

[0138] (1) If E2 is equal to or greater than E1 / 2, The fifth bit sequence is subjected to bit reversal shortening and then punctured in natural order.

[0139] (2) If E2 is less than E1 / 2, The third rate matching is bit reversal shortening.

[0140] Note that if E2 is greater than or equal to E1 / 2, the transmitter performs bit reversal shortening on the to-be-retransmitted bit sequence to shorten it to a length of E1, and then punctures in natural order until the length of the final retransmitted bit sequence is E2; or if E2 is less than E1 / 2, the transmitter first punctures all bits whose sequence numbers fall within [0, N / 2-1], and then performs bit reversal shortening on the remaining N / 2 bits until the length of the final retransmitted bit sequence is E2.

[0141] For ease of understanding, Figure 9 is used as an example in this specification for further explanation. Assume that the length of the initial transmission bit sequence is 14 bits and the corresponding mother code length is 16 bits. Therefore, two bit positions need to be shortened. Based on bit-reversal shortening, the sequence number of each bit position is expressed as a sequence number within [1, 15]. In this case, the two bit positions with the largest sequence numbers are the bit positions corresponding to sequence numbers 14 and 15, respectively, and the corresponding binary representations of the bit positions are [14 (1110), 15 (1111)]. The binary representations of the four bits can be reversed to obtain [7 (0111), 15 (1111)]. That is, after the bit-reversal operation, the positions that need to be finally shortened are the bit positions corresponding to sequence numbers 7 and 15. In Figure 8, the initial transmission bit sequence and the retransmission bit sequence are combined into a long code. Therefore, the mother code length N is added to all bit positions in the initial transmission bit sequence. In this case, the shortened bit positions are changed to the bit positions corresponding to sequence numbers 23 and 31.

[0142] After the initial transmission bit sequence is determined, rate matching is performed for retransmission as follows. Assume that the length E2 of the retransmission bit sequence is 8 bits. In this case, f(E1) = E1 / 2 = 7, and the condition that E2 is greater than or equal to E1 / 2 is met. Therefore, the rate matching method shown on the left side of Figure 9 is used, i.e., bit reversal shortening is performed. From the above method, it can be seen that the bit positions that need to be shortened match the bit positions of the initial transmission. That is, according to the natural order puncturing method, the bit positions corresponding to sequence numbers 7 and 15 are shortened first, and then the retransmission portion is shortened to the required length E2 of the retransmission bit sequence. In this case, if a shortening position is touched when puncturing is performed in natural order, the shortening position is skipped. Assume that the length of the retransmission bit sequence is 4 bits. In this case, the condition that E2 is less than E1 / 2 is met. Therefore, the rate matching method shown on the right side of Figure 9 is used. That is, the bit positions in the retransmission part where the sequence number falls in [0,7] are fixed puncture positions, and in this case, the remaining N / 2 bit positions, i.e., the bit positions where the sequence number falls in [8,15], are shortened to 4 bits according to the bit reversal shortening method. From the bit reversal shortening method described above, it can be seen that the positions that are finally shortened are the bit positions corresponding to sequence numbers 9, 11, 13, and 15.

[0143] The rate matching rule used when f(E1) is expressed as E1 / 2 and the length E2 of the retransmission bit sequence is less than or equal to the length E1 of the initial transmission bit sequence is provided above. In another possible implementation, if the length E2 of the retransmission bit sequence is greater than the length E1 of the initial transmission bit sequence, the retransmission portion can be shortened to E2 based on the length N of the initial transmission mother code. If E2 is greater than N, rate matching is performed by using an iterative operation.

[0144] The above describes a method in an embodiment of the present application. The following describes an apparatus in an embodiment of the present application. The method and the apparatus are based on the same technical concept. The method and the apparatus have similar principles for solving problems. Therefore, cross-references may be made to the implementations of the apparatus and the method. Repetitive parts will not be described.

[0145] In the embodiments of the present application, the device may be divided into functional modules based on the above-mentioned method examples. For example, each functional module may be obtained by dividing it into corresponding functions, or two or more functions may be integrated into one processing module. The modules may be implemented in the form of hardware or software functional modules. It should be noted that in the embodiments of the present application, the division into modules is an example and is merely a logical division of functions. In specific implementations, other division methods may be used.

[0146] Based on the same technical concept as the above-mentioned method, Figure 10 is a schematic diagram of the structure of a rate matching device 1000. The device 1000 may be a transmitter or a chip or a functional unit used in a transmitter, or may be a receiver or a chip or a functional unit used in a receiver.

[0147] If the device 1000 is configured to perform the operations performed by a transmitter, then the device 1000 has any functionality of a transmitter in the methods described above.

[0148] In one possible implementation, the transceiver unit 1010 and the processing unit 1020 may be further configured to perform the following steps in the above-mentioned method.

[0149] The transceiver unit 1010 obtains a bit sequence to be encoded; The processing unit 1020 performs polar encoding on the bit sequence to be encoded to obtain a first bit sequence, where the first bit sequence has a length of N; The processing unit 1020 performs first rate matching on the first bit sequence to obtain a second bit sequence, where the second bit sequence has a length of E1, and the transceiver unit transmits the second bit sequence; The processing unit 1020 performs polar encoding based on the bit sequence to be encoded to obtain a third bit sequence, where the length of the third bit sequence is 2*N; The processing unit 1020 performs second rate matching on the third bit sequence to obtain a fourth bit sequence, where the fourth bit sequence has a length of E2; and The second rate matching is determined based on a relationship between f(E1) and E2, and the value of f(E1) is determined based on E1; The transceiver unit 1010 transmits a fourth bit sequence; N, E1, and E2 are positive integers.

[0150] In one possible embodiment, f(E1)=a*E1+b, where a is a constant greater than 0 and less than or equal to 1, and b is a constant with an absolute value less than E1.

[0151] In one possible implementation, if E2 is greater than or equal to f(E1), the second rate matching is performed based on the fifth bit sequence, or if E2 is less than f(E1), the second rate matching includes puncturing all bits in the fifth bit sequence whose sequence numbers fall within [0, N / 2-1] and performing third rate matching on all bits in the fifth bit sequence whose sequence numbers fall within [N / 2, N-1], wherein the fifth bit sequence consists of all bits in the third bit sequence whose sequence numbers fall within [0, N-1].

[0152] In this embodiment, the fifth bit sequence is the first half of the third bit sequence, i.e., the fifth bit sequence consists of all bits whose sequence numbers fall within [0,N-1] in the third bit sequence. If E2 is equal to or greater than f(E1), the second rate matching is performed based on the mother code length N. If E2 is less than f(E1), the second rate matching is performed based on half the mother code length, i.e., N / 2.

[0153] In one possible embodiment, when E2 is greater than or equal to f(E1): If E2 is less than N, the second rate matching is bit-reversal shortening, or if E2 is greater than N, the second rate matching is repetition, or If E2 is less than f(E1): If E2 is less than N / 2, the third rate matching is bit reversal shortening, or if E2 is greater than N / 2, the third rate matching is repetition; f(E1) is E1-N / 16.

[0154] In one possible embodiment, when E2 is greater than or equal to f(E1), the second rate matching includes bit reversal shortening on the fifth bit sequence followed by puncturing in natural order, or If E2 is less than f(E1), The third rate matching is bit-reversal shortening, f(E1) is E1 / 2.

[0155] In one possible embodiment, N is determined based on E1. Specifically,

number

[0156] In one possible implementation, the first rate matching is bit-reversal shortening.

[0157] If the apparatus 1000 is configured to perform the operations performed by a receiver, then the apparatus 1000 has any of the functions of the receiver in the methods described above.

[0158] In one possible implementation, the transceiver unit 1010 and the processing unit 1020 may be further configured to perform the following steps in the above-mentioned method.

[0159] The transceiver unit 1010 obtains a first sequence, where the length of the first sequence is E1 and the mother code length corresponding to the first sequence is N; the processing unit rate-dematches the first sequence based on a first rate-matching scheme, and then decodes the dematched first sequence; The transceiver unit 1010 obtains a second sequence, the second sequence having a length E2; The processing unit 1020 rate-dematches the third sequence based on the first rate-matching scheme and the second rate-matching scheme, and then decodes the rate-dematched third sequence, where the third sequence consists of the first sequence and the second sequence, the mother code length corresponding to the third sequence is 2*N, the second rate-matching is determined based on a relationship between f(E1) and E2, and the value of f(E1) is determined based on E1; N, E1, and E2 are positive integers.

[0160] In one possible embodiment, f(E1)=a*E1+b, where a is a constant greater than 0 and less than or equal to 1, and b is a constant with an absolute value less than E1.

[0161] In one possible implementation, if E2 is greater than or equal to f(E1), the second rate matching is performed based on the fifth bit sequence, or if E2 is less than f(E1), the second rate matching includes puncturing all bits in the fifth bit sequence whose sequence numbers fall within [0, N / 2-1] and performing third rate matching on all bits in the fifth bit sequence whose sequence numbers fall within [N / 2, N-1], wherein the fifth bit sequence consists of all bits in the third bit sequence whose sequence numbers fall within [0, N-1].

[0162] In this embodiment, the fifth bit sequence is the first half of the third bit sequence, i.e., the fifth bit sequence consists of all bits whose sequence numbers fall within [0,N-1] in the third bit sequence. If E2 is equal to or greater than f(E1), the second rate matching is performed based on the mother code length N. If E2 is less than f(E1), the second rate matching is performed based on half the mother code length, i.e., N / 2.

[0163] In one possible embodiment, when E2 is greater than or equal to f(E1): If E2 is less than N, the second rate matching is bit-reversal shortening, or if E2 is greater than N, the second rate matching is repetition, or If E2 is less than f(E1): If E2 is less than N / 2, the third rate matching is bit reversal shortening, or if E2 is greater than N / 2, the third rate matching is repetition; f(E1) is E1-N / 16.

[0164] In one possible embodiment, when E2 is greater than or equal to f(E1), the second rate matching includes bit reversal shortening on the fifth bit sequence followed by puncturing in natural order, or If E2 is less than f(E1), The third rate matching is bit-reversal shortening, f(E1) is E1 / 2.

[0165] In one possible embodiment, N is determined based on E1. Specifically,

number

[0166] In one possible implementation, the first rate matching is bit-reversal shortening.

[0167] As shown in FIG. 11 , an embodiment of the present application further provides an apparatus 1100. The apparatus 1100 is configured to perform the functions of a transmitter or a receiver in the aforementioned method. The apparatus may be a transmitter or a receiver, a device within a transmitter or a receiver, or a device that can be used in conjunction with a transmitter or a receiver. The apparatus 1100 may be a chip system. In an embodiment of the present application, the chip system may include a chip, or may include a chip and another discrete device. The apparatus 1100 includes at least one processor 1120 configured to perform the functions of a transmitter or a receiver in the method provided in the embodiment of the present application. The apparatus 1100 may further include a transceiver 1110.

[0168] The apparatus 1100 may be specifically configured to perform the associated methods performed by the transmitter in the method embodiments described above. An example is as follows.

[0169] The transceiver 1110 receives a bit sequence to be encoded; The processor 1120 performs polar encoding on the bit sequence to be encoded to obtain a first bit sequence, where the first bit sequence has a length of N; The processor 1120 performs first rate matching on the first bit sequence to obtain a second bit sequence, where the second bit sequence has a length of E1, and the transceiver unit transmits the second bit sequence; The processor 1120 performs polar encoding based on the bit sequence to be encoded to obtain a third bit sequence, wherein the third bit sequence has a length of 2*N; The processor 1120 performs second rate matching on the third bit sequence to obtain a fourth bit sequence, wherein the fourth bit sequence has a length of E2; The second rate matching is determined based on a relationship between f(E1) and E2, and the value of f(E1) is determined based on E1; The transceiver 1110 transmits a fourth bit sequence; N, E1, and E2 are positive integers.

[0170] The apparatus 1100 may be specifically configured to perform the associated methods performed by the receiver in the method embodiments described above. An example is as follows.

[0171] The transceiver 1110 obtains a first sequence, where the length of the first sequence is E1 and the mother code length corresponding to the first sequence is N; the processing unit rate-dematches the first sequence according to a first rate-matching scheme, and then decodes the rate-dematched first sequence; The transceiver 1110 obtains a second sequence, the second sequence having a length of E2; The processor 1120 rate-dematches the third sequence based on the first rate-matching scheme and the second rate-matching scheme, and then decodes the rate-dematched third sequence, where the third sequence consists of the first sequence and the second sequence, a mother code length corresponding to the third sequence is 2*N, the second rate-matching is determined based on a relationship between f(E1) and E2, and the value of f(E1) is determined based on E1; N, E1, and E2 are positive integers.

[0172] The device 1100 may further include at least one memory 1130 configured to store program instructions and / or data. The memory 1130 is coupled to the processor 1120. In an embodiment of the present application, the coupling may be an indirect coupling or communication connection between devices, units, or modules, and may be in an electrical, mechanical, or other form, used for information exchange between the devices, units, or modules. The processor 1120 may cooperate with the memory 1130. The processor 1120 may execute program instructions stored in the memory 1130. In one possible embodiment, at least one of the at least one memory may be integrated with the processor. In another possible embodiment, the memory 1130 is located external to the device 1100.

[0173] The specific connection medium between the transceiver 1110, the processor 1120, and the memory 1130 is not limited in the embodiment of the present application. In the embodiment of the present application, the memory 1130, the processor 1120, and the transceiver 1110 are connected via a bus 1140 in FIG. 11. In FIG. 11, the bus is represented by using a thick line. The connection method between other components is merely an example for explanation and does not constitute a limitation. The bus may be classified into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used to represent the bus in FIG. 11, but this does not mean that there is only one bus or one type of bus.

[0174] In the embodiments of the present application, the processor 1120 may be one or more central processing units (CPUs). When the processor 1120 is a CPU, the CPU may be a single-core CPU or a multi-core CPU. The processor 1120 may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or another programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or perform the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of the present application may be performed and completed directly by a hardware processor, or may be performed and completed using a combination of hardware and software modules in the processor.

[0175] In an embodiment of the present application, the memory 1130 may include, but is not limited to, non-volatile memory such as a hard disk drive (HDD) or a solid-state drive (SSD), random access memory (RAM), erasable programmable read-only memory (EPROM), read-only memory (ROM), portable read-only memory (CD-ROM), etc. The memory is any other medium that can be configured to carry or store expected program code in the form of instructions or data structures and that can be accessed by a computer. However, this is not limited to this. In an embodiment of the present application, the memory may alternatively be a circuit or any other device that can perform a storage function and is configured to store program instructions and / or data. The memory 1130 is used to store related instructions and data.

[0176] As shown in Figure 12, an embodiment of the present application further provides an apparatus 1200 that can be configured to perform the functions of the transmitter in the aforementioned method. The apparatus 1200 can be a communication device or a chip within a communication device. an input / output interface 1210 for receiving the bit sequence to be encoded; a logic circuit 1220 for performing polar encoding on a bit sequence to be encoded to obtain a first bit sequence, the first bit sequence having a length N; Including, The logic circuit 1220 performs first rate matching on the first bit sequence to obtain a second bit sequence, the second bit sequence having a length of E1, and the transceiver unit transmits the second bit sequence; The logic circuit 1220 performs polar encoding based on the bit sequence to be encoded to obtain a third bit sequence, the third bit sequence having a length of 2*N; The logic circuit 1220 performs a second rate match on the third bit sequence to obtain a fourth bit sequence, the fourth bit sequence having a length of E2; The second rate matching is determined based on a relationship between f(E1) and E2, and the value of f(E1) is determined based on E1; The input / output interface 1210 transmits the fourth bit sequence; N, E1, and E2 are positive integers.

[0177] An apparatus 1200 is provided that may be configured to perform the functions of the receiver in the aforementioned method. The apparatus 1200 may be a communication device or a chip within a communication device. an input / output interface 1210 for receiving a first sequence, where the length of the first sequence is E1 and the mother code length corresponding to the first sequence is N; and a processing unit for rate-dematching the first sequence according to a first rate-matching scheme and then decoding the rate-dematched first sequence; Including, The input / output interface 1210 receives a second sequence, the length of the second sequence is E2; The logic circuit 1220 rate-dematches the third sequence based on the first rate-matching scheme and the second rate-matching scheme, and then decodes the rate-dematched third sequence, where the third sequence consists of the first sequence and the second sequence, and the f corresponding to the third sequence is 2*N, the second rate-matching is determined based on a relationship between f(E1) and E2, and the value of f(E1) is determined based on E1; N, E1, and E2 are positive integers.

[0178] 13 is a performance simulation diagram of the solution of the present application and CC-HARQ when the number of bits to be coded is K=424. The horizontal coordinate is the length E2 of the retransmission bit sequence, and the vertical coordinate is E s / N0, i.e., the signal-to-noise ratio. For example, Figure 13 separately shows performance simulation diagrams of the two solutions when the transmission code rates are R=1 / 2, R=2 / 3, R=3 / 4, and R=5 / 6. It can be clearly seen that the solution of the present application has better performance than CC-HARQ at different transmission code rates. Specifically, when the bit error rate is 0.01, as the length E2 of the retransmission bit sequence increases continuously, the signal-to-noise ratio required by the two solutions decreases continuously, i.e., as the length of the retransmission bit sequence increases, the interference prevention capability is strengthened. Also, for the same length of the retransmission bit sequence, the signal-to-noise ratio required by the solution of the present application to achieve a bit error rate of 0.01 is smaller than the signal-to-noise ratio required for CC-HARQ. That is, the solution of the present application can achieve a system indicator under worse communication conditions. In comparison, the solution of the present application has better performance at various different transmission code rates.

[0179] 14A, 14B, and 14C are performance simulation diagrams of the present solution and CC-HARQ, respectively, showing the performance simulation diagrams of the two solutions for different relationships between the length E1 of the initial transmission bit sequence and the length E2 of the retransmission bit sequence. For example, FIGS. 14A, 14B, and 14C show performance simulation diagrams for E1=1 / 4E2, E1=1 / 2E2, and E1=3 / 4E2. The case of E1=1 / 2E2 is used as an example for explanation. In the diagrams, the horizontal coordinate is the length of the information bit sequence, the vertical coordinate is the signal-to-noise ratio, the solid line is the performance simulation diagram of CC-HARQ at different transmission code rates, and the dashed line is the performance simulation diagram of the present solution at different transmission code rates. Similarly, when the bit error rate is 0.01, the signal-to-noise ratio required for the solution of the present application to achieve a bit error rate of 0.01 at the same transmission code rate is smaller than that required for CC-HARQ. That is, the solution of the present application can achieve a system indicator under worse communication conditions. In comparison, the solution of the present application has better performance at various different transmission code rates.

[0180] If the communication device is a chip used in a terminal device, the chip in the terminal device performs the functions of the terminal device in the above-mentioned method embodiments. The chip in the terminal device receives information from another module (e.g., a radio frequency module or an antenna) in the terminal device, and the information is transmitted to the terminal device by the network device. Alternatively, the chip in the terminal device transmits information to another module (e.g., a radio frequency module or an antenna) in the terminal device, and the information is transmitted to the network device by the terminal device.

[0181] If the communication device is a chip used in a network device, the chip in the network device performs the functions of the network device in the above-mentioned method embodiments. The chip in the network device receives information from another module (e.g., a radio frequency module or an antenna) in the network device, and the information is transmitted to the network device by the terminal device. Alternatively, the chip in the network device transmits information to another module (e.g., a radio frequency module or an antenna) in the network device, and the information is transmitted to the terminal device by the network device.

[0182] Based on the same concept as the above-mentioned method embodiment, an embodiment of the present application further provides a computer-readable storage medium, which stores a computer program, and the computer program is executed by hardware (e.g., a processor) to perform some or all of the steps of any method performed by any device in the embodiments of the present application.

[0183] Based on the same concept as the method embodiment, an embodiment of the present application further provides a computer program product including instructions, which, when executed on a computer, enables the computer to perform some or all of the steps of any of the methods in the aforementioned aspects.

[0184] Based on the same concept as the aforementioned method embodiment, the present application further provides a chip or a chip system. The chip may include a processor. The chip may further include a memory (or storage module) and / or a transceiver (or communication module), or the chip is coupled to the memory (or storage module) and / or the transceiver (or communication module). The transceiver (or communication module) may be configured to support the chip in performing wired and / or wireless communication, and the memory (or storage module) may be configured to store a program. The processor may invoke the program to perform the operations performed by the terminal or network device in any one of the method embodiments or possible implementations of the method embodiment. The chip system may include the aforementioned chip, or may include the aforementioned chip and another separate device, for example, the memory (or storage module) and / or the transceiver (or communication module).

[0185] Based on the same concept as the above-mentioned method embodiment, the present application further provides a communication system. The communication system may include the above-mentioned terminal and network device. The communication system may be configured to perform the operations performed by the terminal or network device in any one of the method embodiments or possible implementations of the method embodiment. For example, the communication system may have the structure shown in FIG. 1.

[0186] All or part of the above-described embodiments may be implemented using software, hardware, firmware, or any combination thereof. When software is used for implementation, all or part of the above-described embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded into a computer and executed, all or part of the procedures or functions according to the embodiments of the present application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or another programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, or digital subscriber line) or wireless (e.g., infrared, radio wave, or microwave) method. The computer-readable storage medium may be any available medium accessible by a computer, or may be a data storage device incorporating one or more available media, such as a server or a data center. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, or a magnetic tape), an optical medium (e.g., an optical disk), a semiconductor medium (e.g., a solid-state drive), etc. In the above-mentioned embodiments, the description of the embodiments has its own focus. For parts not described in detail in one embodiment, please refer to the related description of another embodiment.

[0187] In the above-mentioned embodiments, the description of the embodiments has its own focus, and for the parts not described in detail in one embodiment, please refer to the related description of another embodiment.

[0188] In some embodiments provided in this application, it should be understood that the disclosed devices may be implemented in other ways. For example, the described device embodiments are merely examples. For example, the division into units is merely a logical division of functions, and other divisions may be used in actual implementations. For example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not implemented. Furthermore, the shown or described mutual indirect or direct couplings or communication connections may be implemented using some interfaces. Indirect couplings or communication connections between devices or units may be implemented in electronic or other forms.

[0189] The units described as separate parts may or may not be physically separate, and the parts shown as units may or may not be physical units, and may be located in one place or distributed across multiple network units. Some or all of the units may be selected based on actual requirements to achieve the objectives of the solutions in the embodiments.

[0190] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, the integrated unit may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may essentially, or a part that contributes to the prior art, or all or a part of the technical solution may be implemented in the form of a software product. The computer software product is stored in a storage medium and includes some instructions for instructing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or a part of the steps of the method in the embodiments of the present application.

[0191] The above descriptions are merely some specific embodiments of the present application and are not intended to limit the scope of protection of the present application. Those skilled in the art may make other changes and modifications to these embodiments within the technical scope disclosed in the present application. Therefore, the appended claims are intended to be interpreted to include the above-mentioned embodiments and the changes and modifications that fall within the scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope of protection of the claims. [Explanation of symbols]

[0192] 1 HARQ solution 1000 Rate Matching Device 1010 Transceiver Unit 1020 Processing Unit 1100 equipment 1110 transceiver 1120 processor 1130 memory 1140 Bus 1200 equipment 1210 Input / Output Interface 1220 Logic Circuit 1230 memory

Claims

1. 1. A rate matching method, the method comprising: obtaining, by a transmitter, a bit sequence to be encoded; performing, by the transmitter, polar encoding on the to-be-encoded bit sequence to obtain a first bit sequence, the first bit sequence having a length of N; performing, by the transmitter, first rate matching on the first bit sequence to obtain a second bit sequence, wherein the length of the second bit sequence is E 1 Steps transmitting, by the transmitter, the second bit sequence; performing, by the transmitter, polar encoding based on the to-be-encoded bit sequence to obtain a third bit sequence, wherein the third bit sequence has a length of 2*N; performing, by the transmitter, second rate matching on the third bit sequence to obtain a fourth bit sequence, wherein the fourth bit sequence has a length E 2 and the second rate matching is f(E 1 ) and E 2 f(E 1 ) is E 1 and transmitting, by the transmitter, the fourth bit sequence; Including, N, E 1 , and E 2 is a positive integer, f(E 1 )=a*E 1 +b, where a is a constant greater than 0 and less than or equal to 1, b is a constant having an absolute value less than or equal to E 1 , and f(E 1 ) is less than E 1 ; Rate matching method.

2. E 2 f(E 1 ), the second rate matching is performed based on a fifth bit sequence; or E 2 f(E 1 ), the second rate matching includes puncturing all bits in the fifth bit sequence whose sequence numbers fall within [0, N / 2-1], and performing third rate matching on all bits in the fifth bit sequence whose sequence numbers fall within [N / 2, N-1]; The fifth bit sequence consists of all bits in the third bit sequence whose sequence numbers fall within [0, N-1]. The method of claim 1.

3. E 2 f(E 1 ) or greater: E 2 is less than N, the second rate matching is bit-reversal shortening, or E 2 is greater than or equal to N, the second rate matching is iterative; or E 2 f(E 1 ) if: E 2 is less than N / 2, the third rate matching is bit-reversal shortening, or E 2 is greater than or equal to N / 2, the third rate matching is iterative; f (E 1 ) is E 1 -N / 16, The method of claim 2.

4. E 2 f(E 1 ) or more, the second rate matching includes bit reversal shortening of the fifth bit sequence followed by puncturing in natural order; or E 2 f(E 1 ), the third rate matching is bit reversal shortening; f (E 1 ) is E 1 / 2, The method of claim 2.

5. N is E 1 determined based on 5. The method according to any one of claims 1 to 4.

6. the first rate matching is bit reversal shortening; The method of claim 1.

7. 1. A rate matching method, the method comprising: obtaining, by a receiver, a first bit sequence, the length of the first bit sequence being E 1 and a mother code length corresponding to the first bit sequence is N; rate-dematching, by the receiver, the first bit sequence based on a first rate-matching scheme, and then decoding the rate-dematched first bit sequence; obtaining, by the receiver, a second bit sequence, the second bit sequence having a length E 2 Steps rate-dematching, by the receiver, a third bit sequence based on the first rate-matching scheme and a second rate-matching scheme, and then decoding the rate-dematched third bit sequence, wherein the third bit sequence consists of the first bit sequence and the second bit sequence, and a mother code length corresponding to the third bit sequence is 2*N; Including, The second rate matching is f(E 1 ) and E 2 f(E 1 ) is the value of E 1 is determined based on N, E 1 , and E 2 is a positive integer, f(E 1 )=a*E 1 +b, where a is a constant greater than 0 and less than or equal to 1, b is a constant having an absolute value less than or equal to E 1 , and f(E 1 ) is less than E 1 ; Rate matching method.

8. E 2 f(E 1 ), the second rate matching is performed based on a fifth bit sequence; or E 2 f(E 1 ), the second rate matching includes puncturing all bits in the fifth bit sequence whose sequence numbers fall within [0, N / 2-1], and performing third rate matching on all bits in the fifth bit sequence whose sequence numbers fall within [N / 2, N-1]; The fifth bit sequence consists of all bits in the third bit sequence whose sequence numbers fall within [0, N-1]. The method of claim 7.

9. E 2 f(E 1 ) or greater: E 2 is less than N, the second rate matching is bit-reversal shortening, or E 2 is greater than or equal to N, the second rate matching is iterative; or E 2 f(E 1 ) if: E 2 is less than N / 2, the third rate matching is bit-reversal shortening, or E 2 is greater than or equal to N / 2, the third rate matching is iterative; f (E 1 ) is E 1 -N / 16, The method of claim 8.

10. E 2 f(E 1 ) or more, the second rate matching includes bit reversal shortening of the fifth bit sequence followed by puncturing in natural order; or E 2 f(E 1 ), the third rate matching is bit reversal shortening; f (E 1 ) is E 1 / 2, The method of claim 8.

11. N is E 1 determined based on 11. The method according to any one of claims 7 to 10.

12. the first rate matching is bit reversal shortening; The method of claim 7.

13. 1. A rate matching apparatus for use in a transmitter, the apparatus comprising: a transceiver unit and a processing unit; the transceiver unit obtains a bit sequence to be encoded; the processing unit performs polar encoding on the to-be-encoded bit sequence to obtain a first bit sequence, the first bit sequence having a length of N; The processing unit performs first rate matching on the first bit sequence to obtain a second bit sequence, and the second bit sequence has a length E 1 and the transceiver unit transmits the second bit sequence; the processing unit performs polar encoding based on the to-be-encoded bit sequence to obtain a third bit sequence, wherein the third bit sequence has a length of 2*N; The processing unit performs second rate matching on the third bit sequence to obtain a fourth bit sequence, and the fourth bit sequence has a length E 2 and the second rate matching is f(E 1 ) and E 2 f(E 1 ) is the value of E 1 is determined based on the transceiver unit transmits the fourth bit sequence; N, E 1 , and E 2 is a positive integer, f(E 1 )=a*E 1 +b, where a is a constant greater than 0 and less than or equal to 1, b is a constant having an absolute value less than or equal to E 1 , and f(E 1 ) is less than E 1 ; Rate matching device.

14. E 2 f(E 1 ), the second rate matching is performed based on a fifth bit sequence; or E 2 f(E 1 ), the second rate matching includes puncturing all bits in the fifth bit sequence whose sequence numbers fall within [0, N / 2-1], and performing third rate matching on all bits in the fifth bit sequence whose sequence numbers fall within [N / 2, N-1]; The fifth bit sequence consists of all bits in the third bit sequence whose sequence numbers fall within [0, N-1].

14. The apparatus of claim 13.

15. E 2 f(E 1 ) or greater: E 2 is less than N, the second rate matching is bit-reversal shortening, or E 2 is greater than or equal to N, the second rate matching is iterative; or E 2 f(E 1 ) if: E 2 is less than N / 2, the third rate matching is bit-reversal shortening, or E 2 is greater than or equal to N / 2, the third rate matching is iterative; f (E 1 ) is E 1 - expressed as N / 16, 15. The apparatus of claim 14.

16. E 2 f(E 1 ) or more, the second rate matching includes bit reversal shortening of the fifth bit sequence followed by puncturing in natural order; or E 2 f(E 1 ), the third rate matching is bit reversal shortening; f (E 1 ) is E 1 / 2, 15. The apparatus of claim 14.

17. N is E 1 determined based on 17. Apparatus according to any one of claims 13 to 16.

18. the first rate matching is bit reversal shortening; 14. The apparatus of claim 13.

19. 1. A rate matching apparatus for use in a receiver, the apparatus comprising: a transceiver unit and a processing unit; The transceiver unit obtains a first bit sequence, the first bit sequence having a length E 1 and the mother code length corresponding to the first bit sequence is N; The processing unit rate-dematches the first bit sequence based on a first rate-matching scheme, and then decodes the rate-dematched first bit sequence; The transceiver unit obtains a second bit sequence, the second bit sequence having a length E 2 and the processing unit rate-dematches a third bit sequence according to the first rate-matching scheme and the second rate-matching scheme, and then decodes the rate-dematched third bit sequence, wherein the third bit sequence consists of the first bit sequence and the second bit sequence, and a mother code length corresponding to the third bit sequence is 2*N; The second rate matching is f(E 1 ) and E 2 f(E 1 ) is the value of E 1 is determined based on N, E 1 , and E 2 is a positive integer, f(E 1 )=a*E 1 +b, where a is a constant greater than 0 and less than or equal to 1, b is a constant having an absolute value less than or equal to E 1 , and f(E 1 ) is less than E 1 ; Rate matching device.

20. E 2 f(E 1 ), the second rate matching is performed based on a fifth bit sequence; or E 2 f(E 1 ), the second rate matching includes puncturing all bits in the fifth bit sequence whose sequence numbers fall within [0, N / 2-1], and performing third rate matching on all bits in the fifth bit sequence whose sequence numbers fall within [N / 2, N-1].

20. The apparatus of claim 19.

21. E 2 f(E 1 ) or greater: E 2 is less than N, the second rate matching is bit-reversal shortening, or E 2 is greater than or equal to N, the second rate matching is iterative; or E 2 f(E 1 ) if: E 2 is less than N / 2, the third rate matching is bit-reversal shortening, or E 2 is greater than or equal to N / 2, the third rate matching is iterative; f (E 1 ) is E 1 -N / 16, 21. The apparatus of claim 20.

22. E 2 f(E 1 ) or more, the second rate matching includes bit reversal shortening of the fifth bit sequence followed by puncturing in natural order; or E 2 f(E 1 ), the third rate matching is bit reversal shortening; f (E 1 ) is E 1 / 2, 21. The apparatus of claim 20.

23. N is E 1 determined based on 23. Apparatus according to any one of claims 19 to 22.

24. the first rate matching is bit reversal shortening; 20. The apparatus of claim 19.

25. A communications device comprising a processor, a memory, and a transmitter or receiver, the processor coupled to the memory, the memory configured to store a computer program or instructions, the processor configured to execute the computer program or instructions to perform the method of any one of claims 1 to 4 and 6 or any one of claims 7 to 10 and 12. Communication equipment.

26. 1. A communication device that functions as a transmitter, the communication device including a logic circuit and an input / output interface, the input / output interface is configured to pass an externally input bit sequence to be encoded to the logic circuit; the input / output interface is further configured to output the second bit sequence and the fourth bit sequence passed from the logic circuit to the outside; The logic circuit is configured to perform the method of any one of claims 1 to 4 and 6. Communication equipment.

27. A communication device functioning as a receiver includes a logic circuit and an input / output interface, wherein the input / output interface is configured to pass a first bit sequence and a second bit sequence input from an external device to the logic circuit; The logic circuit is configured to perform the method of any one of claims 7 to 10 and 12. Communication equipment.

28. 13. A computer-readable storage medium storing a computer program or instructions that, when executed by a processor on a computer functioning as a transmitter or a receiver, cause the computer to perform the method of any one of claims 1 to 4 and 6 or any one of claims 7 to 10 and 12.

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