Semiconductor light emitting device and method for manufacturing the same

Abstract

To provide a semiconductor light emitting element and a method for manufacturing a semiconductor light emitting element capable of increasing light out-coupling in the main or back surface direction even in a semiconductor light emitting element having a columnar semiconductor layer.SOLUTION: The semiconductor light emitting element (10) has a growth substrate (11), a plurality of columnar semiconductor layers (14-16) formed on the growth substrate (11), and an embedding layer (17) formed over the columnar semiconductor layers (14-16), and the columnar semiconductor layers (14-16) have a nanowire layer (14), active layer (15) formed on the periphery of the nanowire layer (14), and a p-type layer (16) formed on the periphery of the active layer (15), and the side surface of the active layer (15) is formed at an angle to the main surface of the growth substrate (11).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor light emitting device and a method for manufacturing the same, and more particularly to a semiconductor light emitting device having a structure in which a plurality of columnar semiconductor layers are buried in a burying layer, and a method for manufacturing the same. [Background technology]

[0002] In recent years, rapid advances have been made in crystal growth methods for nitride-based semiconductors, leading to the practical application of high-brightness blue and green light-emitting devices using these materials. By combining existing red light-emitting devices with these blue and green light-emitting devices, all three primary colors of light can be achieved, making full-color display devices possible. In other words, mixing all three primary colors of light makes it possible to obtain white light, which can also be applied to lighting devices.

[0003] It is desirable for semiconductor light-emitting elements used as light sources for lighting applications to achieve high energy conversion efficiency and high optical output in high current density regions, and for the light distribution characteristics of the emitted light to be stable.To solve these problems, Patent Document 1 proposes a semiconductor light-emitting element in which an n-type nanowire core, an active layer, and a p-type layer are grown on a growth substrate, and tunnel junction layers are formed on the side surfaces of the p-type layer, which are then buried with an n-type buried layer.

[0004] Figure 4 is a schematic diagram showing a semiconductor light-emitting device with a columnar semiconductor layer that has been proposed in the past, where Figure 4(a) is a schematic cross-sectional view and Figure 4(b) is a schematic perspective view showing the light extraction direction. As shown in Figure 4(a), the semiconductor light-emitting device includes a growth substrate 1, an underlayer 2, a mask 3, a nanowire layer 4, an active layer 5, a p-type layer 6, a buried layer 7, a cathode electrode 8n, and an anode electrode 8p. Here, the nanowire layer 4, the active layer 5, and the p-type layer 6 are formed to stand at a predetermined angle with respect to the main surface of the growth substrate 1, and form a columnar semiconductor layer with a double heterostructure.

[0005] In such a semiconductor light-emitting device, when a voltage is applied between the anode electrode 8p and the cathode electrode 8n, holes are injected from the buried layer 7 into the p-type layer 6, and electrons are injected from the underlayer 2 into the nanowire layer 4, resulting in light emission of a predetermined wavelength by radiative recombination in the active layer 5. In such a semiconductor light-emitting device, fewer crystal defects and threading dislocations occur in each semiconductor layer than in a device in which the active layer is formed over the entire surface of the growth substrate 1, resulting in higher-quality crystals. In addition, because the active layer has a facet in the m-plane, which is a nonpolar plane along the side surface of the columnar semiconductor layer, the external quantum efficiency at high current densities can be improved. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2020-077817 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in this conventional technology, the active layer 5 is formed along the side surface of the pillar-shaped semiconductor layer, and the double heterostructure is also formed along the side surface, so that the light emitted from the active layer 5 tends to be extracted in the in-plane direction rather than the main surface direction, as shown in Figure 4(b). Such in-plane light extraction is not desirable for surface-emitting semiconductor light-emitting devices. In addition, light emitted from each pillar-shaped semiconductor layer may be absorbed by other pillar-shaped semiconductor layers as it travels in the plane, making it difficult to improve the external quantum efficiency.

[0008] Therefore, the present invention has been made in consideration of the above-mentioned conventional problems, and aims to provide a semiconductor light-emitting element and a method for manufacturing a semiconductor light-emitting element that can increase the amount of light extracted in the main surface direction or the back surface direction, even in a semiconductor light-emitting element having a columnar semiconductor layer. [Means for solving the problem]

[0009] In order to solve the above problems, the present invention provides a semiconductor light emitting device including a growth substrate, a plurality of pillar-shaped semiconductor layers formed on the growth substrate, Multiple The pillar-shaped semiconductor layer Side and top formed over the Conductive a buried layer, the columnar semiconductor layer comprising a nanowire layer, an active layer formed on the outer periphery of the nanowire layer, and a p-type layer formed on the outer periphery of the active layer, and a side surface of the active layer is configured as a facet at an inclination angle of 80 degrees or less with respect to the growth substrate.

[0010] In such a semiconductor light-emitting element of the present invention, the side surfaces of the active layer are inclined with respect to the main surface of the growth substrate, so that light emitted from the active layer is extracted diagonally upward from the growth substrate, thereby increasing the amount of light extracted in the direction of the main surface.

[0011] In another aspect of the present invention, the nanowire layer comprises: of the growth substrate The substrate has an inclined side surface that is inclined relative to the main surface.

[0012] In one aspect of the present invention, a mask is formed on the growth substrate, the nanowire layer is selectively grown from openings in the mask, and the inclined side portions are formed in areas that partially cover the mask.

[0013] In one aspect of the present invention, the nanowire layer, the active layer, and the p-type layer are made of nitride semiconductors.

[0014] In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor light-emitting device, comprising: a pillar-shaped semiconductor growth step of forming a plurality of pillar-shaped semiconductor layers on a growth substrate; Multiple The pillar-shaped semiconductor layer Side and top Covering Conductive a buried layer forming step of forming a buried layer, Pillar-shaped semiconductor growth processThe method comprises a nanowire layer growth step of forming a nanowire layer having an inclined side surface portion that is inclined with respect to the main surface of the growth substrate, an active layer growth step of forming an active layer on the outer periphery of the inclined side surface portion, and a p-type layer growth step of forming a p-type layer on the outer periphery of the active layer, wherein the inclined side surface portion is composed of a facet having an inclination angle of 80 degrees or less with respect to the growth substrate.

[0015] In one aspect of the present invention, the nanowire layer growth process includes a nanowire core growth process for forming a nanowire core having side surfaces perpendicular to the main surface of the growth substrate, and an inclined side surface growth process for forming inclined side surfaces around the outer periphery of the nanowire core.

[0016] In one aspect of the present invention, the V / III ratio of the raw material is made lower in the inclined sidewall growth step than in the nanowire core growth step.

[0017] In one aspect of the present invention, the growth temperature in the inclined sidewall growth step is lower than that in the nanowire core growth step. [Effects of the Invention]

[0018] The present invention can provide a semiconductor light-emitting element and a method for manufacturing a semiconductor light-emitting element that can increase the amount of light extracted in the main surface direction or the back surface direction, even in a semiconductor light-emitting element having a columnar semiconductor layer. [Brief explanation of the drawings]

[0019] [Figure 1] 1A and 1B are diagrams showing a semiconductor light emitting device 10 according to a first embodiment, in which FIG. 1A is a schematic cross-sectional view and FIG. 1B is a partially enlarged cross-sectional view showing a columnar semiconductor layer in an enlarged manner. [Figure 2] 2(a) and 2(d) are schematic diagrams showing a method for manufacturing a semiconductor light-emitting element 10, in which FIG. 2(a) shows a mask formation process, FIG. 2(b) shows a nanowire core growth process within the nanowire layer growth process, FIG. 2(c) shows a sloped side portion growth process within the nanowire layer growth process, and FIG. 2(d) shows a growth process of an active layer 15 and a p-type layer 16. [Figure 3] 3A and 3B are schematic diagrams showing a method for manufacturing the semiconductor light emitting element 10, in which FIG. 3E shows a buried layer forming step, FIG. 3F shows a mesa forming step, and FIG. 3G shows an electrode forming step. [Figure 4] 4A and 4B are schematic diagrams showing a semiconductor light emitting device having a columnar semiconductor layer that has been proposed in the past, where FIG. 4A is a schematic cross-sectional view and FIG. 4B is a schematic perspective view showing the light extraction direction. DETAILED DESCRIPTION OF THE INVENTION

[0020] (First embodiment) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be given the same reference numerals, and duplicated descriptions will be omitted as appropriate. Figure 1 shows a semiconductor light emitting device 10 according to this embodiment, with Figure 1(a) being a schematic cross-sectional view and Figure 1(b) being a partially enlarged cross-sectional view showing a columnar semiconductor layer.

[0021] As shown in FIG. 1, a semiconductor light-emitting device 10 includes a growth substrate 11, an underlayer 12, a mask 13, a nanowire layer 14, an active layer 15, a p-type layer 16, a buried layer 17, a cathode electrode 18n, and an anode electrode 18p. The nanowire layer 14, the active layer 15, and the p-type layer 16 are selectively grown on the growth substrate 11 to form a vertically extending columnar shape, constituting the columnar semiconductor layer of the present invention. As shown in FIG. 1(b), the columnar semiconductor layer has side surfaces (inclined side surfaces) that are inclined relative to the major surface of the growth substrate 11, resulting in a trapezoidal cross section. While the columnar semiconductor layer shown here has a top surface and a trapezoidal cross section, it may also have a triangular cross section with the top surface reduced and most of the surface being composed of inclined side surfaces. The active layer 15 along the side surfaces of the nanowire layer 14 forms a double heterostructure sandwiched between the nanowire layer 14 and the p-type layer 16.

[0022] 1, in a portion of the semiconductor light emitting element 10, the buried layer 17 is removed from the surface down to the underlayer 12 to form a mesa groove (mesa structure), and the surface of the underlayer 12 is exposed, where a cathode electrode 18n is formed. In addition, an anode electrode 18p is formed on the buried layer 17. Here, the mesa structure refers to a structure in which a groove is formed through multiple semiconductor layers so as to surround a predetermined region, and a cross section of the stacked structure of each semiconductor layer is exposed from the side.

[0023] The growth substrate 11 is a substantially flat plate-shaped member made of a material on which a semiconductor material can be grown as a crystal. When the semiconductor light-emitting element 10 is made of a nitride-based semiconductor, a GaN substrate is preferably used as the growth substrate 11. To generate laser oscillation, a c-plane GaN substrate, which allows the cavity plane to be easily formed by cleavage, may be used. Alternatively, a heterogeneous substrate, such as a c-plane sapphire substrate or a Si substrate, made of a material different from the semiconductor material grown on the growth substrate 11 may be used.

[0024] The underlayer 12 is a single-crystal semiconductor layer formed on the growth substrate 11. When the growth substrate 11 and the underlayer 12 are made of different materials, it is preferable to grow a buffer layer on the surface of the growth substrate 11 and then form the underlayer 12 on the buffer layer. The underlayer 12 may be formed, for example, by forming undoped GaN to a thickness of several μm and then forming an n-type semiconductor layer such as an n-type contact layer thereon, in a multi-layer configuration. The n-type contact layer is a semiconductor layer doped with n-type impurities, for example, Si-doped n-type Al 0.05 Ga 0.95 N. A mask 13 is formed on the main surface side of the base layer 12. A part of the base layer 12 is exposed, and a cathode electrode 18n is formed thereon.

[0025] The buffer layer is a layer formed between the growth substrate 11 and the underlayer 12 to reduce lattice mismatch between them. When a c-plane sapphire substrate is used as the growth substrate 11, GaN is preferably used for the buffer layer, but AlN, AlGaN, or the like may also be used. When the growth substrate 11 and the underlayer 12 are made of the same material, a configuration without a buffer layer may be adopted. Furthermore, when a single crystal substrate such as a GaN substrate is used as the growth substrate 11, the cathode electrode 18n may be formed on the surface of the growth substrate without providing a buffer layer and underlayer 12.

[0026] The mask 13 is a layer made of a dielectric material formed on the surface of the underlayer 12. The material constituting the mask 13 is selected from those from which it is difficult to grow semiconductor crystals, such as SiO2 or SiN. x Suitable materials include Al2O3 and the like. A plurality of openings 13a, which will be described later, are formed in the mask 13, and a semiconductor layer can be grown on the surface of the base layer 12 that is partially exposed through the openings 13a.

[0027] The pillar-shaped semiconductor layer is a semiconductor layer grown in the openings 13a formed in the mask 13, and has a pillar-shaped structure in which the semiconductor layer is formed upright in a direction perpendicular to the main surface of the growth substrate 11. Such a pillar-shaped semiconductor layer can be obtained by setting appropriate growth conditions according to the semiconductor material and performing selective growth that grows a specific crystal plane orientation. In the example shown in FIG. 1, multiple openings 13a are formed two-dimensionally and periodically in the mask 13, and therefore the pillar-shaped semiconductor layer is also formed two-dimensionally and periodically on the growth substrate 11.

[0028] The nanowire layer 14 is a columnar semiconductor layer selectively grown on the underlayer 12 exposed through the opening 13a of the mask 13. The nanowire layer 14 is composed of, for example, GaN doped with n-type impurities. As shown in FIG. 1(b), the nanowire layer 14 is composed of a nanowire core 14a and inclined sidewalls 14b. The nanowire core 14a is the region indicated by the dashed line in FIG. 1(b) and is a columnar layer formed in a region extending vertically from the opening 13a of the mask 13. The inclined sidewalls 14b are layers formed around the nanowire core 14a and are formed so as to partially cover the mask 13. The sidewalls of the inclined sidewalls 14b constitute the sidewalls of the nanowire layer 14. The diameter of the inclined sidewalls 14b is larger on the side closer to the growth substrate 11 and decreases toward the tip of the nanowire core 14a. The inclined sidewalls 14b are inclined relative to the main surface of the growth substrate 11, forming a trapezoidal cross section. In Figure 1(b), the nanowire core 14a is shown with a dashed line and is described as being distinct from the inclined side portion 14b formed around it, but both can be made of the same material, in which case no clear boundary is formed.

[0029] When GaN is used for the nanowire layer 14, the nanowire core 14a selectively grown on the growth substrate 11 is formed in the shape of a roughly hexagonal prism with six m-planes formed as facets. In FIG. 1(b), the nanowire core 14a appears to grow only in the region where the opening 13a is formed, but in reality, crystal growth also progresses on the mask 13 due to lateral growth, so an enlarged hexagonal prism is formed around the opening 13a. For example, when the opening 13a is formed as a circle with a diameter of about 150 nm, a nanowire core 14a in the shape of a hexagonal prism with a height of about 1 to 2 μm can be formed, with the base being a hexagon inscribed in a circle with a diameter of about 200 nm. When the base layer 12 and the nanowire layer 14 are made of GaN, for example, the nanowire core 14a is formed in the shape of a hexagon with a height of about 1 to 2 μm, with an electron concentration of 10 18 atoms / cm -3 It is preferable that the n-type semiconductor layer be of this order.

[0030] Although this embodiment shows an example in which GaN is used for the nanowire layer 14, when the In composition of the active layer 15 is increased to lengthen the emission wavelength, GaInN may be used for the nanowire layer 14 to reduce misfit dislocations due to lattice mismatch. Similarly, when shortening the wavelength of the semiconductor light emitting element 10, it is also possible to use AlGaN for the nanowire layer 14, or to change the well layer and barrier layer of the active layer 15 to AlGaN with different compositions.

[0031] The active layer 15 is a semiconductor layer grown on the outer periphery of the nanowire layer 14. For example, it may be a multi-quantum well active layer formed by stacking five periods of 3-10 nm thick GaInN quantum well layers and 5-20 nm thick GaN barrier layers. While a multi-quantum well active layer is used here, it may also have a single quantum well structure or a bulk active layer. Because the active layer 15 is formed on the side and top surfaces of the nanowire layer 14, a sufficient area for the active layer 15 can be ensured. The higher the proportion of In incorporated into the active layer, the longer the emission wavelength of the semiconductor light-emitting element 10 becomes. By setting the In composition ratio to 0.10 or higher, an emission wavelength of 480 nm or longer can be achieved. Furthermore, by setting the In composition ratio to 0.12 or higher, an emission wavelength of 500 nm or longer can be achieved.

[0032] Furthermore, since the active layer 15 is formed on the outer periphery of the nanowire layer 14, it has a semipolar plane inclined with respect to the primary surface of the growth substrate 11, similar to the side surfaces of the nanowire layer 14. Here, a semipolar plane in GaN is a plane inclined from the c-plane in the range of more than 0 degrees and less than 90 degrees. Therefore, a voltage is applied to the semipolar plane inclined from the c-plane of GaN in the active layer 15, thereby improving the droop characteristics. Furthermore, the light emitted from the active layer 15 contains a large component perpendicular to the inclined side surface 14b, and a large proportion of the light travels diagonally upward in the growth substrate 11.

[0033] The p-type layer 16 is a semiconductor layer grown on the outer periphery of the active layer 15, and is made of, for example, GaN doped with p-type impurities. As shown in FIG. 1, the p-type layer 16 is formed so as to cover the side and top surfaces of the active layer 15. This forms a double heterostructure with the nanowire layer 14, the active layer 15, and the p-type layer 16, which effectively confines carriers in the active layer 15 and improves the probability of radiative recombination. While FIG. 1 shows an example in which the p-type layer 16 is made up of a single layer, it may also have a multi-layer structure covering the side surfaces of the active layer 15. Furthermore, because the p-type layer 16 is formed on the outer periphery of the active layer 15, it is inclined with respect to the major surface of the growth substrate 11, just like the side surfaces of the nanowire layer 14 and the active layer 15.

[0034] The buried layer 17 is a layer that fills the side and top surfaces of the above-mentioned multiple pillar-shaped semiconductor layers. Examples of materials that can be used to form the buried layer 17 include semiconductor materials such as GaN and transparent electrodes such as ITO (Indium Tin Oxide). An anode electrode 18p is formed on a portion of the surface of the buried layer 17. While FIG. 1 shows an example in which the buried layer 17 is formed as a single layer, it may have a multi-layer structure that is embedded from the surface of the base layer 12 to the top surfaces of the pillar-shaped semiconductor layers. Furthermore, when the buried layer 17 is made of a semiconductor material, a p-type semiconductor layer or an n-type semiconductor layer may be used to include functions such as a tunnel junction layer, a contact layer, and a current diffusion layer.

[0035] The mesa groove is a groove formed penetrating each semiconductor layer from the buried layer 17 to the underlayer 12, and forms a mesa structure by dividing the light emitting region of the semiconductor light emitting element 10. Element isolation grooves are further formed in the mesa groove to individually isolate the semiconductor light emitting elements 10.

[0036] The cathode electrode 18n is an electrode formed in the region where the base layer 12 is exposed in the mesa groove, and is composed of a laminated structure of a metal material that makes ohmic contact with the exposed semiconductor layer and a pad electrode. The anode electrode 18p is an electrode formed on a portion of the buried layer 17, and is composed of a laminated structure of a metal material that makes ohmic contact with the outermost surface of the buried layer 17 and a pad electrode. Although not shown in FIG. 1, a known structure may be applied, such as covering the surface of the semiconductor light emitting element 10 with a passivation film, if necessary. Alternatively, a transparent electrode that extends from the anode electrode 18p over the entire buried layer 17 may be formed.

[0037] 2A and 2B are schematic diagrams showing a method for manufacturing a semiconductor light-emitting element 10, with FIG. 2A showing a mask formation step, FIG. 2B showing a nanowire core growth step within the nanowire layer growth step, FIG. 2C showing a sloped sidewall growth step within the nanowire layer growth step, and FIG. 2D showing a growth step for an active layer 15 and a p-type layer 16. The nanowire core growth step and sloped sidewall growth step form a nanowire layer 14 having sloped sidewalls 14b under two growth conditions, and correspond to the nanowire layer growth step in the present invention. FIG. 3A is a schematic diagram showing a method for manufacturing a semiconductor light-emitting element 10, with FIG. 3E showing a buried layer formation step, FIG. 3F showing a mesa formation step, and FIG. 3G showing an electrode formation step.

[0038] First, as shown in Figure 2(a), a growth substrate 11 is prepared on which an underlayer 12 made of n-type GaN is formed. In the mask formation process, a mask 13 made of SiO2 is deposited on the underlayer 12 by sputtering to a thickness of approximately 30 nm, and an opening 13a with a diameter of approximately 150 nm is formed. A fine pattern formation method such as nanoimprinting lithography can be used to form the opening 13a. When a heterogeneous substrate such as sapphire is used as the growth substrate 11, a buffer layer, underlayer 12, and an n-type semiconductor layer may be formed on the sapphire substrate, and the surface of the n-type semiconductor layer may be used as the surface of the growth substrate 11. The buffer layer growth conditions are, for example, TMA (TriMethyl Aluminum), TMG (TriMethyl Gallium), and ammonia as source gases, a growth temperature of 1100°C, a V / III ratio of 1000, and a pressure of 10 hPa using hydrogen as a carrier gas. The growth conditions for the underlayer and the n-type semiconductor layer are, for example, a growth temperature of 1050° C., a V / III ratio of 1000, and a pressure of 500 hPa using hydrogen as a carrier gas.

[0039] 2(b), a nanowire core 14a made of GaN is grown on the base layer 12 exposed through the opening 13a by selective growth using MOCVD. The growth conditions for the nanowire core 14a are, for example, TMG and ammonia as source gases, a growth temperature of 1100°C, a V / III ratio of 20, hydrogen as carrier gas, and a pressure of 100 hPa. Under these growth conditions, the nanowire core 14a grows into a hexagonal prism shape with the m-plane perpendicular to the growth substrate 11 as a facet.

[0040] 2(c), crystal growth continues on the side and top surfaces of the nanowire core 14a to grow inclined side surfaces 14b, which have side surfaces inclined relative to the main surface of the growth substrate 11. The growth conditions for the inclined side surfaces 14b can be achieved by lowering the V / III ratio of the source material or by lowering the growth temperature compared to the growth conditions for the nanowire core 14a. For example, the V / III ratio can be set in the range of 1000 to 5000, and the growth temperature can be set in the range of 900 to 950°C.

[0041] By performing the inclined sidewall growth process under these growth conditions, the inclined sidewalls 14b formed around the nanowire core 14a have side faces with semipolar planes as facets, resulting in a trapezoidal cross section. Because the nanowire core 14a has a hexagonal prism shape, the nanowire layer 14, including the nanowire core 14a and the inclined sidewalls 14b, is formed into a hexagonal pyramid shape. Examples of semipolar facets include those with high-order plane indices expressed as [10-11], [10-12], [10-13], [20-21], and [30-31], with inclination angles of 62 degrees, 43 degrees, 32 degrees, 75 degrees, and 80 degrees relative to the c-plane, respectively.

[0042] Next, in the growth step of the active layer 15 and the p-type layer 16 shown in FIG. 2(d), the active layer 15 and the p-type layer 16 are grown on the side and upper surfaces of the nanowire layer 14 by MOCVD. The active layer 15 may have a multi-quantum well structure in which a GaInN quantum well layer having a thickness of 3 to 10 nm and a GaN barrier layer having a thickness of 5 to 20 nm are stacked five times. The p-type layer 16 may have a hole concentration of 10 18 ~10 19 atoms / cm -3 The nanowire core growth step shown in Fig. 2(b), the inclined sidewall growth step shown in Fig. 2(c), and the active layer 15 and p-type layer 16 growth step shown in Fig. 2(d) correspond to the columnar semiconductor layer growth step in the present invention.

[0043] The growth conditions for the active layer 15 are, for example, a growth temperature of 800°C, a V / III ratio of 3000, a pressure of 1000 hPa using nitrogen as a carrier gas, and raw material gases of TMG, TMI (TriMethylIndium), and ammonia. The p-type layer 16 may be, for example, p-type GaN made of GaN doped with p-type impurities. The growth conditions for the p-type layer 16 are, for example, a growth temperature of 950°C, a V / III ratio of 4000, a pressure of 300 hPa using hydrogen as a carrier gas, and raw material gases of TMG, Cp2Mg (bisCycropentadienylMagnesium), and ammonia.

[0044] 3(e), buried layer 17 is formed to cover the side and top surfaces of the plurality of columnar semiconductor layers. When buried layer 17 is formed of a p-type semiconductor layer, the growth conditions for buried layer 17 can be, for example, a growth temperature of 950°C, a V / III ratio of 1000, a pressure of 300 hPa using hydrogen as a carrier gas, and TMG, CpMg, and ammonia as source gases. When buried layer 17 is formed of a transparent electrode such as ITO, a known method such as sputtering can be used.

[0045] As described above, the burying layer 17 must be grown on the mask 13 between the pillar-shaped semiconductor layers. During growth of the burying layer 17, voids may form beneath the pillar-shaped semiconductor layers. Therefore, the burying layer 17 is preferably grown using TMG, silane, and ammonia as source gases at a low temperature and a low V / III ratio, which promotes lateral m-plane growth in the initial stage. Examples of low temperatures and low V / III ratios include a temperature of 800°C or lower, a V / III ratio of 100 or less, and a pressure of 200 hPa using hydrogen as a carrier gas. After the lateral growth of the burying layer 17 completely fills the mask 13 beneath the pillar-shaped semiconductor layers, the burying layer 17 is preferably grown at a high temperature and a high V / III ratio, which promotes vertical c-plane growth. Examples of high temperatures and high V / III ratios include a temperature of 1000°C or higher, a V / III ratio of 2000 or more, and a pressure of 500 hPa using hydrogen as a carrier gas.

[0046] 3(f), a mesa groove is formed by selectively removing a portion of the substrate from the buried layer 17 to the underlayer 12 by dry etching to expose the upper surface of the underlayer 12. By forming the mesa groove, the area surrounded by the mesa groove is defined as the light-emitting region of the semiconductor light-emitting element 10.

[0047] 3(g), a cathode electrode 18n is formed on the surface of the base layer 12 exposed in the mesa groove, and an anode electrode 18p is formed on the buried layer 17. After the electrode formation, annealing, formation of a passivation film, and element division are performed as necessary to obtain the semiconductor light emitting element 10.

[0048] In semiconductor light emitting device 10 of this embodiment, when a voltage is applied between cathode electrode 18n and anode electrode 18p, a current flows through buried layer 17, p-type layer 16, active layer 15, nanowire layer 14, and underlayer 12 in that order, and light is generated by radiative recombination in active layer 15. Because inclined side surface portion 14b and active layer 15 are inclined with respect to growth substrate 11, the light emitted from active layer 15 travels diagonally upward in growth substrate 11, improving the amount of light extracted in the direction of the main surface.

[0049] Furthermore, since the inclined side surface portion 14b of the nanowire layer 14 is a semipolar plane, the active layer 15 and p-type layer 16 formed on the outer periphery thereof are also in contact with each other through a semipolar plane. Since the polarization of a semipolar plane is smaller than that of a c-plane, the light-emitting efficiency of the active layer 15 is high, and since all the side surfaces of the hexagonal prism are semipolar planes, the light-emitting efficiency of the semiconductor light-emitting element 10 can be improved. Furthermore, since the film thickness of the active layer can be increased, the volume of the active layer 15 can be increased by approximately 3 to 10 times compared to conventional semiconductor light-emitting elements, thereby reducing the injected carrier density and significantly reducing efficiency droop.

[0050] As described above, in the semiconductor light-emitting element 10 and the method for manufacturing the semiconductor light-emitting element 10 of this embodiment, the side surfaces of the active layer 15 are inclined with respect to the main surface of the growth substrate 11, so that light emitted in the active layer 15 is extracted obliquely upward from the growth substrate 11, thereby increasing the amount of light extracted in the main surface direction. Furthermore, since the light emitted in the active layer 15 travels obliquely upward, the amount of light absorbed by other nanowire layers 14 can be reduced, thereby improving the external quantum efficiency. (Second embodiment)

[0051] Next, a second embodiment of the present invention will be described. Details that overlap with the first embodiment will not be described. In the first embodiment, the nanowire layer 14 is formed by a two-step growth process in which the nanowire core growth step and the inclined side surface growth step are performed under different conditions. However, in this embodiment, the nanowire layer 14 having the inclined side surface 14b is formed in one step.

[0052] In this embodiment, after the mask formation step shown in Fig. 2(a), the nanowire core 14a and the inclined side surface 14b are continuously formed in the nanowire layer growth step under the same conditions. The growth conditions in the nanowire growth step are either a lower V / III ratio of the source material or a lower growth temperature than those in the nanowire core growth step under which the side surface of the m-plane facet is formed.

[0053] For example, the growth conditions for forming m-plane facets are as follows: TMG and ammonia are used as source gases, the growth temperature is 1100°C, the V / III ratio is 20, hydrogen is used as the carrier gas, and the pressure is 100 hPa. Therefore, when growing the nanowire core 14a and the inclined sidewalls 14b in a single growth run, the following conditions can be used: a V / III ratio of 100 and a growth temperature of 1100°C; a V / III ratio of 20 and a growth temperature of 1000°C; or a V / III ratio of 100 and a growth temperature of 1000°C. By using these growth conditions, after the mask formation step shown in FIG. 2(a), upward growth from the opening 13a and lateral growth into the area covered by the mask 13 can be simultaneously performed in parallel, thereby forming the nanowire core 14a and the inclined sidewalls 14b in a single growth run.

[0054] Furthermore, the side surfaces of the nanowire layer 14 formed in this embodiment also have semipolar planes, as in the first embodiment, and the active layer 15 and p-type layer 16 are also formed at an incline with respect to the main surface of the growth substrate 11. This makes it possible to suppress polarization in the active layer 15, improve the luminous efficiency, and increase the amount of light extracted obliquely upward.

[0055] The present invention is not limited to the above-described embodiments, and various modifications within the scope of the claims are possible. Modifications are possible, and the technical means disclosed in the different embodiments may be appropriately combined. The resulting embodiments are also within the scope of the present invention. [Explanation of symbols]

[0056] 10...Semiconductor light emitting device 11...Growth substrate 12…base layer 13...Mask 13a...Opening 14...Nanowire layer 14a…Nanowire core 14b…Slanted side part 15...Active layer 16...p-type layer 17...Buried layer 18n...Cathode electrode 18p...Anode electrode

Claims

1. a growth substrate; a plurality of pillar-shaped semiconductor layers formed on the growth substrate; a conductive buried layer formed to cover the side surfaces and top surfaces of the plurality of pillar-shaped semiconductor layers, the pillar-shaped semiconductor layer includes a nanowire layer, an active layer formed on the outer periphery of the nanowire layer, and a p-type layer formed on the outer periphery of the active layer; A semiconductor light-emitting device, wherein the side surfaces of the active layer are formed as facets at an inclination angle of 80 degrees or less with respect to the growth substrate.

2. The semiconductor light emitting device according to claim 1 , The nanowire layer has an inclined side surface that is inclined with respect to the main surface of the growth substrate.

3. The semiconductor light emitting device according to claim 2, A semiconductor light-emitting element characterized in that a mask is formed on the growth substrate, the nanowire layer is selectively grown from openings provided in the mask, and the inclined side portion is formed in an area partially covering the mask.

4. 4. The semiconductor light emitting device according to claim 1, The semiconductor light-emitting device is characterized in that the nanowire layer, the active layer, and the p-type layer are made of nitride semiconductors.

5. a pillar-shaped semiconductor growth step of forming a plurality of pillar-shaped semiconductor layers on a growth substrate; a buried layer forming step of forming a conductive buried layer to cover the side surfaces and top surfaces of the plurality of pillar-shaped semiconductor layers, the pillar-shaped semiconductor growth step includes a nanowire layer growth step of forming a nanowire layer having an inclined side surface portion that is an inclined side surface with respect to a main surface of the growth substrate, an active layer growth step of forming an active layer on the periphery of the inclined side surface portion, and a p-type layer growth step of forming a p-type layer on the periphery of the active layer, The method for manufacturing a semiconductor light-emitting device, wherein the inclined side surface portion is formed by a facet having an inclination angle of 80 degrees or less with respect to the growth substrate.

6. 6. The method for manufacturing a semiconductor light-emitting device according to claim 5, The method for manufacturing a semiconductor light-emitting element is characterized in that the nanowire layer growth process includes a nanowire core growth process for forming a nanowire core having a side surface perpendicular to the main surface of the growth substrate, and an inclined side surface growth process for forming an inclined side surface portion around the outer periphery of the nanowire core.

7. 7. The method for manufacturing a semiconductor light-emitting device according to claim 6, A method for manufacturing a semiconductor light-emitting element, wherein the V / III ratio of the raw material in the inclined sidewall growth step is lower than that in the nanowire core growth step.

8. 8. A method for manufacturing a semiconductor light-emitting device according to claim 6 or 7, comprising: A method for manufacturing a semiconductor light-emitting element, wherein the growth temperature in the inclined sidewall growth step is lower than that in the nanowire core growth step.

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