Systems and methods for fault-tolerant quantum computing with reduced idle volume

Abstract

A fault-tolerant quantum computer using a topological code such as a surface code can have an architecture that reduces the amount of idle volume generated. The architecture can include qubit modules that generate surface code patches for different qubits and a network of interconnections between the different qubit modules. The interconnections can include "port" connections that selectively allow coupling of boundaries of surface code patches generated at different qubit modules, and / or "quick swap" connections that selectively allow transfer of the state of a surface code patch from one qubit module to another qubit module. The port and / or quick swap connections can be made between a subset of the qubit modules. For example, the port connections can connect a given qubit module to other qubit modules within a fixed range. The quick swap connections can provide a log tree network of direct connections between qubit modules.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Provisional Application No. 63 / 308,879, filed February 10, 2022, and U.S. Provisional Application No. 63 / 427,083, filed November 21, 2022, the disclosures of which are incorporated herein by reference. [Background technology]

[0002] Quantum computing is distinguished from "classical" computing by its reliance on information units called "qubits." Generally speaking, a "qubit" is the information content of a quantum system that can exist in one of two orthogonal states (denoted |0〉 and |1〉 in conventional bracket notation) or in a superposition of two states (e.g., any state (α|0〉 + β|1〉, where |α| 2 +|β| 2 = 1. Physical qubits have been realized in a variety of quantum systems, including superconducting systems, trapped ions, and photons.

[0003] A quantum computer is a device that operates on a system (or ensemble) of physical qubits to perform quantum computations. Because physical qubits (unlike classical bits) can exist in superposition states, quantum computers can rapidly perform certain categories of calculations that would require an impractical amount of time for a classical computer.

[0004] However, the practical application of general-purpose quantum computers remains a difficult challenge. Summary of the Invention

[0005] According to some embodiments, a fault-tolerant quantum computer using surface codes can have an architecture that reduces the amount of idle volume generated. The architecture can include qubit modules that generate surface code patches for different qubits and a network of interconnections between the different qubit modules. In some embodiments, the interconnections can include "port" connections that selectively allow coupling of boundaries of surface code patches generated on different qubit modules. In some embodiments, the interconnections can include "quick-swap" connections that allow selective transfer of the state of the surface code patches from one qubit module to another qubit module. In some embodiments, both a port connection network and a quick-swap connection network are provided. Connections can be made between subsets of qubit modules. For example, port connections can connect a given qubit module to other qubit modules within a fixed range. The quick-swap connections can provide a log-tree network of direct connections between qubit modules.

[0006] According to some embodiments, a system may comprise a plurality of qubit modules, each qubit module including circuitry configured to operate on a plurality of physical qubits to generate a topological code patch (e.g., a surface code patch) for a logical qubit during each of a plurality of code cycles, each topological code patch having a plurality of boundaries associated with different directions in entanglement space; and a plurality of quick-swap connections, each quick-swap connection selectively operable to couple a pair of qubit modules and swap a respective logical qubit between the pair of qubit modules within one code cycle, the quick-swap connections coupling each of the qubit modules to two or more other qubit modules.

[0007] In some embodiments, the quick-swap connections include at least one quick-swap connection coupling a pair of qubit modules that are not physically adjacent to one another.

[0008] In some embodiments, the quick-swap connection couples at least one of the qubit modules to at least four other qubit modules.

[0009] In some embodiments, each quick swap connection implements a lateral swap gate for the physical qubits in the respective topological code patches of the pair of qubit modules.

[0010] In some embodiments, the system may further comprise classical control logic coupled to the quick swap connections and configured to selectively enable or disable operation of each of the quick swap connections.

[0011] In some embodiments, the plurality of qubit modules includes a number (N) of qubit modules, each qubit module having an identification index ranging from 1 to N, and the plurality of quick swap connections includes:

[0012]

number

[0046] The method further includes a quick-swap connection coupling each pair of qubit modules having identification index values ​​i and j such that:

[0013] In some embodiments, the quick swap connections are configured such that swaps can be performed simultaneously for two or more disjoint pairs of qubit modules.

[0014] In some embodiments, the physical qubits are photonic qubits, and each quick-swap connection comprises an optical waveguide.

[0015] According to some embodiments, a method includes providing a plurality of qubit modules, including a plurality of workspace qubit modules and a plurality of memory qubit modules, each qubit module including circuitry configured to operate on a plurality of physical qubits to generate a topological code patch (e.g., a surface code patch) for a logical qubit during a code cycle; storing a logical qubit in each of at least a subset of the memory qubit modules; performing one or more quick swap operations between the memory qubit modules and the workspace qubit modules during a first code cycle, each quick swap operation swapping a current state in one of the workspace qubit modules with a logical qubit in one of the memory qubit modules; and performing a logic cycle comprising a plurality of code cycles. executing, in a plurality of workspace qubit modules, a plurality of logic blocks corresponding to one or more logic gate operations on one or more logical qubits, where executing the logic blocks includes generating topological code patches (e.g., surface code patches) for different logical qubits in at least two of the workspace qubit modules and performing an entanglement operation between the topological code patches in the different workspace qubit modules; and executing a logic cycle that includes, concurrently with executing the plurality of logic blocks, performing one or more additional quick swap operations between the memory qubit modules, where each additional quick swap operation swaps a respective logical qubit between a pair of memory qubit modules within one code cycle.

[0016] In some embodiments, at least one of the additional quick swap operations is performed between a pair of non-adjacent memory qubit modules.

[0017] In some embodiments, performing the one or more additional quick swap operations includes performing a first group of the one or more quick swap operations during a first code cycle of the logic cycle; and executing a second group of one or more quick swap operations during a second code cycle of the logic cycle.

[0018] In some embodiments, the method may further include performing one or more quick swap operations between the memory qubit module and the workspace qubit module, and performing a plurality of logical cycles by repeatedly performing the acts of performing the logical cycles.

[0019] In some embodiments, one or more additional quick swap operations between memory qubit modules performed during the first logic cycle result in rearranging the logical qubits within the memory modules in preparation for a subsequent logic cycle.

[0020] According to some embodiments, a system may comprise: a plurality of qubit modules, each qubit module including circuitry configured to operate on a plurality of physical qubits to generate a topological code patch (e.g., a surface code patch) for a logical qubit during each of a plurality of code cycles, each topological code patch having a plurality of boundaries associated with different directions in entanglement space; and a plurality of quick-swap connections, each quick-swap connection selectively operable to couple a first one of the qubit modules to a second one of the qubit modules and transfer the logical qubit from the first qubit module to the second qubit module within one code cycle, the quick-swap connections coupling each of the qubit modules to two or more other qubit modules.

[0021] In some embodiments, for at least one of the quick-swap connections, the first qubit module and the second qubit module are not physically adjacent to one another.

[0022] In some embodiments, the quick-swap connection couples at least one of the qubit modules to at least four other qubit modules.

[0023] In some embodiments, the quick swap connection is configured such that swaps can be performed simultaneously for two or more disjoint pairs of first and second qubit modules.

[0024] In some embodiments, the system may further comprise classical control logic coupled to the quick swap connections and configured to selectively enable or disable operation of each of the quick swap connections.

[0025] In some embodiments, the plurality of qubit modules includes a number (N) of qubit modules, each qubit module having an identification index ranging from 1 to N, and the plurality of quick swap connections includes:

[0026]

number

[0046] The method further includes a quick-swap connection coupling each pair of qubit modules having identification index values ​​i and j such that:

[0027] In some embodiments, the physical qubits are photonic qubits, and each quick-swap connection comprises an optical waveguide.

[0028] According to some embodiments, a system may include a plurality of qubit modules, each qubit module including circuitry configured to operate on a plurality of physical qubits to generate a topological code patch (e.g., a surface code patch) for a fault-tolerant logical qubit during each of a plurality of operating cycles, each topological code patch having a plurality of boundaries in entanglement space; and a plurality of port connections, each port connection selectively operable to couple a pair of qubit modules and perform a joint measurement operation on the physical qubits of the respective topological code patch generated in the pair of qubit modules during one code cycle, the port connection coupling each of the qubit modules to two or more other qubit modules.

[0029] In some embodiments, the port connections include at least one port connection coupling a pair of qubit modules that are not physically adjacent to one another.

[0030] In some embodiments, the port connections couple at least one of the qubit modules to six or more other qubit modules.

[0031] In some embodiments, the boundaries of each topological code patch are associated with different directions in entanglement space, and each port connection includes multiple separately controllable sub-connections, each sub-connection being associated with a different one of the directions in entanglement space, and each sub-connection coupling one of the boundaries of the topological code patch of a first qubit module of a pair to a corresponding one of the boundaries of the topological code patch of a second qubit module of the pair.

[0032] In some embodiments, the boundaries of the topologically coded patches include a first boundary associated with an input direction in entanglement space, and each sub-connection associated with the input direction laterally couples physical qubits between a first boundary of a first topologically coded patch of a first qubit module of the pair and a first boundary of a second topologically coded patch of a second qubit module of the pair.

[0033] In some embodiments, the lateral coupling of the physical qubits is operable to generate a Bell state between a first logical qubit in the first qubit module and a second logical qubit in the second qubit module.

[0034] In some embodiments, the boundary of each topologically coded patch includes a first boundary associated with an output direction in entanglement space, and each sub-connection associated with the output direction laterally couples physical qubits between a first boundary of a first topologically coded patch of a first qubit module of the pair and a first boundary of a second topologically coded patch of a second qubit module of the pair.

[0035] In some embodiments, the lateral coupling of physical qubits is operable to perform a Bell basis measurement on a first logical qubit in the first qubit module and a second logical qubit in the second qubit module.

[0036] In some embodiments, the system may further comprise classical control logic coupled to the port connections and configured to selectively enable or disable operation of each of the port connections.

[0037] In some embodiments, the plurality of qubit modules includes a number (N) of qubit modules, each qubit module having an identification index in the range of 1 to N, and the plurality of port connections includes a port connection coupling each pair of qubit modules such that 1≦|ij|≦r, where r is a range parameter, r is at least 2, and the port connections include at least one port connection coupling a pair of qubit modules that are not physically adjacent to one another. The range parameter r can be, for example, at least 6, at least 12, or another number.

[0038] In some embodiments, the system may further comprise a plurality of quick swap connections, each quick swap connection selectively operable to couple a pair of qubit modules and swap the fault-tolerant logic qubit from a first qubit module of the pair and a second qubit module of the pair within one code cycle, the quick swap connections coupling each of the qubit modules to two or more other qubit modules.

[0039] In some embodiments, the plurality of qubit modules comprises a number (N) of qubit modules, each qubit module having an identification index in the range of 1 to N, and the plurality of quick swap connections comprises:

[0040]

number

[0041] According to some embodiments, a method includes providing a plurality of qubit modules including a plurality of workspace qubit modules and a plurality of memory qubit modules, each qubit module including circuitry configured to operate on a plurality of physical qubits to generate a topological code patch (e.g., a surface code patch) for a fault-tolerant logical qubit during a code cycle; transferring a logical qubit from the memory qubit module to the workspace qubit module; and, during a logic cycle comprising a plurality of code cycles, providing a logic block network in the workspace qubit module, wherein for each of a plurality of logical blocks in the logic block network, transferring one of the workspace qubit modules to the workspace qubit module. executing a logic block network including generating a topological code patch (e.g., a surface code patch) in one workspace qubit module, where a first topological code patch is generated in a first workspace qubit module and a second topological code patch is generated in a second workspace qubit module, and the first workspace qubit module and the second workspace qubit module are non-adjacent modules; and performing a topological code check operator measurement between the first topological code patch and the second topological code patch using a port connection that directly couples physical qubits between the first workspace qubit module and the second workspace qubit module.

[0042] In some embodiments, a logic block network corresponds to a gate operation on one or more logical qubits.

[0043] In some embodiments, the method may further include performing one or more quick swap operations on the plurality of memory qubit modules during the logic cycle, each quick swap operation swapping a respective logical qubit between a pair of memory qubit modules within one code cycle.

[0044] In some embodiments, at least two logic block networks corresponding to successive gate operations in the quantum circuit are executed in different workspace qubit modules during a logic cycle. In some embodiments, the method may further include, prior to executing the logic block networks, initializing a Bell pair of logical qubits to a Bell state, where a first logical qubit of the Bell pair is initialized as a third topological code patch in a first one of the memory qubit modules and a second logical qubit of the Bell pair is initialized as a first topological code patch in the first one of the workspace qubit modules, and performing Bell basis measurements on the first and second logical qubits of the Bell pair after executing the plurality of logic blocks. In some embodiments, the method may further include performing one or more quick swap operations on the plurality of memory qubit modules during the logic cycle, each quick swap operation swapping a respective logical qubit between the pair of memory qubit modules within one code cycle. In some embodiments, performing the one or more quick swap operations on the plurality of memory qubit modules includes swapping a first logical qubit of the Bell pair from a first memory qubit module of the memory qubit modules to a second memory qubit module of the memory qubit modules, and the Bell basis measurement is performed between the first memory qubit module of the workspace qubit modules and the second memory qubit module of the memory qubit modules.

[0045] According to some embodiments, a method includes providing a plurality of qubit modules, the plurality of qubit modules including a plurality of workspace qubit modules and a plurality of memory qubit modules, each qubit module including circuitry configured to operate on a plurality of physical qubits to generate a topological code patch (e.g., a surface code patch) for a logical qubit during an operational cycle; storing a logical qubit in each of at least a subset of the memory qubit modules; performing, during a first code cycle, a first set of one or more quick swap operations between the memory qubit modules and the workspace qubit modules, wherein each quick swap operation in the first set of one or more quick swap operations swaps a current state in one of the workspace qubit modules with a logical qubit in one of the memory qubit modules; and performing, during a logic cycle comprising a plurality of code cycles, a first set of one or more quick swap operations between the memory qubit modules and the workspace qubit modules. executing a lock network, wherein executing the logic block network includes generating, for each of a plurality of logic blocks in the logic block network, a topological code patch in one of the workspace qubit modules, wherein a first topological code patch is generated in a first workspace qubit module and a second topological code patch is generated in a second workspace qubit module, the first workspace qubit module and the second workspace qubit module being non-adjacent modules; performing a topological code check operator measurement between the first topological code patch and the second topological code patch using a port connection that directly couples physical qubits between the first workspace qubit module and the second workspace qubit module; and performing a second set of quick swap operations on the plurality of memory qubit modules concurrently with executing the logic block network in the workspace qubit modules;performing a second set of quick swap operations, wherein each quick swap operation in the second set of one or more quick swap operations swaps a respective logical qubit between a pair of memory qubit modules in one code cycle, and wherein at least one of the quick swap operations in the second set of one or more quick swap operations swaps a respective logical qubit between a pair of non-adjacent memory qubit modules;

[0046] According to some embodiments, a circuit includes: a resource state interconnect having a plurality of output paths that output a resource state during each of a plurality of operating cycles, each resource state being a quantum system of a plurality of entangled physical qubits, with different physical qubits in the resource state being output on different ones of the output paths; a plurality of reconfigurable fusion circuits, each of the plurality of reconfigurable fusion circuits configured to receive two input physical qubits and selectively perform either a projected entangled measurement between the two input physical qubits or one of a plurality of single-qubit measurements on each of the two input physical qubits, thereby generating measurement result data; and a plurality of routing switches, each routing switch having an input path coupled to a respective one of the output paths of the resource state interconnect and a plurality of output routing paths selectably coupled to the input paths, and for each routing switch, The routing paths may comprise: a plurality of routing switches, the routing paths including a first local path, where the first local paths of different ones of the routing switches introduce different delays; a plurality of internal port routing paths; and a plurality of port forwarding paths exiting the circuit; a plurality of external port routing paths for receiving physical quantum bits from a plurality of external circuits, the plurality of reconfigurable fusion circuits including a plurality of local fusion circuits, each local fusion circuit coupled to a respective first local routing path of two routing switches of the routing switches; and a plurality of port fusion circuits, each port fusion circuit having a first input coupled to one of the internal port routing paths of one of the routing switches and a second input coupled to one of the external port routing paths.

[0047] In some embodiments, the circuit is one of multiple instances of the circuit, and for each routing switch, the port forwarding paths are coupled to external port routing paths of other instances of the circuit.

[0048] In some embodiments, each of the routing switches is associated with a different surface of a topological code patch (e.g., a surface code patch) for the fault-tolerant logical qubits, and the port fusion circuit operates on physical qubits from like surfaces of the different topological code patches.

[0049] In some embodiments, the plurality of local fusion circuits include a first local fusion circuit, a second local fusion circuit, and a third local fusion circuit, wherein one of the first local routing paths coupled to the first local fusion circuit introduces a delay of 1 operation cycle with respect to another of the first local routing paths coupled to the first local fusion circuit, one of the first local routing paths coupled to the second local fusion circuit introduces a delay of a number d operation cycles with respect to another of the first local routing paths coupled to the second local fusion circuit, the number d being a chord distance greater than 1, and one of the first local routing paths coupled to the third local fusion circuit introduces a delay of a number d operation cycles with respect to another of the first local routing paths coupled to the third local fusion circuit. 2 Introduce a delay in the operating cycle.

[0050] In some embodiments, the first local fusion circuit is coupled to a first local routing path of each of the first routing switch and the second routing switch, wherein the first local routing path of the first routing switch introduces a delay of one operating cycle, the plurality of output routing paths of each of the first routing switch and the second routing switch further includes a third local routing path, wherein the third local routing path of the first routing switch introduces a delay of two operating cycles relative to the third local routing path of the second routing switch, and the plurality of local fusion circuits further include a fourth local fusion circuit coupled to the third local routing path of the first routing switch and the second routing switch. In some embodiments, the third local fusion circuit is coupled to a first local routing path of each of the first routing switch and the second routing switch, wherein the first local routing path of the first routing switch introduces a delay of two operating cycles relative to the third local routing path of the second routing switch. 2 By introducing a delay in the operation cycle, the first routing switch has multiple output routing paths, 2 The second routing switch further includes a plurality of quick swap transfer paths that exit the circuit after a delay in the operating cycle, the plurality of output routing paths of the second routing switch further including a plurality of internal quick swap routing paths, the circuit further including a plurality of external quick swap routing paths that receive physical quantum bits from a plurality of external circuits, and the plurality of reconfigurable fused circuits further including a plurality of quick swap fused circuits, each quick swap fused circuit having a first input coupled to one of the internal quick swap routing paths and a second input coupled to one of the external quick swap routing paths.

[0051] In some embodiments, each of the plurality of reconfigurable fused circuits is configured such that the projected entanglement measurement operation includes a destructive measurement on both of the input qubits.

[0052] In some embodiments, each of the reconfigurable fusion circuits is configured such that the projected entanglement measurement is a Type II fusion operation that provides a joint XX measurement result and a joint ZZ measurement result.

[0053] In some embodiments, each of the reconfigurable fused circuits comprises a plurality of single qubit measurements, each of which comprises a Pauli X measurement, a Pauli Y measurement, a Pauli Z measurement, followed by a Pauli Z measurement. -iπ / 8 The phase rotation includes one or more of:

[0054] In some embodiments, the circuit may further comprise classical control logic coupled to the plurality of reconfigurable fused circuits and the plurality of routing switches, the classical control logic configured to select an output routing path for each of the plurality of routing switches and an operation for each of the plurality of reconfigurable fused circuits.

[0055] In some embodiments, the physical qubits of the resource states are photonic qubits. In some embodiments, the resource state interconnect includes a plurality of waveguides coupled between an external source of the resource states and an output path of the resource state interconnect.

[0056] According to some embodiments, a system may include a network of interleaving modules, each interleaving module having a resource state interconnect having a plurality of output paths for outputting a resource state during each of a plurality of operating cycles, each resource state being a quantum system of a plurality of entangled physical qubits, with different physical qubits in the resource state being output on different ones of the output paths; a plurality of reconfigurable fusion circuits, each of the plurality of reconfigurable fusion circuits configured to receive two input physical qubits and selectively perform either a projected entangled measurement between the two input physical qubits or one of a plurality of single-qubit measurements on each of the two input physical qubits, thereby generating measurement result data; and a plurality of routing switches, each routing switch having an input path coupled to a respective one of the output paths of the resource state interconnect and a plurality of output routing paths selectably coupled to the input paths, and a plurality of external port routing paths for receiving physical qubits from a plurality of other interleaving modules in the network, the plurality of reconfigurable fusion circuits including a plurality of local fusion circuits, each local fusion circuit coupled to a respective first local routing path of two routing switches of the routing switches; and a plurality of port fusion circuits, each port fusion circuit having a first input coupled to one of the internal port routing paths of one of the routing switches and a second input coupled to one of the external port routing paths.

[0057] In some embodiments, in each interleave module, each of the routing switches is associated with a different surface of a topological code patch (e.g., a surface code patch) for the fault-tolerant logical qubits, and the port fusion circuitry operates on physical qubits from like surfaces of the different topological code patches.

[0058] In some embodiments, in each interleaving module, the plurality of local fusion circuits include a first local fusion circuit, a second local fusion circuit, and a third local fusion circuit, wherein one of the first local routing paths coupled to the first local fusion circuit introduces a delay of 1 operation cycle with respect to another of the first local routing paths coupled to the first local fusion circuit, one of the first local routing paths coupled to the second local fusion circuit introduces a delay of a number d operation cycles with respect to another of the first local routing paths coupled to the second local fusion circuit, the number d being a code distance greater than 1, and one of the first local routing paths coupled to the third local fusion circuit introduces a delay of a number d operation cycles with respect to another of the first local routing paths coupled to the third local fusion circuit. 2 A delay of

[0059] In some embodiments, in each interleave module, a first local fusion circuit is coupled to a first local routing path of each of the first routing switch and the second routing switch, the first local routing path of the first routing switch introducing a delay of one operating cycle, the multiple output routing paths of each of the first routing switch and the second routing switch further including a third local routing path, the third local routing path of the first routing switch introducing a delay of two operating cycles relative to the third local routing path of the second routing switch, and the multiple local fusion circuits further including a fourth local fusion circuit coupled to the third local routing path of the first routing switch and the second routing switch.

[0060] In some embodiments, the plurality of local fusion circuits include a first local fusion circuit, a second local fusion circuit, and a third local fusion circuit, wherein one of the first local routing paths coupled to the first local fusion circuit introduces a delay of 1 operation cycle with respect to another of the first local routing paths coupled to the first local fusion circuit, one of the first local routing paths coupled to the second local fusion circuit introduces a delay of a number d operation cycles with respect to another of the first local routing paths coupled to the second local fusion circuit, the number d being a chord distance greater than 1, and one of the first local routing paths coupled to the third local fusion circuit introduces a delay of a number d operation cycles with respect to another of the first local routing paths coupled to the third local fusion circuit. 2 Introduce a delay of 1 operating cycle.

[0061] In some embodiments, in each interleave module, a first local fusion circuit is coupled to a first local routing path of each of the first routing switch and the second routing switch, the first local routing path of the first routing switch introducing a delay of one operating cycle, the multiple output routing paths of each of the first routing switch and the second routing switch further including a third local routing path, the third local routing path of the first routing switch introducing a delay of two operating cycles relative to the third local routing path of the second routing switch, and the multiple local fusion circuits further including a fourth local fusion circuit coupled to the third local routing path of the first routing switch and the second routing switch.

[0062] In some embodiments, in each interleaving module, the third local fusion circuit is coupled to a first local routing path of each of the first routing switch and the second routing switch, and the first local routing path of the first routing switch is 2 By introducing a delay in the operation cycle, the first routing switch has multiple output routing paths, 2 The second routing switch further includes a plurality of quick swap transfer paths that exit the circuit after a delay in the operating cycle, the plurality of output routing paths of the second routing switch further including a plurality of internal quick swap routing paths, the circuit further including a plurality of external quick swap routing paths that receive physical quantum bits from a plurality of external circuits, and the plurality of reconfigurable fused circuits further including a plurality of quick swap fused circuits, each quick swap fused circuit having a first input coupled to one of the internal quick swap routing paths and a second input coupled to one of the external quick swap routing paths.

[0063] In some embodiments, in each interleaving module, each of the plurality of reconfigurable fused circuits is configured such that the projected entanglement measurement operation includes a destructive measurement on both of the input qubits.

[0064] In some embodiments, in each interleaving module, each of the reconfigurable fusion circuits is a Type II fusion operation in which a projected entanglement measurement provides a joint XX measurement result and a joint ZZ measurement result, and multiple single qubit measurements are a Pauli X measurement, a Pauli Y measurement, and a Pauli Z measurement, followed by a Pauli Z measurement. -iπ / 8 is configured to include a phase rotation of

[0065] In some embodiments, the system may further comprise classical control logic coupled to the plurality of reconfigurable fused circuits and the plurality of routing switches in the interleaving module, the classical control logic configured to select an output routing path for each of the plurality of routing switches and an operation for each of the plurality of reconfigurable fused circuits. In some embodiments, the classical control logic is further configured to select an output routing path for each of the plurality of routing switches and an operation for each of the plurality of reconfigurable fused circuits based at least in part on a logic block network representing a quantum computation to be performed.

[0066] In some embodiments, the physical qubits of the resource states are photonic qubits. In some embodiments, the resource state interconnect includes a plurality of waveguides coupled between an external source of the resource states and an output path of the resource state interconnect.

[0067] According to some embodiments, a circuit includes: a resource state interconnect having a plurality of output paths that output a resource state during each of a plurality of operating cycles, each resource state being a quantum system of a plurality of entangled physical qubits, with different physical qubits in the resource state being output on different ones of the output paths; a plurality of reconfigurable fusion circuits, each of the plurality of reconfigurable fusion circuits configured to receive two input physical qubits and selectively perform either a projected entangled measurement between the two input physical qubits or one of a plurality of single-qubit measurements on each of the two input physical qubits, thereby generating measurement result data; and a plurality of routing switches, each routing switch having an input path coupled to a respective one of the output paths of the resource state interconnect and a plurality of output routing paths selectably coupled to the input paths, wherein for each routing switch, the plurality of output routing paths include a first local path and a second local path that is coupled to different ones of the routing switches. and a plurality of external quick swap routing paths that receive physical qubits from a plurality of external circuits, the plurality of reconfigurable fused circuits including a plurality of local fused circuits and a plurality of quick swap fused circuits, each local fused circuit coupled to a respective first local routing path of the two routing switches, each quick swap fused circuit having a first input coupled to one of the internal quick swap routing paths of the first routing switch and a second input coupled to one of the external quick swap routing paths.

[0068] In some embodiments, the circuit is one of multiple instances of the circuit, and for each routing switch, the quick swap forwarding path is coupled to the external quick swap routing paths of other instances of the circuit.

[0069] In some embodiments, each of the routing switches is associated with a different surface of a topological code patch (e.g., a surface code patch) for fault-tolerant logic qubits, and the quick swap fusion circuit operates on physical qubits from the top surface of one topological code patch and physical qubits from the bottom surface of another topological code patch.

[0070] In some embodiments, the circuit includes: a resource state interconnect having a plurality of output paths that output a resource state during each of a plurality of operating cycles, each resource state being a quantum system of a plurality of entangled physical qubits, with different physical qubits in the resource state being output on different ones of the output paths; a plurality of reconfigurable fusion circuits, each of the plurality of reconfigurable fusion circuits configured to receive two input physical qubits and selectively perform either a projected entangled measurement between the two input physical qubits or one of a plurality of single-qubit measurements on each of the two input physical qubits, thereby generating measurement result data; and a plurality of routing switches, each routing switch having an input path coupled to a respective one of the output paths of the resource state interconnect and a plurality of output routing paths selectably coupled to the input paths, and a plurality of external port routing paths for receiving physical qubits from a plurality of external circuits, wherein the plurality of reconfigurable fused circuits includes a plurality of local fused circuits, each local fused circuit coupled to a respective first local routing path of two routing switches of the routing switches, and a plurality of port fused circuits, each port fused circuit having a first input coupled to one of the internal port routing paths of one of the routing switches and a second input coupled to one of the external port routing paths, and wherein for a first routing switch of the routing switches, the plurality of output routing paths further include a plurality of internal quick swap routing paths, and for a second routing switch of the routing switches, the plurality of output routing paths further include a plurality of internal quick swap routing paths.and a plurality of external quick swap routing paths that receive physical qubits from a plurality of external circuits, wherein the plurality of reconfigurable fused circuits includes a plurality of local fused circuits, each local fused circuit coupled to a first local routing path of a respective one of the two routing switches, and a plurality of quick swap fused circuits, each quick swap fused circuit having a first input coupled to one of the internal quick swap routing paths of a first one of the routing switches and a second input coupled to one of the external quick swap routing paths.

[0071] In some embodiments, the circuit is one of multiple instances of the circuit, and for each routing switch, the port forwarding paths are coupled to external port routing paths of other instances of the circuit.

[0072] In some embodiments, each of the routing switches is associated with a different surface of a topological code patch (e.g., a surface code patch) for the fault-tolerant logical qubits, and the port fusion circuit operates on physical qubits from like surfaces of the different topological code patches.

[0073] In some embodiments, the plurality of local fusion circuits include a first local fusion circuit, a second local fusion circuit, and a third local fusion circuit, wherein one of the first local routing paths coupled to the first local fusion circuit introduces a delay of 1 operation cycle with respect to another of the first local routing paths coupled to the first local fusion circuit, one of the first local routing paths coupled to the second local fusion circuit introduces a delay of a number d operation cycles with respect to another of the first local routing paths coupled to the second local fusion circuit, the number d being a chord distance greater than 1, and one of the first local routing paths coupled to the third local fusion circuit introduces a delay of a number d operation cycles with respect to another of the first local routing paths coupled to the third local fusion circuit. 2 Introduce a delay in the operating cycle.

[0074] In some embodiments, the first local fusion circuit is coupled to a first local routing path of each of the first routing switch and the second routing switch, the first local routing path of the first routing switch introducing a delay of one operating cycle, the multiple output routing paths of each of the first routing switch and the second routing switch further including a third local routing path, the third local routing path of the first routing switch introducing a delay of two operating cycles relative to the third local routing path of the second routing switch, and the multiple local fusion circuits further including a fourth local fusion circuit coupled to the third local routing path of the first routing switch and the second routing switch.

[0075] In some embodiments, the third local fusion circuit is coupled to a first local routing path of each of the first routing switch and the second routing switch, and the first local routing path of the first routing switch is d 2 Introduces delays in the operation cycle, and multiple quick swap transfer paths 2Exits the circuit after a delay of the operating cycle.

[0076] In some embodiments, each of the plurality of reconfigurable fused circuits is configured such that the projected entanglement measurement operation includes a destructive measurement on both of the input qubits.

[0077] In some embodiments, each of the reconfigurable fusion circuits is configured such that the projected entanglement measurement is a Type II fusion operation that provides a joint XX measurement result and a joint ZZ measurement result.

[0078] In some embodiments, each of the reconfigurable fused circuits comprises a plurality of single qubit measurements, each of which comprises a Pauli X measurement, a Pauli Y measurement, a Pauli Z measurement, followed by a Pauli Z measurement. -iπ / 8 The phase rotation includes at least one of:

[0079] In some embodiments, the circuit may further comprise classical control logic coupled to the plurality of reconfigurable fused circuits and the plurality of routing switches, the classical control logic configured to select an output routing path for each of the plurality of routing switches and an operation for each of the plurality of reconfigurable fused circuits.

[0080] In some embodiments, the physical qubits of the resource states are photonic qubits. In some embodiments, the resource state interconnect includes a plurality of waveguides coupled between an external source of the resource states and an output path of the resource state interconnect.

[0081] According to some embodiments, a system may include a network of interleaving modules, each interleaving module having a resource state interconnect having a plurality of output paths for outputting a resource state during each of a plurality of operating cycles, each resource state being a quantum system of a plurality of entangled physical qubits, with different physical qubits in the resource state being output on different ones of the output paths; a plurality of reconfigurable fusion circuits, each of the plurality of reconfigurable fusion circuits configured to receive two input physical qubits and selectively perform either a projected entangled measurement between the two input physical qubits or one of a plurality of single-qubit measurements on each of the two input physical qubits, thereby generating measurement result data; and a plurality of routing switches, each routing switch having an input path coupled to a respective one of the output paths of the resource state interconnect and a plurality of output routing paths selectably coupled to the input paths, , the plurality of output routing paths may comprise a plurality of routing switches including a first local path, where first local paths of different ones of the routing switches introduce different delays, a plurality of internal port routing paths, and a plurality of port forwarding paths exiting the interleaving module; and a plurality of external port routing paths for receiving physical qubits from a plurality of other interleaving modules in the network, wherein the plurality of reconfigurable fusion circuits include a plurality of local fusion circuits, each local fusion circuit coupled to a respective first local routing path of two routing switches of the routing switches, and a plurality of port fusion circuits, each port fusion circuit having a first input coupled to one of the internal port routing paths of one of the routing switches and a second input coupled to one of the external port routing paths, and for a first routing switch of the routing switches:the plurality of output routing paths further include a plurality of internal quick swap routing paths, and for a second routing switch of the routing switches, the plurality of output routing paths further include a plurality of quick swap transfer paths exiting the circuit and a plurality of external quick swap routing paths receiving physical qubits from a plurality of external circuits, and the plurality of reconfigurable fused circuits include a plurality of local fused circuits, each local fused circuit coupled to a first local routing path of a respective one of the two routing switches, and a plurality of quick swap fused circuits, each quick swap fused circuit having a first input coupled to one of the internal quick swap routing paths of the first routing switch of the routing switches and a second input coupled to one of the external quick swap routing paths;

[0082] In some embodiments, in each interleave module, each of the routing switches is associated with a different surface of a topological code patch (e.g., a surface code patch) for the fault-tolerant logical qubits, and the port fusion circuitry operates on physical qubits from like surfaces of the different topological code patches.

[0083] In some embodiments, in each interleaving module, the plurality of local fusion circuits include a first local fusion circuit, a second local fusion circuit, and a third local fusion circuit, wherein one of the first local routing paths coupled to the first local fusion circuit introduces a delay of 1 operation cycle with respect to another of the first local routing paths coupled to the first local fusion circuit, one of the first local routing paths coupled to the second local fusion circuit introduces a delay of number d operation cycles with respect to another of the first local routing paths coupled to the second local fusion circuit, the number d being a code distance greater than 1, and one of the first local routing paths coupled to the third local fusion circuit introduces a delay of number d operation cycles with respect to another of the first local routing paths coupled to the third local fusion circuit. 2 Introduce a delay in the operating cycle.

[0084] In some embodiments, in each interleave module, a first local fusion circuit is coupled to a first local routing path of each of the first routing switch and the second routing switch, the first local routing path of the first routing switch introducing a delay of one operating cycle, the multiple output routing paths of each of the first routing switch and the second routing switch further including a third local routing path, the third local routing path of the first routing switch introducing a delay of two operating cycles relative to the third local routing path of the second routing switch, and the multiple local fusion circuits further including a fourth local fusion circuit coupled to the third local routing path of the first routing switch and the second routing switch.

[0085] In some embodiments, in each interleaving module, the third local fusion circuit is coupled to a first local routing path of each of the first routing switch and the second routing switch, and the first local routing path of the first routing switch is2 Introduces delays in the operation cycle, and multiple quick swap transfer paths 2 Exits the circuit after a delay of the operating cycle.

[0086] In some embodiments, in each interleaving module, each of the reconfigurable fusion circuits is configured such that the projected entanglement measurement is a Type II fusion operation that provides a joint XX measurement result and a joint ZZ measurement result, and each of the reconfigurable fusion circuits is configured such that the multiple single qubit measurements are a Pauli X measurement, a Pauli Y measurement, a Pauli Z measurement, followed by a Pauli Z measurement. -iπ / 8 The phase rotation includes at least one of:

[0087] In some embodiments, the system may further comprise classical control logic coupled to the plurality of reconfigurable fused circuits and the plurality of routing switches in the interleaving module, the classical control logic configured to select an output routing path for each of the plurality of routing switches and an operation for each of the plurality of reconfigurable fused circuits. In some embodiments, the classical control logic is further configured to select an output routing path for each of the plurality of routing switches and an operation for each of the plurality of reconfigurable fused circuits based at least in part on a logic block network representing a quantum computation to be performed.

[0088] In some embodiments, the physical qubits of the resource states are photonic qubits.

[0089] In some embodiments, the resource state interconnect includes a plurality of waveguides coupled between an external source of resource state and an output path of the resource state interconnect.

[0090] According to some embodiments, a method includes providing, to a classical computer system, a library of logic block networks corresponding to quantum subroutines, where each logic block network specifies a set of port connections between a plurality of logic blocks, each logic block corresponding to a topological code patch (e.g., a surface code patch) for a fault-tolerant logic qubit, and the port connections define a joint operation between the topological code patches; specifying, to the classical computer system, a quantum computation as a sequence of quantum subroutines to be executed; for each quantum subroutine in the sequence of quantum subroutines, determining, by the classical computer system, whether a logic block network corresponding to the quantum subroutine exists in the library; and in response to determining that a logic block network corresponding to the quantum subroutine exists in the library, retrieving, by the classical computer system, a logic block network from the library and adding the logic block network to an execution list. and in response to determining that a logic block network corresponding to the quantum subroutine does not exist in the library, generating, by the classical computer system, a new logic block network corresponding to the quantum subroutine and adding the new logic block network to the execution list; identifying, by the classical computer system, one or more additional logic block networks for generating auxiliary states to be used by the sequence of subroutines; inserting, by the classical computer system, the one or more additional logic block networks into the execution list; scheduling, by the classical computer system and based on the execution list, a sequence of logic cycles, each of the logic block networks from the execution list to be executed by a particular one of the plurality of workspace qubit modules in the quantum computer core during a particular one of the logic cycles, each logic cycle including a plurality of code cycles; and scheduling, by the classical computer system, a sequence of logic cycles.and scheduling one or more layers of quick swap operations to be performed by the plurality of memory qubit modules in the quantum computer core during one or more of the logical cycles based on the execution list, each layer of quick swap operations including one or more quick swaps between disjoint sets of memory qubit modules, each layer of quick swap operations completing within one code cycle; and scheduling additional layers of quick swap operations between the plurality of workspace qubit modules and the plurality of memory qubit modules in the quantum computer core to be performed during successive logical cycles in the sequence of logical cycles based on the execution list.

[0091] In some embodiments, scheduling the sequence of logic cycles includes determining that both the first logic block network and the second logic block network operate on the same input logical qubit; scheduling, during the first logic cycle, the first logic block network for execution on a first group of workspace qubit modules, the first group of workspace qubit modules including a first workspace qubit module that receives the input logical qubit; and scheduling, during the first logic cycle, the second group of workspace qubit modules including a second workspace qubit module that receives the input logical qubit. The method includes scheduling a second logic block network for execution in the second group of workspace qubit modules, the second group of workspace qubit modules including a second workspace qubit module that receives the input logical qubit; scheduling generation of a Bell pair of logical qubits before the first logic cycle such that a first logical qubit of the Bell pair is generated in the first memory qubit module and a second logical qubit of the Bell pair is generated in the second workspace qubit module; and scheduling a Bell measurement between the first logical qubit of the Bell pair and the output logical qubit of the first logic block network after the first logic cycle. In some embodiments, the Bell measurement is scheduled between the first memory qubit module and the first workspace qubit module. In some embodiments, the Bell measurement is scheduled between the first memory qubit module and a third workspace qubit module from the first group of workspace qubit modules.

[0092] In some embodiments, scheduling one or more layers of quick swap operations includes scheduling one or more quick swap operations that move a first logical qubit of a Bell pair from a first memory qubit module to a second memory qubit module.

[0093] In some embodiments, scheduling the sequence of logic cycles includes determining that a first logic block network generates an output logic qubit that is an input qubit of a second logic block network; scheduling a first logic block network for execution on a first group of workspace qubit modules during a first logic cycle, the first group of workspace qubit modules including a first workspace qubit module that generates an output logical qubit; and scheduling a second logic block network for execution on a second group of workspace qubit modules during a second logic cycle, the second group of workspace qubit modules including a second workspace qubit module that receives an input logical qubit; scheduling the generation of a Bell pair during a first logic cycle such that a second logical qubit of the Bell pair is generated in one memory qubit module and a second logical qubit of the Bell pair is generated in a second memory qubit module; scheduling one or more quick swap operations during the first logic cycle to move the first logical qubit of the Bell pair from the first memory qubit module to a third memory qubit module; scheduling a Bell measurement between the second logical qubit of the Bell pair and an output logical qubit from the first workspace module after the first logic cycle; and scheduling a quick swap operation between the third memory qubit module and the second workspace qubit module after the Bell measurement and before the second logic cycle.

[0094] In some embodiments, the method may further include scheduling, by the classical computer system, one or more measurement operations based on the execution list to remove each auxiliary state from the memory qubit module after the auxiliary state has been used in the subroutine.

[0095] In some embodiments, the measurement operation includes a reactive measurement operation, and after being used in the subroutine, each auxiliary state is maintained in the memory qubit module for at least a sufficient reaction time to allow decoding of output data from a previously executed logic block.

[0096] In some embodiments, the quantum subroutine specifies a unitary transform operation on one or more logical qubits, and generating a new logic block network corresponding to the quantum subroutine includes converting the unitary transform operation into a sequence of Pauli product rotations and Clifford gates that operate on all of the logical qubits, and converting the Pauli product rotations and Clifford gates into a logic block network.

[0097] In some embodiments, generating a new logic block network corresponding to a quantum subroutine includes defining the quantum subroutine as a ZX diagram including one or more spiders; optimizing the ZX diagram; and converting the optimized ZX diagram into a logic block network. In some embodiments, optimizing the ZX diagram includes splitting or merging spiders until the number of input ports of each spider is between 0 and 4, the number of output ports of each spider is between 0 and 4, and the total number of input and output ports of each spider is between 2 and 4; and The method includes defining an entanglement space having a first axis, a second axis, and a third axis; assigning each uncoupled input port to a first direction along the first axis and each uncoupled output port to a second direction along the first axis, the second direction being opposite to the first direction; assigning each port coupling between spiders to one or the other of the second or third axis; determining an orientation of each spider; and adding zero or more additional spiders based on the orientation of each spider and the Z-type or X-type of each spider to satisfy an equality constraint. In some embodiments, the quantum subroutine is specified as a unitary transformation operation, and defining the quantum subroutine as a ZX diagram includes converting the unitary transformation operation to a ZX diagram. In some embodiments, the quantum subroutine is specified as a reversible circuit, and defining the quantum subroutine as a ZX diagram includes converting the reversible circuit to a ZX diagram.

[0098] In some embodiments, the method may further include executing a sequence of logical cycles in a quantum computer core having a plurality of qubit modules, a plurality of port connections between pairs of qubit modules, and a plurality of quick-swap connections between pairs of qubit modules, wherein executing the sequence of logical cycles includes generating, in at least some of the qubit modules, a respective topological code patch for a fault-tolerant logical qubit during each of a plurality of code cycles within the logical cycle; operating at least one of the port connections between at least one pair of qubit modules to perform, within one code cycle, a joint measurement operation on the physical qubit of each topological code patch generated in the pair of qubit modules, the port connection operated according to a scheduled logic block network; and operating at least one of the quick-swap connections between at least one pair of qubit modules to swap a respective logical qubit between the pair of qubit modules within one code cycle, the quick-swap connection operated according to a scheduled layer of quick-swap operations.

[0099] In some embodiments, a classical computer system includes: a storage device for storing a library of logic block networks corresponding to quantum subroutines, each logic block network specifying a set of port connections between a plurality of logic blocks, each logic block corresponding to a topological code patch (e.g., a surface code patch) for a fault-tolerant logic qubit, the port connections defining a joint operation between the topological code patches; and a processor, coupled to the storage device, receiving an input specifying a quantum computation as a sequence of quantum subroutines to be executed; for each quantum subroutine in the sequence of quantum subroutines, determining whether a logic block network corresponding to the quantum subroutine exists in the library; and, in response to determining that a logic block network corresponding to the quantum subroutine exists in the library, retrieving a logic block network from the library and adding the logic block network to an execution list; and, in response to determining that a logic block network corresponding to the quantum subroutine does not exist in the library, retrieving a logic block network from the library and adding the logic block network to an execution list. generating a new logic block network corresponding to the quantum subroutine and adding the new logic block network to the execution list in response to generating one or more additional logic block networks for generating auxiliary states to be used by the sequence of subroutines and inserting the one or more additional logic block networks into the execution list; scheduling, based on the execution list, a sequence of logic cycles, wherein each of the logic block networks from the execution list is to be executed by a particular one of the plurality of workspace qubit modules in the quantum computer core during a particular one of the logic cycles, each logic cycle comprising a plurality of code cycles; scheduling, based on the execution list, one or more layers of quick swap operations to be performed by the plurality of memory qubit modules in the quantum computer core during one or more of the logic cycles, wherein each layer of quick swap operations comprises one or more quick swaps between disjoint sets of memory qubit modules;The processor may include a processor configured to schedule one or more layers of quick swap operations, each layer of quick swap operation completing within one code cycle, and to schedule additional layers of quick swap operations between the plurality of workspace qubit modules and the plurality of memory qubit modules in the quantum computer core to be executed between successive logic cycles in the sequence of logic cycles based on the execution list.

[0100] In some embodiments, the processor determines that scheduling a sequence of logic cycles includes determining that both a first logic block network and a second logic block network operate on the same input logical qubit; scheduling, during the first logic cycle, a first logic block network for execution on a first group of workspace qubit modules, the first group of workspace qubit modules including a first workspace qubit module that receives the input logical qubit; and scheduling, during the first logic cycle, a second group of workspace qubit modules including a second workspace qubit module that receives the input logical qubit. The second group of workspace qubit modules is further configured to schedule a second logic block network for execution in the second group of workspace qubit modules, including a second workspace qubit module that receives the input logical qubit; schedule generation of a Bell pair of logical qubits before the first logic cycle, such that a first logical qubit of the Bell pair is generated in the first memory qubit module and a second logical qubit of the Bell pair is generated in the second workspace qubit module; and schedule a Bell measurement between the first logical qubit of the Bell pair and the output logical qubit of the first logic block network after the first logic cycle.

[0101] In some embodiments, the processor further determines that scheduling the sequence of logic cycles causes a first logic block network to generate an output logical qubit that is an input qubit of a second logic block network; during the first logic cycle, schedules the first logic block network for execution on a first group of workspace qubit modules, the first group of workspace qubit modules including a first workspace qubit module that generates the output logical qubit; and during the second logic cycle, schedules the first logic block network for execution on a second group of workspace qubit modules, the second group of workspace qubit modules including a second workspace qubit module that receives the input logical qubit. scheduling the generation of the Bell pair during the first logic cycle such that a first logical qubit of the Bell pair of logical qubits is generated in the first memory qubit module and a second logical qubit of the Bell pair is generated in the second memory qubit module; scheduling one or more quick swap operations during the first logic cycle to move the first logical qubit of the Bell pair from the first memory qubit module to a third memory qubit module; scheduling a Bell measurement between the second logical qubit of the Bell pair and the output logical qubit from the first workspace module after the first logic cycle; and scheduling a quick swap operation between the third memory qubit module and the second workspace qubit module after the Bell measurement but before the second logic cycle.

[0102] In some embodiments, the processor is further configured to schedule, based on the execution list, one or more measurement operations to remove each auxiliary state from the memory qubit module after the auxiliary state has been used in the subroutine.

[0103] In some embodiments, the measurement operations include reactive measurement operations, and the processor is further configured to schedule the reactive measurement operations such that, after being used in a subroutine, each auxiliary state is maintained in the memory qubit module for at least a sufficient reaction time to allow decoding of output data from a previously executed logic block.

[0104] In some embodiments, the quantum subroutine specifies a unitary transform operation on one or more logical qubits, and the processor is further configured such that generating the new logic block network corresponding to the quantum subroutine includes converting the unitary transform operation into a sequence of Pauli product rotations and Clifford gates that operate on all of the logical qubits, and converting the Pauli product rotations and Clifford gates into the logic block network.

[0105] According to some embodiments, a system may include a network of interleaving modules, each interleaving module having a resource state interconnect having a plurality of output paths for outputting a resource state during each of a plurality of operating cycles, each resource state being a quantum system of a plurality of entangled physical qubits, with different physical qubits in the resource state being output on different ones of the output paths; a plurality of reconfigurable fusion circuits, each of the plurality of reconfigurable fusion circuits configured to receive two input physical qubits and selectively perform either a projected entangled measurement between the two input physical qubits or one of a plurality of single-qubit measurements on each of the two input physical qubits, thereby generating measurement result data; and a plurality of routing switches, each routing switch having an input path coupled to a respective one of the output paths of the resource state interconnect and a plurality of output routing paths selectably coupled to the input paths, and for each routing switch, a plurality of routing switches, the routing paths including: first local routing paths, where the first local routing paths of different ones of the routing switches introduce different delays; second local routing paths; and a set of port routing paths including a number r of routing paths, where the number r is greater than 1; a plurality of port input switches, each port input switch having r inputs coupled to respective port routing paths and output paths of the number r other interleaved modules; the plurality of reconfigurable fusion circuits including a plurality of local fusion circuits, each local fusion circuit coupled to a respective first local routing path of two of the routing switches; and a plurality of port fusion circuits, each port fusion circuit coupled to a second local routing path of a respective one of the routing switches and to an output path of a respective one of the port input switches;and a plurality of port input switches including: classical control logic coupled to the network of interleaved modules and configured to control the routing switch and the reconfigurable fused circuit and to receive classical data signals representing measurement result data from the reconfigurable fused circuit.

[0106] In some embodiments, each of the reconfigurable fused circuits is configured such that the plurality of single-qubit measurements includes a Pauli X measurement, a Pauli Y measurement, and a Pauli Z measurement.

[0107] In some embodiments, each of the reconfigurable fused circuits may include a plurality of single qubit measurements followed by a Pauli Z measurement. -iπ / 8 and a phase rotation of

[0108] In some embodiments, the classical control logic is further configured to determine a sequence of control settings for the routing switches and the reconfigurable fused circuit based at least in part on a fused graph representing the quantum computation to be performed.

[0109] In some embodiments, the system may further comprise a plurality of resource state generator circuits for generating resource states and providing the resource states to the resource state interconnects of the interleaving modules.

[0110] In some embodiments, the physical qubits of the resource states are photonic qubits. In some embodiments, the resource state interconnect within each interleaving module includes a plurality of waveguides coupled between an external source of the resource state and an output path of the resource state interconnect.

[0111] According to some embodiments, a method can include initializing a first qubit and a second qubit to a Bell state; performing a first gate on a first set of qubits using a first group of interconnected qubit modules, the first set of qubits including the first qubit; performing a second gate on a second set of qubits using a second group of interconnected qubit modules, the second set of qubits including a third qubit, the first quantum gate and the second quantum gate being performed in parallel, and the first set of qubits and the second set of qubits being disjoint sets; and performing a Bell basis measurement on the second set of qubits and the third set of qubits after performing the first quantum gate and the second quantum gate.

[0112] In some embodiments, the second qubit is not in either the first set or the second set.

[0113] In some embodiments, each of the qubits is a topologically encoded logical qubit, which may be, for example, a surface encoded logical qubit.

[0114] In some embodiments, each of the qubits is a topologically encoded (e.g., surface encoded) logical qubit stored in one of the qubit modules. Executing the first gate includes operating port connections in a first group of interconnected qubit modules to couple the topologically encoded logical qubits, and executing the second gate includes operating port connections in a second group of interconnected qubit modules to couple the topologically encoded logical qubits. In some embodiments, the topological code is a surface code.

[0115] The following detailed description, taken in conjunction with the accompanying drawings, provides a better understanding of the nature and advantages of the claimed invention. [Brief explanation of the drawings]

[0116] [Figure 1] 1 shows two representations of a portion of a pair of waveguides corresponding to a double-rail encoded photonic qubit. [Figure 2A] A schematic diagram of the coupling of the two modes is shown. [Figure 2B] 1 illustrates, in schematic form, a physical implementation of mode coupling in a photonic system that may be used in some embodiments. [Figure 3A] 1 illustrates, in schematic form, an example physical implementation of a Mach-Zehnder Interferometer (MZI) configuration that may be used in some embodiments. [Figure 3B] 1 illustrates, in schematic form, an example physical implementation of a Mach-Zehnder Interferometer (MZI) configuration that may be used in some embodiments. [Figure 4A] 1 shows another schematic diagram of the coupling of two modes. [Figure 4B] 4B illustrates, in schematic form, a physical implementation of the mode coupling of FIG. 4A in a photonic system that can be used in some embodiments. [Figure 5] 1 illustrates a four-mode coupling scheme that implements a "spreader" or "mode information erasure" transformation for the four modes, according to some embodiments. [Figure 6] 6 illustrates an exemplary optical device capable of implementing the four-mode modal diffusion conversion shown schematically in FIG. 5, according to some embodiments. [Figure 7] FIG. 1 shows a circuit diagram of a dual-rail coded Bell state generator that can be used in some embodiments. [Figure 8A] FIG. 1 illustrates a circuit diagram of a dual-rail coded Type I fused gate that can be used in some embodiments. [Figure 8B] 8B illustrates an exemplary result of a Type I fusion operation using the gates of FIG. 8A. [Figure 9A] FIG. 1 illustrates a circuit diagram of a dual-rail coded Type II fused gate that can be used in some embodiments. [Figure 9B] 9B illustrates an exemplary result of a Type II fusion operation using the gates of FIG. 9A. [Figure 10] 1 illustrates an example of a qubit entanglement system according to some embodiments. [Figure 11A] Figures 11A and 11B show examples of surface code implementations for logical qubits. Figure 11A shows a physical qubit, and Figures 11B and 11C show an entanglement system for the physical qubit that provides a surface code that can be used for error correction. Figures 11D-11F show circuits that implement stabilizer measurements for the surface codes of Figures 11B and 11C. Figures 11G and 11H show graphical representations of identity gates applied to logical qubits. [Figure 11B] Figures 11A and 11B show examples of surface code implementations for logical qubits. Figure 11A shows a physical qubit, and Figures 11B and 11C show an entanglement system for the physical qubit that provides a surface code that can be used for error correction. Figures 11D-11F show circuits that implement stabilizer measurements for the surface codes of Figures 11B and 11C. Figures 11G and 11H show graphical representations of identity gates applied to logical qubits. [Figure 11C] Figures 11A and 11B show examples of surface code implementations for logical qubits. Figure 11A shows a physical qubit, and Figures 11B and 11C show an entanglement system for the physical qubit that provides a surface code that can be used for error correction. Figures 11D-11F show circuits that implement stabilizer measurements for the surface codes of Figures 11B and 11C. Figures 11G and 11H show graphical representations of identity gates applied to logical qubits. [Figure 11D]Figures 11A and 11B show examples of surface code implementations for logical qubits. Figure 11A shows a physical qubit, and Figures 11B and 11C show an entanglement system for the physical qubit that provides a surface code that can be used for error correction. Figures 11D-11F show circuits that implement stabilizer measurements for the surface codes of Figures 11B and 11C. Figures 11G and 11H show graphical representations of identity gates applied to logical qubits. [Figure 11E] Figures 11A and 11B show examples of surface code implementations for logical qubits. Figure 11A shows a physical qubit, and Figures 11B and 11C show an entanglement system for the physical qubit that provides a surface code that can be used for error correction. Figures 11D-11F show circuits that implement stabilizer measurements for the surface codes of Figures 11B and 11C. Figures 11G and 11H show graphical representations of identity gates applied to logical qubits. [Figure 11F] Figures 11A and 11B show examples of surface code implementations for logical qubits. Figure 11A shows a physical qubit, and Figures 11B and 11C show an entanglement system for the physical qubit that provides a surface code that can be used for error correction. Figures 11D-11F show circuits that implement stabilizer measurements for the surface codes of Figures 11B and 11C. Figures 11G and 11H show graphical representations of identity gates applied to logical qubits. [Figure 11G] Figures 11A and 11B show examples of surface code implementations for logical qubits. Figure 11A shows a physical qubit, and Figures 11B and 11C show an entanglement system for the physical qubit that provides a surface code that can be used for error correction. Figures 11D-11F show circuits that implement stabilizer measurements for the surface codes of Figures 11B and 11C. Figures 11G and 11H show graphical representations of identity gates applied to logical qubits. [Figure 11H]Figures 11A and 11B show examples of surface code implementations for logical qubits. Figure 11A shows a physical qubit, and Figures 11B and 11C show an entanglement system for the physical qubit that provides a surface code that can be used for error correction. Figures 11D-11F show circuits that implement stabilizer measurements for the surface codes of Figures 11B and 11C. Figures 11G and 11H show graphical representations of identity gates applied to logical qubits. [Figure 12] 1 illustrates a graphical representation of resource states that may be used in fusion-based quantum computing, according to some embodiments. [Figure 13A] 1 illustrates an example of a fused graph that may be used in some embodiments. [Figure 13B] We show examples of how fused graphs (shown in Figure 13D) can be generated from surface code space-time diagrams (shown in Figure 13B) and time slice diagrams (shown in Figure 13C) for various logical operations on logical qubits. [Figure 13C] We show examples of how fused graphs (shown in Figure 13D) can be generated from surface code space-time diagrams (shown in Figure 13B) and time slice diagrams (shown in Figure 13C) for various logical operations on logical qubits. [Figure 13D] We show examples of how fused graphs (shown in Figure 13D) can be generated from surface code space-time diagrams (shown in Figure 13B) and time slice diagrams (shown in Figure 13C) for various logical operations on logical qubits. [Figure 13E] A legend for the fusion graph notation used in Figure 13D is shown. [Figure 14] A schematic diagram of a quantum circuit is shown. [Figure 15] FIG. 1 shows a simplified block diagram of an active volume quantum computer system according to some embodiments. [Figure 16] 1 illustrates example port connections for a representative qubit module of an active volume quantum computer system, according to some embodiments. [Figure 17]FIG. 1 illustrates a surface code level view of a portion of an active volume quantum computer system in operation, according to some embodiments. [Figure 18] 1 illustrates an example of a quick-swap connection for a representative qubit module of an active volume quantum computer system, according to some embodiments. [Figure 19] FIG. 1 illustrates a surface code level view of a portion of an active volume quantum computer system in operation, according to some embodiments. [Figure 20A] 10A-10C illustrate example space-time diagrams for 4-port, 3-port, and 2-port logic blocks that may be used in some embodiments. [Figure 20B] 10A-10C illustrate example space-time diagrams for 4-port, 3-port, and 2-port logic blocks that may be used in some embodiments. [Figure 20C] 10A-10C illustrate example space-time diagrams for 4-port, 3-port, and 2-port logic blocks that may be used in some embodiments. [Figure 20D] 10A-10C illustrate example space-time diagrams for 4-port, 3-port, and 2-port logic blocks that may be used in some embodiments. [Figure 20E] 1 illustrates an example of a logic block corresponding to an identity gate that may be used in some embodiments. [Figure 21A] 1 illustrates the relationship between a space-time diagram and a logical block network, according to some embodiments. [Figure 21B] 1 illustrates the relationship between a space-time diagram and a logical block network, according to some embodiments. [Figure 21C] 1 illustrates the relationship between a space-time diagram and a logical block network, according to some embodiments. [Figure 21D] 1 illustrates the relationship between a space-time diagram and a logical block network, according to some embodiments. [Figure 22A] 1 illustrates a ZX diagram that can be used in some embodiments. [Figure 22B] 1 illustrates a ZX diagram that can be used in some embodiments. [Figure 22C] 1 illustrates a ZX diagram that can be used in some embodiments. [Figure 22D] 1 illustrates a ZX diagram that can be used in some embodiments. [Figure 22E] 1 illustrates a ZX diagram that can be used in some embodiments. [Figure 23] 1 illustrates a process for converting a CNOT gate into a logic block network, according to some embodiments. [Figure 24] 1 illustrates the conversion of a single-qubit Hadamard gate into a logic block network, according to some embodiments. [Figure 25] Two-qubit according to some embodiments

[0117]

number

[0118] Disclosed herein are example systems and methods (also referred to as "embodiments") for performing operations on ensembles of qubits based on various physical quantum systems, including photonic systems. Such embodiments may be used, for example, in quantum computing as well as other contexts that utilize quantum entanglement (e.g., quantum communication). To facilitate understanding of this disclosure, an overview of relevant concepts and terminology is provided in Section 1. Active volume architectures for quantum computers are described in Section 2. Exemplary implementations of active volume architectures using photonic qubits and fusion-based quantum computing (FBQC), as well as quantum computer systems using photonic qubits and fusion, are described in Sections 3 and 4.

[0119] 1. Overview of quantum computing Quantum computing relies on the dynamics of quantum objects, such as photons, electrons, atoms, ions, molecules, nanostructures, etc., which follow the rules of quantum theory. In quantum theory, the quantum state of a quantum object is described by a set of physical properties, the complete set of which is called a mode. In some embodiments, a mode is defined by specifying the value (or distribution of values) of one or more properties of the quantum object. For example, if the quantum object is a photon, the mode can be defined by the frequency of the photon, the position in space of the photon (e.g., the waveguide or superposition of waveguides through which the photon is propagating), the associated propagation direction (e.g., the k-vector of the photon in free space), the polarization state of the photon (e.g., the direction (horizontal or vertical) of the electric and / or magnetic fields of the photon), the time window through which the photon is propagating, the orbital angular momentum state of the photon, etc.

[0120] For photons propagating in a waveguide, it is convenient to represent the state of the photon as one of a set of discrete spatiotemporal modes. For example, the photon's spatial mode k i is determined according to one of a finite set of discrete waveguides through which the photon is propagating, and the time mode t j is determined by one of a set of discrete time periods (referred to herein as "bins") in which a photon exists. In some photonic implementations, the degree of time discretization may be provided by a pulsed laser that generates the photons. The following examples use spatial modes primarily to avoid complicating the explanation. However, those skilled in the art will understand that the systems and methods may be applied to any type of mode, e.g., time mode, polarization mode, and any other mode or set of modes that serve to specify a quantum state. Furthermore, the following description describes an embodiment that uses a photonic waveguide to define the spatial mode of the photons. However, those skilled in the art with access to this disclosure will understand that other types of modes, e.g., time mode, energy state, etc., may be used without departing from the scope of the present disclosure. Additionally, those skilled in the art will be able to implement examples using other types of quantum systems, including, but not limited to, other types of photonic systems.

[0121] In a quantum system of multiple indistinguishable particles, it is useful to describe the quantum state of the many-body system as a whole using a Fock state formalism (sometimes called an occupation number representation) rather than describing the quantum state of each particle in the system. In a Fock state description, the many-body quantum state is specified by how many particles are present in each mode of the system. For example, the multi-mode, two-particle Fock state |1001〉 1,2,3,4specifies a quantum state of two particles, with one particle in mode 1, zero in mode 2, zero in mode 3, and one in mode 4. Again, as introduced above, the modes can be any property of the quantum object. In the case of photons, any two modes of the electromagnetic field can be used, and systems can be designed to use modes associated with degrees of freedom that can be passively manipulated using linear optics, for example. For example, polarization, spatial degrees of freedom, or angular momentum can be used. A four-mode system represented by a two-particle Fock state |1001〉 1,2,3,4 It can be physically implemented as four separate waveguides, two of which have one photon traveling through them. Another example of a state in a many-body quantum system is the four-particle Fock state |1111〉, which represents each mode occupied by one particle. 1,2,3,4 and a four-particle Fock state |2200〉, which represents modes 1 and 2 occupied by two particles, respectively, and modes 3 and 4 occupied by zero particle. 1,2,3,4 For modes in which no particles are present, the term "vacuum mode" is used. For example, the four-particle Fock state |2200〉 1,2,3,4 In this case, modes 3 and 4 are referred to herein as "vacuum modes". Fock states with a single occupied mode can be represented in abbreviation using a subscript to identify the occupied mode, e.g., |0010> 1,2,3,4 is equivalent to |13〉.

[0122] 1.1. Qubit As used herein, a "qubit" (or quantum bit) is a quantum system having an associated quantum state that can be used to encode information. Quantum state space can be modeled as a (complex) two-dimensional vector space, and if one dimension in the vector space is mapped to a logical value of 0 and the other dimension is mapped to a logical value of 1, then a quantum state can be used to encode one bit of information. In contrast to classical bits, quantum bits can have states that are superpositions of the logical values ​​0 and 1. More generally, a "qudit" can be any quantum system with a quantum state space that can be modeled as a (complex) n-dimensional vector space (for any integer n) that can be used to encode n bits of information. For clarity of exposition, the term "qubit" is used herein, although in some embodiments, systems can also use quantum information carriers that encode information in a manner not necessarily associated with binary bits, such as qudits. Qubits (or qudits) can be implemented in a variety of quantum systems. Examples of qubits include the polarization state of a photon, the presence of a photon in a waveguide, or the energy state of a molecule, atom, ion, nucleus, or photon. Other examples include flux qubits, phase qubits, or other engineered quantum systems such as charge qubits (e.g., formed from superconducting Josephson junctions), topological qubits (e.g., Majornaferms), or spin qubits formed from vacancy centers (e.g., nitrogen vacancies in diamond).

[0123] A qubit can be "dual-rail encoded," such that the logical value of the qubit is encoded by occupying one of two modes of the quantum system. For example, the logical values ​​0 and 1 can be encoded as follows:

[0124]

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[0125] 1.2. Entangled state Many of the advantages of quantum computing over "classical" computing (e.g., conventional digital computers using binary logic) come from the ability to generate entangled states of multi-qubit systems. In mathematical terms, the state |ψ〉 of n quantum objects is

[0126]

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[0127]

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[0128] More generally, an n-qubit Greenberger-Horne-Zeilinger (GHZ) state (or "n-GHZ state") is an entangled quantum state of n qubits. For a given orthonormal logical basis, an n-GHZ state is a quantum superposition of all qubits in a first basis state with all qubits in a second basis state.

[0129]

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[0130]

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[0131] 1.3. Physical Implementation Qubits (and operations on qubits) can be implemented using a variety of physical systems. In some examples described herein, qubits are provided in integrated photonic systems using waveguides, beam splitters, photonic switches, and single-photon detectors, and the modes that can be occupied by photons are spatiotemporal modes corresponding to the presence of photons in the waveguides. Modes can be coupled using mode couplers, e.g., optical beam splitters, to implement transformation operations, and measurement operations can be implemented by coupling single-photon detectors to specific waveguides. Those skilled in the art with access to this disclosure will understand that modes defined by any appropriate set of degrees of freedom, e.g., polarization modes, temporal modes, etc., can be used without departing from the scope of this disclosure. For example, in the case of modes that differ only in polarization (e.g., horizontal (H) and vertical (V)), the mode coupler can be any optical element that coherently rotates polarization, e.g., a birefringent material such as a wave plate. In other systems, such as ion trap systems or neutral atom systems, the mode coupler can be any physical mechanism capable of coupling two modes, for example, a pulsed electromagnetic field tuned to couple two internal states of the atoms / ions.

[0132] In some embodiments of a photonic quantum computing system using dual-rail encoding, a qubit may be implemented using a pair of waveguides. Figure 1 shows two representations (100, 100') of a portion of a pair of waveguides 102, 104 that can be used to provide a dual-rail encoded photonic qubit. In 100, a photon 106 is in waveguide 102 and no photons are in waveguide 104 (also called the vacuum mode), which in some embodiments represents the photonic qubit |0> L At 100′, photon 108 is in waveguide 104 and there are no photons in waveguide 102, which in some embodiments corresponds to the state of photonic qubit |1〉 Lcorresponds to a state of . To prepare a photonic qubit in a known logical state, a photon source (not shown) can be coupled to one end of one of the waveguides. The photon source can be operated to emit a single photon into the waveguide to which it is coupled, thereby preparing the photonic qubit in a known state. The photon travels through the waveguides, and by periodically operating the photon source, a quantum system can be generated in the same waveguide pair having qubits whose logical states map to different time modes of the photonic system. In addition, by providing multiple pairs of waveguides, a quantum system can be created having qubits whose logical states correspond to different spatiotemporal modes. It should be understood that the waveguides in such a system need not have a particular spatial relationship to one another. For example, they may be arranged in parallel, but need not be.

[0133] Occupied modes can be generated by using a photon source to generate photons, which then propagate through the desired waveguide. The photon source can be, for example, a cavity-based source that emits photon pairs, also known as a herald single-photon source. In one example of such a source, the source is driven by a pump, e.g., optical pulses, coupled to a system of optical resonators that can generate photon pairs via a nonlinear optical process (e.g., spontaneous four-wave mixing (SFWM), spontaneous parametric down-conversion (SPDC), second harmonic generation, etc.). Many different types of photon sources can be used. An example of a photon pair source can include a microring-based spontaneous four-wave mixing (SPFW) herald photon source (HPS). However, the exact type of photon source used is not critical, and any type of nonlinear source using any process, such as SPFW, SPDC, or any other process, can be used. Other classes of sources that do not necessarily require nonlinear materials, such as quantum dot sources, sources using atoms and / or artificial atomic systems such as color centers in crystals, can also be used. In some cases, the source may or may not be coupled to a photonic cavity, as is the case for artificial atomic systems such as quantum dots coupled to a cavity. Other types of photon sources also exist for SPWM and SPDC, such as optomechanical systems.

[0134] In such cases, the operation of the photon source may be non-deterministic (sometimes referred to as "stochastic"), such that a given pump pulse may or may not produce a photon pair. In some embodiments, coherent spatial and / or temporal multiplexing of several non-deterministic sources (referred to herein as "active" multiplexing) can be used to ensure that the probability of one mode being occupied during a given cycle approaches unity. Those skilled in the art will appreciate that many different active multiplexing architectures incorporating spatial and / or temporal multiplexing are possible. For example, active multiplexing schemes using log trees, generalized Mach-Zehnder interferometers, multimode interferometers, chained light sources, chained light sources with dump-the-pump schemes, asymmetric polycrystalline single-photon sources, or any other type of active multiplexing architecture can be used. In some embodiments, the photon source can employ active multiplexing schemes involving quantum feedback control, etc.

[0135] The measurement operation can be implemented by coupling the waveguide to a single-photon detector that generates a classical signal (e.g., a digital logic signal) indicating that a photon has been detected by the detector. Any type of photodetector that is sensitive to single photons can be used. In some embodiments, the detection of a photon (e.g., at the output end of the waveguide) can indicate an occupied mode, and the absence of a detected photon can indicate an unoccupied mode.

[0136] Some embodiments described below relate to physical implementations of unitary transformation operations that couple modes of a quantum system, which can be understood as transforming the quantum state of the system. For example, if the initial state of the quantum system (before mode coupling) is one in which one mode is occupied with probability 1 and another mode is unoccupied with probability 1 (e.g., the state |10〉 in the Fock notation introduced above), mode coupling can result in a state in which both modes have a non-zero probability of being occupied, e.g., the state a1|10〉+a2|01〉, where |a1| 2 +|a2| 2= 1. In some embodiments, this type of operation can be implemented by using a beam splitter to combine the modes together and a variable phase shifter to apply a phase shift to one or more modes. The amplitudes a1 and a2 depend on the reflectivity (or transmittance) of the beam splitter and any phase shift introduced.

[0137] Figure 2A shows a schematic diagram 210 (also called a circuit diagram or circuit notation) for coupling two modes. The modes are depicted as horizontal lines 212, 214, and the mode coupler 216 is indicated by a vertical line terminating in a node (black circle) to identify the coupled mode. In the more specific language of linear quantum optics, the mode coupler 216 shown in Figure 2A represents a 50 / 50 beam splitter that implements the following transfer matrix:

[0138]

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[0139]

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[0140]

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[0141]

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[0142]

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[0143] FIG. 2B illustrates a physical implementation of mode coupling that implements the transfer matrix T of Equation (9) for two photonic modes, according to some embodiments. In this example, mode coupling is implemented using a waveguide beamsplitter 200, sometimes called a directional coupler or mode coupler. The waveguide beamsplitter 200 can be realized by placing two waveguides 202, 204 close enough that the evanescent field of one waveguide can couple into the other. By adjusting the separation d between the waveguides 202, 204 and / or the length l of the coupling region, different couplings between the modes can be obtained. In this manner, the waveguide beamsplitter 200 can be configured to have a desired transmittance. For example, the beamsplitter can be designed to have a transmittance equal to 0.5 (i.e., a 50 / 50 beamsplitter to implement the particular form of the transfer matrix T introduced above). If other transfer matrices are desired, the reflectance (or transmittance) can be designed to be greater than 0.6, greater than 0.7, greater than 0.8, or greater than 0.9 without departing from the scope of this disclosure.

[0144] In addition to mode coupling, some unitary transformations may involve a phase shift applied to one or more modes. In some photonic implementations, variable phase shifters can be implemented in integrated circuits to provide control over the relative phase of photon states spreading across multiple modes. An example of a transfer matrix defining such a phase shift is given by (to apply +i and −i phase shifts, respectively, to the second mode):

[0145]

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[0146] A beam splitter with variable transmittance and arbitrary phase relationships between output modes can also be achieved by combining a directional coupler and a variable phase shifter in a Mach-Zehnder interferometer (MZI) configuration 300, as shown, for example, in FIG. 3A. Full control over the relative phase and amplitude of the two modes 302a, 302b in dual-rail encoding can be achieved by varying the phase imparted by phase shifters 306a, 306b, and 306c as well as the length and proximity of coupling regions 304a and 304b. FIG. 3B shows a slightly simpler example of an MZI 310 that allows variable transmittance between modes 302a, 302b by varying the phase imparted by phase shifter 306. While FIGS. 3A and 3B are examples of how a mode coupler can be implemented in a physical device, any type of mode coupler / beam splitter can be used without departing from the scope of this disclosure.

[0147] In some embodiments, beam splitters and phase shifters can be used in combination to implement various transfer matrices. For example, Figure 4A shows, in a schematic form similar to Figure 2A, a mode coupler 400 that implements the following transfer matrix:

[0148]

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[0149]

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[0150] Similarly, a network of mode couplers and phase shifters can be used to implement coupling between more than two modes. For example, Figure 5 shows a four-mode coupling scheme that implements a "spreader" or "mode information elimination" transformation for four modes; that is, it captures a photon in any one of the input modes and delocalizes the photon among each of the four output modes so that the photon has an equal probability of being detected in any one of the four output modes. (The well-known Hadamard transform is an example of a spreader transform.) As in Figure 2A, horizontal lines 512-515 correspond to modes, and mode coupling is indicated by vertical line 516 with nodes (dots) identifying the coupled modes. In this case, four modes are coupled. Circuit representation 502 is an equivalent representation of circuit diagram 504, a network of first-order mode coupling. More generally, if higher-order mode coupling can be implemented as a network of first-order mode coupling, a circuit representation similar to representation 502 (with the appropriate number of modes) can be used.

[0151] FIG. 6 illustrates an exemplary optical device 600 capable of implementing the four-mode modal diffusion conversion shown schematically in FIG. 5 , according to some embodiments. The optical device 600 includes a first set of optical waveguides 601, 603 (represented by solid lines in FIG. 6 ) formed in a first material layer and a second set of optical waveguides 605, 607 (represented by dashed lines in FIG. 6 ) formed in a second material layer separate from the first material layer. The second material layer and the first material layer are disposed at different heights above a substrate. Those skilled in the art will understand that an interferometer such as that shown in FIG. 6 can be implemented in a single layer if an appropriate low-loss waveguide intersection is used.

[0152] At least one optical waveguide 601, 603 of the first set of optical waveguides is coupled to an optical waveguide 605, 607 of the second set of optical waveguides using any type of suitable optical coupler, such as a directional coupler described herein (e.g., the optical couplers shown in FIGS. 2B, 3A, and 3B). For example, the optical device shown in FIG. 6 includes four optical couplers 618, 620, 622, and 624. Each optical coupler can have a coupling region in which two waveguides propagate in parallel. Although the two waveguides are shown in FIG. 6 as being offset from each other at the coupling region, the two waveguides may also be positioned directly above and below each other at the coupling region without any offset. In some embodiments, one or more of optical couplers 618, 620, 622, and 624 are configured to have approximately a 50% coupling efficiency between the two waveguides (e.g., a 49%-51% coupling efficiency, a 49.9%-50.1% coupling efficiency, a 49.99%-50.01% coupling efficiency, a 50% coupling efficiency, etc.). For example, the lengths of the two waveguides, the refractive indices of the two waveguides, the widths and heights of the two waveguides, the refractive index of the material disposed between the two waveguides, and the distance between the two waveguides are selected to provide a 50% coupling efficiency between the two waveguides. This allows the optical coupler to operate like a 50 / 50 beam splitter.

[0153] 6 can include two inter-layer optical couplers 614 and 616. Optical coupler 614 enables light propagating in a waveguide on a first material layer to be transferred to a waveguide on a second material layer, and optical coupler 616 enables light propagating in a waveguide on the second material layer to be transferred to a waveguide on the first material layer. Optical couplers 614 and 616 enable optical waveguides located on at least two different layers to be used in a multi-channel optical coupler, which in turn enables a compact multi-channel optical coupler.

[0154] 6 also includes an uncoupled waveguide intersection region 626. In some implementations, two waveguides (603 and 605 in this example) intersect each other without a parallel coupling region present at the intersection in the uncoupled waveguide intersection region 626 (e.g., the waveguides can be two straight waveguides that intersect each other at approximately a 90-degree angle).

[0155] Those skilled in the art will understand that the foregoing examples are illustrative and that photonic circuits using beam splitters and / or phase shifters can be used to implement many different transfer matrices, including transfer matrices for real and imaginary Hadamard transforms of any order, discrete Fourier transforms, etc. One class of photonic circuits, referred to herein as “spreader” or “mode information elimination (MIE)” circuits, has the property that if the input is a single photon localized to one input mode, the circuit delocalizes the photon among each of several output modes so that the photon has an equal probability of being detected in any one of the output modes. Examples of spreader or MIE circuits include circuits that implement Hadamard transfer matrices. (It should be understood that the spreader or MIE circuit may receive inputs that are not localized single photons in one input mode, and the behavior of the circuit in such cases depends on the particular transfer matrix implemented.) In other examples, the photonic circuit may implement other transfer matrices, including transfer matrices that result in unequal probabilities of detecting a photon in a different output mode for a single photon in one input mode.

[0156] In some embodiments, entangled states of multiple photonic qubits can be generated by coupling modes of two (or more) qubits and performing measurements on other modes. As an example, FIG. 7 shows a circuit diagram of a Bell state generator 700 that can be used in some dual-rail coded photonic embodiments. In this example, modes 732(1)-732(4) are initially each occupied by a photon (shown as a dashed line), and modes 732(5)-732(8) are initially vacuum modes. (Those skilled in the art will understand that other combinations of occupied and unoccupied modes can be used.)

[0157] First-order mode combining (e.g., implementing the transfer matrix T of Equation 9) is performed on pairs of occupied and unoccupied modes (see Equation (9)), as shown by mode combiners 731(1) through 731(4). Then, mode information cancellation combining (e.g., implementing a four-mode mode-spreading transformation as shown in FIG. 5) is performed on four of the modes (modes 732(5) through 732(8)), as shown by mode combiner 737. Modes 732(5) through 732(8) serve as "messenger" modes that are measured and used to determine whether Bell states have been successfully generated on the other four modes 732(1) through 732(4). For example, detectors 738(1) through 738(4) can couple to modes 732(5) through 732(8) after second-order mode combiner 737. Each detector 738(1)-738(4) can output a classical data signal (e.g., a voltage level on a conductor) indicating whether it detected a photon (or the number of photons detected). These outputs can be coupled to classical decision logic 740, which determines whether a Bell state exists on the other four modes 732(1)-732(4). For example, decision logic 740 can be configured so that a Bell state is confirmed (also referred to as a "success" of the Bell state generator) only if a single photon is detected by each of exactly two of detectors 738(1)-738(4). Modes 732(1)-732(4) can be mapped to the logical states of two qubits (qubit 1 and qubit 2), as shown in FIG. 7. Specifically, in this example, the logical state of qubit 1 is based on the occupancy of modes 732(1) and 732(2), and the logical state of qubit 2 is based on the occupancy of modes 732(3) and 732(4). Note that the operation of Bell state generator 700 may be non-deterministic; that is, inputting four photons as shown does not guarantee that Bell states will be created on modes 732(1) through 732(4). In one implementation, the probability of success is 4 / 32.

[0158] In some embodiments, it is desirable to form quantum systems of multiple entangled qubits (two or more qubits). One technique for forming multi-qubit quantum systems is through the use of entangled measurements, which are projected measurements that can be used to generate entanglement between systems of qubits. As used herein, "fusion" (or "fusion operation" or "fusion") refers to projected entangled measurements. A "fusion gate" is a structure that accepts two (or more) input qubits, each of which is typically part of a different quantum system. The different quantum systems do not need to be entangled with each other before applying the fusion gate. In the case of two input qubits, the fusion gate performs a projected measurement operation on the input qubits that produces an output qubit of one ("Type I fusion") or zero ("Type II fusion"), such that the initial two quantum systems are fused into a single quantum system of entangled qubits. Fusion gates are an instantiation of a general class of projected entangled measurements and are particularly suited to photonic architectures. Examples of Type I and Type II fusion gates are described below.

[0159] FIG. 8A shows a circuit diagram illustrating a Type I fused gate 800 according to some embodiments. The diagram shown in FIG. 8A is a schematic diagram in which each horizontal line represents a mode of a quantum system, e.g., photons. In dual-rail encoding, each pair of modes represents a qubit. In a photonic implementation of the gate, the modes of a diagram such as that shown in FIG. 8A can be physically realized using a single photon in a photonic waveguide. Most generally, a Type I fused gate such as that shown in FIG. 8A takes as inputs qubit A (e.g., physically realized by photon modes 843 and 845) and qubit B (e.g., physically realized by photon modes 847 and 849) and outputs a single “fused” qubit that inherits the entanglement of either input qubit A or input qubit B (or both) with other previously entangled qubits.

[0160] For example, FIG. 8B shows the result of a Type I fusion of two qubits, A and B, each of which is a qubit located at the end (i.e., leaf) of a longer entangled cluster state (only a portion of which is shown). The qubit 857 remaining after the fusion operation inherits entanglement coupling from the original qubits, A and B, thereby generating a larger linear cluster state. FIG. 8B also shows the result of a Type I fusion of two qubits, A and B, each of which is an interior qubit belonging to a longer entangled cluster of qubits (only a portion of which is shown). As previously mentioned, the qubit 859 remaining after the fusion inherits entanglement coupling from the original qubits, A and B, thereby generating a fused quantum pattern. In this case, the qubit remaining after the fusion operation is entangled with the larger quantum system by its four other nearest neighbors, as shown.

[0161] Returning to the schematic diagram of Type I fused gate 800 shown in FIG. 8A, qubit A is dual-rail encoded by modes 843 and 845, and qubit B is dual-rail encoded by modes 847 and 849. For example, for a path-encoded photonic qubit, the logic 0 state (|0> A) arises when mode 843 is a photonic waveguide containing a single photon and mode 845 is a photonic waveguide containing zero photons (and similarly for qubit B). Type I fusion gate 800 can therefore take two dual-rail encoded photonic qubits as inputs, resulting in a total of four input modes (e.g., modes 843, 845, 847, and 849). To accomplish the fusion operation, a mode coupler (e.g., a 50 / 50 beam splitter) 853 is applied between each mode of the input qubits, e.g., between mode 843 and mode 849, before performing a detection operation on both modes using photon detector 855 (which includes two separate photon detectors coupled to modes 843 and 849, respectively). Additionally, to ensure that the output modes are adjacently positioned, a mode swap operation 851 may be applied that swaps the position of the second mode (mode 845) of qubit A with the position of the second mode (mode 849) of qubit B. In some embodiments, the mode swap can be achieved through a physical waveguide crossing as described above, or by one or more photonic switches, or by any other type of physical mode swap.

[0162] 8A shows only an example arrangement for a Type I fused gate; one skilled in the art will understand that the location of the mode coupler and the presence of mode swap region 851 may be varied without departing from the scope of this disclosure. For example, beam splitter 853 may be applied between modes 845 and 847. Mode swapping is optional and is not necessary if qubits with non-adjacent modes can be handled, for example, by keeping track of which modes belong to which qubits by storing this information in classical memory.

[0163] Type I fusion gate 800 is a non-deterministic gate; i.e., the fusion operation succeeds with some probability less than 1; otherwise, the resulting quantum state is not a larger quantum system, with the original quantum systems fused together to form the larger quantum system. More specifically, gate 800 "succeeds" with a 50% probability if only one photon is detected by detector 855 and "fails" if zero or two photons are detected by detector 855. If the gate succeeds, the two quantum systems of which qubits A and B were part are fused into a single larger quantum system, and the fused qubit remains as the qubit connecting the two previously unconnected quantum systems (see, e.g., FIG. 8B). However, if the fusion gate fails, it has the effect of removing both qubits from the original quantum system without producing a larger quantum system.

[0164] FIG. 9A shows a circuit diagram illustrating a type II fused gate 900 according to some embodiments. As with other figures herein, the diagram shown in FIG. 9A is a schematic diagram in which each horizontal line represents a mode of a quantum system, e.g., photons. In dual-rail encoding, each pair of modes represents a qubit. In a photonic implementation of the gate, the modes of a diagram such as that shown in FIG. 9A can be physically realized using a single photon in a photonic waveguide. Most generally, a type II fused gate such as gate 900 takes as inputs qubit A (e.g., physically realized by photon modes 943 and 945) and qubit B (e.g., physically realized by photon modes 947 and 949) and outputs a quantum state that inherits the entanglement of either input qubit A or input qubit B (or both) with other previously entangled qubits. In type II fusion, if the input quantum states have a total of N qubits between them, the output quantum state has N−2 qubits. This differs from Type I fusion, in which input quantum states with a total of N qubits between them result in an output quantum state with N-1 qubits.

[0165] For example, Figure 9B shows the result of a Type II fusion of two qubits A and B, each of which is a qubit located at the end (i.e., leaf) of a longer entangled cluster state (only a portion of which is shown). The resulting quantum system 971 inherits the entanglement coupling from qubits A and B, thereby creating a larger linear quantum system.

[0166] Returning to the schematic diagram of type II fused gate 900 shown in FIG. 9A, qubit A is dual-rail encoded by modes 943 and 945, and qubit B is dual-rail encoded by modes 947 and 949. For example, for a path-encoded photonic qubit, the logic 0 state (|0> A) arises when mode 943 is a photonic waveguide containing a single photon and mode 945 is a photonic waveguide containing zero photons (similarly for qubit B). Thus, type II fusion gate 900 takes two dual-rail encoded photonic qubits as inputs, thereby resulting in a total of four input modes (e.g., modes 943, 945, 947, and 949). To accomplish the fusion operation, a first mode coupler (e.g., a 50 / 50 beam splitter) 953 is applied between each mode of the input qubits, e.g., between mode 943 and mode 949, and a second mode coupler (e.g., a 50 / 50 beam splitter) 955 is applied between each other mode of the input qubits, e.g., between modes 945 and 947. A detection operation is performed on all four modes using photon detectors 957(1) through 957(4). In some embodiments, a mode-swapping operation (not shown in FIG. 9A ) can be performed to place the modes in adjacent positions before mode coupling. In some embodiments, the mode-swapping can be achieved through a physical waveguide crossing as described above, or by one or more photonic switches, or by any other type of physical mode-swapping. Mode-swapping is optional and is not necessary if qubits with non-adjacent modes can be handled, for example, by keeping track of which modes belong to which qubits by storing this information in classical memory.

[0167] FIG. 9A shows only an example arrangement for a Type II fused gate, and one skilled in the art will understand that the location of the mode coupler and the presence or absence of the mode swap region may be varied without departing from the scope of the present disclosure.

[0168] The Type II fusion gate shown in Figure 9A is a non-deterministic gate; i.e., the fusion operation succeeds with some probability less than 1; otherwise, the resulting quantum state comprises the original quantum systems fused into a larger quantum system, not the larger quantum system. More specifically, the gate "succeeds" if one photon is detected by one of detectors 957(1) and 957(4) and one photon is detected by one of detectors 957(2) and 957(3); in all other cases, the gate "fails." If the gate succeeds, the two quantum systems of which qubits A and B were part are fused into a single, larger quantum system; unlike Type I fusion, no fused qubits remain (compare Figures 8B and 9B). If the fusion gate fails, it has the effect of removing both qubits from the original quantum system without creating a larger quantum system.

[0169] 10 illustrates an example of a qubit entanglement system 1001 according to some embodiments. According to some embodiments, such a system can be used to generate qubits (e.g., photons) in entangled states (e.g., GHZ states, Bell pairs, etc.). In some embodiments, the qubit entanglement system 1001 can operate as a resource state generator, as described below.

[0170] In an exemplary photonic architecture, qubit entanglement system 1001 may include a photon source module 1005 optically connected to entangled state generator 1000. Both photon source module 1005 and entangled state generator 1000 may be coupled to classical processing system 1003 such that classical processing system 1003 can communicate with and / or control photon source module 1005 and / or entangled state generator 1000 (e.g., via classical information channels 1030a-b). Photon source module 1005 may include a collection of single-photon sources that can provide output photons to entangled state generator 1000 by interconnecting waveguides 1032. Entangled state generator 1000 can receive the output photons, convert them into one or more entangled photon states, and then output these entangled photon states to output waveguide 1040. In some embodiments, output waveguide 1040 may be coupled to some downstream quantum photonic circuitry that may use the entangled states, for example, to perform quantum computations. For example, the entangled states generated by entangled state generator 1000 may be used as resource states for one or more interleaving modules, as described below.

[0171] In some embodiments, system 1001 may include classical channels 1030 (e.g., classical channels 1030-a through 1030-d) for interconnecting and providing classical information between components. Note that classical channels 1030-a through 1030-d need not all be the same. For example, classical channels 1030-a through 1030-c may comprise a bidirectional communication bus carrying one or more reference signals, e.g., one or more clock signals, one or more control signals, or any other signals that carry classical information, e.g., messenger signals, photon detector readout signals, etc.

[0172] In some embodiments, the qubit entanglement system 1001 includes a classical computer system 1003 that communicates with and / or controls the photon source module 1005 and / or the entangled state generator 1000. For example, in some embodiments, the classical computer system 1003 can be used to configure one or more circuits, e.g., using a system clock that can be provided to the photon source 1005 and the entangled state generator 1000, as well as any downstream quantum photonic circuitry used to perform quantum computations. In some embodiments, the quantum photonic circuitry can include optical circuits, electrical circuits, or any other type of circuitry. In some embodiments, the classical computer system 1003 includes a memory 1004, one or more processors 1002, a power supply, an input / output (I / O) subsystem, and a communication bus interconnecting these components. The processor 1002 can execute modules, programs, and / or instructions stored in the memory 1004, thereby performing processing operations.

[0173] In some embodiments, memory 1004 stores one or more programs (e.g., instruction sets) and / or data structures. For example, in some embodiments, entangled state generator 1000 can attempt to generate an entangled state over successive stages, any one of which may be successful in generating the entangled state. In some embodiments, memory 1004 stores one or more programs for determining whether each stage is successful and configuring entangled state generator 1000 accordingly (e.g., by configuring photon generator 1000 to switch the entangled state to an output if the stage is successful, or to pass the entangled state to the next stage of photon generator 1000 if the stage is not yet successful). To that end, in some embodiments, memory 1004 stores detection patterns (described below) that enable classical computing system 1003 to determine whether a stage is successful. Additionally, memory 1004 can store settings provided to various configurable components (e.g., switches) described herein, for example, by setting one or more phase shifts for the components.

[0174] In some embodiments, some or all of the above-described functionality may be implemented in hardware circuitry on the photon source module 1005 and / or entangled state generator 1000. For example, in some embodiments, the photon source module 1005 includes one or more controllers 1007-a (e.g., logic controllers) (which may comprise, for example, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICS), "systems on a chip" including classical processors and memory, etc.). In some embodiments, the controller 1007-a determines whether the photon source module 1005 was successful (e.g., for a given attempt on a given clock cycle, as described below) and outputs a reference signal indicating whether the photon source module 1005 was successful. For example, in some embodiments, controller 1007-a outputs a logic high value to classical channel 1030-a and / or classical channel 1030-c when photon source module 1005 is successful, and outputs a logic low value to classical channel 1030-a and / or classical channel 1030-c when photon source module 1005 is unsuccessful. In some embodiments, the output of controller 1007-a may be used to configure hardware within controller 1007-b.

[0175] Similarly, in some embodiments, the entangled state generator 1000 includes one or more controllers 1007-b (e.g., logic controllers) (which may comprise, for example, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICS), etc.) that determine whether each stage of the entangled state generator 1000 was successful, execute the switching logic described above, and output reference signals to classical channels 1030-b and / or 1030-d to notify other components whether the entangled state generator 400 was successful.

[0176] In some embodiments, a system clock signal can be provided to photon source module 1005 and entangled state generator 1000 via an external source (not shown) or by classical computing system 1003 via classical channels 1030a and / or 1030b. In some embodiments, the system clock signal provided to photon source module 1005 triggers photon source module 1005 to attempt to output one photon per waveguide. In some embodiments, the system clock signal provided to entangled state generator 1000 triggers or gates a set of detectors in entangled state generator 1000 to attempt to detect photons. For example, in some embodiments, triggering a set of detectors in entangled state generator 1000 to attempt to detect photons includes gating the set of detectors.

[0177] Note that in some embodiments, photon source module 1005 and entangled state generator 1000 can have internal clocks. For example, photon source module 1005 can have an internal clock generated and / or used by controller 1007a, and entangled state generator 1000 has an internal clock generated and / or used by controller 1007b. In some embodiments, the internal clock of photon source module 1005 and / or entangled state generator 1000 are synchronized (e.g., via a phase-locked loop) to an external clock (e.g., a system clock provided by classical computer system 1003). In some embodiments, any of the internal clocks may itself be used as a system clock; for example, the internal clock of a photon source may be distributed to other components in the system and used as a master / system clock.

[0178] In some embodiments, the photon source module 1005 includes multiple stochastic photon sources, i.e., so-called multiplexed single-photon sources, which may be spatially and / or temporally multiplexed. In one example of such a source, the source is driven by a pump, e.g., an optical pulse, coupled to an optical resonator that can generate zero, one, or more photons through some nonlinear process (e.g., spontaneous four-wave mixing, second harmonic generation, etc.). As used herein, the term "attempt" refers to the act of driving a photon source with some kind of drive signal, e.g., a pump pulse, that can generate output photons non-deterministically (i.e., the probability that the photon source will generate one or more photons in response to the drive signal may be less than one). In some embodiments, each photon source may be most likely to generate zero photons in each attempt (e.g., the probability of generating zero photons per attempt to generate a single photon may be 90%). The second most likely outcome to an attempt may be the generation of a single photon (e.g., there may be a 9% chance of generating a single photon per attempt to generate a single photon). The third most likely outcome to an attempt may be the production of two photons (e.g., there may be about a 1% chance of producing two photons per attempt to produce a single photon). In some circumstances, the chance of producing more than two photons may be less than 1%.

[0179] In some embodiments, the apparent efficiency of a photon source may be increased by using multiple single photon sources and multiplexing the output of the multiple photon sources.

[0180] The exact type of photon source used is not important; any type of source can be used that employs any photon generation process, such as spontaneous four-wave mixing (SPWM), spontaneous parametric down-conversion (SPDC), or any other process. Other classes of sources that do not necessarily require nonlinear materials can also be used, such as quantum dot sources, sources that use atoms and / or artificial atomic systems, such as color centers in crystals. In some cases, the source can be coupled to a photonic cavity, as in the case of an artificial atomic system, such as a quantum dot coupled to a cavity. Other types of photon sources also exist for SPWM and SPDC, such as optomechanical systems. In some examples, the photon source can emit multiple photons that are already in an entangled state, in which case the entangled state generator 400 may not be required, or it may take an entangled state as an input and generate an even larger entangled state.

[0181] For illustrative purposes, an example using spatial multiplexing of several non-deterministic photon sources will be described as an example of a MUX photon source. However, many different spatial MUX architectures are possible without departing from the scope of this disclosure. Time multiplexing can also be implemented instead of or in combination with spatial multiplexing. MUX schemes using log trees, generalized Mach-Zehnder interferometers, multimode interferometers, chain light sources, chain light sources with a dump-and-pump scheme, asymmetric polycrystalline single-photon sources, or any other type of MUX architecture can be used. In some embodiments, the photon source can employ a MUX scheme involving quantum feedback control, etc.

[0182] The preceding description provides examples of how photonic circuits can be used to implement physical qubits and operations on physical qubits using mode coupling between waveguides. In these examples, a pair of modes can be used to represent each physical qubit. The examples described below can be implemented using similar photonic circuit elements.

[0183] 1.4. Fault Tolerance and Logical Qubits "Quantum computing," as used herein, generally refers to performing a sequence of operations ("computation") on an ensemble of qubits. Quantum computing is often considered within the framework of "circuit-based quantum computing" (CBQC), where operations are specified as sequences of logic "gates" performed on qubits. Gates can be either single-qubit unitary operations (rotations), two-qubit entanglement operations such as the CNOT gate, or other multi-qubit gates such as the Toffoli gate. In the CBQC framework, quantum computing can be modeled as a reversible circuit in which a set of input qubits is initialized in a known state and then operated by applying a series of "gates," each of which is a unitary transformation operation that acts on one or more of the qubits. Measuring the state of each qubit after applying the last gate yields the result of the computation. Gates used in quantum computing correspond to unitary operators that act on qubits. Gates can include single-qubit unitary operations (e.g., Pauli rotation, identity gate), two-qubit entangled operations such as the CNOT gate, and other multi-qubit gates such as the three-qubit Toffoli gate. In commonly used circuit models of quantum computing, a particular computation can be defined by specifying the number of qubits and a particular sequence of gates. It has been shown that any quantum computation can be modeled using a finite set of gates, including Clifford gates (which belong to the mathematical group of unitary transformations that includes the Pauli rotation, CNOT gate, and Hadamard transform), and T-gates that implement the transformation.

[0184]

number

[0185] The quantum circuit model provides a conceptual framework that can potentially be realized using various physical systems to implement qubits and gates. However, the physical systems that implement qubits and operations on qubits are often nondeterministic and noisy. For example, the photonic Bell state generator and fused circuit described above can generate entanglement between photonic qubits, but they do so nondeterministically with a probability of success significantly less than one. Furthermore, physical systems can be "noisy"; for example, waveguides that propagate photons can be somewhat less than perfectly efficient, resulting in occasional loss of photons. For these reasons, fault-tolerant quantum computing is a desirable goal. Generally, fault tolerance involves constructing a "logical qubit" using a system of multiple physical qubits entangled in a manner that allows errors to be detected and corrected. Gate operations can then be performed on the logical qubit. One technique for fault tolerance that has been developed uses surface codes, in which many physical qubits undergo parity-checking operations to encode a single logical qubit.

[0186] It should be understood that a "qubit" is a unit of information. In some contexts, the term "qubit" refers to a physical system whose state space corresponds to one quantum bit of information, and in some contexts, the term "qubit" refers to a logical construct (such as a surface code) that includes multiple physical quantum bits that collectively encode one quantum bit of information in a fault-tolerant manner. Where context may ambiguize the meaning, this disclosure uses the term "physical quantum bit" to refer to the physical system and the term "logical quantum bit" to refer to the fault-tolerant construct. A "measurement" operation on a logical quantum bit generally involves measuring the underlying physical quantum bit and analyzing the result (e.g., using a decoder algorithm) to extract the quantum bit of information.

[0187] 1.5. Surface Code Quantum Computing A single physical qubit (such as the two-level physical qubit 1100 shown in FIG. 11A with quantum state |ψ〉=a1|0〉+a2|1〉) can be used for quantum computing. However, individual physical qubits are generally highly susceptible to noise and decoherence. Fault-tolerant quantum computing utilizes multiple entangled physical qubits to encode a single logical qubit, mitigating the failure and / or short coherence time of individual physical qubits. In a fault-tolerant quantum computing scheme, multiple physical qubits, such as those shown in FIG. 11B, are entangled with one another according to a particular error-correcting code to generate a single logical qubit that is less susceptible to noise and decoherence. By encoding the qubits in this manner, the resulting logical qubit is less sensitive to errors and noise, and the resulting errors can be addressed via quantum error correction.

[0188] In some quantum computing methods, such as the fusion-based and circuit-based quantum computing described herein, a logical qubit is encoded from multiple physical qubits using a particular sequence of measurements (e.g., stabilizer measurements). The measurement sequence may be constructed such that a subset of the physical qubits are measured (e.g., generate classical information in the form of a measurement result) such that the remaining unmeasured / unfolded degrees of freedom (e.g., a two-dimensional subspace with support across all physical qubits) form the desired encoded logical qubit. Thus, a process for performing stabilizer measurements and / or encoding a fault-tolerant logical qubit may receive multiple physical qubits as input and may generate as output both the encoded logical qubit and classical information (e.g., syndrome graph data) resulting from the measurement sequence.

[0189] In some quantum computing implementations, classical information takes the form of syndrome graph data, where the syndrome graph is a geometric representation of the outcome of a measurement sequence. Because input physical qubits are prepared in an initial state and measured according to a predetermined measurement sequence, it is possible to determine how the syndrome should appear in the absence of any errors (e.g., Pauli or erasure errors) involving the physical qubits during the measurement sequence. Therefore, any deviations in the syndrome graph data from the expected outcome may indicate one or more errors in the logical qubit. In general, these deviations may not precisely indicate which measurements had errors or which types of errors occurred, as there may be more than one type of error or combination of errors consistent with a given observed deviation from the expected error-free syndrome graph. For example, the syndrome graph may be determined as a grid of parity checks on neighboring nodes of the grid, whereby a parity error may indicate that one or more of the neighboring nodes had an error, but the parity error may not precisely indicate which neighboring nodes had errors or which errors occurred.

[0190] As used herein, the term "syndrome graph data" refers to a set of classical information (e.g., data represented by digital values ​​such as 1s and 0s) that specifies the location of one or more syndromes and / or one or more erasure errors in the syndrome graph of a logic block. A series of measurements (e.g., stabilizer measurements) are applied to the physical qubits of an error-correcting code that contain the encoded logical information, producing the measurement results as classical information. As described in more detail below, based on knowledge of the particular geometry of the error-correcting code, these measurement results can be used to determine classical data, referred to herein as "syndrome graph data."

[0191] Errors that occur during operations on encoded logical qubits can have varying degrees of severity. For example, errors in fault-tolerant logical qubits can cause logical failures if they link up across the syndrome graph of the logical qubits.

[0192] FIG. 11B shows an arrangement of physical qubits, including qubits 1103, 1105, 1107, 1109, and 1111, that may be used to encode fault-tolerant logic qubits using a surface code, according to one or more embodiments. In FIG. 11B, the solid grid lines are a guide to the eye, forming a square array, also referred to herein as a "surface code," with physical "data qubits" (e.g., qubits 1105, 1107, 1109, and 1111) located at the four vertices of each square and physical "measurement qubits" (e.g., qubit 1103) located on the faces of each square. As used herein, a measurement qubit is a physical qubit that is measured to perform stabilizer measurements (also referred to herein as "parity checks") on neighboring data qubits without directly measuring the data qubits and collapsing the quantum information. This example has a surface code length (or more precisely, a "code distance") d of 12, although any length can be used. The surface code arrangement of qubits also includes four lines of boundary measurement qubits (e.g., qubits 1113, 1115) positioned adjacent to the outermost line of data qubits. Each square is referred to herein as a plaquette. Within the bulk of the surface code (i.e., the plaquette that does not form the outer boundary of the code), each data qubit may be coupled to its four nearest neighbor measurement qubits (each on four different plaquette) via four two-qubit gates (not shown in FIG. 11B ); similarly, each measurement qubit may be coupled to its four nearest neighbor data qubits via four two-qubit gates. On the boundary of the code, each boundary measurement qubit may be coupled to its nearest neighbor data qubit via two two-qubit gates (not shown in FIG. 11B ). According to one or more embodiments, the two-qubit gates may be CNOT gates, CZ gates, etc.

[0193] To operate the collection of data and measure the qubits as logical qubits that are protected from errors, the following set of measurements can be repeatedly performed on the system: For each plaquette in the bulk of the surface code, a four-qubit stabilizer is measured. For example, as shown in FIG. 11D, if the data qubits of a given plaquette (e.g., data qubits 1105-1111 in FIG. 11B) are labeled 1, 2, 3, and 4, and the measurement qubit (e.g., measurement qubit 1103 in FIG. 11B) is labeled a, then the stabilizer to be measured on that plaquette can be X1Z2Z3X4. The “quantum circuit” (a term referring to the sequence of gate and measurement operations performed on physical qubits) used to implement this stabilizer measurement is also shown in FIG. 11D as circuit 1121, and involves first initializing measurement qubit a in the |+〉 state, then executing the following gates: CNOT gate 1122 between measurement qubit a and data qubit 1; CZ gates 1123, 1124 between measurement qubit a and qubit 2 and qubit 3, respectively; and CNOT gate Z 125 between measurement qubit a and qubit 4, followed by the X-basis measurement M of measurement qubit a. x follows. The resulting measurement (which takes the form of a classical bit, e.g., 0 or 1 or -1 or 1, depending on the choice of convention) is equivalent to a measurement of the parity-check stabilizer X1Z2Z3X4 and becomes part of the syndrome graph. For a plaquette found at the boundary of a surface code, an example of which is shown in Figure 11E, a two-qubit stabilizer of the form Z1X2 is measured. The quantum circuit 1131 used to implement this two-qubit stabilizer measurement is also shown in Figure 11E and involves first initializing the boundary measurement qubit a in the |+〉 state, then executing a CZ gate 1132 between measurement qubit a and qubit 1, and a CNOT gate 1133 between measurement qubit a and qubit 2, followed by an X-basis measurement M of measurement qubit a. xIn the example surface code 1140 shown in Figure 11C, there are two different types of boundaries, depending on whether the boundary includes shaded plaques (e.g., the top and bottom edges of the depicted figure) or unshaded plaques (e.g., the left and right edges of the figure). Boundaries that include shaded plaques are referred to as "dual boundaries," and measurements involving measurement qubits within dual boundaries contribute to the "dual syndrome graph." Similarly, boundaries that include unshaded plaques are referred to herein as "primary boundaries," and measurements involving measurement qubits within primary boundaries contribute to the "primary syndrome graph."

[0194] To implement the surface code scheme shown in Figures 11C-11E, the plaquette measurements can be divided into two groups: a first group measuring the stabilizer associated with the shaded plaquette for a first duration, and a second group measuring the stabilizer with the unshaded plaquette for a second duration. These two sets of measurements are performed at different times to ensure that each qubit participates in only one quantum gate at a time. Those skilled in the art will understand that any gates that can be interchanged with each other may be performed in the same time step, or simultaneously if desired. The classical data (referred to herein as "syndrome graph data") generated by each one of these measurements is then passed to a decoder for quantum error correction, according to known methods, for example, using union-find decoding, minimum-weight perfect matching, or any other decoding process.

[0195] Those skilled in the art will appreciate that the examples shown in Figures 11C-11E are based on a particular choice of local basis for the surface code, and that other choices for the basis can be used. For example, in some situations, assuming certain assumptions about the likely form of errors that may occur on the underlying data and measurement qubits, a single-qubit gate may be applied to each data qubit to obtain a modified surface code. The basis for each check can be modified to obtain the modified code scheme. One example is the CSS (Calderbank, Shor, Steane) version, where the stabilizer measurements are either x-type or z-type. To obtain this version of the surface code, the stabilizer is Hadamard H: X → Z, Z → X for half of the data qubits in the bipartition. The CSS surface code is obtained by performing X → Z, Z → X on half of the data qubits in the bipartition. Note that the measurement schedule described above remains the same, but the stabilizers are somewhat different, as summarized in Figure 11F.

[0196] When the above-described surface code measurement schedule is applied for many time steps, the system of entangled physical qubits effectively acts as a fault-tolerant quantum memory for the logical qubits encoded by the underlying surface code, or viewed another way, as a fault-tolerant logical identity gate on the logical qubits encoded by the underlying surface code. Viewed yet another way, this process operates as a fault-tolerant logical channel.

[0197] Figure 11G shows a three-dimensional graphical representation of such a fault-tolerant logic identity gate. The surface labeled 1154 is the input port to the gate and contains an arbitrary logic state encoded in a surface code represented as an input checkerboard surface. Similarly, the surface labeled 1158 identifies the output qubit after identity gate I has been applied. The input and output surfaces, which may be associated with the physical 2D arrangements of the data and measurement qubits described above, are connected to each other through intervening volumes that represent unique measurement sets applied over time, as described above with reference to Figures 11C-11E. Thus, in Figure 11G, time progresses from left to right, and the lighter-shaded (before and after) and darker-shaded (top and bottom) sides of the volume's boundary indicate whether a primary or secondary plaquette is located on that boundary, as described above with reference to Figures 11C-11E. For convenience of explanation, a graphical representation of a fault-tolerant gate, such as the identity gate of Figure 11G, can be associated with cardinal directions designated North-South (NS), East-West (EW), and Up-Down (UD), where time flows "upward" along the UD axis and the North, South, East, and West directions correspond to the boundaries of a volume. Reference to such directions should not be understood as implying an actual spatial arrangement of physical qubits or circuit components.

[0198] Figure 11H depicts the same concept (an identity gate) but written in the more familiar quantum circuit notation, illustrating the similarity between surface codes and more familiar quantum circuits. Figure 11G depicts a logical identity gate, but any gate can be depicted this way, and such a depiction is one example of a "logic block" that specifies a set of instructions to be executed on underlying surface code qubits to perform a logical operation (in this example, an identity gate) on logical qubits encoded by the surface code. Other examples of such gates are S gates, Hadamard gates, and CX gates, among other possibilities. Other examples of logic blocks that can be used to construct any logic gate are described below with reference to Figures 20A-20E.

[0199] The sequence of measurements performed over the timeline shown in FIG. 11G (e.g., the sequence of measurements including the circuit measurements shown in FIGS. 11C-11E) may include a subset of measurements that suffer from logic errors (e.g., Pauli errors) or erasure errors. To identify errors in the measurement results, syndrome graph data may be generated from the collection of measurement results resulting from measurements of physical qubits. For example, bit values ​​associated with multiple edge qubits may be combined to create syndrome values ​​associated with adjacent vertices resulting from the intersection of the respective edges, e.g., the results of the measurements shown in FIGS. 11D and 11E. A set of syndrome values ​​(or "syndrome"), also referred to herein as parity checks, may be associated with each vertex of the syndrome graph. The parity check value can be found by calculating the parity of the bit values ​​associated with each edge of the syndrome graph that is incident on the vertex. In some embodiments, the parity calculation involves determining whether the sum of the edge values ​​is an even or odd integer, and the parity result is the result of the sum modulo 2. If no errors occur in the quantum state or qubit measurements, all syndrome values ​​should be even (or 0). Conversely, if errors occur, some odd (or 1) syndrome values ​​may result.

[0200] In some embodiments, half of the bit values ​​from qubit measurements are associated with a primal boundary surface, and this syndrome graph is referred to herein as the "primal graph." The syndrome graph resulting from measurements at a dual boundary surface is referred to as the "dual graph." In general, the syndrome values ​​of the primal and dual graphs have equivalent decoding problems.

[0201] Surface codes may be implemented using a qubit entanglement system, such as the system of FIG. 10 described above, to generate an entangled system of physical qubits. In some embodiments, an entangled system of multiple physical qubits may be mapped to one or more "logical qubits," and operations associated with a quantum computation may be defined as logical operations on the logical qubits, which may be mapped to physical operations on the physical qubits. In general, the term "qubit," when used herein without specifying a physical or logical qubit, should be understood to refer to a physical qubit.

[0202] Those skilled in the art will understand that the foregoing examples of surface codes and stabilizers are illustrative of topological codes that may be used for quantum error correction, and that different topological codes use different stabilizers applied to different numbers and combinations of physical qubits. Thus, although surface codes are used herein for illustrative purposes, the systems and methods described herein are not limited to surface codes or any particular stabilizers, but can be implemented in connection with other topological codes, including toric codes, color codes, etc.

[0203] 1.6. Overview of Fusion-Based Quantum Computing (FBQC) Fusion-based quantum computing (FBQC) is a technique for implementing surface-code quantum computing that is well-suited for systems in which physical qubits are implemented using photons. In FBQC, a large number of "resource states" are generated, each containing a small number (e.g., about 6-30) of entangled qubits. By performing projected entanglement measurements (e.g., the Type II fusion described above) on qubits in different resource states, one can obtain the same parity-check measurements as in conventional surface-code implementations, without the need to build or maintain a large entangled system of physical qubits.

[0204] To understand FBQC, it is useful to first consider measurement-based quantum computation (MBQC), a technique for implementing quantum computation that enables fault tolerance. In MBQC, computation proceeds by first preparing a specific entangled state of many physical qubits, commonly called a "cluster state," and then performing a series of single-qubit measurements to establish (or execute) the quantum computation. For example, rather than implementing a sequence of gates that operate on one or two physical qubits, a subset of the physical qubits in the cluster state can be mapped to a "logical" qubit, and gate operations on the logical qubits can be mapped to a specific set of measurements on the physical qubits associated with one or more logical qubits. Entanglement between physical qubits results in expected correlations between measurements on different physical qubits, which enables error correction. The cluster state can be prepared in a manner that is not specific to a particular computation (other than perhaps the size of the cluster state), and the selection of single-qubit measurements is determined by the particular computation. In the MBQC approach, fault tolerance can be achieved through careful design of the cluster state and by using the topology of the cluster state to encode the logical qubits in a way that protects against any logical errors that may be caused by errors in any of the physical qubits that make up the cluster state. The values ​​(or states) of the logical qubits can be determined, i.e., read out, based on the results of single-particle measurements (also referred to herein as measurement results) made on the physical qubits of the cluster state as the computation progresses.

[0205] For example, a cluster state suitable for MBQC can be defined by preparing a set of physical qubits in a particular state |+〉 (sometimes called a cluster state) and applying controlled-phase gates (sometimes called "CZ gates") between pairs of physical qubits to generate the cluster state. Graphically, the cluster state thus formed can be represented by a graph with vertices representing physical qubits and edges representing entanglement (e.g., the application of CZ gates) between pairs of qubits. The graph may be a three-dimensional graph with a regular structure formed from repeating unit cells, sometimes called a "lattice." One example of a lattice is the Raussendorf lattice, which is described in detail in R. Raussendorf et al., "Fault-Tolerant One-Way Quantum Computer," Annals of Physics 321(9):2242-2270 (2006). In such a representation, two-dimensional boundaries of the lattice can be identified. Qubits that fall within these boundaries are called "boundary qubits," and all other qubits are called "bulk qubits." Other cluster state structures can also be used. Logical operations are performed by performing single-qubit measurements on qubits in cluster states, with each measurement in a particular logical basis selected according to the particular quantum computation being performed. The collection of measurements across the cluster states can be interpreted as the result of a quantum computation on a set of logical qubits through the use of a decoder. Numerous examples of decoder algorithms are available, including the Union-Find decoder described in International Patent Application Publication No. WO 2019 / 002934 A1.

[0206] However, generating and maintaining long-range entanglement across cluster states, and subsequently storing large cluster states, can be challenging. For example, for any physical implementation of the MBQC approach, cluster states containing thousands or more mutually entangled qubits must be prepared and then stored for a period of time before a single-qubit measurement can be performed.

[0207] "Fusion-based quantum computing (FBQC)" is a technique related to MBQC in that a computation on a set of logical qubits can be defined as a set of measurements on a (generally much larger) number of physical qubits, and correlations between the measurement results on the physical qubits enable error correction. However, FBQC avoids the need to first generate and then subsequently manipulate large cluster states. In a photonic implementation of FBQC, entangled states consisting of several physical qubits (called "resource states") are periodically generated and transported (via waveguides) to a circuit capable of performing measurement operations (e.g., the Type II fusion operations described above, which can provide two-qubit and / or single-qubit measurements). The measurements destroy the measured qubits; however, quantum information is preserved as it is transferred (teleported) to other qubits in other resource states. Thus, quantum information is not stored in a static array of physical qubits, but instead is periodically teleported to newly generated physical qubits.

[0208] In FBQC, computations can be mapped onto an undirected graph called a fusion graph, which can have a lattice-like structure, somewhat similar to MBQC. The fusion graph can define operations to be performed on physical qubits in resource states, including fusion operations on selected qubits in different resource states (e.g., in the "bulk" region of the lattice) and individual qubit measurements (e.g., at the boundaries of the lattice). Examples of FBQC techniques are described in International Publication No. 2021 / 155289, "Fusion Based Quantum Computing," published August 5, 2021. This section provides a conceptual description of FBQC to provide context for the interleaving module and other hardware components described below.

[0209] 1.6.1. Resource States As mentioned above, FBQC can use "resource states" as fundamental physical elements for implementing quantum computation. As used herein, "resource state" refers to an entangled system of several physical qubits in a non-separable entangled state (i.e., an entangled state that cannot be decomposed into smaller, distinct entangled states). In various embodiments, the number n can be a small number (e.g., 3-30), although larger numbers are not excluded.

[0210] FIG. 12 illustrates a graphical representation of a resource state 1200 that may be used in accordance with some embodiments. In the graphical representation of FIG. 12, each physical qubit 1201-1206 in the resource state 1200 is represented as a circle, and entanglement between pairs of physical qubits is represented by lines 1211-1216 connecting pairs of qubits. The resource state 1200 may also be referred to as a "six-ring" resource state. In the examples used herein, the entanglement shape defines a three-dimensional space. For convenience, the cardinal directions in the entanglement space are referred to as north-south (NS), east-west (EW), and up-down (UD). The resource state 1200 has one qubit associated with each cardinal direction (N, S, U, D, E, W) in the entanglement space. It should be understood that the direction labels refer to the entanglement space and need not correspond to physical dimensions or directions in physical space. Furthermore, in some examples, the qubits may be separated in the time dimension rather than the spatial dimension. For example, each physical qubit can be implemented using photons propagating in a waveguide, with particular sections of the waveguide propagating photons associated with different qubits at different times.

[0211] In some embodiments, resource state 1200 may be generated using photon sources and entanglement circuits of the types described above. For example, Bell pairs may be generated using one or more photon sources (which may be MUX photon sources as described above) and a circuit such as circuit 700 of FIG. 7. A 3 GHz state may be generated from two Bell pairs using a circuit such as type I fusion 800 of FIG. 8A. A six-ring resource state 1200 may be formed from a set of six 3 GHz states using a circuit such as type II fusion circuit 900 of FIG. 9A. As described above, entanglement generation circuits such as Bell state generation circuit 700 and fusion circuits 800 and 900 may operate non-deterministically. In some implementations, the outputs of several such circuits may be multiplexed using time and / or spatial multiplexing techniques to increase the probability of generating a resource state.

[0212] Resource states 1200 are exemplary and not limiting. In some embodiments, the entanglement shape of a resource state can be selected based on the particular computation being performed, and different resource states used in the same computation can have different entanglement shapes. Additionally, while resource state 1200 includes six qubits, the number of qubits in a resource state can also be varied. Thus, resource states can be larger or smaller than the example shown. The circuitry used to generate resource states can also be varied depending on the particular entanglement shape and / or the probability of success of various entanglement generation operations. Error-correcting codes can also be constructed to account for non-zero probabilities that a resource state will not be generated.

[0213] Logical Operations Operations performed on qubits in resource states in the context of FBQC can be conceptually represented using a fusion graph. Figure 13A shows an example of a fusion graph 1300 according to some embodiments. The same three-dimensional entanglement space defined in Figure 12 is used, using the same NS, EW, and UD naming conventions (which do not necessarily correspond to any physical dimensions or directions). However, unlike Figure 12, each vertex 1301 represents a resource state (e.g., the six-ring resource state 1200) rather than an individual qubit. Each vertex 1301 represents a physically separate instance of a resource state. Each edge 1310 connecting two vertices 1301 corresponds to a fusion operation between qubits in different resource states. Each fusion operation can be, for example, the Type II fusion operation described above, which produces a two-qubit measurement. The specific qubits involved can be identified from the direction of the edge in the entanglement space. Thus, for example, edge 1310a corresponds to a fusion operation between an N qubit in the resource state represented by vertex 1301a and an S qubit in a (different) resource state represented by vertex 1301b, and edge 1310b corresponds to a fusion operation between a U qubit in the resource state represented by vertex 1301b and a D qubit in a (third) resource state represented by vertex 1301c. Each half-edge 1320 (a "half-edge" is connected to only one vertex 1301) represents a single-qubit measurement on the corresponding qubit in the resource state represented by that vertex 1301. Thus, for example, half-edge 1320a corresponds to a single-qubit measurement on the E qubit in the resource state represented by vertex 1301a.

[0214] In some embodiments, a fusion graph such as fusion graph 1300 can be viewed as a series of “layers” 1330, with each layer corresponding to a coordinate on the U-D axis. Implementing FBQC in a physical system can include successively generating resource states for each layer (e.g., in the D to U direction) and performing fusion and single-qubit measurement operations within each layer as specified by the graph edges and half-edges for that layer. As the resource states for successive layers are generated, fusion operations can be performed between the U qubits in the resource states in one layer and the D qubits in the resource states at the corresponding locations in the next layer. In the following description, fusion operations are sometimes referred to as “spatial” or “temporal.” This term alludes to a particular implementation in which different qubits or resource states are generated or received at different times. Spatial fusion can be performed between qubits generated or received simultaneously using different instances of hardware, and temporal fusion can be performed between qubits generated or received at different times using the same instance of hardware (or different instances of hardware). In the case of photonic qubits, temporal fusion can be implemented by delaying an earlier-generated qubit (e.g., using an additional length of waveguide material to create a longer propagation path for the photon), thereby enabling mode coupling with a later-generated qubit. By leveraging temporal fusion, the same hardware can be used to generate and / or process multiple instances of a resource state within a layer and / or to generate multiple layers of resource states. Examples are provided below.

[0215] In some encoding schemes for sequences of operations on logical qubits, logical qubits that are “at rest” (i.e., not interacting with or otherwise operating on other logical qubits) can be mapped onto a fusion graph having a regular lattice pattern, such as that shown in FIG. 13A. For the six-ring resource state of FIG. 12, each resource state in the bulk of the lattice has each of its six qubits fused with a qubit in an adjacent resource state. (Two qubits input to a Type II fusion circuit are sometimes colloquially described as being “fused” with each other. For example, E qubit 1201 of a first instance of resource state 1200 and W qubit 1202 of a second instance of resource state 1200 can be input to a fusion circuit (e.g., the Type II fusion circuit of FIG. 9A), resulting in a two-qubit measurement. At the boundary of the lattice, qubits that do not undergo a fusion operation can undergo a single-qubit measurement.

[0216] Logical operations on logical qubits can be specified by modifying the regular lattice pattern of the fusion graph at selected locations, for example, by replacing single-qubit measurements with fusion operations, or vice versa. The choice of modification depends on the particular computation being performed. Examples are provided below.

[0217] In some embodiments, a fusion graph, such as fusion graph 1300, can be used to specify logical operations to be performed on a set of logical qubits. For example, a fusion graph defining the logical operations implemented in FBQC can be generated from a surface code space-time or time slice diagram of the kind used to define computations in fault-tolerant CBQC, as described above with reference to Figures 11A-11H. Figures 13B-13D illustrate three different logical operations: (a) measurement of an idle logical qubit (i.e., a logical qubit that is not interacting with any other logical qubit); (b) measurement of a two-qubit

[0218]

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[0219] Figure 13B shows examples of surface code spacetime diagrams 1342a-1342c that may be constructed using techniques known in the art. As shown in legend 1352, the surface code spacetime diagrams can represent logical operations (e.g., twists, transpositions) on surfaces (e.g., primary and secondary boundaries) that define logical qubits. Spacetime diagram 1342a corresponds to a logical qubit that undergoes an identity gate as described above with reference to Figures 1G-1H. Spacetime diagram 1342b corresponds to a two-qubit

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[0223] A quantum computation can be represented as a sequence of time slices, such as the time slices in Figure 13C. However, it is often more convenient to represent a sequence of 2D time slices in a 3D diagram, such as space-time diagrams 1342a-1342c in Figure 13B. Solid black lines in the space-time diagram trace the locus of patch corners through space-time. Shading-coded (or color-coded) surfaces track primary and secondary boundaries through space-time, with the meaning of various shading patterns indicated in legend 1352. A 2D spatial cross-section through space-time diagram 1342 corresponds to time slice diagram 1344. The bulk has a regular pattern of primary and secondary measurements (as seen in the various time slice diagrams in Figure 13C), and measurements within the bulk can be inferred from the boundaries. Also shown in Figure 13B are corner lines indicating the twist action (applied in time slice 1344c-1) and the associated boundary displacement. Space-time diagrams need not directly indicate the number (or code distance) of time slices to which they correspond. Typically, but not necessarily, each change to the spatial configuration lasts for a number of time slices equal to the chord distance.

[0224] For purposes of illustration, spacetime diagram 1342a shows a logical qubit that is idle for some time until it is measured in the Z basis, as indicated by the corner lines and double boundary cap-off of spacetime diagram 1342a. Spacetime diagram 1342b shows a logical two-qubit measurement with "lattice operations"

[0225]

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[0226] In some embodiments of FBQC, a spacetime diagram can be converted into a fusion graph in a straightforward manner. For example, FIG. 13D shows fusion graphs 1340a-1340c corresponding to spacetime diagrams 1342a-1342c. Fusion graphs 1340a-1340c may be generally similar to fusion graph 1300 in that both describe a cubic lattice of resource states. However, fusion graph 1340 adds additional information about the measurement operations being performed by assigning colors or shading to specific cubic or cuboid volumes within the lattice. FIG. 13E shows a legend 1350 illustrating how the shading (or color) of the cubic or cuboid volumes in fusion graphs 1340a-1340c maps to corresponding sets of measurements on qubits with different resource states. In FIG. 13E, top row 1361 defines line styles representing specific two-qubit (fused) and single-qubit measurements. The following rows 1362-1366 show how each cubic or rectangular volume is mapped to a combination of fusion and single-qubit measurements. In some embodiments, each two-qubit fusion measurement (e.g., Type II fusion measurement) is

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[0232] The transformation from the space-time diagram to the fused graph can be achieved, for example, by comparing Figures 13C and 13D. The bulk of the fused graph is filled with primary and secondary bulk cubes in a 3D checkerboard pattern, and the primary and secondary boundaries are decorated with primary or secondary half cubes. If twists or lattice dislocations are present, they are added using the cubes shown in legend 1350. Slices of the fused graph can mimic the pattern of the corresponding CBQC time slices, but the interpretation is different, as can be seen by comparing legend 1350 (Figure 13E) with legend 1354 (Figure 13C). The number of cubes in the fused graph depends on the chord distance, and a time slice of a square patch with chord distance d is d. 2 Contains the resource state.

[0233] Additional discussion of generating fusion graphs such as fusion graph 1340 is available in the above-referenced WO 2021 / 155289 pamphlet and H. Bombin et al., “Interleaving: Modular architectures for fault-tolerant photonic quantum computing,” arXiv:2013.08612v1[quant-ph], March 15, 2021, https: / / arxiv.org / abs / 2103.08612.

[0234] 11A-11H and 13A-13E illustrate the principle of using prescribed combinations of single-qubit measurements (on physical qubits) and fusion between (physical) qubits in different resource states to implement logical operations on logical qubits. It should be understood that a fusion graph can specify operations in a manner that is agnostic to the particular implementation of the physical qubits. Some embodiments described below provide reconfigurable hardware modules that can implement operations on physical qubits in resource states. In some embodiments, such operations may correspond to operations specified in a fusion graph, and measurement data provided by the reconfigurable hardware module can be decoded to determine the result of the logical operation. However, the operation of the reconfigurable hardware module does not depend on any particular method of selecting or specifying the operations to be performed or on any particular downstream use of the measurement data generated by the reconfigurable hardware module.

[0235] 2. Active Volume Quantum Computer Architecture In fault-tolerant quantum computing, maintaining idle qubits can consume significant resources. As an example, FIG. 14 shows a schematic diagram of a quantum circuit 1400 having eight qubits 1401-1408 (sometimes referred to as "memory" qubits, represented as horizontal lines) to which a series of T gates 1421-1 through 1421-16 are applied. As shown, not all qubits are actively involved in any one gate; some of the qubits are idle. For example, qubits 1401 and 1402 are idle from gate 1421-2 through gate 1421-14. In a fault-tolerant quantum computer, qubits 1401-1408 are logical qubits (e.g., implemented using surface-code patches as described above), and hardware or storage resources may be required to maintain the information content of the idle (logical) qubits while gate operations are performed on other logical qubits. For example, an identity gate as described above can be applied to each idle qubit. In a typical fault-tolerant quantum computer architecture, an identity gate involves the same number of physical qubits and measurements as any other gate. Therefore, the cost (a measure of resource requirements) for fault-tolerant quantum computation is roughly proportional to the circuit volume, where "circuit volume" is defined as the number of memory qubits multiplied by the number of non-Clifford gates (e.g., T-gates and / or Toffoli gates). The number n Q requires n memory qubits T Calculations involving non-Clifford gates of n Q ×n T The circuit volume is

[0236] The circuit volume of a quantum circuit can be divided into an “active volume” and an “idle volume.” The “active volume” is the portion of the circuit volume corresponding to the logical operations that drive the computation, including both Clifford and non-Clifford gates, and the “idle volume” is the portion of the circuit volume corresponding to idle qubits. As an example, active volume 1430 of circuit 1400 in FIG. 14 is shown in light (cream) shading, and idle volume 1432 is shown in dark (red) shading. The circuit volume is the sum of the active volume and the idle volume. As FIG. 14 suggests, the active volume can be significantly smaller than the circuit volume. The difference between circuit volume and active volume becomes more pronounced in quantum computers with many more (logical) qubits. For example, the active volume of a 10,000-qubit quantum computer, consisting primarily of adders, is more than 100 times smaller than the circuit volume.

[0237] Certain embodiments described herein relate to fault-tolerant quantum computer architectures (and implementations thereof) in which computational cost (measured by spacetime volume) is proportional to active volume rather than circuit volume. For example, in some embodiments, the computational cost of running a given quantum circuit may be roughly twice the active volume of the circuit. Such architectures are referred to herein as "active volume architectures," and quantum computers that implement active volume architectures are referred to as "active volume quantum computers." This section describes the components and properties of active volume architectures and active volume quantum computers. Section 3 describes example implementations using FBQC and photonic qubits.

[0238] 2.1. Components of an Active Volume Quantum Computer 15 shows a simplified block diagram of an active volume quantum computer system 1500, according to some embodiments. System 1500 includes an active volume quantum computer core 1510 coupled to classical control logic 1520.

[0239] The classical control logic 1520 can be implemented as a digital logic circuit involving an arrangement of classical logic gates (AND, OR, NOR, XOR, NAND, NOT, etc.), such as a field programmable gate array (FPGA) or system-on-chip (SOC) with a programmable processor and memory, or as an on-chip hardwired circuit, such as an application-specific integrated circuit (ASIC). In some embodiments, the classical control logic 1520 (or a portion thereof) can be implemented in an off-chip classical computer with a processor and memory, which can be programmed to perform some or all of the operations of the classical control logic 1520. The classical control logic 1520 can be coupled to the quantum computer core 1510 to exchange classical control signals for controlling the operation of the core 1510 and classical measurement data extracted from the core 1510.

[0240] In operation, classical control logic 1520 (which may include a classical computer) may receive instructions 1522 that specify a quantum computation to be performed. For example, instructions 1522 may include a (classical) machine-readable data file that defines a sequence of logic block networks and quick swap operations as described below, a fused graph as mentioned above, or other instructions that define the operations to be performed in core 1510. Classical control logic 1520 may read the program code and generate control signals that cause quantum computer core 1510 to perform the computation. The nature of the control signals will depend on the particular implementation of core 1510, and additional examples are described below.

[0241] Quantum computer core 1510 may include hardware components and devices that create and / or manipulate physical qubits to perform fault-tolerant logical operations on logical qubits. In operation, core 1510 may perform operations in response to control signals from classical control logic 1520 and return classical measurement data to classical control logic 1520. An exemplary structure of core 1510 is described below.

[0242] Once quantum computer core 1510 returns measurement data (which may be classical binary digital data), classical control logic 1520 may apply various analysis algorithms (e.g., including decoder algorithms as described above) to the measurement data to determine the result of the quantum computation. Classical control logic 1520 may output data 1524, which may include, for example, the final state of the logical qubits and / or other information. In some embodiments, classical control logic 1520 may use the results of the analysis algorithm to select a subsequent instruction 1522 to issue to core 1510. As used herein, the term "reactive measurement" generally refers to a situation in which the result of executing a first instruction is used to determine all or part of a subsequent instruction, and is related to a "reaction time" τ r ) refers to the minimum time between the completion of a first instruction and the completion of a subsequent instruction. The reaction time may include the time consumed in decoding measurement data output from the first instruction to determine which subsequent instruction should be issued. In general, the reaction time for a given implementation of system 1500 depends in part on the implementation of core 1510 and in part on the implementation of classical control logic 1520.

[0243] Quantum computer core 1510 may include a number N of interconnected qubit modules 1512. In the example shown in FIG. 15 , N=24. It should be understood that the architecture of core 1510 is scalable and N may be any number, for example, N may be about 100, about 1,000, or about 10,000. The qubit modules 1512 may be physically or conceptually divided into “memory” modules (shown as rows 1514 in core 1510) and “workspace” modules (shown as rows 1516 in core 1510). In embodiments where the total number N of qubit modules is even, the number of memory modules and the number of workspace modules may each be N / 2. As will become apparent, this division can make it easy to define instructions for core 1510. In particular, workspace modules 1516 can be used to perform logical operations, and memory modules 1514 can be used to store logical qubits and rearrange the logical qubits for use in subsequent operations. Despite the different roles of the memory modules and workspace modules, there need not be any difference in physical structure or circuit design between the memory modules and the workspace modules. For ease of identification, each module can be assigned an identification index (or label) ranging from 1 to N. In the examples herein, the memory modules have odd indices and the workspace modules have even indices. In the following description, "M1" refers to the module with index 1, and so on. (In the figures, "M" may be omitted.)

[0244] Each qubit module 1512 may include hardware components (e.g., optical circuits, electronic circuits, engineered structures, etc.) for operating on the physical qubits to generate the surface code patches. In some embodiments, the hardware components include circuitry or other devices for generating, receiving, and / or storing the physical qubits and performing surface code check operator measurements on the physical qubits, which may involve twists and transpositions in at least one direction. The specific hardware components depend on the type and implementation of the physical qubits. Section 3 describes specific examples of circuits that may be used to implement qubit modules 1512 and core 1510 according to some embodiments in which the physical qubits are photonic qubits. Each surface code patch may have dimensions d × d, where d is the code distance as described above. In some embodiments, the value of d may be fixed for a given hardware implementation of the qubit modules 1512. Depending on the implementation, different qubit modules 1512 may operate simultaneously (or in parallel) or sequentially with each other. Regardless of implementation, a "code cycle" for a given qubit module 1512, as used herein, refers to the time required to generate one dxd surface code patch (e.g., the time required to perform a full set of check operator measurements). At any given time, a given qubit module may be said to be empty (i.e., not storing any logical information used in a quantum computation, but possibly storing random or other unuseful qubit states), idle storing or operating on logical qubits (e.g., actively generating surface code patches that encode the states of fault-tolerant logical qubits), or storing or operating on ancillaries (e.g., actively generating surface code patches that can be used in operations on logical qubits).

[0245] As mentioned above, surface codes can be defined in a three-dimensional entangled space with directions conveniently referred to as E, W, N, S, U, and D. For purposes of this description, each d × d surface code patch is defined as lying in a plane transverse to the UD axes and has distinct E, W, N, and S boundaries. Surface code patches in different qubit modules 1512 may be selectively coupled using inter-boundary coupling of E, W, N, or S boundaries as well as lateral coupling in the UD direction. In some embodiments, inter-boundary coupling between modules may be implemented through coupling of a physical qubit on the edge of a patch in one module (e.g., a physical qubit residing on the E boundary) with a respective physical qubit on the edge of a patch in another module. In some embodiments, lateral coupling may be implemented by coupling each physical qubit in a patch in one module with a respective physical qubit in a patch in another module. Examples of connection networks for active volume architectures are described below.

[0246] Qubit modules 1512 also support initialization of logical qubits. In some embodiments, any qubit module 1512 can initialize a (logical) qubit in either the |0〉 state (Pauli Z basis) or the |+〉 state (Pauli X basis) in one code cycle. Initializing a logical qubit generally involves establishing the physical qubit underlying the surface code patch in the appropriate state (which may depend on the choice of Z or X basis).

[0247] Additionally, any qubit module 1512 can complete a (logical) qubit measurement in either the Pauli-X or Pauli-Z basis within one code cycle. Measuring a logical qubit generally involves performing a single-qubit measurement on each physical qubit of the surface-code patch (in the appropriate basis) and providing the measurement results to classical control logic 1520. Classical control logic 1520 can then decode the measurement data and extract the measured state (0 or 1) of the logical qubit.

[0248] The qubit modules 1512 in the active volume core 1510 are advantageously interconnected to form a network in which a given qubit module 1512 is directly connected to multiple other qubit modules 1512, including qubit modules that are not physically adjacent. These interconnections may enable coupling of corresponding boundaries of surface-coded patches in different qubit modules 1512 (e.g., coupling of boundaries oriented in the same direction in entanglement space, such as E to E, W to W, N to N, S to S, U to U, D to D, etc.), as well as lateral coupling of U and D surfaces of surface-coded patches in different qubit modules 1512. In some embodiments, two types of connection networks may be provided, referred to herein as “port” connections and “quick-swap” connections.

[0249] In some embodiments, a port connection couples each pair of qubit modules 1512 with index values ​​i and j, where 1≦|ij|≦r, where r is a range parameter that can be selected to provide a desired degree of connectivity. A pair of qubit modules with index values ​​i and j is said to be “in range” if ij≦r. As shown below, r=12 is sufficient to implement most commonly used quantum algorithms in a resource-efficient manner. However, other values ​​can also be chosen. For example, r can be 6 or 24 or some other value. When qubit modules 1512 are arranged in a two-dimensional grid, r>3 or r>4 may require port connections between pairs of qubit modules that are not physically adjacent.

[0250] 16 shows example port connections for a representative qubit module M12 in a core 1510, according to some embodiments. Each port connection 1610 couples qubit module M12 to a different qubit module within a range, including at least some modules that are not adjacent. In this example, r=6, and module M12 is coupled by a port connection 1610 to each of modules M6, M7, M8, M9, M10, M11, M13, M14, M15, M16, M17, and M18.

[0251] Each port connection 1610 provides multiple “sub-connections” that can directly couple physical qubits at corresponding boundaries of surface-coded patches in the two modules. As shown in inset 1620 of modules M12 and M14, one port connection 1610 can include six sub-connections 1612-W, 1612-N, 1612-E, 1612-S, 1612-D, and 1612-U that couple corresponding boundaries of surface-coded patches between the two modules. As used herein, “corresponding” boundaries of surface-coded patches refer to boundaries oriented in the same direction. Thus, sub-connection 1612-E couples the E boundary of the surface-coded patch in module M12 to the E boundary of the surface-coded patch in module M14, sub-connection 1612-U couples the U boundary of the surface-coded patch in module M12 to the U boundary of the surface-coded patch in module M14, and so on. Port couplings between the EE, WW, SS, and NN boundaries of two surface-code patches can involve performing surface-code check operator measurements between physical qubits at corresponding boundaries of the two patches, and port couplings between the UU and DD boundaries can involve performing two-qubit transverse measurements or transverse preparation of two-qubit entangled states (e.g., Bell states). In some embodiments, each sub-connection 1612 can be implemented by providing a selectable path for transferring physical qubits from one module to another so that check operator measurements can be performed at the associated boundary. (Those skilled in the art will understand that check operator measurements for a given coupling can be performed in only one of the two modules, and no swapping of physical qubits is required.) The sub-connections 1612 can be independently operable to open or close port connections in particular directions.

[0252] To further illustrate the nature of port connections, Figure 17 shows a surface code level view of a portion of core 1510 in operation. Workspace modules M2, M4, M6, M8, and M10 each generate surface code patches, and corresponding boundaries of surface code patches in a particular pair of modules are combined (via port connections) to perform logical operations. Which boundaries of which surface code patches are combined in a given instance depends on the logical operation being performed, and additional examples are described below.

[0253] 17, the boundaries of the W of the surface-code patches in modules M2 and M4 are coupled (e.g., via instances of port connection 1612-W), and a check operator measurement is performed using the boundary qubits of the W of the surface-code patches, as shown at 1724. In some embodiments using FBQC, the check operator measurement and the two-qubit lateral measurement perform a Type II fused measurement on a corresponding pair of physical qubits, thereby converting the state of the pair into a Bell state

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[0255] Referring again to Figure 16, each port connection 1610 also includes sub-connections 1612-U and 1612-D. Sub-connections 1612-D laterally couple the D surfaces of the respective surface-coded patches in two modules (e.g., M12 and M14). That is, a DD coupling is provided between each pair of qubits in the surface-coded patches in the two modules. When modules M12 and M14 are initially empty (i.e., they do not store any logical qubits or any other quantum information), they store only the logical Bell states

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[0258] Subconnections 1612-U laterally couple the U surfaces of each of the surface-code patches in two modules (e.g., M12 and M14). That is, a UU coupling is provided between each pair of qubits in the surface-code patches in the two modules. If modules M12 and M14 each initially hold a surface-code patch corresponding to a logical qubit, then a logical Bell measurement can be performed using the UU port connections to perform a transverse physical Bell measurement between the physical qubits, i.e., a two-qubit Pauli operator.

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[0260] Port connections 1610 may provide separately controllable sub-connections 1612 for each boundary of a surface-code patch; that is, at any given time, a given sub-connection may be either open (meaning that coupling with the boundary of another surface-code patch occurs) or closed (meaning that coupling with the boundary of another surface-code patch does not occur). For example, each sub-connection 1612 shown in inset 1620 may be independently controllable, subject to the condition that for a given direction of sub-connection (e.g., connection 1612-E) and a given qubit module (e.g., qubit module M12), the sub-connection may be open to no more than one other module at any given time. However, a given qubit module may simultaneously have open sub-connections to two (or more) other qubit modules, provided that the open sub-connections couple different boundaries. For example, in the example shown in Figure 17, an EE sub-connection is open between module M8 and module M10, so the connection between the E port of module M8 and any other module is closed, but module M8 simultaneously has an open SS sub-connection to module M6 as shown. In the following description, it should be understood that any port connection, including a particular port, can be implemented using sub-connections such as those shown in Figure 16.

[0261] Some embodiments of the active volume core 1510 may provide a network of "quick swap" connections between pairs of qubit modules in addition to, or instead of, a network of port connections. In some embodiments, the quick swap connections follow a log tree rule, i.e., the quick swap connections are such that |ij|=2 k qubit modules with index values ​​i and j, and k is

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[0263] FIG. 18 shows an example of a quick-swap connection for a representative qubit module M12 in core 1510 according to some embodiments. Each quick-swap connection 1810 couples qubit module M12 to a different qubit module, allowing the respective logical qubits in the two qubit modules to be swapped within one code cycle, for example, by implementing lateral physical swap gates between the physical qubits or by any other operation that shuttles, moves, or transmits physical qubits between modules. In accordance with the log-tree rule, the quick-swap connections 1810 couple qubit module M12 to modules M4, M8, M10, M11, M13, M14, M16, and M20. As shown in inset 1820, the quick-swap connections between a pair of qubit modules (e.g., modules M12 and M14) can provide lateral connections 1812-U and 1812-D from the U surface of the surface-code patch in each module to the D surface of the surface-code patch in the other module. In some embodiments, one of the modules in a quick-swap connection may initially be empty, in which case the effect of the quick-swap is to transfer the logical qubit to the empty module (thereby removing the logical qubit from the module where it originated).

[0264] To further illustrate the nature of quick swap connection 1810, FIG. 19 shows a surface code-level view of a portion of core 1510 in operation. Memory modules M1, M7, and M9 initially each store a logical qubit, while memory modules M3 and M5 are empty. A quick swap operation 1920 between modules M1 and M5 performs a horizontal swap in which the state of the surface code patch (or logical qubit) from module M1 is transferred to module M5. In this case, module M5 is initially empty (as shown in 1921); after the quick swap, module M1 is empty and module M5 now stores a logical qubit (as shown in 1925). Another quick swap operation 1930 between modules M7 and M9, both initially occupied (as shown in 1931), performs a horizontal swap in which the state of the surface code patch from module M7 is transferred to module M9, while the state of the surface code patch from module M9 is transferred to module M7 (as shown in 1935). In this way, a quick swap operation can swap logical qubits between a pair of qubit modules. A quick swap can occur between any pair of qubit modules connected by a quick swap connection, including a pair of memory modules, a pair of workspace modules, or a workspace module and a memory module.

[0265] Quick swap connections provide separately controllable couplings, i.e., at any given time, a given connection can be either open (coupling occurs) or closed (no coupling occurs). When quick swap connections are implemented using lateral physical swap gates, no more than one quick swap connection can be open at a time for a given qubit module. However, any number of quick swap connections between disjoint pairs of modules (i.e., pairs of modules such that any given module is in only one pair) can be executed simultaneously. For example, as shown in FIG. 19, quick swap operations 1920 and 1930, which operate on disjoint pairs of qubit modules, can be executed simultaneously.

[0266] Each of the port connections and quick-swap connections shown in FIGS. 16 and 18 is a direct connection between modules Mi and Mj, which does not pass through other qubit modules. In addition, each of the port sub-connections and quick-swap connections may be implemented using a separate physical connection path, allowing a qubit module to simultaneously participate in multiple port couplings (in different directions). In some embodiments, simultaneous couplings are subject to various restrictions. For example, in the example above, a qubit module can participate in no more than one quick swap during a single code cycle, and a qubit module can participate in no more than one port coupling in a given direction at a time during a single code cycle. Furthermore, in some embodiments, a qubit module cannot participate in a quick-swap coupling and a port coupling during the same code cycle. A qubit module can participate in different couplings at different times (e.g., during different code cycles).

[0267] It should also be noted that port connections and / or quick-swap connections may be provided between pairs of qubit modules that are not physically adjacent to one another. Referring to FIGS. 16 and 18, if each qubit module is implemented using a separate circuit and the circuits are arranged in a grid as shown in the figures, each qubit module has up to three physically adjacent modules. For example, module M12 is physically adjacent to modules M10, M11, and M14. In conventional quantum computer architectures, all connections between qubit modules would be “local” connections (i.e., connections between physically adjacent qubit modules, such as modules M12 and M14). As shown in FIGS. 16 and 18, the active volume architecture is not so limited; some of the quick-swap and port connections may be “non-local” connections (i.e., connections between qubit modules that are not physically adjacent). As shown, this enhanced connectivity can enable a significant reduction in the computational cost of running a given quantum circuit.

[0268] In addition to providing non-local coupling, active volume architectures can provide increased parallelism by executing different logic gates in parallel rather than sequentially. As described below in some embodiments, quantum teleportation can be utilized to allow multiple logic gates operating sequentially on the same logical qubit to be executed in parallel. The ability to execute gates in parallel can increase the throughput of an active volume core of a given size (N qubits), as will become apparent.

[0269] To summarize the above, some embodiments of an active volume quantum computer core have the following properties: (1) A network of N qubit modules for some number N. Each qubit module can store d×d surface-code patches that encode logical qubits, or d×d ancillary patches that facilitate multi-patch operations. Each patch has boundaries, including lateral boundaries (N, E, S, and W) and transverse boundaries (U and D). Not all qubit modules need to store surface-code patches at all times during a computation; some qubit modules may be empty at some times. In some embodiments, no physical qubits, measurements, or other resources are required to maintain qubit modules in an empty state. A pair of qubit modules with indices i and j are directly coupled to each other (said to be “in range”) by a port connection if |ij|≦r, and |ij|=2 k If k is 0, then they are directly coupled to each other by a quick-swap connection (said to be "quick-swappable"), and k is

[0270]

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[0271]

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[0272]

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[0273] Quantum computer cores with some or all of these properties can be implemented using a variety of physical systems and devices. Using photons as physical qubits has the advantage that photons are inherently mobile, and active optical switches and waveguides can be used to implement ports and quick-swap connections to transfer physical qubits between qubit modules. Specific examples of qubit modules implemented using photonic qubits are described in Section 3 below. However, the use of other physical systems and devices is not excluded.

[0274] 2.2. Actions using Active Volume Cores As described above, an active volume core, such as core 1510 in FIG. 15, can perform logic gates on logical qubits. The particular logic gates can be specified using instructions 1522. In some embodiments, the instructions 1522 can specify a particular configuration (open or closed) of port connections and / or quick-swap connections for the active volume core, as well as a particular physical measurement (e.g., a check operator or single-qubit measurement) to be performed by a qubit module. In some embodiments, each workspace module 1516 can be assigned a unit of computational work, referred to herein as a “logic block.” Execution of a logic block can include generating a surface code patch with appropriate port couplings to surface code patches in one or more other workspace modules 1516, and the instructions 1522 can specify the logic block to be performed by a particular workspace module 1516. The instructions 1522 can also include instructions for performing quick-swap operations between qubit modules 1512, instructions for initializing or measuring a particular logical qubit, etc. This section introduces various building blocks for instructions and operations in active volume quantum computers and concludes with some examples showing how these building blocks can be used to implement quantum computation.

[0275] 2.2.1. Logical Blocks and Logical Block Networks In an active-volume quantum computer core, such as core 1510, computations are implemented by performing gate operations on logical qubits. In particular, each workspace module 1516 can be assigned a unit of computational work, referred to herein as a "logic block." Execution of a logic block can include generating a surface code patch with appropriate port couplings to surface code patches in one or more other workspace modules 1516. This section introduces logic blocks and ways in which gate operations (the building blocks of quantum circuits) can be represented as a network of interconnected logic blocks.

[0276] Mathematically speaking, a logic block implements a linear map with 2 to 4 input and output qubits. More specifically, a "Z-block" is a linear map of the form:

[0277]

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[0278]

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[0279] Each of the n input qubits and m output qubits of the linear map is called a "port" of the logic block, and a logic block can have two, three, or four ports. Each port is associated with a specific direction in the surface code entanglement space (one of the U, D, N, S, E, and W directions defined above), and each port of the block has a different direction. Thus, assuming 2≦m+n≦4, a logic block has between two and four ports. As will become clear, in an active volume architecture, the ports of a logic block correspond to open port connections between qubit modules.

[0280] Each logic block has an "orientation," defined as follows: an "N-oriented" logic block has no ports in the N or S directions, an "E-oriented" logic block has no ports in the E or W directions, and a "U-oriented" logic block has no ports in the U or D directions. Note that some linear maps are constructed according to Equation 1. (17) or Equation (18) either have no orientation (e.g., a four-port block with ports in the U, D, N, and E directions has no orientation) or have an ambiguous orientation (e.g., a two-port block with ports in the U and D directions is both N-oriented and E-oriented). In the context of active volume quantum computing, only logic blocks with a single, well-defined orientation advance the computation, and the term "logic block" is used herein to refer to a block with a single, well-defined orientation. The output qubit is associated with the U port, and the input qubit is associated with the D port. An example of a U-oriented Z-shaped block with no input qubit is given mathematically by the following equation:

[0281]

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[0282] Input or output qubits towards the west or east port can also be affected by a Hadamard gate. An example of such an operation is a Z-shaped N-oriented block with one input qubit, given mathematically by:

[0283]

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[0284] As noted above, each logical block has a type and an orientation. Pairs of logical blocks are referred to herein as "identical" if they have the same type and the same orientation, or if they have different types and different orientations. Pairs of blocks having the same type and different orientations, or different types and the same orientation, are referred to herein as "mismatched."

[0285] A logic block can be visualized as a segment of a space-time diagram with a volume dxdxd, with two or more surfaces corresponding to unbounded ports. Figures 20A-20D show examples of space-time diagrams for 4-port, 3-port, and 2-port logic blocks. Figure 20A shows six 4-port logic blocks 2001-2006 arranged according to type and orientation. Each Z-shaped block 2001, 2003, 2005 is a visualization of a linear map in the form of Equation (17). Each X-shaped block 2002, 2004, 2006 is a visualization of a linear map in the form of Equation (18). Note that there are no other 4-port logic blocks (except for blocks with Hadamard ports).

[0286] FIG. 20B shows non-exhaustive examples of space-time diagrams of three-port logic blocks, an X-type E-oriented logic block 2021, an X-type N-oriented logic block 2022, a Z-type N-oriented logic block 2023, and a Z-type U-oriented logic block 2024.

[0287] FIG. 20C shows non-exhaustive examples of two-port logic blocks: a U-oriented X-type logic block 2041 and an N-oriented Z-type logic block 2042.

[0288] 20D shows an example of a space-time diagram of logic blocks with Hadamard ports: an X-type U-oriented logic block 2061 has a Hadamard E-port, and a Z-type N-oriented logic block 2062 has a Hadamard W-port.

[0289] As noted above, a two-port block in which both ports are aligned along the same axis has an ambiguous orientation. Figure 20E illustrates an example of a two-port block 2051 with a D port and a U port. This corresponds to the identity gate described above and is both N- and E-oriented (and therefore ambiguous). As will become clear, this type of block does not facilitate quantum computation and generally corresponds to an idle volume rather than an active volume. Identity blocks of the type shown in Figure 20E may be used to store idle qubits within a memory module. In most examples herein, the memory modules use an orientation in which the logical Z operator points in the north-south direction, as indicated by the shading of the block boundaries. However, identity blocks and other blocks with ambiguous orientations are advantageously avoided when defining and optimizing logic block networks corresponding to logic operations or quantum circuits.

[0290] It may be convenient to represent logic blocks using hexagons rather than space-time diagram segments. As shown in Figures 20A-20D, for each logic block, there is a corresponding hexagonal diagram. The corners of the hexagon are mapped to U, D, N, S, E, and W port directions, as shown in legend 2000 of Figure 20A. (This direction convention is used for all logic blocks in the diagram.) The color (or shading) of the hexagon indicates its type: Z-type is amber (light shading) and X-type is blue (dark shading). Ports of a particular direction are indicated by legs extending outward from the appropriate corner of the hexagon. For logic blocks with Hadamard ports, such as logic blocks 2061 and 2062 in Figure 20D, the Hadamard ports can be indicated using the corner "H" notation.

[0291] A gate operation acting on logical qubits can be defined as a network of logic blocks, also referred to herein as a "logic block network" or "block network." A logic block network describes a logical operation that can be implemented using surface codes and lattice operators. In a logic block network, a lattice operation corresponds to coupling corresponding ports of two logic blocks. Each port connection is a connection between two qubits at the corresponding boundary of the respective surface code patch, such that the pair of qubits at the corresponding boundary of the respective surface code patch is in a Bell state.

[0292]

number

[0293] In some embodiments, the following rules apply when forming a logical block network: (1) Ports are only connected between ports of different logic blocks that point in the same direction (for example, E-port to E-port or U-port to U-port). (2) Two blocks must be equivalent (as defined above) unless exactly one of the two ports connected between them is Hadamard. If exactly one of the two ports connected between them is Hadamard, then the two blocks must be inconsistent. (3) In a logical operation described by a logical block network, all ports in the W, S, E, and N directions must be connected to other logical blocks in the network. (4) Unconnected D(U) ports correspond to input (output) qubits of a logic operation. In some embodiments, the logic block with the input or output qubit must be either an E-oriented Z-type block or an N-oriented X-type block. A pair of connected D ports indicates that the input to the logic operation is a Bell pair.

[0294] To further explain the relationship between space-time diagrams and logic block networks, refer to FIGS. 21A-21D. FIG. 21A shows a gate diagram for a quantum circuit 2100 with eight qubits |q1〉 through |q8〉, in which logical operations, specifically Z-type Pauli product measurements on qubits |q1〉, |q5〉, and |q8〉, are performed. FIG. 21B shows the corresponding space-time diagram 2110 for executing quantum circuit 2100 in a fault-tolerant manner using a surface code to encode eight logical qubits in a conventional architecture. Inset 2112 shows the surface code patch for one time slice. Note that region 2114 does not contribute to the computation and exists only to generate surface code couplings between non-adjacent qubits |q1〉, |q5〉, and |q8〉. (In the terminology introduced above, region 2114 is considered an idle volume rather than an active volume.) Figure 21C shows a modified spacetime diagram 2110' for the execution of quantum circuit 2100, highlighting the logical blocks that contribute to the active volume. In a conventional architecture, if qubits |q1〉, |q5〉, and |q8〉 were adjacent to each other, region 2114' (corresponding to region 2114 in Figure 21B) could be omitted.

[0295] In an active volume architecture that provides port connections between surface code patches generated in non-adjacent workspace qubit modules, qubits such as |q1〉, |q5〉, and |q8〉 can be coupled without the extra computational effort of generating region 2114 by using port connections such as those described above to directly couple surface code patches corresponding to non-adjacent logical qubits.

[0296] Figure 21D shows two diagrams of a logic block network corresponding to spacetime diagram 2110', according to some embodiments. The diagram in Figure 21D uses the hexagonal notation defined above, and the mapping of spacetime regions to logic blocks follows the conventions of Figures 20A-20D. As shown in diagram 2140, each hexagon (or logic block) is assigned a sequential number, which may also refer to its position in the network. Input qubits are shown as coupled to the D ports of logic blocks numbered 1, 3, and 5, which are Z-shaped, E-oriented blocks. Output qubits are shown as coupled to the U ports of logic blocks numbered 1, 3, and 5. Logic blocks numbered 2, 4, and 6 are X-shaped, U-oriented blocks corresponding to the spacetime diagram segments in Figure 21C. Port couplings between logic blocks are shown as lines connecting ports of different hexagons. Figure 2140' shows the same logic block network as Figure 2140, introducing a numbering convention to indicate port couplings instead of actual lines, resulting in a more compact schematic. The numbers on each port identify the logical block to which the port is coupled. Because connections are always between ports pointing in the same direction, there is no need to further specify which port. Thus, diagrams 2140 and 2140' are equivalent.

[0297] In an active volume core with port bindings, a logic block network can be implemented by assigning each logic block to a different workspace module. For example, referring again to FIG. 17, block network diagram 1750 shows logic operations being performed in workspace modules M2, M4, M6, M8, and M10. Logic block 1 is assigned to module M2, logic block 2 to module M4, logic block 3 to module M6, logic block 4 to module M8, and logic block 5 to module M10. Note that the numeric identifier assigned to a logic block indicates the position of the logic block in the block network relative to other logic blocks in the block network, independent of the index of the workspace module that executes the logic block. While it is typically advantageous to assign logic blocks in a network to adjacent workspace modules (e.g., so that port bindings between logic blocks are within the port binding network), this is not required, and the first logic block (or indeed any logic block) need not be assigned to the first workspace module.

[0298] Block network diagram 1750 defines a logical operation with three input qubits (|q2〉, |q3〉, and |q5〉) and four output qubits (|q2〉, |q3〉, |q4〉, and |q5〉). There are port couplings between the W ports of blocks 1 and 2, the S ports of blocks 3 and 4, and the E ports of blocks 4 and 5, and the E port of block 4 is Hadamard. The port couplings between logical blocks in block network diagram 1750 correspond to port connections between open qubit modules. Logical blocks 1 and 2 have their W ports coupled. Thus, the W-W port connection between modules M2 and M4 is opened, and check operator measurements on physical qubits at the W boundaries of each of the surface-code patches in modules M2 and M4 are performed, as shown in 1724. Logical block 4 has an S port coupled to logical block 3 and an E port coupled to logical block 5. Thus, the SS port connection between modules M6 and M8 is opened and check operator measurements on physical qubits at the S boundaries of each of the surface code patches in modules M6 and M8 are performed as shown at 1768. The EE port connection between modules M8 and M10 is also opened and check operator measurements on physical qubits at the E boundaries of each of the surface code patches in modules M8 and M10 are performed as shown at 1781. The E port of logic block 5 is a Hadamard and M10 applies a Hadamard to the E boundaries of its surface code patches as shown at 1780.

[0299] To support the implementation of fault-tolerant logic gates using lattice operations and existing decoder techniques, an operation specified by a logic block network can last for a number of code cycles equal to the code distance d. Thus, a "logic cycle" can be defined as a period equal to d code cycles, and each qubit module can execute a logic block within a logic cycle. Different qubit modules can execute their logic blocks simultaneously, with port connections open or closed as specified by the logic block network. Because port connections have a limited range (defined by the range parameter r), the logic block network can be constrained by the requirement that port connections are only allowed within the block range limit r'. Note that if the assignment of index numbers to qubit modules follows the even / odd alternation shown in FIG. 15, the block range limit r can be smaller than the range parameter r; for example, r can be r / 2.

[0300] Numerous additional examples of logic block networks are described below. It should be understood that any logic block network can specify a set of operations for qubit modules within an active volume core, and the logic block network can be interpreted and executed in the manner shown in FIG.

[0301] 2.2.2. Quantum circuits as logical block networks As described above, logic block networks can implement gate operations on logical qubits. To determine an appropriate logic block network for a particular gate operation, it can be useful to represent the gate operation as a linear map between qubits. ZX calculus (described in B. Coecke and R. Duncan, "Interacting quantum observables: categorical algebra and diagrammatics," New Journal of Physics 13, 043016 (2011)) provides a useful graphical language for linear maps between qubits, which can be used to describe and optimize quantum circuits as well as surface code operations. The graphical language of ZX calculus can also be used to facilitate the definition and optimization of logic block networks corresponding to particular gate operations. To facilitate understanding of the present disclosure, the following brief overview of relevant aspects of ZX diagrams and conversion tools is provided.

[0302] A ZX diagram (sometimes called a "spider diagram") consists of vertices, edges connecting pairs of vertices, and edges connecting to only one vertex. The vertices in a ZX diagram are called "spiders," and each edge (or "leg") connected to a vertex corresponds to a port. Figure 22A shows examples of ZX diagrams 2201-2203. (All spiders in the figures herein are phase-free spiders. A spider with n+m ports represents a linear map with n inputs and m outputs. A Z spider, such as ZX diagram 2201, corresponds to the linear map in equation (17) above. An X spider, such as ZX diagram 2202, corresponds to the linear map in equation (18) above. Note that spiders are explicitly associated with logic blocks, but unlike logic blocks, spiders are not limited by the constraint 2≦m+n≦4. In the figures herein, Z spiders are indicated by amber (or light) shading, and X spiders are indicated by blue (or dark) shading. Spiders can have Hadamard ports that correspond to linear maps such as equation (19) above. ZX diagram 2203 shows an example of a Z spider with Hadamard ports, indicated by an H symbol on the appropriate legs.

[0303] Another definition of a ZX spider relies on operators rather than states. In this definition, the spider can represent a stabilizer state projection, and each n-port spider describes n stabilizer generators on n qubits. A stabilizer generator (X) spider described by Z is

[0304]

number

[0305]

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[0306] Similar to space-time diagrams, ZX diagrams can be used to represent logical operations on logical qubits. For example, referring again to Figure 21B, ZX diagram 2115 corresponding to a three-qubit Z measurement in space-time diagram 2110 is also shown.

[0307] One useful aspect of ZX computation is that ZX diagrams can be manipulated according to various geometric transformation identities. Figure 22C shows the transformation identities used in this disclosure. As shown in 2221 and 2222, two connected spiders of similar type (Z or X) can be merged into a single spider. These identities run in both directions, and a spider can be split into two connected spiders of similar type. As shown in 2224, an X spider can be converted to a Z spider (or vice versa) by reversing the Hadamard or non-Hadamard status of each port. As shown in 2226, a Z spider with only two edges and an X spider with only two edges are each equivalent to a direct connection.

[0308] These transformation identities can be used in optimizing the logical block network for the active volume architecture. For example, referring again to FIG. 21B, ZX diagram 2115 is shown corresponding to space-time diagram 2110. FIG. 21C shows ZX diagram 2115' corresponding to space-time diagram 2110'. ZX diagram 2115' can be derived from ZX diagram 2115 by applying transformation identities 2222 to reduce the number of X-spiders. (Note that ZX diagram 2115' can be further optimized, as described below.)

[0309] Elements of quantum circuit models can also be represented using ZX diagrams. Figure 22D shows an example of the identity between circuit elements used herein and the corresponding ZX diagrams. CNOT gate 2261 corresponds to ZX diagram 2271, which has a three-port Z spider coupled to a three-port X spider. X-basis measurement gate 2262 corresponds to Z spider 2272 with one input port and no output port, and Z-basis measurement gate 2263 corresponds to X spider 2273 with one input port and no output port. Single-qubit Hadamard gate 2264 corresponds to Hadamard port 2274. Initialization of a qubit in the |+〉 state (circuit symbol 2265) corresponds to Z spider 2275 with no input ports and one output port, and initialization of a qubit in the |0〉 state (circuit symbol 2266) corresponds to X spider 2276 with no input ports and one output port.

[0310] Each connection between two spiders corresponds to a Bell state projection, i.e., two qubits i and j, and corresponds to two ports, which is a projection Z i Z j =X i X j =+1. A composite ZX diagram with n unconnected ports also describes n stabilizer generators on n qubits, with four stabilizer generators in the two spider diagrams shown in Figure 22E.

[0311] In the following examples, the transformation of a quantum circuit into a ZX diagram depends on the circuit identity shown in Figure 22D, and the simplification of the ZX diagram depends on the transformation identity shown in Figure 22C.

[0312] In the operator diagram of the phase-free ZX diagram, the composite diagram describes the Clifford gate and the Pauli measurement.

[0313]

number

[0314] Using the identities in Figure 22D, it is possible to convert a quantum circuit diagram into a ZX diagram. The ZX diagram can then be converted into a "directed" ZX diagram (sometimes called a "directed spider diagram") using the following procedure. (1) The number of ports in each spider is constrained to satisfy 2≦m+n≦4, 0≦n≦4, 0≦m≦4 (the same constraints as for the logic block defined above). Spiders can be split or joined using identities 2221 and 2222 until this constraint is met. (2) The input ports in the diagram face in the D direction, and the output ports in the diagram face in the U direction. (As a guide for the eye, the ports can be drawn in the appropriate orientation on the page.) (3) Each port connection between spiders is assigned to either the NS or EW axis. (As a guide for the eye, ports can be drawn in the appropriate direction on the page.) (4) The orientation of each spider is determined using the same definitions as for logic blocks: an E-oriented spider is a spider that does not contain any ports in the W or E direction, an N-oriented spider is one that does not contain any ports in the S or N direction, and a U-oriented spider is one that does not contain any ports in the D or U direction. As with logic blocks, pairs of oriented spiders are defined to be equivalent if they have the same type and the same orientation or if they have different types and different orientations, and unequal if they have the same type and different orientations or if they have different types and the same orientation. (5) If one (but not both) of the two ports connecting two spiders is not Hadamard, then the two connected spiders must be equivalent; otherwise, they must be unequal. To satisfy this requirement, additional spiders can be introduced (using transformation identities 2221 and 2222).

[0315] The oriented ZX diagram can then be converted into the hexagonal representation of logic blocks introduced above by converting each spider into a hexagon and connecting the ports pointing in the same direction. In this way, any quantum circuit diagram can be converted into a logic block network diagram. The following example illustrates this method.

[0316] Figure 23 illustrates the conversion process for a CNOT gate according to some embodiments. Circuit diagram 2310 of a CNOT gate shows two qubits labeled |c〉 and |t〉 (for "control" and "target"). Per circuit identity 2261, circuit diagram 2310 is equivalent to ZX diagram 2320. ZX diagram 2320 can be converted to oriented ZX diagram 2330 using the procedure described above. As a guide to the eye, ZX diagram 2320 can be rotated 90° as shown in diagram 2320' so that the input qubit is pointing down on the page, the output qubit is pointing up on the page, and bond 2326 is oriented along the N-S axis. It is clear from diagram 2320' that spider 2321 is a Z-shaped, E-oriented spider and spider 2322 is an X-shaped, E-oriented spider. Therefore, spiders 2321 and 2322 are not equivalent, and an additional spider should be added.

[0317] Oriented ZX diagram 2330 shows a modified set of spiders. Spiders 2331 and 2332 are obtained by applying transformation identity 2221 to spider 2321. Spider 2331 is a Z-type E-oriented spider, and spider 2332 is also a Z-type E-oriented spider. Spiders 2335 and 2336 are obtained by applying transformation identity 2222 to spider 2325. Spider 2335 is an X-type N-oriented spider, and spider 2336 is also an X-type N-oriented spider. Therefore, all port couplings are between equivalent spiders.

[0318] The oriented ZX diagram 2330 is not directly a logic block network, as it may suggest connections between, for example, E and W ports. Instead, it is intended as a guide to the eye. Each spider in the oriented ZX diagram 2330 is assigned the number of its corresponding logic block (1 through 4). Therefore, converting the oriented ZX diagram 2330 into a logic block network diagram 2340 is straightforward.

[0319] In some embodiments, the active volume of a logical operation can be determined by counting the logical blocks in the corresponding logical block network. Thus, CNOT gate 2310 has an active volume of four blocks.

[0320] Figure 24 illustrates the conversion of a single-qubit Hadamard gate into a logic block network, according to some embodiments. Circuit diagram 2410 shows a qubit |q〉 entering and leaving the Hadamard gate. The corresponding oriented ZX diagram 2430 and logic block network diagram 2440 are shown. The single-qubit Hadamard gate has an active volume of three blocks.

[0321] FIG. 25 illustrates a two-qubit

[0322]

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[0323] Also, note that the active volume of a large circuit may be smaller than the total active volume of its component operations. For example, the active volume of two CNOT gates is 8 blocks, but

[0324]

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[0325] As another example, Figures 26A and 26C illustrate a conversion process for a four-qubit Z-type measurement, according to some embodiments. Gate diagram 2600 shows a four-qubit gate. As shown in circuit diagram 2610, gate 2600 can be represented as four CNOT gates 2611-2614 including an ancilla qubit 2616, followed by a Z measurement 2618 of the ancilla qubit (similar to circuit 2510 in Figure 25). Circuit 2610 can be converted to ZX diagram 2620, which is equivalent to ZX diagram 2625. As shown in Figure 26B,

[0326]

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[0327] 26E shows a generalized logic block network template for measurement of an arbitrary weight w multi-qubit Z operator according to some embodiments. Using the three-block segment of FIG. 26E, a weight w measurement is

[0328]

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[0329] Similarly, any gate operator can be represented as a logic block network. Additional examples of gate operators and corresponding logic block networks are described below.

[0330] 2.2.3. Preparing and Measuring Logical Qubits As described above, logic block networks define gate operations on input qubits and generate output qubits. In some embodiments, the input and output qubits for logic block networks implemented in an active volume architecture can be managed using memory modules of the active volume cores.

[0331] Before a (logical) qubit can be operated on, the qubit must be initialized. In some embodiments, any qubit module that is empty can initialize a qubit in a Pauli X eigenstate |0〉 or a Pauli Z eigenstate |+〉 within one code cycle. The X or Z basis can be specified in the instruction to initialize the qubit in a particular qubit module. In some embodiments, the qubit can be initialized in a memory module and then quick-swapped into a workspace module as an input to the logic block network. However, as mentioned above, the workspace and memory module can be implemented using the same hardware, and the qubit can be initialized in either the workspace or the memory module as needed.

[0332] Additionally, in some embodiments, a pair of logical qubits can be converted to a Bell state within one code cycle using the pair of qubit modules, provided that the qubit modules are in range and initially empty.

[0333]

number

[0334] In addition to these states, it may be desirable to prepare the qubit in other logical states, e.g., the T state

[0335]

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[0336]

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[0337] Once initialized, if the initial qubit module and the target qubit module are quick-swappable, the logical qubit in the initial qubit module can be quick-swapped into the "target" qubit module within one code cycle. For example, a qubit initialized in a memory module can be quick-swapped into a workspace qubit module. As described above, the quick-swap connection for a given qubit couples to the D-port of the target module, matching the association of the D-port with the input qubit in the logic block. If the quick-swap is implemented using a lateral physical swap, quick-swapping a logical qubit from a memory module to a workspace module has the side effect of quick-swapping any state that may exist in the workspace module. This is not an issue as long as you keep track of which logical qubits (or other states) are in which modules.

[0338] An output qubit produced by executing a logic block can also be quick swapped, for example, to move the output qubit from a workspace module to a memory module. In this case, the U port of the workspace module couples to the D port of the memory module, matching the association of the U port with the output qubit in the logic block. If the quick swap is implemented using a lateral physical swap, then quick swapping a logical qubit from a workspace module to a memory module has the side effect of quick swapping to the workspace module any state that may be present in the memory module. Again, this is not an issue if one keeps track of which logical qubits (or other states) are in which modules.

[0339] Quick swaps can also be used to rearrange qubits within memory modules. For example, FIG. 19 illustrates using quick swaps to rearrange qubits within memory modules. An instruction to perform a quick swap can specify a pair of modules to perform the quick swap on, or an instruction to perform multiple quick swaps can specify two or more disjoint pairs of modules to perform separate quick swaps on. Such instructions can be illustrated using a quick swap diagram 1950, in which the quick swap is indicated using an arrow; by convention, the quick swap diagram shows the contents of the qubit modules after the quick swap (the previous state can be inferred from the arrow). Thus, in quick swap diagram 1950, double-ended arrow 1951 indicates a quick swap between memory module M7, which initially stored qubit |q〉, and module M9, which initially stored qubit |q〉. The quick swap can be implemented as described above, such that after the quick swap, module M7 stores qubit |q〉 and module M9 stores qubit |q〉. Single arrow 1652 indicates a quick swap involving an empty memory location, memory module M1, which initially stored qubit |q1〉, with memory module M3, which was initially empty. The quick swap can be implemented as described above, and after the quick swap, module M3 stores qubit |q1〉 and module M1 is empty.

[0340] A quick swap between memory modules can occur during a logic cycle while a workspace module is executing a logic block. A quick swap between a memory module and an idle workspace module can also occur while another workspace module is executing a logic block; however, in the ideal case, the workspace module is not idle.

[0341] As described above, quick swaps can be completed within a code cycle. Quick swaps between disjoint pairs of qubit modules, such as the module pair (M1, M3) and (M7, M9) in FIG. 19, can occur simultaneously (in the same code cycle). Because a logical cycle has a duration of d code cycles, it is possible to perform up to d layers of quick swaps during one logical cycle, thereby rearranging the qubits in the memory modules to the desired arrangement for the next logical cycle. In some embodiments, quick swaps can enable the active volume core to proceed from one logical cycle to the next without incurring additional delay cycles to rearrange the qubits in the memory.

[0342] Logical qubits may also be measured to determine their final state. Measurement of a logical qubit may be implemented by performing a single-qubit measurement on each physical qubit. The results can be interpreted using classical (binary) logic, for example by running a surface code decoder algorithm, to determine the state of the logical qubit. In some embodiments, a logical qubit can be measured in either the X or Z basis within one code cycle. In some embodiments, a pair of qubits stored in modules i and j that are in range can participate in a Bell basis measurement within one code cycle via UU port coupling. (As discussed above, Bell basis measurements are performed using the two-qubit Pauli operator

[0343]

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[0344] In some embodiments, instructions to the quantum computer can specify when to measure a particular qubit (or pair of qubits) and which basis to use. In some cases, the selection of a metric (e.g., an X, Z, or Bell measurement) for a later measurement depends on the results of one or more earlier (logical) measurements. Such a "reactive" measurement involves (1) performing an appropriate set of measurements on the physical qubits (single-qubit X or Z or two-qubit Bell basis measurements), (2) determining a logical measurement result from the set of measurements (e.g., using a classical surface code decoder algorithm), (3) using the logical measurement result to determine a metric for the later (reactive) measurement, and (4) sending the appropriate instruction to the active volume core to perform the later measurement, all with a reaction time τ. r In certain embodiments, the reaction time τ r depends on a variety of factors, including the rate at which physical measurements can be performed, the speed of the decoder algorithm, and the rate at which new instructions can be generated (or selected) and sent to the active volume quantum computer core. In some cases, reaction time affects the throughput of the active volume quantum computer, and additional examples are described below.

[0345] 2.2.4. Quantum Computation A quantum computer with an active volume core, such as core 1510 of Figure 15, can perform a computation by executing a sequence of logical cycles. During each logical cycle, a workspace module can execute a logical block (one logical block per workspace module), and a memory module can perform a quick swap to rearrange qubits in memory in preparation for a subsequent logical cycle. Quick swaps between memory modules and workspace modules can occur during a logical cycle.

[0346] FIG. 27 shows a flow diagram of a process 2700 for performing a quantum computation in an active volume quantum computer core (such as core 1510 of FIG. 15 ), according to some embodiments. Process 2700 assumes that the quantum computation is represented as one or more logical block networks. At block 2702, logical qubits may be initialized in memory modules. The number of logical qubits and their initial states depend on the particular computation. At block 2704, quick swaps between memory modules and workspace modules may be performed. For example, if logical qubits are initialized in memory modules, one or more of the logical qubits can be quick swapped into workspace modules to provide input qubit(s) for the logic block network. At block 2706, a logic cycle may be executed. During the logic cycle, at block 2712, each workspace module may execute a logic block. As described above, executing a logic block may include generating surface code patches and selectively opening port connections to couple the surface code patches at appropriate boundaries specified by the logic block network. While the workspace module is executing the logic block, the memory module may perform zero or more layers of quick swaps to rearrange the qubits in preparation for a subsequent logic cycle in block 2714. The number of layers of quick swaps during a given logic cycle is determined based on the current arrangement of the qubits in the memory and the desired arrangement for the start of the next logic cycle. It is contemplated that at least one layer of quick swaps will be performed during most logic cycles; rearranging the memory in the last logic cycle may have little benefit. At block 2720, upon completion of the logic cycle, if more logic cycles remain to be executed, process 2700 may return to block 2704 to perform a quick swap between the memory module and the workspace module and execute the next logic cycle in block 2722.With appropriate design of the quick swaps in memory at block 2714, all quick swaps between memory and the workspace at block 2704 can be achieved with a single layer of quick swaps. Process 2700 can continue to execute logical cycles in this manner until the computation is complete. After all logical cycles have been executed, the computation is complete and a final operation, including a final measurement of each logical qubit, can be executed at block 2724.

[0347] It should be appreciated that while process 2700 is being performed, core 1510 can send measurement data, including check operator measurements, single qubit measurements, and / or Bell basis measurements, in real time to classical control logic 1520. Classical control logic 1520 can apply a decoder algorithm to the measurement data as it is received and can select or modify instructions for subsequent logic cycles based on the results of the decoder algorithm.

[0348] To further illustrate process 2700, a simple example of performing quantum computations in an active volume core, such as core 1510 of Figure 15, will now be described. This example uses a small core with N=12 qubit modules and a sequence of five gate operations is chosen to illustrate some features and advantages of the active volume architecture. In practice, it is expected that the core could be significantly larger and that a greater number of gate operations could be performed.

[0349] Figure 28A shows a quantum circuit 2800 that specifies a quantum computation as a sequence of five logical gates or gate operations on six logical qubits |q1〉 through |q6〉. Figure 28B shows the logical block networks corresponding to each gate operation. Operation 1 (block network 2801) has an active volume of four blocks, operation 2 (block network 2802) has an active volume of two blocks, operation 3 (block network 2803) has an active volume of six blocks, operation 4 (block network 2804) has an active volume of two blocks, and operation 5 (block network 2805) has an active volume of three blocks. Each operation affects only a subset of the six qubits, and the specific input and output qubits for each operation are indicated in the logical block network diagram of Figure 28B.

[0350] FIG. 28C illustrates an active volume core 2810 capable of executing quantum circuit 2800 by executing logic block networks 2801-2805, according to some embodiments. Active volume core 2810 may be generally similar to active volume core 1510 and may include ports and quick-swap connections as described above. In this example, active volume core 2810 has N=12 qubit modules 2812 evenly divided between memory modules 2814 and workspace modules 2816. Qubit modules 2812 have index values ​​M1-M12 as shown. Modules with odd indices are memory modules, and modules with even indices are workspace modules.

[0351] 28D-28F illustrate "storyboard" diagrams of executing a specified quantum computation by circuit 2800 using process 2700, according to some embodiments. As used herein, a storyboard diagram provides a series of "snapshots" that schematically show the state of an active volume core at different times during the execution of a quantum computation (e.g., using process 2700). It should be understood that the snapshots are selected to highlight particular features, and that the elapsed time between successive snapshots need not be uniform.

[0352] As Figures 28D-28F show, five logic operations are executed in three logic cycles. In each logic cycle, the goal is to execute as many logic blocks as possible, provided that enough workspace modules are available, and multiple logic block networks execute simultaneously (i.e., in the same logic cycle). As noted above, each workspace module can execute one logic block within a logic cycle, so the goal in this case is to execute six logic blocks per cycle, which will fully occupy the workspace module.

[0353] Figure 28D shows a storyboard diagram for the first logic cycle. In the first logic cycle, block network 2801 (four logic blocks) and block network 2802 (two logic blocks) execute. Block network 2801 operates on qubits |q2〉 and |q5〉, and block network 2802 operates on qubits |q3〉 and |q6〉. These are disjoint subsets of qubits, so parallel execution is straightforward.

[0354] Snapshot 2821 corresponds to initialization block 2702 of process 2700. In this example, six qubits |q1〉 through |q6〉 are arranged in an optimized order across six memory modules M1 through M11. Assuming there is no precomputation, arranging the qubits may include initializing each qubit to an appropriate state using the process described above. If a previous computation has been performed, the qubits may be rearranged using quick-swap operations, as will become apparent. The optimized order may be selected so that each qubit is in a memory module that is quick-swappable with the workspace module that will next operate on the qubit.

[0355] Snapshot 2822 corresponds to block 2704 of process 2700. The qubits for operations 1 and 2 are quick swapped from the memory module to the workspace module, as shown. In these storyboard diagrams, the quick swap is represented by an arrow, and the state of the core following the quick swap is shown.

[0356] Snapshot 2823 corresponds to block 2712 of process 2700. Logic block network 2801 for operation 1 is executing in workspace modules M2-M8, while logic block network 2802 for operation 2 is executing in workspace modules M10 and M12. (The two logic blocks in network 2802 are assigned identification numbers 5 and 6 to avoid confusion with network 2801.) Logic block executions occurring in the same logic cycle are described as "concurrent" or "parallel." Logic block execution includes executing surface code check operators, as described above, and controlling port connections to establish bindings between ports of workspace modules as specified in the logic block network being executed. Logic block execution in some embodiments may consume d code cycles, or one logic cycle.

[0357] Snapshot 2824 corresponds to block 2714 of process 2700. While workspace module 2816 is executing logic block networks 2801 and 2802, memory module 2814 can perform quick swap operations to prepare memory for the next logic cycle. Because a given quick swap operation can be completed in one code cycle, memory module 2814 can perform up to d layers or stages of quick swaps during one logic cycle. In this particular case, one layer of quick swaps is sufficient to move qubit |q1〉 to memory module M1 and qubit |q4〉 to memory module M11. (The reasons for these quick swaps will become clear; quick swaps in a given layer can occur between modules that are quick-swappable as described above.)

[0358] Snapshot 2825 shows the state of core 2810 at the end of the first logic cycle. Logic block networks 2801 and 2802 have completed execution, and the output qubits are present in the workspace module. Because the computation is not complete, process 2700 returns to block 2704 for the second logic cycle.

[0359] Figure 28E shows a storyboard diagram of the second logic cycle. In the second logic cycle, operation 3 (logic block 6) is executed. In this case, operation 3 occupies the entire workspace module, so no other operations can be executed simultaneously with operation 3.

[0360] Snapshot 2841 corresponds to the second iteration of block 2704. Qubits |ql〉 and |q4〉 are quick swapped into the workspace, while output qubits |q5〉 and |q3〉 from operations 1 and 2 are quick swapped into memory. It should now become apparent that the purpose of the quick swap in the first logic cycle (in snapshot 2824) was to move qubits |ql〉 and |q4〉 to a memory module that will allow logic block network 2803 (operation 3) to execute in the second logic cycle after a single layer of quick swaps.

[0361] Snapshot 2842, corresponding to the second iteration of block 2712, shows the execution of logic block network 2803 in workspace modules M2-M12. Snapshots 2843 and 2844, corresponding to the second iteration of block 2714, show that while the workspace modules are executing logic block network 2803, they can perform two layers of quick swaps to prepare memory for the third logic cycle, ultimately moving qubit |q3〉 to memory module M5, qubit |q5〉 to memory module M9, and qubit |q6〉 to memory module M3. Note that the quick swap connections follow the log-tree network model described above, and the quick swaps are selected accordingly.

[0362] Snapshot 2845 shows the state of core 2810 at the end of the second logic cycle. Logic block network 2803 has completed execution and the output qubit is found in the workspace module. Because the computation is not yet complete, process 2700 returns to block 2704 for the third logic cycle.

[0363] Figure 28F shows a storyboard diagram of the third logic cycle. In the third logic cycle, operation 4 (two logic blocks) and operation 5 (three logic blocks) are executed to complete the computation. The third logic cycle begins with core 2810 in the state shown in snapshot 2845 (Figure 28E) and can follow immediately after the completion of execution of the logic blocks of the second logic cycle.

[0364] Snapshot 2861 corresponding to the third iteration of block 2704 shows that at the beginning of the third logic cycle, qubits |q2〉, |q6〉, and |q3〉 are swapped to workspace modules M2, M4, and M6. Snapshot 2861 corresponding to the third iteration of block 2712 shows workspace modules M2 and M4 (operation 4) executing logic block network 2804 and workspace modules M6 through M10 (operation 5) executing logic block network 2805. Workspace module M12 is idle. An idle workspace module may occur in an active volume core any time the total number of logic blocks for the logic operations executing in a particular logic cycle is less than the number of workspace modules in the core. No quick swaps are performed in the third logic cycle because there are no subsequent logic cycles to be executed. At the end of the third logic cycle, final measurements can be performed on qubits |q1〉 through |q6〉. In some embodiments, both the workspace module and the memory module include hardware for performing the final single-qubit measurement on the physical qubit of their respective surface-coded patch, and therefore there is no need to move the logical qubit to any particular module for measurement.

[0365] 27 and 28A-28F illustrate a general approach for performing quantum computations using an active volume quantum core, such as core 1510, and is not limited to any particular sequence of operations, sequence length, or size of the active volume core. Instructions, which may use classical data structures, may specify a set of logic blocks to be executed by the workspace module during each logic cycle, as well as one or more layers of quick swaps to be executed by the memory module during the logic cycle. The quick swaps may be scheduled so that, at the end of a logic cycle, a single layer of quick swaps is sufficient to transfer input qubits from the workspace to memory for the next logic cycle. Any number of logic cycles may be executed, and any number of logic block networks may be executed during a logic cycle, limited only by the number of workspace modules.

[0366] Bridge Qubits In the examples of Figures 28A-28F, successive operations operate on disjoint sets of qubits, and it is straightforward to execute multiple operations simultaneously. However, even when successive operations (or logic block networks) use overlapping sets of qubits, concurrent execution of logic block networks in an active volume architecture is still possible by introducing a "bridge qubit." Figure 29A shows a quantum circuit diagram illustrating the construction of a bridge qubit according to some embodiments. Figure 29A shows a quantum circuit 2900 in which qubit |q2〉 is involved in a first gate operation (A) 2902, which is subsequently involved in a second gate operation (B) 2904. Quantum circuit 2900' is an equivalent circuit of quantum circuit 2900. In circuit 2900', the Bell states

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[0371] The use of a bridge qubit allows two operations 2902 and 2904 to be performed in parallel (i.e., in the same logical cycle). Specifically, the original qubits |q1〉 and |q2〉 can participate in operation 2902, while qubits |B〉 and |q3〉 can participate in operation 2904 in the same logical cycle. During this logical cycle, the bridge qubit

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[0376] According to some embodiments, a bridge qubit can be used at any point in a quantum computation when it is desirable to perform two consecutive operations affecting the same qubit simultaneously (in the same logical cycle). In an active volume architecture such as that described above, creating and measuring a Bell pair are operations that can be completed in one code cycle. As described above, creating pairs of qubits in Bell states can be supported using DD port connections, and Bell basis measurements can be supported using UU port connections. Thus, use of a bridge qubit need not slow down the computation, provided that (1) the Bell pair feeding the bridge qubit is created in a pair of qubit modules that is within range, and (2) at the end of the logical cycle, the bridge qubit and other qubits on which the Bell measurement is to be performed are within range. (In some embodiments, quick swaps can be used to move the bridge qubit within range of other qubits. Specific examples in which bridge qubits can be advantageously used are described in the next section. Bridge qubits can also be useful to facilitate the rearrangement of qubits in memory in some situations; examples are provided below.)

[0377] 2.2.6. Example: Sequential Pauli Z Measurement To further illustrate the operation of an active volume quantum core, another example of the implementation of a quantum circuit using an active volume quantum core according to some embodiments will now be described.

[0378] Figure 30A shows a quantum circuit 3000 consisting of a series of Z-type measurement gates 3001, 3002, 3003 applied to eight (logical) qubits |q1〉 to |q8〉. While a typical quantum computation generally involves operations other than Z-type measurement gates, consideration of circuit 3000 reveals various features and advantages of the active volume architecture.

[0379] FIG. 30B illustrates an active volume core 3010 capable of executing a quantum circuit, such as quantum circuit 3000, according to some embodiments. Active volume core 3010 may be generally similar to active volume core 1510 and may include qubit modules 3012. In this example, active volume core 3010 has N=22 qubit modules 3012 evenly divided between memory modules 3014 and workspace modules 3016. The qubit modules 3012 have index values ​​M1 through M22, as shown. Modules with odd indices are memory modules, and modules with even indices are workspace modules. Modules 3012 are connected by a log tree network of quick-swap connections and a network of port connections within range r.

[0380] The first gate 3001 is a Z-type Pauli product measurement on three logical qubits |q1〉, |q5〉, and |q8〉. This is a weight-3 multi-qubit Z-type measurement, and an optimized logic block network can be derived using the specifications of Figure 26E. The resulting logic block network 3011 is shown in Figure 30C. Logic block network 3011 has an active volume of five blocks, which can be assigned to workspace modules M2 through M10 in the first logic cycle.

[0381] Referring again to Figure 30A, the second gate 3002 is a Z-type Pauli product measurement on two logical qubits |q5〉 and |q7〉. The corresponding logic block network 3012 is shown in Figure 30C. Network 3012 can be derived as described above with reference to Figure 25. Logic block network 3012, with an active volume of two blocks, can be assigned to workspace modules M12 and M14 in the first logic cycle.

[0382] Note that gates 3001 and 3002 both operate on qubit |q5〉. As mentioned above, a bridge qubit can be used to parallelize the execution of gates 3001 and 3002, and logic block network 3012 can be assigned to workspace modules M12 and M14 in the first logic cycle. (The role of the bridge qubit is explained below.)

[0383] The third gate 3003 is a 7-qubit Z-type Pauli product measurement involving all qubits except |q₈. According to the definition derived above with reference to Figure 26E, a measurement of weight 7 is

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[0385] While it is possible to wait and execute gate 3003 in the second logic cycle, it is useful to note that the operation of gate 3003 can be divided into two subcircuits that can be implemented using different logic block networks: one of the logic block networks can be small enough (four blocks in this case) to execute in the first logic cycle using the four available workspace modules in core 3010, and the other logic block network for gate 3003 executes in the second logic cycle.

[0386] Figure 31 shows an example of splitting the operation of gate 3003 into two sub-circuits, according to some embodiments. It is observed that in this example, the operation of gate 3003 is equivalent to the operation of circuit 3110 followed by circuit 3112. Circuit 3110 produces an ancilla qubit |a〉 as output 3113, which is input to circuit 3112 and ultimately measured as shown by Z measurement circuit 3114. Using ZX diagrams 3120 (corresponding to circuit 3110) and 3122 (corresponding to circuit 3112) and translating them into logic block diagrams 3130 and 3132, gate 3003 can be executed by assigning 4-block network 3130 to workspace modules M16-M22 in the first logic cycle and assigning 9-block network 3132 to workspace modules M2-M18 in the second logic cycle. Note that in this case, the division between circuits 3110 and 3112 is defined such that circuit 3110 operates on qubits |q2〉 and |q3〉 that are both idle in gate operations 3001 and 3002, and circuit 3112 operates on the remaining qubits. (This choice reduces the need for bridge qubits, but is not required.)

[0387] The advantage of splitting the gate operation into two steps may not be immediately apparent in this example because circuit 3000 does not include any further operations after gate 3003. However, if there are subsequent operations, a policy of having all workspace modules occupied by logic blocks in every logic cycle can significantly reduce computation time.

[0388] 32A and 32B illustrate a storyboard diagram of the execution of a circuit 3000 within a core 3010 according to some embodiments. The circuit 3000 can be executed using the process 2700 described above. FIG. 32A illustrates a storyboard diagram of the first logic cycle, in which the first four block steps of gate operation 3001, gate operation 3002, and gate operation 3003 execute in parallel. Snapshot 3201 shows the initial state of eight qubits |q1〉 to |q8〉 arranged in an optimized order across eight memory modules M1 to M21. This order is selected to facilitate quick swaps between memory modules and workspace modules, as will become apparent. Assuming there is no precomputation, arranging the qubits can include initializing each qubit to the appropriate state using the process described above. If a previous computation has been performed, the qubits can be rearranged into the optimized order using a quick swap operation. The optimized order may be selected so that at the end of a given logic cycle, each memory qubit is in a memory module that is quick-swappable with the workspace module that operates on the qubit during the next logic cycle.

[0389] In snapshot 3202, the qubits for gate operation 3001 (which affect qubits |q1〉, |q5〉, and |q8〉) are quick swapped into workspace modules as shown. For gate operation 3002, which affects qubits |q5〉 and |q7〉, qubit |q7〉 is quick swapped into workspace modules as shown. However, qubit |q5〉 is already involved in gate operation 3001. Therefore, bridge qubits, such as those described above, are used to enable parallel execution of gate operations 3001 and 3002. Specifically, the pair of qubits |B1〉 and |q8〉 are quick swapped into workspace modules as shown.

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[0392] In snapshot 3203, logic block network 3011 for gate operation 3001 executes in workspace modules M2 through M10, logic block network 3012 for gate operation 3003 executes in workspace modules M12 and M14, and logic block network 3130 for the first portion of gate operation 3002 executes in workspace modules M16 through M22. In this manner, each workspace module has a logic block to execute, and throughput is maximized. As described above, execution of a logic block includes executing surface code check operators and controlling port connections to establish bindings between ports of workspace modules specified in the logic block network being executed. Execution of a logic block in some embodiments may consume d code cycles, or one logic cycle.

[0393] In snapshots 3204, 3205, and 3206, while workspace modules M2 through M22 (even-numbered) are executing their respective logic blocks, memory modules M1 through M21 (odd-numbered) can perform quick swap operations to prepare memory for the next logic cycle. Because a given quick swap operation can be completed in one code cycle, memory modules M1 through M21 can perform up to d layers or stages of quick swap during one logic cycle. In this case, three layers of quick swap are performed. At the end of the logic cycle, the bridge qubit

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[0398] In addition to these quick swaps, snapshot 3203 also includes the second Bell pair, qubits |B2〉 and

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[0403] Snapshot 3207 shows the state of core 3010 at the completion of a logic block in a workspace module. Output qubit |q1〉 is available in workspace module M2, and output qubit |q1〉 in workspace module M6

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[0406] Snapshot 3208 shows the bridge qubit

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[0411] More generally, the Bell pair |B2〉 and

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[0415] Figure 32B shows a storyboard diagram for the second logic cycle. In the second logic cycle, the remaining steps of gate 3003 (logic block network 3132) are executed using workspace modules M6-M22. Workspace modules M2 and M4 are idle because this is the end of the computation. In this case, the assignment of logic blocks to workspace modules is based on the ease of rearranging qubits in memory.

[0416] Snapshot 3221 shows that at the beginning of the second logic cycle, qubits |q8〉, |q2〉, and |q3〉 are quick swapped from memory to workspace modules M8, M16, and M20, while qubit |q5〉 is quick swapped from workspace module M12 to workspace module M10. This example shows that quick swaps can be used advantageously when a pair of workspace modules is quick-swappable. Qubit |q7〉 and ancilla qubit |a〉 remain in workspace modules M14 and M22.

[0417] Snapshot 3222 shows workspace modules M6-M22 executing logic block network 3132. Since there are no further operations to be performed and no bridge qubits are involved in the second logic cycle, the qubits in memory can remain in place.

[0418] Snapshot 3223 shows the state of core 3010 at the end of execution circuit 3000. Logical qubits |q1〉 through |q8〉 are available for final measurement or for subsequent operations, as desired.

[0419] It should be understood that this example is illustrative and illustrates various features of the active volume core, including the use of bridge qubits to speed up computations by increasing parallelism and by teleporting qubits from one module to another. In this example, two logical cycles are required because the number of logical blocks to be executed exceeds the number of workspace modules in core 3010. Given a larger core (i.e., more qubit modules), gates 3001-3003 may execute in a single logical cycle using additional bridge qubits. It is anticipated that in practical applications, active volume cores may include significantly more than 22 qubit modules. Some quantum algorithms require hundreds or thousands of logical qubits, and the active volume core design may be scaled to support such algorithms. (Some considerations related to scaling and performance are addressed below. Any number of bridge qubits can be introduced into a logical cycle, and any number of gate operations can be performed in parallel, limited only by the number of workspace modules in a particular core. As the previous example shows, gate operations can be split into multiple steps to maximize the use of workspace modules in each logical cycle. Although not shown in this example, it should be understood that operations on disjoint sets of qubits can be reordered to better fit into the workspace.

[0420] 2.3. Implementation of specific subroutines Many quantum computations can be defined as a sequence of quantum subroutines, where the subroutines implement specific computational steps. Examples of quantum subroutines known in the art include Pauli product rotation, Pauli product measurement, Toffoli gates, adders, data loaders, and magic state distillations. Those skilled in the art will recognize many applications for these quantum subroutines.

[0421] Using the techniques described above, any quantum subroutine that can be expressed as a quantum circuit can be converted into a logic block network that can be executed using an active volume quantum computer. For example, it is possible to convert any quantum circuit diagram into a ZX diagram, apply orientation rules to the ZX diagram (as described above), and then convert the oriented ZX diagram into a logic block network.

[0422] To further illustrate various features and advantages of the active volume architecture, exemplary implementations of specific quantum subroutines as logic block networks are presented. The examples selected herein include subroutines commonly used in quantum algori...

Claims

1. 1. A system comprising: a plurality of qubit modules, each qubit module including circuitry configured to operate on a plurality of physical qubits to generate a topological code patch for a logical qubit during each of a plurality of code cycles, each topological code patch having a plurality of boundaries associated with different directions in entanglement space; a plurality of quick swap connections, each quick swap connection selectively operable to couple a pair of the qubit modules and swap a respective logical qubit between the pair of the qubit modules within one code cycle, the quick swap connections coupling each of the qubit modules to two or more other qubit modules.

2. 10. The system of claim 1, wherein the quick swap connections include at least one quick swap connection coupling a pair of qubit modules that are not physically adjacent to one another.

3. 10. The system of claim 1, wherein the quick swap connections couple at least one of the qubit modules to at least four other qubit modules.

4. 10. The system of claim 1, wherein each quick swap connection implements a lateral swap gate for a physical qubit in the respective topological code patch of the pair of qubit modules.

5. 10. The system of claim 1, further comprising: classical control logic coupled to the quick swap connections and configured to selectively enable or disable operation of each of the quick swap connections.

6. The plurality of qubit modules includes a number (N) of qubit modules, each qubit module having an identification index ranging from 1 to N, and the plurality of quick swap connections include: [Equation 1] So that |i−j|=2 for all integer k. ｋ 10. The system of claim 1, comprising a quick-swap connection coupling each pair of qubit modules having identification index values ​​i and j such that:

7. 10. The system of claim 1, wherein the quick swap connections are configured such that swaps can be performed simultaneously for two or more disjoint pairs of qubit modules.

8. 10. The system of claim 1, wherein the physical qubits are photonic qubits and each quick-swap connection comprises an optical waveguide.

9. 1. A method comprising: providing a plurality of qubit modules, the plurality of qubit modules including a plurality of workspace qubit modules and a plurality of memory qubit modules, each qubit module including circuitry configured to operate on a plurality of physical qubits to generate a topological code patch for a logical qubit during a code cycle; storing a logical qubit in each of at least a subset of the memory qubit modules; performing, during a first code cycle, one or more quick swap operations between memory qubit modules and workspace qubit modules, each quick swap operation swapping a current state in one of the workspace qubit modules with a logical qubit in one of the memory qubit modules; and executing a logic cycle comprising a plurality of code cycles, wherein executing the logic cycle comprises: executing a plurality of logic blocks corresponding to one or more logic gate operations on one or more logical qubits in the plurality of workspace qubit modules, wherein executing the logic blocks includes generating topological code patches for different logical qubits in at least two of the workspace qubit modules and performing an entanglement operation between the topological code patches in the different workspace qubit modules; concurrently with executing the plurality of logical blocks, performing one or more additional quick swap operations between memory qubit modules, each additional quick swap operation swapping a respective logical qubit between a pair of memory qubit modules within one code cycle.

10. 10. The method of claim 9, wherein at least one of the additional quick swap operations is performed between a pair of non-adjacent memory qubit modules.

11. performing the one or more additional quick swap operations executing a first group of one or more quick swap operations during a first code cycle of the logic cycle; and executing a second group of one or more quick swap operations during a second code cycle of the logic cycle.

12. 10. The method of claim 9 , further comprising performing one or more quick swap operations between the memory qubit module and the workspace qubit module to perform a plurality of logic cycles by repeatedly performing the acts of performing a logic cycle.

13. 13. The method of claim 12, wherein the one or more additional quick swap operations between memory qubit modules performed during a first logic cycle result in rearranging logical qubits within the memory modules in preparation for a subsequent logic cycle.

14. 1. A system comprising: a plurality of qubit modules, each qubit module including circuitry configured to operate on a plurality of physical qubits to generate a topological code patch for a logical qubit during each of a plurality of code cycles, each topological code patch having a plurality of boundaries associated with different directions in entanglement space; a plurality of quick swap connections, each quick swap connection selectively operable to couple a first one of the qubit modules to a second one of the qubit modules and transfer a logical qubit from the first qubit module to the second qubit module in one code cycle, the quick swap connections coupling each of the qubit modules to two or more other qubit modules.

15. 15. The system of claim 14, wherein for at least one of the quick-swap connections, the first qubit module and the second qubit module are not physically adjacent to one another.

16. 15. The system of claim 14, wherein the quick-swap connections couple at least one of the qubit modules to at least four other qubit modules.

17. 15. The system of claim 14, wherein the quick swap connection is configured such that swaps can be performed simultaneously for two or more disjoint pairs of first and second qubit modules.

18. 15. The system of claim 14, further comprising: classical control logic coupled to the quick swap connections and configured to selectively enable or disable operation of each of the quick swap connections.

19. The plurality of qubit modules includes a number (N) of qubit modules, each qubit module having an identification index ranging from 1 to N, and the plurality of quick swap connections include: [Equation 2] So that |i−j|=2 for all integer k. ｋ 15. The system of claim 14, comprising a quick-swap connection coupling each pair of qubit modules having identification index values ​​i and j such that

20. 15. The system of claim 14, wherein the physical qubits are photonic qubits and each quick-swap connection comprises an optical waveguide.

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