Multi-qubit quantum error correction

Abstract

A method of performing quantum error correction at a decoding system of a quantum computing system wherein a quantum error correction code (QEC) is represented by a hypergraph (i.e. a graph connecting

Description

Field of the invention The present invention relates to quantum error correction. Background Quantum computers have the potential to perform computations that would be intractable on even the most powerful classical computers. Instead of representing information using classical bits, quantum computers generally use qubits that can be in a simultaneous superposition of multiple quantum states. Qubits exhibit much higher error rates than the bits used in classical computers, and quantum computers therefore require the use of quantum error correction in order to identify and correct qubit errors. The inherently delicate nature of quantum states means that quantum error correction is likely to be necessary even once quantum computing technology matures. Numerous approaches to fault-tolerant quantum computation exist. One prominent approach is lattice surgery, in which entangling operations can be performed between logical qubits by selectively combining and splitting different regions of a surface code. A key advantage of lattice surgery is that it can be implemented on quantum hardware with limited connectivity between qubits, e.g. on regular arrays of qubits having degree-four connectivity. One drawback of lattice surgery is that performing entangling operations between logical qubits in regions of the surface code that are far apart requires a large number of rounds of error correction. This makes lattice surgery well-suited to quantum architectures such as superconducting qubits, which generally use fixed arrays of qubits with nearest-neighbour connectivity, where the high clock speed of superconducting qubits helps to offset the high number of error correction operations required. Another approach to fault-tolerant quantum computation is to use transversal logical gates. Transversal logical gates implement logical gates by performing corresponding physical gates on the physical qubits making up the logical qubits. For example, a transversal controlled-NOT (CNOT) gate can be performed between two logical qubits by performing CNOT gates between the physical qubits that make up those two logical qubits. An advantage of transversal gates is that they can be performed with fewer rounds of error correction compared to lattice surgery. However, transversal multi-qubit gates require direct connectivity between the physical qubits that make up the logical qubits involved in the gate, which means they are generally not well-suited to architectures with fixed connectivity. Instead, transversal logical gates are better suited to architectures such as neutral atom qubits, which allow entangling operations to be performed between arbitrary physical qubits. Whilst transversal two-qubit logical gates do not require as many rounds of error correction, existing methods for performing error correction with multi-qubit transversal logical gates either require complex hypergraph decoding techniques or require additional buffering rounds of error correction immediately before and after the transversal gates, the latter of which counteracts the inherent benefits of transversal logical gates. There is a need for high-accuracy graph-based decoding techniques that can handle transversal logical gates without requiring additional rounds of error correction. Summary of the invention According to a first aspect, there is provided a method of performing a quantum error correction code at a decoding system of a quantum computing system, the method comprising: obtaining a hypergraph representation of an error model for performing a transversal logical gate between logical qubits in the quantum error correction code; identifying one or more spanning hyperedges connecting regions of the hypergraph representation associated with different logical qubits; determining a decomposition of each of the one or more spanning hyperedges, each decomposition comprising at least one virtual edge having cardinality-two connecting nodes of the hypergraph representation associated with successive timesteps of the QEC code; and generating, using the decomposition of each of the one or more spanning hyperedges, a decoding graph for each logical qubit. The resulting decoding graphs do not have any higher-order hyperedges and are unconnected (i.e. there are no edges between different decoding graphs of distinct logical qubits). This means that standard graph-based decoding approaches (such as minimum-weight-perfect matching (MWPM), union-find (UF) and clustering decoders) can be used to decode errors. In addition, each decoding graph can be decoded separately rather than having to process a single larger decoding graph (or hypergraph) that combines all logical qubits (which is not scalable to large quantum computing systems). Unlike existing approaches, the method of the first aspect also avoids introducing time-like gaps in the decoding graph (i.e. it does not sever the decoding graph), which means ensures that the code exhibits an error threshold whilst also reducing the number of rounds of error correction compared to other approaches (because approaches that sever the decoding graph generally require d (where d is the code distance) additional rounds of error correction to compensate for the time-like gap in the decoding graphs). A quantum computing system (also referred to herein as a quantum computer) is a computing system that exploits quantum mechanical phenomena (i.e. using quantum devices) to perform computations. The quantum devices may be any quantum devices capable of storing quantum information (i.e. any devices suitable for encoding information using quantum computational states). The quantum devices may be qubits. Alternatively, the quantum devices may be other devices capable of storing quantum information, such as qudits or qutrits. While the description herein will primarily refer to qubits, any reference herein to qubits should be understood to also encompass other types of quantum devices unless explicitly stated otherwise. Quantum error correction occurs at a low level in the quantum stack, so the benefits of the present invention occur at the architecture level of the quantum computer (the error correction occurs at the architecture level and is independent of the data being processed / applications being run) and makes the quantum computer run more efficiently and effectively as a computer (due to reduced logical error rates, faster syndrome extraction and reduced runtime compared to alternative approaches). A decoding system (also referred to herein as a decoder) is a classical computing system that decodes syndromes and provides one or both of (i) possible error locations (i.e. which qubits may have experienced an error), and (ii) a correction for the qubit error state (e.g. a correction for one or more encoded logical qubits states). It is possible to determine a correction during decoding without determining error locations, and the correction may be one or more bits representing whether a logical error has occurred for each logical operator of each logical qubit encoded (e.g. for each qubit, there may be a one bit representing whether a logical X error has occurred, and another bit representing whether a logical Z error has occurred). The correction can generally be tracked by a classical computer (e.g. by the decoder or a control system) and does not generally need to be applied to the quantum devices. The decoder may be a dedicated hardware device (e.g. implemented using an FPGA or ASIC or similar) or it may be a software component implemented using a CPU. The decoding system may comprise multiple decoding units capable of separately performing decoding operations (e.g. decoding all or part of a decoding graph), preferably in parallel. The decoding system may additionally comprise a controller to oversee / orchestrate the decoding process, or one of the decoding units may be responsible for such actions. A logical qubit is a qubit that encodes a logical quantum state in multiple physical quantum devices (such as physical qubits, qutrits or higher-order qudits). Each logical qubit is therefore made up of physical quantum devices. A logical gate is a gate that acts on a logical state encoded in a logical qubit. A transversal logical gate is a gate in which the same operation is performed on physical quantum devices making up a logical qubit. For example, a logical transversal CNOT gate between two logical qubits may be implemented by performing CNOT gates between the qubits making up those two logical qubits. Quantum error correction generally involves multiple rounds of syndrome extraction (also referred to as rounds of syndrome measurement). A single round of syndrome extraction may involve measuring all stabilisers of a stabiliser code. A round of syndrome extraction may also be referred to as a round of error correction. Each round of syndrome extraction may be referred to as a timestep of the QEC code; this is distinguished from timesteps of physical gates (multiple physical gate timesteps may make up a single QEC timestep). A timestep of a QEC code may therefore alternatively be referred to as a round of syndrome extraction. Unless indicated otherwise, reference herein to “timestep”, “QEC timestep” or “timestep of a QEC code” should be interpreted as a round of syndrome extraction. Nodes associated with successive timesteps of a QEC code are therefore nodes associated with (i.e. representing detectors of the QEC code in) successive rounds of syndrome extraction. A virtual edge is an edge (i.e. a hyperedge having cardinality two) between nodes that are not (already) directly connected by an edge (i.e. hyperedge having cardinality two) in the hypergraph representation (although these nodes may already be connected by higher-order hyperedges). In other words, a virtual edge is a new edge that is not already in the hypergraph representation (i.e. was not in the original hypergraph representation of the error model). Introducing new virtual edges that are not already in the hypergraph representation goes against conventional approaches to decomposing hypergraphs, which instead require there to be independent lower order error mechanisms already in the hypergraph when decomposing spanning hyperedges. Introducing these virtual edges restores components of the graph-like structure that would otherwise be missing due to the high-order spanning hyperedges. The cardinality of a hyperedge is the number of nodes connected to the hyperedge. An error model (also referred to as a detector error model) describes error mechanisms that can occur in the QEC code. A hypergraph representation of an error model uses hyperedges to represent the error mechanisms. The hyperedges may optionally be weighted. A spanning hyperedge is a hyperedge that connects regions of the hypergraph representation associated with different logical qubits. One skilled in the art will appreciate that a hypergraph representation may comprise multiple regions each associated with different logical qubits, and that nodes and hyperedges in a respective region represent detectors and error mechanisms acting on a respective logical qubit. A decoding graph is a graph (in the mathematical sense) comprising edges representing error mechanisms, and nodes (or vertices) representing differences in successive syndrome measurements (or more generally, a decoding graph comprises nodes representing detectors, which are measurement results that sum to zero (e.g. modulo 2 sum) during perfect (i.e. error-free) operation of the quantum computing system). The decoding graph may have one or more boundaries, which involve edges extending beyond the graph (e.g. to one or more virtual boundary nodes), i.e. the decoding graph may be a subgraph of a larger graph including the virtual boundary node(s)). Conventionally, some error correction literature has referred to “rough” boundaries and “smooth boundaries”. However, the “smooth” boundaries in such literature are not actually boundaries in the above sense, and they will not be referred to as boundaries in the present disclosure. Accordingly, the boundaries referred to herein are synonymous with the “rough” boundaries in such literature. A decomposition of a hyperedge involves splitting that hyperedge into lower-order hyperedges (i.e. splitting a hyperedge into multiple edges each having a cardinality lower than the cardinality of the hyperedge being decomposed / split). A component being associated with an edge means that the component was part of the same hypergraph decomposition as that edge. The method may further comprise receiving syndrome data representative of (i.e. encoding) an error state of quantum devices in the quantum computing system; and determining a correction for the error state by decoding the syndrome data using the decoding graph for each logical qubit. The syndrome data may indicate locations of defects in the quantum error correction code. The syndrome data (also referred to herein as a syndrome) may be derived from the independent outcomes, or it may be the raw independent outcomes. The syndrome data may be obtained by classical processing of the independent outcomes for each stabiliser. For example, a surface code syndrome is generally obtained by identifying changes in stabiliser values (e.g. using XOR operations between independent outcomes obtained in successive stabiliser measurement rounds for the same stabiliser). One skilled in the art will appreciate that the manner in which the syndrome data is obtained from the independent outcomes will depend upon the specifics of the quantum error correction code being implemented. A defect (also referred to as an excitation or measurement event) generally represents the end of a chain of errors in the decoding graph (the chain of errors may span both spacelike and time-like dimensions of the decoding graph). Defects are non-trivial syndrome values, and they may correspond to a change in value of a syndrome qubit measurement outcome between successive rounds of syndrome measurement. The method may further comprise receiving a logical state measurement of one or more of the logical qubits; and applying the correction to the logical state measurement. The logical state measurement may be measurement of a logical qubit in a Pauli basis, such as the computational basis (Z basis) or X basis. The logical state measurement may indicate which logical state the qubit is in (e.g. |0) or |1) for Z basis measurements), and applying the correction may involve updating the state according to the correction (e.g. flipping the state if necessary). Preferably, the one or more spanning hyperedges have cardinality of at least three. Determining a decomposition of each of the one or more spanning hyperedges preferably comprises decomposing each hyperedge into a plurality of hyperedges having cardinality less than three (e.g. into edges having cardinality two). The at least one virtual edge may be one of a time-like edge and a hook edge. A time-like edge is an edge that connects corresponding nodes in subsequent timesteps of the QEC code, i.e. nodes that are directly vertically above each other. A hook edge is an edge representing a hook error mechanism. The at least one virtual edge only connects nodes associated with the same logical qubit (i.e. the virtual edge does not span regions of the decoding hypergraph associated with different logical qubits), thereby allowing the decoding problem to be parallelised into the different decoding graph regions. The decoding graph for each logical qubit preferably comprises a plurality of cardinality-two hyperedges of the hypergraph representation, and preferably at least one decoding graph comprises at least one virtual edge. The method may further comprise storing decomposition information in a data structure associated with the decoding graph for a first logical qubit. The data structure may be a map. This decomposition information can be used to infer correlations between errors and corrections in different decoding graphs. The information may comprise an identifier of a component in the decoding graph for a second logical qubit, and the component may be associated with a virtual edge in the decoding graph for the first logical qubit. The component may be an edge or node. The virtual edge may be a key in the map, and the component may be the value associated with that key. Hyperedges of the hypergraph representation may represent error mechanisms associated with quantum operations performed on physical qubits that make up the logical qubits. Nodes of the hypergraph representation may represent detectors of the quantum error correction code. According to a second aspect, there is provided a decoding system configured to perform the method of the first aspect. According to a third aspect, there is provided a computer-readable medium comprising instructions which, when executed by a decoding system, cause the decoding system to perform the method of the first aspect. Any feature of the first aspect may be combined with the second or third aspects. The second and third aspects provide the same benefits as the first aspect. According to a fourth aspect, there is provided a method of performing a quantum error correction code at a decoding system of a quantum computing system, the method comprising: obtaining a first decoding graph associated with a first logical qubit and a second decoding graph associated with a second logical qubit, the first decoding graph comprising at least one virtual edge of a decomposition of a spanning hyperedge connecting regions of a hypergraph representation of an error model associated with the first and second logical qubits; receiving syndrome data representative of an error state of quantum devices in the quantum computing system; initialising states of nodes in the first and second decoding graphs according to the syndrome data; performing a first decoding round to identify a proposed correction involving a virtual edge in the first decoding graph; identifying a component in a second decoding graph associated with the virtual edge in the proposed correction; updating a state of the identified component in the second decoding graph in response to the proposed correction; and performing a second decoding round on the first and second decoding graphs to determine a committed correction for the error state. The parallelisability of the method of the fourth aspect means it is more scalable that existing graph-based decoding techniques, thereby facilitating fault-tolerant quantum computation with larger quantum computing systems. This parallelisability arises from identifying correlations between decoding graphs (i.e. a component in the second decoding graph associated with the correction in the first decoding graph) and updating the decoding graphs in response to these correlations (i.e. updating the state of the component in the second decoding graph). The second round of decoding is then used to account for these correlations. In some cases, additional intermediate decoding rounds may be performed between the first and second decoding rounds to identify further proposed corrections. Initialising states of the nodes may involve setting an initial defect state of each node according to the syndrome data (in other words, initialising the state of the nodes may comprise identifying defect locations in the syndrome data and setting the states of the nodes according to the identified defect locations). The proposed correction may also be referred to as a tentative correction. Edges in the proposed correction do not necessarily form part of the committed correction and will therefore not necessarily be directly used to correct subsequent logical state measurements. The committed correction is a correction that the decoder can use when correcting subsequent logical state measurements. The committed correction is not necessarily a final correction because errors in further rounds of error correction may necessitate additional corrections. Determining the committed correction may involve computing a final homology based on error mechanisms committed to during decoding rounds. A decoding graph is associated with a logical qubit if the edges in that decoding graph represent error mechanisms affecting the physical qubits (or other quantum devices) making up that logical qubit. In other words, nodes and edges in a decoding graph associated with a logical qubit represent detectors and error mechanisms acting on that logical qubit. The method may further comprise receiving a logical state measurement of at least one of the first and second logical qubits; and applying the committed correction to the logical state measurement. The error model may be an error model for a transversal logical gate between the first and second logical qubits. Preferably, the first and second decoding graphs are unconnected. Unconnected means that there are no edges connecting a node in the first decoding graph to a node in the second decoding graph. The syndrome data preferably indicates locations of defects in the quantum error correction code. The component may be an edge or node. When the component in the second decoding window is an edge, updating a state of the component may comprise flipping an error state associated with the edge. Each edge has an associated error state (which may also be referred to as a correction state) which indicates whether the decoder has identified that edge in a correction (e.g. in a proposed correction or committed correction). The method may further comprise updating (e.g. flipping) defect states of nodes connected to the edge in response to flipping the error state associated with the edge. The defect state of a node is generally based on a parity of errors / corrections on edges connected to that node, so changes in error / correction states of edges affect the defect state of connected nodes. When the component in the second decoding window is a node, updating a state of the component may comprise flipping a defect state associated with the edge. For example, a defect flag may be flipped from true to false (e.g. 1 to 0) or vice-versa. Identifying the component associated with the virtual edge in the proposed correction may comprise retrieving an identifier of the component from a data structure of the first decoding graph. The data structure may be a map. The virtual edge may be a key in the map, and the component may be the value associated with that key. Hyperedges of the hypergraph representation may represent error mechanisms associated with quantum operations performed on physical qubits that make up the logical qubits. Nodes of the hypergraph representation may represent detectors of the quantum error correction code. The method may further comprise performing a third decoding round in parallel with the first decoding round to identify another proposed correction involving one or more edges in the second decoding graph. The other proposed correction may involve another virtual edge in the second decoding graph, and the method may further comprise identifying another component in a first decoding graph associated with the other virtual edge in the other proposed correction and updating a state of the other identified component in the first decoding graph in response to the other proposed correction (the state of the other component may be updated analogously to updating the component in the second decoding graph). Advantageously, decoding both decoding graphs in parallel allows both decoding graphs to be updated when multiple transversal multi-qubit logical gates are performed in opposite directions (e.g. with the control / target qubits swapped). The second decoding round is preferably performed on the first and second decoding graphs in parallel. Decoding the decoding graphs in parallel (e.g. using multiple decoding units) ensures that the decoding time does scale in proportion to the number of logical qubits. The at least one virtual edge may be between nodes that are not directly connected by an edge in the hypergraph representation. In other words, the at least one virtual edge may be an edge that does not already exist in the hypergraph representation. Using decoding graphs with virtual edges that are not in the hypergraph representation goes against conventional approaches, which instead require there to be independent lower order error mechanisms already in the hypergraph when decomposing spanning hyperedges. Introducing these virtual edges restores components of the graph-like structure that would otherwise be missing due to the high-order spanning hyperedges. The method may further comprise updating a state of one or more nodes in the first decoding graph in response to the proposed correction. For example, the method may involve flipping defect states of nodes at ends of one or more chains of errors in the proposed correction. According to a fifth aspect, there is provided a decoding system configured to perform the method of the fourth aspect. According to a sixth aspect, there is provided a computer-readable medium comprising instructions which, when executed by a decoding system, cause the decoding system to perform the method of the fourth aspect. Any feature of the fourth aspect may be combined with the fifth or sixth aspects. The fifth and sixth aspects provide the same benefits as the fourth aspect. According to a seventh aspect, there is provided a method of performing a quantum error correction code at a decoding system of a quantum computing system, the decoding system comprising a plurality of decoding units, the method comprising: obtaining a plurality of decoding graphs associated with a plurality of logical qubits; receiving syndrome data representative of an error state of quantum devices in the quantum computing system; initialising states of nodes in the decoding graph according to the syndrome data; determining a first decoding window for a decoding graph associated with a first logical qubit and a second decoding window for a different decoding graph associated with a second logical qubit; performing, at a first decoding unit, a first round of decoding with the first decoding window to identify a proposed correction involving one or more edges in the first decoding graph; identifying, at the first decoding unit, a component in the second decoding window associated with an edge in the proposed correction; updating, at a second decoding unit, a state of the identified component in response to the proposed correction; and determining a committed correction for the error state by performing, at the first and second decoding units respectively, a second round of decoding on the first and second decoding windows respectively. The method of the seventh aspect utilises multiple decoding units to provide a windowed decoding approach that is more scalable that existing graph-based decoding techniques, thereby facilitating fault-tolerant quantum computation with larger quantum computing systems. The decoding units can decode each decoding graph separately rather than having to decoding an entire decoding graph using a single processing element, which allows for parallel decoding. This parallelisability arises from identifying correlations between decoding graphs (i.e. a component in the second decoding graph associated with the correction in the first decoding graph) and updating the decoding graphs in response to these correlations (i.e. updating the state of the component in the second decoding graph). The second round of decoding is then used to account for these correlations. In some cases, additional intermediate decoding rounds may be performed between the first and second decoding rounds to identify further proposed corrections. A decoding unit is a classical processing element capable of performing decoding tasks, e.g. decoding a decoding graph. The decoding system may further comprise a controller for performing any task not explicitly performed by a decoding unit (e.g. receiving and processing syndrome data etc.) and / or distributing / allocating such tasks (or parts of such tasks) to the processing units. Alternatively, one or more of the decoding units may be responsible for these tasks. One skilled in the art will appreciate that it is immaterial which part of the decoding system performs such tasks provided that the decoding is distributed between the decoding units as described above. A decoding window is a subset of a decoding graph, for example each decoding window may comprise a pre-set number of rounds of the decoding graph (e.g. in proportion to the code distance). One skilled in the art will appreciate that the methods herein provide a windowing technique can be used to provide space-like windowing of decoding graphs. These approaches can be combined with conventional sliding window techniques in the time-like direction (existing sliding window techniques alone can not be used to provide windowing in the space-like direction when implementing transversal multi-qubit logical gates). The method may further comprise receiving a logical state measurement of at least one of the first and second logical qubits; and applying the committed correction to the logical state measurement. Preferably, the first decoding graph comprises at least one virtual edge of a decomposition of a spanning hyperedge connecting regions of a hypergraph representation of an error model associated with the first and second logical qubits. Transversal multi-qubit logical gates lead to spanning hyperedges. Existing graph-based techniques for decoding transversal multi-qubit logical gates require additional rounds of error correction and exhibit reduced error-suppression compared to non-transversal logical gates. The method of the seventh aspect can advantageously be used to perform graphbased decoding transversal multi-qubit logical gate operations involving decompositions of spanning hyperedges. Compared to existing approaches, the method of the fourth aspect provides improved error suppression with fewer rounds of error correction. The edge in the proposed correction may be a virtual edge. The error model may be an error model for a transversal logical gate between the first and second logical qubits. Hyperedges of the hypergraph representation may represent error mechanisms associated with quantum operations performed on physical qubits that make up the logical qubits. Nodes of the hypergraph representation may represent detectors of the quantum error correction code. The at least one virtual edge may be between nodes that are not directly connected by an edge in the hypergraph representation. In other words, the at least one virtual edge may be an edge that does not already exist in the hypergraph representation. Using decoding graphs with virtual edges that are not in the hypergraph representation goes against conventional approaches, which instead require there to be independent lower order error mechanisms already in the hypergraph when decomposing spanning hyperedges. Introducing these virtual edges restores components of the graph-like structure that would otherwise be missing due to the high-order spanning hyperedges. Identifying the component associated with the edge in the proposed correction may comprise retrieving an identifier of the component from a data structure of the first decoding graph. The data structure may be a map. The virtual edge may be a key in the map, and the component may be the value associated with that key. Updating a state of the component associated with the edge may comprise transmitting the identifier from the first decoding unit to the second decoding unit. The method may further comprise performing, at the second decoding unit, a third round of decoding with the second decoding window in parallel with the first round of decoding to identify another proposed correction involving one or more edges in the second decoding graph. The other proposed correction may involve another virtual edge in the second decoding graph, and the method may further comprise identifying, at the second decoding unit, another component in a first decoding window associated with the other virtual edge in the other proposed correction and updating, at the first decoding unit, a state of the other identified component in the first decoding window in response to the other proposed correction (the state of the other component may be updated analogously to updating the component in the second decoding graph). Advantageously, decoding both decoding graphs in parallel allows both decoding graphs to be updated when multiple transversal multi-qubit logical gates are performed in opposite directions (e.g. with the control / target qubits swapped). The component may be an edge or node. When the component in the second decoding window is an edge, wherein updating a state of the component may comprise flipping an error state associated with the edge. The method may further comprise updating defect states of nodes connected to the edge in response to flipping the error state associated with the edge. When the component in the second decoding window is a node, updating a state of the component may comprise flipping a defect state associated with the edge. For example, a defect flag may be flipped from true to false (e.g. 1 to 0) or vice-versa. Preferably, the first and second decoding graphs are unconnected. Unconnected means that there are no edges connecting a node in the first decoding graph to a node in the second decoding graph. The syndrome data may indicate locations of defects in the quantum error correction code. Preferably, the second decoding round is performed by the first and second decoding units in parallel. Decoding the decoding windows in parallel using multiple decoding units ensures that the decoding time does scale in proportion to the number of logical qubits. The method may further comprise updating, by the first decoding unit, a state of one or more nodes in the first decoding window in response to the proposed correction. For example, the method may involve flipping, by the first decoding unit, defect states of nodes at ends of one or more chains of errors in the proposed correction. According to an eighth aspect, there is provided a decoding system comprising a plurality of decoding units and configured to perform the method of the seventh aspect. According to a ninth aspect, there is provided a computer-readable medium comprising instructions which, when executed by a decoding system comprising a plurality of decoding units, cause the decoding system to perform the method of the seventh aspect. Any feature of the seventh aspect may be combined with the eighth or ninth aspects. The eighth and ninth aspects provide the same benefits as the seventh aspect. It should be understood that any definition or explanation provided in relation to a feature in the context of one aspect is applicable to any that same feature in the context of all other aspects. Brief description of the drawings Examples of the present invention will now be described in detail with reference to the accompanying drawings, in which: Fig. 1 is a schematic of a quantum computing system; Fig. 2 is a gate schedule for transversal logical gates; Figs. 3a-d show sections of hypergraphs for a transversal logical gate; Fig. 4 is a flowchart of a quantum error correction method; Fig. 5 is a flowchart of another quantum error correction method; Fig. 6 is a flowchart of yet another quantum error correction method; and Figs. 7a-d illustrate decoding steps using of a quantum error correction method. Detailed description Quantum error correction (QEC) algorithms are used to detect and correct errors at the physical qubit level to mitigate against computational errors at the logical qubit level. QEC is expected to be essential for performing useful computations on early quantum computers, and the delicate nature of qubits means that QEC is likely to remain necessary even once quantum computing hardware matures. The goal of QEC is to reduce the effect of noise within a quantum computer: building in redundancies to protect fragile quantum systems. This is achieved with QEC codes that encode a number of logical qubits (one or more) into a larger number of physical qubits. If the error rate of the physical qubits is below a certain threshold associated with the QEC code being used, the logical qubits will exhibit a reduced effective error rate compared to the error rate experienced by the physical qubits. Simply put, each logical qubit will outperform the sum of its parts. The present disclosure focuses on quantum decoding. By interacting non-destructively with the encoded quantum state via auxiliary qubits (i.e. additional physical qubits that do not themselves encode logical states), it is possible to determine the signature of errors that have affected the logical state; this signature is known as an error syndrome. The process of obtaining this error syndrome, known as syndrome extraction, provides only partial information. As such, decoding algorithms are employed to determine most likely error occurrences and / or corrections (some decoding algorithms, such as some clustering algorithms, can determine a correction without determining likely error occurrences). These algorithms are typically deployed on classical computing hardware with restricted memory and / or processing capabilities. The output of a decoder is a probabilistic prediction. Given the syndrome observed, the decoder outputs an error with high associated probability that explains the syndrome, or alternatively a likely correction that will correct the error. A given family of error correction codes may have a variety of decoding algorithms to choose from; selecting the decoder is a balance between accuracy, speed, and compute budget for decoding. A more accurate decoder will be more effective at determining errors / corrections, and this will result in improved logical accuracy of the quantum computation. The decoder is therefore a key element in the performance of the QEC protocol, and therefore the quantum computation as a whole. QEC codes require hardware that can receive and process enormous amounts of error information (i.e. syndrome data) in real-time almost instantaneously. A delay in decoding can lead to the creation of a backlog that grows exponentially with the size of the computation, which will ultimately lead to failure of the quantum computation. Improvements to decoding hardware and algorithms help to prevent this backlog, thereby enabling quantum computers with higher numbers of qubits and lower error rates (faster decoders 14 can handle quantum error correction codes involving more data qubits, and using more data qubits leads to a reduction in logical error rates when performing fault-tolerant quantum computation). A schematic of an exemplary quantum computing system 100 suitable for performing the methods of the present disclosure is shown in Fig. 1. The quantum computing system 100 comprises a plurality of physical qubits 106 (unless specified otherwise, reference herein to qubits should be understood to refer to physical qubits rather than logical qubits). The qubits 106 may include data qubits used to encode logical qubit states, and auxiliary qubits (or syndrome qubits) used to perform syndrome measurements for QEC. While the exemplary quantum computing system 100 uses qubits 106, one skilled in the art will appreciate that the invention described herein is also applicable to quantum computing systems that use other quantum devices, such as qutrits and qudits. Accordingly, it should be understood that any reference herein to qubits is applicable to any type of quantum devices that can be used to encode quantum information. The qubits 106 are controlled by a control system 104 having one or more classical processors. The control system 104 transmits control signals (e.g. RF pulses) to the qubits 106 for performing operations on the qubits 106 (including measurement operations) and receives measurement information from the qubits 106. The measurement information will generally be analogue data signals, although the analogue signals may alternatively be converted to digital signals before being transmitted to the control system 104 in some implementations (e.g. the qubits 106 may be provided with one or more analogue to digital converters). The control system 104 may receive high-level instructions from an algorithmic system or similar (not shown) and convert these high-level instructions (such as logic gates) into low-level qubit instructions (e.g. microwave pulses etc.), which may be in analogue format. The quantum computing system 100 also comprises a decoding system 102 (also referred to herein as a decoder). The decoding system 102, which is generally a classical computing system, receives an error syndrome (also referred to as syndrome data) obtained from measurements of syndrome qubits. The error syndrome may comprise raw analogue measurement data, or it may alternatively be pre-processed (e.g. into digital format) by the control system 104. The decoding system 102 may be connected to the control system 104 and receive the error syndrome via the control system 104 as illustrated in Fig. 1 (potentially via one or more additional intermediary systems), or in alternative examples the decoding system 102 may be connected directly to the qubits 106 and receive the error syndrome from the qubits 106 (e.g. as raw analogue signals or digital measurement values). The decoding system 102 uses a decoding process / algorithm to decode the error syndrome to determine a correction for an error state of the qubits 106 associated with the error 15 syndrome (i.e. an error state that causes the measured error syndrome). The decoding system 102 may comprise one or more decoding units capable of performing decoding tasks, e.g. decoding part of a larger decoding problem. One of the decoding units may be responsible forcoordinating / orchestrating the decoding process between decoding units, or the decoding system 102 may alternatively comprise an additional processing unit (e.g. a CPU or controller) that manages the decoding process. One skilled in the art will appreciate that the quantum computing system 100 may also comprise additional intermediary components positioned between the illustrated components, and that the illustrated components may be connected in a different configuration (e.g. the decoding system 102 may be connected directly to the qubits 106 as previously described). Many conventional QEC schemes utilise a decoding graph when decoding error syndromes. A decoding graph is a graph comprising edges representing error mechanisms and nodes (or vertices) representing syndrome measurement outcomes or differences between successive syndrome measurements; decoding graph nodes may also be referred to as detectors. The syndrome data does not provide the exact location of errors, but it instead provides information that can be used to infer likely errors and / or corrections. For example, the syndrome data may indicate end points of strings / chains of errors. Non-trivial syndrome values (e.g. changes in value between successive syndrome measurements) are referred to as defects, excitations or detection events; the location of these defects in the decoding graph acts as a (generally non-unique) symptom of the underlying qubit errors (i.e. errors in the data and syndrome qubits). Decoding syndrome data using a decoding graph generally involves grouping these defects. Numerous graph-based decoding techniques are known, including minimum-weight-perfect-matching, union find and collision clustering. Decoding graphs work well for scenarios involving a single logical qubit (e.g. quantum memory) or when performing multi-qubit logical gates using lattice surgery. However, error mechanisms associated with multi-qubit transversal gates (such as transversal CNOT gates) introduce higher order “hyperedges” that connect more than two nodes; error models for transversal multi-qubit logical gates therefore require hypergraph representations with hyperedges that have cardinality three or more (the cardinality of a hyperedge is the number of nodes that are connected by the hyperedge - an edge is special case of hyperedge having cardinality two, and a graph is a special case of a hypergraph in which all edges have cardinality two). These hyperedges, which in the case of a transversal logical CNOT result from single errors in the syndrome extraction round before the transversal CNOT causing three defects, cannot be represented using decoding graphs and cannot be readily decomposed into edges, which presents challenges when using graph-based decoders. In particular, existing attempts to decode hypergraph error models with graph-based decoders exhibit increased logical error rates and / or require additional rounds of error correction (therefore slowing the quantum computation and offsetting inherent speed benefits provided by transversal gates). While hypergraph decoders exist for hypergraph error models having hyperedges with cardinality three or more, hypergraph decoding is much more complex than graph-based decoding (which means hypergraph decoding is generally slower than graph-based decoding) and requires visibility over the full spatial dimension of the decoding problem (which is not viable for large quantum computing systems). The methods of the present invention allow for graph-based decoding of multi-qubit transversal gates with a constant number of error correction rounds between gates (i.e. the number of rounds of error correction required between successive logical gates does not increase with increasing code distance) and provide higher error suppression (and therefore lower logical error rates) than existing approaches that use graph-based decoders to decode error syndromes arising from transversal multi-qubit logical gates. In addition, the present invention also provides parallelised graph-based decoding of transversal multi-qubit logical gates. Fig. 2 shows N stacks of logical operations 202-1 to 202-N in a multi-qubit gate schedule involving N logical qubits, with each stack of logical operations 202-1 to 202-N being associated with a single logical qubit. The illustrated schedule involves 16 error correction rounds, with each rectangle representing a single round on a given logical qubit. An error correction round involves a single round of syndrome extraction. The first round is represented by the bottom rectangle in each stack of logical operations 202-1 to 202-N, with each subsequent round being immediately above the previous round (in other words, time increases in the horizontally upwards direction of Fig. 2). Each round may involve a single-qubit transversal logical gate (e.g. a transversal single-qubit logical gate, such as a quantum memory (QMEM) / logical identity operation, logical Hadamard gate or a logical Pauli gate etc.) or a multi-qubit transversal logical gate (e.g. a transversal CNOT gate). Multi-qubit logical gates between a first logical qubit i and a second logical qubit j are denoted i <>j. In the illustrated schedule, multiple multi-qubit logical gates involving different logical qubits are performed within a few rounds. In general, error correction for a code of size d will require the decoder to process at least d rounds of error correction. When using conventional decoding techniques to decode errors with a gate schedule such as that shown in Fig. 2, a decoder would therefore need to decode errors on all of the logical qubits using a single large decoding graph, which would require enormous processor and memory capabilities. To demonstrate the scale of this problem, each pair of rectangles for a given multi-qubit gate in Fig. 2 may be associated with in excess of 10,000 unique hyperedges within a single round for reasonable sized fault-tolerant quantum computing systems. Furthermore, within d rounds, the fact that transversal gates can be applied in quick succession (i.e. multiple multi-qubit gates can be performed within d rounds, unlike logical operations implemented with lattice surgery) means that the decoding graph (or hypergraph) for single logical qubit can become interlinked with decoding graphs / hypergraphs of a large number of other logical qubits in the system. This presents major challenges when attempting to parallelise the decoding problem because the decoding graph (or hypergraph) cannot be easily split into separate regions associated with different logical qubits that can be decoded in parallel. In particular, while existing sliding window techniques can be used to divide the problem in the time-like direction, these techniques are not suitable for dividing a decoding graph (or hypergraph) into separate windows for each logical qubit. In other words, sliding window techniques would require decoding graph windows involving decoding graph regions associated with different logical qubits, which is not scalable to large quantum computing systems. The present invention provides a technique for decomposing hypergraph edges such that the decoding problem can solved using graph-based decoding techniques and can be parallelised across multiple processing units. Figs. 3a-d show sections of hypergraph representations of an error model for a transversal CNOT gate; such representations can be generated using known techniques, for example using the Stim quantum circuit simulator (arXiv:2103.02202 [quant-ph]). The error model, which may also be referred to as a detector error model, represents error mechanisms associated with performing the transversal CNOT logical gate in a fault-tolerant manner (i.e. as part of a quantum error correction code); the transversal CNOT gate is preceded and succeeded by several rounds of syndrome extraction. In particular, nodes (or vertices) 306 of the hypergraph are associated with detectors of the quantum error correction code, and each hyperedge of the hypergraph representation represents an error mechanism that affects (e.g. flips) the state of detectors connected to that hyperedge. The illustrated hypergraphs show edges (i.e. hyperedges having cardinality-two) in a layer of the hypergraph. Time can be considered to increase in the vertically upwards direction, with each vertical layer of the graph being associated with a round of syndrome measurement. A first region 302a of the hypergraph is associated with a first logical qubit (the target qubit of the transversal logical CNOT gate) and a second region 302b of the hypergraph is associated with a second logical qubit (the control qubit of the transversal logical CNOT gate). One skilled in the art will recognise that Figs. 3a-d represent cross sections of a standard decoding graph and that decoding techniques for error correction codes such as surface codes generally utilise decoding graphs with a second space-like direction (not shown). The illustrated hypergraph includes space-like edges 304a, time-like edges 304b, and hook edges 304c. The full hypergraph additionally includes hyperedges (not shown) having cardinality greater than two that span between the regions 302a, 302b of the hypergraph associated with the different logical qubits. The illustrated hypergraph also includes boundary edges 304d (also referred to as singleton edges) represented by dashed lines. The illustrated boundary edges 304d are a special instance of space-like edges that each only connect to a single detector of the error correction code. Conceptually, these boundary edge 304d can be considered to connect to a boundary node (also referred to as a virtual node). Boundary edges and boundary nodes are well-known to those skilled in the art and therefore are not elaborated upon in the present disclosure. In the illustrated decoding graph, the boundary edges are each labelled L0, L1 or L0L1; this label indicates whether the boundary edge is part of a logical operator (e.g. a logical X or logical Z operator, for example) acting upon the first logical qubit, the second logical qubit, or both logical qubits respectively. One skilled in the art will appreciate that the definition of the logical operators in a surface code is somewhat arbitrary because logical operators can be redefined by combining the stabilisers of the code. One skilled in the art will further appreciate that a full decoding graph may have additional edges that form part of the logical operator, and that logical operators need not be defined using boundary edges. The hypergraph error model may be used as a decoding hypergraph for quantum error correction. However, this either requires the use of a hypergraph decoder that can handle hyperedges having cardinality greater than two (i.e. not graph-based decoders) or requires decomposing the higher-order hyperedges into edges. Existing approaches for decomposing higher order hyperedges into edges have resulted in reduced decoding performance, which necessitates additional rounds of error correction. In particular, existing techniques lead to a gap in the time-like direction of the decoding graph where the transversal multi-qubit gates is performed (the same as shown in the second region 302b of Fig. 3a - the hypergraph is effectively severed into separate decoding graphs), and d rounds of error correction must be performed before and after the transversal gate to compensate for this gap. Fig. 3b shows nodes 310a-c of a spanning hyperedge, which is a hyperedge that connects regions of the decoding graph associated with different logical qubits (the hyperedge itself is not shown - only the nodes 310a-c connected by the hyperedge). One node 310a of the hyperedge is associated with the first region 302a of the hypergraph (i.e. associated with the first logical qubit), and the other nodes 310b, 310c of the hyperedge are associated with the second region 302b (i.e. associated with the second logical qubit). This hyperedge cannot be decomposed into a combination of existing edges of the hypergraph without severing the decoding graph. The method of the present disclosure overcomes this problem by introducing new virtual edges (i.e. edges that are not in the hypergraph representation of the error model, in other words the virtual edges are between nodes of the hypergraph that are not connected by edges) connecting nodes associated with successive timesteps of the QEC code. Such a decomposition is shown in Fig. 3c, in which a new virtual edge 312 is created between nodes 310b and 310c. The spanning hyperedge connecting nodes 310a-c can then be decomposed into a combination of the new virtual edge 312 and the existing boundary edge connected to the node 310a in the first region 302a of the hypergraph representation. Repeating this process for all spanning edges leads to repopulation of the severed region of the graph with virtual time-like and hook-like edges, as shown in Fig. 3d. In addition to the virtual time-like and hook-like edges, new virtual boundary edges 314 have been added to nodes in the first region 302a of the hypergraph that were involved in spanning hyperedges but did not have an existing (i.e. non-virtual) boundary edge; these virtual boundary edges connect to the boundary node (not shown). The resulting decomposed representation uses only edges (i.e. hyperedges having cardinality two) and does not have a gap between layers associated with successive timesteps of the QEC code. The resulting representation can therefore used to decode with existing graph-based decoding techniques (such as minimum-weight-perfect-matching or clustering) without requiring additional rounds of error correction to be performed. When decoding using the decomposed representation, relationships (or correlations) between the decomposed edges may be maintained in order to ensure consistent decoding. For example, when a correction is identified that involves an edge that is part of a decomposition, the states of nodes (or detectors) associated with the original undecomposed hyperedge may need to be updated. Decomposition information may be stored in a data structure (such as a map) associated with the decoding graph for the first logical qubit. This decomposition information can be used to infer correlations between errors and corrections in different decoding graphs. For example, the information may include an identifier of a component (i.e. edge or node) in the decomposition, and the virtual edge may be used as a key to access this identifier. In the example shown in Fig. 3c, a correction involving the virtual edge 312 will affect (e.g. flip, depending on which other edges are also involved) the state of the adjacent nodes 310b and 310c. However, because the virtual edge 312 was part of a hyperedge also involving node 310a, the state of node 310a should also be updated (e.g. flipped). During decoding, the decoder can use a data structure such as a map (e.g. an adaptivity map) to identify components (i.e. nodes and / or edges) in a second decoding graph associated with (i.e. part of the same spanning hyperedge decomposition) one or more edges in a first decoding graph (e.g. edges in the first decoding graph that are part of proposed correction). If the first and second decoding graphs are processed by different decoding units, a message comprising an identifier can be passed between the decoding units to indicate the component in the second decoding graph, and a state of the component can be updated accordingly (e.g. by flipping a defect state of an identified node, or by flipping the error / correction state of an identified edge and flipping the defect state of any nodes connected to that edge). In order to account for the updated state of components in the second decoding graph, multiple iterations of decoding may be used. In particular, a proposed correction may be determined for each decoding graph in a first round of decoding, and any necessary updates resulting from hyperedge decompositions may be propagated between decoding units to update decoding graph states. A further iteration (or iterations) of decoding may then be performed to determine a committed correction. Optionally, some or all of virtual edges (in particular, the virtual boundary edges) may be disabled / removed from the decoding graph for some rounds of decoding. Fig. 4 shows a flowchart of a quantum error correction method that decomposes higher order hyperedges into edges. This method ensures that the gap between the layers of nodes / detectors arising from transversal multi-qubit logical gates is populated with time-like and hooklike edges that the hyperedges otherwise obscure. Advantageously, this enabled error correction operations involving multi-qubit transversal logical gates to be implemented with a constant number of rounds between logical gates, unlike existing graph-based decoding methods in which the number of rounds increases in proportion to the code distance (and therefore cannot be scaled to large quantum computing systems that use error correction codes with large code distances). In step 401, a hypergraph representation is obtained of an error model for a transversal logical gate between logical qubits in a quantum error correction code, such as a surface code. The hypergraph representation may comprise a plurality of nodes (or vertices) representing detectors of the QEC code, and a plurality of hyperedges (including edges) representing error mechanisms in the QEC code. For example, a hyperedge may represent a particular physical qubit error that can occur during syndrome extraction; this error would flip the state of the nodes (detectors) connected to that hyperedge in the syndrome. In step 402, one or more hyperedges spanning between regions of the hypergraph representation associated with different logical qubits are identified. These spanning hyperedges result from the propagation of physical qubit errors through the transversal logical gate and will generally have cardinality three or more. In step 403, a decomposition of each of the identified spanning hyperedges is determined. The decomposition may be determined using the techniques described in relation to Figs. 3a-d. In particular, each decomposition comprises at least one virtual edge (i.e. at least one virtual hyperedge having cardinality of two) connecting nodes associated with successive timesteps of the QEC code (i.e. a virtual time-like edge or a virtual hook edge). Decomposing spanning hyperedges into virtual edges that connect nodes in successive timesteps ensures that the resulting decoding graphs are not severed when performing a transversal multi-qubit gate, which in turn avoids the need to perform additional rounds of error correction. The decomposition may comprise additional edges, for example edges already present in the hypergraph error model and / or further virtual edges, such as virtual boundary edges. In general, decompositions can be determined using the following process. Each spanning hyperedge connects multiple nodes of the hypergraph. For each spanning hyperedge, represent these nodes in a list and perform a search over all cardinality-two hyperedges in the hypergraph (excluding boundary edges). If a non-boundary cardinality-two hyperedge is identified that connects two nodes that are in the list of nodes, this cardinality-two hyperedge is added to the decomposition and the corresponding nodes are removed from the list of nodes and the search continues over the remaining cardinality-two hyperedges, with the process being repeated for any further hyperedges that connect two nodes in the updated list of nodes. Next, a search is made for virtual time-like edges. In other words, it is determined whether any two nodes remaining in the list of nodes are positioned vertically on top of each other and separated by only a single timestep. If any virtual time-like edges are identified, these virtual edges are added to the decomposition and the nodes connected by the virtual edge are removed from the list of nodes. A corresponding search may then be performed for virtual hook edges. The configuration of hook edges is dependent upon the QEC code, so this step may involve performing an analysis of the structure of the hooks from the round above the transversal gate. One skilled in the art will appreciate that this step may be adjusted to account for different decoding graph geometries. What is important is that the virtual edges introduce new connections between nodes associated with successive timesteps of the QEC code (i.e. nodes that are not already connected by edges). The 22 configuration of these virtual edges can be determined by analysing the structure of the hypergraph representation (e.g. the configuration of the edges) between layers of the hypergraph associated with successive timesteps that do not involve a transversal multiqubit logical gate. If there are any remaining nodes in the node list, a search is then performed over all boundary edges. If a boundary edge is connected to a node in the node list, the boundary edge is added to the decomposition and the node is removed from the node list. If any nodes remain in the node list after this step, virtual boundary edges are introduced connected to each remaining node in the node list. During this process, the effect that the decomposed edges have upon the logical operators may also be tracked so that this effect can be accounted for when decomposed edges (e.g. virtual edges) are subsequently included in a correction. In step 404, a decoding graph is generated for each logical qubit. The generated decoding graphs are preferably unconnected (i.e. there are no edges or hyperedges connecting the different decoding graphs). While each logical qubit is preferably associated with a different logical qubit, multiple logical qubits may optionally be associated with a single decoding graph (e.g. if a combination of transversal logic and lattice surgery are used). Each generated decoding graph may comprise edges from the hypergraph representation of the error model (i.e. hyperedges having cardinality-two, including boundary edges), and at least one decoding graph may comprise virtual edges from one or more the decompositions of the spanning hyperedges. The method may further involve receiving syndrome data representative of an error state of qubits (or other types of quantum devices) in the quantum computing system and determining a correction for the error state using the decoding graphs generated for the logical qubits. The correction may optionally be applied to a logical state measurement obtained by measuring one or more logical states encoded in the quantum devices. The correction may optionally comprise a separate correction for each logical qubit. Decomposing hyperedges using the approach described above in relation to Figs. 3a-d can advantageously provide a separate respective unconnected decoding graph for each logical qubit, which allows for parallelised decoding of the decoding graphs for each logical qubit The present inventors have recognised that parallel decoding can be performed by utilising relationships between the edges and nodes in spanning hyperedge decompositions and updating decoding graph detector states in an iterative fashion. Fig. 5 is a flowchart of such a quantum error correction method. In a first step 501, a decoding system obtains a first decoding graph associated with a first logical qubit and a second decoding graph associated with a second logical qubit. The decoding graphs are preferably unconnected. The decoding graphs may be generated using the approach described in relation to Figs. 3a-d. That is, the decoding graphs may comprise edges from decompositions of spanning hyperedges of hypergraph representations of an error model associated with a multi-qubit transversal logical gate, wherein the spanning hyperedges are hyperedges connecting regions of the hypergraph representation associated with different logical qubits. In a second step 502, syndrome data is received that is representative of an error state of quantum devices in the quantum computing system. The syndrome data may be syndrome data for multiple logical qubits in the error correction code. In step 503, states of nodes (or detectors) in the plurality of decoding graphs are initialised / set according to the syndrome. That is, defect nodes in the graph are identified using the syndrome, for example by setting a “defect” flag to true. In step 504, a first round of error correction is performed with the first decoding graph to identify a proposed (or tentative) correction involving one or more edges in the first decoding graph, e.g. a correction involving one or more virtual edges. Optionally, a round of error correction with the second decoding graph may be performed in to determine another proposed correction involving one or more edges in the second decoding graph. In step 505, a component in the second decoding window (i.e. an edge or node) associated with an edge in the proposed correction is identified. For example, the component may be part of the same hyperedge decomposition as the edge in the proposed correction. The edge in the proposed correction may be a virtual edge. Identifying the component in the second decoding window may involve retrieving an identifier of the component from a data structure (such as a map data structure) of the first decoding graph. In step 506, a state of the identified component in response to the proposed correction is updated. For example, the decoding system may flip a defect state of an identified node, or it may flip the error / correction state of an identified edge and may flip the defect state of any nodes connected to the identified edge in accordance with the updated error / correction state of the identified edge. In step 507, a further decoding round is performed on the first and second decoding graphs (preferably in parallel) to determine a committed correction for the error state. The committed correction may comprise one or more edges of the proposed correction (e.g. one or more virtual edges of the proposed correction). The committed correction may also comprise edges that were not in the proposed correction. The method may further comprise obtaining a logical state measurement of at least one of the first and second logical qubits and applying the committed correction to the logical state measurement. Fig. 6 shows a flowchart of a quantum error correction method that utilises multiple decoding units and decoding windows to perform parallel decoding; this approach can be applied to the decoding method of Fig. 5. In a first step 601, the decoding system obtains a plurality of decoding graphs associated with a plurality of logical qubits. The decoding graphs are preferably unconnected. The decoding system comprises a plurality of decoding units, each of which is a classical processing device configured to decode a syndrome on a decoding graph. Decoding graphs associated with different logical qubits may be assigned to (i.e. decoded by) different decoding units. Optionally, decoding graphs for more than one logical qubit may be assigned to the same processing unit. The decoding graphs may be generated using the approach described in relation to Figs. 3a-d. That is, the decoding graphs may comprise edges from decompositions of spanning hyperedges of hypergraph representations of an error model associated with a multi-qubit transversal logical gate, wherein the spanning hyperedges are hyperedges connecting regions of the hypergraph representation associated with different logical qubits. In a second step 602, syndrome data is received that is representative of an error state of quantum devices in the quantum computing system. The syndrome data may be syndrome data for multiple logical qubits in the error correction code. The syndrome data may be received by a controller of the decoding system, which may distribute the syndrome data to the decoding units. In step 603, states of nodes (or detectors) in the plurality of decoding graphs are initialised / set according to the syndrome, e.g. by the respective decoding unit to which each respective decoding graph is assigned. That is, defect nodes in the graph are identified using the syndrome, for example by setting a “defect” flag to true. Alternatively, the node states may be initialised (e.g. by the controller) before the decoding graphs are provided to the decoding units. In step 604, a first decoding window is determined for a first decoding graph associated with a first logical qubit, and a second decoding window is determined for a different second decoding graph associated with a second logical qubit. The first and second decoding windows may be determined by the first and second decoding units. A decoding window comprises a subgraph of a decoding graph. The size of the decoding window will generally be chosen according to code distance and / or processing capabilities of the decoding units. For example, a decoding window for a code having distance d may involve d rounds of syndrome extraction. In step 605, the first decoding unit performs a first round of error correction with the first decoding window to identify a proposed (or tentative) correction involving one or more edges in the first decoding graph, e.g. a correction involving one or more virtual edges. Optionally, the second decoding unit may perform a round of error correction with the second decoding window in parallel to determine another proposed correction involving one or more edges in the second decoding graph. In step 606, the first decoding unit identifies a component in the second decoding window (i.e. an edge or node) associated with an edge in the proposed correction. For example, the component may be part of the same hyperedge decomposition as the edge in the proposed correction. The edge in the proposed correction may be a virtual edge. Identifying the component in the second decoding window may involve retrieving an identifier of the component from a data structure of the first decoding graph. For example, a map data structure (such as an adaptivity map) or similar data structure may be associated with decoding graph, and edges (e.g. virtual edges) in the decoding graph may acts as keys for the map data structure. Whenever the decoder decodes to an edge (i.e. includes that edge in a correction), the decoding unit accesses the map to identify whether the edge is associated with any nodes in a another decoding graph. This identifier may then be transmitted (e.g. as part of a message) from the first decoding unit to the second decoding unit. The message may optionally indicate that the state of the component should be updated (e.g. by flipping a defect flag from true to false or vice-versa), or receipt of the message may itself be sufficient for the decoding unit to infer that the state of the node should be updated. In step 607, the second decoding unit updates a state of the identified component in response to the proposed correction. For example, the second decoding unit may flip a defect state of an identified node, or it may flip the error / correction state of an identified edge and may flip the defect state of any nodes connected to the identified edge in accordance with the updated error / correction state of the identified edge. The first decoding unit may also update the state of nodes in the first decoding graph in response to the proposed correction (e.g. flipping the states of nodes at the ends of correction chains in the proposed correction). In step 608, the first and second decoding unit perform another round of decoding on the first and second decoding windows respectively (preferably in parallel) to determine a committed correction for the error state. The committed correction may comprise one or more edges of the proposed correction (e.g. one or more virtual edges of the proposed correction). The committed correction may also comprise edges that were not in the proposed correction. The method may further comprise receiving a logical state measurement of at least one of the first and second logical qubits and applying the committed correction to the logical state measurement. The logical state measurement may be obtained by the controller, and the correction may be applied by the controller. Alternatively, the controller may distribute logical state measurements to the decoding units, and the decoding units may apply corrections. Figs. 7a-d show an example of performing quantum error correction using the methods of Fig. 5 and Fig. 6. Fig. 7a shows an initial state of first and second decoding graphs 702a and 702b associated with first and second logical qubits respectively. Respective first and second decoding windows 706a and 706b are determined for the first and second decoding graphs 702a, 702b. Detector locations 704a-e marked with crosses indicate the location of defects in the syndrome data. A first round of decoding is performed with the first decoding window 706a by a first decoding unit As shown in Fig. 7b, this first round of decoding may provide a proposed correction involving the virtual edge 708 connecting the detector locations 704a, 704b in the first decoding window 706a. The first decoding unit then identifies (using a map or similar data structure) a component (i.e. a node or an edge) in the second decoding window 706b that is associated with this virtual edge 708. For example, the first decoding unit may identify the node at detector location 704e, or the boundary edge 710 connected to this node. The first decoding unit then passes a message to the second decoding unit identifying this component, and the second decoding unit updates the state of the component accordingly, e.g. by flipping the defect flag from true to false or flipping an error / correction state of the edge from true to false or vice-versa (and also flipping the state of the defect flag of the node(s) connected to the edge to reflect the updated error state). In some cases, a round of decoding may also be performed with the second decoding window 706b by the second decoding unit in parallel with the first round of decoding performed with the first decoding window 706a. In this scenario, similar messages may also be passed from the second decoding unit to the first decoding unit. A further round of decoding is then performed on each of the decoding windows 706a, 706b as shown in Fig. 7c, preferably in parallel. Only two defects 704c, 704d remain, both of which are in the second decoding window 706b. The second decoding unit may then identify a correction 712 involving two edges of the second decoding graph 702b (one space-like edge and one hook edge). As no defects remain in the second decoding window 706a, the second decoding unit does not need to identify any corrections during this round of decoding. As the remaining defects are explained by a correction that does not involve any virtual edges, a committed correction, shown in Fig. 7d, can be determined as a combination of the virtual edge 708, the boundary edge 710, and the correction 712. While the above methods have been described in relation to performing one transversal multi-qubit logical gate, it should be understood that the method can also be applied to series of multiple transversal multi-qubit logical gates (including logical gates involving more than two logical qubits). Any method described herein may be provided as a computer program product and / or on a computer readable medium such as a non-transitory computer readable medium. It should be understood that any method of the present disclosure could include additional steps, and any device could include additional components. In addition, unless indicated otherwise or technically infeasible, the method steps disclosed herein may be performed in alternative orders, and any order described herein should be considered as exemplary rather than limiting. As a non-limiting example, the step of receiving the syndrome data in Fig. 8 need not occur at the start of the process but could occur any time prior to determining the correction. The illustrated steps and components could be split into multiple sub-steps / subcomponents. Furthermore, one skilled in the art will appreciate that any computation that can be performed by a classical processing device can also be performed by a quantum computing device. Accordingly, any methods or described herein that is performed on a classical computing device (such as a CPU) can also be performed by a quantum processing device, such as a quantum processing unit (QPU) comprising a plurality of qubits. When used herein, the term “flipping” or “flip” should be understood to mean a bit flip, i.e. a bitwise NOT operation. Flipping changes a 0 to a 1 and vice versa, true to false and vice versa etc. Any reference herein to higher order hyperedges should be understood to mean hyperedges with cardinality greater than two. While the present invention has primarily been described in the context of surface codes, it should be understood that the invention can also be applied to other QEC codes that use decoding graphs generated based on error models that use hypergraph representations.

Claims

1. A method of performing a quantum error correction code at a decoding system of a quantum computing system, the method comprising:obtaining a hypergraph representation of an error model for performing a transversal logical gate between logical qubits in the quantum error correction code;identifying one or more spanning hyperedges connecting regions of the hypergraph representation associated with different logical qubits;determining a decomposition of each of the one or more spanning hyperedges, each decomposition comprising at least one virtual edge having cardinality-two connecting nodes of the hypergraph representation associated with successive timesteps of the QEC code; andgenerating, using the decomposition of each of the one or more spanning hyperedges, a decoding graph for each logical qubit.

2. The method of claim 1, further comprising:receiving syndrome data representative of an error state of quantum devices in the quantum computing system; anddetermining a correction for the error state by decoding the syndrome data using the decoding graph for each logical qubit.

3. The method of claim 2, further comprising:receiving a logical state measurement of one or more of the logical qubits; andapplying the correction to the logical state measurement.

4. The method of claim 2 or claim 3, wherein the syndrome data indicates locations of defects in the quantum error correction code.

5. The method of any preceding claim, wherein the one or more spanning hyperedges have cardinality of at least three.

6. The method of any preceding claim, wherein determining a decomposition of each of the one or more spanning hyperedges comprises decomposing each hyperedge into a plurality of hyperedges having cardinality less than three.

7. The method of any preceding claim, wherein the at least one virtual edge is one of a time-like edge and a hook edge.

8. The method of any preceding claim, wherein the decoding graph for each logical qubit comprises a plurality of cardinality-two hyperedges of the hypergraph representation, and wherein at least one decoding graph comprises at least one virtual edge.

9. The method of any preceding claim, further comprising storing decomposition information in a data structure associated with the decoding graph for a first logical qubit.

10. The method of claim 9, wherein the information comprises an identifier of a component in the decoding graph for a second logical qubit, the component associated with a virtual edge in the decoding graph for the first logical qubit.

11. The method of claim 10, wherein the component is an edge or node.

12. The method of any preceding claim, wherein hyperedges of the hypergraph representation represent error mechanisms associated with quantum operations performed on physical qubits that make up the logical qubits.

13. The method of any preceding claim, wherein nodes of the hypergraph representation represent detectors of the quantum error correction code.

14. The method of any preceding claim, wherein the at least one virtual edge is between nodes that are not directly connected by an edge in the hypergraph representation15. A decoding system configured to perform the method of any preceding claim.

16. A computer-readable medium comprising instructions which, when executed by a decoding system, cause the decoding system to perform the method of any of claims 1 to 14.

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