A parallel hypergraph construction method and device based on FPGA

Abstract

The application discloses a parallel hypergraph construction method and device based on FPGA. The device comprises a computer system and an FPGA which are connected in communication. The computer system is configured to send an undirected adjacency matrix representing a common graph to the FPGA, receive all hyperedges sent by the FPGA and construct a hypergraph according to all hyperedges. The FPGA is configured to receive and store the undirected adjacency matrix, generate an adjacency vertex set corresponding to each target vertex according to the undirected adjacency matrix, construct a hyperedge corresponding to each target vertex in parallel according to the adjacency vertex set, and transmit all hyperedges to the computer system. The device and method convert the time complexity of hyperedge construction into spatial complexity through parallel computation of FPGA hyperedges, thereby reducing the operation time overhead and realizing fast construction of an accurate hypergraph.

Description

Technical Field

[0001] This invention belongs to the fields of network analysis and graph theory analysis, and specifically relates to a parallel hypergraph construction method and apparatus based on FPGA. Background Technology

[0002] In the field of network analysis, graph theory is a powerful tool that can represent the relationships between vertices in a network and solve a wide variety of combinatorial problems. Hypergraphs, as an extension of the graph concept, can contain two or more vertices through a single hyperedge; multiple hyperedges form a hypergraph, whereas a single edge in a regular graph can only connect two vertices. Compared to graphs, hypergraphs can represent higher-order data information, thus exhibiting better performance in complex analytical tasks such as social network analysis, data mining, bioinformatics network analysis, and image processing.

[0003] Common methods for constructing hypergraphs include direct construction and ordinary graph transformation. Direct construction builds the hypergraph based on relationships between target objects, such as distance, correlation, or attributes. Methods include k-Nearest Neighbor (kNN). These methods only consider the relationships between target vertices and their neighbors, neglecting the relationships between neighboring vertices. Therefore, vertices that don't belong to the hyperedge may be included, or vertices that should belong to the hyperedge may be missed, affecting subsequent processing. However, due to its high computational efficiency, it is currently the most commonly used method.

[0004] The ordinary graph transformation method is an algorithmic approach to convert a generated ordinary graph into a hypergraph. It involves representing each target vertex using a two-dimensional adjacency matrix based on certain relationships, and then using a search method to transform this adjacency matrix into a hypergraph matrix. Common search methods include Depth-First Search (DFS), Breadth-First Search (BFS), and algorithms developed based on these methods, such as the CLIQUES algorithm. These algorithms can obtain complete hyperedges well, which is helpful for further processing; however, they have high computational complexity and are usually performed sequentially, resulting in significant time overhead. Therefore, they are not currently the most commonly used hypergraph construction method, although the performance of the constructed hypergraphs is superior to that constructed by direct methods.

[0005] Reducing the computational time complexity of hypergraphs using conventional graph transformation methods is a key direction for improving hypergraph structures. One approach is to transform sequential computation steps into parallel computations, thereby reducing time overhead by converting time complexity into space complexity. Some existing work has implemented hypergraph computation using GPUs, achieving partial acceleration. Field-Programmable Gate Arrays (FPGAs) are well-suited for parallel computing tasks, as all their functions are implemented in hardware, offering high real-time performance and demonstrating potential for reducing computational time overhead. Summary of the Invention

[0006] In view of the above, the purpose of this invention is to provide a parallel hypergraph construction method and apparatus based on FPGA. By using the parallel computation of FPGA hyperedges, the time complexity of hyperedge construction is transformed into space complexity to reduce the computation time overhead, thereby achieving rapid construction of accurate hypergraphs.

[0007] To achieve the above-mentioned objectives, the present invention provides the following technical solution:

[0008] A parallel hypergraph construction device based on FPGA includes a computer system and an FPGA connected in communication.

[0009] The computer system is configured to send an undirected adjacency matrix representing a general graph to the FPGA, receive all hyperedges sent by the FPGA, and construct a hypergraph based on all hyperedges.

[0010] The FPGA is configured to receive and store an undirected adjacency matrix, generate a set of adjacent vertices corresponding to each target vertex based on the undirected adjacency matrix, construct hyperedges corresponding to each target vertex in parallel based on the set of adjacent vertices, and transmit all hyperedges to the computer system.

[0011] In one embodiment, the undirected adjacency matrix is ​​a two-dimensional matrix of size N*N. The element values ​​in the two-dimensional matrix represent the association information between vertices. If the i-th vertex is associated with the j-th vertex, the value of the i-th row and j-th column in the two-dimensional matrix is ​​1, otherwise it is 0.

[0012] In one embodiment, the FPGA includes a data storage module, an adjacent vertex generation module, a hyperedge calculation module, and a result output module;

[0013] The data storage module is used to store the received undirected adjacency matrix, including: constructing a storage space with a depth of N and a bit width of N for the undirected adjacency matrix of size N, storing each row of the undirected adjacency matrix as binary data, that is, storing the binary data of the row corresponding to each vertex in an address space, and marking the address of the address space as the corresponding vertex;

[0014] The adjacent vertex generation module is used to extract storage receipts from the data storage module, treat each vertex as a single target vertex, and construct a set of adjacent vertices for each target vertex.

[0015] The hyperedge calculation module is used to construct hyperedges in parallel based on N sets of adjacent vertices;

[0016] The result output module is used to transmit all constructed hyperedges to the computer system in sequence.

[0017] In one embodiment of the adjacent vertex generation module, the address and binary data of each address space are extracted from the data storage module. The vertex stored in the address is used as a single target vertex. The data after setting the data value of the target vertex position in the binary data to 0 is used as the set of adjacent vertices of the target vertex. The vertices with a value of 1 in the adjacent vertex set are adjacent vertices.

[0018] In one embodiment of the hyperedge calculation module, the first round of parallel hyperedge construction is performed based on a set of N adjacent vertices, including: taking each target vertex as the starting vertex, and performing the following hyperedge construction steps:

[0019] First, let AVS be the set of adjacent vertices of the starting vertex. initial,j And initialize the set of hyperedges BC for the target vertex. initial,j and alternative set SS initial,j , among which, BC initial,j and SS initial,j bit width and AVS initial,j They are equal, and all values ​​are 0;

[0020] Then, traverse AVS initial,j Each adjacent vertex P i And execute: Get adjacent vertex P i The set of adjacent vertices AVS adjoin,i , will AVS adjoin,i With the current BC initial,j Perform an AND operation, when the result of the AND operation is the same as BC. initial,j If they are equal, then BC will be... initial,j Middle adjacent vertex P i The corresponding position is assigned a value of 1 to update BC. initial,j Otherwise, SS initial,jMiddle adjacent vertex P i The corresponding position is assigned a value of 1 to update SS. initial,j ;

[0021] After traversing AVS initial,j For all adjacent vertices in the array, the last updated BC will be used. initial,j The hyperedge that serves as the target vertex.

[0022] In one embodiment of the hyperedge computation module, after the k-th round of parallel hyperedge construction is completed, when SS initial,j If the value 1 exists in the array, perform parallel hyperedge construction in round (k+1), including: AVS for each round (k). initial,j The AVS in round k initial,j The corresponding initial vertex is removed from the undirected adjacency matrix, and the adjacent vertices P of the initial vertex are updated. i The set of adjacent vertices AVS adjoin,i The updated set of adjacent vertices AVS adjoin,i Each adjacent vertex P i As the initial vertex of round k+1, execute the hyperedge construction step of round k+1.

[0023] In the result output module of one embodiment, all hyperedges computed in parallel are output in the order of each round, and the hyperedges constructed in each round are output in the order of the initial vertex number within each round.

[0024] To achieve the above-mentioned objectives, an embodiment also provides a parallel hypergraph construction method based on FPGA. The parallel hypergraph construction method employs the aforementioned parallel hypergraph construction apparatus and includes the following steps:

[0025] The computer system sends an undirected adjacency matrix representing a general graph to the FPGA;

[0026] After receiving and storing the undirected adjacency matrix, the FPGA generates a set of adjacent vertices corresponding to each target vertex based on the undirected adjacency matrix, constructs a hyperedge corresponding to each target vertex in parallel based on the set of adjacent vertices, and transmits all hyperedges to the computer system.

[0027] The computer system receives all the hyperedges sent by the FPGA and constructs a hypergraph based on all the hyperedges.

[0028] Compared with the prior art, the beneficial effects of the present invention include at least the following:

[0029] Leveraging the parallel processing and accelerated computing capabilities of FPGA, after receiving and storing the undirected adjacency matrix, a set of adjacent vertices corresponding to each target vertex is generated based on the undirected adjacency matrix. The hyperedge corresponding to each target vertex is then constructed in parallel based on the set of adjacent vertices, thereby reducing computational time overhead and accelerating the generation of the hypergraph. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of the FPGA-based parallel hypergraph construction device provided in an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram illustrating the principle of constructing an undirected adjacency matrix for a general graph, as provided in an embodiment of the present invention.

[0033] Figure 3 This is an example schematic diagram of generating a hyperedge in the hyperedge calculation module provided in an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the scope of protection of this invention.

[0035] To reduce the computational overhead of generating hypergraphs from ordinary graphs in computer systems, thereby improving computational efficiency and accelerating hypergraph generation, this embodiment provides a parallel hypergraph construction method and apparatus based on FPGA.

[0036] Figure 1 This is a schematic diagram of the structure of the FPGA-based parallel supergraph construction device provided in an embodiment of the present invention. Figure 1 As shown, the FPGA-based parallel hypergraph construction apparatus provided in the embodiment includes a computer system and an FPGA.

[0037] In this embodiment, the computer system is configured to send an undirected adjacency matrix representing a general graph to the FPGA and receive all hyperedges sent by the FPGA, constructing a hypergraph based on all hyperedges. The undirected adjacency matrix is ​​derived from the undirected general graph and is an N*N two-dimensional matrix. The elements in the two-dimensional matrix represent the association information between vertices; if the i-th vertex is associated with the j-th vertex, the value in the i-th row and j-th column of the two-dimensional matrix is ​​1, otherwise it is 0. For example, ... Figure 2 As shown, the left image is an undirected ordinary graph where vertices 1, 2, and 3 are connected to vertex 4. The right image shows the transformation into an undirected adjacency matrix. In this matrix, connected vertices are assigned a value of 1, while unconnected vertices are assigned a value of 0. Additionally, the values ​​on the diagonal of the matrix are also assigned a value of 1, representing the vertices themselves. The computer system then sends the transformed undirected adjacency matrix to the FPGA via a network.

[0038] In this embodiment, the FPGA is configured to receive and store an undirected adjacency matrix, generate a set of adjacent vertices corresponding to each target vertex based on the undirected adjacency matrix, construct a hyperedge corresponding to each target vertex in parallel based on the set of adjacent vertices, and transmit all hyperedges to the computer system. Figure 1 As shown, it includes a data storage module, an adjacent vertex generation module, a hyperedge calculation module, and a result output module.

[0039] In this embodiment, the data storage module is used to store the received undirected adjacency matrix, including: constructing a storage space of depth N and bit width N for the N*N undirected adjacency matrix; storing each row of the undirected adjacency matrix as binary data, that is, storing the binary data of the row corresponding to each vertex in an address space, and marking the address of the address space as the corresponding vertex. The storage space can be RAM space. Subsequent calculations will process the data in the data storage format.

[0040] In this embodiment, the adjacent vertex generation module extracts storage data from the data storage module, treats each vertex as a single target vertex, and constructs an adjacent vertex set for each target vertex. Specifically, it extracts the address and binary data of each address space from the data storage module. The vertex stored at the address is treated as a single target vertex, and the data value of the target vertex position in the binary data after setting it to 0 is used as the adjacent vertex set of the target vertex. Vertices with a value of 1 in the adjacent vertex set are considered adjacent vertices. For example, if the binary number in address 1 is 10001001, the target vertex obtained in the adjacent vertex generation module is 1, and the corresponding adjacent vertex set is 00001001. The search process starts from all vertices, thus generating N vertices and N adjacent vertex sets in parallel.

[0041] In this embodiment, the hyperedge calculation module is used to construct hyperedges in parallel based on a set of N adjacent vertices. Specifically, the first round of parallel hyperedge construction based on the set of N adjacent vertices includes: taking each target vertex as the starting vertex, performing the following hyperedge construction steps:

[0042] (a) First, denote the set of adjacent vertices of the starting vertex as AVS. initial,j And initialize the set of hyperedges BC for the target vertex. initial,j and alternative set SS initial,j , among which, BC initial,j and SS initial,j bit width and AVS initial,j (a) Equal, and all values ​​are 0; (b) Then, traverse AVS initial,j Each adjacent vertex P i And execute: Get adjacent vertex P i The set of adjacent vertices AVS adjoin,i , will AVS adjoin,i With the current BC initial,j Perform an AND operation, when the result of the AND operation is the same as BC. initial,j If they are equal, then BC will be... initial,j Middle adjacent vertex P i The corresponding position is assigned a value of 1 to update BC. initial,j Otherwise, SS initial,j Middle adjacent vertex P i The corresponding position is assigned a value of 1 to update SS. initial,j (c) After traversing AVS initial,j For all adjacent vertices in the array, the last updated BC will be used. initial,j The hyperedge is the target vertex, where i is the index of the adjacent vertex and j is the index of the initial vertex.

[0043] In the embodiment, SS initial,j Used to determine whether to terminate the hyperedge calculation. If SS initial,j If all values ​​in SS are 0, then the construction of the next round of hyperedges can be terminated. initial,j If the value 1 exists in the SS, then proceed to the next round of parallel hyperedge construction. Specifically, in the hyperedge calculation module, after the k-th round of parallel hyperedge construction, when SS... initial,j If the value 1 exists in the array, perform parallel hyperedge construction in round (k+1), including: AVS for each round (k). initial,j The AVS in round k initial,j The corresponding initial vertex is removed from the undirected adjacency matrix, and the adjacent vertices P of the initial vertex are updated. i The set of adjacent vertices AVS adjoin,i The updated set of adjacent vertices AVS adjoin,i Each adjacent vertex Pi Create the initial vertex for the (k+1)th round, and perform the parallel hyperedge construction for the (k+1)th round, that is, perform the hyperedge construction steps in steps (a) to (c) above for the (k+1)th round.

[0044] For example, such as Figure 3 As shown, Figure 3 On the left is an undirected general graph and its undirected adjacency matrix G. With vertex 4 as the target vertex, the right side shows a set of hyperedges BC obtained by searching from the target vertex 4. target,4 AVS at target vertex 4 target,4 Given the value 001011110, we need to determine if the vertices with a value of 1, i.e., adjacent vertices 3, 5, 6, 7, 8, can form a hyperedge. We first traverse from adjacent vertex 3, checking the AVS of adjacent vertex 3. adjoin,3 =010100011 and the BC of the target vertex initial,4 =000100000 performs a bitwise AND operation, and the result of the AND operation is ANDed with BC. initial,4 =000100000 are equal, therefore, BC initial,4 Assign 1 to the corresponding 3rd bit, that is, update BC. initial,4 =001100000; then iterate to adjacent vertex 5, and the AVS of adjacent vertex 5. adjoin,5 =000101000 and the BC of the target vertex initial,4 = 001100000 performs a bitwise AND operation, and the result of the AND operation, 000100000, is then ANDed with BC. initial,4 =001100000 are not equal, so SS initial,4 Assign 1 to the corresponding 5th bit, that is, update SS. initial,4 =000010000; Next, traverse adjacent vertices 6, 7, and 8 and update BC. initial,4 or SS initial,4 Finally, after traversing all adjacent vertices, the resulting superedge BC is obtained. initial,4 =001100010.

[0045] After the first round of superedge construction, the SS of round k=1 initial,4 =000011100, if there is a value of 1, then parallel hyperedge construction in round k=2 is required, including: for each round 1 AVS initial,4 The first round of AVS initial,4 The corresponding initial vertex is removed from the undirected adjacency matrix, and the adjacent vertices P of the initial vertex are updated. i The set of adjacent vertices AVS adjoin,i Taking adjacent vertex 3 as an example, after deleting the initial vertex 4, the updated set of adjacent vertices AVS of adjacent vertex 3 is as follows: adjoin,3=011000011 indicates that adjacent vertex 3 is connected to vertices 2, 8, and 9, and the adjacent vertex set AVS is updated accordingly. adjoin,i Each adjacent vertex P i As the initial vertex of the (k+1)th round, the hyperedge construction step of the (k+1)th round is executed. Assuming that the adjacent vertex 3 is the initial vertex, the connection between the initial vertex and the corresponding adjacent vertices 2, 8, and 9 needs to be calculated according to steps (a)-(c).

[0046] In this embodiment, the result output module is used to transmit all constructed hyperedges to the computer system sequentially. Since there is only one output channel, all hyperedges computed in parallel are output in round-by-round order, with each round's constructed hyperedges output according to the initial vertex index within each round, i.e., outputting BC sequentially. initial,1 BC initial,2 BC initial,3 , ..., BC initial,N The computer system receives all hyperedges and then constructs a hypergraph based on them.

[0047] The embodiment also provides a parallel hypergraph construction method based on FPGA. Figure 1 The parallel hypergraph construction apparatus shown includes the following steps:

[0048] Step 1: The computer system sends an undirected adjacency matrix representing a general graph to the FPGA;

[0049] Step 2: After receiving and storing the undirected adjacency matrix, the FPGA generates a set of adjacent vertices corresponding to each target vertex based on the undirected adjacency matrix, constructs the hyperedge corresponding to each target vertex in parallel based on the set of adjacent vertices, and transmits all hyperedges to the computer system.

[0050] Step 3: The computer system receives all the hyperedges sent by the FPGA and constructs a hypergraph based on all the hyperedges.

[0051] The FPGA-based parallel hypergraph construction method and the FPGA-based parallel hypergraph construction device mentioned above belong to the same inventive concept. The specific implementation process and effects of each step are detailed in the parallel hypergraph construction device, and will not be repeated here.

[0052] The FPGA-based parallel hypergraph construction method and apparatus provided in the above embodiments reduce computational time overhead by converting the time complexity of hyperedge construction into space complexity through parallel computation of FPGA hyperedges, thereby achieving rapid construction of accurate hypergraphs.

[0053] The specific embodiments described above illustrate the technical solution and beneficial effects of the present invention in detail. It should be understood that the above description is only the most preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, additions, and equivalent substitutions made within the scope of the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A parallel hypergraph construction device based on FPGA, characterized in that, This includes computer systems and FPGAs with communication connections; The computer system is configured to send an undirected adjacency matrix representing a general graph to the FPGA, receive all hyperedges sent by the FPGA, and construct a hypergraph based on all hyperedges. The FPGA is configured to receive and store an undirected adjacency matrix, generate a set of adjacent vertices corresponding to each target vertex based on the undirected adjacency matrix, construct a hyperedge corresponding to each target vertex in parallel based on the set of adjacent vertices, and transmit all hyperedges to the computer system. The FPGA includes a data storage module, an adjacent vertex generation module, a hyperedge calculation module, and a result output module; The data storage module is used to store the received undirected adjacency matrix, including: constructing a storage space of depth N and bit width N for the N*N undirected adjacency matrix; storing each row of the undirected adjacency matrix as binary data, that is, storing the binary data of the row corresponding to each vertex in an address space, and marking the address of the address space as the corresponding vertex; the adjacent vertex generation module is used to extract the stored data from the data storage module, taking each vertex as a single target vertex, and constructing a set of adjacent vertices for each target vertex; the hyperedge calculation module is used to construct hyperedges in parallel based on the N adjacent vertex sets; the result output module is used to transmit all constructed hyperedges to the computer system in sequence; In the hyperedge calculation module, the first round of parallel hyperedge construction is performed based on the set of N adjacent vertices, including: taking each target vertex as the starting vertex, and performing the following hyperedge construction steps: First, let AVS denote the set of adjacent vertices of the starting vertex. initial,j And initialize the set of hyperedges BC for the target vertex. initial,j and alternative set SS initial,j , among which, BC initial,j and SS initial,j bit width and AVS initial,j They are equal, and all values ​​are 0; Then, traverse AVS initial,j Each adjacent vertex P i And execute: Get adjacent vertex P i Adjacent vertex set AVS adjoin,i , will AVS adjoin,i With the current BC initialt,j Perform an AND operation, when the result of the AND operation is the same as BC. initial,j If they are equal, then BC will be... initial,j Middle adjacent vertex P i The corresponding position is assigned a value of 1 to update BC. initial,j Otherwise, SS initial,j Middle adjacent vertex P i The corresponding position is assigned a value of 1 to update SS. initial,j ; After traversing AVS initial,j For all adjacent vertices in the array, the last updated BC will be used. initial,j The hyperedge that serves as the target vertex.

2. The FPGA-based parallel hypergraph construction device according to claim 1, characterized in that, The undirected adjacency matrix is ​​a two-dimensional matrix of size N*N. The element values ​​in the two-dimensional matrix represent the association information between vertices. If the i-th vertex is associated with the j-th vertex, the value of the i-th row and j-th column in the two-dimensional matrix is ​​1, otherwise it is 0.

3. The FPGA-based parallel hypergraph construction device according to claim 2, characterized in that, In the adjacent vertex generation module, the address and binary data of each address space are extracted from the data storage module. The vertex stored in the address is used as a single target vertex. The data value of the target vertex position in the binary data is set to 0 and then used as the set of adjacent vertices of the target vertex. The vertex with a value of 1 in the set of adjacent vertices is the adjacent vertex.

4. The FPGA-based parallel hypergraph construction device according to claim 1, characterized in that, In the hyperedge computation module, after the k-th round of parallel hyperedge construction, when SS initial,j If the value 1 exists in the array, perform parallel hyperedge construction in round (k+1), including: AVS for each round (k). initial,j The k-th round of AVS initial,j The corresponding initial vertex is removed from the undirected adjacency matrix, and the adjacent vertices P of the initial vertex are updated. i Adjacent vertex set AVS adjoin,i The updated set of adjacent vertices AVS adjoin,i Each adjacent vertex P i As the initial vertex of round k+1, execute the hyperedge construction step of round k+1.

5. The FPGA-based parallel hypergraph construction device according to claim 1, characterized in that, In the result output module, all hyperedges computed in parallel are output in the order of each round, and within each round, they are output in the order of the initial vertex number.

6. A parallel hypergraph construction method based on FPGA, characterized in that, The parallel hypergraph construction method employs the parallel hypergraph construction apparatus according to any one of claims 1-5, and includes the following steps: The computer system sends an undirected adjacency matrix representing a general graph to the FPGA; After receiving and storing the undirected adjacency matrix, the FPGA generates a set of adjacent vertices corresponding to each target vertex based on the undirected adjacency matrix, constructs a hyperedge corresponding to each target vertex in parallel based on the set of adjacent vertices, and transmits all hyperedges to the computer system. The computer system receives all the hyperedges sent by the FPGA and constructs a hypergraph based on all the hyperedges.

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