Processing device and processing method

Abstract

To improve throughput of an arithmetic processing apparatus that executes a plurality of pieces of data processing divided into a plurality of pipeline stages.SOLUTION: An arithmetic processing apparatus includes: a pipeline control unit that causes a processing unit to execute in parallel a plurality of pieces of data processing divided into a plurality of pipeline stages by shifting a timing; a measurement unit that measures a processing time of each of the plurality of pipeline stages; and a priority setting unit that sets a priority of each of the plurality of pipeline stages higher in an order of longer measured processing times.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a processing device and a processing method. [Background technology]

[0002] A pipeline parallel system is known that improves throughput by executing data processing divided into multiple stages in parallel with staggered timing. In this type of pipeline parallel system, the load on each stage is calculated based on the input number of executable processors, and the number of processors assigned to each stage is automatically changed (see, for example, Patent Document 1).

[0003] When each stage reads and writes processing data to memory via a common bus, the stage that is causing the bottleneck is identified depending on the status of data transfer stoppage between stages, and the priority of memory access by the identified stage is set high (see, for example, Patent Document 2). In a data processing device that executes processing in response to processing requests, when there is contention for resources that execute processing for multiple processing requests, the resource contention is avoided by executing the processes in order (see, for example, Patent Document 3). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-118589 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-91307 [Patent Document 3] Japanese Patent Publication No. 2020-101921 Summary of the Invention [Problem to be solved by the invention]

[0005] In a pipeline parallel system, if there is a stage that takes longer to process than other stages, data waiting to be processed accumulates in a buffer that supplies data to the stage with the longer processing time, and the throughput of the pipeline parallel system decreases.

[0006] In one aspect, the present invention aims to improve the throughput of a processing unit that sequentially executes a plurality of data processing operations that are divided into a plurality of pipeline stages. [Means for solving the problem]

[0007] According to one aspect, the processing units each include a plurality of seed The multiple data processing divided into pipeline stages is executed in parallel by the processing unit with staggered timing. A processing instruction for each type of pipeline stage is input to the processing unit. a pipeline control unit; For each of the plurality of types of pipeline stages a measurement unit that measures a processing time; The plurality of types Pipeline Stage By type a priority setting unit that sets the priority in descending order of the measured processing time; After the priority setting unit sets the priority, the pipeline control unit inputs processing instructions to the processing unit in order of priority, starting with the processing instruction of the pipeline stage with the highest priority, and the priority setting unit changes the priority for each type of the plurality of types of pipeline stages by hooking an application programmable interface of a driver that controls the operation of the processing unit. . [Effects of the Invention]

[0008] The throughput of a processing unit that executes a plurality of data processes divided into a plurality of pipeline stages can be improved. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a block diagram illustrating an example of a processing unit according to an embodiment. [Figure 2] FIG. 10 is a block diagram illustrating an example of an information processing device including an arithmetic processing device according to another embodiment. [Figure 3] 3 is a block diagram showing an example of a functional configuration of a pipeline system realized by the information processing device of FIG. 2. [Figure 4] FIG. 3 is an explanatory diagram showing an example of image recognition processing using a trained neural network executed by the information processing device of FIG. 2; [Figure 5] 3 is an explanatory diagram showing an example in which processing instructions are input to the accelerator of FIG. 2 according to the priority of each operation stage. [Figure 6] 5 is an explanatory diagram showing an example in which a distribution instruction unit of the processing priority control unit in FIG. 4 changes queue priorities using an API hook; FIG. [Figure 7] 5 is a flowchart showing an example of the operation of the processing priority control unit in FIG. 4. [Figure 8] 3 is an operational sequence diagram showing an example of pipeline parallel processing executed by the information processing device of FIG. 2. FIG. [Figure 9] 5 is an explanatory diagram showing an example of a change in processing time before and after priority control by the processing priority control unit of FIG. 4. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings.

[0011] FIG. 1 shows an example of a processing device according to an embodiment. The processing device 1 shown in FIG. 1 includes a pipeline control unit 2, a measurement unit 3, a priority setting unit 4, and a processing unit 5. For example, the processing device 1 is a processor such as a CPU (Central Processing Unit). The pipeline control unit 2, the measurement unit 3, and the priority setting unit 4 may be realized by a control program executed by the processing device 1, or may be realized by hardware. Furthermore, the pipeline control unit 2, the measurement unit 3, and the priority setting unit 4 may be realized by combining software and hardware.

[0012] For example, the processing unit 5 may be realized by a plurality of arithmetic cores mounted on the arithmetic processing device 1. The processing unit 5 executes pipeline parallel processing in which a plurality of data processes are executed in parallel with shifted timing. The processing contents of the plurality of data processes are the same except that the input data and output data are different for each process.

[0013] The arithmetic processing device 1 may be realized by a server including a processor such as a CPU and an accelerator such as a GPU (Graphics Processing Unit). In this case, the arithmetic processing device 1 may be realized by an information processing device such as a server having a control board on which the processor and accelerator are mounted. The pipeline control unit 2, the measurement unit 3, and the priority setting unit 4 may be realized by a control program executed by the processor. The processing unit 5 may be realized by multiple arithmetic cores mounted on the accelerator.

[0014] When the processing unit 5 is realized by an accelerator, the pipeline control unit 2 causes the processing unit 5 to execute data processing via a driver that controls the operation of the accelerator. The driver has an application programmable interface (API) and communicates with the pipeline control unit 2 via the API.

[0015] In the example shown in FIG. 1, each data process is divided into multiple stages A, B, C, ... and executed. Each stage A, B, C, ... is executed using one of multiple arithmetic cores included in the processing unit 5. For example, the arithmetic cores that execute stages A, B, C, ... are different from each other. Each stage A, B, C, ... is an example of a pipeline stage. Hereinafter, when stages A, B, C, ... are described without distinction, they will be simply referred to as stages.

[0016] The pipeline control unit 2 causes the processing unit 5 to execute multiple data processing processes in parallel with staggered timing. During an initialization period (evaluation period) before the pipeline control unit 2 causes the processing unit 5 to execute multiple data processing processes, the measurement unit 3 causes the processing unit 5 to execute each of multiple stages while changing input data, and measures the processing time for each stage. The measurement unit 3 then acquires statistics of the processing time for each stage. For example, the measurement unit 3 causes the processing unit 5 to execute each stage via the pipeline control unit 2, and measures the processing time.

[0017] The priority setting unit 4 sets the priority of each stage during the initialization period in descending order of processing time based on the processing time for each stage measured by the measurement unit 3. Note that the priority setting unit 4 may, for example, set the priorities of a predetermined number of stages with the longest processing times to the highest in descending order of processing time, and not set priorities for the other stages. Alternatively, the priority setting unit 4 may set the priorities of the other stages to the lowest. For example, if the processing unit 5 is implemented by an accelerator, the priority setting unit 4 hooks the API of the accelerator driver to change the priorities for each of the multiple stages.

[0018] In this embodiment, the priority setting unit 4 sets the priority of the stage in descending order of processing time based on the processing time for each stage measured by the measurement unit 3. Therefore, in the subsequent data processing, the processing of the high-priority stage can be executed without being interrupted by other processing.

[0019] Therefore, even if there is a stage whose processing time is extended due to an interruption from another process, the processing unit 5 can shorten the processing time of the stage by changing the priority. This allows the arithmetic processing device 1 to prevent stages with long processing times from having to wait when executing data processes that are executed sequentially by the processing unit 5. As a result, the arithmetic processing device 1 can make the processing times of each stage approximately equal, as shown in FIG. 1, thereby improving the execution efficiency of data processing using pipeline parallel processing. That is, in this embodiment, it is possible to improve the throughput of the arithmetic processing device 1 that executes multiple data processes divided into multiple pipeline stages.

[0020] When the processing unit 5 is realized by an accelerator, the priority setting unit 4 changes the priority for each of the multiple stages by hooking the API of the accelerator driver. As a result, even when the pipeline control unit 2 cannot set the priority for each stage, the priority setting unit 4 can appropriately set the priority for each stage according to the actual processing time of each stage.

[0021] The measurement of processing time by the measurement unit 3 and the reassignment of priorities by the priority setting unit 4 are performed during an initialization period before the processing unit 5 sequentially executes a plurality of data processes in parallel. Because the priority of each stage is reassigned in advance, the arithmetic processing device 1 can prevent a decrease in processing efficiency when executing data processes.

[0022] 2 shows an example of an information processing device including an arithmetic processing device according to another embodiment. The information processing device 100 shown in FIG. 2 is, for example, a server, and includes a processor 10, a memory 20, an auxiliary storage device 30, an accelerator 40, a memory 50, a connection interface unit 60, an input interface unit 70, an output interface unit 80, and a network interface unit 90.

[0023] The processor 10 is, for example, a CPU, and includes a pipeline control unit 11, a processing priority control unit 12, and a shared memory 15 such as a static random access memory (SRAM). The pipeline control unit 11 and the processing priority control unit 12 may be realized by the processor 10 executing a control program stored in the memory 20. The processor 10 may have multiple cores, and the number of processors 10 installed in the information processing device 100 may be two or more.

[0024] The processing priority control unit 12 has a performance analysis unit 13 and a distribution instruction unit 14. The performance analysis unit 13 is an example of a measurement unit, and the distribution instruction unit 14 is an example of a priority setting unit. The performance analysis unit 13 measures the processing time for each of the operation stages 43a, 43b of the pipeline 41 described in FIG. 3. The distribution instruction unit 14 sets the priority of each operation stage 43a, 43b in descending order of processing time based on the processing time for each of the operation stages 43a, 43b measured by the performance analysis unit 13. Examples of the functions of the performance analysis unit 13 and the distribution instruction unit 14 are described in FIGS. 5 and 6.

[0025] The memory 20 is a main storage device such as a dynamic random access memory (DRAM). The memory 20 stores control programs and various data executed by the processor 10. The auxiliary storage device 30 is a hard disk drive (HDD) or a solid state drive (SSD). The auxiliary storage device 30 stores control programs to be transferred to the memory 20, input data for data processing to be executed by the accelerator 40, configuration information for the neural network that executes the data processing, and the like.

[0026] The accelerator 40 is, for example, a GPU, and is capable of performing calculations at high speed for specific processes. In this embodiment, the accelerator 40 executes data processing such as image recognition processing using a trained neural network based on instructions from the processor 10. The memory 50 is, for example, a main storage device such as a DRAM. The memory 50 holds input data used in the data processing and output data resulting from the data processing. The accelerator 40 cannot directly access the shared memory 15 of the processor 10. Therefore, of the data held in the shared memory 15, the data used by the accelerator 40 is transferred from the shared memory 15 to the memory 50.

[0027] The connection interface unit 60 is, for example, a PCIe (Peripheral Component Interconnect express) switch, etc. The connection interface unit 60 connects the processor 10, the accelerator 40, the input interface unit 70, the output interface unit 80, and the network interface unit 90 to one another.

[0028] One of the input interface units 70 is connected to a camera (not shown) that captures moving images and the like, and inputs moving image data acquired by the camera. Another of the input interface units 70 may be connected to a mouse or keyboard (not shown). The output interface unit 80 is connected to a display (not shown) that displays images, text, and the like. The network interface unit 90 is, for example, a network interface card (NIC), and is connected to a network (not shown).

[0029] 3 shows an example of the functional configuration of a pipeline system realized by the information processing device 100 of FIG. 2. In FIG. 3, thick arrows indicate data transmission paths, and thin arrows indicate transmission paths of control signals such as commands. A pipeline 41, which divides data processing into multiple stages and executes them in parallel, includes an input stage 42, multiple operation stages 43 (43a, 43b, etc.), and an output stage 44. For example, data processing by the pipeline 41 is executed by at least one of the processor 10 and the accelerator 40.

[0030] Before starting data processing by the pipeline 41, the performance analysis unit 13 sequentially supplies data from the input stage 42 to each calculation stage 43. The performance analysis unit 13 measures the processing time by receiving the processing results of each calculation stage 43 via the output stage 44. The performance analysis unit 13 may also sequentially supply data to each calculation stage 43 of interest and measure the processing time based on the completion of the calculation of the calculation stage 43 of interest. Based on the processing time for each calculation stage 43 measured by the performance analysis unit 13, the distribution instruction unit 14 sets the priority of each calculation stage 43 in descending order of processing time before starting data processing by the pipeline 41.

[0031] When starting data processing by the pipeline 41, the pipeline control unit 11 issues an instruction to start the execution of an operation for each data processing. When issuing an instruction, the pipeline control unit 11 assigns a unique ID (Identification) to the data to be processed, thereby making it possible to identify the data processing to be executed. For example, if the data processing executed by the pipeline 41 is a video recognition process, the unique ID may be the frame number of the image, etc. When the data processing by the pipeline 41 ends, the pipeline control unit 11 receives a processing completion notification from the output stage 44, thereby knowing the number of remaining data processing operations currently being executed by the pipeline 41.

[0032] The input stage 42 receives input data such as image data via the input interface unit 70 or the network interface unit 90 in FIG. 2 and writes the received input data to the shared memory 15. The shared memory 15 is accessible from each stage of the pipeline 41. The input stage 42 determines the write destination of the input data according to a unique ID, thereby preventing the input data from being overwritten in the shared memory 15.

[0033] The processing by the multiple calculation stages 43a, 43b is executed by, for example, the accelerator 40 or the processor 10. Each calculation stage 43a, 43b acquires data to be processed from the shared memory 15 based on the unique ID received from the previous stage. Each calculation stage 43a, 43b then executes calculations using the acquired data and writes data indicating the calculation results as processing results in a storage area of ​​the shared memory 15 assigned according to the unique ID.

[0034] The output stage 44 obtains the processing result from the storage area of ​​the shared memory 15 corresponding to the unique ID. The output stage 44 transmits the obtained processing result to an output device via the output interface unit 80 in Fig. 2, or transmits it to a remote node on the network via the network interface unit 90 in Fig. 2. The output stage 44 notifies the pipeline control unit 11 that the data in the shared memory 15 used for data processing of the unique ID can be reused.

[0035] The external command control unit 18 receives commands from the outside of the pipeline system shown in Fig. 3 and outputs the received commands to the pipeline control unit 11. For example, the commands received by the external command control unit 18 may be issued by a user program requesting data processing. In the following description, the calculation stages 43 (43a, 43b, etc.) are also simply referred to as stages 43 (43a, 43b, etc.).

[0036] Fig. 4 shows an example of image recognition processing using a trained neural network executed by the information processing device 100 of Fig. 2. For example, in the image recognition processing shown in Fig. 4, the information processing device 100 recognizes a person appearing in each frame of a video image received in real time from a camera or the like, and estimates the person's behavior from the movement of the person appearing in the previous and subsequent frames.

[0037] In the image recognition processing, the information processing device 100 sequentially executes video processing, person recognition processing, posture recognition processing, tracking processing, and behavior estimation processing. In the example shown in Fig. 4, the video processing, person recognition processing, and posture recognition processing are each executed by the accelerator 40 as processing in the calculation stage 43 based on instructions from the processor 10. The video processing, person recognition processing, and posture recognition processing may cause contention for resources of the accelerator 40.

[0038] The tracking process and the behavior estimation process are each executed by the processor 10 as processing of the calculation stage 43. Note that the moving image processing, the person recognition process, the posture recognition process, the tracking process, and the behavior estimation process may be executed by only the accelerator 40 or by only the processor 10.

[0039] In video processing, the accelerator 40 sequentially extracts frame data corresponding to one image from video image data. In person recognition processing, the accelerator 40 extracts a person from each frame of data. In posture recognition processing, the accelerator 40 recognizes the posture of the extracted person for each frame.

[0040] In the tracking process, the processor 10 detects changes in the posture of the person recognized by the posture recognition process in previous and subsequent frames and determines the person's movement. For example, the person's movement may be standing still, walking, running, sitting down, etc. In the behavior estimation process, the processor estimates the person's behavior based on the determination result of the tracking process.

[0041] The user scripts for the video processing, human recognition processing, and posture recognition processing are executed by the accelerator 40 via a framework, a library, and a driver for the accelerator 40. The user scripts for the tracking processing and behavior estimation processing are executed by the processor 10 via a framework and a library. As described above, the distribution instruction unit 14 of the processing priority control unit 12 hooks the API of the driver for the accelerator 40 to set a priority for each of the multiple stages.

[0042] 5 shows an example in which processing commands are input to the accelerator 40 according to the priority of each calculation stage 43. For example, a framework used for deep learning or recognition processing after deep learning hides low-level APIs so that detailed control does not need to be included in the description of a user script.

[0043] Furthermore, when an external device such as the accelerator 40 is used for deep learning or recognition processing, the framework also hides the APIs of the drivers related to the accelerator 40. Furthermore, the framework also hides libraries for mathematical operations, etc. This allows a user script to be written by being aware of the APIs provided by the framework. In other words, a user script can be written without being aware of whether the calculation processing will be executed by the processor 10 or the accelerator 40.

[0044] Furthermore, in this embodiment, an API for creating a prioritized queue for each calculation stage 43 for managing processing instructions for the accelerator 40 is hidden. For example, processing instructions are submitted to the accelerator 40 via software-level queues 45 (45a, 45b) managed by the driver of the accelerator 40 and a hardware-level queue 46 managed by the accelerator 40.

[0045] When there is free space in the hardware-level queue 46, the software-level queue 45 submits a processing instruction to the hardware-level queue 46. The accelerator 40 executes the processing instructions submitted from the hardware-level queue 45 in the order of submission. When submitting instructions from the software-level queue 45 to the hardware-level queue 46, higher priority queues are given priority.

[0046] 5 shows software-level queues 45a and 45b corresponding to the operation stages 43a and 43b, respectively. The queue 45a corresponding to the operation stage 43a has a higher priority than the queue 45b corresponding to the operation stage 43b. Therefore, the processing instructions a1 and a2 held in the queue 45a are input to the hardware-level queue 46 with priority over the processing instructions b1 and b2 held in the queue 45b. The queue 46 then inputs the processing instructions a1, a2, b1, and b2 to the accelerator 40 in the order in which they were held. As a result, the processing by the operation stage 43a is executed with priority over the processing by the operation stage 43b.

[0047] 6 shows an example in which the distribution instruction unit 14 of the processing priority control unit 12 in FIG. 4 reassigns queue priorities by hooking an API. The distribution instruction unit 14 hooks both a function that generates a non-priority queue and a function that generates a priority queue using the driver's API. The distribution instruction unit 14 then replaces the queue-generating function using the API with a function that generates a priority queue with a priority set based on the processing time of the calculation stage 43 measured by the performance analysis unit 13.

[0048] Although not particularly limited, a function for creating a queue without priority is "cuStreamCreate", and a function for creating a queue with priority is "cuStreamCreateWithPriority".

[0049] Fig. 7 shows an example of the operation of the processing priority control unit 12 in Fig. 4. The processing flow shown in Fig. 7 is realized by the processor 10 executing a control program. That is, Fig. 7 shows an example of a calculation processing method by the processor 10. The processing flow shown in Fig. 7 is executed during an initialization period (evaluation period) before the pipeline control unit 11 causes the accelerator 40 to execute multiple data processes.

[0050] First, in step S10, the performance analysis unit 13 of the processing priority control unit 12 obtains dummy data for performance analysis from the memory 20 or the auxiliary storage device 30 and writes it to the shared memory 15. The dummy data includes input data that causes the accelerator 40 to execute the calculations of each stage 43. Then, the performance analysis unit 13 transfers the dummy data from the shared memory 15 to the memory 50 and causes the accelerator 40 to execute the calculations of each stage 43.

[0051] Next, in step S20, the performance analysis unit 13 measures the processing time required for the calculation process of each stage 43. In the example shown in Fig. 7, the processing time of the stage 43c is the longest, and the processing time of the stage 43d is the shortest.

[0052] Next, in step S30, the distribution instruction unit 14 of the processing priority control unit 12 sets the priority of each stage 43 in descending order of processing time based on the processing time measured by the performance analysis unit 13. For example, the distribution instruction unit 14 sets the priority of stage 43c, which has the longest processing time, to the highest priority of "1," and sets the priority of stage 43b, which has the second longest processing time, to the second highest priority of "2." The distribution instruction unit 14 sets the priority of stage 43a, which has the third longest processing time, to "3," and sets the priority of stage 43d, which has the shortest processing time, to the lowest priority of "4."

[0053] Next, in step S40, the distribution instruction unit 14 associates the thread ID (or process ID) that executes the arithmetic processing of each stage 43 with a priority. For example, the distribution instruction unit 14 associates the priority "1" of stage 43a with the thread ID (or process ID) "1113" that executes the arithmetic processing of stage 43c. The distribution instruction unit 14 associates the priority "2" of stage 43b with the thread ID (or process ID) "1112" that executes the arithmetic processing of stage 43b. The distribution instruction unit 14 also associates the priorities of the other stages 43 with thread IDs.

[0054] Next, in step S50, the distribution instruction unit 14 hooks the API of the driver of the accelerator 40 as described in Fig. 6, thereby reassigning the priority determined in step S30 for each stage 43. Next, in step S60, the distribution instruction unit 14 regenerates the queue 45 having the priority set in step S50, and completes the initialization operation shown in Fig. 7.

[0055] Fig. 8 shows an example of pipeline parallel processing executed by the information processing device 100 of Fig. 2. In the pipeline parallel processing shown in Fig. 8, image recognition processing is executed using the trained neural network shown in Fig. 4. The upper part of Fig. 8 shows an example of pipeline parallel processing when the processing priority control unit 12 is not operated and the priority is not associated with the length of processing time. The lower part of Fig. 8 shows an example of pipeline parallel processing when the processing priority control unit 12 is operated and the priority is associated with the length of processing time.

[0056] When the processing priority control unit 12 is not operated, as shown in FIG. 7, the processing time increases in the order of stages 43c, 43b, 43a, and 43d. Because the processing time of each stage 43 varies, a wait time tends to occur between two adjacent stages 43 until the operation of the subsequent stage 43 starts. The wait time increases as the processing time of the subsequent stage 43 increases, and accumulates as the pipeline parallel processing progresses. Therefore, when the processing priority control unit 12 is not operated, the execution efficiency of the operation processing by the pipeline parallel processing decreases.

[0057] In a pipeline design, the amount of processing in each stage is set to be approximately equal. However, for example, if another arithmetic process interrupts the arithmetic process of stage 43c, the processing time of stage 43c will be extended. The lower the priority set for stage 43c, the more likely the arithmetic process interrupts. In FIG. 8, other arithmetic processes interrupt the arithmetic process of stage 43c all at once, but the interrupts from other arithmetic processes may occur multiple times at intervals.

[0058] On the other hand, when the processing priority control unit 12 is operated, the distribution instruction unit 14 sets the priority of each stage 43 in descending order of the processing time. This allows the priority to be set higher for stages 43 that have a higher interrupt frequency and longer processing times, making it possible to make the processing times of each stage approximately equal.

[0059] Therefore, the processor 10 can shorten the waiting time between two adjacent stages 43 until the start of the operation of the later stage 43. As a result, the processor 10 can reduce unnecessary waiting time compared to when the processing priority control unit 12 is not operated, and can improve the execution efficiency of the operation processing by pipeline parallel processing. In other words, even in this embodiment, it is possible to improve the throughput of the information processing device 100 that executes multiple data processing operations divided into multiple pipeline stages.

[0060] Fig. 9 shows an example of the change in processing time before and after priority control by the processing priority control unit 12 in Fig. 4. Fig. 9 shows the change in processing time when frames 120 to 138 of a video are processed in real time in stage 43c, which has the longest processing time as measured in Fig. 7.

[0061] The processing time before priority control corresponds to the case where the processing priority control unit 12 in Fig. 8 is not operating, and the processing time after priority control corresponds to the case where the processing priority control unit 12 in Fig. 8 is operating. In the processing time for each frame, "images" indicates reading of input data, "CPN_prep" indicates preprocessing, and "CPN_resize" indicates resizing of image data. "model" indicates image processing, and "CPN_peak" indicates post-processing.

[0062] Before priority control, there was a large variation in processing time depending on the frame. In stage 43c, the processing volume for each frame was roughly the same. Therefore, the increase in processing time was caused by processing delays due to interrupts from other processes. The maximum processing time before priority control was 112 ms. For example, when processing video without dropping any frames, the video input from the camera must be kept to 8 frames per second or less.

[0063] On the other hand, after priority control with a high priority is applied, the maximum processing time improves to 63 ms. When processing video without dropping frames, video input from the camera can be up to 15 frames per second. Therefore, by executing priority control using the processing priority control unit 12, the processor 10 can improve the performance of image recognition processing.

[0064] As described above, this embodiment can also achieve the same effects as the above-described embodiment. For example, it is possible to shorten the processing time of stage 43, which had been extended due to interrupts from other processes before priority setting. Therefore, in pipeline parallel processing in which multiple data processes each divided into multiple stages 43 are executed sequentially, the information processing device 100 can make the processing times of the multiple stages 43 approximately equal. As a result, the information processing device 100 can improve the execution efficiency of data processing using pipeline parallel processing.

[0065] The distribution instruction unit 14 reassigns priorities for each of the multiple stages 43 by hooking the API of the driver of the accelerator 40. As a result, even if the pipeline control unit 11 cannot set the priority of each stage 43, the information processing device 100 can set the priority by the distribution instruction unit 14 according to the actual processing time of each stage 43. The measurement of processing time by the performance analysis unit 13 and the setting of priorities by the distribution instruction unit 14 are performed during an initialization period before the accelerator 40 sequentially executes multiple data processing tasks in parallel. Because the priority of each stage 43 is set in advance, the information processing device 100 can prevent a decrease in processing efficiency when executing data processing.

[0066] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims encompass the features and advantages of the above-described embodiments without departing from the spirit and scope of the claims. Furthermore, any improvements and modifications will be readily apparent to those skilled in the art. Therefore, it is not intended that the scope of the inventive embodiments be limited to the above-described embodiments, and appropriate improvements and equivalents within the scope of the disclosed embodiments may be utilized. [Explanation of symbols]

[0067] 1. Processing unit 2 Pipeline control section 3. Measurement section 4 Priority setting section 5 Processing section 10 processors 11 Pipeline control section 12 Processing priority control section 13 Performance Analysis Department 14 Distribution instruction section 15 Shared Memory 18 External command control section 20 memory 30 Auxiliary storage 40 Accelerator 41 Pipeline 42 Input Stage 43 Calculation Stage 44 Output Stage 45a, 45b, 46 cues 50 memory 60 Connection interface section 70 Input interface section 80 Output interface section 90 Network Interface Unit

Claims

1. a pipeline control unit that inputs processing instructions for each type of pipeline stage to the processing unit, causing the processing unit to execute a plurality of data processes, each of which is divided into a plurality of types of pipeline stages, in parallel with shifted timing; a measurement unit that measures a processing time for each of the plurality of types of pipeline stages; a priority setting unit that sets a priority for each type of the plurality of types of pipeline stages in descending order of measured processing time; and the pipeline control unit, after the priority setting unit has set the priority, inputs processing instructions to the processing unit in order starting from the processing instruction of the pipeline stage with the highest priority; The priority setting unit changes the priority for each of the plurality of types of pipeline stages by hooking an application programmable interface of a driver that controls the operation of the processing unit. Processing unit.

2. The measurement of processing time by the measurement unit and the setting of priorities by the priority setting unit are performed before the pipeline control unit causes the processing units to execute the plurality of types of data processing. The processor according to claim 1 .

3. inputting processing instructions for each type of pipeline stage to the processing unit, which causes the processing unit to execute a plurality of data processes, each of which is divided into a plurality of types of pipeline stages, in parallel with shifted timing; measuring a processing time for each of the plurality of types of pipeline stages; setting a priority for each type of the plurality of types of pipeline stages in descending order of measured processing time; After setting the priority, inputting the processing instructions to the processing unit in order from the processing instruction of the pipeline stage with the highest priority; By hooking an application programmable interface of a driver that controls the operation of the processing unit, the priority is changed for each type of the plurality of types of pipeline stages. Arithmetic processing method.

Images