Buried Microstrip Transmission Line

Abstract

Techniques are provided for embedded microstrip transmission lines implemented in one or more superconducting microwave electronic devices. For example, one or more embodiments described herein may include an apparatus that includes a superconducting material layer disposed on a ridge of a dielectric substrate. The ridge may protrude from a surface of the dielectric substrate. The apparatus may also include a dielectric film covering the superconducting material layer and at least a portion of the ridge of the dielectric substrate.

Description

[Technical Field]

[0001] The subject disclosure relates to the structure and / or fabrication of buried microstrip transmission lines, and more particularly to one or more microstrip transmission lines that may be buried under a superconducting ground plane to reduce crosstalk in superconducting microwave electronic devices. Summary of the Invention

[0002] The following presents a summary to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements or to delineate the scope of particular embodiments or claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, systems, apparatus, and / or methods related to buried microstrip transmission lines are described.

[0003] According to one embodiment, an apparatus is provided. The apparatus may include a layer of superconducting material disposed on a ridge of a dielectric substrate. The ridge may protrude from a surface of the dielectric substrate. The apparatus may also include a dielectric film covering the layer of superconducting material and at least a portion of the ridge of the dielectric substrate.

[0004] According to one embodiment, a method is provided. The method may include depositing a superconducting material layer on a dielectric substrate. The method may also include disposing the superconducting material layer on a raised portion of the dielectric substrate by etching the superconducting material layer and the dielectric substrate. Additionally, the method may include depositing a dielectric film on the superconducting material layer and the dielectric substrate.

[0005] According to one embodiment, another device is provided. The device may include a first chip including a superconducting qubit disposed on a first dielectric substrate. The device may also include a second chip bonded to the first chip, the second chip including a superconducting material layer disposed on a raised portion of a second dielectric substrate, and a dielectric film covering the superconducting material layer and at least a portion of the raised portion. The raised portion may protrude from a surface of the dielectric substrate. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram of an exemplary, non-limiting microstrip transmission line structure that may be embedded beneath the ground plane of one or more superconducting microwave devices according to one or more embodiments described herein. [Figure 2] FIG. 1 is a diagram of an exemplary, non-limiting microstrip transmission line during a first stage of fabrication, according to one or more embodiments described herein. [Figure 3] FIG. 1 is a diagram of an exemplary non-limiting microstrip transmission line during a second stage of fabrication according to one or more embodiments described herein. [Figure 4] FIG. 10 is a diagram of an exemplary non-limiting microstrip transmission line during a third stage of fabrication in accordance with one or more embodiments described herein. [Figure 5] FIG. 10 is a diagram of an exemplary non-limiting microstrip transmission line during a fourth stage of fabrication according to one or more embodiments described herein. [Figure 6] FIG. 1 is an exemplary, non-limiting side view of a stacked quantum computing device according to one or more embodiments described herein. [Figure 7] FIG. 1 illustrates an exemplary, non-limiting plan view of a quantum computing device chip that may include an embedded microstrip transmission line that may be operably coupled to a coplanar waveguide transmission line, according to one or more embodiments described herein. [Figure 8]FIG. 1 illustrates an exemplary, non-limiting plan view of a quantum computing device chip that may include embedded microstrip transmission lines that may be operably coupled to signal bumps in accordance with one or more embodiments described herein. [Figure 9] 1A-1B are diagrams of an exemplary, non-limiting chip of a quantum computing device that may include an embedded microstrip transmission line that may be operably coupled to a signal bump according to one or more embodiments described herein. [Figure 10] FIG. 1 illustrates an exemplary, non-limiting plan view of a quantum computing device chip that may include embedded microstrip transmission lines that may be operably coupled to qubits, according to one or more embodiments described herein. [Figure 11] FIG. 1 illustrates a flow diagram of an exemplary, non-limiting method that may facilitate fabricating a buried microstrip transmission line in accordance with one or more embodiments described herein. [Figure 12] FIG. 1 illustrates a flow diagram of an exemplary, non-limiting method that may facilitate fabricating a buried microstrip transmission line in accordance with one or more embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0007] The following detailed description is merely exemplary and is not intended to limit the embodiments and / or their application or uses, nor is it intended to be bound by any express or implied information presented in the preceding "Technical Field" or "Summary" sections or in the "Description of the Preferred Embodiments" section.

[0008] One or more embodiments will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent in various instances that the one or more embodiments may be practiced without these specific details. Furthermore, features represented in the drawings by, for example, shading, cross-hatching, or coloring, or a combination thereof, may have a common composition or material, or both.

[0009] Superconducting microwave electronics utilize transmission lines to transmit signals and / or for circuit elements such as filters and / or resonators as building blocks. Traditionally, coplanar waveguide (CPW) transmission lines fabricated from superconducting materials have been employed due to their ease of fabrication and / or low-loss tangent elements. However, CPW transmission lines can suffer from significant crosstalk, which can limit the miniaturization and placement of transmission lines on a chip. To prevent unacceptable levels of crosstalk, CPW transmission lines must be physically spaced relatively far apart. Furthermore, prior art shields CPW transmission lines using, for example, air-bridge ground straps, ground bumps, or both. Thus, the surface area of ​​a superconducting microwave electronic device can be substantially covered by transmission lines. For example, a significant portion of a quantum processor chip may be composed of transmission lines. Thus, the circuit architecture (e.g., the number and / or placement of qubits in a quantum processor) may be limited by the size, number, and / or location of the CPW transmission lines and / or shielding elements.

[0010] Various embodiments of the present invention may be directed to devices, systems, or methods, or combinations thereof, related to buried microstrip transmission lines. For example, one or more embodiments described herein may relate to a microstrip transmission line disposed beneath a superconducting ground plane. The microstrip transmission line may be disposed on a ridge of a recessed substrate and / or covered by a low-loss dielectric film. This configuration of the microstrip transmission line may provide low-crosstalk shielding. In various embodiments, the reduced crosstalk experienced by buried microstrip transmission lines may enable higher density transmission lines compared to prior art. Furthermore, in one or more embodiments, buried microstrip transmission lines may be employed in one or more quantum computing devices, such as readout resonators.

[0011] As described herein, the term "deposition process" and / or "deposition processes" may refer to any process that produces, coats, deposits, or otherwise transfers one or more first materials onto one or more second materials, or a combination thereof.Exemplary deposition processes include physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), atomic layer deposition ("ALD"), low-pressure chemical vapor deposition ("LPCVD"), plasma-enhanced chemical vapor deposition ("PECVD"), high-density plasma chemical vapor deposition ("HDPCVD"), sub-atmospheric pressure chemical vapor deposition ("SACVD"), rapid thermal chemical vapor deposition ("RTCVD"), in situ radical-assisted deposition, high temperature oxide deposition ("HTO"), low temperature oxide deposition ("LTO"), limited reaction processing CVD ("LRPCVD"). These include, but are not limited to, deposition, reaction processing (CVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), metalorganic chemical vapor deposition (MOCVD), chemical oxidation, sputtering, plating, evaporation, spin-on coating, ion beam deposition, electron beam deposition, laser assisted evaporation, chemical solution deposition, combinations thereof, and / or the like.

[0012] As described herein, the terms “etching process,” “etching processes,” “removal process,” or “removal processes,” or combinations thereof, may refer to any process that removes one or more first materials from one or more second materials. Examples of etching processes and / or removal processes include, but are not limited to, wet etching, dry etching (e.g., reactive ion etching (“RIE”), deep reactive ion etching (“DRIE”), or the like, or combinations thereof), chemical-mechanical planarization (“CMP”), combinations thereof, and / or the like.

[0013] As described herein, the terms "lithography process" and / or "lithography processes" can refer to the formation of a three-dimensional relief image or three-dimensional pattern on a material for subsequent transfer of the pattern to the material. In lithography, the pattern can be formed with a light-sensitive polymer called a photoresist. Multiple lithography processes and / or multiple etch-pattern transfer steps can be repeated multiple times to build the complex structures that make up electronic devices and the many interconnects that connect various features of a circuit. Each pattern printed on the wafer can be aligned with previously formed patterns, and features of interest (e.g., conductors, insulators, or selectively doped regions, or a combination thereof) can be gradually built up to form the final device.

[0014] As described herein, the term "superconducting" may describe the property of a material that exhibits superconducting properties below a superconducting critical temperature, such as aluminum (e.g., a superconducting critical temperature of 1.2 Kelvin) or niobium (e.g., a superconducting critical temperature of 9.3 Kelvin). In addition, those skilled in the art will recognize that other superconductor materials (e.g., hydride superconductors such as lithium / magnesium hydride alloys) may be used in various embodiments described herein.

[0015] As described herein, the term "low loss" can describe the property of a material that exhibits a loss tangent that is e-5 or less at microwave frequencies (e.g., between about 1 gigahertz (GHz) and about 10 GHz).

[0016] FIG. 1 illustrates an exemplary, non-limiting cross-sectional view of a microstrip transmission line structure 100. Repetitive descriptions of similar elements employed in other embodiments described herein are omitted for brevity. FIG. 1 illustrates a cross-sectional view of the microstrip transmission line structure 100 along an exemplary A-A′ plane. Additionally, the microstrip transmission line structure 100 may include a superconducting material layer 102 at least partially covered by a dielectric film 104 and disposed below a superconducting electrode 106. Furthermore, the superconducting material layer 102 may be disposed on a raised portion 108 of a substrate 110.

[0017] In various embodiments, substrate 110 may be a low-loss substrate. For example, substrate 110 may comprise a low-loss dielectric material suitable for superconducting microwave electronic devices. In one or more embodiments, substrate 110 may be suitable for use in one or more quantum computing circuit elements. Exemplary materials that may be included within substrate 110 may include, but are not limited to, silicon, sapphire, silicon-on-insulator ("SOI"), combinations thereof, and / or the like. For example, in one or more embodiments, substrate 110 may be a silicon wafer.

[0018] As shown in FIG. 1 , the top surface 112 of the substrate 110 may be recessed (e.g., along the “Y” axis shown in FIG. 1 ) to define a ridge 108 of the substrate 110. For example, the ridge 108 may protrude from the top surface 112 to a tip 114. The tip 114 may protrude from the top surface 112 to a height (e.g., along the “Y” axis shown in FIG. 1 ) in the range of, for example, 10 nanometers (nm) or more and 500 nm or less. Additionally, the ridge 108 may have a width (e.g., along the “X” axis shown in FIG. 1 ) based on one or more operational characteristics of the resulting microstrip transmission line (e.g., 10 micrometers (μm)). For example, the ridge 108 may have a width (e.g., along the “X” axis shown in FIG. 1 ) in the range of 2 μm or more and 20 μm or less.

[0019] The location of the ridges 108 on the substrate 110 may depend on the desired location of the microstrip transmission line structure 100. Furthermore, in various embodiments, the ridges 108 may run across the top surface 112 according to one or more patterns to facilitate a desired circuit layout on the substrate 110. While FIG. 1 shows a single microstrip transmission line structure 100 on the substrate 110, the architecture is not so limited. For example, multiple microstrip transmission line structures 100 may be disposed on the substrate 110. If multiple microstrip transmission line structures 100 are employed, each microstrip transmission line structure 100 may include one or more superconducting material layers 102 disposed on a respective ridge 108. In one or more embodiments, a single microstrip transmission line may be disposed on each ridge 108 according to the microstrip transmission line structure 100.

[0020] The one or more superconducting material layers 102 may form one or more microstrip transmission lines, or one or more other circuit elements (e.g., capacitive pads, bus resonators, direct capacitive couplers (e.g., between qubits), inter-qubit coupling elements, input / output capacitors, readout resonators, Purcell filters, combinations thereof, and / or the like), or both. Exemplary superconducting materials that may be included within the one or more superconducting material layers 102 may include, but are not limited to, niobium, aluminum, titanium, tantalum, rhenium, titanium nitride, combinations thereof, and / or the like. For example, the one or more superconducting material layers 102 may be one or more layers of niobium. In various embodiments, the one or more superconducting material layers 102 may be disposed on the surface of the tip 114 of the ridge 108. For example, the placement of the one or more superconducting material layers 102 may be limited to the ridge 108.

[0021] In one or more embodiments, the one or more superconducting material layers 102 may have a thickness (e.g., along the "Y" axis shown in FIG. 1 ) ranging from 10 nm to 500 nm, for example. The one or more superconducting material layers 102 may also have a width (e.g., along the "X" axis shown in FIG. 1 ) ranging from 2 μm to 20 μm, for example. While FIG. 1 depicts the one or more superconducting material layers 102 comprising a single layer, the architecture of the one or more superconducting material layers 102 is not so limited. Embodiments in which the one or more superconducting material layers 102 comprise multiple layers are also contemplated. Furthermore, when the one or more superconducting material layers 102 comprise multiple layers, the composition of each layer may be the same or different. Additionally, the thickness and / or width of the one or more superconducting material layers 102 may be substantially the same along the extent of the one or more superconducting material layers 102 running across the ridge 108, or may vary along one or more portions of the ridge 108.

[0022] The one or more superconducting material layers 102 may be substantially covered or at least partially covered by one or more dielectric films 104. In various embodiments, the one or more dielectric films 104 may include a low-loss dielectric material. Exemplary materials that may be included within the one or more dielectric films 104 may include, but are not limited to, hydrogenated amorphous silicon ("α-Si:H"), polysilicon, silicon-germanium, combinations thereof, and / or the like. In one or more embodiments, the one or more dielectric films 104 may have a thickness (e.g., along the "Y" axis shown in FIG. 1 ) above the one or more superconducting material layers 102, for example, in the range of 10 nm or more and 2 μm or less.

[0023] 1 , the one or more dielectric films 104 may cover one or more superconducting material layers 102 and / or ridges 108 of the substrate 110. For example, the one or more dielectric films 104 may extend (e.g., along the “X” axis shown in FIG. 1 ) from a location above the one or more superconducting material layers 102 and / or ridges 108 to a location above the recessed top surface 112 of the substrate 110. In various embodiments, the one or more superconducting material layers 102 may be embedded between the tips 114 of the ridges 108 and the one or more dielectric films 104. Furthermore, according to one or more embodiments described herein, the one or more dielectric films 104 may be patterned to expose one or more portions of the one or more superconducting material layers 102.

[0024] The superconducting electrode 106 may be further disposed on the one or more dielectric films 104. In various embodiments, the superconducting electrode 106 may be a superconducting ground plane for one or more superconducting microwave devices. Exemplary superconducting materials that may be included within the superconducting electrode 106 may include, but are not limited to, aluminum, niobium, titanium, tantalum, rhenium, titanium nitride, combinations thereof, and / or the like. As shown in FIG. 1 , the superconducting electrode 106 may extend from a position above one or more superconducting material layers 102 and / or ridges 108 to a position above the top surface 112 of the substrate 110. For example, if the superconducting electrode 106 is disposed above the top surface 112, the superconducting electrode 106 may be disposed at a height from the top surface 112 that is below the tips 114 of the ridges 108. Thus, at least a portion of the superconducting electrode 106 may be disposed at a height (e.g., along the “Y” axis) that is lower than the height of the one or more superconducting material layers 102. Thus, the superconducting electrodes 106 may at least partially surround one or more layers of superconducting material 102 .

[0025] In various embodiments, the superconducting electrodes 106 may be further patterned to facilitate the creation of one or more circuit elements on the substrate 110. For example, the superconducting electrodes 106 may be patterned to couple one or more signals to buried microstrip transmission lines formed by one or more layers of superconducting material 102.

[0026] FIG. 2 shows a diagram of an exemplary, non-limiting microstrip transmission line structure 100 during a first stage of fabrication. Repetitive descriptions of similar elements employed in other embodiments described herein are omitted for brevity. As shown in FIG. 2, during the first stage of fabrication, one or more superconducting material layers 102 may be deposited on a substrate 110. The one or more superconducting material layers 102 may be deposited by one or more deposition processes, such as sputtering. Following deposition in the first stage of fabrication, the one or more superconducting material layers 102 and / or the substrate 110 may be patterned to define one or more superconducting circuit elements, such as a buried microstrip transmission line (e.g., as shown in FIG. 1).

[0027] FIG. 3 shows a diagram of an exemplary, non-limiting microstrip transmission line structure 100 during a second stage of fabrication. Repetitive descriptions of similar elements employed in other embodiments described herein are omitted for brevity. As shown in FIG. 3 , during the second stage of fabrication, one or more resist layers 302 may be deposited on one or more dielectric layers 104 by one or more deposition processes. In various embodiments, the one or more resist layers 302 may be patterned on one or more superconducting material layers 102 at locations corresponding to desired locations for one or more microstrip transmission lines formed from the one or more superconducting material layers, or one or more other circuit elements (e.g., resonators, filters, capacitive pads, bus resonators, direct capacitance filters, combinations thereof, and / or the like), or both.

[0028] In various embodiments, the one or more resist layers 302 may protect portions of the one or more superconducting material layers 102 and / or the substrate 110 from one or more subsequent etching processes. The thickness of the one or more resist layers 302 (e.g., along the “Y” axis shown in FIG. 3 ) may depend on the amount of etching performed by the one or more etching processes, the composition of the resist layers 302, or both. For example, the thickness of the one or more resist layers 302 may range from 500 nm or more to 3 μm or less. Exemplary materials that may be included within the one or more resist layers 302 may include, but are not limited to, polymethyl methacrylate (“PMMA”), AZ5214, SU-8, combinations thereof, and / or the like. For example, in one or more embodiments, the one or more resist layers 302 may be photoresist layers.

[0029] FIG. 4 illustrates a diagram of an exemplary, non-limiting microstrip transmission line structure 100 during a third stage of fabrication. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for the sake of brevity. As shown in FIG. 4 , during the third stage of fabrication, one or more portions of one or more superconducting material layers 102, or substrate 110, or both, may be removed by one or more etching processes. For example, RIE may be employed to selectively remove portions of one or more superconducting material layers 102, or substrate 110, or both, during the third stage of fabrication.

[0030] As shown in FIG. 4 , portions of one or more superconducting material layers 102 and / or substrate 110 covered by one or more resist layers 302 may be protected from one or more etching processes. As a result of the one or more etching processes, the top surface 112 of the substrate may be recessed to define a ridge 108. For example, the ridge 108 may be a portion of the substrate 110 covered by the one or more resist layers 302 and thus protected from the one or more etching processes. In various embodiments, the one or more etching processes may define a height of the ridge 108 from the top surface 112 (e.g., represented by “H1” in FIG. 4 ), thereby defining a height of the one or more superconducting material layers 102 from the top surface 112 (e.g., represented by “H1” in FIG. 4 ). After the one or more etching processes, the one or more resist layers 302 may be removed.

[0031] 5 shows a diagram of an exemplary, non-limiting microstrip transmission line structure 100 during a fourth stage of fabrication. Repetitive descriptions of similar elements employed in other embodiments described herein are omitted for the sake of brevity. As shown in FIG. 5, during the fourth stage of fabrication, one or more dielectric films 104 may be deposited on one or more superconducting material layers 102, or on the substrate 110, or both, by one or more deposition processes. For example, the one or more dielectric films 104 may be deposited by CVD, PECVD, sputtering, catalytic CVD, combinations thereof, and / or the like.

[0032] As shown in FIG. 5 , one or more dielectric films 104 may cover one or more superconducting material layers 102, the ridges 108 of the substrate 110, or the top surface of the substrate 110, or a combination thereof. In various embodiments, the one or more dielectric films 104 may exhibit a constant or near-constant thickness. In one or more embodiments, portions of the dielectric film 104 may be thinner or thicker relative to other portions of the dielectric film 104. Furthermore, in various embodiments, the one or more dielectric films 104 may be patterned to facilitate producing one or more circuit elements from the one or more superconducting material layers 102. For example, the one or more dielectric films 104 may be patterned to cover one or more portions of the one or more superconducting material layers 102 while leaving one or more other portions of the one or more superconducting material layers 102 exposed.

[0033] During a fifth stage of fabrication, one or more superconducting electrodes 106 may be further deposited on the one or more dielectric films 104 to achieve the structure depicted in Figure 1. The one or more superconducting electrodes 106 may be deposited by one or more deposition processes, such as sputtering, electron beam evaporation, or the like, or a combination thereof.

[0034] In various embodiments, one or more superconducting electrodes 106 may exhibit a constant or near-constant thickness. In one or more embodiments, portions of the superconducting electrodes 106 may be thinner or thicker relative to other portions of the superconducting electrodes 106. Furthermore, in various embodiments, one or more superconducting electrodes 106 may be patterned to facilitate creating one or more circuit elements coupled to one or more layers of superconducting material 102. For example, one or more superconducting electrodes 106 may be patterned by one or more lithography processes, etching processes, resist stripping, or cleaning processes, or a combination thereof.

[0035] In various embodiments, the microstrip transmission line structure 100 may be employed in one or more microwave electronic devices, such as quantum computers and / or quantum computing devices. For example, the microstrip transmission line structure 100 may be employed in one or more quantum computers that include quantum hardware devices that can utilize the laws of quantum mechanics (e.g., superposition and / or entanglement) to facilitate computational processing (e.g., while satisfying the DiVincenzo criterion). In one or more embodiments, the one or more quantum computers may include a quantum data plane, a control processor plane, a control and measurement plane, and / or qubit technology.

[0036] In one or more embodiments, a quantum data plane may include one or more quantum circuits, including physical qubits, structures for fixing the positions of qubits, and / or support circuitry. The support circuitry may, for example, facilitate measurement of the qubit states, perform gate operations on the qubits, or both (e.g., in the case of gate-based systems). In some embodiments, the support circuitry may comprise a wiring network that may enable multiple qubits to interact with one another. Furthermore, the wiring network may facilitate transmission of control signals via direct electrical connections, electromagnetic radiation (e.g., optical, microwave, or low-frequency signals, or a combination thereof), or both. For example, the support circuitry may comprise one or more superconducting resonators operably coupled to one or more qubits.

[0037] In one or more embodiments, the control processor plane may verify and / or initiate Hamiltonian sequences of quantum gate operations and / or measurements, which may execute programs (e.g., provided by a host processor) to execute quantum algorithms. For example, the control processor plane may translate compiled code into commands for the control and measurement planes. In one or more embodiments, the control processor plane may further execute one or more quantum error correction algorithms.

[0038] In one or more embodiments, the control and measurement plane may convert digital signals generated by the control processor plane that may accurately describe a quantum operation to be performed into analog control signals to perform that operation on one or more qubits in the quantum data plane. The control and measurement plane may also convert one or more analog measurement outputs of qubits in the data plane into classical binary data that can be shared with other computer components.

[0039] Those skilled in the art will recognize that various qubit technologies can provide the underlying principles for one or more qubits in one or more quantum computers. Two exemplary qubit technologies can include trapped ion qubits or superconducting qubits, or both. For example, if a quantum computer utilizes trapped ion qubits, the quantum data plane can include multiple ions that act as qubits and one or more traps that function to hold the ions in specific locations. Additionally, the control and measurement plane can include a laser or microwave source directed at one or more ions to affect their quantum state, a laser to cool the ions and / or enable measurement of the ions, and / or one or more photon detectors to measure the ions' state. In another example, a superconducting qubit (e.g., a superconducting quantum interference device, or "SQUID") can be a lithographically defined electronic circuit that can be cooled to millikelvin temperatures and exhibit quantized energy levels (e.g., due to quantized states of electron charge or magnetic flux). The superconducting qubits may be Josephson junction-based transmon qubits, and / or the like. Superconducting qubits are also compatible with microwave-controlled electronics and may be utilized with gate-based technologies or integrated cryogenic control. Additional exemplary qubit technologies may include, but are not limited to, photonic qubits, quantum dot qubits, gate-based neutral atom qubits, semiconductor qubits (e.g., optically or electrically gated), topological qubits, combinations thereof, and / or the like.

[0040] FIG. 6 illustrates a cross-sectional view of an exemplary, non-limiting stacked quantum computing device 600 that may include a microstrip transmission line structure 100 in accordance with one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. As shown in FIG. 6 , stacked quantum computing device 600 may include a first chip 602 that may include one or more superconducting qubits 604 and a second chip 606 that may include a microstrip transmission line structure 100. In various embodiments, stacked quantum computing device 600 may be included in one or more quantum computers. For example, first chip 602 may be included in the quantum data plane of a quantum computer, or second chip 606 may be included in the control and measurement plane of a quantum computer, or both. For example, second chip 606 may include one or more qubit readout resonators that include a microstrip transmission line structure 100.

[0041] To increase superconducting qubit density and thereby provide more superconducting qubits 604 for quantum data processing operations, quantum computer circuitry may be formed on multiple chips coupled to one another. For example, a first chip 602 and a second chip 606 may each comprise predetermined quantum computer circuitry, and the first chip 602 and the second chip 606 may be stacked on one another and / or coupled via, for example, superconducting interconnects. For example, in one or more embodiments, superconducting interconnects 608, such as bump connections, may be employed to electrically couple one or more components of the first chip 602 to one or more components of the second chip 606. In another example, one or more interconnect 608 bump connections may be employed to physically bond the first chip 602 and the second chip 606 without providing an electrical connection.

[0042] As shown in FIG. 6 , the first chip 602 may include a qubit surface 610 facing the second chip 606. The qubit surface 610 may include one or more superconducting qubits 604, one or more circuit elements interconnecting one or more superconducting qubits 604, or both. For example, the qubit surface 610 may include one or more superconducting resonator lines, buses, gates, filters, coupler qubits, direct capacitive couplers, combinations thereof, and / or the like, which may establish and / or facilitate electrical connections between the superconducting qubits 604. In various embodiments, the qubit surface 610 may be disposed on a low-loss dielectric substrate 110 of the first chip 602 suitable for quantum computing circuit elements (e.g., a silicon or sapphire wafer).

[0043] 6 , second chip 606 may include a wiring surface 614 facing first chip 602. Wiring surface 614 may include microstrip transmission line structures 100. For example, microstrip transmission line structures 100 may function as one or more wiring circuits that facilitate the functioning of the control and measurement plane of the quantum computer. For example, in various embodiments, wiring surface 614 may include qubit readout resonators that couple to one or more superconducting qubits 604, and / or employ microstrip transmission line structures 100. By moving the wiring circuitry of the control and measurement plane (e.g., qubit readout resonators including microstrip transmission line structures 100) to a chip separate from superconducting qubits 604, crosstalk between superconducting qubits 604 and the wiring may be reduced. Additionally, because the microstrip transmission line structure 100 can embed and shield the microstrip transmission line (e.g., composed of one or more superconducting material layers 102) under a superconducting ground plane (e.g., superconducting electrodes 106), crosstalk can be further reduced by employing the microstrip transmission line structure 100 for one or more of the wiring circuit elements.

[0044] In various embodiments, the first chip 602 may be aligned over the second chip 606 and physically connected via one or more interconnects 608. In various embodiments, the one or more interconnects 608 may be one or more bump connections. Additionally, in one or more embodiments, the one or more interconnects 608 may electrically couple components between the first chip 602 and the second chip 606. In one or more embodiments, a vacuum may be maintained between the first chip 602 and the second chip 606.

[0045] In one or more embodiments, one or more of the interconnects 608 may be superconducting bump connections that may electrically couple components between the first chip 602 and the second chip 606. Exemplary materials that may be included in the one or more superconducting bump connections may include, but are not limited to, indium, lead, rhenium, palladium, niobium, gold, titanium, combinations thereof, and / or the like. The thickness (e.g., along the “Y” axis shown in FIG. 6 ) of the interconnects 608 may define the distance between the first chip 602 and the second chip 606. In various embodiments, the spacing between the first chip 602 and the second chip 606 may affect the capacitive or inductive coupling between components of the first chip 602 and the second chip 606. The thickness (e.g., along the “Y” axis shown in FIG. 6 ) of the interconnects 608 may be, for example, 20 μm or more and 100 μm or less.

[0046] FIG. 7 illustrates a plan view of an exemplary, non-limiting second chip 606 according to one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. The plan view illustrated in FIG. 7 may represent a portion of the wiring surface 614 facing the first chip 602. As shown in FIG. 7, the wiring surface 614 may include a wiring architecture including a microstrip transmission line 701 electrically coupled to a first pad element 702 and a second pad element 704 electrically coupled to a coplanar waveguide (“CPW”) transmission line 706. In various embodiments, the microstrip transmission line 701 may have a microstrip transmission line structure 100 and may be defined by the dotted line in FIG. 7. For example, the superconducting electrode 106 may function as a superconducting ground plane covering at least a portion of the wiring surface 614, and the microstrip transmission line 701 may be embedded below the superconducting electrode 106 (e.g., as shown in FIG. 1) at the location defined by the dotted line in FIG. 7.

[0047] As described herein, the microstrip transmission line 701 may have an architecture according to the microstrip transmission line structure 100. For example, an exemplary location of the A-A' cross section depicted in FIG. 1 is indicated by a line in FIG. 7 to illustrate structural features located below the superconducting ground plane of the second chip 606 that are not visible from the plan view shown in FIG. 7. For example, the microstrip transmission line 701 may be located on the raised portion 108 of the substrate 110 of the second chip 606 and may be at least partially covered by one or more low-loss dielectric films 104 according to the microstrip transmission line structure 100.

[0048] In various embodiments, one or more superconducting material layers 102 may form a microstrip transmission line 701 and a first pad element 702. As shown in FIG. 7 , the microstrip transmission line structure 100 (e.g., a metal laminate structure) may allow for coexistence with one or more CPW transmission lines. For example, the first pad element 702 may be disposed adjacent to a second pad element 704 coupled to a CPW transmission line 706. In one or more embodiments, the second pad element 704, or one or more CPW transmission lines 706, or both, may be comprised of superconducting electrodes 106. This allows signals to be transferred from the microstrip transmission line 701 (which may have a low impedance, e.g., about 15 ohms) to the CPW transmission line 706 (which may have a high impedance, e.g., about 50 ohms). Additionally, in various embodiments, first pad element 702 and / or second pad element 704 may be aligned with one or more superconducting qubits 604 when first chip 602 and second chip 606 are stacked and / or bonded to one another.

[0049] In one or more embodiments, a portion of the superconducting electrode 106 may be etched away by one or more etching processes (e.g., during or after the fifth stage of fabrication described herein) to expose the first pad element 702 and / or define the second pad element 704 and the CPW transmission line 706. Additionally, a portion of one or more dielectric films 104 may be optionally etched away along with a portion of the superconducting electrode 106 to expose the first pad element 702 and / or define the second pad element 704 and the CPW transmission line 706 (e.g., as shown in FIG. 7). In one or more embodiments, the one or more dielectric films 104 may remain disposed above the first pad element 702. Also, as shown in FIG. 7, a microstrip transmission line 701 may extend beneath the superconducting electrode 106 (e.g., beneath the ground plane of the second chip 606) and be electrically coupled to the first pad element 702. When first pad element 702 is aligned with superconducting qubit 604 of first chip 602, microstrip transmission line 701 can be laterally moved out of alignment with the qubit.

[0050] FIG. 8 illustrates another plan view of an exemplary, non-limiting second chip 606 according to one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. FIG. 8 depicts an exemplary qubit readout resonator structure that may be on the wiring surface 614 of the second chip 606 and may include a microstrip transmission line structure 100. For example, according to one or more embodiments, the qubit readout resonator depicted in FIG. 8 may comprise a microstrip transmission line 701 described herein and a first pad element 702. Additionally, one or more of the interconnects 608 may be in direct contact with the first pad element 702 (e.g., the superconducting electrode 106 and one or more dielectric films 104 may be etched away to expose the superconducting material layer 102 that forms the first pad element 702). Additionally, one or more interconnects 608 disposed on the first pad element 702 may be electrically coupled to one or more superconducting qubits 604 of the first chip 602. In this manner, signals carried on the microstrip transmission line 701 may be carried to or from other chips (e.g., the first chip 602) via galvanic coupling.

[0051] In various embodiments, the first pad element 702 may be aligned with the superconducting qubit 604 when the first chip 602 and the second chip 606 are bonded to one another (e.g., via interconnects 608). For example, one or more of the interconnects 608 may be disposed on the first pad element 702 and electrically couple the first pad element 702 to one or more aligned components of another chip (e.g., aligned components of the first chip 602). For example, one or more of the interconnects 608 may be disposed on the first pad element 702 and electrically couple the first pad element 702 to aligned superconducting qubits 604 from the first chip 602. In one or more embodiments, one or more of the interconnects 608 may be superconducting bumps disposed on the first pad element 702 (e.g., as shown in FIG. 8 ). This allows signals carried on the microstrip transmission line 701 to be transferred to or from other chips (e.g., to the first chip 602) via interconnects (e.g., superconducting bumps) disposed on the first pad element 702.

[0052] 9(A) shows another plan view of an exemplary, non-limiting second chip 606 according to one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. FIG. 9(A) depicts another exemplary qubit readout resonator structure that may be on the wiring surface 614 of the second chip 606 and may include a microstrip transmission line structure 100. For example, according to one or more embodiments, the qubit readout resonator structure depicted in FIG. 9(A) may comprise a microstrip transmission line 701 and a first pad element 702 described herein.

[0053] In various embodiments, the first pad element 702 (e.g., comprised of one or more superconducting material layers 102) may remain covered by one or more dielectric films 104 and superconducting electrodes 106. As shown in FIG. 9(A), portions of the superconducting electrodes 106 surrounding the periphery of the first pad element 702 may be etched away by one or more etching processes, thereby exposing portions of the one or more dielectric films 104. Additionally, one or more interconnects 608 may be disposed on the portions of the superconducting electrodes 106 covering the first pad element 702. For example, one or more superconducting bumps may be disposed on the superconducting electrodes 106 above the first pad element 702. In this manner, signals carried on the microstrip transmission line 701 may be carried to or from other chips (e.g., the first chip 602) via capacitive coupling. For example, the first pad element 702 may be capacitively coupled to the superconducting qubit 604 of the first chip 602 (e.g., via an interconnect such as a superconducting bump pad), and the amount of capacitive coupling may depend on the size of the first pad element 702, the size of the aligned superconducting qubit 604, or the spacing between the first chip 602 and the second chip 606 (e.g., the thickness of one or more interconnects 608), or a combination thereof.

[0054] FIG. 9(B) shows a cross-sectional view of an exemplary, non-limiting second chip 606 according to one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. FIG. 9(B) depicts a cross-section of the second chip 606 along the B-B′ plane depicted in FIG. 9(A) to illustrate one or more structural features that are otherwise not visible from a plan view of the second chip 606. As shown in FIG. 9(B), the first pad element 702 may be comprised of one or more superconducting material layers 102 disposed on the raised portion 108 of the substrate 110 of the second chip 606. Furthermore, the first pad element 702 may be at least partially covered by one or more dielectric films 104. Furthermore, portions of the superconducting electrodes 106 may be etched away by one or more etching processes to expose a portion of the dielectric film 104 that at least partially surrounds the first pad element 702. Additionally, one or more interconnects 608 (e.g., superconducting bump pads) may be disposed on the superconducting electrode 106 above the first pad element 702. As shown in Figures 7 and / or 8, in one or more embodiments, one or more dielectric films 104 may also be etched away to achieve one or more desired circuit architectures on the wiring surface 614 of the second chip 606.

[0055] FIG. 10 shows a plan view of an exemplary, non-limiting first chip 602 according to one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein are omitted for brevity. For example, FIG. 10 shows a plan view of a qubit surface 610 that may employ one or more transmission lines 701 (e.g., having microstrip transmission line structures 100) operably coupled to one or more superconducting qubits 604. In various embodiments, if the first chip 602 employs features of the microstrip transmission line structures 100 to couple one or more superconducting qubits 604, the first chip 602 may be operated without the second chip 606. For example, a quantum computer may include quantum computing circuitry on a single chip (e.g., the first chip 602) rather than across multiple chips (e.g., as shown in FIG. 6).

[0056] As shown in FIG. 10 , one or more superconducting qubits 604 may be coupled to a first capacitor pad 1002, a second capacitor pad 1004, or one or more Josephson junctions 1006 (e.g., “

number

[0057] In various embodiments, qubit surface 610 may be formed by etching away superconducting electrode 106 and one or more dielectric films 104 to expose first pad element 702 (e.g., comprised of one or more superconducting material layers 102) and the future location of superconducting qubit 604. For example, following the fifth stage of fabrication described herein, top superconducting electrode 106 may be patterned (e.g., by one or more lithography processes). Further, one or more etching processes may be employed to selectively etch away superconducting electrode 106 and one or more dielectric layers 104 in a patterned manner to expose one or more superconducting material layers 102 that may comprise first pad element 702 and a portion of top surface 112 of substrate 110.

[0058] The exposed portion of top surface 112 may then be cleaned, and one or more superconducting metals may be deposited (e.g., by one or more deposition processes) on exposed top surface 112 to form superconducting qubits 604. Thus, one or more superconducting qubits 604 may be deposited on the same chip as microstrip transmission line 701 (e.g., on the same substrate 110 as microstrip transmission line structure 100) without dielectric film 104 being located under first capacitor pad 1002 or second capacitor pad 1004.

[0059] 11 is a flow diagram of an exemplary, non-limiting method 1100 that may be employed to fabricate a microstrip transmission line structure 100 according to one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. In various embodiments, the method 1100 may be employed to fabricate a microstrip transmission line 701 or a first pad element 702, or both, described in one or more embodiments herein. For example, the method 1100 may be employed to fabricate a qubit readout resonator, where crosstalk between the qubit readout resonator and one or more superconducting qubits (e.g., superconducting qubit 604) may be suppressed by the nature of the microstrip transmission line 701 resting on a raised portion 108 of the dielectric substrate 110 and buried beneath the dielectric film 104 and the superconducting electrodes 106.

[0060] At 1102, the method 1100 may include depositing one or more superconducting material layers 102 on the dielectric substrate 110. For example, the depositing at 1102 may be performed according to at least the first stage of fabrication described herein with reference to FIG. 2. At 1104, the method 1100 may include disposing the one or more superconducting material layers 102 on the raised portions of the dielectric substrate 110 by etching the one or more superconducting material layers 102 and the dielectric substrate 110. For example, the disposing at 1104 may be performed according to at least the second and third stages of fabrication described herein with reference to FIGS. 3-4. For example, the one or more superconducting material layers 102 may be patterned with one or more resist layers 302 to selectively recess the dielectric substrate 110 with one or more etching processes. Additionally, etching at 1104 may define the location of a portion of one or more superconducting material layers 102 that may function as one or more circuit elements, such as a transmission line (e.g., microstrip transmission line 701) or a bonding pad (e.g., first pad element 702), or both.

[0061] At 1106, the method 1100 may include depositing one or more dielectric films 104 over the one or more superconducting material layers and the dielectric substrate 110. For example, the deposition at 1106 may be performed according to at least the fourth stage of fabrication described herein with reference to FIG. 5. Additionally, one or more superconducting electrodes 106 may be deposited on the one or more dielectric films 104 to form a ground plane. Thus, the one or more superconducting material layers 102 may be disposed on the raised portion 108 of the dielectric substrate 110, covered by the dielectric film 104, and at least partially buried under the superconducting ground plane.

[0062] 12 shows a flow diagram of an exemplary, non-limiting method 1200 that may be employed to fabricate the microstrip transmission line structure 100 according to one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein are omitted for brevity. In various embodiments, the method 1200 may be employed to fabricate one or more circuit elements on the qubit surface 610 of the first chip 602 and / or the wiring surface 614 of the second chip 606.

[0063] At 1202, method 1200 may include depositing one or more superconducting material layers 102 on a dielectric substrate 110. For example, the deposition at 1202 may be performed according to the first stage of fabrication described herein with reference to at least FIG. 2 . In various embodiments, the dielectric substrate 110 may be a dielectric wafer for the first chip 602 or the second chip 606. At 1204, method 1200 may include patterning the one or more superconducting material layers 102 with one or more resist layers 302. For example, the patterning at 1204 may be performed according to the second stage of fabrication described herein with reference to at least FIG. 3 . In various embodiments, the patterning at 1204 may define the placement of one or more microstrip transmission lines 701 and / or first pad elements 702.

[0064] At 1206, method 1200 may include etching (e.g., by one or more etching processes) the one or more superconducting material layers 102 and the dielectric substrate 110 according to the patterning from 1204. For example, the etching at 1206 may be performed according to at least the third stage of fabrication described herein with reference to FIG. 4. In various embodiments, the etching at 1206 may form a raised portion 108 in the dielectric substrate 110 on which the one or more superconducting material layers 102 of the microstrip transmission line 701 and / or the first pad element 702 may be disposed.

[0065] At 1208, the method 1200 may include depositing (e.g., by one or more deposition processes) one or more dielectric films 104 over the one or more superconducting material layers 102 and the dielectric substrate 110. For example, the deposition at 1208 may be performed according to at least the fourth stage of fabrication described herein with reference to FIG. 5 . At 1210, the method 1200 may include depositing (e.g., by one or more deposition processes) superconducting electrodes 106 onto the one or more dielectric films 104 and over the one or more superconducting material layers 102. At 1212, the method 1200 may include patterning the superconducting electrodes 106 with one or more resist layers 302. At 1214, the method 1200 may include etching (e.g., by one or more etching processes) the superconducting electrodes as patterned at 1212. In one or more embodiments, the etching at 1214 may further etch away one or more portions of one or more dielectric films 104 disposed below the superconducting electrode 106. In various embodiments, the etching at 1214 may define and / or facilitate the formation of one or more circuit elements on the qubit surface 610 and / or the wiring surface 614. For example, the etching at 1214 may expose the first pad element 702 and / or define the second pad element 704 and / or the CPW transmission line 706, as depicted in FIG. 7. In another example, the etching at 1214 may expose the first pad element 702 for contacting the interconnect 608, as depicted in FIG. 8. In a further example, the etching at 1214 may define a portion of the superconducting electrode above the first pad element 702 for capacitive coupling, as depicted in FIG. 9(A).

[0066] In still a further example, the etching at 1214 may expose an upper surface of the dielectric substrate 110 for formation of one or more superconducting qubits 604. For example, at 1216, the method 1200 may include forming a superconducting qubit on the exposed surface of the dielectric substrate 110. For example, the forming at 1216 may be performed by depositing one or more superconducting metals on the exposed surface of the dielectric substrate 110 adjacent to the first pad element 702, as depicted in FIG.

[0067] The foregoing description includes merely exemplary systems, computer program products, and computer-implemented methods. Naturally, for purposes of describing this disclosure, it is not possible to describe every conceivable combination of components, products, or computer-implemented methods, or combinations thereof; however, those skilled in the art will recognize that many additional combinations and permutations of the present disclosure are possible. Furthermore, to the extent that terms such as "includes," "has," and "possesses" are used in the detailed description, claims, appendices, and drawings, these terms are intended to be inclusive, similar to the use of "comprising" when "comprising" is employed as a transitional term in the claims. The description of various embodiments has been presented for illustrative purposes and is not intended to be exhaustive or to be limited to the disclosed embodiments. Many modifications and variations that do not depart from the scope and spirit of the described embodiments will be apparent to those skilled in the art. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. a layer of superconducting material disposed on a raised portion of a dielectric substrate, the raised portion protruding from a first surface of the dielectric substrate; a dielectric film covering the layer of superconducting material and the top and both sides of the protrusion of the dielectric substrate; the ridge projects from the first surface to a tip, and the layer of superconducting material is on a second surface of the tip. Device.

2. 10. The device of claim 1, wherein the dielectric film has a dissipation factor of 5e-5 or less at a frequency between 4.5 and 5.5 gigahertz.

3. The apparatus of claim 2 , wherein the layer of superconducting material is fastened to the second surface.

4. 4. The device according to claim 1, further comprising a superconducting electrode disposed on the dielectric film and overlying the layer of superconducting material.

5. 5. The apparatus of claim 4, wherein the superconducting electrode extends from a first location above the layer of superconducting material to a second location above the first surface of the dielectric substrate.

6. 6. The apparatus of claim 5, wherein the superconducting material layer is disposed at a first height from the first surface and the superconducting electrode at the second position is disposed at a second height from the first surface, the first height being greater than the second height.

7. a layer of superconducting material disposed on a raised portion of a dielectric substrate, the raised portion protruding from a first surface of the dielectric substrate; a dielectric film covering the superconducting material layer and at least a portion of the protrusion of the dielectric substrate; Equipped with the superconducting material layer is a microstrip transmission line, and further comprising a superconducting electrode disposed on the dielectric film overlying the superconducting material layer, the superconducting electrode being a ground plane, and the microstrip transmission line being buried beneath the ground plane.

8. 7. The device of claim 1, wherein the device is a qubit readout resonator.

9. depositing a layer of superconducting material on a dielectric substrate; disposing the superconducting material layer on the raised portion of the dielectric substrate by etching the superconducting material layer and the dielectric substrate; depositing a dielectric film on the dielectric substrate so as to cover the superconducting material layer and both sides of the protrusion; depositing a superconducting electrode on the dielectric film overlying the layer of superconducting material; A method comprising:

10. The method of claim 9 , wherein the etching forms the ridges by recessing the dielectric substrate.

11. The method of claim 10 , wherein the dielectric film and the superconducting electrodes extend above a portion of the dielectric substrate recessed by the etching.

12. 12. The method of claim 9, wherein the dielectric film has a dissipation factor of 5e-5 or less at a frequency between 4.5 and 5.5 gigahertz.

13. depositing a layer of superconducting material on a dielectric substrate; disposing the superconducting material layer on the raised portion of the dielectric substrate by etching the superconducting material layer and the dielectric substrate; depositing a dielectric film over the layer of superconducting material and the dielectric substrate; removing a portion of the dielectric film from above a portion of the dielectric substrate recessed by the etching; and depositing a superconducting metal over the portion of the dielectric substrate recessed by the etching, thereby forming a superconducting qubit.

14. a first chip including superconducting qubits disposed on a first dielectric substrate; a second chip bonded to the first chip, the second chip including a layer of superconducting material disposed on a raised portion of a second dielectric substrate and a dielectric film covering the layer of superconducting material and both sides of the raised portion, the raised portion protruding from a surface of the second dielectric substrate.

15. 15. The device of claim 14, wherein the dielectric film has a loss tangent that is less than or equal to 5e-5 at a frequency between 4.5 and 5.5 gigahertz.

16. 16. The apparatus of claim 14, wherein the second tip further comprises a superconducting electrode disposed on the dielectric film and between the dielectric film and the first tip.

17. 17. The apparatus of claim 14, wherein the layer of superconducting material is a qubit readout resonator located on the second chip.

18. a first chip including a superconducting qubit disposed on a first dielectric substrate; a second chip bonded to the first chip, the second chip including a superconducting material layer disposed on a raised portion of a second dielectric substrate, and a dielectric film covering the superconducting material layer and at least a portion of the raised portion, the raised portion protruding from a surface of the second dielectric substrate; A device in which the superconducting material layer forms a microstrip transmission line and a pad element of a qubit readout resonator, the pad element being electrically coupled to the superconducting qubit.

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