Semiconductor Devices

Abstract

To provide a transistor with stable electric characteristics.SOLUTION: A semiconductor device includes a first insulator formed on a substrate, a second insulator formed on the first insulator, an oxide semiconductor formed in contact with at least a part of an upper surface of the second insulator, a third insulator formed in contact with at least a part of an upper surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator formed on the third insulator, a third conductor formed on the fourth insulator and having at least a part formed between the first conductor and the second conductor, and a fifth insulator formed on the third conductor. The first insulator contains a halogen element.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device. For example, the present invention relates to a method for manufacturing a transistor and a semiconductor device. The present invention relates to a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a processor, and an electronic device. The present invention also relates to a manufacturing method of a display device, a liquid crystal display device, a light emitting device, a storage device, and an electronic device. The present invention also relates to a display device, a liquid crystal display device, a light emitting device, a storage device, and a method for driving electronic equipment.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. One aspect of the invention is a process, machine, manufacture, or composition of matter. It concerns the matter of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, including display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices. The vessel may include a semiconductor device. [Background technology]

[0004] The technology of constructing transistors using semiconductors on substrates with insulating surfaces is attracting attention. The transistor is widely used in semiconductor devices such as integrated circuits and display devices. Silicon is known as a semiconductor that can be used in transistors.

[0005] The silicon used as a semiconductor in transistors is either amorphous silicon or polycrystalline silicon depending on the application. For example, it is suitable for transistors that make up large display devices. When using amorphous silicon, it is preferable to use amorphous silicon, for which film formation technology for large-area substrates has been established. On the other hand, it is also applied to transistors that constitute high-performance display devices that are integrally formed with driving circuits. In this case, polycrystalline silicon is used, which allows for the fabrication of transistors with high field-effect mobility. Polycrystalline silicon is preferably obtained by heat treatment at high temperature or laser treatment on amorphous silicon. A method of forming the layer by phototreatment is known.

[0006] In recent years, transistors using oxide semiconductors (typically In-Ga-Zn oxide) have become The history of oxide semiconductors is long, and in 1988, crystalline In-Ga It has been disclosed that Zn oxide is used in semiconductor devices (see Patent Document 1). In 1995, a transistor using an oxide semiconductor was invented, and its electrical properties is disclosed (see Patent Document 2).

[0007] The transistor using an oxide semiconductor includes a transistor using amorphous silicon, and It has different characteristics from transistors using polycrystalline silicon. A display device using a transistor using such an oxide is known to have low power consumption. Semiconductors can be deposited using methods such as sputtering, making it possible to form large-scale display devices using semiconductors. In addition, a transistor using an oxide semiconductor can be used as a high-voltage transistor. Because it has field effect mobility, it is possible to realize a high-performance display device in which a driving circuit is integrally formed. In addition, it is possible to improve and use some of the production equipment for amorphous silicon transistors. This also has the advantage of reducing capital investment. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent Publication No. 63-239117 [Patent Document 2] Special table 11-505377 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of the present invention is to provide a transistor having stable electrical characteristics. An object of the present invention is to provide a transistor with low leakage current when conducting. Another object of the present invention is to provide a transistor having excellent frequency characteristics. Another object of the present invention is to provide a transistor having turn-off electrical characteristics. An object of the present invention is to provide a transistor with a small threshold swing value. An object of the present invention is to provide a highly reliable transistor.

[0010] Another object is to provide a semiconductor device including the transistor. Another object of the present invention is to provide a module including the semiconductor device. It is an object of the present invention to provide an electronic device having the module. It is an object of the present invention to provide a novel semiconductor device. Another object of the present invention is to provide a novel electronic device.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention is a semiconductor device including a first insulator formed on a substrate and a semiconductor layer formed on the first insulator. a second insulator and an oxide semiconductor formed in contact with at least a portion of the top surface of the second insulator; a third insulator formed in contact with at least a portion of the top surface of the oxide semiconductor; A first conductor and a second conductor electrically connected to the semiconductor and formed on a third insulator. a fourth insulator formed on the fourth insulator and at least a portion of which is connected to the first conductor; a third conductor formed between the second conductors; and a second conductor formed on the third conductor. and a fifth insulator formed on the first insulator, the first insulator including a halogen element.

[0013] In addition, one aspect of the present invention is the above-mentioned invention, wherein a sixth insulator formed under the first insulator. The sixth insulator is less permeable to water and hydrogen than the first insulator. It is a location.

[0014] In addition, one aspect of the present invention is the above-mentioned invention, wherein a sixth insulator and a first insulator are formed between the sixth insulator and the first insulator. a fourth conductor at least partly overlapping with an oxide semiconductor; be.

[0015] In addition, one aspect of the present invention is a method for manufacturing a semiconductor device, comprising: In the gas release analysis, the amount of water molecules released was 1.0 × 10 13molecules / cm 2 Below Upper 1.4×10 16 molecules / cm 2 The semiconductor device is as follows.

[0016] In addition, one aspect of the present invention is the above-mentioned invention, wherein a fourth conductor and a first insulator are formed between the fourth conductor and the first insulator. The seventh insulator is a semiconductor device including hafnium.

[0017] In addition, one aspect of the present invention is a laminated film of the first insulator and the seventh insulator in the above invention. The water contained in the sample was measured by thermal desorption spectroscopy, and the number of desorbed water molecules was 1.0 × 10 13 mol ecules / cm 2 Over 1.4 x 10 16 molecules / cm 2 Semiconductors that are It is a body device.

[0018] In addition, one aspect of the present invention is a laminated film of the first insulator and the seventh insulator in the above invention. The hydrogen contained in the sample was measured by thermal desorption spectroscopy, and the desorption amount of hydrogen molecules was 1.0 × 10 13 m olecules / cm 2 Over 1.2 x 10 15 molecules / cm 2 is It is a semiconductor device.

[0019] In addition, one aspect of the present invention is the above-mentioned invention, wherein the halogen element is fluorine, chlorine, or This is a semiconductor device that is either bromine. [Effects of the Invention]

[0020] It is possible to provide a transistor having stable electrical characteristics. It is possible to provide a transistor with a small leakage current. Alternatively, a transistor having normally-off electrical characteristics can be provided. Alternatively, a transistor having a small subthreshold swing value can be provided. It is possible to provide a highly reliable transistor. This can be done.

[0021] Alternatively, a semiconductor device including the transistor can be provided. Alternatively, a module having the semiconductor device or the module can be provided. Alternatively, a novel semiconductor device can be provided. Or, a new module can be provided. Or, a new power supply can be provided. Child devices can be provided.

[0022] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above is self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0023] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 2] 1A and 1B are diagrams illustrating structural analysis of a CAAC-OS and a single-crystal oxide semiconductor by XRD, and a selected-area electron diffraction pattern of a CAAC-OS. [Figure 3] Cross-sectional TEM image of CAAC-OS, as well as planar TEM image and its image analysis. [Figure 4] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 5] Cross-sectional TEM image of a-like OS. [Figure 6] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 7] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 8] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 9] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 10] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 16] 1A and 1B are a schematic view and a cross-sectional view illustrating a film forming apparatus. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 20] FIG. 1 is a top view illustrating a manufacturing apparatus according to one embodiment of the present invention. [Figure 21] FIG. 1 is a top view illustrating a chamber according to one embodiment of the present invention. [Figure 22] FIG. 1 is a top view illustrating a chamber according to one embodiment of the present invention. [Figure 23]FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 24] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 25] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 26] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 27] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 28] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 29] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 30] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 31] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 32] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 33] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 34] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 35] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 36] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 37] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 38] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 39] 1A and 1B are a perspective view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 40] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 41] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 42] 1A to 1C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 43]1A and 1B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 44] FIG. 10 is a perspective view illustrating an electronic device according to one embodiment of the present invention. [Figure 45] Graph showing the results of TDS analysis measured in the examples. [Figure 46] Graph showing the results of TDS analysis measured in the examples. [Figure 47] Graph showing the results of TDS analysis measured in the examples. [Figure 48] Graph showing the results of ESR measurements performed in the examples. [Figure 49] 1 is a graph showing Id-Vg characteristics measured in an example. [Figure 50] 1 is a graph showing the shift variation measured in the example. [Figure 51] Graph showing the results of a stress test measured in an example. [Figure 52] 1 is a graph showing the results of film formation rates measured in Examples. [Figure 53] 1 is a graph showing the amount of released hydrogen calculated from the TDS analysis measured in the example. [Figure 54] 1 is a graph showing the amount of water released calculated from the TDS analysis measured in the examples. [Figure 55] Graph showing the results of TDS analysis measured in the examples. [Figure 56] Graph showing the results of TDS analysis measured in the examples. [Figure 57] Graph showing the results of TDS analysis measured in the examples. [Figure 58] Graph showing the results of TDS analysis measured in the examples. [Figure 59] Graph showing the results of SIMS measurement performed in an example. [Figure 60] Graph showing the results of SIMS measurement performed in an example. [Figure 61] Graph showing the results of XPS measurement performed in the examples. [Figure 62] FIG. 1 shows an ALD recipe used in the examples. [Figure 63]1 is a graph showing the results of TDS analysis measured in an example, and a graph showing the amount of water released calculated from the graph. [Figure 64] A diagram showing the results of TDS analysis. [Figure 65] A graph showing the cumulative amount of emissions calculated from the TDS analysis results. [Figure 66] A diagram showing the results of TDS analysis. [Figure 67] A diagram showing the results of TDS analysis. [Figure 68] A diagram showing the results of TDS analysis. [Figure 69] A diagram showing the results of TDS analysis. [Figure 70] A graph showing the cumulative amount of emissions calculated from the TDS analysis results. [Figure 71] A graph showing the cumulative amount of emissions calculated from the TDS analysis results. [Figure 72] A graph showing the cumulative amount of emissions calculated from the TDS analysis results. [Figure 73] A graph showing the cumulative amount of emissions calculated from the TDS analysis results. [Figure 74] 1A and 1B are diagrams illustrating a bonding state of silicon oxide. [Figure 75] 1A to 1C are diagrams illustrating heat treatment. [Figure 76] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 77] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 78] Graph showing the results of a stress test measured in an example. [Figure 79] Graph showing the results of TDS analysis measured in the examples. [Figure 80] Graph showing the results of TDS analysis measured in the examples. [Figure 81] Graph showing the results of SIMS analysis measured in the examples. [Figure 82] Graph showing the results of HX-PES analysis measured in the examples. [Figure 83] 1A and 1B are graphs showing Id-Vg characteristics, threshold voltages, and shifts measured in an example, and a model of a transistor used in the example. DETAILED DESCRIPTION OF THE INVENTION

[0024] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description, and various modifications in form and details can be easily made by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same symbols are used It is used in common among different drawings. When referring to the same thing, the hatch pattern is used in the same way. In some cases, no particular symbol is given.

[0025] The configurations shown in the following embodiments may be applied or combined as appropriate with other configurations shown in the embodiments. Combinations, substitutions, etc. can be made to form one embodiment of the present invention.

[0026] In the drawings, the size, thickness of the film (layer), or area is exaggerated for clarity. This may be the case.

[0027] In this specification, the terms "film" and "layer" are interchangeable. It is possible to do this.

[0028] Also, a voltage is a voltage between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be replaced with potential. Generally, potential (voltage) is relative, and the magnitude is relative to a reference potential. Therefore, even if it is described as "ground potential", The potential is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential." Or, the intermediate potential in the circuit may be the "ground potential." In this case, the positive potential and the negative potential are defined based on that potential.

[0029] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. It does not indicate the layer order. Therefore, for example, "first" should not be changed to "second" or "third." In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers The term and the ordinal number used to identify an aspect of the present invention may not match.

[0030] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be called an "insulator." In addition, the boundary between "semiconductors" and "insulators" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is not necessarily an "insulator" Similarly, the term "insulator" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0031] Also, even if a material is written as a "semiconductor," if the material has a sufficiently high conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is not necessarily a "conductor" Similarly, the term "conductor" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0032] The impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor. Elements present at concentrations of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the conductor and carrier movement The semiconductor may be an oxide semiconductor, and the crystallinity may decrease. In the case of a conductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1, Group elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., in particular, , hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, oxygen vacancies can be created by the inclusion of impurities such as hydrogen. In addition, when the semiconductor is silicon, there are cases where an impurity that changes the properties of the semiconductor is formed. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0033] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source The distance between the drain electrode and the drain region is called the distance between the In the transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one value, the maximum value, in the region where the channel is formed. , the minimum or average value.

[0034] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the gate electrode overlaps with the electrode (the area where current flows) forms a channel. The length of the region where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. In the detailed description, the channel width is any one value, the maximum value in the region where the channel is formed. , the minimum or average value.

[0035] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width shown in the figure becomes larger, and the effect becomes non-negligible. For example, in transistors with a fine, three-dimensional structure, the side surface of the semiconductor In this case, the ratio of the channel region formed in the top view may be increased. The effective channel width of the channel is actually formed rather than the apparent channel width shown. will be larger.

[0036] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width if the channel conditions are not precisely known. .

[0037] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length is the length of the part where the source and drain face each other in the overlapping region. The above channel width is called "Surrounded Channel Width (SCW)". In this specification, it is simply referred to as the channel width. In some cases, it may refer to the enclosed channel width or apparent channel width. In this specification, when simply referring to a channel width, it may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, and The width of the interstitial channel can be determined by acquiring a cross-sectional TEM image and analyzing the image. Thus, the value can be determined.

[0038] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0039] In this specification, when it is stated that A has a shape that protrudes more than B, it means that Or in the cross-sectional view, at least one end of A is outside at least one end of B. Therefore, it is written that A has a shape that protrudes more than B. For example, in the top view, one end of A is located outside one end of B. This can be read as having the following.

[0040] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to a state in which two lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0041] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0042] (Embodiment 1) In this embodiment, a structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. This will be explained using:

[0043] <Transistor configuration> The following describes the structure of a transistor as an example of a semiconductor device according to one embodiment of the present invention. explain.

[0044] The structure of the transistor 10 will be described with reference to FIGS. 1A to 1C. FIG. 1(A) is a top view of the transistor 10. FIG. 1(B) is a cross section of the dashed line A1-A2 in FIG. 1(C) is a cross-sectional view corresponding to the dashed line A3-A4 in FIG. 1(A). In the region indicated by the dashed line A1-A2, the channel length of the transistor 10 is The region indicated by the dashed line A3-A4 shows the structure of the transistor 10. The structure in the channel width direction is shown. The source (source region or source electrode) and the drain (drain region or drain electrode) ) and the channel width direction is the direction in which carriers move within the plane parallel to the substrate. In FIG. 1(A), the direction perpendicular to the channel length direction is indicated. The insulator 106a, the semiconductor 106b, and the insulator 106c are connected to the conductors 108a, 108b, etc. Although the insulators 106a can be provided so as to almost overlap each other, this is difficult to see in a top view. , semiconductor 106b, and insulator 106c are shown slightly shifted and indicated by thin dashed lines.

[0045] The transistor 10 includes an insulator 104 formed on a substrate 100 and a gate insulating film 106 formed on the insulator 104. and a conductive film formed in contact with at least a part of the upper surface of the insulator 106a. and an insulator formed in contact with at least a portion of the upper surface of the semiconductor 106b. 106c, and the conductors 108a and 108b electrically connected to the semiconductor 106b. , an insulator 112 formed on the insulator 106c, and a small Conductor 108 is formed so that at least a part of it is located between conductor 108a and conductor 108b. 14 and an insulator 116 formed on the conductor 114.

[0046] For example, as shown in FIGS. 1A to 1C, the transistor 10 is formed by The insulator 101, the conductor 102, the insulator 105, the insulator 103 and the insulator 1 104, an insulator 106a formed on the insulator 104, a semiconductor 106b, an insulator 106 conductor 108a, conductor 108b, and conductor 11c formed on semiconductor 106b. 10a and conductor 110b, an insulator 112 formed on insulator 106c, and an insulator 112 formed on insulator 106c. 12, a conductor 114 formed on the insulating layer 116, and an insulating layer 116 formed on the conductor 114. The semiconductor device includes an edge 118, a conductor 120a, and a conductor 120b.

[0047] Here, the insulator 101, the insulator 103, the insulator 104, the insulator 105, the insulator 106a , the insulator 106c, the insulator 112, the insulator 116, and the insulator 118 are insulating films or insulating layers. In addition, the conductor 102, the conductor 108a, the conductor 108b, and the conductor 1 10a, conductor 110b, conductor 114, conductor 120a and conductor 120b are conductive The semiconductor 106b can also be called a semiconductor film or a semiconductor layer. You can also do this.

[0048] As will be described in detail later, when the insulator 106a and the insulator 106c are used alone, In some cases, materials may be used that can function as conductors, semiconductors, or insulators. However, when a transistor is formed by stacking the semiconductor 106b, electrons 106b, the vicinity of the interface between the semiconductor 106b and the insulator 106a, and the vicinity of the interface between the semiconductor 106b and the insulator 106a. The insulators 106a and 106c flow near the interface of the transistor. Therefore, in this specification and the like, the insulator 1 The semiconductor 106a and the insulator 106c are not described as conductors and semiconductors, but as insulators. do.

[0049] A conductor 102 is formed on an insulator 101 formed on a substrate 100. At least a portion of 102 overlaps with an insulator 106a, a semiconductor 106b, and an insulator 106c. An insulator 105 is formed on the conductor 102 so as to be in contact with the conductor 102 and cover the conductor 102. The insulator 103 is formed on the insulator 105, and the insulator 10 is formed on the insulator 103. 4 is formed.

[0050] An insulator 106a is formed on the insulator 104, and at least one of the upper surfaces of the insulator 106a is In FIG. 1B, the insulator 106a and the semiconductor 106b are formed in contact with the insulator 106a. The insulator 106a and the semiconductor 106b are formed so that the ends of the conductor 106b are approximately aligned. However, the structure of the semiconductor device described in this embodiment mode is not limited to this.

[0051] The conductors 108a and 108b are in contact with at least a portion of the top surface of the semiconductor 106b. The conductor 108a and the conductor 108b are formed apart from each other, as shown in FIG. ) it is preferable that they are formed facing each other with the conductor 114 in between.

[0052] An insulator 106c is formed in contact with at least a portion of the top surface of the semiconductor 106b. 106c is a region sandwiched between the conductor 108a and the conductor 108b and the insulator 106b. In FIG. 1B, the insulator 106c is in contact with the conductor 108a and the conductor The upper surface of the body 108b is generally covered with the insulating film 108a. The configuration is not limited to this.

[0053] An insulator 112 is formed on the insulator 106c. The conductor 114 is formed so as to overlap between the conductor 108a and the conductor 108b. The insulator 112 and the insulator 106c are connected together so that the ends of the insulator 112 and the insulator 106c are approximately aligned. However, the structure of the semiconductor device shown in this embodiment is not limited to this. There is no.

[0054] An insulator 116 is formed on the conductor 114 and the insulator 112, and an insulating layer is formed on the insulator 116. An insulator 118 is formed. A conductor 120a and a conductor 120b are formed on the insulator 118. The conductor 120a and the conductor 120b are connected to the insulator 106c, the insulator 112, and the insulator 114. The conductor 108a and the conductor 108b are electrically connected to each other through openings formed in the edge 116 and the insulator 118. It is connected to 8b.

[0055] The conductor 114 is made up of the insulators 112, 106c, 104, and 103. Alternatively, the insulating layer 105 may be connected to the conductor 102 through an opening formed in the insulating layer 105 or the like. stomach.

[0056] <Semiconductors> The detailed configuration of the semiconductor 106b will be described below.

[0057] In this section, the semiconductor 106b, the insulator 106a, and the insulator 106c are The detailed configuration will also be explained.

[0058] The semiconductor 106b is, for example, an oxide semiconductor containing indium. For example, when indium is contained, the carrier mobility (electron mobility) increases. The body 106b preferably contains the element M. The element M is preferably Ti, Ga, Y, Zr , La, Ce, Nd, Sn or Hf, where the element M is the aforementioned element The element M may have a bond energy with oxygen of, for example, For example, the bond energy with oxygen is higher than that of indium. Alternatively, the element M may have a function of increasing the energy gap of the oxide semiconductor, for example. The semiconductor 106b preferably contains zinc. If lead is included, crystallization may occur more easily.

[0059] However, the semiconductor 106b is not limited to an oxide semiconductor containing indium. 06b does not contain indium, such as zinc tin oxide, gallium tin oxide, etc. Oxide semiconductors containing zinc, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. It's okay if there is.

[0060] For example, the insulators 106a and 106c are made of oxygen other than the oxygen that constitutes the semiconductor 106b. The semiconductor 106b is an oxide semiconductor composed of one or more of the elements. The insulator 106a and the insulator 10 are made of one or more elements other than oxygen. 6c is formed, the interface between the insulator 106a and the semiconductor 106b and the semiconductor 106 At the interface between the layer 106b and the insulator 106c, defect levels are unlikely to be formed.

[0061] The insulator 106a, the semiconductor 106b, and the insulator 106c contain at least indium. When the insulator 106a is an In-M-Zn oxide, the sum of In and M is preferably When the atomic percentage is 100, it is preferable that In is less than 50 atomic percent and M is less than 50. atomic %, more preferably In is less than 25 atomic % and M is 75 atomic % When the semiconductor 106b is an In-M-Zn oxide, I When the sum of n and M is 100 atomic %, In is preferably 25 atomic %. %, and M is less than 75 atomic %, and more preferably In is 34 atomic % The insulator 106c is In-M-Zn. In the case of oxides, when the sum of In and M is 100 atomic %, In is preferably 50 atomic %, M is higher than 50 atomic %, and more preferably In is 2 5 atomic % or less, and M is higher than 75 atomic %. However, the same oxide as the insulator 106a may be used. In some cases, the insulator 106c does not need to contain indium. 106a and / or the insulator 106c is gallium oxide or Ga-Zn oxide, It should be noted that the respective components included in the insulator 106a, the semiconductor 106b, and the insulator 106c may be The atomic numbers of elements do not have to be in a simple integer ratio.

[0062] For example, when the insulator 106a or the insulator 106 A typical example of the atomic ratio of the metal elements in the target used in c is In:M:Zn=1:2. :4, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1 :3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:3, In:M:Zn =1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4:6, In:M: Zn=1:6:3, In:M:Zn=1:6:4, In:M:Zn=1:6:5, In: M:Zn=1:6:6, In:M:Zn=1:6:7, In:M:Zn=1:6:8, I n:M:Zn=1:6:9, In:M:Zn=1:10:1, etc. The atomic ratio of the metal elements in the target used for 6a or insulator 106c is M:Zn=10: It can also be set to 1.

[0063] In addition, for example, when a film is formed by sputtering, the substrate used for the semiconductor 106b is Typical examples of atomic ratios of metal elements in the get are In:M:Zn=1:1:1, In:M :Zn=1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1: 2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn= 4:2:4.1, In:M:Zn=5:1:7, etc. In particular, sputtering targets When the atomic ratio of In:Ga:Zn=4:2:4.1 is used as the substrate, the semiconductor The atomic ratio of the body 106b may be approximately In:Ga:Zn=4:2:3.

[0064] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the insulator 106c preferably contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and More preferably, it is 90% or more.

[0065] The semiconductor 106b is made of, for example, an oxide with a large energy gap. The energy gap of 6b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2. The value is preferably 8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less. The energy gap of the insulator 106a is larger than the energy gap of the semiconductor 106b. The energy gap of the insulator 106c is larger than that of the semiconductor 106b. Bigger than a cup.

[0066] The semiconductor 106b is an oxide having a larger electron affinity than the insulator 106a or the insulator 106c. For example, the semiconductor 106b is made of a material having a higher conductivity than the insulators 106a and 106c. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less. 5 or less, more preferably, an oxide having a larger energy level than the above by 0.15 eV or more and 0.4 eV or less. , electron affinity is the energy difference between the vacuum level and the bottom of the conduction band. The energy level of the conduction band minimum of the semiconductor 106a or the insulator 106c is It is closer to the vacuum level than the energy level at the lower band edge.

[0067] At this time, when a gate voltage is applied, the insulator 106a, the semiconductor 106b, and the insulator 106 A channel is formed in the semiconductor 106b having a large electron affinity among the semiconductors 106a and 106b. When a voltage is applied to the insulator 106a, the insulator 106a is electrically connected to the semiconductor 106b. Current may also flow near the interface between 6c and semiconductor 106b.

[0068] As described above, when the insulators 106a and 106c are used alone, they are not conductive or semi-conductive. It consists of a material that can function as either a conductor or an insulator. When a transistor is formed by stacking the semiconductor 106b and the semiconductor 106, electrons are transferred through the semiconductor 106b and the semiconductor 106. The flow passes through the vicinity of the interface between the semiconductor 106b and the insulator 106a, and the vicinity of the interface between the semiconductor 106b and the insulator 106c. The insulators 106a and 106c do not function as the channel of the transistor. Therefore, in this specification and the like, the insulator 106a and the insulator 10 6c will not be described as a semiconductor but as an insulator. The insulator 106c is described as an insulator because it is a transistor compared to the semiconductor 106b. Since the function of the insulating material is similar to that of an insulator, the insulating material 106a or the insulating material 106c is In some cases, a material that can be used for the semiconductor 106b may be used.

[0069] Here, there is a gap between the insulator 106a and the semiconductor 106b. In addition, there may be a mixed region between the semiconductor 106b and the insulator 106c. , the semiconductor 106b and the insulator 106c may have a mixed region. Therefore, the level density of the insulator 106a, the semiconductor 106b, and the insulator 106c is In the laminated film, the energy changes continuously near each interface (also known as a continuous junction). The band diagram is as follows. The interface between the semiconductor 106c and the semiconductor 106b may not be clearly distinguishable.

[0070] At this time, the electrons are not in the insulator 106a and the insulator 106c but in the semiconductor 106b. As described above, the electrons move mainly through the interface between the insulator 106a and the semiconductor 106b. and the defect state density at the interface between the semiconductor 106b and the insulator 106c. By lowering the concentration, the movement of electrons in the semiconductor 106b is less hindered, The on-state current of the transistor can be increased.

[0071] In addition, the on-current of the transistor can be increased by reducing the factors that hinder the movement of electrons. For example, if there are no factors that hinder the movement of electrons, electrons can move efficiently. It is estimated that the electron movement is slower when, for example, the physical unevenness of the channel formation region is large. is also inhibited.

[0072] In order to increase the on-current of the transistor, for example, The square of the surface (the surface to be formed, here the upper surface of the insulator 106a) in the range of 1 μm×1 μm Root Mean Square (RMS) roughness less than 1 nm, preferably is less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in the area of ​​1 μm × 1 μm is 1n less than 0.6 nm, more preferably less than 0.5 nm, and The maximum height difference (PV) in the area of ​​1 μm x 1 μm should be less than 0.4 nm. ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, More preferably, it should be less than 7 nm. RMS roughness, Ra and PV are - Using a scanning probe microscope system SPA-500 manufactured by Nano Technology Co., Ltd. It can be measured.

[0073] In addition, in order to increase the on-state current of the transistor, the thickness of the insulator 106c is preferably as small as possible. The thickness of the insulator 106c is preferably smaller than the thickness of the insulator 106a. For example, the thickness is less than 10 nm, preferably 5 nm or less, More preferably, the insulator 106c has a region of 3 nm or less. 06c is a semiconductor 106b in which a channel is formed, and is formed by introducing oxygen other than oxygen constituting the adjacent insulator. It has the function of blocking elements (hydrogen, silicon, etc.) from entering. It is preferable that the insulator 106c has a certain thickness, for example, 0.3 nm or more. , preferably 1 nm or more, more preferably 2 nm or more insulator 10 Just use 6c.

[0074] In order to improve reliability, it is preferable that the insulator 106a is thick. 0 nm or more, preferably 20 nm or more, more preferably 40 nm or more, and more preferably The insulator 106a may have a region with a thickness of 60 nm or more. By increasing the thickness, a channel is formed from the interface between the adjacent insulator and the insulator 106a. However, this may result in a decrease in productivity of the semiconductor device. Therefore, for example, it is set to 200 nm or less, preferably 120 nm or less, and more preferably Insulator 106a may have a region with a thickness of 80 nm or less.

[0075] Silicon in an oxide semiconductor may act as a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor 106b, the more preferable. b and the insulator 106a, a secondary ion mass spectroscopy (SIMS) Ion Mass Spectrometry (IMS) 16 atoms / c m 3 More than 1×10 19 atoms / cm 3 Less than 1 × 10 16 atoms / c m 3 5x10 or more 18 atoms / cm 3 or less, more preferably 1 × 10 16 atom s / cm 3 Over 2×10 18 atoms / cm 3 The silicon concentration in the region is In addition, SIMS showed that the thickness of the semiconductor 106b and the insulator 106c was 1×10 16 a toms / cm 3 More than 1×10 19 atoms / cm 3 Less than 1 × 10 16 a toms / cm 3 5x10 or more 18 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 Over 2×10 18 atoms / cm 3 The silicon concentration is It has an area.

[0076] In order to reduce the hydrogen concentration in the semiconductor 106b, the insulator 106a and the insulator 106b are It is preferable to reduce the hydrogen concentration in the insulator 106a and the insulator 106c. In S, 1×10 16 atoms / cm 3 Over 2×10 20 atoms / cm 3 below , preferably 1 x 10 16 atoms / cm 3 5x10 or more 19 atoms / cm 3 below , more preferably 1 × 10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 5x10 or more 18 atoms / cm 3 The hydrogen concentration in the semiconductor 106b is reduced. Therefore, it is preferable to reduce the nitrogen concentration in the insulators 106a and 106c. The 106a and the insulator 106c have a SIMS resolution of 1×10 15 atoms / cm3 5x10 or more 19 atoms / cm 3 Less than 1 × 10 15 atoms / cm 3 5x10 or more 18 atoms / cm 3 Less than or equal to 1×10 15 atoms / c m 3 More than 1×10 18 atoms / cm 3 or less, more preferably 1 × 10 15 atom s / cm 3 5x10 or more 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0077] The insulator 106a, the semiconductor 106b, and the insulator 106c shown in this embodiment, particularly the semiconductor 106b is an oxide semiconductor having a low impurity concentration and a low density of defect states (few oxygen vacancies). and can be called a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. A highly intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, Therefore, a channel region can be formed in the oxide semiconductor. The transistors used in this study have electrical characteristics in which the threshold voltage is negative (also known as normally-on). In addition, oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic are The defect level density is low in the silicon dioxide, so the trap level density may also be low. Intrinsic or substantially highly purified intrinsic oxide semiconductors have a significantly small off-state current and a high channel density. The width W is 1×10 6 Even if the device has a channel length L of 10 μm, the source electrode and drain When the voltage between the drain electrodes (drain voltage) is in the range of 1V to 10V, the off-state current is below the measurement limit of the body parameter analyzer, i.e., 1 × 10 -13 A characteristic of A or less It is possible.

[0078] Therefore, the channel region is formed in the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The transistors in which this region is formed have small fluctuations in electrical characteristics and are highly reliable. Note that charges trapped in the trap states of the oxide semiconductor do not disappear until It takes a long time for the charge to dissipate, and it may behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor with a high density of drop states has Impurities include hydrogen, nitrogen, alkali metals, or alkalis. These include lithium-earth metals.

[0079] The hydrogen contained in the insulator 106a, the semiconductor 106b, and the insulator 106c bonds with metal atoms. The lattice from which oxygen is released (or the part from which oxygen is released) reacts with the oxygen to form water. When hydrogen enters the oxygen vacancy, electrons, which act as carriers, are generated. In addition, some of the hydrogen atoms may bond with oxygen atoms that bond with metal atoms, forming carriers. In particular, hydrogen trapped in oxygen vacancies can cause the band structure of semiconductors to change. Therefore, the oxide semiconductor containing hydrogen may have a shallow donor level. A transistor using a conductor tends to have a normally-on characteristic. a) It is preferable that the semiconductor 106b and the insulator 106c have as little hydrogen as possible. Specifically, in the insulator 106a, the semiconductor 106b, and the insulator 106c, SIM The hydrogen concentration obtained by S analysis is 2 × 10 20 atoms / cm 3 Below, preferably 5 x10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below Bottom, 5×10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Less than or equal to 5 × 10 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 The following applies.

[0080] In the insulator 106a, the semiconductor 106b, and the insulator 106c, one of the group 14 elements is When certain silicon or carbon is included, the insulator 106a, the semiconductor 106b, and the insulator 106c As a result, oxygen vacancies increase in the insulator 106a and the semiconductor 10 The concentrations of silicon and carbon in the insulator 106a, the semiconductor 106b, and the insulator 106c are The concentration of silicon and carbon near the interface between the insulating layer 106b and the insulating layer 106c (obtained by SIMS analysis) The concentration of 18 atoms / cm 3 Less than or equal to 2 x 10 17 atom s / cm 3 The following applies.

[0081] In addition, in the insulator 106a, the semiconductor 106b, and the insulator 106c, SIMS analysis The concentration of alkali metal or alkaline earth metal obtained by 18 atoms / cm 3 Less than or equal to 2 x 1016 atoms / cm 3 The following are alkali metals and When alkaline earth metals bond with oxide semiconductors, they can generate carriers. Therefore, the insulator 106a and the semiconductor 10 6b and the insulator 106c. preferable.

[0082] Furthermore, when nitrogen is contained in the insulator 106a, the semiconductor 106b, and the insulator 106c, Electrons, which act as carriers, are generated, increasing the carrier density and making it easier to become n-type. A transistor using an oxide semiconductor film containing such a metal oxide tends to be normally on. Therefore, it is preferable that nitrogen be reduced as much as possible in the oxide semiconductor film. For example, the nitrogen concentration obtained by SIMS analysis is 5×10 18 atoms / cm 3 below It is preferable to do so.

[0083] FIG. 1D shows an enlarged cross-sectional view of the insulator 106a and the semiconductor 106b near their centers. As shown in FIGS. 1B and 1D, a conductive material such as a semiconductor 106b or an insulator 106c is used. The area in contact with the conductive body 108a or the conductive body 108b (shown by dotted lines in FIGS. 1B and 1D) ) may form low resistance regions 109a and 109b. The low-resistance region 109a and the low-resistance region 109b are mainly formed by the conductor 108a or the conductor 108b in contact with the semiconductor 106b. The oxygen is extracted by the conductor 108a or the conductor 108b. The conductive material is formed by bonding with the elements in the semiconductor 106b. The formation of the high resistance region 109a and the low resistance region 109b allows the conductor 108a or the conductor Since the contact resistance between the conductive body 108b and the semiconductor 106b can be reduced, the transistor The on-current of the capacitor 10 can be increased.

[0084] Although not shown, the insulator 106a and the conductor 108a or the conductor 108b A low resistance region may also be formed in the contact region. Similar dotted lines indicate low resistance regions.

[0085] As shown in FIG. 1D, the semiconductor 106b is formed by a conductor 108a and a conductor 108b. There is a region between the conductive layers 108a and 108b that is thinner than the region where the conductive layers 108a and 108b overlap. This is because when the conductor 108a and the conductor 108b are formed, the semiconductor 106b The upper surface of the semiconductor 106b is formed by removing a part of the upper surface of the conductor 10. When the conductors that will become the conductors 8a and 108b are formed, the low resistance regions 109a and 109b In this way, a low resistance region similar to that of the upper surface of the semiconductor 106b may be formed. By removing the region located between the conductor 108a and the conductor 108b, the semiconductor 10 This can prevent a channel from being formed in the low resistance region on the top surface of 6b. In subsequent drawings, even if an area with a thin film thickness is not shown in an enlarged view, it is assumed that the area with a thin film thickness is the same. Areas may be formed.

[0086] The above-described three-layer structure of the insulator 106a, the semiconductor 106b, and the insulator 106c is an example. For example, a two-layer structure in which either the insulator 106a or the insulator 106c is not provided may be used. Alternatively, a single-layer structure without the insulator 106a or the insulator 106c may be used. Alternatively, one layer may be formed in addition to the insulator 106a, the semiconductor 106b, and the insulator 106c. It is also acceptable to have an n-layer structure (n is an integer of 4 or more) having the above. , can be used for either the insulator 106a, the semiconductor 106b or the insulator 106c. It is sufficient to use materials that can be used.

[0087] <Oxide semiconductor structure> The structure of an oxide semiconductor will be described below.

[0088] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- like oxide semiconductor) and amorphous oxide semiconductor be.

[0089] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductor, and nc-OS.

[0090] Amorphous structures are generally isotropic and have no heterogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The position is not fixed, the bond angle is flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0091] Looking at it from the other way around, a stable oxide semiconductor can be considered completely amorphous. In addition, it is not isotropic (for example, in a small area) and cannot be called an oxide semiconductor. An oxide semiconductor having a periodic structure cannot be called a completely amorphous oxide semiconductor. On the other hand, a-like OS is not isotropic but has unstable voids. In terms of instability, a-like OS is physically amorphous oxide. It is similar to a semiconductor.

[0092] <caac-os> First, let me explain about CAAC-OS.

[0093] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0094] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystal structure was analyzed by the out-of-plane method. As shown in Figure 2(A), a peak appears at a diffraction angle (2θ) of approximately 31°. The crystal structure is attributed to the (009) plane of the InGaZnO4 crystal. The crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be seen that the crystal is oriented in a direction perpendicular to the surface, or in a direction approximately perpendicular to the surface. In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the nucleus are due to the crystal structure classified into the space group Fd-3m. It is preferable that -OS does not exhibit such a peak.

[0095] On the other hand, in-pl, X-rays are incident on the CAAC-OS from a direction parallel to the surface to be formed. When structural analysis is performed using the ane method, a peak appears at 2θ around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. And, 2θ is fixed at around 56°. The sample is then rotated around the normal vector of the sample surface as the axis (φ axis) for analysis (φ scan). Even if this is done, no clear peak appears, as shown in Figure 2(B). When φ was scanned with 2θ fixed at around 56° for nO4, the results were as shown in Figure 2(C). Six peaks attributable to the crystal plane equivalent to the (110) plane are observed. From the structural analysis using D, it was found that the orientation of the a-axis and b-axis of CAAC-OS is irregular. can be confirmed.

[0096] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the process was performed parallel to the surface on which the CAAC-OS was formed. When an electron beam with a probe diameter of 300 nm is incident, a diffraction pattern (control pattern) like that shown in Figure 2(D) is generated. This diffraction pattern may contain In. This includes spots due to the (009) plane of the GaZnO4 crystal. Even in such cases, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed. On the other hand, for the same sample, the direction of the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm was incident perpendicularly is shown in Figure 2(E). A ring-shaped diffraction pattern is observed in Figure 2(E). The pellets contained in CAAC-OS were also identified by electron diffraction using a 300 nm electron beam. It can be seen that the a-axis and b-axis of the first phosphorus in FIG. The glitches are thought to be due to the (010) and (100) planes of the InGaZnO4 crystal. The second ring in Figure 2(E) is thought to be due to the (110) plane. do.

[0097] In addition, transmission electron microscope (TEM) Combined analysis of bright-field images and diffraction patterns of CAAC-OS using a microscope When observing the image (also called a high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain boundaries), are not clearly visible. It may not be possible to clearly identify the boundary. It can be said that C-OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0098] Figure 3(A) shows a high-resolution T image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image shown here is a spherical aberration correction (SAC) image. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. It can be observed that

[0099] From Figure 3(A), we can see the pellet, which is the region where metal atoms are arranged in layers. It has been found that the size of a single pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). Also, CAAC-OS can be used with CANC (C-Axis Aligned Nano The pellets can also be called oxide semiconductors with CAAC -OS surface or upper surface unevenness is reflected, and CAAC-OS surface or upper surface unevenness is reflected. is parallel to the surface.

[0100] In addition, Figures 3(B) and 3(C) show the CAAC- Figure 3(D) and Figure 3(E) show Cs-corrected high-resolution TEM images of the OS surface, respectively. These are images obtained by processing Figures 3(B) and 3(C). The image processing method is explained below. First, let us consider the case where Figure 3(B) is subjected to a Fast Fourier Transform (FFT). Then, the FFT image is obtained by performing the r Transform process. 2.8nm based on the origin -1 to 5.0 nm -1 Masking to leave the range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT). e Fast Fourier Transform (FT) processing is used to process the image. The image acquired in this way is called an FFT filtered image. FFT filtering The image is an image in which the periodic component is extracted from a Cs-corrected high-resolution TEM image, and shows the lattice arrangement. There are.

[0101] In Figure 3(D), the area where the lattice arrangement is disrupted is indicated by a dashed line. The area surrounded by the dashed line is The area indicated by the broken line is the connection between the pellets. The broken line indicates a hexagonal shape, which indicates that the pellets are hexagonal. The shape of the dot is not limited to a regular hexagon, and is often a non-regular hexagon.

[0102] In Figure 3(E), a dotted line separates a region with a uniform lattice arrangement from a region with a different uniform lattice arrangement. The lattice orientation is indicated by a dotted line, and the direction of the lattice arrangement is indicated by a dashed line. If you connect the grid points around the dotted line, you will get a distorted hexagon. In other words, by distorting the lattice arrangement, This is because the CAAC-OS has ab plane. The atomic arrangement is not dense in the direction, and the bond distance between atoms is reduced by the substitution of metal elements. This is thought to be because distortion can be tolerated by changing the

[0103] As described above, the CAAC-OS has a c-axis orientation and is Multiple pellets (nanocrystals) are connected to form a distorted crystal structure. AAC-OS, CAA crystal(c-axis-aligned abp It can also be called an oxide semiconductor with lane-anchored crystals. Cut.

[0104] CAAC-OS is an oxide semiconductor with high crystallinity. Conversely, CAAC-O may be affected by contamination or defect formation. S can be considered an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0105] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more oxidative than metal elements that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0106] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 traps hydrogen and becomes a carrier generation source.

[0107] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. There is. Specifically, 8×10 11 pieces / cm 3 Less than 1 x 10 11 / cm 3 less than , and more preferably 1 × 10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 The above Such an oxide semiconductor can be obtained by using a high-purity pure oxide semiconductor. CAAC-OS is a highly pure or substantially highly pure intrinsic oxide semiconductor. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0108] <nc-os> Next, we will explain nc-OS.

[0109] We will explain the analysis of nc-OS by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0110] For example, an nc-OS having InGaZnO4 crystals was thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region m, the A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. In addition, the diffraction pattern (nano) when an electron beam with a probe diameter of 1 nm is incident on the same sample. The electron diffraction pattern (BEM) is shown in Figure 4(B). Multiple spots are observed. Therefore, the nc-OS is an electron probe with a diameter of 50 nm. However, when an electron beam with a probe diameter of 1 nm is irradiated, the order is not confirmed. By doing so, order can be confirmed.

[0111] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in Figure 4(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. Therefore, in the range of thickness less than 10 nm, the nc-OS is ordered. It can be seen that the crystals are oriented in various directions. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0112] Figure 4(D) shows the Cs-corrected high-resolution image of the cross section of nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. There are two areas where crystals can be seen, as shown in Fig. 1, and areas where no clear crystals can be seen. The crystal part contained in the nc-OS has a size of 1 nm to 10 nm. In particular, the size is often between 1 nm and 3 nm. An oxide semiconductor having a size of more than 0 nm and not more than 100 nm is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). It is sometimes called a crystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries may not be clearly visible in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, the crystalline part of the nc-OS may be referred to as a pellet below.

[0113] In this way, nc-OS can be used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. In the case of the SiO2 film, there is no regularity in the crystal orientation between different pellets. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. In some cases, it may be difficult to distinguish them from solid oxide semiconductors.

[0114] In addition, since there is no regularity in the crystal orientation between the pellets (nanocrystals), nc-OS , oxidation with RANC (Random Aligned nanocrystals) semiconductors or NANC (Non-Aligned nanocrystals) The oxide semiconductor may also be called an oxide semiconductor.

[0115] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0116] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a semiconductor.

[0117] Figure 5 shows high-resolution cross-sectional TEM images of the a-like OS. Figure 5(B) shows a high-resolution cross-sectional TEM image of the a-like OS at the start of irradiation. 4.3×10 8 e - / nm 2 electrons (e - ) High decomposition of a-like OS after irradiation Figures 5(A) and 5(B) show that the a-like OS is From the start of the irradiation, striped bright areas extending in the vertical direction are observed. It can be seen that the shape of the sample changes after electron irradiation. The bright areas are voids or low-density areas. It is speculated.

[0118] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0119] As samples, a-like OS, nc-OS, and CAAC-OS were prepared. Both samples are In-Ga-Zn oxides.

[0120] First, high-resolution cross-sectional TEM images of each sample are acquired. All of the materials have crystalline parts.

[0121] The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn It is known that the structure has a total of nine layers, six of which are -O layers, stacked in layers along the c-axis. The distance between these adjacent layers is determined by the lattice spacing (also called the d value) of the (009) plane. The value is about the same, and is calculated to be 0.29 nm from crystal structure analysis. In the following, the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less is referred to as InGaZ. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0122] Figure 6 shows an example of the average size of the crystal parts (22 to 30 locations) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. The crystal part of the OS grows in size according to the cumulative amount of electron irradiation used to obtain a TEM image. As can be seen from Figure 6, the size was about 1.2 nm at the beginning of the TEM observation. The crystal part (also called the initial nucleus) - ) cumulative exposure is 4.2 × 10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron irradiation dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals in the range of Regardless of the cumulative irradiation dose of the atoms, the size of the crystalline parts of nc-OS and CAAC-OS was The results show that the electron beam irradiation and T The EM observation was performed using a Hitachi transmission electron microscope H-9000NAR. The electron beam irradiation conditions were The voltage was 300 kV and the current density was 6.7 × 10 5 e - / (nm 2 s), the diameter of the irradiated area was set to 230 nm.

[0123] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in nc-OS and CAAC-OS, the growth of the crystals by electron irradiation is almost nonexistent. In other words, a-like OS is not seen in comparison with nc-OS and CAAC-OS. , it is clear that this is an unstable structure.

[0124] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal of the same composition. The density of the nc-OS is 78.6% or more and less than 92.3% of that of the normal crystal. The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0125] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It will be less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0126] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By combining these, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density corresponding to a single crystal of a desired composition is calculated based on the ratio of the single crystals of different compositions combined. However, the density can be estimated by using as few types of single crystals as possible. It is preferable to estimate them together.

[0127] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the above-mentioned compounds.

[0128] <Substrate, insulator, conductor> Each of the non-semiconductor components of transistor 10 will be described in detail below.

[0129] The substrate 100 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of the substrate include a glass substrate, a quartz substrate, a sapphire substrate, and a stabilized zirconia substrate. Substrates (such as yttria-stabilized zirconia substrates), resin substrates, etc. Also, semiconductor substrates Examples of the substrate include a single semiconductor substrate such as silicon or germanium, or silicon carbide. , silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. Furthermore, there are semiconductor substrates having an insulating region inside the semiconductor substrate. Examples of suitable substrates include silicon-on-insulator (SOI) substrates. Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. The substrates include substrates having metal nitrides and substrates having metal oxides. a substrate in which a conductor or a semiconductor is provided on a solid substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or an insulator is provided on a conductive substrate. The substrate may have elements mounted thereon. These include capacitors, resistors, switch elements, light-emitting elements, and memory elements.

[0130] In addition, a flexible substrate that can withstand the heat treatment during transistor fabrication is used as the substrate 100. As a method for providing a transistor on a flexible substrate, a non-flexible After forming the transistor on the substrate, the transistor is peeled off and the substrate 1, which is a flexible substrate, is removed. There is also a method to transpose it to 00. In that case, there is a peeling between the non-flexible substrate and the transistor. The substrate 100 may be a sheet, film or A foil or the like may be used. The substrate 100 may also have flexibility. The material may have the property of returning to its original shape when the bending or pulling is stopped. The thickness of the substrate 100 may be, for example, 5 μm to 700 μm. m or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less The thickness of the substrate 100 is set to 1 μm or less. By making the substrate 100 thinner, the weight of the semiconductor device can be reduced. By making the substrate 100 thin, it is possible to make it flexible and foldable even when glass or the like is used. When the bending or pulling is stopped, the material may return to its original shape. The impact applied to the semiconductor device on the substrate 100 can be reduced by the support or the like. In other words, a robust semiconductor device can be provided.

[0131] The substrate 100, which is a flexible substrate, may be made of, for example, metal, alloy, resin, or glass. Alternatively, fibers thereof can be used. The substrate 100, which is a flexible substrate, has a linear expansion coefficient of 100. The lower the expansion ratio, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1× 10 -5 The resin may be, for example, polyester, Polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate Aramid, in particular, has a low linear expansion coefficient, making it suitable for flexible substrates. It is suitable as the plate 100.

[0132] The insulator 101 is an insulator that has the function of blocking hydrogen or water. The hydrogen and water in the insulator provided near the semiconductor 106a, the semiconductor 106b, and the insulator 106c are converted into oxides. Carriers are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c, which also function as semiconductors. This may result in a decrease in the reliability of the transistor 10. In particular, a substrate on which a silicon-based semiconductor element such as a switch element is provided is used as the substrate 100. When the semiconductor device is in a semiconductor device, hydrogen is used to terminate the dangling bonds of the semiconductor device. There is a risk that hydrogen may diffuse to the transistor 10. To prevent this, hydrogen or water is blocked. By providing the insulator 101 having the function of This can prevent water from diffusing, thereby improving the reliability of the transistor 10. It is preferable that the insulator 101 is less permeable to hydrogen or water than the insulator 105 or the insulator 104. It's nice.

[0133] In addition, the insulator 101 preferably has a function of blocking oxygen. By blocking oxygen diffusing from the insulator 104, Oxygen can be effectively supplied to the semiconductor 106a, the insulator 106b, and the semiconductor 106c.

[0134] The insulator 101 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium oxynitride or the like can be used. This allows the film to function as an insulating film that blocks the diffusion of oxygen, hydrogen, or water. The insulator 101 may be made of, for example, silicon nitride or silicon nitride oxide. By using these as the insulator 101, the diffusion of hydrogen and water can be blocked. It should be noted that in this specification and the like, the term "nitride" refers to a material that functions as an insulating film that exhibits a blocking effect. Silicon oxide is a material that contains more nitrogen than oxygen. Silicon nitride refers to a material whose composition contains more oxygen than nitrogen.

[0135] The conductor 102 has at least a region sandwiched between the conductors 108a and 108b. Preferably, the conductor 102 overlaps with the semiconductor 106b. By providing such a conductor 102, the transistor The threshold voltage of the transistor 10 can be controlled. Therefore, when the voltage applied to the gate (conductor 114) of transistor 10 is low, e.g. When the applied voltage is 0 V or less, the transistor 10 can be prevented from being turned on. In other words, the electrical characteristics of the transistor 10 are shifted more toward normally-off. This makes it easier.

[0136] The conductor 102 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, Thorium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and Conductors containing one or more of tungsten and cerium may be used in a single layer or a multilayer. , alloys or compounds, and conductors containing aluminum, conductors containing copper and titanium Conductors containing copper and manganese, conductors containing indium, tin and oxygen, titanium and conductors containing nitrogen may also be used.

[0137] The insulator 105 is provided so as to cover the conductor 102. The insulator 105 is an insulating material as will be described later. An insulator similar to body 104 or insulator 112 can be used.

[0138] The insulator 103 is provided to cover the insulator 105. The insulator 103 blocks oxygen. By providing such an insulator 103, This prevents the conductor 102 from extracting oxygen from the insulator 104. 104 to effectively supply oxygen to the insulator 106a, the semiconductor 106b, and the insulator 106c. In addition, by increasing the coverage of the insulator 103, the insulator 104 can be more effectively covered. The oxygen extracted from the insulator 104 is further reduced, and the insulator 106a, the semiconductor 106b, and the Oxygen can be supplied to the insulator 106c more effectively.

[0139] The insulator 103 may be boron, aluminum, silicon, scandium, titanium, or gallium. Sodium, yttrium, zirconium, indium, lanthanum, cerium, neodymium, halide An oxide or nitride containing hafnium or thallium is used. Preferably, hafnium oxide is used. Aluminum or aluminum oxide is used.

[0140] In the insulators 105, 103, and 104, the insulator 103 traps electrons. It is preferable that the insulator 105 and the insulator 104 have a function of suppressing the emission of electrons. When the insulator 103 has the function of trapping electrons, the electrons trapped in the insulator 103 behave like fixed negative charges. Therefore, by injecting electrons into the insulator 103, the threshold voltage of the transistor 10 can be increased. The injection of electrons into the insulator 103 causes the conductor 102 to become positive or negative. This can be achieved by applying a negative potential.

[0141] In addition, the time for which the potential is applied to the conductor 102 and / or the potential to be applied can be varied. The amount of implanted electrons can be adjusted to set the threshold voltage of the transistor to the desired value. The potential applied to the conductor 102 is such that a tunnel current flows in the insulator 105. For example, the voltage may be 20V or more and 60V or less, preferably 24V or more and 50V or less. The potential may be applied to the substrate at a voltage of 30 V or more and more preferably 30 V or more and 45 V or less. For example, the range is 0.1 seconds or more and 20 seconds or less, preferably 0.2 seconds or more and 10 seconds or less. That's fine.

[0142] It is also preferable that the insulator 103 contains less hydrogen or water. The body 103 is measured by thermal desorption spectroscopy (TDS) analysis at a temperature of 100°C or higher and 700°C or lower. In the surface temperature range of 100°C to 500°C, the number of water molecules desorbed is 1.0 × 10 13 molecules / cm 2 Over 1.0 x 10 16 molecules / cm 2 Below, Furthermore, 1.0 × 10 13 molecules / cm 2 Over 3.0 x 10 15 molecul es / cm 2 The following is preferred: A method for measuring the amount of released molecules using TDS analysis Details will be provided later.

[0143] The insulator 104 preferably contains a small amount of water or hydrogen. The insulator 104 is preferably an insulator having excess oxygen. Examples of suitable elements include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, and silicon. Cr, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, Insulators containing lanthanum, neodymium, hafnium or tantalum, either in single or multilayer configurations For example, the insulator 104 may be aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, Hafnium oxide or tantalum oxide may be used. Preferably, silicon oxide or oxide Silicon nitride is used.

[0144] The amount of water or hydrogen contained in the insulator 104 is preferably small. The body 104 has a temperature of 100°C or higher and 700°C or lower or 100°C or higher and 500°C or lower by TDS analysis. In the range of surface temperatures below, the number of water molecules desorbed is 1.0 × 10 13 molecules / cm 2 Over 1.4 x 10 16 molecules / cm 2 Below, 1.0 x 10 13 mol ecules / cm 2 Over 4.0 x 10 15 molecules / cm 2 Below, one more .0×10 13 molecules / cm 2 Over 2.0 x 10 15 molecules / cm 2 Furthermore, it is preferable that the temperature is between 100°C and 700°C by TDS analysis. or in the surface temperature range of 100°C to 500°C, the amount of hydrogen molecules desorbed is 1.0 × 10 1 3 molecules / cm 2 Over 1.2 x 10 15 molecules / cm 2 below, Furthermore, 1.0×10 13 molecules / cm 2 Over 9.0 x 10 14 molecu les / cm 2 It is preferable that the following conditions are met: The determination method will be described in detail later.

[0145] As described above, impurities such as water and hydrogen are introduced into the insulator 106a, the semiconductor 106b, and the insulator 106c. 06c, especially in the semiconductor 106b, a defect level is formed, which changes the electrical characteristics of the transistor. Therefore, the insulator 106a, the semiconductor 106b, and the insulator 106c By reducing the amount of water or hydrogen in the insulator 104 provided below, the insulator 1 Water, hydrogen, etc. are supplied from 04 to the semiconductor 106b, etc., and defect levels are formed. By using an oxide semiconductor with a reduced density of defect states, It is possible to provide a transistor having stable electrical characteristics.

[0146] As will be described in detail later, the insulator 104, the insulator 106a, the semiconductor 106b, and the insulator 106 In the case of c, heat treatment is carried out to dehydrate, dehydrogenate, or reduce oxygen deficiency. However, by performing a high-temperature heat treatment, the insulating layer 104 is In particular, when the transistor 10 shown in this embodiment is used in a semiconductor 106 b) is stacked on a semiconductor element layer having a semiconductor (e.g., silicon) different from that of b) as an active layer. In the case of forming the semiconductor element layer, the heat treatment may be performed to remove various elements, wirings, and the like included in the semiconductor element layer. may be damaged or deteriorated.

[0147] For example, when forming a semiconductor element layer on a silicon substrate, in order to miniaturize the elements, There is a demand for lower resistance in elements. For example, Cu wiring, which has low resistivity, is formed as the wiring material. To form the source and drain regions of the transistor, nickel silicon is deposited in the regions. However, both Cu wiring and nickel silicide are heat-resistant. For example, high-temperature heat treatment of Cu wiring can cause voids and hillocks. Deterioration occurs due to the formation of nickel silicide or Cu diffusion. High-temperature heat treatment expands the silicide region and forms the source and drain regions of the transistor. Deterioration such as short circuiting occurs.

[0148] For this reason, the above heat treatment must be carried out within a temperature range that does not deteriorate the underlying semiconductor element layer. However, if the insulator 104 contains a large amount of water and hydrogen during film formation, Even if heat treatment is performed within a temperature range that does not deteriorate the semiconductor element layer, water and Furthermore, the insulator 106a, the semiconductor 106b, and the When heat treatment is performed in the same temperature range after the formation of the insulator 104 and the insulator 106c, water, Hydrogen and the like are supplied to the semiconductor 106b and the like, and defect levels are formed.

[0149] In contrast, the insulator 104 described in this embodiment has a low content of water and hydrogen as described above. Because the temperature is reduced, it can be used at relatively low temperatures (for example, in the temperature range of 350°C to 445°C). The heating can sufficiently remove water, hydrogen, etc. Even if heat treatment is performed in the same temperature range after the formation of the insulator 106b and the insulator 106c, Since the water and hydrogen contained in 04 are sufficiently reduced, the defect level of semiconductor 106b is The formation of the bond can be suppressed.

[0150] The insulator 104 is formed by the PECVD method, which can produce a high-quality film at a relatively low temperature. However, for example, a silicon oxide film is preferably formed by the PECVD method. In this case, silicon hydride is often used as the source gas, and the insulating material is Therefore, hydrogen, water, etc. are introduced into the insulator 104 shown in this embodiment. The film formation of 4 is preferably carried out using silicon halide as a source gas. Examples of silicon halides include SiF4 (silicon tetrafluoride) and SiCl4 (chloride tetrachloride). silicon), SiHCl3 (silicon trichloride), SiH2Cl2 (dichlorosilane) or Si Br4 (silicon tetrabromide) and the like can be used.

[0151] By using silicon halide as a source gas for forming the insulator 104, In some cases, halogen is contained in the insulator 104. In addition, the components of the insulator 104 and the halogen are covalent. For example, the insulator 104 is formed using SiF4 as a raw material gas. In this case, fluorine may be contained in the insulator 104, and a covalent bond of Si—F may be formed. Here, the insulator 104 having a covalent bond of SiF is identified by X-ray photoelectron spectroscopy (XPS). 68% of the total energy was used for evaluation using ray photoelectron spectroscopy (PDPS). The spectrum may have a peak in the range of 5.4 eV to 687.5 eV.

[0152] In addition, when silicon halide is used as a source gas for forming the insulator 104, the halogen In addition to silicon hydride, silicon hydride may be added. The hydrogen and water contents in the insulator 104 are reduced compared to when the raw material gas is made of chlorine. The film formation rate can be improved compared to when only silicon dioxide is used as the source gas. The insulator 104 may be formed using iF4 and SiH4 as raw material gases. The flow rate of SiH4 is determined appropriately in consideration of the content of water and hydrogen in the insulator 104 and the film formation rate. The details of a method for forming the insulator 104 will be described later.

[0153] In addition to the insulator 104, the insulator 101 and the insulator 106a are In this embodiment, the laminated film of the insulator 105, the insulator 103, and the insulator 104 It is preferable that the amount of water or hydrogen contained in the laminated film is small. If 101 is an insulator that has the function of blocking water and hydrogen, then the insulator 106a, the semiconductor When forming the oxide film 106b, water and hydrogen are supplied to the oxide film 106b. 05, insulator 103 and insulator 104. Therefore, insulator 106a When forming an oxide film to be the semiconductor 106b, the insulators 105, 103, and If the amount of water or hydrogen contained in the laminated film of the insulator 104 is sufficiently small, the insulator 106a, the semiconductor This can reduce the supply of water or hydrogen to the conductor 106b.

[0154] For example, the stacked film of the insulators 105, 103, and 104 was found to have the following properties by TDS analysis: In the surface temperature range of 100°C to 700°C or 100°C to 500°C, water molecules The amount of desorption is 1.0×10 13 molecules / cm 2 Over 1.4 x 10 16 mole cules / cm 2 Below, 1.0 x 10 13 molecules / cm 2 4. 0×10 15 molecules / cm 2 Below, 1.0 x 10 13 molecul es / cm 2 Over 2.0 x 10 15 molecules / cm 2 It is preferable that In addition, TDS analysis shows that the temperature is between 100°C and 700°C or between 100°C and 500°C. In the surface temperature range, the amount of hydrogen molecules desorbed is 1.0×10 13 molecules / cm 2 Over 1.2 x 10 15 molecules / cm 2 Below, 1.0 x 10 13 mol ecules / cm 2 Over 9.0 x 10 14 molecules / cm 2 The following will be true: It is preferable to use TDS analysis for measuring the amount of released molecules. do.

[0155] In addition, such an insulator with reduced water and hydrogen can be used not only for the insulator 104 but also for other insulators. For example, it may be used for the insulator 105, or for the insulator 112, It may be used for the insulator 118. If it has a blocking property against hydrogen or water, it may be used for the insulator 118. The insulating layer 101 may be used for the insulating layer 102, the insulating layer 116, etc. When a layer or wiring layer is provided, it is used as an interlayer insulating film for the semiconductor element layer or wiring layer. In addition, when a semiconductor element layer, a wiring layer, or the like is provided over the insulator 118, the semiconductor element layer, the wiring layer, or the like may be formed over the insulator 118. It may also be used as an interlayer insulating film between conductive element layers or wiring layers.

[0156] Also, the insulator 104 is preferably an insulator having excess oxygen. By providing the insulator 104, the insulator 106a, the semiconductor 106b, and the insulating Oxygen can be supplied to the oxide semiconductor insulator 106c. The oxygen vacancies that cause defects in the semiconductor 106a, the semiconductor 106b, and the insulator 106c can be reduced. This allows the insulator 106a, the semiconductor 106b, and the insulator 106c to have a low defect level density. Therefore, an oxide semiconductor having stable characteristics can be obtained.

[0157] In this specification and the like, excess oxygen refers to oxygen contained in excess of the stoichiometric composition. Alternatively, the excess oxygen refers to oxygen that is released by heating, for example. This refers to oxygen released from a film or layer. Excess oxygen may be released, for example, by moving inside the film or layer. The movement of excess oxygen can occur between atoms in the film or layer, or between oxygen atoms that make up the film or layer. In some cases, the two move in a domino effect, replacing each other.

[0158] The insulator 104 having excess oxygen has a temperature of 100° C. or higher and 700° C. or lower as determined by TDS analysis. In the surface temperature range of 100°C to 500°C, the amount of desorption of oxygen molecules is 1.0 × 10 14 m olecules / cm 2 Over 1.0 x 10 16 molecules / cm 2 More information below: Preferably, 1.0 x 10 15 molecules / cm 2 Over 5.0 x 10 15 mol ecules / cm 2 The following is the result.

[0159] Regarding the method for measuring the amount of released molecules using TDS analysis, the amount of released oxygen is as follows: will be explained.

[0160] The total amount of gas released when the measurement sample is subjected to TDS analysis is calculated by the integral value of the ion intensity of the released gas. By comparison with a standard sample, the total amount of gas released can be calculated.

[0161] For example, the TDS analysis results of a silicon substrate containing a specified density of hydrogen as a standard sample, and From the TDS analysis results of the measurement sample, the amount of oxygen molecules released from the measurement sample (N O2 ) is shown below Here, the gas detected at a mass-to-charge ratio of 32 obtained by TDS analysis can be calculated using the formula: We assume that all of the carbon atoms are derived from oxygen molecules. The mass-to-charge ratio of CH3OH is 32, but It is not considered here as it is unlikely. Also, the mass number of the isotope of the oxygen atom is 17. The existence of oxygen atoms with mass number 18 and oxygen molecules with mass number 18 in nature is also Not considered as the ratio is extremely small.

[0162] N O2 =N H2 / S H2 ×S O2 ×α

[0163] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is the standard This is the integrated value of the ion intensity when the sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 Let's say S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. Details of the above formula For details, see Japanese Patent Application Laid-Open No. 6-275697. A thermal desorption analyzer EMD-WA1000S / W manufactured by Kagaku Co., Ltd. was used as a standard sample. Measurements are made using a silicon substrate containing a fixed amount of hydrogen atoms.

[0164] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The atomic ratio can be calculated from the ionization rate of oxygen molecules. Since it includes the ionization rate of the molecules, evaluating the amount of released oxygen molecules can be used to estimate the amount of released oxygen atoms. It is also possible to estimate.

[0165] In addition, N O2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount of offspring released.

[0166] Alternatively, insulators that release oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to peroxide radicals is 5×10 17 spins / cm 3 Insulators containing peroxide radicals can be analyzed by electron spin resonance (E In SR (Electron Spin Resonance), the g value is around 2.01. It may also have an asymmetric signal.

[0167] The insulator 104 may also have a function of preventing the diffusion of impurities from the substrate 100. .

[0168] As mentioned above, it is preferable that the upper or lower surface of the semiconductor 106b is highly flat. Therefore, the upper surface of the insulator 104 is subjected to chemical mechanical polishing (CMP). To improve the flatness, a flattening process is performed using methods such as the CAL Polishing. Good too.

[0169] The conductor 108a and the conductor 108b are the source electrode or It functions as either a drain electrode or a gate electrode.

[0170] The conductor 108a and the conductor 108b may include, for example, boron, nitrogen, oxygen, fluorine, Silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, Zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium Conductors containing one or more of aluminum, tin, tantalum and tungsten are used in a single layer or multilayer. For example, alloys or compounds may be used, and conductors containing aluminum, copper, Conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductors containing titanium and nitrogen, etc. may also be used.

[0171] Here, it is preferable that the lower surfaces of the conductors 108a and 108b do not come into contact with the upper surface of the insulator 104. For example, as shown in FIG. 1B, the bottom surfaces of the conductors 108a and 108b are It is sufficient that the semiconductor 106b is formed in contact with only the upper surface of the semiconductor 106b. As a result, oxygen is drawn from the insulator 104 to the lower surfaces of the conductors 108a and 108b. As a result, the conductors 108a and 108b are partially oxidized. The increase in resistivity due to the change in the insulating layer 104 is suppressed, and the insulating layer 106a and the semiconductor layer 106 are separated. b and the insulator 106c can be supplied with oxygen effectively.

[0172] In addition, the conductors 108a and 108b have a small area in the area where they do not overlap with the conductor 114. It is preferable that at least a part of the insulating material 106 overlaps with the insulating material 112 via the insulating material 106c. As shown in FIG. 1(B), most of the upper surfaces of the conductors 108a and 108b are covered with the insulator 10 By adopting such a configuration, the conductor 108a and the conductor 6c are covered. On the upper surface of the insulator 108b, oxygen can be prevented from being extracted from the insulator 112. This prevents a portion of the conductor 108a and the conductor 108b from being oxidized and increasing the resistivity. and the insulator 112 to the insulator 106a, the semiconductor 106b and the insulator 106c. This effectively supplies oxygen.

[0173] The insulator 112 functions as a gate insulating film for the transistor 10. The insulator 112 may be an insulator having excess oxygen, similar to the insulator 104. By providing the insulating layer 112, the insulating layer 106a, the semiconductor layer 106b, and the insulating layer 106c can supply oxygen to

[0174] The insulator 112 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium Insulators containing aluminum, zirconium, lanthanum, neodymium, hafnium or tantalum are used alone. For example, the insulator 112 may be made of aluminum oxide, Magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide For example, tantalum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used.

[0175] The conductor 114 functions as the gate electrode of the transistor 10. Any conductor that can be used as the conductor 102 may be used.

[0176] Here, as shown in FIG. 1C, the electric fields of the conductors 102 and 114 The semiconductor 106b can be electrically surrounded (the electric field generated by the conductor The structure of a transistor that electrically surrounds the body is called a surrounded channel ( Therefore, the entire semiconductor 106b (top, bottom, and In the s-channel structure, the channel is formed in the source and side of the transistor. A large current can be passed between the source and drain, and the current during conduction (on-state current) can be increased. can.

[0177] When the transistor has an s-channel structure, the side surface of the semiconductor 106b is Therefore, the thicker the semiconductor 106b, the larger the channel region. That is, the thicker the semiconductor 106b, the higher the on-current of the transistor. In addition, the thicker the semiconductor 106b, the greater the proportion of the region with high carrier controllability. For example, the subthreshold swing value can be reduced to 10 nm or more. Preferably, it is 20 nm or more, more preferably 30 nm or more, and even more preferably 50 nm or more. However, the productivity of the semiconductor device may be reduced. Therefore, for example, it is set to 300 nm or less, preferably 200 nm or less, and more preferably In this case, the semiconductor 106b may have a region with a thickness of 150 nm or less.

[0178] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor The device can be a highly integrated, high density semiconductor device. The transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. Preferably, the transistor has a channel width of 20 nm or less. or 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. It has a region.

[0179] The insulator 116 functions as a protective insulating film for the transistor 10. The thickness of the insulating film can be, for example, 5 nm or more, or 20 nm or more. At least a portion of the body 116 is formed in contact with the upper surface of the insulator 104 or the upper surface of the insulator 112. It is preferable that

[0180] The insulator 116 may be, for example, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in single or double layers. The insulator 116 may be made of oxygen, hydrogen, water, alkali metals, alkaline earth metals, or the like. It is preferable that the insulating material has an effect of blocking metals, etc. Examples of such insulating materials include The nitride insulating film may be made of silicon nitride, oxynitride, or the like. Silicon nitride, aluminum nitride, aluminum oxide nitride, etc. Alternatively, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples of the oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, and oxide Gallium nitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride Funium, etc.

[0181] Here, the insulator 116 is preferably formed by sputtering. It is more preferable to carry out the sputtering method in an atmosphere containing By forming the insulator 116, the insulator 104 or the insulator 112 is formed. near the surface of the insulator 116 (the interface between the insulator 104 or the insulator 112 and the insulator 116 after the insulator 116 is formed) Oxygen is added nearby.

[0182] The insulator 116 is an insulator that is less permeable to oxygen than the insulators 104 and 112. It is preferable that the insulating material 116 has a function of blocking oxygen. As a result, the insulator 104 and the insulator 112 are replaced by the insulator 106a, the semiconductor 106b, and the insulator 112. When oxygen is supplied to the insulator 106c, the oxygen is released to the outside above the insulator 116. This can prevent accidents.

[0183] Aluminum oxide has a film that is resistant to both impurities such as hydrogen and moisture, and oxygen. It is preferable to apply it to the insulator 116 because it has a high blocking effect of preventing transmission.

[0184] The insulator 116 can be used as the insulator 106a or the insulator 106c. These oxides can be compared using the sputtering method. Since the insulators 104 and 112 can be formed relatively easily, oxygen can be effectively added to the insulators 104 and 112. As such an insulator 116, it is preferable to use an oxide insulator containing In. For example, In-Al oxide, In-Ga oxide, and In-Ga-Zn oxide are used. Oxide insulators containing In are prone to generate particles when they are formed by sputtering. Because they are few in number, they are suitable for use as insulator 116 .

[0185] The insulator 118 functions as an interlayer insulating film. Any insulator that can be used as the insulating layer may be used.

[0186] The conductor 120a and the conductor 120b are the source electrode and the drain electrode of the transistor 10. The conductors 120a and 120b function as wiring electrically connected to the electrodes. In this case, a conductor that can be used as the conductor 108a and the conductor 108b may be used. stomach.

[0187] By adopting the above-described structure, a transistor having stable electrical characteristics can be provided. Alternatively, it is possible to provide a transistor with a small leakage current when it is not conducting. Alternatively, a transistor having high frequency characteristics can be provided. In this way, a transistor having normally-off electrical characteristics can be provided. It is possible to provide a transistor with a small threshold swing value. This makes it possible to provide a highly reliable transistor.

[0188] <Modification of Transistor> Modified examples of the transistor 10 will be described below with reference to FIGS. 7 to 12 show the structure of the transistor in the channel length direction, similar to FIGS. 1B and 1C. The diagrams are a cross-sectional view and a cross-sectional view in the channel width direction of the transistor.

[0189] The transistor 12 shown in FIGS. 7A and 7B has a feature that the insulator 105 is not formed. This differs from the transistor 10 in that the conductor 102 is separated from the insulator 101 and the insulator 10 3. Here, the insulators 101 and 103 block oxygen. By adopting such a structure, it is preferable that the insulating material 104 and the like have the function of This prevents the conductor 102 from being oxidized due to oxygen being extracted. The insulator 106a and the semiconductor 106b are prevented from being oxidized and the resistivity is prevented from increasing. 106b and the insulator 106c can be supplied with oxygen effectively.

[0190] The transistor 14 shown in FIGS. 7C and 7D has an insulator 103 and an insulator 105. This differs from the transistor 10 in that the insulator 104 is not connected to the conductor 10. 2. Here, the insulator 101 has a function of blocking oxygen. By adopting such a configuration, the insulating material 104 is separated from the insulating material 106a and the semiconductor material 106b. When oxygen is supplied to the conductor 106b and the insulator 106c, the oxygen diffused into the insulator 104 This prevents the insulator 106 from diffusing into layers below the insulator 104. a, the semiconductor 106b, and the insulator 106c can be supplied with oxygen effectively.

[0191] In the transistor 14, the conductor 102 may be made of Ru, titanium nitride, or tungsten. Oxidation resistance of sten silicide, platinum, iridium, ruthenium oxide, iridium oxide, etc. By using such a structure, the insulator 104 can be formed in a deposition atmosphere. The conductor 102 has strong oxidation resistance against halogens such as fluorine contained in the atmosphere. This can prevent oxidation.

[0192] The transistor 16 shown in FIGS. 8A and 8B includes a conductor 102, an insulator 103, and an insulator 104. The transistor 10 differs from the transistor 10 in that the insulator 101 is not formed. It is preferable that the insulating layer has a function of blocking oxygen. When oxygen is supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c, Furthermore, it is possible to prevent oxygen diffused in the insulator 104 from diffusing to layers below the insulator 104. This allows oxygen to be effectively introduced into the insulator 106a, the semiconductor 106b, and the insulator 106c. can be supplied.

[0193] The transistor 18 shown in FIGS. 8C and 8D has a conductor 102a instead of the conductor 102. The transistor 14 and the conductor 102b are stacked on top of each other. The conductor 102a is a conductor that can be used as the conductor 102. The conductor 102b may be made of Ru, titanium nitride, tungsten silicide, platinum, or the like. If a highly oxidation-resistant conductor such as iridium, ruthenium oxide, or iridium oxide is used, By adopting such a configuration, the fluorine contained in the film-forming atmosphere of the insulator 104 can be effectively prevented. The conductor 102b has strong oxidation resistance against any halogen, so the conductor 102a It is possible to suppress oxidation.

[0194] The transistor 20 shown in FIGS. 9A and 9B has an insulator 107 provided over an insulator 101. The insulator 107 is formed of a conductive material 102 embedded in an opening in the insulator 107. Here, the insulator 107 can be used as the insulator 105. The top surfaces of the insulator 107 and the conductor 102 may be formed by a CMP method. It is preferable to improve the flatness by performing a flattening process using a method such as the above. Even if the conductor 102 functioning as a gate is provided, the flatness of the surface on which the semiconductor 106b is formed is not Since the conductivity is not impaired, the mobility of carriers is improved and the on-current of the transistor 20 is increased. In addition, there is no step on the surface of the insulator 104 due to the shape of the conductor 102. As a result, the conductors 108a and 108b function as drains and the conductor 108c function as drains. 02, the leakage current generated through the step portion of the insulator 104 can be reduced. This allows the off-state current of the transistor 20 to be reduced.

[0195] The transistor 22 shown in FIGS. 10A and 10B includes a conductor 108a, a conductor 108b, and a An insulator 117 is formed covering the insulator 104, and the insulator 117 has a thickness that reaches the semiconductor 106b. An opening is provided through which the insulator 106c, the insulator 112, and the conductor 114 are embedded. The transistor 20 is different from the transistor 20 in that the opening is provided so as to be enclosed within the opening. Therefore, the conductor 108a and the conductor 108b are spaced apart. A conductor 114 that functions as a gate electrode is formed through an opening formed by an insulator 117 or the like. Since it is self-aligned to fill the gap, TGSA s -channel FET(Trench Gate Self Align s-ch It can also be called a channel FET.

[0196] Here, the insulator 117 may be formed using an insulator that can be used for the insulator 104. The upper surface of the insulator 117 may be flattened by a CMP method or the like.

[0197] Here, similarly to the insulator 104, when the insulator 117 is formed, a halogen such as SiF4 is used. When silicon nitride is used, halogen such as fluorine is contained in the insulator 117. During the heat treatment, oxygen in the insulator 117 is substituted with fluorine and the oxygen is released. The insulating layer 106a and the semiconductor 106b may be supplied with halogen. The insulator 117 is made to have a relative dielectric constant of less than 3.5, more preferably It is preferable that the insulator 117 functions as a low-k film having a thickness of less than 3. By doing so, the parasitic capacitance can be further reduced.

[0198] In the transistor 22, an insulator 117 is provided between the conductor 108a and the conductor 114, and an insulator 118 is provided between the conductor 108a and the conductor 114. 106c and an insulator 112 are provided. In addition, an insulator is provided between the conductor 108b and the conductor 114. The conductive body 117, the insulator 106c, and the insulator 112 are provided. the distance between the upper surface of the conductor 108b and the lower surface of the conductor 114, The distance between the conductors 11 can be increased by the thickness of the insulator 117. 4 and the conductor 108a or the conductor 108b. By reducing the parasitic capacitance, the switching speed of the transistor can be improved. Therefore, a transistor having high frequency characteristics can be provided.

[0199] The transistor 24 shown in FIGS. 10C and 10D includes an insulator 117, an insulator 106c, and an insulator The upper surfaces of the body 112 and the conductor 114 are generally flush with each other and are flat. , and transistor 22. This is because the insulator 117, the insulator 106c, the insulator 112, and The upper surface of the conductor 114 may be planarized by a CMP method or the like.

[0200] As a result, the area where the conductor 114 overlaps with the conductor 108a or the conductor 108b is almost Since the gate-source and gate-drain of the transistor 24 are not formed, By reducing the parasitic capacitance, the This allows for the improvement of the switching speed of transistors with high frequency characteristics. A register can be provided.

[0201] The transistor 29 shown in FIGS. 11A and 11B has an insulator 107 provided over an insulator 101. The conductor 102 is embedded in the opening in the insulator 107, and the transistor The insulator 106c is different from the semiconductor 24. The transistor 29 also differs from the transistor 24 in that it covers the insulator 1. The insulator 106c is not provided on the side of the opening of the insulator 117. The length of the conductor 114 in the channel length direction is made longer than that of the transistor 24, etc. It is possible.

[0202] In the transistor 29, the upper surfaces of the conductors 108a and 108b and Metal oxide 111a and metal oxide 111b are provided on the side surfaces. The metal oxide 111a and the metal oxide 111b are the metal oxides of the conductors 108a and 108b. The conductor 108a and the conductor 108b may be formed thicker on the side than on the top. The metal oxide 111a and the metal oxide 111b are formed on the upper surface and the side surface of the body 108b. This is due to the different processes used.

[0203] The metal oxide 111a and the metal oxide 111b are, for example, insulating materials when the insulator 117 is formed. The conductive layer 112 is formed by one or more processes such as deposition of the conductive layer 112 or plasma treatment. In this case, the metal oxide 11 is formed by oxidation of the metal oxide 11. The metal oxide 111a and the metal oxide 111b are the elements that make up the conductor 108a and the conductor 108b. The oxide has the following structure:

[0204] The combined volume of the conductor 108a and the metal oxide 111a is Similarly, the volume of the conductor 108b and the gold The volume of the conductor 108b including the metal oxide 111b is larger than the volume of the conductor 108b before the formation of the metal oxide 111b. The amount of damage may be larger than the actual damage.

[0205] The metal oxide 111 is formed on the top surface and the side surface of the conductor 108a and the conductor 108b. a and metal oxide 111b, the transistor 29 This structure alleviates the electric field concentration at the electrode end. A transistor with high reliability and small short channel effect can be obtained.

[0206] However, the metal oxide 111a and the metal oxide 111b are in the case of the transistor 29. For example, other transistors may be formed on the metal oxide 111a and the metal oxide 111b. It is also acceptable to have 11b.

[0207] The transistor 26 shown in FIGS. 12A and 12B includes the conductor 108a and the conductor 108b. The conductor 114 and the insulator 112 are not provided with a conductor 114 and an insulator 112, and the end side surfaces of the conductor 114 and the insulator 112 are provided so as to be substantially aligned with each other. The transistor 10 and the like are different from the transistor 20 in that they are In the transistor manufacturing process, a low resistance region 10 which functions as a source region or a drain region is formed. 9a, 109b are formed before the formation of the conductor 114 that functions as the gate. In contrast, the transistor 26 is manufactured in the transistor manufacturing process as follows: The low resistance regions 109a and 109b functioning as source and drain regions are used as gates. This is a gate first method in which the gate is formed after the formation of the conductor 114 that functions as a gate electrode.

[0208] In the transistor 26, the low resistance region 109a and the low resistance region 109b are formed by insulating material 1. 16. The low resistance region 109a and the low resistance region 10 A part of 9b is roughly the same as the region (channel formation region) where the semiconductor 106b overlaps with the conductor 114. It is preferable that the area is in contact with or overlaps with a part of the area.

[0209] In addition, the low resistance region 109a and the low resistance region 109b are formed by using an element contained in the insulator 116. Since the semiconductor 106b is doped with Zn, the low resistance region 109a and the low resistance region 109b of the semiconductor 106b are not SIMS analysis is more sensitive to the area of ​​the semiconductor 106b than to the area of ​​the semiconductor 106c that overlaps the conductor 114. This results in a higher concentration of the element.

[0210] The elements added to the low resistance region 109a and the low resistance region 109b include, for example, boron. element, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, Zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum or tungsten These elements are relatively easy to form oxides, and the oxides are semiconductors. Therefore, the semiconductor 106a, the semiconductor 106b, or the insulator 106c can function as a semiconductor or an insulator. For example, the low resistance region 109a and the low resistance region 109b are preferably added to the low resistance region 109c. b contains 1×10 14 molecules / cm 2 Over 2×10 16 mole cules / cm 2 It is preferable that the insulator 106c contains the following: The region 109a and the low resistance region 109b are formed by the low resistance region 109a and the low resistance region 109b of the insulator 106c. than the area other than the area 109b (for example, the area where the insulator 106c overlaps with the conductor 114). , high concentrations of the above-mentioned elements.

[0211] The low resistance regions 109a and 109b contain nitrogen, thereby forming n-type Therefore, the low resistance region 109a and the low resistance region 109b of the semiconductor 106b can be b (for example, the area of ​​the semiconductor 106b overlapping with the conductor 114) The nitrogen concentration obtained by analysis is higher.

[0212] By forming such low resistance regions 109a and 109b, a conductive The semiconductor 108a or the conductor 108b and the insulator 106a, the semiconductor 106b or the insulator 106c Since the contact resistance can be reduced, the on-current of the transistor 10 can be increased. This can be done.

[0213] In the transistor 26, the semiconductor 106b is connected to the insulator 106a and the insulator 106c. Therefore, the end side surface of the semiconductor 106b, in particular the chip The vicinity of the end side surface in the channel width direction is provided in contact with the insulator 106a and the insulator 106c. As a result, the insulator 106a or the insulator 106b is A continuous junction is formed between the low-resistance region 106c and the low-resistance region 106c, and the defect level density is reduced. Even if the on-current becomes easy to flow by providing the low-resistance region 109a and the low-resistance region 109b, The side surfaces of the ends of the conductor 106b in the channel width direction do not become parasitic channels, and stable electrical characteristics are obtained. can be obtained.

[0214] The transistor 28 shown in FIGS. 12C and 12D is provided with an insulator 112 and a conductor 114. Transistor 28 differs from transistor 10 in that it is not This is a so-called bottom gate transistor.

[0215] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0216] (Embodiment 2) In this embodiment, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. This will be explained using FIG.

[0217] <Transistor manufacturing method> A method for manufacturing the transistor 10 will be described below with reference to FIGS. 13 to 15. do.

[0218] First, a substrate 100 is prepared. The substrate used for the substrate 100 may be any of the above-mentioned substrates. That's fine.

[0219] Next, the insulator 101 is formed. As the insulator 101, any of the above insulators may be used.

[0220] The insulator 101 is formed by a sputtering method, a chemical vapor deposition (CVD) method, or the like. Vapor Deposition method, Molecular Beam Epitaxy (MBE) Laser Beam Epitaxy (PLD) or Pulsed Laser Deposition (PLD) Atomic Layer Deposition (ALD) This can be done using a method such as er deposition.

[0221] Next, a conductor that will become the conductor 102 is formed. The conductive material can be formed by a sputtering method, a CVD method, an MB method, etc. This can be carried out using the E method, PLD method, ALD method, or the like.

[0222] Next, a resist or the like is formed on the conductor, and the conductor 10 is processed using the resist or the like. 2 is formed (see Figures 13(A) and 13(B)). This also includes the case where an anti-reflection layer is formed under the resist.

[0223] The resist is removed after the object is processed by etching or other methods. For this purpose, plasma treatment and / or wet etching are used. Plasma ashing is suitable for this purpose. If the removal of resist, etc. is insufficient, Hydrofluoric acid and / or ozone at a concentration of 1% by volume or more but not exceeding 1% by volume Residual resist may be removed using rinsing water or the like.

[0224] Next, the insulator 105 is formed. As the insulator 105, any of the above insulators may be used. The insulator 105 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In addition, the water or hydrogen contained in the insulator 105 can be reduced by For example, the film may be formed while the substrate is heated to reduce the When a semiconductor element layer is provided on the substrate, a relatively low temperature range (for example, 350°C or higher, 44°C or higher) is used. It may be heated to a temperature range of approximately 5°C or less.

[0225] In addition, by forming a film by the PECVD method using the same method as the insulator 104 described later, In addition, the water or hydrogen contained in the insulator 105 may be reduced.

[0226] Next, the insulator 103 is formed. As the insulator 103, any of the above insulators may be used. The insulator 103 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In addition, the water or hydrogen contained in the insulator 103 can be reduced by For example, the film may be formed while the substrate is heated to reduce the When a semiconductor element layer is provided on the substrate, a relatively low temperature range (for example, 350°C or higher, 44°C or higher) is used. It may be heated to a temperature range of approximately 5°C or less.

[0227] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0228] The PECVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the object to be treated because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device When a charge is received from the plasma, it may be charged up. The accumulated charge may destroy the wiring, electrodes, elements, etc. contained in the semiconductor device. On the other hand, in the case of the TCVD method, which does not use plasma, such plasma damage does not occur. Therefore, the yield of semiconductor devices can be increased. Since no plasma damage occurs, a film with few defects can be obtained.

[0229] The ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with few defects can be produced. is obtained.

[0230] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is less affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it suitable for forming thin films with high aspect ratios. This is suitable for coating the surface of a highly porous opening. However, the ALD method has a relatively slow film formation rate, It may be preferable to use it in combination with other film formation methods such as CVD, which has a high film formation rate. be.

[0231] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having the following composition. By changing the flow rate ratio of the source gases while oxidizing, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film using a vacuum chamber, the time required for film formation is shorter due to the time required for transport and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0232] In conventional film-forming equipment using the CVD method, one of the source gases for the reaction is used for film formation. Multiple species are supplied to the chamber simultaneously. A raw material gas (also called a precursor) and a gas that acts as a reactant (also called a reactant) These gases are introduced alternately into the chamber, and film formation is performed by repeating the introduction of these gases. The switching of the introduced gas is performed using, for example, the respective switching valves (also called high-speed valves) can be switched between.

[0233] For example, the film is formed in the following procedure: First, the precursor is introduced into the chamber. The precursor is adsorbed onto the substrate surface (first step). By depositing the precursor on the substrate, a self-limiting mechanism of the surface chemical reaction takes effect, and the precursor is deposited on the substrate. Furthermore, the self-limiting mechanism of the surface chemical reaction is at work. The optimum substrate temperature range is also called the ALD window. It is determined by the temperature characteristics of the case, vapor pressure, decomposition temperature, etc. Next, inert gas (argon or nitrogen) into the chamber, and excess precursors and reaction products are removed by The chamber is evacuated (second step). Excess precursors and reaction products may be discharged from the chamber by A reactant (e.g., an oxidizing agent (H2O, O3, etc.)) is introduced into the chamber, and the reactant is oxidized on the substrate surface. The film is reacted with the adsorbed precursor, and one of the precursors is removed while the constituent molecules of the film are adsorbed on the substrate. Next, the excess gas is removed by introducing an inert gas or by evacuating. The reactants and reaction products are then discharged from the chamber (fourth step).

[0234] In addition, the introduction of reactant in the third step and the introduction of inert gas in the fourth step The introduction of may be repeated multiple times. That is, after the first step and the second step, 3rd step, 4th step, 3rd step, 4th step... and 3rd step and 4th step Repeated tapping may be performed.

[0235] For example, in the third step, O3 is introduced as an oxidant, and in the fourth step, N2 is purged. This process may be repeated multiple times.

[0236] Also, when repeating the third and fourth steps, the same type of reactant is not necessarily used. For example, if H2O is used as an oxidant in the first third step, Alternatively, O3 may be used as the oxidizing agent in the third step from the second time onwards.

[0237] In this way, the introduction of oxidizing agent and inert gas (or vacuum exhaust) in the chamber By repeating this process multiple times in a short time, excess hydrogen atoms are released from the precursor adsorbed on the substrate surface. It is possible to remove the oxidizing agent species more reliably and expel them from the chamber. By increasing the number of species to two, excess hydrogen atoms and other In this way, hydrogen atoms are incorporated into the film during film formation. By doing so, water, hydrogen, etc. contained in the formed insulator 103 etc. can be reduced. It is possible.

[0238] By using this method, the insulator 103 is heated to 100°C or higher for 7 hours as determined by TDS analysis. In the surface temperature range of 100°C or below or 100°C to 500°C, the amount of water molecules released is 1. 0×10 13 molecules / cm 2 Over 1.0 x 10 16 molecules / c m 2 or less, more preferably 1.0 × 10 13 molecules / cm 2 Over 3.0 x 10 15 molecules / cm 2 The insulator may be:

[0239] In this way, a first monolayer can be formed on the surface of the substrate, and the first to fourth steps are carried out. By repeating the process, a second monolayer can be laminated on top of the first monolayer. Steps 1 to 4 are repeated multiple times while controlling the gas introduction until the film reaches the desired thickness. This allows the formation of a thin film with excellent step coverage. The thickness of the thin film increases depending on the number of repetitions. Therefore, precise film thickness control is possible, and fine transistors can be fabricated. It is suitable for manufacturing.

[0240] The ALD method is a film formation method in which precursors are reacted using thermal energy. In the reaction of the reactant, the reactant is converted into a radical state using plasma. The ALD method in which the process is performed as a plasma is sometimes called the plasma ALD method. The ALD method in which the reaction between precursors and reactants is carried out using thermal energy is called thermal ALD. There is.

[0241] The ALD method can deposit extremely thin films with uniform thickness. It also has a high surface coverage rate.

[0242] In addition, by forming the film using the plasma ALD method, it is possible to form the film at a lower temperature than with the thermal ALD method. The plasma ALD method can be used at temperatures below 100 degrees without reducing the film formation rate. In addition, plasma ALD can be used with not only oxidizing agents but also nitrogen gas. Many reactants can be used, so not only oxides but also nitrides and fluorides can be used. It is possible to form many types of films, including metal films.

[0243] In addition, when using the plasma ALD method, ICP (Inductively Coupled Plasma) It is also possible to generate plasma away from the substrate, such as with LED Plasma. By generating plasma in this way, plasma damage can be suppressed. can.

[0244] Here, as an example of an apparatus capable of forming a film using the ALD method, a film forming apparatus 1000 The configuration will be explained using Fig. 16(A) and Fig. 16(B). Fig. 16(A) shows the FIG. 16(B) is a schematic diagram of a multi-chamber type film forming apparatus 1000. FIG. 1 is a cross-sectional view of an ALD apparatus that can be used in the present invention.

[0245] <<Configuration example of film formation device>> The film forming apparatus 1000 includes a carry-in chamber 1002, a carry-out chamber 1004, a transfer chamber 1006, and a film forming chamber 1008. 1008, a film forming chamber 1009, a film forming chamber 1010, and a transfer arm 1014. Here, the loading chamber 1002, the unloading chamber 1004, and the film forming chambers 1008 to 1010 are a transfer chamber 10 06. This allows the film formation chambers 1008 to 1010 to be exposed to the atmosphere. This allows continuous film formation without the need for a separate process, and prevents impurities from being mixed into the film.

[0246] The loading chamber 1002, the unloading chamber 1004, the transfer chamber 1006, the film forming chambers 1008 to 1010, 0 is filled with an inert gas (nitrogen gas, etc.) with a controlled dew point to prevent moisture from adhering. It is preferable to keep the pressure reduced.

[0247] In addition, ALD equipment can be used in the film formation chambers 1008 to 1010. A film forming apparatus other than an ALD apparatus may be used in any of the film chambers 1008 to 1010. The film forming apparatus used in the film forming chambers 1008 to 1010 may be, for example, a sputtering There are various types of equipment, including PECVD equipment, TCVD equipment, and MOCVD equipment.

[0248] For example, the film formation chambers 1008 to 1010 may be configured to include an ALD apparatus and a PECVD apparatus. By doing so, the insulator 1 made of silicon oxide of the transistor 10 shown in FIGS. 05 is formed by the PECVD method, and the insulator 103 made of hafnium oxide is formed by the ALD method. The insulator 104 made of silicon oxide containing halogen can be formed by the PECVD method. The series of film formation processes are carried out continuously without exposing the film to the atmosphere, so there is no risk of impurities being mixed into the film. Film formation can be performed without any need for a solder paste.

[0249] The film forming apparatus 1000 includes a carry-in chamber 1002, a carry-out chamber 1004, and film forming chambers 1008 to 1009. However, the present invention is not limited to this. The number of film formation chambers may be four or more. The film forming apparatus 1000 may be of a single wafer type. A batch system in which films are formed on a plurality of substrates at once may also be used.

[0250] 《ALD equipment》 Next, the configuration of an ALD apparatus that can be used in the film formation apparatus 1000 will be described. The D device includes a film-forming chamber (chamber 1020), raw material supply units 1021a and 1021b, and a flow The high-speed valves 1022a and 1022b are volume controllers, and the raw material inlets 1023a and 1023b are b, a raw material outlet 1024, and an exhaust device 1025. The raw material inlets 1023a and 1023b are connected to the raw material supply unit 1021 via supply pipes and valves. The raw material outlet 1024 is connected to the discharge pipe, valve, and pressure It is connected to the exhaust device 1025 via a power regulator.

[0251] Also, as shown in FIG. 16(B), a plasma generator 1028 is connected to the chamber 1020. By connecting the two, film formation can be performed by the plasma ALD method in addition to the thermal ALD method. With the plasma ALD method, film formation can be performed at low temperatures without reducing the film formation rate, so there is no need to worry about low film formation efficiency. It is preferable to use it in a single-wafer deposition apparatus.

[0252] Inside the chamber, there is a substrate holder 1026 equipped with a heater. 6, a substrate 1030 on which a film is to be formed is placed.

[0253] In the raw material supply units 1021a and 1021b, solid raw materials and The raw material supply units 1021a and 1021b generate raw material gas from a liquid raw material. The gas may be supplied from the source material.

[0254] Although an example in which two raw material supply units 1021a and 1021b are provided is shown, there is no particular limitation. In addition, three or more high-speed valves 1022a and 1022b can be provided. The gas supply system is configured to supply either the raw material gas or the inert gas. The high-speed valves 1022a and 1022b are flow rate controllers for the source gases and also for the inert gas. It can also be called a flow rate controller.

[0255] In the film forming apparatus shown in FIG. 16(B), the substrate 1030 is carried onto the substrate holder 1026. After the chamber 1020 is sealed, the substrate 10 is heated by the heater of the substrate holder 1026. 30 is heated to a desired temperature (for example, 80°C or higher, 100°C or higher, or 150°C or higher), and the raw material Gas supply, exhaust by exhaust device 1025, inert gas supply, exhaust device 1025 By repeating this process and exhausting the gas, a thin film is formed on the surface of the substrate.

[0256] In the film forming apparatus shown in FIG. 16(B), the raw materials ( By appropriately selecting the appropriate volatile organic metal compounds, hafnium, aluminum, tantalum, Oxides (including composite oxides) containing one or more elements selected from tantalum, zirconium, etc. Specifically, an insulating layer containing hafnium oxide can be formed. an insulating layer containing aluminum oxide; an insulating layer containing hafnium silicate; an insulating layer comprising aluminum silicate; In addition, the raw material used in the raw material supply units 1021a and 1021b can be By appropriately selecting the appropriate organic compound (e.g., volatile organometallic compound), it is possible to form a tungsten layer, a titanium layer, etc. Any thin film such as a metal layer or a nitride layer, such as a titanium nitride layer, can be deposited.

[0257] For example, when forming a hafnium oxide layer using an ALD system, the solvent and the hafnium precursor are Liquids containing precursor compounds (hafnium alkoxides, tetrakisdimethylamidohafnium The raw material gas is vaporized hafnium amide (TDMAH) and ozone is used as an oxidizer. In this case, two kinds of gases are used: the first gas supplied from the raw material supply unit 1021a, and the second gas (O3). The first raw material gas is TDMAH, and the second raw material gas supplied from the raw material supply unit 1021b is O. The chemical formula of tetrakisdimethylamidohafnium is Hf[N(CH3) 2]4. Other material liquids include tetrakis(ethylmethylamide)hafnium. There are many examples.

[0258] When forming an aluminum oxide layer using an ALD system, a solvent and an aluminum precursor are used. The raw material gas is made by vaporizing a liquid containing a compound (TMA: trimethylaluminum, etc.) and an acid. In this case, two kinds of gases are used, one of which is a nitriding agent and the other is H2O. The first source gas supplied from the source supply unit 1021b is TMA, and the second source gas supplied from the source supply unit 1021b is The chemical formula for trimethylaluminum is Al(CH3)3. Other liquid materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionato) Examples include:

[0259] When forming a tungsten layer using an ALD system, WF6 gas and B2H6 gas are used. The initial tungsten layer is formed by repeatedly introducing WF6 gas and H2 gas. The tungsten layer is formed by repeatedly introducing SiH instead of B2H6 gas. These gases may be controlled by a mass flow controller. This may also be configured as follows.

[0260] Next, the insulator 104 is formed (see FIGS. 13(C) and 13(D)). The insulator 104 can be formed by a sputtering method, a CVD method, an MB method, or the like. This can be carried out using the E method, PLD method, ALD method, or the like.

[0261] The insulator 104 is preferably formed by CVD, particularly PECVD. It is preferable to do this in a

[0262] When the insulator 104 is formed by the PECVD method, the source gas is preferably a gas containing no hydrogen or a gas containing no hydrogen. It is preferable to use a substance with a low hydrogen content, for example, a halide. For example, a silicon oxide or silicon oxynitride film is formed as the insulator 104. In this case, it is preferable to use silicon halide as the source gas, for example, SiF4 (tetrafluoroethylene). Silicon fluoride), SiCl4 (silicon tetrachloride), SiHCl3 (silicon trichloride), SiH 2Cl2 (dichlorosilane) or SiBr4 (silicon tetrabromide) can be used. do.

[0263] When the insulator 104 is formed by the PECVD method, an oxidizing gas (such as N2O) is introduced. The silicon halide is less reactive than SiH4, so it is oxidizing. The gas easily acts on the insulator 103. As a result, the water or hydrogen contained in the insulator 103 is desorbed by the oxidizing gas, and the amount of water and hydrogen contained in the insulator 103 is reduced. It is possible that this is possible.

[0264] In addition, when silicon halide is used as a source gas for forming the insulator 104, the halogen In addition to silicon hydride, silicon hydride may be added. The hydrogen and water contents in the insulator 104 are reduced compared to when the raw material gas is made of chlorine. The film formation rate can be improved compared to when only silicon dioxide is used as the source gas. The insulator 104 can be formed using iF4 and SiH4 as raw material gases. For example, SiH4 The flow rate is set to be greater than 1 sccm and less than 10 sccm, more preferably, greater than 2 sccm and less than 4 sccm. ccm or less, both the content of water and hydrogen in the insulator 104 and the film formation rate can be reduced. However, the flow rate ratio of SiF4 and SiH4 is The temperature can be appropriately set taking into consideration the water and hydrogen content in the O4 and the film formation rate.

[0265] In addition, in order to reduce the amount of water or hydrogen contained in the insulator 104, the substrate is heated. For example, a semiconductor element layer is provided below the transistor 10. Relatively low temperature range (for example, a temperature range of 350°C to 445°C) Even if heated at room temperature, the insulator 104 is formed as a film by the method described below, and water, hydrogen, etc. are sufficiently absorbed. etc. can be removed.

[0266] In addition, before forming the insulator 104 on the substrate, SiH4 is introduced into the chamber. It is relatively easy to form a film on hafnium oxide, on which it is difficult to form a film of silicon oxide containing fluorine. A silicon oxide film containing fluorine can be easily formed.

[0267] By using this method, the insulator 104 is heated to 100° C. or higher by TDS analysis. In the surface temperature range of 700°C or less or 100°C to 500°C, the amount of water molecules released is 1 .0×10 13 molecules / cm 2 Over 1.4 x 10 16 molecules / cm 2 Below, 1.0 x 10 13 molecules / cm 2 Over 4.0 x 10 15 molecules / cm 2 Below, 1.0 x 10 13 molecules / cm 2 Over 2.0 x 10 15 molecules / cm 2 The insulator can be In addition, the insulator 104 is subjected to a TDS analysis at a temperature of 100°C or higher and 700°C or lower. In the surface temperature range of 500°C or less, the amount of hydrogen molecules desorbed is 1.0×10 13 molecu les / cm 2 Over 1.2 x 10 15 molecules / cm 2 Below, 1.0x 10 13 molecules / cm 2 Over 9.0 x 10 14 molecules / cm 2 The following insulators can be used:

[0268] In addition, it is preferable that the upper or lower surface of the semiconductor 106b to be formed later has high flatness. Therefore, the top surface of the insulator 104 is subjected to a planarization process such as CMP to improve the planarity. That's fine.

[0269] Next, heat treatment is preferably performed. By the heat treatment, the insulator 105 and the insulator The water or hydrogen in the insulating material 103 and the insulating material 104 can be further reduced. In some cases, excess oxygen can be contained in the insulating layer 104. 650°C or less, preferably 450°C or more and 600°C or less, more preferably 520°C or more and 5 The heat treatment should be carried out at 70°C or below. The heat treatment should be carried out in an inert gas atmosphere or in an oxidizing gas atmosphere at 10ppm. The heat treatment is carried out in an atmosphere containing more than m, more than 1%, or more than 10%. Alternatively, the heat treatment may be carried out in an inert gas atmosphere, followed by a gas to replenish the desorbed oxygen. Therefore, heat treatment is performed in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. Heat treatment may be performed to increase the crystallinity of the insulator 126a and the semiconductor 126b. It is possible to remove impurities such as hydrogen and water. The heat treatment using an RTA device is shorter than that using a furnace. This is effective in increasing productivity because it requires only a small amount of time.

[0270] In addition, when a semiconductor element layer is provided below the transistor 10, a relatively low temperature It can be heated in a range (for example, a temperature range of 350°C to 445°C). For example, any one of the substrate heating temperatures during the deposition of the insulators 105, 103, and 104 It is preferable that the heating temperature is equal to or lower than the highest heating temperature among the above.

[0271] Next, the insulator 126a is formed. The insulator 126a may be formed using an insulator or a semiconductor that can be used in various ways. The method can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. This can be done.

[0272] Next, the semiconductor 126b is formed. The semiconductor 126b can be formed by sputtering. This can be done by using a method such as a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 126a and the semiconductor 126b are successively formed without being exposed to the atmosphere. By carrying out this treatment, it is possible to reduce the amount of impurities entering the film and the interface.

[0273] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the insulator 126a and the semiconductor In some cases, the hydrogen concentration in the insulator 126a and the insulator 126b can be reduced. The heat treatment may be performed at 250° C. or higher than 650°C, preferably higher than 450°C and lower than 600°C, and more preferably higher than 520°C The heat treatment can be carried out at a temperature of 570°C or less. The heat treatment is carried out in an atmosphere containing more than ppm, more than 1%, or more than 10%. Alternatively, the heat treatment may be carried out in an inert gas atmosphere, followed by absorbing the desorbed oxygen. To compensate for this, heat treatment is carried out in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. The crystallinity of the insulator 126a and the semiconductor 126b can be improved by heat treatment. The heating process can be performed by lamp heating or by removing impurities such as hydrogen and water. An RTA device can also be used. Heat treatment with an RTA device is shorter than that with a furnace. This is effective in increasing productivity because it only takes a short time. When CAAC-OS is used as a fluorine-containing compound, the peak intensity increases by heat treatment. The full width of the value is reduced, which means that the crystallinity of the CAAC-OS is increased by the heat treatment.

[0274] In addition, when a semiconductor element layer is provided below the transistor 10, a relatively low temperature It can be heated in a range (for example, a temperature range of 350°C to 445°C). For example, the substrate heating temperature during the deposition of the insulators 105, 103, and 104, or the insulating film the temperature of the heat treatment after the formation of the insulating film 104, or By forming the insulator 104 by the above-described method, the water in the insulator 104, Since hydrogen and the like are sufficiently removed, water or hydrogen is not present in the insulator 126a and the semiconductor 126b. The amount of supply can be reduced significantly.

[0275] The heat treatment causes oxygen to be transferred from the insulator 104 to the insulator 126a and the semiconductor 126b. By subjecting the insulator 104 to a heat treatment, Oxygen can be supplied to the insulator 126a and the semiconductor 126b.

[0276] Here, the insulator 103 functions as a barrier film that blocks oxygen. By providing the insulating layer 104 under the insulating layer 104, oxygen diffused into the insulating layer 104 is prevented from This can prevent diffusion to layers below the body 104.

[0277] In this way, oxygen is supplied to the insulator 126a and the semiconductor 126b, and oxygen vacancies are reduced. As a result, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor having a low density of defect states can be obtained. It can be said that:

[0278] Further, high density plasma treatment may be performed. High density plasma is generated by using microwaves. In the high-density plasma treatment, for example, an oxidizing gas such as oxygen or nitrous oxide is used. Alternatively, a mixture of an oxidizing gas and a rare gas such as He, Ar, Kr, or Xe can be used. A mixed gas may be used. In the high density plasma treatment, a bias may be applied to the substrate. This allows oxygen ions in the plasma to be drawn to the substrate. The plasma treatment may be performed while heating the substrate. When performing plasma treatment, the same effect can be obtained at a temperature lower than that of the heat treatment. The high-density plasma treatment may be performed before the formation of the insulator 126a or after the formation of the insulator 112. This may be performed after the deposition of the insulator 116 or after the deposition of the insulator 116, for example.

[0279] Next, a conductor 128 is formed (see FIGS. 13(E) and 13(F)). Any conductor that can be used as the conductor 108a and the conductor 108b described above may be used. The conductor 128 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an A method. This can be done using the LD method or the like.

[0280] Next, a resist or the like is formed on the conductor 128, and the resist or the like is used to process the conductor. The conductive body 108a and the conductive body 108b are formed.

[0281] Next, a resist or the like is formed on the semiconductor 126b, and the resist or the like is and conductor 108b to form insulator 106a and semiconductor 106b (FIG. 1). See 3(G)(H). ).

[0282] In addition, in the region of the semiconductor 106b that contacts the conductor 108a and the conductor 108b, In this case, low resistance regions 109a and 109b may be formed. The conductive body 106b is disposed between the conductive body 108a and the conductive body 108b. The conductor 108a and the conductor 108b may have a region with a thinner film thickness than the region overlapping with the conductor 108a and the conductor 108b. When forming the conductor 108b, a part of the upper surface of the semiconductor 106b is removed. will be done.

[0283] Next, heat treatment is preferably performed. By the heat treatment, the insulator 104 and the insulator 103 and the insulator 105, the water or hydrogen in the insulator 106a and the semiconductor 106b is further The heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower, preferably 450°C or lower. The heating temperature is preferably from 520°C to 570°C. The treatment may be carried out in an inert gas atmosphere or in an atmosphere containing an oxidizing gas. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an inert gas atmosphere. After the treatment, oxidizing gas is added at 10 ppm or more, 1% or more, or 1% or more to replace the oxygen that has been removed. Heat treatment may be carried out in an atmosphere containing 0% or more of SiO2. Heat treatment may be carried out in an RTA device using lamp heating. Heat treatment using an RTA device can be completed in a shorter time than using a furnace, It is effective in increasing productivity.

[0284] If a semiconductor element layer is provided below the transistor 10, the semiconductor element In order to avoid deterioration of the substrate, the temperature range is relatively low (for example, between 350°C and 445°C). It is preferable to heat the mixture at a temperature in the range of 100°C.

[0285] Here, if the insulator 104 contains a large amount of water and hydrogen during film formation, the semiconductor element in the lower layer Even if the heat treatment is performed within a temperature range that does not deteriorate the insulating layer, water, hydrogen, etc. are sufficiently removed from the insulator 104. Furthermore, after the insulator 106c is formed, the insulator 106c may not be removed properly. When the heat treatment is performed within the temperature range, water, hydrogen, etc. are supplied from the insulator 104 to the semiconductor 106b, etc. This may result in the formation of defect levels.

[0286] In contrast, as described above, the insulator 106a and the semiconductor 106b are formed, and the insulator 106b is By performing a heat treatment at the stage when the surface of the insulating layer 106a and the semiconductor layer 104 is exposed, While suppressing the supply of water and hydrogen to the insulator 106b, the insulator 104, the insulator 103 and the insulator The water or hydrogen in the insulator 105 can be further reduced. By further reducing the amount of water or hydrogen in the insulating material 103 and the insulating material 105, (For example, in the temperature range of 350°C to 445°C) to sufficiently remove water, hydrogen, etc. This can prevent defect levels from being formed in the semiconductor 106b and the like. In this way, a highly reliable transistor can be provided.

[0287] In addition, when forming the insulator 106a and the semiconductor 106b, hydrogen, carbon, etc. When an etching gas containing impurities is used, the insulator 106a and the semiconductor 106b Impurities such as hydrogen and carbon may be trapped in the insulator 106a. Further, by performing a heat treatment after the formation of the semiconductor 106b, the semiconductor 106b is taken in during etching. Impurities such as hydrogen and carbon can be desorbed.

[0288] In addition, the above-mentioned high density plasma treatment may be performed instead of the heat treatment, or the upper surface may be treated with the high density plasma treatment after the heat treatment. The high density plasma treatment described above may be performed. Impurities such as hydrogen and carbon that have been incorporated can be released and oxygen vacancies can be filled with oxygen. do.

[0289] After the conductor 128 is formed, the insulator 126a, the semiconductor 126b, and the conductor 128 are The insulator 106a and the semiconductor 106b are processed together, and the semiconductor 106b overlaps with the insulator 106a. The conductor having a shape overlapping the semiconductor 106b is further processed to form a conductor. The conductive material 108a and the conductive material 108b may be formed.

[0290] Next, the insulator 126c is formed. The insulator 126c may be formed from an insulator or a semiconductor that can be used in various ways. The method can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Before the insulator 126c is formed, the semiconductor 106b, the conductor 108a, and the conductor The surface of the body 108b may be etched, for example, using a plasma containing a rare gas. After that, the insulator 126c is continuously etched without being exposed to the atmosphere. By forming the film, the semiconductor 106b, the conductors 108a and 108b, and the insulator The inclusion of impurities at the interface between the film and the film can be reduced. Impurities present in the film may be more diffusible than impurities in the film. By reducing the input, stable electrical characteristics can be imparted to the transistor.

[0291] Next, an insulator 132 is formed. The insulator 132 is the same as the insulator 112 described above. The insulator 132 can be formed by a sputtering method, a CV method, or the like. This can be done by using the D method, MBE method, PLD method, ALD method, etc. The deposition of the insulating layer 126c and the deposition of the insulating layer 132 are performed successively without exposure to the atmosphere. This can reduce the amount of impurities entering the film and at the interface.

[0292] Next, a conductor 134 is formed (see FIGS. 14(A) and 14(B)). The conductor 134 may be any conductor that can be used as the conductor 114. The film is formed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. The deposition of the insulator 132 and the deposition of the conductor 134 can be performed by exposing the insulator 132 and the conductor 134 to the atmosphere. By performing this process continuously without any additional steps, it is possible to reduce the inclusion of impurities in the film and at the interface. do.

[0293] Next, a resist or the like is formed on the conductor 134, and the resist or the like is used to process the conductor. The body 114 is formed.

[0294] Next, a resist or the like is formed on the conductor 114 and the insulator 132, and the resist or the like is used to The insulating film 106c and the insulating film 112 are formed by processing the insulating film 106c and the insulating film 112 (see FIGS. 14(C) and 14(D)). At this time, the conductors 120a and 120b to be formed later will overlap the conductors 108a and 108b. The insulators 106c and 112 are formed so as to expose the areas in contact with the conductor 108b. You may do so.

[0295] Next, the insulator 116 is formed (see FIGS. 14(E) and 14(F)). The insulator 116 can be formed using any of the above insulators. This can be carried out using a BE method, a PLD method, an ALD method, or the like.

[0296] Here, the insulator 116 is a material such as aluminum oxide that blocks oxygen, hydrogen, water, etc. It is preferable to provide an oxide insulating film having a blocking effect.

[0297] The insulator 116 is preferably formed by plasma deposition, for example, by sputtering. It is more preferable to carry out the process using a sputtering method in an atmosphere containing oxygen. is more preferable.

[0298] The sputtering method uses a direct current (DC) power supply for the sputtering power supply. Current sputtering method, and pulsed DC sputtering method, which applies a bias in a pulsed manner. RF (Radio Frequency) sputtering method, which uses a high frequency power supply for sputtering. A sputtering method may also be used. A magnetron having a magnet mechanism inside the chamber may also be used. bias sputtering, which applies voltage to the substrate during film formation; reactive A reactive sputtering method performed in a gas atmosphere may also be used. The oxygen gas flow rate and film formation power for sputtering may be adjusted depending on the amount of oxygen. The amount may be determined appropriately depending on the amount added, etc.

[0299] By forming the insulator 116 by sputtering, the insulator 116 is formed simultaneously with the film formation. The surface of the insulator 104 or the insulator 112 (after the insulator 116 is formed, it is insulated from the insulator 104 or the insulator 112) Oxygen is added to the vicinity of the interface of the insulating layer 116. Here, the oxygen is, for example, oxygen radicals. The oxygen is added to the insulator 104 or the insulator 112 as a Oxygen is not limited to the above. Oxygen can be used as an insulator 104 or an insulating material in the form of an oxygen atom or an oxygen ion. The addition of oxygen may cause the insulator 104 or the insulator 112 to deteriorate. In some cases, oxygen is contained in excess of the stoichiometric composition, and in this case, the oxygen is called excess oxygen. You can also do this.

[0300] Next, it is preferable to carry out a heat treatment (see FIGS. 15(A) and (B)). As a result, the oxygen added to the insulator 104 or the insulator 112 is diffused, and the insulators 106a and 106b are formed. The heat treatment can be performed at 250° C. or higher. The heat treatment may be carried out at 50°C or less, preferably 350°C or more and 450°C or less. atmosphere, or an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more The heat treatment may be carried out under reduced pressure. The heat treatment is carried out using an RTA device with lamp heating. can also be used.

[0301] The temperature of this heat treatment is preferably lower than that of the heat treatment performed after the formation of the semiconductor 126b. The temperature difference between the heat treatment after the semiconductor 126b deposition and the heat treatment after the semiconductor 126b deposition is 20°C or more and 150°C or less, preferably 4 The temperature is set to 0° C. or higher and 100° C. or lower. This allows excess oxygen (oxygen) to be released from the insulator 104 and the like. ) can be suppressed from being released. In the case where the heat treatment for the insulating layer 118 can be performed by the heat treatment for the insulating layer 118 during the film formation, In some cases, this may not be necessary (when equivalent heating is performed in the deposition of the film).

[0302] By this heat treatment, the insulator 116 is formed, and the insulators 104 and 112 The oxygen added thereto (hereinafter referred to as oxygen 186) is diffused into the insulator 104 or the insulator 112. The insulator 116 is the insulator 104 or the insulator 112. It is an insulator that is less permeable to oxygen and functions as a barrier film that blocks oxygen. Since the insulator 116 is formed on the insulator 104 or the insulator 112, the insulating Oxygen 186 diffusing through the body 104 or the insulator 112 is absorbed by the surface of the insulator 104 or the insulator 112. The insulator 104 or the insulator 112 does not diffuse in the horizontal direction, but diffuses mainly in the horizontal direction or downward direction.

[0303] The oxygen 186 diffusing through the insulator 104 or the insulator 112 is transferred to the insulators 106a and 112. At this time, the insulating layer 106c and the semiconductor 106b are provided with an oxygen blocking function. Since the insulating body 103 is provided under the insulating body 104, the insulating body 104 is not diffused into the insulating body 104. This can prevent oxygen 186 from diffusing into layers below the insulator 104 .

[0304] In this way, the insulator 106a, the insulator 106c and the semiconductor 106b, especially the semiconductor 106b, Oxygen 186 can be effectively supplied to the region where the channel is formed by O6b. In this way, oxygen is supplied to the insulator 106a, the insulator 106c, and the semiconductor 106b, and oxygen vacancies are eliminated. By reducing the density of the defect states, a high-purity intrinsic or substantially high-purity intrinsic oxide can be obtained. The semiconductor may be a nitride semiconductor.

[0305] The heat treatment after the formation of the insulator 116 may be performed at any time after the formation of the insulator 116. For example, this may be done after the formation of the insulator 118 or after the formation of the conductors 120a and 120b. You can go later.

[0306] Next, the insulator 118 is formed. The insulator 118 may be any of the above-described insulators. The insulator 118 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. This can be done using methods such as the

[0307] Next, a resist or the like is formed on the insulator 118, and the insulators 118, 116, and An opening is then formed in the conductor 120a and the insulator 106c. The conductors to be the conductors 120a and 120b are formed as follows: The conductive material can be formed by a sputtering method, a CVD method, or the like. This can be done using the MBE method, PLD method, ALD method, or the like.

[0308] Next, a resist or the like is formed on the conductor, and the conductor 12 is processed using the resist or the like. Then, a conductive layer 120a and a conductive layer 120b are formed (see FIGS. 15(C) and (D)).

[0309] Through the above steps, a transistor according to one embodiment of the present invention can be manufactured.

[0310] A manufacturing method of the transistor 29 will be described below with reference to FIGS. The transistor 29 may be manufactured by the same method as that described above. The law can be taken into consideration.

[0311] First, a substrate 100 is prepared. The substrate used for the substrate 100 may be any of the above-mentioned substrates. That's fine.

[0312] Next, the insulator 101 is formed. As the insulator 101, any of the above insulators may be used.

[0313] Next, an insulator film is formed to become the insulator 107. If the insulator described above is used as the insulator, The insulator film can be formed by sputtering, CVD, MBE, PLD, or ALD. This can be done using methods such as the

[0314] Next, a resist or the like is formed on the insulator, and the resist or the like is used to process the insulator, forming an opening. The insulating layer 107 is formed.

[0315] Next, a conductor that will become the conductor 102 is formed. The conductive material can be formed by a sputtering method, a CVD method, an MB method, etc. This can be carried out using the E method, PLD method, ALD method, or the like.

[0316] Next, the conductor is polished until the insulator 107 is exposed, forming the conductor 102 (FIG. 17). See (A) and (B).) Polishing can be performed by CMP processing or the like.

[0317] Next, the insulator 105 is formed. As the insulator 105, any of the above insulators may be used. The insulator 105 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In addition, the water or hydrogen contained in the insulator 105 can be reduced by For example, the film may be formed while the substrate is heated to reduce the When a semiconductor element layer is provided on the substrate, a relatively low temperature range (for example, 350°C or higher, 44°C or higher) is used. It may be heated to a temperature range of approximately 5°C or less.

[0318] In addition, by forming a film by the PECVD method using the same method as the insulator 104 described above, In addition, the water or hydrogen contained in the insulator 105 may be reduced.

[0319] Next, the insulator 103 is formed. As the insulator 103, any of the above insulators may be used. The insulator 103 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In addition, the water or hydrogen contained in the insulator 103 can be reduced by For example, the film may be formed while the substrate is heated to reduce the When a semiconductor element layer is provided on the substrate, a relatively low temperature range (for example, 350°C or higher, 44°C or higher) is used. It may be heated to a temperature range of approximately 5°C or less.

[0320] Next, the insulator 104 is formed (see FIGS. 17(C) and (D)). The insulator 104 may be formed using any of the above insulators. This can be carried out using a BE method, a PLD method, an ALD method, or the like.

[0321] In addition, it is preferable that the upper or lower surface of the semiconductor 106b to be formed later has high flatness. Therefore, the top surface of the insulator 104 is subjected to a planarization process such as CMP to improve the planarity. That's fine.

[0322] Next, a heat treatment is preferably carried out.

[0323] Next, an insulator that will become the insulator 106a is formed. An insulator or a semiconductor that can be used as a film may be used. It can be performed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. can.

[0324] Next, a semiconductor film is formed to become the semiconductor 106b. The semiconductor film may be formed by a sputtering method, This can be done by using a CVD method, an MBE method, a PLD method, an ALD method, or the like. By forming the insulating film and the semiconductor film consecutively without exposing them to the atmosphere, This can reduce the amount of impurities entering the interface.

[0325] Next, heat treatment is preferably performed. By the heat treatment, the insulator 105 and the insulator The water or hydrogen in the insulating material 103 and the insulating material 104 can be further reduced. In some cases, excess oxygen can be contained in the insulating layer 104. 650°C or less, preferably 450°C or more and 600°C or less, more preferably 520°C or more and 5 The heat treatment should be carried out at 70°C or below. The heat treatment should be carried out in an inert gas atmosphere or in an oxidizing gas atmosphere at 10ppm. The heat treatment is carried out in an atmosphere containing more than m, more than 1%, or more than 10%. Alternatively, the heat treatment may be carried out in an inert gas atmosphere, followed by a gas to replenish the desorbed oxygen. Therefore, heat treatment is performed in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. By the heat treatment, the insulator 106a and the semiconductor 106b are formed. It is possible to improve the crystallinity of semiconductors and remove impurities such as hydrogen and water. Heat treatment can also be performed using an RTA device that uses lamp heating. The process takes less time than a furnace, making it effective for increasing productivity.

[0326] In addition, when a semiconductor element layer is provided below the transistor 10, a relatively low temperature It can be heated in a range (for example, a temperature range of 350°C to 445°C). For example, any one of the substrate heating temperatures during the deposition of the insulators 105, 103, and 104 It is preferable that the heating temperature is equal to or lower than the highest heating temperature among the above.

[0327] Here, when the insulator 104 is formed, a silicon halide such as SiF4 is used. When the heat treatment is performed, halogens such as fluorine are contained in the insulator 104. The oxygen in the silicon dioxide is replaced by fluorine, and oxygen is released (SiO+F → SiF+O), forming an insulator 1 It can be inferred that the semiconductor is supplied to the insulator 106a and the semiconductor 106b. The mechanism is explained below.

[0328] <Fluorine-containing silicon oxide> Below, we will discuss silicon oxide containing fluorine, which is an example of an insulator containing excess oxygen. This will be explained using Figure 74.

[0329] Assume silicon oxide (SiO2) with two oxygen atoms per silicon atom. As shown in 74(A), one silicon atom is bonded to four oxygen atoms. One oxygen atom is bonded to two silicon atoms.

[0330] When two fluorine atoms enter silicon oxide, one bonded to two silicon atoms is broken down. The oxygen atom bond breaks (…Si-O-Si… + 2F → …Si- -O- -S i… + 2F). And, a fluorine atom, a silicon atom whose bond with an oxygen atom has been broken, bonds (…Si- -O- -Si… + 2F → …Si-F F-Si… + O). At this time, the oxygen atom that has broken the bond becomes excess oxygen (see Figure 74(B)).

[0331] The excess oxygen contained in silicon oxide can reduce oxygen vacancies in the oxide semiconductor. Oxygen vacancies in oxide semiconductors can become hole traps. When the semiconductor device has excess oxygen, stable electrical characteristics can be imparted to the transistor.

[0332] In this way, excess oxygen is generated when fluorine enters silicon oxide. When excess oxygen is consumed by reducing oxygen vacancies in an oxide semiconductor, silicon oxide There will be less oxygen in the air than before the fluorine was introduced.

[0333] To give the transistor stable electrical characteristics and bring them closer to those of a normally-off transistor To achieve this, a sufficient amount of excess oxygen is required.

[0334] <About heat treatment> Here, referring to Figure 75, we will explain the furnace control method that can be used when performing heat treatment. The atmosphere of the heat treatment used in the description is an example, and may be changed as appropriate. stomach.

[0335] Figure 75(A) shows an example in which the heat treatment was carried out twice by switching the atmosphere. Put the material to be treated into the furnace. Next, put nitrogen gas into the furnace and heat it up to the first temperature. Then, heat it up to the second temperature. The temperature is increased in one hour. Then, the temperature is maintained at the second temperature for one hour. Then, the temperature is increased to the third temperature in one hour. The temperature is then lowered. Next, nitrogen gas and oxygen gas are introduced into the furnace. Next, the furnace is maintained at the third temperature for 1 hour. Next, the temperature is increased to the fourth temperature in one hour. Then, the fourth temperature is maintained for one hour. Then, the temperature is decreased to the fifth temperature over one hour. Next, the object to be treated is removed from the furnace.

[0336] The first temperature, the third temperature, and the fifth temperature are temperatures at which the object to be treated can be put in and taken out. The first temperature, the third temperature, and the fifth temperature are in the range (for example, 50°C or more and 200°C or less). If the temperature is too low, it may take a long time to cool down, which may result in lower productivity. In addition, if the first temperature and the fifth temperature are too high, the object to be treated may be damaged when it is put in or taken out. The second temperature and the fourth temperature are determined based on the respective atmospheres. The maximum temperature of the heat treatment (for example, 250°C or higher and 650°C or lower) is used herein. When the time for heat treatment is stated, it is the time when the sample was held at the maximum temperature in each atmosphere. Indicates the time.

[0337] In the method shown in Figure 75(A), when heat treatment is performed in two atmospheres for one hour each, It takes a total of 7 hours.

[0338] Figure 75(B) shows an example of a single heat treatment without changing the atmosphere. Next, clean dry air (CDA) is introduced into the furnace. CDA is a food grade food that contains less than 20 ppm of water, less than 1 ppm of water, or The air is 10 ppb or less. Then, the temperature is raised to the seventh temperature in one hour. The temperature is then lowered to the eighth temperature in one hour. Take it out.

[0339] The sixth and eighth temperatures are within a temperature range in which the workpiece can be taken in and out. The seventh temperature is the maximum temperature of the heat treatment in each atmosphere.

[0340] In the method shown in FIG. 75(B), when heat treatment is performed for two hours in one atmosphere, the total It turns out it takes 4 hours.

[0341] Figure 75(C) shows an example of a single heat treatment performed by switching the atmosphere. Next, nitrogen gas is introduced into the furnace and the temperature is raised to the ninth temperature. The temperature is raised to 100°C for 1 hour. Then, the temperature is maintained at 100°C for 1 hour. Next, CDA is placed in the furnace. Next, the temperature is maintained at the 10th temperature for 1 hour. Then, the temperature is lowered to the 11th temperature over 1 hour. Then, the workpiece is removed from the furnace.

[0342] The ninth and eleventh temperatures are within the temperature range in which the object to be treated can be put in and taken out. The tenth temperature is the maximum temperature of the heat treatment in each atmosphere.

[0343] In the method shown in FIG. 75(C), when heat treatment is performed for two hours in two atmospheres, the total It turns out it takes 4 hours.

[0344] By carrying out the heat treatment as shown in Fig. 75(B) and Fig. 75(C), As a result, the heat treatment time can be shortened compared to 75(A). It can increase the sexiness.

[0345] Next, a resist or the like is formed on the semiconductor, and the resist or the like is used to process the semiconductor, and an insulator 10 6a and semiconductor 106b are formed (see FIGS. 17(E) and (F)).

[0346] Next, heat treatment is preferably performed. By the heat treatment, the insulator 105 and the insulator The water or hydrogen in the insulating material 103 and the insulating material 104 can be further reduced. In some cases, excess oxygen can be contained in the insulating layer 104. 650°C or less, preferably 450°C or more and 600°C or less, more preferably 520°C or more and 5 The heat treatment should be carried out at 70°C or below. The heat treatment should be carried out in an inert gas atmosphere or in an oxidizing gas atmosphere at 10ppm. The heat treatment is carried out in an atmosphere containing more than m, more than 1%, or more than 10%. Alternatively, the heat treatment may be carried out in an inert gas atmosphere, followed by a gas to replenish the desorbed oxygen. Therefore, heat treatment is performed in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. By the heat treatment, the insulator 106a and the semiconductor 106b are formed. It is possible to improve the crystallinity of semiconductors and remove impurities such as hydrogen and water. Heat treatment can also be performed using an RTA device that uses lamp heating. The process takes less time than a furnace, making it effective for increasing productivity.

[0347] In addition, when a semiconductor element layer is provided below the transistor 10, a relatively low temperature It can be heated in a range (for example, a temperature range of 350°C to 445°C). For example, any one of the substrate heating temperatures during the deposition of the insulators 105, 103, and 104 It is preferable that the heating temperature is equal to or lower than the highest heating temperature among the above.

[0348] Next, the insulator 106c is formed (see FIGS. 17(G) and (H)). In this case, an insulator or a semiconductor that can be used as the insulator 106c may be used. The insulator 106c can be formed by sputtering, CVD, MBE, or PLD. , ALD method, etc.

[0349] Next, a conductor that will become the conductor 108a and the conductor 108b is formed. Any conductor that can be used as the conductor 108a and the conductor 108b described above may be used. Conductive films are formed by sputtering, CVD, MBE, PLD, or ALD methods. This can be done using, for example.

[0350] In addition, the semiconductor 106b and the insulator 106c are electrically conductive to form the conductor 108. In the nearby area, a low resistance region 109 may be formed.

[0351] Next, a resist or the like is formed on the conductor, and the conductor 10 is processed using the resist or the like. Form 8.

[0352] Next, the insulator 113 that will become the insulator 110 is formed. The insulator 113 may be formed by a method such as sputtering. This can be done using methods such as CVD, MBE, PLD, and ALD. Cut.

[0353] When the insulator 113 is formed, the upper surface and a part of the side surface of the conductor 108 are oxidized, and the metal oxide In some cases, an object 111 may be formed (see FIGS. 18(A) and (B)).

[0354] Next, a resist or the like is formed on the insulator 113, and the resist or the like is used to process the insulator. The conductive material 110, the metal oxide 111a, the metal oxide 111b, the conductive material 108a, and the conductive material 10 8b is formed (see Figures 18(C) and (D)).

[0355] Next, a high-density plasma treatment may be performed in an oxygen atmosphere. The oxygen atmosphere is a gas atmosphere containing oxygen atoms, and is preferably oxygen, ozone, or Nitrogen oxides (nitric oxide, nitrogen dioxide, dinitrogen monoxide, dinitrogen trioxide, dinitrogen tetroxide, pentoxide) In addition, in an oxygen atmosphere, nitrogen or rare gas (helix, etc.) Inert gases such as ammonium, argon, etc. may be included. By performing plasma treatment, for example, carbon, hydrogen, etc. can be desorbed. In addition, by performing high-density plasma treatment in an oxygen atmosphere, hydrocarbons and other substances can be removed from the object to be treated. Organic compounds are also easily desorbed.

[0356] Annealing may be performed before or after the high-density plasma treatment. To increase the intensity, it may be preferable to flow a sufficient amount of gas. If the reaction time is not long enough, the deactivation rate of radicals may be faster than the rate of radical generation. When a flow rate of 100sccm or more, 300sccm or more, or 800sccm or more is preferable There is.

[0357] High density plasma processing is performed using a frequency of, for example, 0.3 GHz or more and 3.0 GHz or less, 0.7G Hz or higher and 1.1GHz or lower, or 2.2GHz or higher and 2.8GHz or lower (typically 2. Microwaves generated using a high frequency generator (45 GHz) can be used. The pressure is set to 10 Pa or more and 5000 Pa or less, preferably 200 Pa or more and 1500 Pa or less, More preferably, the pressure is 300 Pa or more and 1000 Pa or less, and the substrate temperature is 100° C. or more and 600° C. or less. (typically 400° C.) and using a mixed gas of oxygen and argon.

[0358] High density plasma is generated by using microwaves of, for example, 2.45 GHz. , electron density is 1×10 11 / cm 3 More than 1×10 13 / cm 3 Below, the electron temperature is 2eV or less. It is preferable that the ion energy is 5 eV or less. The kinetic energy of radicals in plasma treatment is small, and plasma treatment is more effective than conventional plasma treatment. This reduces damage caused by the micro-defects. The distance from the antenna generating the wave to the object to be treated is 5 mm or more and 120 mm or less, preferably It is recommended to set it to between 20mm and 60mm.

[0359] Alternatively, a plasma that applies an RF (Radio Frequency) bias to the substrate side can be used. The RF bias frequency may be, for example, 13.56 MHz or 27. By using high density plasma, high density oxygen ions can be generated. By applying an RF bias to the substrate, high-density plasma is generated. The generated oxygen ions can be efficiently guided to the object to be treated. Oxygen ions can be efficiently guided to the inside of the opening. It is preferable to perform the high-density plasma treatment while applying a voltage of 0.1 V to the plasma.

[0360] In addition, after the high-density plasma treatment, annealing was performed without exposure to the atmosphere. Furthermore, the high density plasma treatment may be performed continuously after the annealing treatment without exposing the substrate to the atmosphere. By performing the high density plasma treatment and the annealing treatment successively, This prevents impurities from being mixed in during the process. After the annealing treatment, the oxygen added to the object is removed by the annealing treatment. In this way, unnecessary oxygen that was not used to compensate for the oxygen vacancies can be desorbed. The annealing process may be performed by, for example, lamp annealing.

[0361] The treatment time for high-density plasma treatment is 30 seconds or more and 120 minutes or less, and 1 minute or more and 90 minutes or less. Preferably, the time is between 2 and 30 minutes, or between 3 and 15 minutes.

[0362] Annealing is performed at temperatures between 250°C and 800°C, between 300°C and 700°C, or Treatment times between 400°C and 600°C are between 30 seconds and 120 minutes, and between 1 minute and 90 minutes. , and it is preferable that the time is 2 minutes or more and 30 minutes or less, or 3 minutes or more and 15 minutes or less.

[0363] By performing high density plasma treatment and / or annealing treatment, the semiconductor 106b It is possible to reduce the defect level in the region that will become the channel formation region. At this time, a part of the low resistance region 109 is also made high resistance. , the conductors 108a and 108b are separated into low resistance regions 109a and 109b. Metal oxide 111a and metal oxide 111b are formed on the side surfaces of conductor 108b and conductor 108c. (See Figures 18(E) and 18(F)).

[0364] Next, an insulator 132 is formed. The insulator 132 is the same as the insulator 112 described above. The insulator 132 can be formed by a sputtering method, a CV method, or the like. This can be done by using the D method, MBE method, PLD method, ALD method, etc. The deposition of the insulating layer 126c and the deposition of the insulating layer 132 are performed successively without exposure to the atmosphere. This can reduce the amount of impurities entering the film and at the interface.

[0365] Next, a conductor 134 is formed (see FIGS. 19(A) and (B)). The conductor 134 may be any conductor that can be used as the conductor 114. The film is formed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. The deposition of the insulator 132 and the deposition of the conductor 134 can be performed by exposing the insulator 132 and the conductor 134 to the atmosphere. By performing this process continuously without any additional steps, it is possible to reduce the inclusion of impurities in the film and at the interface. do.

[0366] Next, the conductor 134, the insulator 132, and the insulator 113 are removed until the insulator 113 is exposed. By polishing, the conductor 114, the insulator 112, and the insulator 110 are formed (FIG. 19). (See (C) and (D).) The conductor 114 and the insulator 112 are transistors 29 The conductive layer functions as a gate electrode and a gate insulator. 114 and insulator 112 can be formed in a self-aligned manner.

[0367] Next, the insulator 116 is formed (see FIGS. 19(E) and (F)). The insulator 116 can be formed using any of the above insulators. This can be carried out using a BE method, a PLD method, an ALD method, or the like.

[0368] Next, a heat treatment is preferably carried out.

[0369] Through the above steps, a transistor according to one embodiment of the present invention can be manufactured.

[0370] By manufacturing a transistor by the method described in this embodiment, the semiconductor 106b This can prevent water, hydrogen, etc. from being supplied to the Alternatively, a transistor having a low leakage current when non-conducting can be provided. Alternatively, a small transistor having normally-off electrical characteristics can be provided. Alternatively, a transistor having a small subthreshold swing value can be provided. It is possible to provide a highly reliable transistor. This can be done.

[0371] Furthermore, by manufacturing a transistor by the method described in this embodiment, The heat treatment in the low temperature range suppresses the supply of water, hydrogen, etc. to the semiconductor 106b, etc. Therefore, a semiconductor element layer or a wiring layer, etc., can be formed in the layer below the transistor. Even if a semiconductor device is formed, the transistor can be manufactured without being deteriorated at high temperatures. Cut.

[0372] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0373] (Embodiment 3) <Manufacturing equipment> A manufacturing apparatus for performing high-density plasma processing according to one embodiment of the present invention will be described below. .

[0374] First, let us look at the configuration of manufacturing equipment that minimizes the inclusion of impurities during the manufacture of semiconductor devices, etc. (Fig. 2). 0, and will be explained using Figures 21 and 22.

[0375] FIG. 20 is a schematic top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing equipment 2700 includes a cassette port 2761 for accommodating substrates and a substrate alignment unit. and an atmosphere-side substrate supply chamber 2701 having an alignment port 2762 for performing the alignment. The substrate supply chamber 2701 is connected to the atmospheric substrate transfer chamber 2702, which transfers the substrate. and a load lock chamber in which the pressure inside the chamber is switched from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure. 2703a, and the substrate is removed, and the pressure in the chamber is reduced to atmospheric pressure, or atmospheric pressure to atmospheric pressure. The unload lock chamber 2703b is switched to a reduced pressure, and the transfer chamber 2703b transfers the substrate in a vacuum. 704, chamber 2706a, chamber 2706b, and chamber 2706c. , and chamber 2706d.

[0376] The atmospheric substrate transfer chamber 2702 is provided with a load lock chamber 2703a and an unload lock chamber 2703b. The load lock chamber 2703a and the unload lock chamber 2703b are connected to the 3b is connected to a transfer chamber 2704, which is connected to a chamber 2706a, a chamber Bar 2706b connects chamber 2706c and chamber 2706d.

[0377] A gate valve GV is provided at the connection between each chamber, and the atmosphere-side substrate supply chamber 270 1 and the atmosphere side substrate transfer chamber 2702, each chamber can be independently maintained in a vacuum state. In addition, a transfer robot 2763a is provided in the atmospheric substrate transfer chamber 2702. The transfer room 2704 is provided with a transfer robot 2763b. and a transfer robot 2763b, which can transfer substrates within the manufacturing equipment 2700. do.

[0378] The back pressure (total pressure) of the transfer chamber 2704 and each of the chambers 2706a to 2706d is, for example, 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, more preferably 1 × 1 0 -5 The pressure in the transfer chamber 2704 and each of the chambers 2706a to 2706b is set to be equal to or less than Pa. The partial pressure of a gas molecule (atom) with a mass-to-charge ratio (m / z) of 18 is, for example, 3 × 10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa In addition, the m / z of the transfer chamber 2704 and each of the chambers 2706a to 2706d is The partial pressure of a gas molecule (atom) with a mass of 28 is, for example, 3 x 10 -5 Pa or less, preferably 1 x10 -5 Pa or less, more preferably 3×10 -6 Pa or less. 04 and gas molecules (atoms) with m / z of 44 in each of chambers 2706a to 2706d. ) partial pressure is, for example, 3 × 10 -5 Pa or less, preferably 1×10 -5 Pa or less, and Preferably 3 x 10 -6 Pa or less.

[0379] The total pressure and distribution in the transfer chamber 2704 and each of the chambers 2706a to 2706d are The pressure can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer manufactured by ULVAC, Inc. A Qulee CGM-051 mass spectrometer (also called Q-mass) can be used.

[0380] In addition, the transfer chamber 2704 and each of the chambers 2706a to 2706d are designed to prevent external leaks. For example, the transfer chamber 2704 and each chamber are preferably configured to have a small internal leak. The leak rate of chambers 2706a to 2706d is 3 x 10 -6 Pa·m 3 / s or less , preferably 1 x 10 -6 Pa·m 3 / s or less. For example, if the m / z is 18, The leak rate of gas molecules (atoms) is 1×10 -7 Pa·m 3 / s or less, preferably 3x 10 -8 Pa·m 3 / s or less. For example, a gas molecule (atom) with m / z of 28 ) leak rate is 1×10 -5 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 44 is is 3 x 10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less .

[0381] The leak rate was calculated from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on the external leak and the internal leak. The problem is that gas enters from outside the vacuum system due to a small hole or poor sealing. Leaks occur due to leakage from partitions such as valves in the vacuum system or gas released from internal components. To keep the leak rate below the above-mentioned value, both external and internal leaks are considered. It is necessary to take measures from

[0382] For example, the opening and closing parts of the transfer chamber 2704 and each of the chambers 2706a to 2706d are metal. It is recommended to seal with a metal gasket. Metal gaskets are made of iron fluoride and aluminum oxide. It is preferable to use a metal gasket coated with chromium oxide. It has a higher adhesion than a ring and can reduce external leakage. Metal gaskets are made of metals that are passivated by coating them with chrome or chromium oxide. This suppresses the release of gas containing impurities from the semiconductor device, thereby reducing internal leakage.

[0383] In addition, the components constituting the manufacturing equipment 2700 are made of aluminum, which emits less gas containing impurities. The alloys used are aluminum, chromium, titanium, zirconium, nickel, or vanadium. The above-mentioned members may be used by being coated with an alloy containing iron, chromium, or nickel. Alloys containing titanium or nickel are rigid, heat resistant, and easy to process. Therefore, if the surface irregularities of the component are reduced by polishing or the like to reduce the surface area, Gas emissions can be reduced.

[0384] Alternatively, the components of the manufacturing apparatus 2700 may be made of iron fluoride, aluminum oxide, chromium oxide, etc. It may be coated with, for example.

[0385] It is preferable that the components of the manufacturing apparatus 2700 are made of metal only, for example, quartz. When installing a viewing window made of iron fluoride, the surface is coated with iron fluoride to suppress gas emissions. It is recommended to coat it thinly with aluminum oxide or chromium oxide.

[0386] The adsorbed substances present in the transfer chamber 2704 and each of the chambers 2706a to 2706d are Because they are attached to the walls, the transfer chamber 2704 and each chamber 2706a to 2706 d, but does not affect the pressure in the transfer chamber 2704 and each of the chambers 2706a to 2706d. This causes gas emission when pumping. Therefore, there is no correlation between the leak rate and the pumping speed. However, using a pump with high exhaust capacity, the transfer chamber 2704 and each chamber 2706a It is important to desorb as much of the adsorbed matter as possible from 2706d and evacuate it in advance. In order to promote the desorption of adsorbed substances, the transfer chamber 2704 and each chamber 270 6a to 6d may be baked. By baking, the desorption rate of the adsorbed substance can be increased. It can be made about 10 times larger. Baking should be done at a temperature between 100℃ and 450℃. At this time, an inert gas is supplied to the transfer chamber 2704 and each of the chambers 2706a to 2706c. d) to remove adsorbed substances, the desorption rate of water, which is difficult to desorb by evacuation alone, is increased. The temperature of the inert gas introduced can be increased to the same temperature as the baking temperature. The desorption rate of the adsorbed substances can be further increased by heating the adsorbed substances to about 1000 kJ / min. It is preferable to use a rare gas as the gas source.

[0387] Alternatively, an inert gas such as a heated rare gas or oxygen may be introduced into the transfer chamber 27. 04 and the pressure in each chamber 2706a to 2706d is increased, and after a certain time has passed, The transfer chamber 2704 and each of the chambers 2706a to 2706d are evacuated. By introducing heated gas, the transfer chamber 2704 and each of the chambers 2706a to The adsorbed substances in the transport chamber 2704 and each chamber 27 can be desorbed. This process can reduce impurities present in the 2706a to 2706d. It is effective to repeat the treatment in the range of 5 to 15 times, preferably 10 to 30 times. Specifically, the temperature is 40°C or higher and 400°C or lower, preferably 50°C or higher and 200°C or lower. By introducing an inert gas or oxygen, etc., the transfer chamber 2704 and each chamber 270 The pressure in 6a to 2706d is set to 0.1 Pa or more and 10 kPa or less, preferably 1 Pa or more and 1 kPa or less, more preferably 5 Pa to 100 Pa, and the pressure should be maintained for 1 minute or more. The time is set to 300 minutes or less, preferably 5 minutes or more and 120 minutes or less. 4 and each of the chambers 2706a to 2706d for 5 minutes or more and 300 minutes or less, preferably 1 The exhaust is performed for a period of 0 to 120 minutes.

[0388] Next, the chamber 2706b and the chamber 2706c are shown in the cross-sectional diagram of FIG. This will be explained using a diagram.

[0389] The chambers 2706b and 2706c are, for example, a chamber for providing a high density plastic to the object to be treated. This is a chamber where Zuma processing can be performed. The only difference between the bar 2706c and the bar 2706d is the atmosphere in which the high density plasma treatment is performed. Since these configurations are common to both, they will be explained together below.

[0390] Chamber 2706b and chamber 2706c are connected to a slot antenna plate 2808. , a dielectric plate 2809, a substrate stage 2812, and an exhaust port 2819. Outside the chamber 2706b and the chamber 2706c, a gas supply source 2801 and , a valve 2802, a high frequency generator 2803, a waveguide 2804, and a mode converter 280 5, a gas pipe 2806, a waveguide 2807, a matching box 2815, and a high frequency A source 2816, a vacuum pump 2817, and a valve 2818 are provided.

[0391] The high frequency generator 2803 is connected to the mode converter 2805 via the waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is placed in contact with the dielectric plate 2809. The gas supply source 2801 is connected to a mode converter 2805 via a valve 2802. Then, the gas passing through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809 Pipe 2806 delivers gas to chamber 2706b and chamber 2706c. The vacuum pump 2817 also supplies the chamber with air via a valve 2818 and an exhaust port 2819. It has the function of exhausting gases and the like from the member 2706b and the chamber 2706c. The high frequency power supply 2816 is connected to the substrate stage 2812 via a matching box 2815. is connected to.

[0392] The substrate stage 2812 has a function of holding the substrate 2811. For example, 1 by electrostatic chuck or mechanical chuck. It also functions as an electrode to which power is supplied from the inside. , has the function of heating the substrate 2811 .

[0393] Examples of vacuum pumps 2817 include dry pumps, mechanical booster pumps, Ion pump, titanium sublimation pump, cryopump or turbomolecular pump In addition to the vacuum pump 2817, a cryotrap can be used. Water can be efficiently pumped out by using a cryopump and a cryotrap. This is particularly preferred.

[0394] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like. Alternatively, heat can be transferred by heat conduction or heat radiation from a medium such as a heated gas, as follows: For example, a GRTA (Gas Rapid Therma) l Annealing) or LRTA (Lamp Rapid Thermal Annealing) RTA (Rapid Thermal Annealing) GRTA uses high-temperature gases for heat treatment. An inert gas is used.

[0395] The gas supply source 2801 is connected to a refiner via a mass flow controller. The gas used has a dew point of -80°C or less, preferably -100°C or less. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) are preferably used. Just use it.

[0396] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide (aluminum), or the like. The dielectric plate 28 may be made of yttrium oxide (yttria) or yttrium oxide (yttria). Another protective layer may be formed on the surface of the substrate 9. The protective layer may be a layer of magnesium oxide. Sium, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, Silicon oxide, aluminum oxide, yttrium oxide, or the like may be used. 2809 is exposed to a particularly high density region of the high density plasma 2810 described later. Therefore, providing a protective layer can mitigate damage. This can suppress the increase in the number of

[0397] The high frequency generator 2803 can be used for frequencies in the range of 0.3 GHz to 3.0 GHz, for example, 0.7 GHz. Generates microwaves between 1.1GHz and 2.2GHz, or between 2.8GHz and 2.2GHz. The microwave generated by the high frequency generator 2803 is guided through the waveguide 2804. The mode converter 2805 converts the TE mode The transmitted microwaves are converted into TEM mode. Then, the microwaves pass through the waveguide 280 7 to the slot antenna plate 2808. The slot antenna plate 2808 has a plurality of The microwave passes through the slot holes and the dielectric plate 2809. Then, an electric field is generated below the dielectric plate 2809, and a high density plasma 2810 is generated. The high density plasma 2810 can be generated by the gas supply source 2801. There are ions and radicals depending on the gas species used. For example, oxygen radicals or nitrogen radicals There are also other types such as dichlorvos.

[0398] At this time, the ions and radicals generated by the high density plasma 2810 The film on the substrate 2811 can be modified. It may be preferable to apply a bias to the 2811 side. For example, RF (Radio Frequency) signals with frequencies such as 13.56MHz and 27.12MHz. By applying a bias to the substrate side, high density plasma2 The ions in 810 can be efficiently transported to the depths of the openings in the film on the substrate 2811. can.

[0399] For example, in the chamber 2706b, oxygen is introduced from the gas supply source 2801 to The oxygen radical treatment was carried out using high density plasma 2810, and the gas Nitrogen radicals were generated using high density plasma 2810 by introducing nitrogen from a gas supply source 2801. Processing can be performed.

[0400] Next, the chamber 2706a and the chamber 2706d are shown in cross-sectional view in FIG. This will be explained using a diagram.

[0401] The chambers 2706a and 2706d are used for, for example, irradiating the object to be treated with electromagnetic waves. It is possible to perform a shot in this chamber. The only difference between this and 706d is the type of electromagnetic wave. Because there are many parts, we will explain them together below.

[0402] Chamber 2706a and chamber 2706d may contain one or more lamps 2820 , a substrate stage 2825, a gas inlet 2823, and an exhaust port 2830. In addition, outside the chamber 2706a and the chamber 2706d, a gas supply source 282 1, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0403] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822 . The vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. The substrate stage 2820 is disposed opposite the substrate stage 2825. The substrate stage 2825 has a function of holding the substrate 2824. It has a heating mechanism 2826 and has the function of heating the substrate 2824 .

[0404] The lamp 2820 has a function of emitting electromagnetic waves such as visible light or ultraviolet light. For example, a light source having a wavelength of 10 nm or more and 2500 nm or less, or 500 nm or less Emits electromagnetic waves with a peak between 2000 nm and 40 nm or between 340 nm and 400 nm. A light source having this function may be used.

[0405] For example, the lamp 2820 may be a halogen lamp, a metal halide lamp, or a xenon lamp. Arc lamps, carbon arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps A light source of this type may be used.

[0406] For example, the electromagnetic waves emitted from the lamp 2820 may be partially or completely transmitted to the substrate 2824. By being absorbed by the substrate 2824, the film on the substrate 2824 can be modified. For example, It is possible to form or reduce impurities, or remove impurities. When this is done, defects can be efficiently generated or reduced, or impurities can be removed.

[0407] Alternatively, for example, the substrate stage 282 may be heated by electromagnetic waves emitted from the lamp 2820. 5 may be heated to heat the substrate 2824. In this case, the inside of the substrate stage 2825 The heating mechanism 2826 may not be included.

[0408] For the vacuum pump 2828, please refer to the description of the vacuum pump 2817. The mechanism 2826 is described with reference to the description of the heating mechanism 2813. Please refer to the description of the gas supply source 2801.

[0409] By using the above manufacturing equipment, it is possible to suppress the inclusion of impurities in the processed object while improving the film quality. This makes it possible to:

[0410] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0411] (Fourth embodiment) In this embodiment, a semiconductor device using a transistor according to one embodiment of the present invention will be described. An example of the circuit of the device will be described. <Circuit> An example of a circuit of a semiconductor device using a transistor according to one embodiment of the present invention will be described below. This article explains:

[0412] <CMOSインバータ> The circuit diagram shown in FIG. 23A includes a p-channel transistor 2200 and an n-channel transistor The transistors 2100 are connected in series and the gates of the transistors are connected together. The configuration of the OS inverter is shown.

[0413] <Structure of semiconductor device> 24 is a cross-sectional view of the semiconductor device corresponding to FIG. 23(A). The device includes a transistor 2200 and a transistor 2100. The transistor 2100 is disposed above the transistor 2200. 9A and 9B is used as an example, but the present invention The semiconductor device according to one aspect is not limited to this. The transistor described above can be used as the transistor 2100. For the transistor 2100, the above description of the transistor may be referred to as appropriate.

[0414] The transistor 2200 shown in FIG. 24 is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472a in the semiconductor substrate 450 and a region 472b in the semiconductor substrate 450. The region 472b includes an insulator 462 and a conductor 454.

[0415] In transistor 2200, regions 472a and 472b are source and drain regions. The insulator 462 also functions as a gate insulator. The conductor 454 also functions as a gate electrode. The resistance of the channel forming region can be controlled by the potential applied to the electrode 454 . That is, the potential applied to the conductor 454 causes conduction between the region 472a and the region 472b. Non-conduction can be controlled.

[0416] The semiconductor substrate 450 may be, for example, a single semiconductor substrate such as silicon or germanium. or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide A semiconductor substrate such as lead or gallium oxide may be used. Preferably, the semiconductor substrate 450 A single crystal silicon substrate is used as the substrate.

[0417] The semiconductor substrate 450 is a semiconductor substrate containing impurities that impart n-type conductivity. However, a semiconductor substrate having impurities that impart p-type conductivity is used as the semiconductor substrate 450. In that case, the region that will become the transistor 2200 is given n-type conductivity. Alternatively, if the semiconductor substrate 450 is an i-type, It's okay.

[0418] The upper surface of the semiconductor substrate 450 preferably has a (110) surface. The on-state characteristics of the transistor 2200 can be improved.

[0419] The regions 472a and 472b are regions containing impurities that impart p-type conductivity. In this way, the transistor 2200 constitutes a p-channel transistor.

[0420] Note that the transistor 2200 is separated from adjacent transistors by a region 460 or the like. The region 460 is an insulating region.

[0421] The semiconductor device shown in FIG. 24 includes an insulator 464, an insulator 466, an insulator 468, and a conductive Conductor 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478 b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 49 6c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, Insulator 489, insulator 490, insulator 491, insulator 492, insulator 493, and an insulator 494.

[0422] The insulator 464 is disposed on the transistor 2200. The insulator 466 is disposed on the 464. Insulator 468 is disposed on insulator 466. Insulator 489 is disposed on the insulator 468. Also, the transistor 2100 is disposed on the insulator 489. The insulator 493 is disposed on the transistor 2100. 494 is disposed on the insulator 493 .

[0423] The insulator 464 has an opening that reaches the region 472a, an opening that reaches the region 472b, and a conductive The openings also include openings that reach the conductors 480a and 454. The conductor 480b or the conductor 480c is embedded.

[0424] Insulator 466 also has an opening that reaches conductor 480a and an opening that reaches conductor 480b. The openings each have a mouth and an opening that reaches the conductor 480c. The conductive body 478a, the conductive body 478b, or the conductive body 478c is embedded therein.

[0425] Insulator 468 also has an opening that reaches conductor 478b and an opening that reaches conductor 478c. The openings each have a conductor 476a or a conductor 476b. It is embedded.

[0426] The insulator 489 has an opening overlapping with a channel formation region of the transistor 2100 and It has an opening that reaches the conductor 476a and an opening that reaches the conductor 476b. The openings are filled with a conductor 474a, a conductor 474b, or a conductor 474c. It is being done.

[0427] The conductor 474a may function as the gate electrode of the transistor 2100. Alternatively, for example, applying a constant potential to the conductor 474a can turn on the transistor 21. The electrical properties of the conductor 47 may be controlled, such as the threshold voltage of the conductor 47. 4a and the conductor 504 that functions as the gate electrode of the transistor 2100 are electrically connected. This increases the on-state current of the transistor 2100. In addition, since the punch-through phenomenon can be suppressed, the transistor 21 The electrical characteristics in the saturated region of 00 can be stabilized. Since this corresponds to the conductor 102 in the embodiment, please refer to the description of the conductor 102 for details. It is possible.

[0428] Insulator 490 also has an opening that reaches conductor 474b and an opening that reaches conductor 474c. The insulator 490 corresponds to the insulator 103 in the above embodiment. For details, the description of the insulator 103 can be referred to. As shown in FIG. 1, an insulator 490 is placed over the conductors 474a to 474c except for the openings. By providing the insulating material 491, the conductors 474a to 474c can extract oxygen from the insulating material 491. This prevents the oxide semiconductor of the transistor 2100 from being exposed to the insulator 491. It can provide oxygen to the body effectively.

[0429] The insulator 491 has an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. The insulator 491 corresponds to the insulator 104 in the above embodiment. For details, the description of the insulator 104 can be referred to.

[0430] As shown in the above embodiment, by reducing the water and hydrogen content of the insulator 491, Therefore, formation of defect states in the oxide semiconductor of the transistor 2100 can be suppressed. This allows the electrical characteristics of the transistor 2100 to be stabilized.

[0431] In addition, such an insulator with reduced water and hydrogen can be used not only for the insulator 491 but also for other insulators. For example, insulator 466, insulator 468, insulator 489, and insulator 493 It may also be used in the following cases.

[0432] 24, the insulator 105 and the insulator 101 in the transistor 20 are Although the corresponding insulators are not shown, they may be provided. An insulator equivalent to the insulator 101 may be provided between the insulator 468 and the insulator 489. An insulator equivalent to the insulator 105 may be provided between the edge 489 and the insulator 490. Between the insulators 468 and 489, there is a material equivalent to the insulator 101 that blocks water, hydrogen, etc. The insulator 491 is provided with a function of reducing the water and hydrogen content as described above. This further suppresses the formation of defect states in the oxide semiconductor of the transistor 2100. It can be controlled.

[0433] The insulator 492 is also connected to one of the source and drain electrodes of the transistor 2100. An opening through conductor 516b, which is the transistor 210, to conductor 474b. An opening that reaches the conductor 516a, which is the other of the source electrode or drain electrode of 0, and An opening reaching the conductor 504, which is the gate electrode of the transistor 2100, and an opening reaching the conductor 474c The insulator 492 corresponds to the insulator 116 in the above embodiment. Therefore, the description of the insulator 116 can be referred to for details.

[0434] The insulator 493 is connected to one of the source and drain electrodes of the transistor 2100. An opening through conductor 516b, which is the transistor 210, to conductor 474b. An opening that reaches the conductor 516a, which is the other of the source electrode or drain electrode of 0, and An opening reaching the conductor 504, which is the gate electrode of the transistor 2100, and an opening reaching the conductor 474c The openings are provided with a conductor 496a and a conductor 496b. b, the conductor 496c or the conductor 496d is embedded. The portion may also be connected through an opening in any of the components, such as the transistor 2100. There is a match.

[0435] The insulator 494 also has an opening that reaches the conductor 496a and an opening that reaches the conductor 496b and the conductor The opening extends to the conductive body 496d and the opening extends to the conductive body 496c. The conductive body 498a, the conductive body 498b, and the conductive body 498c are embedded in the respective portions. There are.

[0436] Insulator 464, insulator 466, insulator 468, insulator 489, insulator 493 and insulator The body 494 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Nitride, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, di a single layer of an insulator containing zinc, lanthanum, neodymium, hafnium or tantalum; Alternatively, they may be used in a laminated state.

[0437] Insulator 464, Insulator 466, Insulator 468, Insulator 489, Insulator 493 or Insulator At least one of the bodies 494 is made of an insulator that has the function of blocking impurities such as hydrogen and oxygen. It is preferable to provide impurities such as hydrogen and oxygen near the transistor 2100. By disposing an insulator with a blocking function, the electrical The characteristics can be stabilized.

[0438] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include fluorine, Uron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators containing titanium, hafnium or tantalum may be used in single or multilayer configurations.

[0439] Conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b , conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b , conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d The conductors 498a, 498b, and 498c may include, for example, boron, nitrogen, and the like. element, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt Nickel, Copper, Zinc, Gallium, Yttrium, Zirconium, Molybdenum, Ruthenium Conductors containing one or more of aluminum, silver, indium, tin, tantalum and tungsten are used. It may be used in layers or laminates. For example, it may be an alloy or compound, such as aluminum. Conductors containing copper and titanium, conductors containing copper and manganese, indium Conductors containing titanium, tin and oxygen, and conductors containing titanium and nitrogen may also be used.

[0440] The semiconductor device shown in FIG. 25 is the same as the transistor 2200 of the semiconductor device shown in FIG. Therefore, the semiconductor device shown in FIG. 25 is different from that shown in FIG. Specifically, the semiconductor device shown in FIG. The transistor 2200 is a Fin type. As a result, the effective channel width is increased, and the on-characteristics of the transistor 2200 are improved. In addition, the contribution of the electric field of the gate electrode can be increased, The off characteristics of the transistor 2200 can be improved.

[0441] 26 is a circuit diagram of the semiconductor device shown in FIG. 24. Therefore, the semiconductor device shown in FIG. 26 is different from that shown in FIG. Specifically, the semiconductor device shown in FIG. 2200 is provided on a semiconductor substrate 450 which is an SOI substrate. shows a structure in which an insulator 452 separates a region 456 from a semiconductor substrate 450 . By using an SOI substrate as the semiconductor substrate 450, punch-through phenomena and the like are suppressed. Therefore, the off characteristics of the transistor 2200 can be improved. The insulator 452 can be formed by insulating the semiconductor substrate 450. For example, the insulator 452 can be silicon oxide.

[0442] The semiconductor device shown in FIGS. 24 to 26 is a p-channel transistor formed on a semiconductor substrate. The area occupied by the element is reduced by fabricating a capacitor and fabricating an n-channel transistor above it. In other words, the degree of integration of the semiconductor device can be increased. A p-channel transistor and a p-channel transistor are fabricated using the same semiconductor substrate. Since the process can be simplified compared to the conventional method, the productivity of semiconductor devices can be increased. Furthermore, the yield of the semiconductor device can be increased. The transistor has an LDD (Lightly Doped Drain) region, a shallow It may be possible to omit complex processes such as wrench structure and distortion design. Compared to fabricating a silicon-doped transistor using a semiconductor substrate, productivity and yield are improved. It may be possible to make it higher.

[0443] <CMOSアナログスイッチ> The circuit diagram shown in FIG. 23B shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called CMOS analog switch.

[0444] <Storage device 1> A memory device using a transistor according to one embodiment of the present invention and capable of storing stored contents even when power is not supplied An example of a semiconductor device (memory device) that can retain data and has no limit on the number of times it can be written is shown in Figure 2. Shown in 7.

[0445] The semiconductor device shown in FIG. 27A includes a transistor 3200 using a first semiconductor and a transistor 3200 using a second semiconductor. The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 is the same as the transistor 2100 described above. You can be there.

[0446] The transistor 3300 is preferably a transistor with low off-state current. For example, a transistor using an oxide semiconductor can be used as the transistor 300. The low off-state current of the STAR 3300 allows for long-term storage of specific nodes in the semiconductor device. It is possible to retain the stored contents, i.e., no refresh operation is required, and This allows for extremely low frequency refresh operations, resulting in low power consumption. It becomes a conductor device.

[0447] In FIG. 27A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 3 005 is electrically connected to the other electrode of the capacitor 3400 .

[0448] The semiconductor device shown in FIG. 27A can hold the potential of the gate of the transistor 3200. This property makes it possible to write, store, and read information, as shown below. be.

[0449] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to The transistor 3300 is set to a potential at which it becomes conductive, thereby making the transistor 3300 conductive. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and The voltage is applied to a node FG electrically connected to one electrode of the capacitor 3400. A predetermined charge is applied to the gate of the transistor 3200 (write). The charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) ) is given. Then, the potential of the fourth wiring 3004 is given to the transistor. The potential is set to a level at which the transistor 3300 is in a non-conducting state. As a result, charge is held (retained) at node FG.

[0450] Since the off-state current of the transistor 3300 is small, the charge of the node FG is maintained for a long period of time. Retained.

[0451] Next, reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the second wiring The line 3002 takes on a potential corresponding to the amount of charge held in the node FG. If the transistor 3200 is an n-channel type, a high level voltage is applied to the gate of the transistor 3200. The apparent threshold voltage V under load th_H is a transistor 3200 The apparent threshold voltage V when a low-level charge is applied to the gate of th_L Here, the apparent threshold voltage is the voltage at which the transistor 3200 The potential of the fifth wiring 3005 required to make the fifth wiring 3005 in a "conductive state" is referred to as the potential of the fifth wiring 3005. Then, the potential of the fifth wiring 3005 is V th_H and V th_L The potential between For example, in a write operation, the charge applied to node FG can be determined by When a high level charge is applied to G, the potential of the fifth wiring 3005 becomes V0 ( >V th_H ), transistor 3200 is in a "conducting state." Meanwhile, node F When a low level charge is applied to G, the potential of the fifth wiring 3005 becomes V0 (< V th_L ), transistor 3200 remains in a "non-conducting state." Therefore, by determining the potential of the second wiring 3002, the data stored in the node FG can be read. It can be seen.

[0452] When memory cells are arranged in an array, the information of a desired memory cell is read out. For example, in a memory cell that does not read information, The transistor 3200 is in a "non-conducting state" regardless of the charge applied to the FG terminal. Electric potential, i.e., V th_H By applying a lower potential to the fifth wiring 3005, a desired memory Alternatively, the memory cell may be configured so that only the information in the memory cell can be read. In this case, the transistor 3200 is in a "conducting state" regardless of the charge applied to the node FG. ", that is, V th_L By applying a higher potential to the fifth wiring 3005, In this way, it is possible to read out only the information from the desired memory cell.

[0453] In the above, an example in which two types of charges are held at node FG is shown. The semiconductor device according to the present invention is not limited to this. For example, the node FG of the semiconductor device It is also possible to have a configuration in which three or more types of charges can be held in the electrode. The semiconductor device can be made multi-valued to increase the storage capacity.

[0454] <Structure of memory device 1> 28 is a cross-sectional view of the semiconductor device corresponding to FIG. 27(A). The device includes a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are connected to the upper side of the transistor 3200. The transistor 3300 is arranged in the same manner as the transistor 2100. The transistor 3200 may be the transistor shown in FIG. Please refer to the description of the transistor 2200. Note that in FIG. Although the case where the transistor 3200 is a p-channel transistor has been described, A channel transistor may also be used.

[0455] The transistor 3200 shown in FIG. 28 is a transistor using a semiconductor substrate 450. The transistor 3200 includes a region 472a in the semiconductor substrate 450 and a region 472b in the semiconductor substrate 450. The region 472b includes an insulator 462 and a conductor 454.

[0456] The semiconductor device shown in FIG. 28 includes an insulator 464, an insulator 466, an insulator 468, and a conductive Conductor 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478 b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, and conductor Conductor 474b, conductor 474c, conductor 496a, conductor 496b, and conductor 49 6c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, Insulator 489, insulator 490, insulator 491, insulator 492, insulator 493, and an insulator 494.

[0457] The insulator 464 is disposed on the transistor 3200. The insulator 466 is disposed on the insulator 464. Insulator 468 is disposed on insulator 466. Insulator 489 is disposed on the insulator 468. Also, the transistor 3300 is disposed on the insulator 489. The insulator 493 is disposed on the transistor 3300. 494 is disposed on the insulator 493 .

[0458] The insulator 464 has an opening that reaches the region 472a, an opening that reaches the region 472b, and a conductive The openings also include openings that reach the conductors 480a and 454. The conductor 480b or the conductor 480c is embedded.

[0459] Insulator 466 also has an opening that reaches conductor 480a and an opening that reaches conductor 480b. The openings each have a mouth and an opening that reaches the conductor 480c. The conductive body 478a, the conductive body 478b, or the conductive body 478c is embedded therein.

[0460] Insulator 468 also has an opening that reaches conductor 478b and an opening that reaches conductor 478c. The openings each have a conductor 476a or a conductor 476b. It is embedded.

[0461] The insulator 489 has an opening overlapping with a channel formation region of the transistor 3300 and It has an opening that reaches the conductor 476a and an opening that reaches the conductor 476b. The openings are filled with a conductor 474a, a conductor 474b, or a conductor 474c. It is being done.

[0462] The conductor 474a may function as a bottom gate electrode of the transistor 3300. Alternatively, for example, applying a constant potential to the conductor 474a can The electrical properties of the capacitor 3300, such as the threshold voltage, may be controlled. The body 474a and the conductor 504, which is the top gate electrode of the transistor 3300, are electrically connected. This can increase the on-state current of the transistor 3300. In addition, since the punch-through phenomenon can be suppressed, the transistor 330 This makes it possible to stabilize the electrical characteristics in the saturated region of 0.

[0463] Insulator 490 also has an opening that reaches conductor 474b and an opening that reaches conductor 474c. The insulator 490 corresponds to the insulator 103 in the above embodiment. For details, the description of the insulator 103 can be referred to. As shown in FIG. 1, an insulator 490 is placed over the conductors 474a to 474c except for the openings. By providing the insulating material 491, the conductors 474a to 474c can extract oxygen from the insulating material 491. This prevents the oxide semiconductor of the transistor 3300 from being exposed to the insulator 491. It can provide oxygen to the body effectively.

[0464] The insulator 491 has an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. The insulator 491 corresponds to the insulator 104 in the above embodiment. For details, the description of the insulator 104 can be referred to.

[0465] As shown in the above embodiment, by reducing the water and hydrogen content of the insulator 491, Therefore, formation of defect states in the oxide semiconductor of the transistor 2100 can be suppressed. This allows the electrical characteristics of the transistor 2100 to be stabilized.

[0466] In addition, such an insulator with reduced water and hydrogen can be used not only for the insulator 491 but also for other insulators. For example, insulator 466, insulator 468, insulator 489, and insulator 493 It may also be used in the following cases.

[0467] 24, the insulator 105 and the insulator 101 in the transistor 20 are Although the corresponding insulators are not shown, they may be provided. An insulator equivalent to the insulator 101 may be provided between the insulator 468 and the insulator 489. An insulator equivalent to the insulator 105 may be provided between the edge 489 and the insulator 490. Between the insulators 468 and 489, there is a material equivalent to the insulator 101 that blocks water, hydrogen, etc. The insulator 491 is provided with a function of reducing the water and hydrogen content as described above. This further suppresses the formation of defect states in the oxide semiconductor of the transistor 3300. It can be controlled.

[0468] The insulator 492 is connected to one of the source and drain electrodes of the transistor 3300. An opening through conductor 516b, which is the transistor 330, to conductor 474b. 516a, which is the other of the source electrode or drain electrode of 0, and the insulator 511. An opening reaching the overlying conductor 514 and the conductor that is the gate electrode of transistor 3300 504 and the other of the source electrode or drain electrode of transistor 3300. and an opening that passes through the conductor 516a, which is an insulator, and reaches the conductor 474c. The insulator 492 corresponds to the insulator 116 in the above embodiment, and therefore the details are the same as those of the insulator 11. The description in 6 can be taken into consideration.

[0469] The insulator 493 is connected to one of the source and drain electrodes of the transistor 3300. An opening through conductor 516b, which is the transistor 330, to conductor 474b. 516a, which is the other of the source electrode or drain electrode of 0, and the insulator 511. An opening reaching the overlying conductor 514 and the conductor that is the gate electrode of transistor 3300 504 and the other of the source electrode or drain electrode of transistor 3300. and an opening through the conductor 516a, which is the opening, to the conductor 474c. The openings are provided with conductors 496a, 496b, 496c, and 496d. However, each opening is filled with a transistor 3300 or the like. This may be through an opening in any of the components.

[0470] In addition, the insulator 494 has an opening that reaches the conductor 496a and an opening that reaches the conductor 496b. The openings each have a mouth and an opening that reaches the conductor 496c. The conductive body 498a, the conductive body 498b, or the conductive body 498c is embedded therein.

[0471] Insulator 464, Insulator 466, Insulator 468, Insulator 489, Insulator 493 or Insulator At least one of the bodies 494 is made of an insulator that has the function of blocking impurities such as hydrogen and oxygen. It is preferable to have impurities such as hydrogen and oxygen near the transistor 3300. By disposing an insulator with a blocking function, the electrical The characteristics can be stabilized.

[0472] The source or drain of transistor 3200 is connected to conductor 480b and conductor 478b. , the conductor 476a, the conductor 474b, and the conductor 496c. The conductive material 516b is electrically connected to the source electrode or the drain electrode of the semiconductor device 300. The conductor 454, which is the gate electrode of the transistor 3200, is connected to the conductor 480c. via the conductor 478c, the conductor 476b, the conductor 474c, and the conductor 496d The conductor 516a, which is the other of the source electrode and the drain electrode of the transistor 3300, and Connect emotionally.

[0473] The capacitor 3400 is connected to the other of the source electrode and the drain electrode of the transistor 3300. The insulating film 51 includes a conductor 516a, a conductor 514, and an insulator 511. 1 is formed through the same process as the insulator that functions as the gate insulator of the transistor 3300. This can be preferable in some cases because it can increase productivity. The conductor 504 that functions as the gate electrode of the transistor 3300 is formed in the same process. In some cases, using a layer formed on the substrate can be preferable because it can increase productivity.

[0474] For other structures, please refer to the descriptions in Figure 24 etc. as appropriate.

[0475] The semiconductor device shown in FIG. 29 is the same as the transistor 3200 of the semiconductor device shown in FIG. Therefore, the semiconductor device shown in FIG. 29 is different from that shown in FIG. Specifically, the semiconductor device shown in FIG. The figure shows the case where the transistor 3200 is a fin type. For details, please refer to the description of the transistor 2200 shown in FIG. The transistor 2200 is a p-channel transistor. The transistor 3200 may be an n-channel transistor.

[0476] 30 is a semiconductor device having a transistor 3200 in the semiconductor device shown in FIG. Therefore, the semiconductor device shown in FIG. 30 is different from that shown in FIG. Specifically, the semiconductor device shown in FIG. 3200 is provided on a semiconductor substrate 450 which is an SOI substrate. The transistor 3200 provided on the semiconductor substrate 450 is shown in FIG. Please refer to the description of the transistor 2200. Note that in FIG. Although the case where the transistor 3200 is a p-channel transistor has been described, A channel transistor may also be used.

[0477] <Storage device 2> The semiconductor device shown in FIG. 27B is different from the semiconductor device shown in FIG. 27A in that it does not include the transistor 3200. In this case, the operation is the same as that of the semiconductor device shown in FIG. This allows information to be written and retained.

[0478] How to read data from the semiconductor device shown in FIG. When the capacitor 3300 is brought into a conductive state, the third wiring 3003 and the capacitor element 340, which are in a floating state, 0 is electrically connected, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is The potential of one of the electrodes of the capacitor 3400 (or the charge stored in the capacitor 3400) and take different values.

[0479] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the The capacitance component of the third wiring 3003 is CB, and the capacitance of the third wiring 3003 before the charge is redistributed is If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB ×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is The potential of one of the electrodes of the element 3400 takes two states: V1 and V0 (V1>V0). and the potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+C× V1) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained. =(CB×VB0+C×V0) / (CB+C)).

[0480] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0481] In this case, the first semiconductor is applied to a driving circuit for driving the memory cell. A transistor in which a second semiconductor is applied as the transistor 3300. may be stacked on the drive circuit.

[0482] The semiconductor device described above includes a transistor using an oxide semiconductor and having low off-state current. By using this function, it is possible to retain the memory contents for a long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is fixed, it is possible to store it for a long period of time. The content can be preserved.

[0483] Furthermore, since the semiconductor device does not require a high voltage to write information, deterioration of the elements does not occur. For example, unlike conventional non-volatile memory, the flow of electrons to the floating gate Since there is no injection or extraction of electrons from the floating gate, there is no degradation of the insulator. That is, the semiconductor device according to one embodiment of the present invention does not have the same problem as the conventional nonvolatile memory. There is no limit to the number of times that data can be rewritten, which is a problem in the past, and reliability has improved dramatically. Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This allows for high-speed operation.

[0484] <Storage device 3> Regarding a modification of the semiconductor device (memory device) shown in FIG. 27(A), a circuit diagram shown in FIG. This will be used to explain.

[0485] The semiconductor device shown in FIG. 31 includes transistors 4100 to 4400 and capacitors The transistor 4100 includes an element 4500 and a capacitor 4600. A transistor similar to the transistor 3200 can be used, and the transistor 420 0 to 4400 can be transistors similar to the transistor 3300 described above. Although not shown in FIG. 31, the semiconductor device shown in FIG. 31 can be implemented in a matrix. The semiconductor device shown in FIG. 31 includes a wiring 4001, a wiring 4003, and a wiring 400 5 to 4009, the writing and reading of the data voltage is controlled according to the signal or potential applied to It is possible.

[0486] One of the source and the drain of the transistor 4100 is connected to a wiring 4003. The other of the source and drain of the transistor 4100 is connected to a wiring 4001. 31, the conductivity type of the transistor 4100 is shown as a p-channel type, but it is an n-channel type. Good too.

[0487] The semiconductor device shown in FIG. 31 has two data holding units. For example, the first data holding unit is one of the source and drain of the transistor 4400 connected to the node FG1, Between one electrode of the element 4600 and one of the source and drain of the transistor 4200 The second data storage unit stores the charge in the transistor connected to node FG2. the gate of the transistor 4100, the other of the source or drain of the transistor 4200, A charge is transferred between one of the source or drain of 4300 and one electrode of the capacitor element 4500. Hold.

[0488] The other of the source and the drain of the transistor 4300 is connected to a wiring 4003. The other of the source and drain of the transistor 4400 is connected to a wiring 4001. The gate of the transistor 4400 is connected to the wiring 4005. The gate of the transistor 4300 is connected to a wiring 4007. The other electrode of the capacitor 4600 is connected to the wiring 4008. The other electrode of the element 0 is connected to a wiring 4009.

[0489] The transistors 4200 to 4400 control writing of data voltages and retention of electric charges. The transistors 4200 to 4400 function as switches. In this case, a transistor with a low current (off-state current) that flows between the source and drain is used. As a transistor with a low off-state current, it is preferable to use a transistor having an oxide layer in the channel formation region. Preferably, the transistor is an OS transistor having an oxide semiconductor. The advantage of silicon-based transistors is that they have low off-state current and can be stacked with silicon-based transistors. In FIG. 31, the conductivity types of the transistors 4200 to 4400 are n-channel. However, it may be a p-channel type.

[0490] The transistors 4200, 4300, and 4400 are oxidized. Even if the transistor uses a compound semiconductor, it is preferable to provide it in a separate layer. The semiconductor device shown in FIG. 1 includes a first layer 4 having a transistor 4100 as shown in FIG. 021, and a second layer 4022 having transistors 4200 and 4300. and a third layer 4023 having a transistor 4400. By stacking layers having transistors, the circuit area can be reduced, and The device can be made smaller.

[0491] Next, the operation of writing information into the semiconductor device shown in FIG. 31 will be described.

[0492] First, the data voltage is written to the data storage unit connected to node FG1 (hereinafter referred to as This will be referred to as write operation 1. The data voltage to be written to the connected data storage unit is V D1 and the threshold voltage of the transistor 4100 is Voltage is V th Let's say.

[0493] In write operation 1, the wiring 4003 is connected to V D1 After setting the wiring 4001 to ground potential, , and are electrically floating. Also, the wirings 4005 and 4006 are set to high level. 4007 to 4009 are set to a low level. Then, the node FG The potential of the wiring 4 rises, and a current flows through the transistor 4100. The potential of 001 rises. Also, the transistor 4400 and the transistor 4200 are in a conducting state. Therefore, as the potential of the wiring 4001 increases, the potentials of the nodes FG1 and FG2 The potential of the node FG2 rises, and the potential between the gate and source of the transistor 4100 rises. Voltage (V gs ) is the threshold voltage V of the transistor 4100 th Then, transistor 41 Therefore, the potential of the wiring 4001 and the nodes FG1 and FG2 The rise of V stopped. D1 From V th The V dropped by D1 -V th " and becomes constant.

[0494] In other words, the V given to wire 4003 D1 is generated by the current flowing through transistor 4100. The potential is applied to the wiring 4001, and the potentials of the nodes FG1 and FG2 increase. The potential of node FG2 becomes "V D1 -V th " Then, the V of the transistor 4100 gs V th Therefore, the current stops.

[0495] Next, a data voltage write operation (hereinafter, This will be called write operation 2. The data voltage written to the memory is V D2 It will be explained as follows.

[0496] In write operation 2, wire 4001 is connected to V D2 After setting the wiring 4003 to ground potential, , and are electrically floating. The wiring 4007 is set to a high level. 4006, 4008, and 4009 are set to low level. Transistor 4300 is set to the conductive state. Therefore, the potential of the node FG2 is also set to low. The voltage of the wiring 4003 decreases, and a current flows through the transistor 4100. The potential rises. In addition, the transistor 4300 is turned on. As the potential at node FG2 rises, the potential at node FG3 rises. V at transistor 4100 gs is the V of the transistor 4100 th When the transistor Therefore, the current flowing through the wiring 4003 and the node FG2 is increased. The rise stops, V D2 From V th The V dropped by D2 -V th " and becomes constant.

[0497] In other words, the V given to wire 4001 D2 is generated by the current flowing through transistor 4100. is applied to the wiring 4003, and the potential of the node FG2 increases. The potential of FG2 is "V D2 -V th " Then, the V of the transistor 4100 gs V th At this time, the potential of the node FG1 is 4400 are in a non-conducting state, and the "V D1 -V th " is held will be done.

[0498] In the semiconductor device shown in FIG. 31, after writing data voltages to a plurality of data holding units, The line 4009 is set to a high level, and the potentials of the nodes FG1 and FG2 are raised. The transistor is turned off, preventing the transfer of charge and maintaining the written data voltage. do.

[0499] By the above-described operation of writing data voltages to the nodes FG1 and FG2, multiple data The data voltage can be held in the data holding section. D1 -V th " and "V D2 -V th " was used as an example, but these are multi-valued data. Therefore, each data storage unit stores 4 bits of data. When holding data, 16 values ​​of "V D1 -V th " and "V D2 -V th " can be taken.

[0500] Next, the operation of reading information from the semiconductor device shown in FIG. 31 will be described.

[0501] First, the data voltage is read from the data storage unit connected to node FG2 (hereinafter referred to as (This is called read operation 1.) will now be described.

[0502] In the read operation 1, the wiring 400 is precharged and then brought into an electrically floating state. 3 is discharged. The wirings 4005 to 4008 are set to a low level. The wiring 4009 is set to a low level. The potential of the electrically floating node FG2 is set to low level. D2 -V th "and When the potential of the node FG2 decreases, a current flows through the transistor 4100. The flow of current reduces the potential of the wiring 4003, which is in an electrically floating state. As the voltage drops, the V gs becomes smaller. Transistor 4100 V gs is the V of the transistor 4100 th When this happens, the current flowing through transistor 4100 That is, the potential of the wiring 4003 becomes smaller than the potential of the node FG2, D2 -V th " to V th The value "V D2 The potential of this wiring 4003 is This corresponds to the data voltage of the data storage section connected to FG2. The data voltage undergoes A / D conversion and the data is acquired from the data storage section connected to node FG2. do.

[0503] That is, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. Switching from high to low allows current to flow through transistor 4100. As a result, the potential of the floating wiring 4003 drops to "V D2 " Tiger In Transistor 4100, the "V D2 -V th "V between gs V th Tona The current stops. Then, the wiring 4003 is connected to the "V D 2" is read out.

[0504] After acquiring the data from the data storage section connected to node FG2, transistor 4300 is in a conducting state, and "V D2 -V th " is discharged.

[0505] Next, the charge held at node FG1 is distributed to node FG2, and the charge held at node FG1 is transferred to node FG3. The data voltage of the data storage unit connected to node FG1 is transferred to the data storage unit connected to node FG2. Then, the wirings 4001 and 4003 are set to low level, and the wiring 4006 is set to high level. In addition, the wiring 4005 and the wirings 4007 to 4009 are set to low level. When node FG1 is in a conductive state, the charge of node FG1 is shared with node FG2.

[0506] Here, the potential after the charge distribution is the written potential "V D1 -V th " will decrease from Therefore, the capacitance value of the capacitor 4600 is set to be larger than the capacitance value of the capacitor 4500. Alternatively, the potential "V D1 -V th " is the same design The potential "V D2 -V th It is preferable to make the capacitance larger than . By changing the ratio of the values ​​and increasing the potential to be written in advance, the potential after the charge distribution The change in potential due to the distribution of charge will be described later.

[0507] Next, the data voltage is read from the data storage unit connected to the node FG1 (hereinafter, This will be referred to as read operation 2.

[0508] In the read operation 2, the wiring 400 is precharged and then brought into an electrically floating state. 3 is discharged. The wirings 4005 to 4008 are set to a low level. The wiring 4009 is The line 4009 is set to a high level during precharge and then set to a low level. By using this as a bell, the electrically floating node FG2 is set to the potential "V D1 -V th " When the potential of the node FG2 decreases, a current flows through the transistor 4100. The flow of current reduces the potential of the electrically floating wiring 4003. As V decreases, the V of transistor 4100 gs becomes smaller. V gs is the V of the transistor 4100 th When the current through transistor 4100 becomes That is, the potential of the wiring 4003 becomes smaller than the potential of the node FG2 “V D1 -V th " From V th The value "V D1 The potential of the wiring 4003 is The data voltage of the data storage section connected to G1 corresponds to the data of the analog value that is read out. The voltage of the capacitor undergoes A / D conversion and acquires data from the data storage section connected to node FG1. This completes the read operation of the data voltage to the data storage unit connected to node FG1. .

[0509] That is, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. Switching from high to low allows current to flow through transistor 4100. As a result, the potential of the floating wiring 4003 drops to "V D1 " Tiger In Transistor 4100, the "V D1 -V th "V between gs V th Tona The current stops. Then, the wiring 4003 is connected to the "V D "1" is read out.

[0510] By the above-described operation of reading the data voltages from the nodes FG1 and FG2, a plurality of The data voltage can be read from the data storage unit. For example, the node FG1 and the node FG2 stores 4 bits (16 values) of data, for a total of 8 bits (256 values) In FIG. 31, the first layer 4021 to the third layer 4022 can store data. However, by forming further layers, the surface of the semiconductor device can be It is possible to increase the storage capacity without increasing the product.

[0511] The potential that is read out is V th It is read as a voltage larger than Therefore, the "V D1 -V th " and "V D2 -V th "V th As a result, the memory cell This improves the storage capacity per unit and makes the read data closer to the correct data. Therefore, the reliability of the data can be improved.

[0512] 32 shows a cross-sectional view of the semiconductor device corresponding to FIG. 31. The semiconductor device shown in FIG. The transistors 4100 to 4400, the capacitor 4500, and the capacitor 4600, where the transistor 4100 is formed in the first layer 4021, The transistors 4200 and 4300 and the capacitor 4500 are formed in the second layer 4022. The transistor 4400 and the capacitor 4600 are formed in the third layer 4023 .

[0513] Here, the transistors 4200 to 4400 are the transistor 3300. The description of the transistor 3200 can be referred to for the transistor 4100. In addition, the description in Figure 28 can be taken into consideration as appropriate for other wiring, insulators, etc.

[0514] In the capacitor element 3400 of the semiconductor device shown in FIG. 28, the conductive layer is set parallel to the substrate. The capacitor elements 4500 and 4600 have a trench-shaped conductive layer. By using this structure, the same occupied area can be Even if the capacitance is a product, a large capacitance value can be ensured.

[0515] <Storage device 4> The semiconductor device shown in FIG. 27C includes a transistor 3500 and a sixth wiring 3006. This differs from the semiconductor device shown in FIG. It is possible to write and store information in the same way as in a semiconductor device. The transistor 3500 may be the same as the transistor 3200 described above. .

[0516] The sixth wiring 3006 is electrically connected to the gate of the transistor 3500. One of the source and drain of the transistor 3500 is electrically connected to the drain of the transistor 3200. The other of the source and drain of the transistor 3500 is electrically connected to a third wiring 3003. is connected to.

[0517] 33 shows an example of a cross-sectional view of the semiconductor device shown in FIG. 27(C). 33 and 34 show an example of a cross section taken along a B3-B4 direction, which is approximately perpendicular to the B1-B2 direction shown in FIG. The semiconductor device shown in FIG. 27C includes five layers, ie, layers 1627 to 1631. Layer 1627 includes transistors 3200, 3500, and 3600. The layer 1628 and the layer 1629 include a transistor 3300.

[0518] Layer 1627 is a layer of a substrate 1400 and a transistor 3200 on the substrate 1400. Insulator 1464 on transistor 3500, transistor 3600, transistor 3200, etc. , plug 1541, etc. The plug 1541, etc., is, for example, a transistor 3200 The plug 1541 is connected to a gate electrode, a source electrode, a drain electrode, or the like. Preferably, the body 1464 is formed to fill the space.

[0519] Transistor 3200, transistor 3500, and transistor 3600 are The description of transistor 2200 can be taken into consideration.

[0520] The insulator 1464 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, nitride Aluminum or the like may be used.

[0521] Insulator 1464 is made by sputtering, CVD (thermal CVD, MOCVD, PECV) It can be formed by the MBE method, the ALD method, the PLD method, or the like. In particular, when the insulator is formed by a CVD method, preferably a plasma CVD method, the coating In addition, to reduce damage caused by plasma, Thermal CVD, MOCVD or ALD is preferred.

[0522] Also, as the insulator 1464, silicon carbonitride (silicon carbonitride) ride), silicon oxycarbide, etc. Also, USG (Undoped Silicate Glass), BP SG(Boron Phosphorus Silicate Glass), BSG( Borosilicate Glass) can be used. USG, BPSG, etc. The film may be formed by atmospheric pressure CVD. The film may be formed by coating.

[0523] The insulator 1464 may be a single layer or may be a laminate of multiple materials.

[0524] Here, in FIG. 33, the insulator 1464 is an insulator 1464a and an insulator on the insulator 1464a. 1464b and 1464c are used as an example of a two-layer structure.

[0525] Insulator 1464a protects region 1476 of transistor 3200, transistor 3200, etc. It is preferable that the conductive material 1454 functioning as a gate has good adhesion and coverage.

[0526] As an example of the insulator 1464a, silicon nitride formed by a CVD method can be used. Here, it may be preferable that the insulator 1464a contains hydrogen. By including hydrogen, defects and the like in the substrate 1400 are reduced, and the transistor 3200 For example, if a material containing silicon is used as the substrate 1400, In this case, hydrogen can terminate defects such as dangling bonds of silicon. do.

[0527] Here, the conductor under the insulator 1464a such as the conductor 1454 and the insulator such as the conductor 1511 are It is preferable that the parasitic capacitance formed between the body 1464b and the conductor formed on the body 1464b is small. Therefore, it is preferable that the insulator 1464b has a low dielectric constant. It has a lower dielectric constant than the insulator 1462 that serves as the gate insulator for transistors such as 3200. It is also preferable that the insulator 1464b has a lower dielectric constant than the insulator 1464a. For example, the relative dielectric constant of the insulator 1464b is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 1464b is preferably 0.01 times that of the insulator 1464a. 0.7 times or less is preferred, and 0.6 times or less is more preferred.

[0528] Here, as an example, silicon nitride is used for the insulator 1464a and USG is used for the insulator 1464b. It can be used.

[0529] Here, the insulator 1464a and the insulator 1581a are made of silicon nitride or silicon carbonitride. By using materials with low copper permeability such as copper conductors, In this case, diffusion of copper into upper and lower layers such as the insulator 1464a and the insulator 1581a can be suppressed. There are cases where this happens.

[0530] Also, for example, from the upper surface of the conductor 1511b that is not covered by the conductor 1511a, an insulator Impurities such as copper may diffuse to the upper layer through the conductor 1584. The insulator 1584 on 11b is preferably made of a material with low impurity permeability, such as copper. For example, the insulator 1584 may be a laminated structure of the insulators 1581a and 1581b. A laminated structure like this can be used.

[0531] Layer 1628 includes an insulator 1581, an insulator 1584 on insulator 1581, and an insulator 1585 on insulator 1586. 84 and an insulator 1571 on the insulator 1571. Conductors 1511 and the like on the edge 1464, and plugs 1543 and the like connected to the conductors 1511 and the like. , a conductor 1513 on an insulator 1571. The conductor 1511 is connected to an insulator 1581. It is preferable that the plug 1543 is formed so as to be embedded. The conductor 1513 is preferably formed so as to be embedded in the insulator 1571. It is preferably formed so as to be embedded in the insulator 1585 .

[0532] Layer 1628 may also include conductor 1413. Conductor 1413 may be formed by insulating material 15. It is preferable that the insulating layer 85 is formed so as to be embedded therein.

[0533] The insulators 1584 and 1585 may be, for example, silicon oxide or silicon oxynitride. , silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide nitride, nitride oxide Aluminum oxide, aluminum nitride, etc. may be used.

[0534] The insulators 1584 and 1585 are formed by sputtering, CVD (thermal CVD), MOCVD, PECVD, etc.), MBE, ALD, or PLD In particular, the insulator can be formed by a CVD method, preferably a plasma CVD method. Therefore, when a film is formed, the coating property can be improved, which is preferable. It is preferable to form the film using silane (TEOS: Si(OC2H5)4) as the film forming gas. It is preferable to form the film while heating. By forming a film of 1585 or the like, the hydrogen concentration in the film can be reduced. When heating, keep the temperature within a relatively low range (for example, between 350°C and 445°C). It is preferable to heat the insulator having the reduced hydrogen concentration in the film in this way. It may also be used as an interlayer insulating film.

[0535] To reduce damage caused by plasma, thermal CVD, MOCVD, or ALD methods are used. The law is preferred.

[0536] Also, silicon carbide, silicon carbonitride (SiC) are used as 1584 and insulator 1585. Silicon carbonitride, silicon oxy carbide carbide) can be used. Also, USG (Undoped Silica Gel) can be used. cate Glass), BPSG (Boron Phosphorus Silica) Use of glass (glass), borosilicate glass (BSG), etc. USG, BPSG, etc. can be formed by atmospheric pressure CVD. Alternatively, HSQ (hydrogen silsesquioxane) or the like may be formed by coating.

[0537] The insulators 1584 and 1585 may be single layers or may be made of multiple layers of materials. good.

[0538] The insulator 1581 may be formed by stacking multiple layers. For example, as shown in FIG. The insulating layer 1581 is made up of two layers: an insulating layer 1581a and an insulating layer 1581b on the insulating layer 1581a. That's fine.

[0539] The plug 1543 also has a protrusion on the insulator 1571 .

[0540] Metal materials such as the conductor 1511, the conductor 1513, the conductor 1413, the plug 1543, etc. Conductive materials such as metals, alloys, or metal oxides can be used. Aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, niobium, Metals such as molybdenum, silver, tantalum, or tungsten, or materials containing these as their main components The alloys can be used as single layer or multilayer structures. Metal nitrides such as molybdenum nitride and titanium nitride can be used.

[0541] Here, the conductors such as the conductor 1511 and the conductor 1513 are the semiconductor device shown in FIG. Therefore, it is preferable that these conductors function as wiring or wiring. These conductors are connected by plugs such as plug 1543. It is preferable that

[0542] The insulator 1581 can be described by referring to the description of the insulator 1464. It may be a single layer or may be made of a laminate of multiple materials. In this example, the insulating layer 1581 is made of two layers: an insulator 1581a and an insulator 1581b on the insulator 1581a. Regarding materials that can be used for the insulators 1581a and 1581b and methods for forming them, The materials that can be used for the insulator 1464a and the insulator 1464b are as follows: The description of the formation method can be referred to.

[0543] As an example of the insulator 1581a, silicon nitride formed by a CVD method can be used. Here, the semiconductor element included in the semiconductor device shown in FIG. 300, etc., hydrogen diffuses into the semiconductor element, causing a deterioration in the characteristics of the semiconductor element. Therefore, it is preferable to use a film that releases less hydrogen as the insulator 1581a. The amount of desorption of hydrogen can be measured by, for example, thermal desorption spectroscopy (TDS). It can be analyzed using techniques such as sorption spectroscopy. The amount of hydrogen desorption from insulator 1581a was measured in the range of 50°C to 500°C by TDS analysis. In this case, the amount of hydrogen atoms lost is, for example, 5 × 10 20 atoms / cm 3 Below, I prefer Or 2 x 10 20 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 Alternatively, the amount of desorption of the insulator 1581a converted into hydrogen atoms is equal to or less than the insulating film. For example, 5 x 10 15 atoms / cm 2 Less than or equal to 2 x 10 15 a toms / cm 2 Less than or equal to 1×10 15 atoms / cm 2 If it's below stomach.

[0544] In addition, silicon nitride with a low hydrogen desorption rate is not only an insulator 1581a but also a It may be used for the insulator layer above the insulator 1581a shown in FIG. Instead of silicon, an insulating material similar to the insulator 104 in which hydrogen and water are reduced as shown in the above embodiment is used. A peripheral body may also be used.

[0545] Furthermore, it is preferable that the insulator 1581b has a lower dielectric constant than the insulator 1581a. For example, the relative dielectric constant of the insulator 1581b is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 1581b is preferably 0.7 times or less the relative dielectric constant of the insulator 1581a. It is preferable that the ratio is 0.6 times or less.

[0546] The insulator 1571 is preferably formed using an insulating material with low impurity permeability. For example, it is preferable that the insulator 1571 has low oxygen permeability. It is preferable that the insulator 71 has low hydrogen permeability. Preferably it is low.

[0547] The insulator 1571 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, or oxide. Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTi O3) or (Ba,Sr)TiO3 (BST), silicon nitride, etc. are used in single layer or multilayer. Alternatively, these insulators may contain, for example, aluminum oxide, bismuth oxide, or oxide. Germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide Thorium, zirconium oxide, or gallium oxide may be added. The insulating layer may be nitrided to form an oxynitride. Alternatively, silicon nitride may be laminated. In particular, aluminum oxide has high resistance to water and hydrogen. This is preferable because it has excellent barrier properties.

[0548] The insulator 1571 may be, for example, silicon carbide, silicon carbonitride, or silicon oxycarbide. Cone etc. may also be used.

[0549] The insulator 1571 is made by laminating a layer of material with low water and hydrogen permeability with a layer containing other insulating material. For example, a layer containing silicon oxide or silicon oxynitride, a layer containing metal oxide, A layer containing the above may be laminated and used.

[0550] For example, when the semiconductor device shown in FIG. 27C includes an insulator 1571, The elements contained in the conductor 1513, the conductor 1413, etc. are mixed with the insulator 1571 and the layer below it (insulator This can prevent diffusion into the insulating layer 1584, the insulating layer 1581, the layer 1627, etc.

[0551] If the dielectric constant of the insulator 1571 is higher than that of the insulator 1584, the dielectric constant of the insulator 1571 The thickness of the insulating layer 1584 is preferably smaller than that of the insulating layer 1584. The dielectric constant is preferably 0.7 times or less, more preferably 0.7 times or less, the relative dielectric constant of the insulator 1571. For example, the thickness of the insulator 1571 is preferably 5 nm or more and 200 nm or less. The thickness of the insulator 1584 is preferably 5 nm or more and 60 nm or less. Preferably, the thickness is 30 nm or more and 800 nm or less, more preferably 50 nm or more and 500 nm or less. Also, for example, the thickness of the insulator 1571 must be one-third or less of the thickness of the insulator 1584. is preferred.

[0552] Layer 1629 includes transistor 3300 and plugs such as plug 1544 and plug 1544b. The plugs, such as plug 1544 and plug 1544b, are formed in layer 1628. the conductor 1513 of the transistor 3300, the gate electrode, the source electrode, or The transistor 3300 has the same structure as the transistor 20 and the transistor 3301. The descriptions of Transistor 2100 and other products can be taken into consideration.

[0553] The transistor 3300 includes a conductor 1413, an insulator 1571a, an insulator 1402, and a conductor The conductor 1416a, the conductor 1416b, the conductor 1404, the insulator 1408, and the insulator 1591 are The conductor 1413 is the conductor 102, the insulator 1571a is the insulator 103, and the insulator 1402 is the insulator 104, conductor 1416a is the conductor 108a, and conductor 1416b is the conductor conductor 1404 is conductor 114; insulator 1408 is insulator 116; insulator 1 591 can refer to the insulator 118.

[0554] 76 and 77, the insulator 105 in the transistor 20 76 and 77 are the same as those in FIGS. 33 and 34 only in that an insulator 1402a is provided. 34. For example, the insulator 1402a is provided between the insulator 1585 and the insulator 1571a. Here, in the insulator 1402a, the insulator 1571a, and the insulator 1402, Therefore, it is preferable that the insulator 1571a has an electron trapping region. When the insulator 1402 has a function of suppressing the emission of electrons, the electrons trapped in the insulator 1571a The electron behaves like a fixed negative charge. Therefore, injecting electrons into the insulator 1571a By this, the threshold voltage of the transistor 3300 can be changed. The injection of electrons into 71a is achieved by applying a positive or negative potential to the conductor 1413. This can be done.

[0555] In addition, depending on the time for applying a potential to the conductor 1413 and / or the potential to be applied, The amount of electron injection can be adjusted to set the threshold voltage of the transistor to a desired value. The potential applied to the conductor 1413 can be used to generate a tunneling current in the insulator 1402a. It is sufficient that the voltage is such that a current flows, for example, 20V or more and 60V or less, preferably 24V or more. A potential of 50 V or less, more preferably 30 V to 45 V may be applied. The heating time is, for example, in the range of 0.1 seconds or more and 20 seconds or less, preferably 0.2 seconds or more and 10 seconds or less. It is sufficient to set the range as

[0556] As in the above embodiment, the insulator 1571 corresponds to the insulator 106a of the transistor 20. A laminated film of an insulator (in this embodiment, an insulator 1585) is provided between the insulators. , the insulator 1402a, the insulator 1571a, and the insulator 1402), or As described above, the insulator 1571 is preferably a material that blocks water and hydrogen. As an insulator having a blocking function, the insulator 106a of the transistor 20 and the semiconductor 10 When forming the oxide film 6b, water and hydrogen are supplied to the oxide film 6b. 5, insulator 1402a, insulator 1571a, and insulator 1402 are included. Therefore, when the oxide is formed, the insulator 1585, the insulator 1402a, and the insulator 157 1a and the insulator 1402, particularly the water contained in the insulator 1402, or If the amount of hydrogen is sufficiently small, it is possible to reduce the supply of water or hydrogen to the oxide. can.

[0557] The conductors 1416a and 1416b are formed in contact with the upper surfaces of the conductors 1416a and 1416b. It is preferable that the material used is one that has low permeability to the elements contained in the material 1544b.

[0558] The conductor 1416a and the conductor 1416b may be a stacked film. The conductor 1416a and the conductor 1416b are stacked as a first layer and a second layer. Here, a first layer is formed on an oxide semiconductor layer, and a second layer is formed on the first layer. For example, tungsten is used as the first layer, and for example, tantalum nitride is used as the second layer. Here, copper is used for the plug 1544b etc. Copper has low resistance and is suitable for plugs, wiring etc. On the other hand, copper is easily diffused and is not suitable for use as a semiconductor in transistors. The diffusion of these elements into the semiconductor layer, gate insulating film, etc. may degrade the transistor characteristics. Here, the conductor 1416a and the conductor 1416b contain tantalum nitride, so that the plating This may prevent copper contained in the gap 1544b and the like from diffusing into the oxide semiconductor layer.

[0559] In the semiconductor device illustrated in FIG. 27C according to one embodiment of the present invention, plugs, wirings, and the like are formed in a manner similar to that of a semiconductor element. When the semiconductor device contains elements and compounds that cause deterioration of the semiconductor device's properties, the elements and compounds diffuse into the semiconductor device. It is preferable that the structure suppresses this.

[0560] Layer 1630 includes insulator 1592, conductors such as conductor 1514, and plugs such as plug 1545. and plugs, such as plug 1545, that connect to conductors, such as conductor 1514.

[0561] The layer 1631 includes a capacitor 3400. The capacitor 3400 includes a conductor 1516. The insulator 1572 is a conductor 1517. The layer 1631 has a region sandwiched between the insulator 1594 and the conductor 1517. It is preferable to have a plug 1547 on the conductor 1517. The plug 1547 is an insulator 1 594. Also, the layer 1631 is preferably formed so as to be embedded in the layer 163 conductor 1516b connected to a plug having 0, and plug 1547 on conductor 1516b It is preferred that b.

[0562] The layer 1631 may also have a wiring layer connected to the plug 1547 and the plug 1547b. In the example shown in FIG. 33, the wiring layer is a conductive layer connected to the plug 1547 and the plug 1547b. conductor 1518, etc., plug 1548 on conductor 1518, insulator 1595, and plug 15 48 and an insulator 1599 on the conductor 1519. 48 is preferably formed so as to be embedded in the insulator 1595. 599 has an opening over the conductor 1519 .

[0563] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0564] (Embodiment 5) In this embodiment, an imaging device including a transistor according to one embodiment of the present invention will be described. An example of this will be described.

[0565] <Imaging device> An imaging device according to one aspect of the present invention will be described below.

[0566] 35A is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral The pixel section 210 has a pixel circuit 270, a peripheral circuit 280, and a peripheral circuit 290. It has a plurality of pixels 211 arranged in a matrix of columns (p and q are integers of 2 or more). The peripheral circuits 260, 270, 280, and 290 are respectively The pixel 211 is connected to the plurality of pixels 211 and has a function of supplying signals for driving the plurality of pixels 211. In this specification and the like, the peripheral circuits 260, 270, 280, and The peripheral circuit 290 and the like may be referred to as the "peripheral circuit" or the "drive circuit." For example, peripheral circuit 260 can be considered a part of the peripheral circuit.

[0567] The imaging device 200 preferably includes a light source 291. The light source 291 emits detection light. It can emit P1.

[0568] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the substrate on which the pixel section 210 is formed. Also, semiconductor devices such as IC chips may be used for part or all of the peripheral circuits. The peripheral circuits are peripheral circuits 260, 270, 280, and 29. One or more of the 0s may be omitted.

[0569] As shown in FIG. 35B, in the pixel section 210 of the imaging device 200, The pixels 211 may be arranged at an angle. By arranging the pixels 211 at an angle, the pixel This allows the pixel interval (pitch) in the column direction to be shortened. This can further improve the quality of imaging in the imaging device.

[0570] <Pixel configuration example 1> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and each The sub-pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By doing so, it is possible to obtain information for realizing a color image display.

[0571] FIG. 36(A) is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 36(A) has a color filter that transmits light in the red (R) wavelength band. The sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") has a wavelength band of green (G). A sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a light-transmitting color filter and blue (B) wavelength band light. 2 (hereinafter also referred to as "subpixel 212B"). This can be used to make it function.

[0572] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 2 31, and are electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The subpixels 212R, 212G, and 212B are each connected to an independent wiring 2 53. In this specification, for example, the pixel connected to the n-th row pixel 211 is The wiring 248 and the wiring 249 are respectively referred to as wiring 248[n] and wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the m-th column is referred to as wiring 253[m 36A, the sub-pixel 212 of the pixel 211 in the m-th column is written as The wiring 253 connected to R is the wiring 253[m]R, and the wiring 253 connected to the subpixel 212G is the wiring 253[m]R. The wiring 253[m]G and the wiring 253 connected to the subpixel 212B are referred to as wiring 253[m]B. The subpixel 212 is electrically connected to the peripheral circuit via the wiring.

[0573] In addition, the imaging device 200 detects color components of adjacent pixels 211 that transmit light in the same wavelength band. The sub-pixels 212 provided with the filters are electrically connected to each other via switches. In FIG. 36(B), n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q) and a sub-pixel 212 of a pixel 211 arranged in the (n+1)th row and the (m)th column adjacent to the pixel 211. 36B shows an example of connection of the sub-pixels 212 included in the pixel 211 arranged in the The sub-pixel 212R arranged in the nth row and the mth column and the sub-pixel 212R arranged in the n+1th row and the mth column are The sub-pixels 212G are connected via a switch 201. The sub-pixels 212G are arranged in n rows and m columns. The sub-pixels 212G arranged in the n+1th row and the mth column are connected via the switches 202. In addition, the sub-pixel 212B arranged in the nth row and the mth column and the sub-pixel 212B arranged in the n+1th row and the mth column are connected via a switch 203.

[0574] The color filters used for the subpixel 212 are limited to red (R), green (G), and blue (B). color filters that transmit cyan (C), yellow (Y) and magenta (M) light, respectively. A sub-pixel for detecting light of three different wavelength bands may be used in one pixel 211. By providing the element 212, a full color image can be obtained.

[0575] Alternatively, color filters that transmit red (R), green (G), and blue (B) light are used. In addition to the sub-pixel 212, a color filter that transmits yellow (Y) light is provided. Alternatively, a pixel 211 having sub-pixels 212 may be used. The sub-pixel 212 is provided with a color filter that transmits light of blue (Y) and magenta (M). In addition, a pixel 212 having a sub-pixel 212 provided with a color filter that transmits blue (B) light is 11 may be used. One pixel 211 may have four sub-pixels that detect light in different wavelength bands. By providing 212, the color reproducibility of the acquired image can be further improved.

[0576] Also, for example, in FIG. 36(A), the sub-pixel 212 that detects light in the red wavelength band, a sub-pixel 212 that detects light in the blue wavelength band, and a sub-pixel 21 The pixel ratio (or light receiving area ratio) of 2 does not have to be 1:1:1. For example, A Bayer array with a ratio (light receiving area ratio) of red:green:blue=1:2:1 may also be used. Alternatively, the pixel number ratio (light receiving area ratio) may be set to red:green:blue=1:6:1.

[0577] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that the number is two or more. For example, by providing two or more sub-pixels 212 that detect light in the same wavelength band, redundancy can be increased. The reliability of the imaging device 200 can be improved.

[0578] In addition, IR (Infrared) filters absorb or reflect visible light and transmit infrared light. ) filter, an imaging device 200 that detects infrared light can be realized.

[0579] In addition, ND (Neutral Density) filters (light-reducing ...

Claims

1. a first transistor, a second transistor, a capacitor, a first insulator, and a second insulator; a channel formation region of the second transistor is formed in an oxide semiconductor; the second transistor has a first gate electrode below the oxide semiconductor and a second gate electrode above the oxide semiconductor; the first gate electrode overlaps with the oxide semiconductor via a third insulator; the first insulator is disposed above a gate electrode of the first transistor; the first gate electrode is disposed above the first insulator; the second insulator is disposed above the second gate electrode; the capacitor overlaps with the gate electrode of the first transistor via the first insulator; the capacitor has a conductor functioning as a source electrode or a drain electrode of the second transistor as one electrode; the conductor is disposed so as to be in contact with a top surface of the oxide semiconductor and not in contact with a side surface of the oxide semiconductor; the capacitor overlaps with the oxide semiconductor; the third insulator is disposed below a region of the oxide semiconductor that overlaps with the capacitor.

2. a first transistor, a second transistor, a capacitor, a first insulator, and a second insulator; a channel formation region of the second transistor is formed in an oxide semiconductor; the second transistor has a first gate electrode below the oxide semiconductor and a second gate electrode above the oxide semiconductor; the first gate electrode overlaps with the oxide semiconductor via a third insulator; the first insulator is disposed above a gate electrode of the first transistor; the first gate electrode is disposed above the first insulator; the second insulator is disposed above the second gate electrode; a gate electrode of the first transistor and a source or a drain of the second transistor are electrically connected to each other through an opening in the first insulator; the capacitor overlaps with the gate electrode of the first transistor via the first insulator; the capacitor has a conductor functioning as a source electrode or a drain electrode of the second transistor as one electrode; the conductor is disposed so as to be in contact with a top surface of the oxide semiconductor and not in contact with a side surface of the oxide semiconductor; the capacitor overlaps with the oxide semiconductor; the third insulator is disposed below a region of the oxide semiconductor that overlaps with the capacitor.

3. a first transistor, a second transistor, a capacitor, a first insulator, and a second insulator; a channel formation region of the first transistor includes silicon; a channel formation region of the second transistor is formed in an oxide semiconductor; the second transistor has a first gate electrode below the oxide semiconductor and a second gate electrode above the oxide semiconductor; the first gate electrode overlaps with the oxide semiconductor via a third insulator; the first insulator is disposed above a gate electrode of the first transistor; the first gate electrode is disposed above the first insulator; the second insulator is disposed above the second gate electrode; the capacitor overlaps with the gate electrode of the first transistor via the first insulator; the capacitor has a conductor functioning as a source electrode or a drain electrode of the second transistor as one electrode; the conductor is disposed so as to be in contact with a top surface of the oxide semiconductor and not in contact with a side surface of the oxide semiconductor; the capacitor overlaps with the oxide semiconductor; the third insulator is disposed below a region of the oxide semiconductor that overlaps with the capacitor.

4. a first transistor, a second transistor, a capacitor, a first insulator, and a second insulator; a channel formation region of the first transistor includes silicon; a channel formation region of the second transistor is formed in an oxide semiconductor; the second transistor has a first gate electrode below the oxide semiconductor and a second gate electrode above the oxide semiconductor; the first gate electrode overlaps with the oxide semiconductor via a third insulator; the first insulator is disposed above a gate electrode of the first transistor; the first gate electrode is disposed above the first insulator; the second insulator is disposed above the second gate electrode; a gate electrode of the first transistor and a source or a drain of the second transistor are electrically connected to each other through an opening in the first insulator; the capacitor overlaps with the gate electrode of the first transistor via the first insulator; the capacitor has a conductor functioning as a source electrode or a drain electrode of the second transistor as one electrode; the conductor is disposed so as to be in contact with a top surface of the oxide semiconductor and not in contact with a side surface of the oxide semiconductor; the capacitor overlaps with the oxide semiconductor; the third insulator is disposed below a region of the oxide semiconductor that overlaps with the capacitor.

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