Thin film transistor, thin film transistor array, and method for manufacturing thin film transistor

Abstract

The purpose of the present invention is to provide a thin film transistor that has preferable element characteristics and high flexibility, a thin film transistor array, and a thin film transistor production method. Thus, the thin film transistor of the present invention has an insulative substrate, a gate electrode, a first gate insulating layer, a second gate insulating layer, a semiconductor layer, an insulative protection layer, a source electrode, and a drain electrode. The first gate insulating layer comprises an insulating material including an organic material, the second gate insulating layer comprises an inorganic insulating material, the thickness of the second gate insulating layer is thinner than the thickness of the first gate insulating layer, and the second gate insulating layer is formed only in a range overlapping the semiconductor layer or the protection layer.

Description

[Technical Field]

[0001] The present invention relates to a thin film transistor, a thin film transistor array, and a method for manufacturing a thin film transistor. [Background technology]

[0002] Thin-film transistors are widely used in active-matrix display devices such as liquid crystal displays (LCDs), organic electroluminescence (EL) displays, and electronic paper displays by arranging them in a planar fashion to form thin-film transistor arrays. Planar sensors using thin-film transistor arrays are also being considered as applications for thin-film transistors.

[0003] 2. Description of the Related Art In recent years, studies have been conducted on the manufacture of flexible display devices and sensors by forming thin film transistors on flexible substrates to form flexible thin film transistors.

[0004] Known semiconductor materials used in thin film transistors include inorganic semiconductor materials such as amorphous silicon, polycrystalline silicon, and oxide semiconductors, as well as organic semiconductor materials.

[0005] In particular, organic semiconductor materials are more flexible than inorganic semiconductor materials and can be formed at low temperatures, and are therefore used as semiconductor materials for flexible thin-film transistors using plastic substrates (Non-Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 5489429 [Non-patent literature]

[0007] [Non-Patent Document 1] CDSheraw, L. Zhou, JR Huang, DJ Gundlach, and TN Jackson, “Organic thin-film transistor-driven polymer-dispersed liquid crystal displays on flexible polymeric substrates”, Applied Physics Letters, 80, 1088 (2002). [Non-patent document 2] Asal Kiazadeh, Henrique L. Gomes, Pedro Barquinha, Jorge Martins, Ana Rovisco, Joana V. Pinto, Rodrigo Martins, and Elvira Fortunato, “Improving positive and negative bias illumination stress stability in parylene passivated IGZO transistors”, Applied Physics Letters, 109,051606 (2016). Summary of the Invention [Problem to be solved by the invention]

[0008] However, although organic thin-film transistors using organic semiconductor materials have the advantages of being able to be formed at low temperatures and having high flexibility, the characteristics of the organic thin-film transistors are not sufficient due to the low mobility of the organic semiconductor materials.

[0009] Furthermore, thin-film transistors using silicon-based and oxide-based semiconductors can achieve high performance, but because they use a combination of an insulating layer made of inorganic material and a semiconductor, it is difficult to achieve high flexibility.

[0010] To solve these problems, a technique is known in which a highly flexible organic insulating material is used as a gate insulating film, and an inorganic insulating material is sandwiched between a semiconductor layer made of a metal oxide material and the gate insulating layer, thereby forming a flexible oxide thin-film transistor (e.g., Patent Document 1).

[0011] It is known that in thin-film transistors using oxide semiconductors, the effects of gases adsorbed on the surface of the semiconductor layer have a significant impact on their characteristics and stability (e.g., Non-Patent Document 2). In order to realize thin-film transistors with high characteristics and reliability, protection of the semiconductor layer from the outside world is a very important factor.

[0012] An object of the present invention is to provide a thin film transistor having good device characteristics and high flexibility, a thin film transistor array, and a method for manufacturing the thin film transistor. [Means for solving the problem]

[0013] In order to solve the above problems, one representative thin film transistor of the present invention has an insulating substrate, a gate electrode, a first gate insulating layer, a second gate insulating layer, a semiconductor layer, an insulating protective layer, and a source electrode and a drain electrode, wherein the first gate insulating layer is made of an insulating material containing an organic material, the second gate insulating layer is made of an inorganic insulating material, the thickness of the second gate insulating layer is thinner than the thickness of the first gate insulating layer, and the second gate insulating layer is formed only in an area overlapping with the semiconductor layer or the protective layer. [Effects of the Invention]

[0014] According to the present invention, it is possible to provide a thin film transistor having good element characteristics and high flexibility, a thin film transistor array, and a method for manufacturing a thin film transistor. Problems, configurations, and effects other than those described above will become apparent from the following description of the preferred embodiments. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a schematic cross-sectional view and a schematic plan view of a thin film transistor according to a first embodiment of the present invention. [Figure 2] 2A to 2C are schematic cross-sectional views illustrating a manufacturing process of the thin film transistor according to the first embodiment of the present invention. [Figure 3] FIG. 3 is a schematic plan view of the thin film transistor array according to the first embodiment of the present invention. [Figure 4] FIG. 4 is a schematic cross-sectional view of a region where gate electrode wiring and source electrode wiring of the thin film transistor array according to the first embodiment of the present invention intersect. [Figure 5] FIG. 5 is a schematic cross-sectional view of a thin film transistor according to a second embodiment of the present invention. [Figure 6] 6A to 6C are schematic cross-sectional views illustrating a manufacturing process of a thin film transistor according to the second embodiment of the present invention. [Figure 7] FIG. 7 is a schematic cross-sectional view of a thin film transistor according to a third embodiment of the present invention. [Figure 8] FIG. 8 is a schematic cross-sectional view of a thin film transistor according to a fourth embodiment of the present invention. [Figure 9] FIG. 9 is a schematic cross-sectional view of a thin film transistor according to Comparative Example 1. As shown in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view of a thin film transistor according to Comparative Example 2. As shown in FIG. [Figure 11] FIG. 11 is a diagram showing the transfer characteristics of the thin film transistor according to the embodiment of the present invention. [Figure 12] FIG. 12 is a diagram showing the transfer characteristics of a thin film transistor according to a comparative example. [Figure 13] FIG. 13 is a diagram showing the transfer characteristics of thin film transistors according to the example and comparative example of the present invention in a bent state. [Figure 14] FIG. 14 is a diagram showing the transfer characteristics of the thin film transistor according to Example 4 of the present invention. [Figure 15] FIG. 15 is a diagram showing the transfer characteristics of the thin film transistor according to Example 5 of the present invention. [Figure 16] FIG. 16 is a diagram showing the transfer characteristics of the thin film transistor according to Example 6 of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the present invention is not limited to this embodiment. In addition, in the description of the drawings, the same parts are designated by the same reference numerals.

[0017] (First embodiment) Fig. 1(a) is a schematic cross-sectional view showing a thin-film transistor 100 according to a first embodiment of the present invention, and Fig. 1(b) is a schematic plan view showing the thin-film transistor 100. Fig. 1(a) shows a cross section taken along line AB in Fig. 1(b).

[0018] The thin film transistor 100 comprises at least an insulating substrate 1, a gate electrode 2, a first gate insulating layer 3, a second gate insulating layer 4, a semiconductor layer 5, an insulating protective layer 6, a source electrode 7, and a drain electrode 8.

[0019] 1, in the thin film transistor 100, a gate electrode 2 is formed on a substrate 1, a first gate insulating layer 3 is formed on the gate electrode 2, a second gate insulating layer 4 is formed on the first gate insulating layer 3, a semiconductor layer 5 is formed on the second gate insulating layer 4, a protective layer 6 is formed on the semiconductor layer 5, and a source electrode 7 and a drain electrode 8 are formed on the protective layer 6 so as to be connected to the semiconductor layer 5. The second gate insulating layer 4 is formed only in an area overlapping with the semiconductor layer 5 or the protective layer 6.

[0020] The first gate insulating layer 3 is formed from a material mainly composed of an organic material, and the second gate insulating layer 4 is formed from an inorganic material. By forming the second gate insulating layer 4 in contact with the semiconductor layer 5 from an inorganic material in this way, it is possible to maintain a good interface between the gate insulating layer and the semiconductor layer 5, and high transistor characteristics can be achieved. Furthermore, by patterning the second gate insulating layer 4 so that it is formed only in the area that overlaps with the semiconductor layer 5 or the protective layer 6, flexibility can be improved.

[0021] Furthermore, thin film transistors 100 can be arranged to form a thin film transistor array, which can be used as an electronic device such as an image display device, a sensor, etc. When used as an electronic device, an interlayer insulating film, a pixel electrode, a sensor electrode, a counter electrode, and a counter second substrate (not shown) can be provided, and these structures can be changed as appropriate depending on the type of electronic device to be manufactured.

[0022] Hereinafter, each component of the thin film transistor 100 will be described together with a method for manufacturing the thin film transistor 100 using FIG.

[0023] First, a substrate 1 is prepared as shown in Fig. 2(a). Materials that can be used for the substrate 1 include, but are not limited to, polycarbonate, polyethylene sulfide, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, cycloolefin polymer, ethylene-tetrafluoroethylene copolymer resin, glass fiber reinforced acrylic resin film, polyimide, fluorine-based resin, and thin glass. These materials may be used alone, or two or more types may be laminated to form a composite substrate 1.

[0024] When the substrate 1 is an organic film, a gas barrier layer (not shown) may be formed to improve the durability of the thin film transistor 100. Materials for the gas barrier layer include aluminum oxide (Al2O3), silicon oxide (SiO x ), silicon nitride (SiN xExamples of suitable gas barrier layers include, but are not limited to, silicon oxynitride (SiON), silicon carbide (SiC), and diamond-like carbon (DLC). Two or more of these gas barrier layers can also be stacked. The gas barrier layer can be formed on either one side of the substrate 1 using an organic film, or on both sides. The gas barrier layer can be formed using, but is not limited to, vacuum deposition, ion plating, sputtering, laser ablation, plasma CVD (Chemical Vapor Deposition), hot-wire CVD, and sol-gel methods.

[0025] 2(a), a gate electrode 2 is formed on the substrate 1. The gate electrode 2, source electrode 7, and drain electrode 8 of the thin film transistor do not need to be clearly separated into electrode portions and wiring portions, and hereinafter, as components of the thin film transistor 100, they are referred to as electrodes, including wiring portions.

[0026] The gate electrode 2 can be made of metal materials such as silver (Ag), aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), tungsten (W), manganese (Mn), niobium (Nb), and tantalum (Ta). Conductive metal oxide materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) can also be used. These materials can be used as a single layer, a laminate, or an alloy. Aluminum alloys are preferred because of their high flexibility, conductivity, and processability, but are not limited thereto.

[0027] The gate electrode 2 can be formed by, but is not limited to, vacuum film formation methods such as vacuum deposition and sputtering, a sol-gel method using a precursor of a conductive material, or a wet film formation method such as screen printing, relief printing, or inkjet printing using nanoparticles as an ink. The gate electrode 2 can be patterned, for example, by using photolithography to protect the pattern formation area with a resist or the like and then removing unnecessary areas by etching, or by directly patterning using a printing method or the like. However, the method is not limited to these, and any known patterning method can be used.

[0028] 2(b), a first gate insulating layer 3 is formed on the gate electrode 2. The first gate insulating layer 3 is provided at least on the gate electrode 2 to electrically insulate the gate electrode 2 from electrodes such as the source electrode 7 and the drain electrode 8, and the semiconductor layer 5, but may also be provided on the entire surface of the substrate 1 except for the portion of the gate electrode 2 that is connected to the outside.

[0029] The first gate insulating layer 3 is made of an insulating material containing an organic insulating material. Examples of organic insulating materials that can be used include organic insulating resin materials such as acrylic resins such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), epoxy resins, polyimides, and parylene. These materials may be used in a single layer or in a laminate of two or more layers. They may also be used as a thin film of a copolymer thereof or an inorganic-organic resin hybrid material to which an inorganic material is added, or may have a composition gradient in the growth direction. In particular, photoreactive resin materials that can be patterned by photolithography are suitable for use. Furthermore, by subjecting the surface of the first gate insulating layer 3 to a surface treatment such as ultraviolet irradiation or a self-assembled monolayer, the surface energy of the first gate insulating layer 3 can be controlled, thereby improving adhesion to the second gate insulating layer formed on the first gate insulating layer.

[0030] The first gate insulating layer 3 can be formed by a wet film formation method such as spin coating, slit coating, etc. For patterning, a known general method can be used, but when a photoreactive resin material is used as the material for the first gate insulating layer 3, patterning can be performed by exposure and development using a photolithography method, and such a method can be preferably used.

[0031] In order to electrically insulate the gate electrode 2 from other electrodes, the first gate insulating layer 3 must completely cover at least the gate electrode 2 except for the portion of the gate electrode 2 that is connected to the outside. The thickness of the first gate insulating layer 3 is preferably 0.2 μm to 1.2 μm, and more preferably 0.5 μm to 1.0 μm.

[0032] (Film thickness measurement) The film thickness can be measured by known general methods such as measuring with a stylus profilometer, measuring with an atomic force microscope (AFM), or cutting the substrate and observing the cross section with a scanning electron microscope (SEM). However, these methods can be appropriately selected depending on the size and shape of the sample and the range of film thickness.

[0033] The first gate insulating layer 3 has a resistivity of 10 11 Ωcm or more, preferably 10 14 It is desirable that the relative dielectric constant of the first gate insulating layer 3 is Ωcm or more. The relative dielectric constant of the first gate insulating layer 3 is preferably about 2.0 to 5.0.

[0034] (resistivity measurement) The resistivity can be measured by fabricating a capacitor element for measurement, which has electrodes formed above and below the first gate insulating layer 3, separately from the thin film transistor 100 of the present invention, and measuring the current value when a voltage is applied to the upper and lower electrodes.

[0035] (Measurement of relative permittivity) The dielectric constant can be measured using the same capacitor element as in the resistivity measurement. Specifically, a voltage at a desired frequency is applied to the capacitor element to be measured using an LCR meter or the like, and the capacitance at that time is measured, thereby allowing the dielectric constant to be calculated.

[0036] Next, a second gate insulating layer 4 is formed on the first gate insulating layer 3. For the second gate insulating layer 4, an inorganic insulating material such as silicon oxide, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, zirconium oxide, or silicon nitride can be used. These may be used as a single layer, a laminate of two or more layers, or a mixture of these. Furthermore, the composition may be graded in the growth direction.

[0037] The second gate insulating layer 4 can be formed by a vacuum film formation method such as sputtering, atomic layer deposition (ALD), pulsed laser deposition (PLD), or chemical vapor deposition (CVD), or a wet film formation method such as a sol-gel method using an organometallic compound as a precursor.

[0038] As mentioned above, since the second gate insulating layer 4 is made of an inorganic insulating material, if the second gate insulating layer 4 is too thick, strain caused by bending the thin-film transistor 100 of the present invention may cause cracks and lead to destruction. Therefore, it is preferable to set the thickness of the second gate insulating layer 4 thin. By reducing the thickness of the second gate insulating layer 4, strain can be reduced and the flexibility of the thin-film transistor 100 can be increased. However, although this may vary somewhat depending on the method for forming the second gate insulating layer 4, if the thickness is too thin, it becomes difficult to form the film and to ensure the stability of the manufacturing process. Therefore, the thickness of the second gate insulating layer 4 is preferably approximately 2 nm to 100 nm, and more preferably 5 nm to 50 nm.

[0039] The second gate insulating layer 4 preferably has a resistivity of 10 10 Ωcm or more, preferably 1013 The dielectric constant is preferably Ωcm or more. The dielectric constant is preferably 3 to 25. It is known that the higher the dielectric constant of a gate insulating layer in a thin-film transistor, the greater the capacitance and the greater the amount of induced charge, resulting in better device characteristics for a given film thickness. However, in this embodiment, the film thickness of the second gate insulating layer 4 is set sufficiently thinner than the film thickness of the first gate insulating layer 3, and the effect on the capacitance of the entire gate insulating layer is not significant. Therefore, as long as the second gate insulating layer 4 has the resistivity and dielectric constant described above within the film thickness range, the effect of the second gate insulating layer 4 is not particularly impaired even if the film thickness is thin.

[0040] Next, as shown in FIG. 2(c), a semiconductor layer 5 is formed on the second gate insulating layer 4. The semiconductor layer 5 can be made of an oxide of a metal selected from indium, gallium, zinc, and tin, amorphous silicon, microcrystalline silicon, or the like. Examples of metal oxide materials that can be used include indium oxide, zinc oxide, gallium oxide, tin oxide, indium zinc oxide, indium gallium oxide, and indium gallium zinc oxide. Furthermore, these metal oxides can also be mixed with other metal elements, such as aluminum, zirconium, hafnium, tungsten, and magnesium.

[0041] The semiconductor layer 5 may be an amorphous film, or may be a microcrystalline film or a polycrystalline film. When a microcrystalline film or a polycrystalline film is used, the film formation conditions for the semiconductor layer 5 may be adjusted to form a microcrystalline film or a polycrystalline film, or a method may be used in which an amorphous film is formed and then subjected to a heat treatment or the like to form a microcrystalline or polycrystalline film. The crystallinity of the semiconductor layer 5 can be measured using an X-ray diffraction method (XRD method) or the like, and the crystallinity of an amorphous, microcrystalline, or polycrystalline film can be evaluated by a known general method.

[0042] The semiconductor layer 5 can be formed using a vacuum film formation method such as sputtering, atomic layer deposition (ALD), pulsed laser deposition (PLD), or chemical vapor deposition (CVD), or a wet film formation method such as a sol-gel method using an organometallic compound as a precursor.

[0043] The device characteristics of the thin-film transistor 100 can be adjusted by adjusting the carrier concentration of the semiconductor layer 5 to a desired value using various means. For example, when the semiconductor layer 5 is a metal oxide, the carrier concentration can be adjusted by adjusting the oxygen concentration during film formation to adjust oxygen vacancies in the film. The carrier concentration can also be changed by changing the metal composition ratio of the metal oxide, and can be adjusted appropriately depending on the metal elements used. Furthermore, the carrier concentration may be adjusted to an optimum value by performing a heat treatment after the semiconductor layer 5 is formed.

[0044] The region of the semiconductor layer 5 in the thin-film transistor 100 that serves as the channel region of the transistor is an extremely thin region at the interface of the semiconductor layer 5 that contacts the second gate insulating layer 4 in the film thickness direction of the semiconductor layer 5. Therefore, it is necessary to maintain a good interface between the second gate insulating layer 4 and the semiconductor layer 5. Specifically, the surface roughness (Ra) of the interface between the second gate insulating layer and the semiconductor layer 5 is preferably 2 nm or less, and more preferably 1 nm or less.

[0045] As mentioned above, the region that functions as a channel in the thickness direction of the semiconductor layer 5 is an extremely thin region, and it is possible for the semiconductor layer 5 to function as a transistor even with an extremely thin film thickness. However, in order to form a semiconductor layer 5 with stable film quality, the thickness of the semiconductor layer 5 is preferably 5 nm to 100 nm, more preferably 15 nm to 40 nm.

[0046] Furthermore, if the semiconductor layer 5 is present over the entire surface of the substrate, leakage current may occur between adjacent thin film transistors when the thin film transistors 100 are assembled into a thin film transistor array. Therefore, it is preferable to pattern the semiconductor layer 5 as shown in FIG. 2(d). In the process of patterning the second gate insulating layer 4 described below, in order to minimize the area where the second gate insulating layer 4 is formed, it is preferable to pattern the area where the semiconductor layer 5 is formed as small as possible. However, the semiconductor layer 5 must be patterned so as to have at least the channel region of the thin film transistor 100 and connection portions with the source electrode 7 and the drain electrode 8. The semiconductor layer 5 can be patterned using a known method, and a method such as photolithography is preferably used.

[0047] Next, as shown in FIG. 2( e), a protective layer 6 is formed on the semiconductor layer 5. The protective layer 6 is formed to cover at least the channel region of the semiconductor layer 5 in a planar view in order to protect the back channel portion of the semiconductor layer 5. The back channel portion is a region that becomes the surface of the semiconductor layer 5 when the semiconductor layer 5 is formed, on the side opposite to the interface where the channel is formed. It is known that exposure of this back channel portion to chemical substances or adsorption of gases in the atmosphere can affect the electronic state of the semiconductor layer 5. Therefore, protecting the back channel portion of the semiconductor layer 5 with the protective layer 6 and maintaining it in good condition is extremely important for achieving good device characteristics.

[0048] Furthermore, when the thin-film transistor 100 is used as a thin-film transistor array, a second gate insulating layer 4 and a protective layer 6 can be formed in the region where electrode wiring, such as gate electrode wiring and source electrode wiring, intersect. FIG. 3 shows a schematic plan view of the thin-film transistor array, and FIG. 4 shows a schematic cross-sectional view of the region where the gate electrode wiring and source electrode wiring of the thin-film transistor array intersect. FIG. 4 shows the cross section taken along CD in FIG. 3. In the region where the gate electrode wiring 2 and the source electrode wiring 7 intersect, in addition to the first gate insulating layer 3, a second gate insulating layer 4 and a protective layer 6 are formed. This can improve the insulation of the region where these electrode wirings intersect.

[0049] An insulating material is used for the protective layer 6. Examples of suitable insulating materials include inorganic insulating materials such as silicon oxide, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, zirconium oxide, and silicon nitride, as well as organic insulating resin materials such as acrylic resins such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), epoxy resins, polyimide, and parylene. These materials may be used as a single layer or as a laminate of two or more layers. They may also be used as a thin film of a mixture or copolymer of these materials, a hybrid material of inorganic material and organic resin, or a material with a composition gradient in the growth direction. When the protective layer 6 is formed by laminating an oxide insulating material and an organic insulating material, the order of lamination is not particularly specified. However, a suitable method is to form the inorganic material, then the organic material, and then pattern the inorganic material using the organic material as a mask.

[0050] The protective layer 6 has a resistivity of 10 11 Ωcm or more, preferably 10 14 It is desirable that the resistance be Ωcm or more.

[0051] When an organic material is used, the protective layer 6 preferably has a thickness equal to or less than that of the first gate insulating layer 3. When an inorganic material is used, the protective layer 6 preferably has a thickness equal to that of the second gate insulating layer 4. The protective layer 6 preferably has a forward tapered pattern at its ends. By making the pattern ends forward tapered, disconnection of the source electrode 7 and the drain electrode 8 formed on the protective layer 6 can be prevented.

[0052] The protective layer 6 can be formed by a vacuum film formation method such as sputtering, CVD, ALD, or PLD, or a wet film formation method such as spin coating, slit coating, or printing, depending on the material.

[0053] After forming the protective layer 6, as shown in FIG. 2(f), the second gate insulating layer 4 is patterned to match the region where the protective layer 6 or the semiconductor layer 5 is formed. The second gate insulating layer 4 may be patterned by forming a resist or the like on the semiconductor layer 5 and the protective layer 6 and using the resist as a mask, or by using the semiconductor layer 5 and the protective layer 6 as a mask. When etching is performed using the semiconductor layer 5 and the protective layer 6 as a mask, the step of forming a resist or the like on the semiconductor layer 5 and the protective layer 6 can be omitted. The etching of the second gate insulating layer 4 can be performed by a method suited to the material of the second gate insulating layer. For example, dry etching methods such as reactive ion etching (RIE) and plasma etching (PE) may be used, or wet etching using an etching solution may be used. Any known method can be used.

[0054] Because the thin film transistor 100 has high flexibility, large distortion occurs when the thin film transistor 100 is bent. Therefore, by patterning the second gate insulating layer 4 formed using an inorganic material so that the area where the second gate insulating layer 4 is formed is as small as possible, distortion of the second gate insulating layer 4 when bent can be reduced, and it becomes possible to prevent damage to the element when the thin film transistor 100 is bent.

[0055] By patterning the second gate insulating layer 4 after forming the protective layer 6, it is possible to prevent damage and contamination from occurring on the surface of the second gate insulating layer 4 during patterning, and also to prevent damage from occurring on the back channel portion, which is the surface of the semiconductor layer 5. By maintaining good conditions at the interface between the second gate insulating layer 4 and the semiconductor layer 5 and in the back channel portion of the semiconductor layer 5, it is possible to realize a thin film transistor 100 with good device characteristics.

[0056] 2(g), the source electrode 7 and the drain electrode 8 are formed. The source electrode 7 and the drain electrode 8 can be formed using the same material and method as the gate electrode 2 described above.

[0057] The source electrode 7 and the drain electrode 8 are formed so as to be spaced apart from each other and connected to the semiconductor layer 5. The source electrode 7 and the drain electrode 8 may be formed separately using different materials, but considering the time and effort required for the formation process, it is preferable to form them simultaneously using the same material. Furthermore, in order to reduce the contact resistance between the source electrode 7 and the drain electrode 8 and the semiconductor layer 5, it is also possible to perform surface treatment such as plasma treatment on the connection portions of the semiconductor layer 5 with the source electrode 7 and the drain electrode 8 before forming the source electrode 7 and the drain electrode 8.

[0058] (Second embodiment) FIG. 5 is a schematic cross-sectional view showing a thin film transistor 101 according to a second embodiment of the present invention.

[0059] 5, the thin film transistor 101 has the same configuration as the thin film transistor 100, except that the protective layer 6 in the thin film transistor 100 is formed of a first protective layer 6a and a second protective layer 6b.

[0060] A method for manufacturing the thin film transistor 101 will be described below with reference to FIG. After the semiconductor layer 5 is formed, a first protective layer 6a is formed as shown in FIG. 6(e1). The first protective layer 6a can be formed using the same material as the second gate insulating layer 4. Furthermore, the first protective layer 6a can be formed using the same method as the second gate insulating layer 4.

[0061] After the first protective layer 6a is formed, the second protective layer 6b is formed as shown in Fig. 6(e2). The second protective layer 6b can be formed using the same material as the protective layer 6 in the thin film transistor 100. Furthermore, the second protective layer 6b can be formed using the same method as the protective layer 6 in the thin film transistor 100.

[0062] After forming the second protective layer 6b, as shown in FIG. 6(f), the first protective layer 6a and the second gate insulating layer 4 are patterned to match the region where the second protective layer 6b or the semiconductor layer 5 is formed. When the first protective layer 6a and the second gate insulating layer 4 are formed using the same material, the first protective layer 6a and the second gate insulating layer 4 can be patterned using the same method. The first protective layer 6a and the second gate insulating layer 4 may be patterned by etching using the semiconductor layer 5 and the second protective layer 6b as a mask.

[0063] Other processes are the same as those for the thin film transistor 100. By forming the first protective layer 6a in contact with the semiconductor layer 5 from an inorganic material in this way, it is possible to maintain a good interface between the protective layer and the semiconductor layer 5, and high transistor characteristics can be achieved.

[0064] (Third embodiment) FIG. 7 is a schematic cross-sectional view showing a thin film transistor 102 according to the third embodiment of the present invention.

[0065] The thin film transistor 102 comprises at least an insulating substrate 1, a gate electrode 2, a first gate insulating layer 3, a second gate insulating layer 4, a semiconductor layer 5, an insulating protective layer 6, a source electrode 7, and a drain electrode 8.

[0066] 7, in the thin film transistor 102, a gate electrode 2 is formed on a substrate 1, a first gate insulating layer 3 is formed on the gate electrode 2, a second gate insulating layer 4 is formed on the first gate insulating layer 3, a semiconductor layer 5 is formed on the second gate insulating layer 4, a protective layer 6 is formed on the semiconductor layer 5, and a source electrode 7 and a drain electrode 8 are formed on the protective layer 6 so as to be connected to the semiconductor layer 5. The second gate insulating layer 4 is formed only in an area overlapping with the semiconductor layer 5 or the protective layer 6.

[0067] FIG. 7(a) is a schematic cross-sectional view showing a thin-film transistor 102 in which the second gate insulating layer 4 is formed only in the area where it overlaps with the semiconductor layer 5, and FIG. 7(b) is a schematic cross-sectional view showing a thin-film transistor 102 in which the second gate insulating layer 4 is formed only in the area where it overlaps with the protective layer 6.

[0068] The first gate insulating layer 3 is formed from a material mainly composed of an organic material, and the second gate insulating layer 4 is formed from an inorganic material. By forming the second gate insulating layer 4 in contact with the semiconductor layer 5 from an inorganic material in this way, it is possible to maintain a good interface between the gate insulating layer and the semiconductor layer 5, and high transistor characteristics can be achieved. Furthermore, by patterning the second gate insulating layer 4 so that it is formed only in the area that overlaps with the semiconductor layer 5 or the protective layer 6, flexibility can be improved.

[0069] The protective layer 6 is made of a material primarily composed of a highly flexible organic material, which prevents cracking or peeling even when the thin film transistor is bent, thereby improving the flexibility of the thin film transistor. Furthermore, the inclusion of fluorine effectively blocks external gases that affect the semiconductor layer surface, thereby achieving high transistor characteristics.

[0070] Furthermore, thin film transistors 102 can be arranged to form a thin film transistor array, which can be used in electronic devices such as image display devices, sensors, etc. When used as an electronic device, an interlayer insulating film, a pixel electrode, a sensor electrode, a counter electrode, and a counter second substrate (not shown) can be provided, and these structures can be changed as appropriate depending on the type of electronic device to be manufactured.

[0071] Hereinafter, each component of the thin film transistor 102 will be described together with a method for manufacturing the thin film transistor 102.

[0072] First, a substrate 1 is prepared. Materials that can be used for the substrate 1 include, but are not limited to, polycarbonate, polyethylene sulfide, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, cycloolefin polymer, ethylene-tetrafluoroethylene copolymer resin, glass fiber reinforced acrylic resin film, polyimide, fluorine-based resin, and thin glass. These materials may be used alone, or two or more types may be laminated to form a composite substrate 1.

[0073] When the substrate 1 is an organic film, a gas barrier layer (not shown) may be formed to improve the durability of the thin film transistor 102. Materials for the gas barrier layer include aluminum oxide (Al2O3), silicon oxide (SiO x ), silicon nitride (SiN xExamples of suitable gas barrier layers include, but are not limited to, silicon oxynitride (SiON), silicon carbide (SiC), and diamond-like carbon (DLC). Two or more of these gas barrier layers can also be stacked. The gas barrier layer can be formed on either one side of the substrate 1 using an organic film, or on both sides. The gas barrier layer can be formed using, but is not limited to, vacuum deposition, ion plating, sputtering, laser ablation, plasma CVD (Chemical Vapor Deposition), hot-wire CVD, and sol-gel methods.

[0074] Next, a gate electrode 2 is formed on the substrate 1. The gate electrode 2, source electrode 7, and drain electrode 8 of the thin film transistor do not need to be clearly separated into electrode portions and wiring portions, and hereinafter, as components of the thin film transistor 102, they will be referred to as electrodes, including the wiring portions.

[0075] The gate electrode 2 can be made of metal materials such as silver (Ag), aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), tungsten (W), manganese (Mn), niobium (Nb), and tantalum (Ta). Conductive metal oxide materials such as indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) can also be used. These materials can be used as a single layer, a laminate, or an alloy. Aluminum alloys are preferred because of their high flexibility, conductivity, and processability, but are not limited thereto.

[0076] The gate electrode 2 can be formed by, but is not limited to, vacuum film formation methods such as vacuum deposition and sputtering, a sol-gel method using a precursor of a conductive material, or a wet film formation method such as screen printing, relief printing, or inkjet printing using nanoparticles as an ink. The gate electrode 2 can be patterned, for example, by using photolithography to protect the pattern formation area with a resist or the like and then removing unnecessary areas by etching, or by directly patterning using a printing method or the like. However, the method is not limited to these, and any known patterning method can be used.

[0077] Next, a first gate insulating layer 3 is formed on the gate electrode 2. The first gate insulating layer 3 is provided at least on the gate electrode 2 to electrically insulate the gate electrode 2 from electrodes such as the source electrode 7 and the drain electrode 8, and the semiconductor layer 5, but may also be provided on the entire surface of the substrate 1 except for the portion of the gate electrode 2 that is connected to the outside.

[0078] The first gate insulating layer 3 is made of an insulating material containing an organic insulating material. Examples of organic insulating materials that can be used include organic insulating resin materials such as acrylic resins such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), epoxy resins, polyimides, and parylene. These materials may be used in a single layer or in a laminate of two or more layers. They may also be used as a thin film of a copolymer thereof or an inorganic-organic resin hybrid material to which an inorganic material is added, or may have a composition gradient in the growth direction. In particular, photoreactive resin materials that can be patterned by photolithography are suitable for use. Furthermore, by subjecting the surface of the first gate insulating layer 3 to a surface treatment such as ultraviolet irradiation or a self-assembled monolayer, the surface energy of the first gate insulating layer 3 can be controlled, thereby improving adhesion to the second gate insulating layer formed on the first gate insulating layer.

[0079] The first gate insulating layer 3 can be formed by a wet film formation method such as spin coating, slit coating, etc. For patterning, a known general method can be used, but when a photoreactive resin material is used as the material for the first gate insulating layer 3, patterning can be performed by exposure and development using a photolithography method, and such a method can be preferably used.

[0080] In order to electrically insulate the gate electrode 2 from other electrodes, the first gate insulating layer 3 must completely cover at least the gate electrode 2 except for the portion of the gate electrode 2 that is connected to the outside. The thickness of the first gate insulating layer 3 is preferably 0.2 μm to 1.2 μm, and more preferably 0.4 μm to 1.0 μm.

[0081] (Film thickness measurement) The film thickness can be measured by known general methods such as measuring with a stylus profilometer, measuring with an atomic force microscope (AFM), or cutting the substrate and observing the cross section with a scanning electron microscope (SEM). However, these methods can be appropriately selected depending on the size and shape of the sample and the range of film thickness.

[0082] The first gate insulating layer 3 has a resistivity of 10 11 Ωcm or more, preferably 10 14 It is desirable that the relative dielectric constant of the first gate insulating layer 3 is Ωcm or more. The relative dielectric constant of the first gate insulating layer 3 is preferably about 2.0 to 5.0.

[0083] (resistivity measurement) The resistivity can be measured by fabricating a capacitor element for measurement, which has electrodes formed above and below the first gate insulating layer 3, separately from the thin film transistor 102 of the present invention, and measuring the current value when a voltage is applied to the upper and lower electrodes.

[0084] (Measurement of relative permittivity) The dielectric constant can be measured using the same capacitor element as in the resistivity measurement. Specifically, a voltage at a desired frequency is applied to the capacitor element to be measured using an LCR meter or the like, and the capacitance at that time is measured, thereby allowing the dielectric constant to be calculated.

[0085] Next, a second gate insulating layer 4 is formed on the first gate insulating layer 3. For the second gate insulating layer 4, an inorganic insulating material such as silicon oxide, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, zirconium oxide, or silicon nitride can be used. These may be used as a single layer, a laminate of two or more layers, or a mixture of these. Furthermore, the composition may be graded in the growth direction.

[0086] The second gate insulating layer 4 can be formed by a vacuum film formation method such as sputtering, atomic layer deposition (ALD), pulsed laser deposition (PLD), or chemical vapor deposition (CVD), or a wet film formation method such as a sol-gel method using an organometallic compound as a precursor.

[0087] As mentioned above, since the second gate insulating layer 4 is made of an inorganic insulating material, if the second gate insulating layer 4 is too thick, strain caused by bending the thin-film transistor 102 of the present invention may cause cracks and lead to destruction. Therefore, it is preferable to set the thickness of the second gate insulating layer 4 thin. By reducing the thickness of the second gate insulating layer 4, strain can be reduced and the flexibility of the thin-film transistor 102 can be increased. However, although this may vary somewhat depending on the method for forming the second gate insulating layer 4, if the thickness is too thin, it becomes difficult to form the film and ensure the stability of the manufacturing process. Therefore, the thickness of the second gate insulating layer 4 is preferably approximately 2 nm to 100 nm, and more preferably 5 nm to 50 nm.

[0088] The second gate insulating layer 4 preferably has a resistivity of 10 10 Ωcm or more, preferably 1013 The dielectric constant is preferably Ωcm or more. The dielectric constant is preferably 3 to 25. It is known that the higher the dielectric constant of a gate insulating layer in a thin-film transistor, the greater the capacitance and the greater the amount of induced charge, resulting in better device characteristics for a given film thickness. However, in this embodiment, the film thickness of the second gate insulating layer 4 is set sufficiently thinner than the film thickness of the first gate insulating layer 3, and the effect on the capacitance of the entire gate insulating layer is not significant. Therefore, as long as the second gate insulating layer 4 has the resistivity and dielectric constant described above within the film thickness range, the effect of the second gate insulating layer 4 is not particularly impaired even if the film thickness is thin.

[0089] Next, a semiconductor layer 5 is formed on the second gate insulating layer 4. For the semiconductor layer 5, an oxide of a metal selected from indium, gallium, zinc, and tin, amorphous silicon, microcrystalline silicon, or the like can be used. Examples of metal oxide materials that can be used include indium oxide, zinc oxide, gallium oxide, tin oxide, indium zinc oxide, indium gallium oxide, and indium gallium zinc oxide. Furthermore, these metal oxides can also be mixed with other metal elements, such as aluminum, zirconium, hafnium, tungsten, and magnesium.

[0090] The semiconductor layer 5 may be an amorphous film, or may be a microcrystalline film or a polycrystalline film. When a microcrystalline film or a polycrystalline film is used, the film formation conditions for the semiconductor layer 5 may be adjusted to form a microcrystalline film or a polycrystalline film, or a method may be used in which an amorphous film is formed and then subjected to a heat treatment or the like to form a microcrystalline or polycrystalline film. The crystallinity of the semiconductor layer 5 can be measured using an X-ray diffraction method (XRD method) or the like, and the crystallinity of an amorphous, microcrystalline, or polycrystalline film can be evaluated by a known general method.

[0091] The semiconductor layer 5 can be formed using a vacuum film formation method such as sputtering, atomic layer deposition (ALD), pulsed laser deposition (PLD), or chemical vapor deposition (CVD), or a wet film formation method such as a sol-gel method using an organometallic compound as a precursor.

[0092] The device characteristics of the thin film transistor 102 can be adjusted by adjusting the carrier concentration of the semiconductor layer 5 to a desired value using various means. For example, when the semiconductor layer 5 is a metal oxide, the carrier concentration can be adjusted by adjusting the oxygen concentration during film formation to adjust oxygen vacancies in the film. The carrier concentration can also be changed by changing the metal composition ratio of the metal oxide, and can be adjusted appropriately depending on the metal elements used. Furthermore, the carrier concentration may be adjusted to an optimum value by performing a heat treatment after the semiconductor layer 5 is formed.

[0093] The region of the semiconductor layer 5 in the thin-film transistor 102 that serves as the channel region of the transistor is an extremely thin region at the interface of the semiconductor layer 5 that contacts the second gate insulating layer 4 in the film thickness direction of the semiconductor layer 5. Therefore, it is necessary to maintain a good interface between the second gate insulating layer 4 and the semiconductor layer 5. Specifically, the surface roughness (Ra) of the interface between the second gate insulating layer and the semiconductor layer 5 is preferably 2 nm or less, and more preferably 1 nm or less.

[0094] As mentioned above, the region that functions as a channel in the thickness direction of the semiconductor layer 5 is an extremely thin region, and it is possible for the semiconductor layer 5 to function as a transistor even with an extremely thin film thickness. However, in order to form a semiconductor layer 5 with stable film quality, the thickness of the semiconductor layer 5 is preferably 5 nm to 100 nm, more preferably 15 nm to 40 nm.

[0095] Furthermore, with regard to the region where the semiconductor layer 5 is formed, if the semiconductor layer 5 is present over the entire surface of the substrate, there is a risk of leakage current occurring between adjacent thin film transistors when the thin film transistors 102 are formed into a thin film transistor array. Therefore, it is preferable to pattern the semiconductor layer 5. In the step of patterning the second gate insulating layer 4 described below, in order to minimize the region where the second gate insulating layer 4 is formed, it is preferable to pattern the region where the semiconductor layer 5 is formed as small as possible. However, the semiconductor layer 5 needs to be patterned so as to have at least the channel region of the thin film transistor 102 and connection portions with the source electrode 7 and the drain electrode 8. The semiconductor layer 5 can be patterned using a known method, and a method such as photolithography is preferably used.

[0096] After the semiconductor layer 5 is formed, the second gate insulating layer 4 is patterned to match the region where the semiconductor layer 5 is formed. The second gate insulating layer 4 may be patterned by etching using the resist used for patterning the semiconductor layer 5 as a mask. A method suited to the material of the second gate insulating layer 4 can be selected for etching the second gate insulating layer 4. For example, a dry etching method such as reactive ion etching (RIE) or plasma etching (PE) may be used, or a wet etching method using an etching solution may be used, and any known general method may be used.

[0097] Because the thin film transistor 102 has high flexibility, large distortion occurs when the thin film transistor 102 is bent. Therefore, by patterning the second gate insulating layer 4 formed using an inorganic material so that the area where the second gate insulating layer 4 is formed is made as small as possible, distortion of the second gate insulating layer 4 when bent can be reduced, and it becomes possible to prevent damage to the element when the thin film transistor 102 is bent.

[0098] Patterning the second gate insulating layer 4 after forming the semiconductor layer 5 can prevent damage and contamination during patterning on the surface of the second gate insulating layer 4. Furthermore, maintaining a good state of the interface between the second gate insulating layer 4 and the semiconductor layer 5 makes it possible to realize a thin film transistor 102 with good device characteristics.

[0099] Next, a protective layer 6 is formed on the semiconductor layer 5. The protective layer 6 is formed to cover at least the channel region of the semiconductor layer 5 in a planar view in order to protect the back channel portion of the semiconductor layer 5. The back channel portion is a region that becomes the surface of the semiconductor layer 5 when the semiconductor layer 5 is formed, on the side opposite to the interface where the channel is formed in the semiconductor layer 5. It is known that exposure of this back channel portion to chemical substances or adsorption of gases in the atmosphere can affect the electronic state of the semiconductor layer 5. Therefore, protecting the back channel portion of the semiconductor layer 5 with the protective layer 6 and maintaining it in good condition is very important for achieving good device characteristics.

[0100] Furthermore, when the thin film transistor 102 is used as a thin film transistor array, the second gate insulating layer 4 and the protective layer 6 can be formed in the region where electrode wirings such as the gate electrode wiring and the source electrode wiring intersect, thereby improving the insulation properties of the region where these electrode wirings intersect.

[0101] The protective layer 6 is made of an insulating organic material containing fluorine. Examples of suitable organic insulating resin materials include acrylic resins such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), epoxy resins, polyimide, parylene, and fluororesins. These materials may be used as a single layer or as a laminate of two or more layers. They may also be used as a thin film of a mixture or copolymer of these materials, a hybrid material of an inorganic material and an organic resin, or a material with a composition gradient in the growth direction. Using an insulating organic material for the protective layer 6 allows for high flexibility without cracking the protective layer even when the thin-film transistor 102 is bent.

[0102] The fluorine contained in the protective layer 6 can be a fluororesin, an organic resin containing fluorine as part of its constituents, or an organic resin to which a fluorine-based material has been added. By including fluorine in the protective layer 6, it is possible to effectively prevent external chemical substances, atmospheric water, oxygen, and the like from being adsorbed onto the semiconductor layer 5. In particular, by increasing the fluorine concentration on the surface of the protective layer 6, it is possible to obtain a high level of protection from the outside. Furthermore, when a fluorine-based material is added to an insulating organic material to form the fluorine-containing protective layer 6, a fluorine-based surfactant can be suitably used. Furthermore, it is preferable to use a nonionic surfactant so as not to affect the insulating properties and charge accumulation of the protective layer 6.

[0103] The fluorine contained in the protective layer 6 can be evaluated using a time-of-flight secondary ion mass spectrometer (TOF-SIMS) or the like. In particular, when analyzing the amount of fluorine in the depth direction, it is preferable to use a gas cluster ion gun (GCIB) because fluorine atoms tend to be desorbed by the ion gun used for depth direction analysis, making the analysis difficult. Furthermore, a method for easily estimating the fluorine concentration present on the surface of the protective layer 6 is to measure the surface energy of the protective layer 6. The surface energy can be measured by dropping water or an organic solvent on the surface and calculating from the contact angle. The surface energy of the protective layer 6 is 30 mJ / m 2 Less than or equal to 25 mJ / m 2 It is desirable that the following:

[0104] The protective layer 6 has a resistivity of 10 11 Ωcm or more, preferably 10 14 It is desirable that the resistance be Ωcm or more.

[0105] The thickness of the protective layer 6 is preferably about 0.3 μm or more and 3 μm or less. The shape of the protective layer 6 is preferably such that the edges of the pattern are forward tapered. By making the edges of the pattern forward tapered, it is possible to prevent disconnection of the source electrode 7 and the drain electrode 8 formed on the protective layer 6 and defects in the patterns formed thereon.

[0106] The protective layer 6 can be formed by a wet film forming method such as spin coating, slit coating, or printing, depending on the material.

[0107] Next, the source electrode 7 and the drain electrode 8 are formed. The source electrode 7 and the drain electrode 8 can be formed using the same material and method as the gate electrode 2 described above.

[0108] The source electrode 7 and the drain electrode 8 are formed so as to be spaced apart from each other and connected to the semiconductor layer 5. The source electrode 7 and the drain electrode 8 may be formed separately using different materials, but considering the time and effort required for the formation process, it is preferable to form them simultaneously using the same material. Furthermore, in order to reduce the contact resistance between the source electrode 7 and the drain electrode 8 and the semiconductor layer 5, it is also possible to perform surface treatment such as plasma treatment on the connection portions of the semiconductor layer 5 with the source electrode 7 and the drain electrode 8 before forming the source electrode 7 and the drain electrode 8.

[0109] (Fourth embodiment) FIG. 8 is a schematic cross-sectional view showing a thin film transistor 103 according to a fourth embodiment of the present invention.

[0110] Figure 8(a) is a schematic cross-sectional view showing a thin film transistor 103 in which the second gate insulating layer 4 is formed only in the area where it overlaps with the semiconductor layer 5, and Figure 8(b) is a schematic cross-sectional view showing a thin film transistor 103 in which the second gate insulating layer 4 is formed only in the area where it overlaps with the protective layer 6.

[0111] As shown in FIG. 8, the thin film transistor 103 differs from the thin film transistor 102 in the order in which the protective layer 6, the source electrode 7 and the drain electrode 8 are formed.

[0112] In the thin film transistor 103, the source electrode 7 and the drain electrode 8 are formed after the semiconductor layer 5 is formed. In this case, the source electrode 7 and the drain electrode 8 can be formed by the same method as the source electrode 7 and the drain electrode 8 of the thin film transistor 102 described above. However, when the source electrode 7 and the drain electrode 8 are formed by photolithography, it is necessary to select an agent that does not easily dissolve the semiconductor layer 5 as an etching solution to prevent damage to the semiconductor layer 5 when etching these electrodes. Alternatively, a method such as dry etching can be suitably used to etch the source electrode 7 and the drain electrode 8.

[0113] After forming the source electrode 7 and the drain electrode 8, the protective layer 6 is formed. The protective layer 6 can also be formed by the same method as in the thin film transistor 102 of the third embodiment.

[0114] The protective layer 6 is preferably formed so as to cover at least the semiconductor layer 5, but may be formed on the entire surface of the substrate except for the electrode connection portions and the like.

[0115] Other steps are the same as those for the thin film transistor 102. By forming the source electrode 7 and the drain electrode 8 before forming the protective layer 6 in this way, it becomes possible to set the channel length of the thin film transistor to be short, making it easier to obtain a higher current value.

[0116] When the thin film transistors 100 to 103 are used to form electronic devices such as image display devices and sensor elements, other insulating layers, electrodes, display elements, sensor elements, and a counter substrate are appropriately formed. There are no particular limitations on the materials used for these, but the insulating layers may be formed with materials similar to those used for the first gate insulating layer 3 and the second gate insulating layer 4, and the electrodes may be formed with materials similar to those used for the gate electrode 2. The counter substrate may also be made of a material similar to that used for the substrate 1, but this is not a limitation.

[0117] When the electronic device using the thin film transistors 100 to 103 is an image display device, liquid crystal, electrophoretic particles, organic electroluminescence, etc. can be used as the display element. Image display devices are not limited to either reflective or transmissive types, and these well-known general display elements can be used. Depending on the display element used, it is also possible to use a configuration in which multiple thin film transistors 100 to 103 are installed within one pixel.

[0118] Furthermore, when an electronic device using the thin film transistors 100 to 103 is a sensor element, a material that reacts to temperature or pressure may be connected to any electrode of the thin film transistor as a sensor active layer, or a functional film such as a self-assembled monolayer may be formed on any electrode of the thin film transistor and used as an electrode that reacts to biomolecules, metal ions, etc. Furthermore, a configuration in which multiple thin film transistors 100 to 103 are installed may be used depending on the application of the sensor to be used. [Example]

[0119] Example 1 As Example 1, a thin film transistor 100 shown in FIG. 1 was fabricated.

[0120] As the substrate 1, a polyimide varnish was applied to a non-alkali glass substrate having a thickness of 0.7 mm and baked to form a polyimide film having a thickness of 20 μm.

[0121] An aluminum alloy film was formed on the substrate 1 using DC magnetron sputtering to a thickness of 100 nm, and then patterned into a desired shape using photolithography. Specifically, a photosensitive positive resist OFPR800 (Tokyo Ohka Kogyo Co., Ltd.) was applied, followed by mask exposure and alkaline development to form a resist pattern of the desired shape, and unnecessary portions of the aluminum alloy were etched using an etching solution made of a mixture of phosphoric acid, nitric acid, and acetic acid. The resist film was then removed using a resist stripper to form a gate electrode 2 of the desired shape (hereinafter, this patterning method will be abbreviated as "photolithography").

[0122] A photosensitive acrylic resin was applied to the substrate on which the gate electrode 2 was formed using a slit coating method, and patterned by mask exposure and alkaline development, followed by baking at 230°C to form a first gate insulating layer 3 of the desired shape. The film thickness of the first gate insulating layer 3 after baking was 1.0 μm. The relative dielectric constant of the first gate insulating layer 3 was 3.6.

[0123] On the substrate on which the first gate insulating layer 3 was formed, a second gate insulating layer 4 made of silicon oxide was formed by chemical vapor deposition (CVD) using silane (SiH4) and nitrous oxide (N2O) as raw material gases. The film thickness of the second gate insulating layer 4 was set to 30 nm. The relative dielectric constant of the second gate insulating layer 4 was 5.0.

[0124] Then, on the second gate insulating layer 4, a sputtering method was used to deposit an IGZO thin film with a thickness of 30 nm using a target material having a composition of InGaZnOx (IGZO) and argon (Ar) and oxygen (O2) as sputtering gases, and the film was patterned by photolithography to form a semiconductor layer 5.

[0125] Furthermore, an acrylic resin was applied onto the semiconductor layer 5, patterned by mask exposure and alkaline development, and baked at 230° C. to form a protective layer 6 of a desired shape. The thickness of the protective layer 6 was 0.6 μm.

[0126] Thereafter, the second gate insulating layer 4 was etched by reactive ion etching (RIE) using carbon tetrafluoride (CF4) gas to pattern the second gate insulating layer 4. At this time, the second gate insulating layer 4 that overlaps the semiconductor layer 5 or the protective layer 6 is not etched because the semiconductor layer 5 and the protective layer 6 act as a mask, as shown in FIG. 2(f).

[0127] Thereafter, a molybdenum (Mo) film was formed to a thickness of 150 nm by sputtering, and patterned into a desired shape by photolithography to form a source electrode 7 and a drain electrode 8.

[0128] Through the above steps, the thin film transistor 100 according to the first embodiment of the present invention was fabricated.

[0129] Example 2 As Example 2, a thin film transistor 101 shown in FIG. 5 was fabricated.

[0130] As the substrate 1, a polyimide varnish was applied to a non-alkali glass substrate having a thickness of 0.7 mm and baked to form a polyimide film having a thickness of 20 μm.

[0131] An aluminum alloy film was formed on the substrate 1 to a thickness of 100 nm by DC magnetron sputtering, and the film was patterned into a desired shape by photolithography to form the gate electrode 2.

[0132] A photosensitive acrylic resin was applied to the substrate on which the gate electrode 2 was formed using a slit coating method, and patterned by mask exposure and alkaline development, followed by baking at 230°C to form a first gate insulating layer 3 of the desired shape. The film thickness of the first gate insulating layer 3 after baking was 1.0 μm. The relative dielectric constant of the first gate insulating layer 3 was 3.6.

[0133] Silicon oxide (SiO ) was deposited on the substrate on which the first gate insulating layer 3 was formed by chemical vapor deposition (CVD) using silane (SiH ) and nitrous oxide (NO) as raw material gases. x ) was formed. The film thickness of the second gate insulating layer 4 was set to 30 nm. The relative dielectric constant of the second gate insulating layer 4 was 5.0.

[0134] Then, on the second gate insulating layer 4, a sputtering method was used to deposit an IGZO thin film with a thickness of 30 nm using a target material having a composition of InGaZnOx (IGZO) and argon (Ar) and oxygen (O2) as sputtering gases, and the film was patterned by photolithography to form a semiconductor layer 5.

[0135] Silicon oxide (SiO x After forming a first protective layer 6a made of ) to a thickness of 30 nm, an acrylic resin was applied, and patterning was performed by mask exposure and alkaline development, followed by baking at 230°C to form a second protective layer 6b of a desired shape. The thickness of the second protective layer 6b was set to 0.7 µm.

[0136] Thereafter, the first protective layer 6a and the second gate insulating layer 4 were etched by reactive ion etching (RIE) using carbon tetrafluoride (CF4) gas, and the first protective layer 6a and the second gate insulating layer 4 were patterned.

[0137] Thereafter, a molybdenum (Mo) film was formed to a thickness of 150 nm by sputtering, and patterned into a desired shape by photolithography to form a source electrode 7 and a drain electrode 8.

[0138] Through the above steps, the thin film transistor 101 according to the second embodiment of the present invention was fabricated.

[0139] Example 3 As Example 3, the thin film transistor 100 shown in FIG. 1 was fabricated.

[0140] As the substrate 1, a polyimide varnish was applied to a non-alkali glass substrate having a thickness of 0.7 mm and baked to form a polyimide film having a thickness of 20 μm.

[0141] An aluminum alloy film was formed on the substrate 1 to a thickness of 100 nm by DC magnetron sputtering, and the film was patterned into a desired shape by photolithography to form the gate electrode 2.

[0142] A photosensitive acrylic resin was applied to the substrate on which the gate electrode 2 was formed using a slit coating method, and patterned by mask exposure and alkaline development, followed by baking at 230°C to form a first gate insulating layer 3 of the desired shape. The film thickness of the first gate insulating layer 3 after baking was 0.7 μm. The relative dielectric constant of the first gate insulating layer 3 was 3.6.

[0143] Silicon oxide (SiO ) was deposited on the substrate on which the first gate insulating layer 3 was formed by chemical vapor deposition (CVD) using silane (SiH ) and nitrous oxide (NO) as raw material gases. x) was formed. The film thickness of the second gate insulating layer 4 was set to 10 nm. The relative dielectric constant of the second gate insulating layer 4 was 5.0.

[0144] Then, on the second gate insulating layer 4, a sputtering method was used to deposit an IGZO thin film with a thickness of 30 nm using a target material having a composition of InGaZnOx (IGZO) and argon (Ar) and oxygen (O2) as sputtering gases, and the film was patterned by photolithography to form a semiconductor layer 5.

[0145] Furthermore, an acrylic resin was applied onto the semiconductor layer 5, patterned by mask exposure and alkaline development, and baked at 230° C. to form a protective layer 6 of a desired shape. The thickness of the protective layer 6 was 0.6 μm.

[0146] Thereafter, the second gate insulating layer 4 was etched by reactive ion etching (RIE) using carbon tetrafluoride (CF4) gas, and the second gate insulating layer 4 was patterned.

[0147] Thereafter, a molybdenum (Mo) film was formed to a thickness of 150 nm by sputtering, and patterned into a desired shape by photolithography to form a source electrode 7 and a drain electrode 8.

[0148] Through the above steps, the thin film transistor 100 according to the first embodiment of the present invention was fabricated.

[0149] (Comparative Example 1) As Comparative Example 1, a thin film transistor 200 shown in FIG. 9 was fabricated.

[0150] As the substrate 1, a polyimide varnish was applied to a non-alkali glass substrate having a thickness of 0.7 mm and baked to form a polyimide film having a thickness of 20 μm.

[0151] An aluminum alloy film was formed on the substrate 1 to a thickness of 100 nm by DC magnetron sputtering, and the film was patterned into a desired shape by photolithography to form the gate electrode 2.

[0152] A photosensitive acrylic resin was applied by slit coating onto the substrate on which the gate electrode 2 was formed, and patterning was performed by mask exposure and alkaline development, followed by baking at 230°C to form a first gate insulating layer 3 of a desired shape. The film thickness of the first gate insulating layer 3 after baking was set to 0.7 μm.

[0153] Silicon oxide (SiO ) was deposited on the substrate on which the first gate insulating layer 3 was formed by chemical vapor deposition (CVD) using silane (SiH ) and nitrous oxide (NO) as raw material gases. x ) was formed. The film thickness of the second gate insulating layer 4 was set to 30 nm.

[0154] Then, on the second gate insulating layer 4, a sputtering method was used to deposit an IGZO thin film with a thickness of 30 nm using a target material having a composition of InGaZnOx (IGZO) and argon (Ar) and oxygen (O2) as sputtering gases, and the film was patterned by photolithography to form a semiconductor layer 5.

[0155] Next, an acrylic resin was applied onto the semiconductor layer 5, patterned by mask exposure and alkaline development, and baked at 230° C. to form a protective layer 6 of a desired shape. The thickness of the protective layer 6 was 0.6 μm.

[0156] Thereafter, a molybdenum (Mo) film was formed to a thickness of 150 nm by sputtering, and patterned into a desired shape by photolithography to form a source electrode 7 and a drain electrode 8.

[0157] Through the above steps, the thin film transistor 200 according to Comparative Example 1 was fabricated.

[0158] (Comparative Example 2) As Comparative Example 2, a thin film transistor 201 shown in FIG. 10 was fabricated.

[0159] As the substrate 1, a polyimide varnish was applied to a non-alkali glass substrate having a thickness of 0.7 mm and baked to form a polyimide film having a thickness of 20 μm.

[0160] An aluminum alloy film was formed on the substrate 1 to a thickness of 100 nm by DC magnetron sputtering, and the film was patterned into a desired shape by photolithography to form the gate electrode 2.

[0161] A photosensitive acrylic resin was applied by slit coating onto the substrate on which the gate electrode 2 was formed, and patterning was performed by mask exposure and alkaline development, followed by baking at 230°C to form a first gate insulating layer 3 of a desired shape. The film thickness of the first gate insulating layer 3 after baking was 1.0 μm.

[0162] Then, on the first gate insulating layer 3, a sputtering method was used to deposit an IGZO thin film with a thickness of 30 nm using a target material having a composition of InGaZnOx (IGZO) and argon (Ar) and oxygen (O2) as sputtering gases, and the film was patterned by photolithography to form a semiconductor layer 5.

[0163] Furthermore, an acrylic resin was applied onto the semiconductor layer 5, patterned by mask exposure and alkaline development, and baked at 230° C. to form a protective layer 6 of a desired shape. The thickness of the protective layer 6 was 0.6 μm.

[0164] Thereafter, a molybdenum (Mo) film was formed to a thickness of 150 nm by sputtering, and patterned into a desired shape by photolithography to form a source electrode 7 and a drain electrode 8.

[0165] Through the above steps, a thin film transistor 201 according to Comparative Example 2 was formed.

[0166] Comparison was made between thin film transistors according to Examples 1, 2, and 3, and Comparative Examples 1 and 2, which were fabricated by the above steps. In Examples 1 and 3, the gate insulating layer of the thin film transistor was made up of two layers, a first gate insulating layer 3 and a second gate insulating layer 4, and the region of the second gate insulating layer 4 was defined by the regions of the semiconductor layer 5 and the protective layer 6, and the second gate insulating layer 4 was formed in an island shape.

[0167] In addition, in Example 2, the gate insulating layer is formed in the same manner as in Example 1, and in addition, the protective layer 6 is made up of a first protective layer 6a and a second protective layer 6b, and the first protective layer 6a and the second gate insulating layer 4 are formed to have an island shape.

[0168] The difference between Comparative Example 1 and Examples 1 and 3 is that in Comparative Example 1, the second gate insulating layer 4 is not patterned, and the area of ​​the second gate insulating layer 4 is formed to be sufficiently large relative to the channel region of the thin-film transistor 200.

[0169] Furthermore, the difference between Comparative Example 2 and Examples 1, 2, and 3 is that in Comparative Example 2, the second gate insulating layer 4 is not formed.

[0170] To compare the device characteristics of the thin-film transistors according to Examples 1, 2, and 3 of the present invention and Comparative Examples 1 and 2, the transfer characteristics of the thin-film transistor devices were measured. A semiconductor parameter analyzer B1500A (manufactured by Keysight Technologies) was used to measure the transfer characteristics. In addition, to investigate the flexibility of the fabricated thin-film transistors, the fabricated transistors were wrapped halfway around a metal rod with a specified radius and the transfer characteristics were measured in a bent state.

[0171] 11 and 12 are graphs showing the transfer characteristics of thin film transistors in Examples 1, 2, and 3 of the present invention and Comparative Examples 1 and 2 before bending. Vgs represents the voltage between the gate electrode and source electrode, and Ids represents the current between the drain electrode and source electrode. Measurements were performed by setting the drain voltage to 10 V, the source voltage to 0 V, and sweeping the gate electrode voltage from -20 V to 20 V. The channel size of the measured thin film transistor was 20 μm in length and 50 μm in width.

[0172] 11 and 12, good device characteristics were exhibited in Examples 1, 2, and 3 and Comparative Example 1, but sufficient transistor characteristics could not be obtained in Comparative Example 2. This shows that the second gate insulating layer 4 of the thin film transistor of the present invention has a tremendous effect in obtaining good device characteristics.

[0173] 13 is a graph showing the transfer characteristics measured after bending the thin film transistors of Examples 1, 2, and 3 of the present invention and Comparative Example 1 to a curvature radius R of 1 mm. While Examples 1, 2, and 3 exhibited favorable device characteristics, the thin film transistor 200 of Comparative Example 1 failed to exhibit such characteristics. Observation of the thin film transistor 200 of Comparative Example 1 confirmed that cracks had occurred in the second gate insulating layer 4 due to bending. It is believed that these cracks caused the semiconductor layer, source electrode, and drain electrode to break, resulting in the loss of device characteristics.

[0174] Table 1 shows the results of comparing the device characteristics and flexibility of Examples 1, 2, and 3 of the present invention and Comparative Examples 1 and 2. [Table 1]

[0175] As a result of the experiment, the thin film transistors 100 of Examples 1 and 3 and the thin film transistor 101 of Example 2 of the present invention exhibited good element characteristics even when bent with a small radius of curvature, demonstrating that it is possible to fabricate thin film transistors with extremely high flexibility.

[0176] Example 4 As Example 4, a thin film transistor 102 shown in FIG. 7(a) was fabricated.

[0177] As the substrate 1, a polyimide varnish was applied to a non-alkali glass substrate having a thickness of 0.7 mm and baked to form a polyimide film having a thickness of 20 μm.

[0178] An aluminum alloy film was formed on the substrate 1 using DC magnetron sputtering to a thickness of 100 nm, and then patterned into a desired shape using photolithography. Specifically, a photosensitive positive resist OFPR800LB (Tokyo Ohka Kogyo Co., Ltd.) was applied, followed by mask exposure and alkaline development to form a resist pattern of the desired shape, and unnecessary portions of the aluminum alloy were etched using an etching solution containing a mixture of phosphoric acid, nitric acid, and acetic acid. The resist film was then removed using a resist stripper to form a gate electrode 2 of the desired shape (hereinafter, this patterning method will be abbreviated as "photolithography").

[0179] A photosensitive acrylic resin was applied to the substrate on which the gate electrode 2 was formed using a slit coating method, and patterned by mask exposure and alkaline development, followed by baking at 230°C to form a first gate insulating layer 3 of the desired shape. The film thickness of the first gate insulating layer 3 after baking was 1.0 μm. The relative dielectric constant of this insulating layer was 3.8.

[0180] On the substrate on which the first gate insulating layer 3 was formed, a second gate insulating layer 4 made of silicon oxide was formed by chemical vapor deposition (CVD) using silane (SiH4) and nitrous oxide (N2O) as raw material gases. The film thickness of the second gate insulating layer 4 was set to 10 nm. The relative dielectric constant of the second gate insulating layer 4 was 5.0.

[0181] Then, on the second gate insulating layer 4, a sputtering method was used to deposit an IGZO thin film with a thickness of 30 nm using a target material having a composition of InGaZnOx (IGZO) and argon (Ar) and oxygen (O2) as sputtering gases, and the film was patterned by photolithography to form a semiconductor layer 5.

[0182] The second gate insulating layer 4 was patterned using the resist used to pattern the semiconductor layer 5. The second gate insulating layer 4 was patterned by reactive ion etching using carbon tetrafluoride (CF4) gas.

[0183] Furthermore, a photosensitive acrylic resin solution containing a photosensitive nonionic fluorine-based surfactant was applied onto the semiconductor layer 5, and after the solvent was removed by drying, patterning was performed by mask exposure and alkaline development, and the resulting solution was baked at 230°C to form a protective layer 6 of the desired shape. The thickness of the protective layer 6 was 0.6 μm. The concentration of the fluorine-based surfactant was 2.4% relative to the solid content of the photosensitive acrylic resin solution. Furthermore, in order to measure the surface energy and fluorine concentration of the protective layer 6, the protective layer 6 was formed on a separate substrate and measurements were carried out. The surface energy of the protective layer 6 was found to be 18.8 mJ / m 2 The surface energy was measured by measuring the contact angles of water and diiodomethane using the sessile drop method, and the surface energy was calculated from these values ​​using the Kaelble-Uy method.

[0184] Furthermore, analysis was performed using TOF-SIMS to observe the amount of fluorine in the depth direction of the protective layer 6. An Ar gas cluster ion gun (GCIB) was used for etching to analyze the depth direction. As a result, the amount of fluorine contained in the protective layer 6 was greatest at the surface, and the concentration decreased from the surface to a depth of approximately 30 nm, after which the fluorine concentration remained constant. The amount of fluorine present at the outermost surface was approximately 170 times higher than that at the constant fluorine concentration.

[0185] Thereafter, a molybdenum (Mo) film was formed to a thickness of 150 nm by sputtering, and patterned into a desired shape by photolithography to form a source electrode 7 and a drain electrode 8.

[0186] Through the above steps, the thin film transistor 102 according to the third embodiment of the present invention was fabricated.

[0187] Example 5 As Example 5, a thin film transistor 102 shown in FIG. 7(a) was fabricated.

[0188] As the substrate 1, a polyimide varnish was applied to a non-alkali glass substrate having a thickness of 0.7 mm and baked to form a polyimide film having a thickness of 20 μm.

[0189] An aluminum alloy film was formed on the substrate 1 to a thickness of 100 nm by DC magnetron sputtering, and the film was patterned into a desired shape by photolithography to form the gate electrode 2.

[0190] A photosensitive acrylic resin was applied to the substrate on which the gate electrode 2 was formed using a slit coating method, and patterned by mask exposure and alkaline development, followed by baking at 230°C to form a first gate insulating layer 3 of the desired shape. The film thickness of the first gate insulating layer 3 after baking was 1.0 μm. The relative dielectric constant of this first gate insulating layer 3 was 3.8.

[0191] On the substrate on which the first gate insulating layer 3 was formed, a second gate insulating layer 4 made of silicon oxide was formed by chemical vapor deposition (CVD) using silane (SiH4) and nitrous oxide (N2O) as raw material gases. The film thickness of the second gate insulating layer 4 was set to 10 nm. The relative dielectric constant of the second gate insulating layer 4 was 5.0.

[0192] Then, on the second gate insulating layer 4, a sputtering method was used to deposit an IGZO thin film with a thickness of 30 nm using a target material having a composition of InGaZnOx (IGZO) and argon (Ar) and oxygen (O2) as sputtering gases, and the film was patterned by photolithography to form a semiconductor layer 5.

[0193] The second gate insulating layer 4 was patterned using the resist used to pattern the semiconductor layer 5. The second gate insulating layer 4 was patterned by reactive ion etching using carbon tetrafluoride (CF4) gas.

[0194] Furthermore, a photosensitive acrylic resin solution containing a photosensitive nonionic fluorine-based surfactant was applied onto the semiconductor layer 5, and after the solvent was removed by drying, patterning was performed by mask exposure and alkaline development, and the resulting solution was baked at 230°C to form a protective layer 6 of the desired shape. The thickness of the protective layer 6 was 0.6 μm. The concentration of the fluorine-based surfactant was 0.7% relative to the solid content of the photosensitive acrylic resin solution. Furthermore, in order to measure the surface energy and fluorine concentration of the protective layer 6, the protective layer 6 was formed on a separate substrate and measurements were carried out. The surface energy of the protective layer 6 was found to be 24.5 mJ / m 2 The surface energy was measured by measuring the contact angles of water and diiodomethane using the sessile drop method, and the surface energy was calculated from these values ​​using the Kaelble-Uy method.

[0195] Furthermore, analysis was performed using TOF-SIMS to observe the amount of fluorine in the depth direction of the protective layer 6. An Ar gas cluster ion gun (GCIB) was used for etching to analyze the depth direction. As a result, the amount of fluorine contained in the protective layer 6 was greatest at the surface, and the concentration decreased from the surface to a depth of approximately 20 nm, after which the fluorine concentration remained constant. The amount of fluorine present at the outermost surface was approximately 200 times higher than that at the constant fluorine concentration.

[0196] Thereafter, a molybdenum (Mo) film was formed to a thickness of 150 nm by sputtering, and patterned into a desired shape by photolithography to form a source electrode 7 and a drain electrode 8.

[0197] Through the above steps, the thin film transistor 102 according to the third embodiment of the present invention was fabricated.

[0198] Example 6 As Example 6, a thin film transistor in which the protective layer 6 did not contain fluorine was fabricated.

[0199] As the substrate 1, a polyimide varnish was applied to a non-alkali glass substrate having a thickness of 0.7 mm and baked to form a polyimide film having a thickness of 20 μm.

[0200] An aluminum alloy film was formed on the substrate 1 to a thickness of 100 nm by DC magnetron sputtering, and the film was patterned into a desired shape by photolithography to form the gate electrode 2.

[0201] A photosensitive acrylic resin was applied to the substrate on which the gate electrode 2 was formed using a slit coating method, and patterned by mask exposure and alkaline development, followed by baking at 230°C to form a first gate insulating layer 3 of the desired shape. The film thickness of the first gate insulating layer 3 after baking was 1.0 μm. The relative dielectric constant of this insulating layer was 3.8.

[0202] On the substrate on which the first gate insulating layer 3 was formed, a second gate insulating layer 4 made of silicon oxide was formed by chemical vapor deposition (CVD) using silane (SiH4) and nitrous oxide (N2O) as raw material gases. The film thickness of the second gate insulating layer 4 was set to 10 nm. The relative dielectric constant of the second gate insulating layer 4 was 5.0.

[0203] Then, on the second gate insulating layer 4, a sputtering method was used to deposit an IGZO thin film with a thickness of 30 nm using a target material having a composition of InGaZnOx (IGZO) and argon (Ar) and oxygen (O2) as sputtering gases, and the film was patterned by photolithography to form a semiconductor layer 5.

[0204] The second gate insulating layer 4 was patterned using the resist used to pattern the semiconductor layer 5. The second gate insulating layer 4 was patterned by reactive ion etching using carbon tetrafluoride (CF4) gas.

[0205] Furthermore, a photosensitive acrylic resin solution was applied onto the semiconductor layer 5, and after the solvent was removed by drying, patterning was performed by mask exposure and alkaline development, and the resulting product was baked at 230°C to form a protective layer 6 of the desired shape. The thickness of the protective layer 6 was 0.6 μm. In addition, in order to measure the surface energy of the protective layer 6, the protective layer 6 was formed on a separate substrate and measurements were carried out. The surface energy of the protective layer 6 was found to be 45.0 mJ / m 2 The surface energy was measured by measuring the contact angles of water and diiodomethane using the sessile drop method, and the surface energy was calculated from these values ​​using the Kaelble-Uy method.

[0206] Thereafter, a molybdenum (Mo) film was formed to a thickness of 150 nm by sputtering, and patterned into a desired shape by photolithography to form a source electrode 7 and a drain electrode 8.

[0207] Through the above steps, a thin film transistor was fabricated in which the protective layer 6 did not contain fluorine. Example 6 does not correspond to the thin film transistor 102 according to the third embodiment of the present invention, since the protective layer 6 does not contain fluorine. However, Example 6 corresponds to the thin film transistor according to the first embodiment of the present invention, in which the second gate insulating layer 4 is formed only in the area overlapping with the semiconductor layer 5.

[0208] The thin film transistors according to Examples 4, 5, and 6, which were fabricated by the above-described process, were compared. In Examples 4 and 5, the protective layer of the thin film transistor was made of an organic material containing fluorine, and the difference between Examples 4 and 5 was the amount of fluorine contained in the protective layer. In addition, Example 6 differs from Examples 4 and 5 in that the protective layer did not contain fluorine.

[0209] To compare the device characteristics of the thin-film transistors according to Examples 4, 5, and 6 of the present invention, the transfer characteristics of the thin-film transistor devices were measured. A semiconductor parameter analyzer B1500A (manufactured by Keysight Technologies) was used to measure the transfer characteristics. A negative bias stress (NBS) test was also conducted to investigate the reliability of the fabricated thin-film transistors. To investigate the flexibility of the fabricated thin-film transistors, the fabricated transistors were wrapped halfway around a metal rod with a specified radius and the transfer characteristics were measured in a bent state.

[0210] 14 to 16 are diagrams showing the transfer characteristics of thin film transistors according to Examples 4, 5, and 6 of the present invention. Vgs represents the voltage between the gate electrode and source electrode, and Ids represents the current between the drain electrode and source electrode. Measurements were performed by setting the drain voltage to 10 V, the source voltage to 0 V, and sweeping the gate electrode voltage from -20 V to 20 V. The channel size of the measured thin film transistor was 20 μm in length and 50 μm in width.

[0211] 14 to 16, Examples 4, 5, and 6 exhibit good device characteristics. Table 2 shows the device characteristic values ​​of each device. Comparing the device characteristic values, Examples 4 and 5, which contain fluorine in the protective layer 6, exhibit higher device characteristics than Example 6, demonstrating the effect of containing fluorine in the protective layer 6. [Table 2]

[0212] The threshold voltage change (ΔVth) in Table 2 indicates the change in threshold voltage before and after the NBS test. The NBS test was performed by applying a voltage for 1000 seconds at a substrate temperature of 60°C with a gate electrode voltage (Vgs) of -15V, a source voltage (Vs) and a drain voltage (Vd) of 0V. Examples 4 and 5 showed smaller threshold voltage changes than Example 6, indicating improved reliability of the thin-film transistor elements. This is because the protective layer 6 contains fluorine, which effectively reduces external influences. Furthermore, when a bending test was carried out on the thin film transistors, the thin film transistor elements of Examples 4, 5, and 6 were not broken at curvature radii R=5 mm to R=1 mm, and good element characteristics were exhibited (Table 3). This indicates that the thin film transistors have high flexibility by using an organic insulating material for the protective layer 6, regardless of the amount of fluorine contained in the protective layer 6 of the thin film transistor. [Table 3]

[0213] As a result of the experiment, the thin film transistors 102 of Examples 4 and 5 of the present invention exhibited good element characteristics even when bent with a small radius of curvature, demonstrating that it is possible to fabricate thin film transistors that have very high flexibility, high reliability, and good element characteristics.

[0214] Therefore, according to the present invention, it is possible to provide a thin film transistor, a thin film transistor array, and a method for manufacturing a thin film transistor that have good device characteristics and high flexibility.

[0215] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present invention. [Explanation of symbols]

[0216] REFERENCE SIGNS LIST 1...substrate, 2...gate electrode, 3...first gate insulating layer, 4...second gate insulating layer, 5...semiconductor layer, 6...protective layer, 7...source electrode, 8...drain electrode, 100, 101, 102, 103...thin film transistor

Claims

1. A thin film transistor comprising an insulating substrate, a gate electrode, a first gate insulating layer, a second gate insulating layer, a semiconductor layer, an insulating protective layer, and a source electrode and a drain electrode stacked in this order, the first gate insulating layer is made of an insulating material containing an organic material, the second gate insulating layer is made of an inorganic insulating material, the second gate insulating layer has a thickness smaller than the thickness of the first gate insulating layer; the second gate insulating layer is formed only in an area overlapping the semiconductor layer or the protective layer, the protective layer comprises a first protective layer and a second protective layer, the first protective layer is made of an inorganic insulating material, the second protective layer is made of a fluorine-containing organic material; Thin film transistor.

2. 2. The thin film transistor of claim 1, the semiconductor layer is made of silicon or an oxide of a metal selected from indium, gallium, zinc, and tin; Thin film transistor.

3. 3. The thin film transistor according to claim 1, the second gate insulating layer has a thickness of 2 nm or more and 100 nm or less; Thin film transistor.

4. 4. The thin film transistor according to claim 1, the second gate insulating layer is made of an oxide of a metal selected from silicon, aluminum, tantalum, hafnium, yttrium, and zirconium; Thin film transistor.

5. 4. The thin film transistor according to claim 1, the second gate insulating layer is made of silicon nitride; Thin film transistor.

6. 6. The thin film transistor according to claim 1, the first gate insulating layer is made of an organic polymer material; Thin film transistor.

7. A thin film transistor array in which the thin film transistors according to any one of claims 1 to 6 are arranged, the second gate insulating layer and the protective layer are formed in a region where the wiring of the gate electrode and the wiring of the source electrode intersect; Thin film transistor array.

8. A method for manufacturing a thin film transistor according to any one of claims 1 to 6, comprising the steps of: patterning the second gate insulating layer after patterning the semiconductor layer; A method for manufacturing a thin film transistor.

9. 9. A method for manufacturing a thin film transistor according to claim 8, comprising: etching the second gate insulating layer using the resist used in patterning the semiconductor layer as a mask; A method for manufacturing a thin film transistor.

10. A method for fabricating a thin film transistor, comprising: The thin film transistor is an insulating substrate, a gate electrode, a first gate insulating layer, a second gate insulating layer, a semiconductor layer, an insulating protective layer, and a source electrode and a drain electrode, which are stacked in this order; the first gate insulating layer is made of an insulating material containing an organic material, the second gate insulating layer is made of an inorganic insulating material, the second gate insulating layer has a thickness smaller than the thickness of the first gate insulating layer; the second gate insulating layer is formed only in an area overlapping the semiconductor layer or the protective layer, the protective layer comprises a first protective layer and a second protective layer, patterning the semiconductor layer and the second protective layer, and then patterning the first protective layer and the second gate insulating layer; A method for manufacturing a thin film transistor.

11. 11. A method for manufacturing a thin film transistor according to claim 10, comprising: etching the first protective layer and the second gate insulating layer using the semiconductor layer and the second protective layer as a mask; A method for manufacturing a thin film transistor.

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