Application Programming Interface for Identifying Memory

Abstract

Apparatus, systems, and techniques for executing one or more application programming interface (API) functions to facilitate parallel computing, in at least one embodiment, the one or more APIs point to one or more storage locations using various novel techniques described herein.

Description

[Technical Field]

[0001] This application is a continuation of U.S. Provisional Patent Application No. 63 / 174,895, entitled "ENHANCEMENTS TO STREAM ORDERED ALLOCATORS," filed on April 14, 2021 (Attorney Docket No. 0112912-269PR0), U.S. Patent Application No. 17 / 720,179, entitled "APPLICATION PROGRAMMING INTERFACE TO IDENTIFY MEMORY," filed on April 13, 2022 (Attorney Docket No. 0112912-269US0), and U.S. Patent Application No. 17 / 719,961, entitled "APPLICATION PROGRAMMING INTERFACE TO IDENTIFY SHARABLE MEMORY," filed on April 13, 2022 (Attorney Docket No. No. 17 / 720,095, filed April 13, 2022 (Attorney Docket No. 0112912-269US2), entitled "APPLICATION PROGRAMMING INTERFACE TO INDICATE MEMORY INFORMATION," the entire contents of each of which are incorporated herein by reference.

[0002] At least one embodiment relates to processing resources used to execute one or more application programming interfaces (APIs) to facilitate parallel computing. For example, at least one embodiment relates to a processor or computing system used to execute one or more programs that implement one or more APIs to facilitate parallel computing, including various novel techniques described herein. [Background technology]

[0003] The development of various accelerators (e.g., graphics processing units (GPUs)) has brought many benefits, but these benefits have come with increased complexity. In general, different programming models create complexity that, if not effectively managed, can lead to less than optimal performance. As one example, memory management can be complex, especially in the context of one processor offloading operations to another, such as by executing a kernel. Some techniques for addressing these issues involve either over-allocating or under-allocating memory, which can lead to inefficiencies and / or performance issues. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram illustrating a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs), according to at least one embodiment. [Figure 2] FIG. 1 is a block diagram illustrating an API for determining whether a memory address is contained in one or more memory blocks used by one or more computing devices, according to at least one embodiment. [Figure 3] FIG. 1 is a block diagram illustrating an API for determining whether one or more memory blocks used by one or more computing devices are shareable during the execution of one or more software modules, according to at least one embodiment. [Figure 4] FIG. 1 is a block diagram illustrating an API for determining one or more attributes of one or more memory blocks used by one or more computing devices, according to at least one embodiment. [Figure 5]FIG. 10 illustrates a process for determining, by one or more APIs, whether a memory address is contained in one or more memory blocks used by one or more computing devices, according to at least one embodiment. [Figure 6] FIG. 10 illustrates a process for determining, by one or more APIs, whether one or more memory blocks used by one or more computing devices are shared and / or were shared during execution of one or more software modules, according to at least one embodiment. [Figure 7] FIG. 10 is a diagram of a process for determining one or more attributes of one or more memory blocks used by one or more computing devices in response to one or more calls to one or more APIs, according to at least one embodiment. [Figure 8] FIG. 1 illustrates an exemplary data center, according to at least one embodiment. [Figure 9] FIG. 1 illustrates a processing system according to at least one embodiment. [Figure 10] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 11] FIG. 1 illustrates a system according to at least one embodiment. [Figure 12] FIG. 1 illustrates an exemplary integrated circuit according to at least one embodiment. [Figure 13] FIG. 1 illustrates a computing system according to at least one embodiment. [Figure 14] FIG. 1 illustrates an APU, according to at least one embodiment. [Figure 15] FIG. 1 illustrates a CPU according to at least one embodiment. [Figure 16] FIG. 2 illustrates an exemplary accelerator integration slice, according to at least one embodiment. [Figure 17A]FIG. 1 illustrates an exemplary graphics processor according to at least one embodiment. [Figure 17B] FIG. 1 illustrates an exemplary graphics processor according to at least one embodiment. [Figure 18A] FIG. 1 illustrates a graphics core according to at least one embodiment. [Figure 18B] FIG. 1 illustrates a GPGPU, according to at least one embodiment. [Figure 19A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 19B] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 19C] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 20] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 21] FIG. 1 illustrates a processor according to at least one embodiment. [Figure 22] FIG. 1 illustrates a processor according to at least one embodiment. [Figure 23] FIG. 1 illustrates a graphics processor core according to at least one embodiment. [Figure 24] FIG. 1 illustrates a PPU, according to at least one embodiment. [Figure 25] FIG. 1 illustrates a GPC, according to at least one embodiment. [Figure 26] FIG. 1 illustrates a streaming multiprocessor according to at least one embodiment. [Figure 27] FIG. 1 illustrates a software stack for a programming platform according to at least one embodiment. [Figure 28] FIG. 28 illustrates a CUDA implementation of the software stack of FIG. 27, according to at least one embodiment. [Figure 29]FIG. 28 illustrates an ROCm implementation of the software stack of FIG. 27, according to at least one embodiment. [Figure 30] FIG. 28 illustrates an OpenCL implementation of the software stack of FIG. 27, according to at least one embodiment. [Figure 31] FIG. 1 illustrates software supported by a programming platform according to at least one embodiment. [Figure 32] FIG. 31 illustrates compiling code for execution on the programming platform of FIGS. 27-30 according to at least one embodiment. [Figure 33] FIG. 31 illustrates in more detail compiling code for execution on the programming platform of FIGS. 27-30 according to at least one embodiment. [Figure 34] FIG. 1 illustrates translating source code prior to compiling the source code, according to at least one embodiment. [Figure 35A] FIG. 1 illustrates a system configured to compile and execute CUDA source code using different types of processing units, according to at least one embodiment. [Figure 35B] FIG. 35B illustrates a system configured to compile and execute the CUDA source code of FIG. 35A using a CPU and a CUDA-enabled GPU, according to at least one embodiment. [Figure 35C] FIG. 35B illustrates a system configured to compile and execute the CUDA source code of FIG. 35A using a CPU and a non-CUDA-enabled GPU, according to at least one embodiment. [Figure 36] FIG. 35D illustrates an example kernel translated by the CUDA-to-HIP translation tool of FIG. 35C, in accordance with at least one embodiment. [Figure 37]FIG. 35D illustrates the non-CUDA GPU of FIG. 35C in more detail, according to at least one embodiment. [Figure 38] FIG. 38 illustrates how threads of an exemplary CUDA grid are mapped to different compute units of FIG. 37, according to at least one embodiment. [Figure 39] FIG. 1 illustrates how to migrate existing CUDA code to Data Parallel C++ code, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0005] FIG. 1 is a block diagram illustrating a driver and / or runtime 104 comprising or providing access to one or more libraries 106, where the one or more libraries include one or more application programming interfaces (APIs) implemented as a result of calls by a software program 102, according to at least one embodiment. In at least one embodiment, the software program 102 is a software module. In at least one embodiment, the software program 102 includes one or more software modules. In at least one embodiment, the one or more APIs 110 are sets of software instructions that, when executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, the one or more APIs 110 are distributed or provided as part of one or more libraries 106, runtime 104, driver 104, and / or any other grouping of software and / or executable code described further herein. In at least one embodiment, one or more APIs 110 perform one or more computational operations in response to being invoked by a software program 102. In at least one embodiment, the software program 102 is a collection of software code, commands, instructions, or other sequences of text that instruct a computing device to perform one or more computational operations and / or invoke and execute one or more other sets of instructions, such as the API 110 or API functions 112. In at least one embodiment, the functionality provided by the one or more APIs 110 includes software functions 112, such as those that can be used to accelerate one or more portions of the software program 102 using one or more parallel processing units (PPUs), such as a graphics processing unit (GPU).

[0006] In at least one embodiment, the API 110 is a hardware interface to one or more circuits for performing one or more computational operations. In at least one embodiment, one or more software APIs 110 described herein are implemented as one or more circuits for performing one or more techniques described below in conjunction with Figures 2-7. In at least one embodiment, one or more software programs 102 include instructions that, when executed, cause one or more hardware devices and / or circuits to perform one or more techniques described further below in conjunction with Figures 2-7.

[0007] In at least one embodiment, a software program 102, such as a user-implemented software program, utilizes one or more application programming interfaces (APIs) 110 to perform various computational operations, such as memory reservation, matrix multiplication, or any computational operation performed by a parallel processing unit (PPU), such as a graphics processing unit (GPU), as described further herein. In at least one embodiment, the one or more APIs 110 provide a set of callable functions 112, referred to herein as APIs, API functions, and / or functions, which individually perform one or more computational operations, such as computational operations associated with parallel computing. For example, in one embodiment, the one or more APIs 110 provide functions 112 to perform memory allocation and management for one or more PPUs, such as graphics processing units (GPUs).

[0008] In at least one embodiment, one or more software programs 102 interact or communicate with one or more APIs 110 to perform one or more computational operations using one or more PPUs, such as a GPU. In at least one embodiment, the one or more computational operations using one or more PPUs include at least one or more groups of computational operations that are accelerated, at least in part, by execution by the one or more PPUs. In at least one embodiment, one or more software programs 102 interact with one or more APIs 110 to facilitate parallel computing using remote or local interfaces.

[0009] In at least one embodiment, an interface is software instructions that, when executed, provide access to one or more functions 112 provided by one or more APIs 110. In at least one embodiment, a software program 102 uses a local interface when a software developer compiles one or more software programs 102 in conjunction with one or more libraries 106 that include or provide access to one or more APIs 110. In at least one embodiment, one or more software programs 102 are statically compiled in conjunction with precompiled libraries 106 or uncompiled source code that includes instructions for executing one or more APIs 110. In at least one embodiment, one or more software programs 102 are dynamically compiled, and the one or more software programs utilize a linker to link to one or more precompiled libraries 106 that include one or more APIs 110.

[0010] In at least one embodiment, a software program 102 uses a remote interface when a software developer executes a software program that utilizes or communicates with a library 106 containing one or more APIs 110 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 106 containing the one or more APIs 110 are executed by a remote computing device, such as a computing resource service provider. In another embodiment, the one or more libraries 106 containing the one or more APIs 110 are executed by any other computing host that provides the one or more APIs 110 to the one or more software programs 102.

[0011] In at least one embodiment, one or more software programs 102 utilize one or more APIs 110 to allocate and manage memory used by the software programs 102. In at least one embodiment, one or more software programs 102 utilize one or more APIs 110 to allocate and manage memory used by one or more portions of the software programs 102 that are accelerated using one or more PPUs, such as a GPU, or any other accelerator or processor described further herein. Such software programs 102 request and allocate memory for one or more PPUs using memory allocation functions 112, which in one embodiment are provided by one or more APIs 110.

[0012] In at least one embodiment, API 110 is an API for facilitating parallel computing. In at least one embodiment, API 110 is any other API described further herein. In at least one embodiment, API 110 is provided by a driver and / or runtime 104. In at least one embodiment, API 110 is provided by a CUDA user-mode driver. In at least one embodiment, API 110 is provided by a CUDA runtime. In at least one embodiment, driver 104 is data values ​​and software instructions that, when executed, perform or facilitate the operation of one or more functions 112 of API 110 during the loading and execution of one or more portions of software program 102. In at least one embodiment, runtime 104 is data values ​​and software instructions that, when executed, perform or facilitate the operation of one or more functions 112 of API 110 during the execution of software program 102. In at least one embodiment, one or more software programs 102 utilize one or more APIs 110 implemented or provided by a driver and / or runtime 104 to allocate or reserve one or more memory regions for use by portions of the one or more software programs 102 during execution by one or more PPUs, such as a GPU.

[0013] In at least one embodiment, one or more software programs 102 utilize one or more APIs 110 provided by a driver and / or runtime 104 to allocate or reserve one or more blocks of memory 114 of one or more PPUs, such as GPUs. In at least one embodiment, one or more software programs 102 utilize one or more APIs 110 provided by a driver and / or runtime 104 to allocate or reserve one or more pools 116, 118, 120 of memory 114 of one or more PPUs, such as GPUs. In at least one embodiment, the pools 116, 118, 120 of memory 114, referred to herein as memory pools (mempools) and / or memory zones (memzones), are logical groupings of one or more blocks of memory available for use by one or more computing devices, such as individual processors of one or more PPUs, such as GPUs. In at least one embodiment, one or more APIs 110 can be used to manage one or more pools 116, 118, 120 and / or other blocks of memory 114. For example, in one embodiment, one or more streaming processors on one or more PPUs, such as GPUs, as described further herein, have physical memory usable by each of the one or more streaming processors and / or shared physical memory usable by each of the one or more streaming processors. In at least one embodiment, the API 110, through a driver and / or runtime 104, provides one or more APIs 110 or API functions 112 to allocate, deallocate, or manage the pools 116, 118, 120 of memory or other portions of memory, either individual to each streaming processor or shared among them.

[0014] In at least one embodiment, the one or more APIs 110 include one or more functions 121 for allocating and / or managing one or more pools 116, 118, 120 or other regions of memory 114. In at least one embodiment, the one or more APIs 110 implement memory allocation and management operations through a driver and / or runtime 104, as described above. In at least one embodiment, the one or more drivers and / or runtimes 104 providing the one or more APIs 110 organize the memory 114 into logical groupings or pools 116, 118, 120, such as memory pools or any other grouping described further herein. In at least one embodiment, the logical groupings or pools 116, 118, 120 of memory 114 include regions or subregions of one or more blocks of memory 114 that are usable by one or more computing devices. In at least one embodiment, a block of memory includes all memory available to or usable by one or more PPUs. In at least one embodiment, a block of memory 114 includes all memory 114 associated with or usable by a single computing device, such as a streaming processor or any other processor described further herein. In at least one embodiment, pools 116, 118, 120 include one or more regions of memory 114 of one or more PPUs that are usable or usable by one or more devices, such as a streaming processor or any other processor described further herein.

[0015] In at least one embodiment, the one or more APIs 110 allocate, manage, and / or access one or more pools 116, 118, 120 of memory 114, as described below in conjunction with Figures 2-4. In at least one embodiment, the one or more APIs 110 provide allocation, management, and / or access to one or more groupings or pools 116, 118, 120 of memory 114, such as a memory pool or any other grouping described further herein. In at least one embodiment, the one or more APIs 110 provide synchronized allocation and / or deallocation and / or access to the pools 116, 118, 120 of memory 114 or other groupings of memory 114. In at least one embodiment, one or more APIs 110 synchronously allocate and / or deallocate and / or access the pools 116, 118, 120 of memory 114 or other groupings of memory 114 through the driver and / or runtime 104. In at least one embodiment, one or more APIs 110 asynchronously allocate and / or deallocate and / or access the pools 116, 118, 120 of memory 114 or other groupings of memory 114. In at least one embodiment, one or more APIs 110 asynchronously allocate and / or deallocate and / or access the pools 116, 118, 120 of memory 114 or other groupings of memory 114 through the driver and / or runtime 104.

[0016] In at least one embodiment, one or more APIs 110 implement and / or provide one or more API 110 functions 112 that include an asynchronous allocator, such as a stream-ordered memory allocator. In at least one embodiment, the stream-ordered memory allocator is a data value and software instruction that, when executed, enables the software program 102 to allocate memory 114 into logical memory groupings, such as pools 116, 118, 120, and free allocated memory. In at least one embodiment, the stream-ordered memory allocator allocates memory 114 in stream order. In at least one embodiment, memory 114 is allocated in stream order if one or more regions or subregions of one or more pools 116, 118, 120 of memory are allocated in advance of use by one or more operations in a stream executed by one or more PPUs, such as a GPU, that depend on the one or more regions or subregions to use. In at least one embodiment, a stream ordered memory allocator is a data value and software instruction that, when executed, allocates memory 114 into logical groupings of memory, such as pools 116, 118, 120, and free allocated memory, in asynchronous response to one or more calls or function 112 or API 110 calls by software programs 102. In at least one embodiment, a stream ordered memory allocator preserves one or more allocations of memory 114 in a logical grouping of memory, such as pools 116, 118, 120, between uses by one or more user-implemented software programs until a free operation releases the memory allocation. In at least one embodiment, one or more regions or subregions of memory 114 allocated by a stream ordered allocator may be shared among multiple software programs 102.In at least one embodiment, regions or sub-regions of allocated memory 114 shared between two or more software programs 102 do not overlap, such that the regions or sub-regions of memory are accessed during parallel execution of segments of the two or more software programs 102.

[0017] In at least one embodiment, one or more asynchronous allocator functions 112, such as a stream-ordered memory allocator, provided by one or more APIs 110 manage memory 114 of one or more PPUs, such as GPUs. To improve optimization of software program 102 and / or one or more portions of software program 102 to be accelerated by one or more PPUs, such as GPUs, in one embodiment, one or more APIs 110 provide one or more API functions 112 to collect or determine memory usage of one or more blocks of memory 114, such as pools 116, 118, 120, available or used by one or more computing devices, as described above and further below in conjunction with FIGS.

[0018] FIG. 2 is a block diagram illustrating application programming interfaces (APIs) 202, 204 that determine whether a memory address is included in one or more memory blocks used by one or more computing devices, according to at least one embodiment. In at least one embodiment, the one or more APIs 202, 204 are software instructions that, when executed, perform one or more computational operations, such as those described above in conjunction with FIG. 1. In at least one embodiment, the one or more APIs 202, 204 are software functions that, when invoked, perform one or more computational operations. In at least one embodiment, the one or more APIs 202, 204 are interfaces to one or more functions for performing one or more memory operations, such as those described above in conjunction with FIG. 1. In at least one embodiment, the one or more APIs 202, 204 include one or more functions that, when invoked, cause one or more software instructions and / or hardware operations to be executed by one or more processors, including parallel processing units (PPUs), such as graphics processing units (GPUs) as further described herein.

[0019] In at least one embodiment, one or more APIs 202, 204 include API calls 202 and API responses 204. In at least one embodiment, API calls 202 are interfaces to one or more functions that, when invoked, perform one or more computational operations. In at least one embodiment, API calls 202 are one or more instructions that, when executed, cause one or more functions, APIs, API functions, and / or other computational operations to be executed. In at least one embodiment, API calls 202 receive one or more parameters as input. In at least one embodiment, API responses 204 are interfaces that indicate, transmit, return, or communicate one or more data values ​​resulting from the execution of one or more functions, APIs, API functions, or any other computational operations. In at least one embodiment, API responses 204 indicate, transmit, return, or communicate one or more data values ​​to one or more functions invoking or executing API calls 202. In at least one embodiment, API response 204 is one or more instructions that, when executed, return one or more data values ​​as a result of invoking one or more API calls 202 .

[0020] In at least one embodiment, the one or more API calls 202 cause one or more APIs to indicate one or more addresses of data that the one or more APIs reference. In at least one embodiment, the one or more APIs reference one or more addresses of data if one or more blocks, regions, or pools of memory, such as those described above in conjunction with FIG. 1, are identifiable or identifiable by the one or more APIs. In at least one embodiment, the one or more APIs reference one or more addresses of data if the one or more APIs, or any other API, such as an asynchronous allocation function described above in conjunction with FIG. 1, allocates or uses one or more blocks, regions, and / or pools of memory that include the one or more addresses. In at least one embodiment, the one or more API calls 202 cause one or more APIs or other software libraries, such as those described above in conjunction with Figure 1, to determine whether one or more memory location identifiers are within range for one or more memory blocks and / or memory regions, such as a pool of memory allocated by an asynchronous allocator, such as those described above in conjunction with Figure 1. In at least one embodiment, the one or more API calls 202 cause one or more APIs or other software libraries, such as those described above in conjunction with Figure 1, to determine whether one or more memory locations are encompassed by one or more addresses of data referenced by the one or more APIs. In at least one embodiment, the memory location identifiers are data values, such as pointers, that contain information to indicate one or more memory locations, such as memory addresses. In at least one embodiment, one or more API calls 202, when invoked, cause one or more software instructions to be executed, where the one or more software instructions determine whether a memory location will be or has been allocated as a result of one or more particular function calls.For example, in one embodiment, if a memory location identifier parameter to API call 202 indicates a memory region or memory address allocated as a result of a call to a particular asynchronous allocator, a handle to a particular memory pool or grouping that includes the memory region is returned in API response 204. In at least one embodiment, in response to one or more API calls 202 causing one or more APIs or other software libraries to determine whether one or more memory location identifiers are within one or more memory regions, the one or more APIs cause API response 304 to indicate one or more data values ​​that include memory set identifiers. In at least one embodiment, the memory set identifier is one or more data values ​​that include information to indicate one or more memory blocks and / or memory regions, such as pools of memory as described above in conjunction with FIG. 1. In at least one embodiment, the memory set identifier is a NULL data value to indicate the absence of memory blocks and / or memory regions, as described below.

[0021] In at least one embodiment, exemplary API call 202 causes an API, such as a compute uniform device architecture (CUDA), to determine whether one or more memory location identifiers, such as pointers, obtained as a result of one or more memory allocation operations include information to indicate and / or point to one or more memory regions allocated by an asynchronous allocator within a grouping or pool of memory, such as a memory pool as described above in conjunction with FIG. 1, as follows: CUMemoryPool pool = NULL; cuPointerGetAttribute(&pool, CU_POINTER_ATTRIBUTE_MEMPOOL_HANDLE, ptr); In at least one embodiment, one or more software programs include one or more API calls 202 that, when invoked or executed, query a particular memory pool or grouping that allocated a pointer indicated as a parameter to one of the API calls 202. In at least one embodiment, CU_POINTER_ATTRIBUTE_MEMPOOL_HANDLE is an attribute specific to one or more APIs, such as CUDA or any other API described further herein. In at least one embodiment, CU_POINTER_ATTRIBUTE_MEMPOOL_HANDLE is an attribute for indicating a particular memory allocation operation to be performed by an allocator. In at least one embodiment, pointerGetAttribute is a function including a set of instructions, such as an API as described above in conjunction with FIG. 1. In at least one embodiment, cuPointerGetAttribute is a function including a set of instructions, such as an API. In at least one embodiment, pointerGetAttribute, cuPointerGetAttribute, or any other API call 202 receives as one or more parameters at least one memory location identifier including an attribute such as CU_POINTER_ATTRIBUTE_MEMPOOL_HANDLE. In at least one embodiment, pointerGetAttribute, cuPointerGetAttribute, or any other API call 202 to a function returns, via an API response 204, a memory set identifier such as a handle or pointer to a memory address that indicates a pool or grouping of memory, such as a memory pool, to which a pointer (e.g., ptr) points, or that includes a memory region pointed to by a pointer provided as a parameter to the function. In at least one embodiment, the memory set identifier is a data value that includes information for indicating a pool or grouping of memory, such as a memory pool. In at least one embodiment, the memory set identifier includes a memory address that indicates a first address of a pool or grouping of memory, such as a memory pool.

[0022] In at least one embodiment, to determine the memory set identifier that will be indicated by an API or function in an API response 204, the API or function performs one or more computational operations to determine whether the memory location identifier is contained within a memory set, such as a pool or grouping of memory. In at least one embodiment, the memory set identifier that will be returned in an API response 204 and indicates a grouping or pool of memory within a memory object (memobj) that contains an address pointed to by a pointer provided as a parameter to pointerGetAttribute, cuPointerGetAttribute, or any other API call 202 by a particular owner is computed and / or derived as follows: &((CUImemblockPool)(memobj->PoolObj->info->pool->owner))->publicHandle; In at least one embodiment, a memory set identifier indicating a grouping or pool when the memory in the memory object (memobj) to be returned by the API response 204 contains an address pointed to by a pointer provided as a parameter to pointerGetAttribute, cuPointerGetAttribute, or any other API call 202 is calculated and / or derived as follows: &memobj- <extpoolobg->extMemPool->publicHandle; In at least one embodiment, if the memory location identifier indicated as a parameter to pointerGetAttribute, cuPointerGetAttribute, or any other API call 202 cannot be found, cannot be determined, or is not a memory pool object, the API response 204 returns a memory set identifier containing a NULL data value in response to pointerGetAttribute, cuPointerGetAttribute, or any other API call 202.

[0023] FIG. 3 is a block diagram illustrating an API 302, 304 for determining whether one or more memory blocks, regions, and / or pools of memory used by one or more computing devices are shareable during the execution of one or more software modules, according to at least one embodiment. In at least one embodiment, one or more computing devices are parallel processing units (PPUs). In at least one embodiment, one or more computing devices are central processing units (CPUs). In at least one embodiment, one or more computing devices are graphics processing units (GPUs). In at least one embodiment, one or more computing devices are any other processors and / or hardware and / or software devices described further herein. In at least one embodiment, one or more software modules are any composition or logical organization of software instructions that, when executed, cause one or more processors to perform one or more operations. In at least one embodiment, one or more software modules are kernels. In at least one embodiment, one or more software modules are graphics processing unit (GPU) kernels. In at least one embodiment, one or more software modules are compute uniform device architecture (CUDA) kernels. In at least one embodiment, one or more software modules are user-mode processes. In at least one embodiment, one or more software modules are kernel-mode processes. In at least one embodiment, one or more software modules are any other packaging or type of software that, when executed, causes one or more processors to perform one or more operations.

[0024] In at least one embodiment, the one or more APIs 302, 304 include one or more API calls 302 and / or one or more API responses 304. In at least one embodiment, an API call 302, such as described above in conjunction with Figures 1 and 2, receives one or more data values ​​as parameters and causes one or more APIs or other software libraries to determine, calculate, or generate information indicating whether one or more memory blocks, regions, and / or pools of memory of one or more devices indicated by the one or more parameters will become or were shareable during execution of one or more software modules. In at least one embodiment, the API response 304, as described above in conjunction with Figures 1 and 2, returns, communicates, or indicates one or more data values ​​including a set of supported handle types that can be used to share one or more memory blocks, regions, and / or pools of memory during execution of one or more software modules.

[0025] In at least one embodiment, the one or more API calls 302 cause one or more APIs or other software libraries, such as those described above in conjunction with FIG. 1, to determine whether one or more memory blocks, regions, and / or pools of memory of one or more devices indicated by one or more device identifier parameters are currently sharable, become sharable, or were sharable during execution of one or more software modules. In at least one embodiment, the one or more API calls 302 cause one or more APIs or other software libraries, such as those described above in conjunction with FIG. 1, to determine whether one or more memory blocks, regions, and / or pools of memory of one or more devices indicated by one or more device identifier parameters are currently allocatable, become sharable, or were allocatable during execution of one or more software modules. In at least one embodiment, the device identifier parameters are one or more data values ​​usable to indicate one or more devices, such as any computing device described further herein. In at least one embodiment, the device identifier is a device attribute. In at least one embodiment, the device identifier is any type of data value that can be used to identify one or more devices or one or more attributes of one or more devices, such as any computing device described further herein. In at least one embodiment, the one or more APIs determine, using one or more other APIs, such as APIs described further herein, whether one or more storage locations indicated by one or more parameters to the one or more APIs can be shared during execution of one or more software modules, and indicate one or more handles that can be used to share the one or more storage locations.In at least one embodiment, the one or more APIs determine whether one or more storage locations indicated by one or more parameters to the one or more APIs are available for allocation using one or more other APIs, such as the asynchronous allocation API described above in conjunction with FIG. 1, and indicate whether the one or more storage locations are available for allocation. In at least one embodiment, the one or more APIs indicate whether the one or more storage locations are available for sharing using one or more data values ​​indicated by the API response 304. In at least one embodiment, the one or more APIs indicate whether the one or more storage locations are available for allocation using one or more data values ​​indicated by the API response 304. In at least one embodiment, the memory set identifier is one or more data values ​​that include information to indicate one or more memory blocks and / or memory regions, such as a pool of memory as described above in conjunction with FIG. 1. In at least one embodiment, one or more API calls 302, when invoked, cause one or more software instructions to execute one or more software instructions that cause one or more processors to determine whether one or more memory blocks, regions, and / or pools of memory indicated by one or more device identifier parameters are currently shared or shareable, will become shared or shareable, or were shared or shareable during execution of one or more software modules, as described above.In at least one embodiment, one or more API calls 302, when invoked, cause one or more software instructions to execute one or more processors to determine whether one or more memory blocks, regions, and / or pools of memory indicated by one or more memory set identifier parameters are to be allocated or are allocatable using one or more asynchronous APIs, such as the asynchronous memory allocation functions described above in conjunction with FIG. 1. In at least one embodiment, in response to the one or more API calls 302, the one or more APIs cause or execute API responses 304 to indicate one or more data values ​​including one or more handles. In at least one embodiment, a handle is a data value usable by one or more software modules to share memory with one or more other software modules. In at least one embodiment, in response to one or more API calls 302, one or more APIs cause or execute API responses 304 to indicate one or more data values ​​that include an API indicator. In at least one embodiment, the API indicator is one or more data values ​​that include information indicating whether one or more memory blocks, regions, and / or pools of memory indicated by one or more memory set identifier parameters will be allocated or are allocable, or have been allocated or are allocable, using one or more asynchronous APIs, such as the asynchronous memory allocation functions described above in conjunction with FIG.

[0026] In at least one embodiment, the one or more API calls 302 cause one or more APIs or other software libraries to perform one or more computational operations to determine whether one or more memory blocks, regions, and / or pools of memory indicated by one or more memory set identifier parameters support particular memory operations, such as allocation and / or sharing, as described above. In at least one embodiment, the one or more API calls 302 result in the one or more APIs performing one or more operations to determine whether a computing device, including memory and other components, supports inter-process communication (IPC) between two or more processes using memory regions allocated within a specified pool or grouping of memory, such as a memory pool. For example, in one embodiment, if one or more devices containing memory allocated by one or more asynchronous allocators do not support IPC, such as memory pool-based IPC, one or more attributes may be returned as a result of one or more function calls to one or more APIs to facilitate parallel computing that requests the attributes of the one or more devices.

[0027] In at least one embodiment, an exemplary API call 302 for determining whether one or more devices executing one or more software programs support particular memory operations, such as memory pool operations, including asynchronous memory allocation and / or sharing, is as follows: int supportedHandles = 0; Curesult result = cuDeviceGetAttribute(&supportedHandles, CU_DEVICE_ATTRIBUTE_MEMPOOL_SUPPORTED_HANDLE_TYPES, dev); In at least one embodiment, one or more software programs may interrogate a particular device to determine whether one or more memory operations, such as memory pool IPC, are supported by the device. In at least one embodiment, CU_DEVICE_ATTRIBUTE_MEMPOOL_SUPPORTED_HANDLE_TYPES is an attribute specific to one or more APIs, such as CUDA or any other API described further herein. In at least one embodiment, CU_DEVICE_ATTRIBUTE_MEMPOOL_SUPPORTED_HANDLE_TYPES is a data value that includes data indicating one or more types of data, including information for indicating one or more memory addresses, such as handles, to be queried within one or more devices.

[0028] In at least one embodiment, deviceGetAttribute is a set of instructions that, when executed, performs one or more API operations. In at least one embodiment, deviceGetAttribute is an API call 302 or an interface to an API call 302. In at least one embodiment, cuDeviceGetAttribute is a set of instructions provided by an API to facilitate parallel computing, such as CUDA. In at least one embodiment, deviceGetAttribute, cuDeviceGetAttribute, or any other API call 302 interface to one or more APIs or API functions returns one or more handles as a result of API response 304. In at least one embodiment, deviceGetAttribute, cuDeviceGetAttribute, or any other API call 302 interface to one or more APIs or API functions returns one or more API indicators as a result of API response 304. In at least one embodiment, the one or more handles and / or other data returned by API response 304 includes a mask of supported handle types as a result of receiving CU_DEVICE_ATTRIBUTE_MEMPOOL_SUPPORTED_HANDLE_TYPES as a parameter. In at least one embodiment, the one or more API indicators include a mask of supported handle types as a result of receiving CU_DEVICE_ATTRIBUTE_MEMPOOL_SUPPORTED_HANDLE_TYPES as a parameter. In at least one embodiment, the one or more API calls 302 accept as a parameter any device identifier that has a handle type set in the mask returned as a result of the one or more API calls 302, as described above. In at least one embodiment, the one or more API calls 302 accept as a parameter any memory set identifier that has a handle type set in the mask returned as a result of the one or more API calls 302, as described above.In at least one embodiment, one or more functions to be called by one or more API calls 302, such as cuMempoolExportToShareableHandle and cuMempoolImportFromShareableHandle, may return any data value to indicate information about whether memory of one or more devices is shareable, including a data value that indicates true or any other data value that indicates success. In at least one embodiment, one or more functions to be called by one or more API calls 302, such as cuMempoolExportToShareableHandle and cuMempoolImportFromShareableHandle, may return any API indicator, including a data value that indicates true or any other data value that indicates success.

[0029] FIG. 4 is a block diagram illustrating APIs 402, 404 for determining one or more attributes of one or more memory blocks, regions, and / or pools of memory used by one or more computing devices, according to at least one embodiment. In at least one embodiment, the one or more APIs 402, 404 include one or more API calls 402 and / or one or more API responses 404. In at least one embodiment, an API call 402, such as those described above in conjunction with FIGS. 1 and 2, receives one or more data values ​​as parameters and causes one or more APIs or other software libraries to determine, calculate, or generate information indicating one or more characteristics of the one or more memory blocks, regions, and / or pools of memory indicated by the one or more parameters, such as usage information. In at least one embodiment, an API response 404 returns, communicates, or indicates one or more data values ​​including information about the one or more memory blocks, regions, and / or pools of memory, as described above in conjunction with FIGS. 1-3.

[0030] In at least one embodiment, one or more API calls 302 cause one or more APIs or other software libraries, such as those described above in conjunction with FIG. 1, to calculate, generate, or determine information about one or more memory blocks, regions, and / or pools of memory indicated by one or more memory set identifier parameters to the one or more API calls 302. In at least one embodiment, a memory set identifier is one or more data values ​​that include information to indicate one or more memory blocks and / or memory regions, such as pools of memory, as described above in conjunction with FIG. 1. In at least one embodiment, one or more API calls 402, when invoked, cause one or more software instructions to execute one or more software instructions, where the one or more software instructions calculate, generate, or determine one or more attributes of one or more memory blocks, regions, and / or pools of memory indicated by one or more attribute indicator parameters to the one or more API calls 402. In at least one embodiment, the attribute indicator is a data value that includes information to indicate one or more characteristics of one or more memory blocks, regions, and / or pools of memory, such as usage information, as described below. In at least one embodiment, in response to one or more API calls 402, the one or more APIs cause or implement API response 404 to indicate one or more data values ​​that include the attribute information indicated by the attribute indicator parameter to API call 402. In at least one embodiment, the attribute information is one or more data values ​​that include information about one or more memory blocks, regions, and / or pools of memory, such as usage information, or any other attribute of said one or more memory blocks, regions, and / or pools of memory, as further described herein.

[0031] In at least one embodiment, one or more API calls 402, when invoked, cause one or more APIs to collect attribute information indicated by one or more attribute indicator parameters for one or more memory blocks, regions, and / or pools of memory indicated by one or more memory set identifier parameters. In at least one embodiment, the one or more APIs, in response to the one or more API calls 402, indicate information about one or more storage locations referenced by the one or more APIs. In at least one embodiment, the one or more storage locations referenced by the one or more APIs are one or more memory blocks, regions, and / or pools of memory, such as those described above in conjunction with FIG. 1. In at least one embodiment, the one or more storage locations referenced by the one or more APIs are indicated to the one or more APIs by one or more memory set identifier parameters that identify one or more memory blocks, regions, and / or pools of memory. In at least one embodiment, one or more attributes of one or more memory blocks, regions, and / or pools of memory include usage statistics. In at least one embodiment, in response to one or more API calls 402, a user-mode driver as further described herein collects one or more attributes for one or more memory blocks, regions, and / or pools of memory. In at least one embodiment, in response to one or more API calls 402, the user-mode driver calculates statistics indicative of attribute information indicated by one or more attribute indicators. In at least one embodiment, in response to one or more API calls 402, the one or more APIs execute one or more API responses 404 to indicate or return data including attribute information to one or more software programs executing the one or more API calls 402.In at least one embodiment, as a result of one or more API calls 402, the API and / or user-mode driver calculates or collects attribute information indicative of the total device memory currently reserved and / or cached by a logical grouping or pool of memory, such as a memory pool, and provides it to the one or more API calls 402 as an API response 404. In at least one embodiment, as a result of one or more API calls 402, the API and / or user-mode driver calculates or collects attribute information indicative of the amount of memory currently allocated and / or in use and provides it to the one or more API calls 402 as an API response 404. In at least one embodiment, as a result of one or more API calls 402, the API and / or user-mode driver calculates or collects attribute information indicative of a historical high-water mark or a maximum amount of currently reserved and / or cached memory and provides it to the one or more API calls 402 as an API response 404. In at least one embodiment, as a result of one or more API calls 402, an API and / or user-mode driver calculates or collects attribute information indicating a historical high watermark or maximum amount of allocated memory and provides it to the one or more API calls 402 as an API response 404. In at least one embodiment, the one or more API calls 402 cause the one or more APIs to reset one or more attributes of one or more memory blocks, regions, and / or pools of memory, such as usage statistics, or attributes collected or calculated by the user-mode driver.

[0032] In at least one embodiment, the attribute information indicated by one or more API responses 404 includes data values ​​such as: enum CUmemPool_attribute { CU_MEMPOOL_ATTR_RESERVED_MEM_CURRENT, CU_MEMPOOL_ATTR_RESERVED_MEM_HIGH, CU_MEMPOOL_ATTR_USED_MEM_CURRENT, CU_MEMPOOL_ATTR_USED_MEM_HIGH } In at least one embodiment, the attribute information includes one or more data values ​​indicated by an enumeration or enum, as described above, and may be retrieved or set as a result of one or more API calls 402, such as memPoolGetAttribute and / or memPoolSetAttribute. In at least one embodiment, the attribute information includes one or more data values ​​indicated by an enumeration or enum, such as CUmemPool_attribute, and is indicated by an API response 404 as a result of one or more API calls 402, such as CUDA corresponding cuMemPoolGetAttribute and cuMemPoolSetAttribute. In at least one embodiment, the attribute information including one or more data values ​​is retrieved, calculated, generated, or set as a result of any of the one or more API calls 402 described further herein. In at least one embodiment, the CU_MEMPOOL_ATTR_RESERVED_MEM_CURRENT attribute indicator is a data value that is presented to one or more API calls 402 to receive attribute information via an API response 404, the data value including a data result indicating the amount of physical memory currently allocated to a pool of memory, such as a memory pool. In at least one embodiment, any attempt to set the attribute indicated by CU_MEMPOOL_ATTR_RESERVED_MEM_CURRENT returns an invalid data value or a data value indicating an invalid value. In at least one embodiment, the CU_MEMPOOL_ATTR_RESERVED_MEM_HIGH attribute indicator is a data value that is presented to one or more API calls 402 to receive attribute information, the data result including a data result indicating the maximum value achieved by another attribute, such as CU_MEMPOOL_ATTR_RESERVED_MEM_CURRENT, as described above.In at least one embodiment, any attempt to set the attribute indicated by CU_MEMPOOL_ATTR_RESERVED_MEM_HIGH causes any high-water mark value returned as a result of a call to cuMemPoolGetAttribute or any other function provided by one or more APIs using the CU_MEMPOOL_ATTR_RESERVED_MEM_HIGH attribute indicator as a parameter to be reset. In at least one embodiment, the CU_MEMPOOL_ATTR_USED_MEM_CURRENT attribute indicator is a data value indicated in an API response 404 to one or more API calls 402 to receive attribute information including a data result indicating the total size of allocations that have not yet been freed. In at least one embodiment, any attempt to set the attribute indicated by CU_MEMPOOL_ATTR_USED_MEM_CURRENT returns an invalid data value or a data value indicating an invalid value. In at least one embodiment, the CU_MEMPOOL_ATTR_USED_MEM_HIGH attribute indicator is a data value indicated in an API response 404 to one or more API calls 402 to receive attribute information including a data result indicating the maximum value achieved by another attribute, such as CU_MEMPOOL_ATTR_USED_MEM_CURRENT, as described above. In at least one embodiment, any attempt to set the attribute indicated by CU_MEMPOOL_ATTR_USED_MEM_HIGH causes any high-water mark value returned as a result of the API call 402 to cuMemPoolGetAttribute or any other function provided by one or more APIs using the CU_MEMPOOL_ATTR_USED_MEM_HIGH attribute indicator as a parameter to be reset.

[0033] In at least one embodiment, an exemplary API call 402 for querying usage statistics for one or more groupings or pools of memory, such as a memory pool, is as follows: uint64_t poolAllocatedMem = 0; CUresult result = cuMemPoolGetAttribute(pool, CU_MEMPOOL_ATTR_REERVED_MEM_CURRENT, &poolAllocatedMem); In at least one embodiment, a memPoolGetAttribute or any other API call 402 to one or more APIs, including functions provided by the one or more APIs, returns attribute information via an API response 404, including one or more results indicating data values ​​corresponding to one or more parameters provided to memPoolGetAttribute or other functions provided by the one or more APIs. In at least one embodiment, an API call 402, such as cuMemPoolGetAttribute, causes an API response 404 to return attribute information including one or more results indicating data values ​​corresponding to one or more attribute indicator parameters provided to the cuMemPoolGetAttribute API call 402. In at least one embodiment, one or more parameters provided to one or more API calls 402 to memPoolGetAttribute, memPoolSetAttribute, cuMemPoolGetAttribute, cuMemPoolSetAttribute, or any other functions provided by one or more APIs, are described above in conjunction with CUmemPool_attribute or other attributes.

[0034] In at least one embodiment, one or more API calls 402, such as memPoolGetAttribute, memPoolSetAttribute, cuMemPoolGetAttribute, cuMemPoolSetAttribute, or any other APIs described further herein, cause a user-mode driver corresponding to the one or more APIs to collect or calculate data returned via an API response 404 as a result of the one or more API calls 402. In at least one embodiment, one or more API calls 402, such as memPoolGetAttribute, memPoolSetAttribute, cuMemPoolGetAttribute, cuMemPoolSetAttribute, or any other function provided by one or more APIs, cause any other software function supporting the one or more APIs to collect or calculate attribute information returned as a result of the one or more API calls 402. In at least one embodiment, one or more software programs execute one or more API calls, such as memPoolGetAttribute, memPoolSetAttribute, cuMemPoolGetAttribute, cuMemPoolSetAttribute, or any other function provided by one or more APIs, to reset one or more usage data values ​​or statistics indicated to the one or more API calls by one or more attribute indicator parameters.

[0035] 5 is a diagram of a process 500 for determining whether one or more memory addresses indicated by one or more memory location identifiers are included in one or more memory sets by one or more APIs, according to at least one embodiment. In at least one embodiment, process 500 begins 502 by receiving one or more memory location identifiers as a result of one or more API calls, such as those described above in conjunction with FIGURES 1 and 2. In at least one embodiment, the one or more memory location identifiers are data values, including pointers, memory addresses, or any other data values ​​that can be used to identify one or more locations in memory, as described above in conjunction with FIGURE 2.

[0036] In at least one embodiment, when one or more APIs receive one or more memory location identifiers as a result of one or more API calls, as described above in conjunction with FIG. 2, the one or more APIs perform one or more operations to determine and / or calculate 506 whether the one or more memory location identifiers are within one or more memory sets, as described above in conjunction with FIG. 1.

[0037] In at least one embodiment, if one or more memory location identifiers received 504 by one or more APIs as parameters to one or more API calls are within one or more memory sets 506, the one or more APIs return one or more memory set identifiers via one or more API responses such as described above in conjunction with Figure 2. In at least one embodiment, if one or more memory location identifiers received 504 by one or more APIs as parameters to one or more API calls are not within one or more memory sets 506, the one or more APIs return one or more data values ​​indicating NULL values ​​via one or more API responses such as described above in conjunction with Figure 2. In at least one embodiment, once the one or more APIs implement one or more API responses 508, 510 as a result of the one or more API calls, the process 500 for determining whether one or more memory addresses indicated by one or more memory location identifiers by the one or more APIs are included in one or more memory sets ends 512.

[0038] 6 is a diagram of a process for determining whether one or more memory blocks used by one or more computing devices are shared and / or were shared during execution of one or more software modules by one or more APIs, according to at least one embodiment. In at least one embodiment, process 600 begins 602 by one or more APIs receiving one or more device identifiers 604 as a result of one or more API calls, as described above in conjunction with FIGS. 2 and 3. In at least one embodiment, the device identifiers include information for identifying one or more memory blocks, regions, and / or pools, as described above in conjunction with FIGS. 1 and 3.

[0039] In at least one embodiment, when one or more APIs receive the device identifiers as a result of one or more API calls 604, the one or more APIs determine whether one or more memory sets usable by the one or more devices indicated by the one or more devices support sharing during execution of one or more software modules, as described above in conjunction with Figure 3. In at least one embodiment, in response to the one or more API calls to determine whether one or more memory sets support sharing during execution of one or more software modules, the one or more APIs return 608 one or more handles and / or other data values ​​as described above in conjunction with Figure 3 and further described herein. In at least one embodiment, the one or more handles are one or more data values ​​usable to indicate and / or share one or more memory sets as described herein. In at least one embodiment, once one or more APIs execute one or more API responses and return one or more handles and / or other data values ​​described above in conjunction with FIG. 3 608, the process for determining whether one or more memory blocks to be used by one or more computing devices by one or more APIs are shared and / or were shared during execution of one or more software modules ends 612.

[0040] 7 is a diagram of a process 700 for determining one or more attributes of one or more memory blocks used by one or more computing devices in response to one or more calls to one or more APIs, according to at least one embodiment. In at least one embodiment, process 700 begins 702 by one or more APIs receiving one or more memory set identifiers and / or one or more attribute identifiers as a result of one or more API calls, as described above in conjunction with FIG. 4. In at least one embodiment, the one or more attribute identifiers are data values ​​that include information to indicate one or more attributes of one or more memory blocks, regions, and / or pools, as described above in conjunction with FIG.

[0041] In at least one embodiment, the one or more APIs determine one or more attributes of one or more memory blocks, regions, and / or pools indicated by one or more attribute identifiers received as parameters to the one or more API calls. In at least one embodiment, the one or more APIs calculate 706 attribute information for one or more memory sets indicated as parameters to the one or more API calls, as described above in conjunction with FIG. 4. In at least one embodiment, the attribute information includes data indicating one or more usage values ​​for the one or more memory blocks, regions, and / or pools. In at least one embodiment, the attribute information includes data indicating any other attributes of the one or more memory blocks, regions, and / or pools described further herein.

[0042] In at least one embodiment, in response to the one or more API calls, the one or more APIs return 708 the attribute information through one or more API responses, as described above in conjunction with Figure 4. In at least one embodiment, once the one or more APIs execute the one or more API responses to return 708 the attribute information as a result of the one or more API calls, the process 700 for determining one or more attributes of one or more memory blocks to be used by one or more computing devices in response to one or more calls to one or more APIs ends 712.

[0043] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concept may be practiced without one or more of these specific details.

[0044] Data Center 8 illustrates an exemplary data center 800, according to at least one embodiment. In at least one embodiment, data center 800 includes, but is not limited to, a data center infrastructure layer 810, a framework layer 820, a software layer 830, and an application layer 840. In at least one embodiment, software layer 830 and / or application layer 840 include instructions that, when executed, cause a processor to implement, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-7.

[0045] In at least one embodiment, as shown in FIG. 8 , data center infrastructure layer 810 may include a resource orchestrator 812, grouped computing resources 814, and node computing resources (“node CR”) 816(1) through 816(N), where “N” represents any positive integer. In at least one embodiment, nodes CR816(1)-816(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), data processing units (“DPUs”) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, cooling modules, etc. In at least one embodiment, one or more nodes CR from among nodes CR816(1)-816(N) may be a server having one or more of the computing resources described above.

[0046] In at least one embodiment, the grouped computing resources 814 may include a distinct grouping of node CRs housed within one or more racks (not shown), or many racks housed in a data center at various geographic locations (also not shown). The distinct groupings of node CRs within the grouped computing resources 814 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0047] In at least one embodiment, resource orchestrator 812 may configure or otherwise control one or more nodes CR 816(1)-816(N) and / or grouped computing resources 814. In at least one embodiment, resource orchestrator 812 may include a software design infrastructure (“SDI”) management entity for data center 800. In at least one embodiment, resource orchestrator 812 may include hardware, software, or some combination thereof.

[0048] 8 , framework layer 820 includes, but is not limited to, a job scheduler 832, a configuration manager 834, a resource manager 836, and a distributed file system 838. In at least one embodiment, framework layer 820 may include a framework for supporting software 852 in software layer 830 and / or one or more applications 842 in application layer 840. In at least one embodiment, software 852 or application(s) 842 may include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure, respectively. In at least one embodiment, framework layer 820 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter “Spark”), which may utilize distributed file system 838 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 832 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 800. In at least one embodiment, configuration manager 834 may be capable of configuring different tiers, such as software tier 830 and framework tier 820, which includes Spark and distributed file system 838 to support large-scale data processing. In at least one embodiment, resource manager 836 may be capable of managing clustered or grouped computing resources mapped or allocated to support distributed file system 838 and job scheduler 832. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 814 in data center infrastructure tier 810.In at least one embodiment, resource manager 836 may manage these mapped or allocated computing resources in coordination with resource orchestrator 812.

[0049] In at least one embodiment, software 852 included in software layer 830 may include software used by nodes CR 816(1)-816(N), grouped computing resources 814, and / or at least a portion of distributed file system 838 of framework layer 820. The one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0050] In at least one embodiment, the application(s) 842 included in the application layer 840 may include one or more types of applications used by the nodes CR 816(1)-816(N), the grouped computing resources 814, and / or at least a portion of the distributed file system 838 of the framework layer 820. At least one or more types of applications may include, but are not limited to, CUDA applications.

[0051] In at least one embodiment, any of configuration manager 834, resource manager 836, and resource orchestrator 812 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may relieve data center operators of data center 800 from determining potentially faulty configurations and potentially avoiding underutilized and / or underperforming portions of the data center.

[0052] Computer-Based Systems The following diagram describes an exemplary computer-based system that may be used to implement at least one embodiment, but is not limited to the embodiment.

[0053] FIG. 9 illustrates a processing system 900 according to at least one embodiment. In at least one embodiment, the processing system 900 includes one or more processors 902 and one or more graphics processors 908 and may be a single-processor desktop system, a multiprocessor workstation system, or a server system having multiple processors 902 or processor cores 907. In at least one embodiment, the processing system 900 is a processing platform integrated into a system-on-a-chip ("SoC") integrated circuit for use in a mobile, handheld, or embedded device. In at least one embodiment, the processor 900 includes hardware for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, the processor 900 includes hardware for executing one or more instructions that, when executed, cause the processor 900 to perform the various operations described above in conjunction with FIGS. 1-7.

[0054] In at least one embodiment, processing system 900 may include or be incorporated within a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, processing system 900 is a mobile phone, a smartphone, a tablet computing device, or a mobile internet device. In at least one embodiment, processing system 900 may also include, be coupled to, or be incorporated within a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 900 is a television or set-top box device having one or more processors 902 and a graphical interface generated by one or more graphics processors 908.

[0055] In at least one embodiment, the one or more processors 902 each include one or more processor cores 907 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 907 is configured to process a particular instruction set 909. In at least one embodiment, the instruction set 909 may facilitate Complex Instruction Set Computing ("CISC"), Reduced Instruction Set Computing ("RISC"), or computing via Very Long Instruction Words ("VLIW"). In at least one embodiment, the processor cores 907 may each process a different instruction set 909, and the instruction set 909 may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 907 may also include other processing devices, such as a digital signal processor ("DSP").

[0056] In at least one embodiment, processor 902 includes cache memory (“cache”) 904. In at least one embodiment, processor 902 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 902. In at least one embodiment, processor 902 also uses an external cache (e.g., a level 3 (“L3”) cache or a last level cache (“LLC”)) (not shown), which may be shared among processor cores 907 using known cache coherency techniques. In at least one embodiment, processor 902 additionally includes a register file 906, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 906 may include general-purpose registers or other registers.

[0057] In at least one embodiment, one or more processors 902 are coupled to one or more interface buses 910 for transmitting communication signals, such as address, data, or control signals, between the processors 902 and other components in the processing system 900. In at least one embodiment, the interface bus 910 in one embodiment may be a processor bus, such as a version of a Direct Media Interface ("DMI") bus. In at least one embodiment, the interface bus 910 is not limited to a DMI bus, but may include one or more peripheral component interconnect buses (e.g., Peripheral Component Interconnect, PCI Express ("PCIe")), a memory bus, or other types of interface buses. In at least one embodiment, the processor(s) 902 include an integrated memory controller 916 and a platform controller hub 930. In at least one embodiment, a memory controller 916 facilitates communication between memory devices and other components of the processing system 900, and a platform controller hub (“PCH”) 930 provides connectivity to I / O devices via a local input / output (“I / O”) bus.

[0058] In at least one embodiment, memory device 920 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, a phase-change memory device, or any other memory device having suitable performance to serve as processor memory. In at least one embodiment, memory device 920 may operate as system memory for processing system 900 to store data 922 and instructions 921 for use when one or more processors 902 execute applications or processes. In at least one embodiment, memory controller 916 also couples to an optional external graphics processor 912, which may communicate with one or more graphics processors 908 in processor 902 to perform graphics and media operations. In at least one embodiment, display device 911 may be connected to processor(s) 902. In at least one embodiment, display device 911 may include one or more of an internal display device, such as in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device 911 may include a head mounted display ("HMD"), such as a stereoscopic display device for use in virtual reality ("VR") or augmented reality ("AR") applications.

[0059] In at least one embodiment, platform controller hub 930 allows peripherals to connect to memory device 920 and processor 902 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 946, a network controller 934, a firmware interface 928, a wireless transceiver 926, a touch sensor 925, and a data storage device 924 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 924 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as PCI or PCIe. In at least one embodiment, touch sensor 925 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, wireless transceiver 926 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution ("LTE") transceiver. In at least one embodiment, firmware interface 928 enables communication with system firmware and may be, for example, a unified extensible firmware interface ("UEFI"). In at least one embodiment, network controller 934 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples to interface bus 910. In at least one embodiment, audio controller 946 is a multi-channel high-definition audio controller.In at least one embodiment, processing system 900 includes an optional legacy I / O controller 940 for coupling legacy (e.g., Personal System 2 (“PS / 2”)) devices to processing system 900. In at least one embodiment, platform controller hub 930 can also connect to one or more Universal Serial Bus (“USB”) controller 942-connected input devices, such as a keyboard and mouse combination 943, a camera 944, or other USB input devices.

[0060] In at least one embodiment, instances of memory controller 916 and platform controller hub 930 may be embedded in a discreet external graphics processor, such as external graphics processor 912. In at least one embodiment, platform controller hub 930 and / or memory controller 916 may be external to one or more processors 902. For example, in at least one embodiment, processing system 900 may include external memory controller 916 and platform controller hub 930, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset in communication with processor(s) 902.

[0061] FIG. 10 illustrates a computer system 1000 according to at least one embodiment. In at least one embodiment, computer system 1000 may be a system, a SOC, or some combination with interconnected devices and components. In at least one embodiment, computer system 1000 is formed with a processor 1002, which may include an execution unit for executing instructions. In at least one embodiment, computer system 1000 may include components, such as, but not limited to, processor 1002, to employ an execution unit that includes logic for implementing algorithms for processing data. In at least one embodiment, computer system 1000 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™, and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1000 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used. In at least one embodiment, computer system 1000 includes hardware for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, computer system 1000 includes hardware for executing one or more instructions that, when executed, cause computer system 1000 to perform the various operations described above in conjunction with FIGS. 1-7.

[0062] In at least one embodiment, computer system 1000 may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (DSP), an SoC, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system capable of performing one or more instructions.

[0063] In at least one embodiment, computer system 1000 may include, but is not limited to, a processor 1002, which may include one or more execution units 1008 that may be configured to execute, but is not limited to, Compute Unified Device Architecture (“CUDA”) (CUDA® is developed by NVIDIA Corporation of Santa Clara, California) programs. In at least one embodiment, the CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 1000 is a single-processor desktop or server system. In at least one embodiment, computer system 1000 may be a multiprocessor system. In at least one embodiment, processor 1002 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as, for example, a digital signal processor. In at least one embodiment, the processor 1002 may be coupled to a processor bus 1010 that may transmit data signals between the processor 1002 and other components in the computer system 1000.

[0064] In at least one embodiment, processor 1002 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1002. In at least one embodiment, processor 1002 may also include a combination of both internal and external cache. In at least one embodiment, register file 1006 may store different types of data in various registers, including, but not limited to, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0065] In at least one embodiment, an execution unit 1008, including logic for performing integer and floating-point operations, may also be present in the processor 1002. The processor 1002 may also include a microcode (“u-code”) read-only memory (“ROM”) that stores microcode for some macroinstructions. In at least one embodiment, the execution unit 1008 may include logic for dealing with a packed instruction set 1009. In at least one embodiment, by including the packed instruction set 1009, along with associated circuitry for executing the instructions, in the instruction set of the general-purpose processor 1002, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 1002. In at least one embodiment, many multimedia applications may be accelerated and run more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0066] In at least one embodiment, the execution unit 1008 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuitry. In at least one embodiment, the computer system 1000 may include, but is not limited to, a memory 1020. In at least one embodiment, the memory 1020 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other memory device. The memory 1020 may store instruction(s) 1019 and / or data 1021 represented by data signals that may be executed by the processor 1002.

[0067] In at least one embodiment, a system logic chip may be coupled to the processor bus 1010 and the memory 1020. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1016, and the processor 1002 may communicate with the MCH 1016 via the processor bus 1010. In at least one embodiment, the MCH 1016 may provide a high-bandwidth memory path 1018 to the memory 1020 for instruction and data storage, and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1016 may direct data signals between the processor 1002, the memory 1020, and other components in the computer system 1000, and may bridge data signals between the processor bus 1010, the memory 1020, and the system I / O 1022. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1016 may be coupled to memory 1020 through a high-bandwidth memory path 1018, and the graphics / video card 1012 may be coupled to the MCH 1016 via an Accelerated Graphics Port (“AGP”) interconnect 1014.

[0068] In at least one embodiment, computer system 1000 may use system I / O 1022, a proprietary hub interface bus, to couple MCH 1016 to I / O controller hub (“ICH”) 1030. In at least one embodiment, ICH 1030 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripherals to memory 1020, a chipset, and processor 1002. Examples may include, but are not limited to, an audio controller 1029, a firmware hub (“flash BIOS”) 1028, a wireless transceiver 1026, data storage 1024, a legacy I / O controller 1023 including a user input interface 1025 and a keyboard interface, a serial expansion port 1027 such as USB, and a network controller 1034. Data storage 1024 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0069] In at least one embodiment, FIG. 10 illustrates a system including interconnected hardware devices or "chips." In at least one embodiment, FIG. 10 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 10 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1000 are interconnected using a Compute Express Link ("CXL") interconnect.

[0070] 11 illustrates a system 1100, according to at least one embodiment. In at least one embodiment, system 1100 is an electronic device utilizing a processor 1110. In at least one embodiment, system 1100 may be, for example, but not limited to, a notebook, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more on-premise or cloud service providers, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0071] In at least one embodiment, system 1100 may include, without limitation, a processor 1110 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. 2 The devices may be coupled using a bus or interface, such as a C bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, USB (versions 1, 2, and 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 11 illustrates a system including interconnected hardware devices or “chips.” In at least one embodiment, FIG. 11 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 11 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of Figure 11 are interconnected using a CXL interconnect. In at least one embodiment, system 1100 includes hardware for implementing the various components and / or performing the various operations described above in conjunction with Figures 1-7. In at least one embodiment, system 1100 includes hardware for executing one or more instructions that, when executed, cause system 1100 to perform the various operations described above in conjunction with Figures 1-7.

[0072] In at least one embodiment, FIG. 11 includes a display 1124, a touch screen 1125, a touch pad 1130, a Near Field Communication ("NFC") unit 1145, a sensor hub 1140, a thermal sensor 1146, an Express Chipset ("EC") 1135, a Trusted Platform Module ("TPM") 1138, a BIOS / firmware / flash memory ("BIOS,FW flash") 1122, a DSP 1160, a Solid State Disk ("SSD") or Hard Disk Drive ("HDD") 1120, a Wireless Local Area Network ("WLAN") unit 1150, a Bluetooth unit 1152, a Wireless Wide Area Network ("WWAN") unit 1154, a Bluetooth® unit 1156, a Bluetooth® unit 1158, a Bluetooth® unit 1159, a Bluetooth® unit 1160, a Bluetooth® unit 1161, a Bluetooth® unit 1162, a Bluetooth® unit 1163, a Bluetooth® unit 1164, a Bluetooth® unit 1165, a Bluetooth® unit 1166, a Bluetooth® unit 1167, a Bluetooth® unit 1168, a Bluetooth® unit 1169, a Bluetooth® unit 1170, a Bluetooth® unit 1172, a Bluetooth® unit 1174, a Bluetooth® unit 1176, a Bluetooth® unit 1178, a Bluetooth® unit 1179, a Bluetooth® unit 1180, a Bluetooth® unit 1182, a Bluetooth® unit 1184, a Bluetooth® unit 1186, a Bluetooth® unit 1188, a Bluetooth® unit 1188, a Bluetooth® unit 1188, a Bluetooth® unit 1189, a Bluetooth® unit 1190, a Bluetooth® unit 1192, a Bluetooth® unit 1194, a Bluetooth® unit 1 Network) 1156, Global Positioning System (“GPS”) 1155, a camera such as a USB 3.0 camera (“USB 3.0 Camera”) 1154, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) implemented, for example, in the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0073] In at least one embodiment, other components may be communicatively coupled to the processor 1110 through the components described above. In at least one embodiment, an accelerometer 1141, an ambient light sensor (“ALS”) 1142, a compass 1143, and a gyroscope 1144 may be communicatively coupled to the sensor hub 1140. In at least one embodiment, a thermal sensor 1139, a fan 1137, a keyboard 1136, and a touchpad 1130 may be communicatively coupled to the EC 1135. In at least one embodiment, a speaker 1163, headphones 1164, and a microphone (“mic”) 1165 may be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 1162, which may be communicatively coupled to the DSP 1160. In at least one embodiment, the audio unit 1162 may include, for example, without limitation, an audio coder / decoder ("codec") and a Class D amplifier. In at least one embodiment, a SIM card ("SIM") 1157 may be communicatively coupled to the WWAN unit 1156. In at least one embodiment, components such as the WLAN unit 1150 and Bluetooth unit 1152, and the WWAN unit 1156 may be implemented in a Next Generation Form Factor ("NGFF").

[0074] 12 illustrates an exemplary integrated circuit 1200, according to at least one embodiment. In at least one embodiment, the exemplary integrated circuit 1200 is an SoC that may be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 1200 includes one or more application processors 1205 (e.g., CPU, DPU), at least one graphics processor 1210, and may additionally include an image processor 1215 and / or a video processor 1220, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1200 includes a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I / O controller 1240. 2 S / I 2 1-7 。 In at least one embodiment, integrated circuit 1200 may include peripheral or bus logic including a high-definition multimedia interface ("HDMI") controller 1250 and a display device 1245 coupled to one or more of a high-definition multimedia interface ("HDMI") controller 1250 and a mobile industry processor interface ("MIPI") display interface 1255. In at least one embodiment, storage may be provided by a flash memory subsystem 1260 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1265 for access to an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1270. In at least one embodiment, example integrated circuit 1200 includes one or more circuits for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7 . In at least one embodiment, the exemplary integrated circuit 1200 includes one or more circuits for executing one or more instructions that, when executed, cause the exemplary integrated circuit 1200 to perform the various operations described above in conjunction with FIGS. 1-7.

[0075] 13 illustrates a computing system 1300, according to at least one embodiment. In at least one embodiment, computing system 1300 includes a processing subsystem 1301 having one or more processors 1302 and system memory 1304 that communicate via an interconnection path that may include a memory hub 1305. In at least one embodiment, memory hub 1305 may be a separate component within a chipset component or may be incorporated within one or more processors 1302. In at least one embodiment, memory hub 1305 couples to an I / O subsystem 1311 via communication link 1306. In at least one embodiment, I / O subsystem 1311 includes an I / O hub 1307 that may enable computing system 1300 to receive input from one or more input devices 1308. In at least one embodiment, I / O hub 1307 can enable a display controller, which may be included in one or more processors 1302, to provide output to one or more display devices 1310A. In at least one embodiment, one or more display devices 1310A coupled with I / O hub 1307 can include local, internal, or embedded display devices. In at least one embodiment, computing system 1300 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, computing system 1300 includes hardware for executing one or more instructions that, when executed, cause computing system 1300 to perform the various operations described above in conjunction with FIGS. 1-7.

[0076] In at least one embodiment, processing subsystem 1301 includes one or more parallel processors 1312 coupled to memory hub 1305 via a bus or other communication link 1313. In at least one embodiment, communication link 1313 may be one of any number of standards-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a vendor-specific communication interface or fabric. In at least one embodiment, one or more parallel processors 1312 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many-integrated-core processor. In at least one embodiment, one or more parallel processors 1312 form a graphics processing subsystem that can output pixels to one of one or more display devices 1310A coupled via I / O hub 1307. In at least one embodiment, the one or more parallel processors 1312 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1310B.

[0077] In at least one embodiment, system storage unit 1314 may connect to I / O hub 1307 to provide storage for computing system 1300. In at least one embodiment, I / O switch 1316 may be used to provide an interface mechanism to enable connections between I / O hub 1307 and other components, such as network adapter 1318 and / or wireless network adapter 1319, which may be embedded in the platform, as well as various other devices, which may be added via one or more add-in devices 1320. In at least one embodiment, network adapter 1318 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1319 may include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more wireless radios.

[0078] In at least one embodiment, computing system 1300 may include other components not expressly shown that may also be connected to I / O hub 1307, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the communication paths interconnecting the various components in FIG. 13 may be implemented using any suitable protocol, such as a PCI-based protocol (e.g., PCIe), or other bus or point-to-point communication interface and / or protocol(s), such as an NVLink high-speed interconnect, or interconnect protocol.

[0079] In at least one embodiment, one or more parallel processors 1312 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, to form a graphics processing unit ("GPU"). In at least one embodiment, one or more parallel processors 1312 incorporate circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 1300 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1312, memory hub 1305, processor(s) 1302, and I / O hub 1307 may be integrated into an SoC integrated circuit. In at least one embodiment, components of computing system 1300 may be integrated into a single package to form a system-in-package ("SIP") configuration. In at least one embodiment, at least a portion of the components of computing system 1300 may be incorporated into a multi-chip module ("MCM"), which may be interconnected with other multi-chip modules to form a modular computing system. In at least one embodiment, I / O subsystem 1311 and display device 1310B are omitted from computing system 1300.

[0080] Processing System The following figures describe exemplary processing systems that may be used to implement, but are not limited to, at least one embodiment.

[0081] FIG. 14 illustrates an accelerated processing unit ("APU") 1400 according to at least one embodiment. In at least one embodiment, the APU 1400 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the APU 1400 may be configured to execute application programs, such as CUDA programs. In at least one embodiment, the APU 1400 includes, but is not limited to, a core complex 1410, a graphics complex 1440, a fabric 1460, an I / O interface 1470, a memory controller 1480, a display controller 1492, and a multimedia engine 1494. In at least one embodiment, the APU 1400 may include, but is not limited to, any number of core complexes 1410, any number of graphics complexes 1450, any number of display controllers 1492, and any number of multimedia engines 1494 in any combination. For purposes of explanation, multiple instances of similar objects are referred to herein with a reference number that identifies the object and, where necessary, a parenthetical number that identifies the instance. In at least one embodiment, APU 1400 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with Figures 1-7. In at least one embodiment, APU 1400 includes hardware for executing one or more instructions that, when executed, cause APU 1400 to perform the various operations described above in conjunction with Figures 1-7.

[0082] In at least one embodiment, core complex 1410 is a CPU, graphics complex 1440 is a GPU, and APU 1400 is a processing unit incorporating 1410 and 1440 on a single chip, without limitation. In at least one embodiment, some tasks may be assigned to core complex 1410 and other tasks may be assigned to graphics complex 1440. In at least one embodiment, core complex 1410 is configured to execute main control software associated with APU 1400, such as an operating system. In at least one embodiment, core complex 1410 is the master processor of APU 1400, controlling and coordinating the operation of the other processors. In at least one embodiment, core complex 1410 issues commands that control the operation of graphics complex 1440. In at least one embodiment, core complex 1410 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1440 may be configured to execute device executable code derived from CUDA source code.

[0083] In at least one embodiment, core complex 1410 includes, but is not limited to, cores 1420(1)-1420(4) and an L3 cache 1430. In at least one embodiment, core complex 1410 may include, but is not limited to, any number of cores 1420 and any number and type of caches in any combination. In at least one embodiment, cores 1420 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1420 is a CPU core.

[0084] In at least one embodiment, each core 1420 includes, but is not limited to, a fetch / decode unit 1422, an integer execution engine 1424, a floating-point execution engine 1426, and an L2 cache 1428. In at least one embodiment, the fetch / decode unit 1422 fetches instructions, decodes such instructions, generates micro-ops, and dispatches separate micro-instructions to the integer execution engine 1424 and the floating-point execution engine 1426. In at least one embodiment, the fetch / decode unit 1422 can simultaneously dispatch one micro-instruction to the integer execution engine 1424 and another micro-instruction to the floating-point execution engine 1426. In at least one embodiment, the integer execution engine 1424 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1426 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch decode unit 1422 dispatches microinstructions to a single execution engine that replaces both the integer execution engine 1424 and the floating-point execution engine 1426 .

[0085] In at least one embodiment, each core 1420(i), where i is an integer representing a particular instance of core 1420, may access an L2 cache 1428(i) included in core 1420(i). In at least one embodiment, each core 1420 included in a core complex 1410(j), where j is an integer representing a particular instance of core complex 1410, is connected to the other cores 1420 included in core complex 1410(j) via an L3 cache 1430(j) included in core complex 1410(j). In at least one embodiment, a core 1420 included in a core complex 1410(j), where j is an integer representing a particular instance of core complex 1410, may access all of the L3 caches 1430(j) included in core complex 1410(j). In at least one embodiment, the L3 cache 1430 may include, without limitation, any number of slices.

[0086] In at least one embodiment, the graphics complex 1440 may be configured to perform compute operations in a highly parallel manner. In at least one embodiment, the graphics complex 1440 is configured to execute graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations related to rendering an image to a display. In at least one embodiment, the graphics complex 1440 is configured to execute non-graphics related operations. In at least one embodiment, the graphics complex 1440 is configured to execute both graphics related and non-graphics related operations.

[0087] In at least one embodiment, the graphics complex 1440 includes, but is not limited to, any number of compute units 1450 and an L2 cache 1442. In at least one embodiment, the compute units 1450 share the L2 cache 1442. In at least one embodiment, the L2 cache 1442 is partitioned. In at least one embodiment, the graphics complex 1440 includes, but is not limited to, any number of compute units 1450 and any number and type of cache (including zero). In at least one embodiment, the graphics complex 1440 includes, but is not limited to, any amount of dedicated graphics hardware.

[0088] In at least one embodiment, each compute unit 1450 includes, but is not limited to, any number of SIMD units 1452 and shared memory 1454. In at least one embodiment, each SIMD unit 1452 may be configured to implement a SIMD architecture and perform operations in parallel. In at least one embodiment, each compute unit 1450 may execute any number of thread blocks, with each thread block executing on a single compute unit 1450. In at least one embodiment, a thread block includes, but is not limited to, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1452 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication may be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via shared memory 1454.

[0089] In at least one embodiment, fabric 1460 is a system interconnect that facilitates data and control transmission across core complex 1410, graphics complex 1440, I / O interface 1470, memory controller 1480, display controller 1492, and multimedia engine 1494. In at least one embodiment, APU 1400 may include any quantity and type of system interconnect in addition to or instead of fabric 1460, which facilitates data and control transmission across any number and type of directly or indirectly linked components, which may be internal or external to APU 1400. In at least one embodiment, I / O interface 1470 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1470. In at least one embodiment, peripheral devices coupled to I / O interface 1470 may include, but are not limited to, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0090] In at least one embodiment, display controller AMD92 displays images on one or more display devices, such as liquid crystal display ("LCD") devices. In at least one embodiment, multimedia engine 1494 includes any quantity and type of circuitry related to multimedia, such as, but not limited to, a video decoder, a video encoder, and an image signal processor. In at least one embodiment, memory controller 1480 facilitates data transfer between APU 1400 and unified system memory 1490. In at least one embodiment, core complex 1410 and graphics complex 1440 share unified system memory 1490.

[0091] In at least one embodiment, the APU 1400 implements a memory subsystem including, but not limited to, any quantity and type of memory controller 1480 and memory devices (e.g., shared memory 1454) that may be dedicated to one component or shared among multiple components. In at least one embodiment, the APU 1400 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1428, L3 cache 1430, and L2 cache 1442), each of which may be private to any number of components (e.g., core 1420, core complex 1410, SIMD unit 1452, compute unit 1450, and graphics complex 1440) or shared among any number of components.

[0092] FIG. 15 illustrates a CPU 1500 according to at least one embodiment. In at least one embodiment, the CPU 1500 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the CPU 1500 may be configured to execute application programs. In at least one embodiment, the CPU 1500 may be configured to execute main control software, such as an operating system. In at least one embodiment, the CPU 1500 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1500 may be configured to execute host executable code derived from CUDA source code, and the external GPU may be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1500 includes, but is not limited to, any number of core complexes 1510, a fabric 1560, an I / O interface 1570, and a memory controller 1580. In at least one embodiment, CPU 1500 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with Figures 1-7. In at least one embodiment, CPU 1500 includes hardware for executing one or more instructions that, when executed, cause CPU 1500 to perform the various operations described above in conjunction with Figures 1-7.

[0093] In at least one embodiment, core complex 1510 includes, but is not limited to, cores 1520(1)-1520(4) and an L3 cache 1530. In at least one embodiment, core complex 1510 may include, but is not limited to, any number of cores 1520 and any number and type of caches in any combination. In at least one embodiment, cores 1520 are configured to execute instructions of a particular ISA. In at least one embodiment, each core 1520 is a CPU core.

[0094] In at least one embodiment, each core 1520 includes, but is not limited to, a fetch / decode unit 1522, an integer execution engine 1524, a floating-point execution engine 1526, and an L2 cache 1528. In at least one embodiment, the fetch / decode unit 1522 fetches instructions, decodes such instructions, generates micro-ops, and dispatches separate micro-instructions to the integer execution engine 1524 and the floating-point execution engine 1526. In at least one embodiment, the fetch / decode unit 1522 can simultaneously dispatch one micro-instruction to the integer execution engine 1524 and another micro-instruction to the floating-point execution engine 1526. In at least one embodiment, the integer execution engine 1524 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1526 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch decode unit 1522 dispatches microinstructions to a single execution engine that replaces both the integer execution engine 1524 and the floating-point execution engine 1526 .

[0095] In at least one embodiment, each core 1520(i), where i is an integer representing a particular instance of core 1520, may access an L2 cache 1528(i) included in core 1520(i). In at least one embodiment, each core 1520 included in a core complex 1510(j), where j is an integer representing a particular instance of core complex 1510, is connected to the other cores 1520 in core complex 1510(j) via an L3 cache 1530(j) included in core complex 1510(j). In at least one embodiment, a core 1520 included in a core complex 1510(j), where j is an integer representing a particular instance of core complex 1510, may access all of the L3 caches 1530(j) included in core complex 1510(j). In at least one embodiment, L3 cache 1530 may include, without limitation, any number of slices.

[0096] In at least one embodiment, fabric 1560 is a system interconnect that facilitates data and control transmission across core complexes 1510(1) through 1510(N), where N is an integer greater than 0, I / O interface 1570, and memory controller 1580. In at least one embodiment, CPU 1500 may include any quantity and type of system interconnect in addition to or instead of fabric 1560, which facilitates data and control transmission across any number and type of directly or indirectly linked components, which may be internal or external to CPU 1500. In at least one embodiment, I / O interface 1570 represents any number and type of I / O interface (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1570. In at least one embodiment, peripheral devices coupled to I / O interface 1570 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0097] In at least one embodiment, memory controller 1580 facilitates data transfer between CPU 1500 and system memory 1590. In at least one embodiment, core complex 1510 and graphics complex 1540 share system memory 1590. In at least one embodiment, CPU 1500 implements a memory subsystem including, but not limited to, any quantity and type of memory controller 1580 and memory devices, which may be dedicated to one component or shared among multiple components. In at least one embodiment, CPU 1500 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1528 and L3 cache 1530), each of which may be private to any number of components (e.g., core 1520 and core complex 1510) or shared among any number of components.

[0098] FIG. 16 illustrates an exemplary accelerator integration slice 1690 according to at least one embodiment. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integration circuit. In at least one embodiment, the accelerator integration circuit provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines included in a graphics acceleration module. The graphics processing engines may each comprise a separate GPU. Alternatively, the graphics processing engine may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU with multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip. In at least one embodiment, the accelerator integration slice 1690 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, the accelerator integrated slice 1690 includes hardware for executing one or more instructions that, when executed, cause the accelerator integrated slice 1690 to perform the various operations described above in conjunction with Figures 1-7.

[0099] Application effective address space 1682 in system memory 1614 stores process element 1683. In one embodiment, process element 1683 is stored in response to GPU call 1681 from application 1680 executing on processor 1607. Process element 1683 contains the process state of the corresponding application 1680. Work descriptor (“WD”) 1684 contained in process element 1683 may be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1684 is a pointer to a job request queue in application effective address space 1682.

[0100] The graphics acceleration module 1646 and / or individual graphics processing engines may be shared by all or a subset of the processes in the system. In at least one embodiment, infrastructure may be included for setting process state and submitting WD 1684 to the graphics acceleration module 1646 to start a job in a virtualized environment.

[0101] In at least one embodiment, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 1646 or an individual graphics processing engine. Because the graphics acceleration module 1646 is owned by a single process, the hypervisor initializes the accelerator integration circuitry for the owning partition, and the operating system initializes the accelerator integration circuitry for the owning process when the graphics acceleration module 1646 is allocated.

[0102] In operation, WD fetch unit 1691 in accelerator integrated slice 1690 fetches the next WD 1684, which contains instructions for work to be performed by one or more graphics processing engines of graphics acceleration module 1646. As shown, data from WD 1684 is stored in register 1645 and may be used by memory management unit (“MMU”) 1639, interrupt management circuitry 1647, and / or context management circuitry 1648. For example, one embodiment of MMU 1639 includes segment / page walk circuitry for accessing segment / page table 1686 within OS virtual address space 1685. Interrupt management circuit 1647 may process interrupt events (“INT”) 1692 received from graphics acceleration module 1646. When performing graphics operations, effective addresses 1693 generated by the graphics processing engines are translated into real addresses by MMU 1639.

[0103] In one embodiment, the same set of registers 1645 may be replicated for each graphics processing engine and / or graphics acceleration module 1646 and initialized by the hypervisor or operating system. Each of these replicated registers may be included in the accelerator integration slice 1690. Exemplary registers that may be initialized by the hypervisor are shown in Table 1. [Table 1]

[0104] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 2]

[0105] In one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or a particular graphics processing engine. The WD 1684 may contain all the information needed by the graphics processing engine to perform work, or the WD 1684 may be a pointer to a memory location where the application has set up a command queue for work to be completed.

[0106] 17A-17B illustrate exemplary graphics processors, according to at least one embodiment. In at least one embodiment, any of the exemplary graphics processors may be fabricated using one or more IP cores. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is for use within an SoC.

[0107] FIG. 17A illustrates an exemplary graphics processor 1710 of an SoC integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 17B illustrates an additional exemplary graphics processor 1740 of an SoC integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the graphics processor 1710 of FIG. 17A is a low-power graphics processor core. In at least one embodiment, the graphics processor 1740 of FIG. 17B is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1710, 1740 may be a variation of the graphics processor 1210 of FIG. 12. In at least one embodiment, the graphics processor 1710 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, graphics processor 1710 includes hardware for executing one or more instructions that, when executed, cause graphics processor 1710 to perform the various operations described above in conjunction with FIGS. 1-7.

[0108] In at least one embodiment, the graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D-1715N-1, and 1715N). In at least one embodiment, the graphics processor 1710 can execute different shader programs through separate logic, whereby the vertex processor 1705 is optimized to perform operations for vertex shader programs, and one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1705 performs the vertex processing stage of the 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, fragment processor(s) 1715A-1715N use the primitive and vertex data generated by vertex processor 1705 to create a frame buffer that is displayed on a display device. In at least one embodiment, fragment processor(s) 1715A-1715N are optimized to execute fragment shader programs such as those provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs such as those provided in the Direct 3D API.

[0109] In at least one embodiment, the graphics processor 1710 additionally includes one or more MMUs 1720A-1720B, cache(s) 1725A-1725B, and circuit interconnect(s) 1730A-1730B. In at least one embodiment, the one or more MMUs 1720A-1720B provide virtual-to-physical address mapping for the graphics processor 1710, including the vertex processor 1705 and / or fragment processor(s) 1715A-1715N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 1725A-1725B. In at least one embodiment, one or more MMUs 1720A-1720B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1205, image processor 1215, and / or video processor 1220 of Figure 12, thereby allowing each processor 1205-1220 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable graphics processor 1710 to interface with other IP cores in the SoC, either via the SoC's internal bus or via a direct connection.

[0110] In at least one embodiment, graphics processor 1740 includes one or more MMUs 1720A-1720B, caches 1725A-1725B, and circuit interconnects 1730A-1730B of graphics processor 1710 of FIG. 17A. In at least one embodiment, the graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F-1755N-1, and 1755N), where the one or more shader cores 1755A-1755N provide a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, graphics processor 1740 includes an inter-core task manager 1745 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1755A-1755N, and a tiling unit 1758 for accelerating tiling operations for tile-based rendering, where rendering operations for a scene are subdivided in image space, e.g., to exploit local spatial coherence within the scene or to optimize internal cache usage. In at least one embodiment, graphics processor 1740 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, graphics processor 1740 includes hardware for executing one or more instructions that, when executed, cause graphics processor 1740 to perform the various operations described above in conjunction with FIGS. 1-7.

[0111] FIG. 18A illustrates a graphics core 1800 according to at least one embodiment. In at least one embodiment, graphics core 1800 may be included within graphics processor 1210 of FIG. 12. In at least one embodiment, graphics core 1800 may be unified shader cores 1755A-1755N as in FIG. 17B. In at least one embodiment, graphics core 1800 includes a shared instruction cache 1802, a texture unit 1818, and a cache / shared memory 1820, which are common to execution resources within graphics core 1800. In at least one embodiment, graphics core 1800 may include multiple slices 1801A-1801N, or partitions for each core, and a graphics processor may include multiple instances of graphics core 1800. The slices 1801A-1801N may include support logic including a local instruction cache 1804A-1804N, a thread scheduler 1806A-1806N, a thread dispatcher 1808A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional function units (“AFUs”) 1812A-1812N, floating-point units (“FPUs”) 1814A-1814N, integer arithmetic logic units (“ALUs”) 1816-1816N, address computational units (“ACUs”) 1813A-1813N, double-precision floating-point units (“DPFPUs”) 1815A-1815N, and matrix processing units (“MPUs”) 1817A-1817N.In at least one embodiment, graphics core 1800 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with Figures 1-7. In at least one embodiment, graphics core 1800 includes hardware for executing one or more instructions that, when executed, cause graphics core 1800 to perform the various operations described above in conjunction with Figures 1-7.

[0112] In at least one embodiment, the FPUs 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 1815A-1815N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and may be configured for mixed-precision operations. In at least one embodiment, the MPUs 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1817A-1817N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication ("GEMM"). In at least one embodiment, the AFUs 1812A-1812N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0113] FIG. 18B illustrates a general-purpose graphics processing unit (“GPGPU”) 1830, according to at least one embodiment. In at least one embodiment, the GPGPU 1830 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, the GPGPU 1830 may be configured to allow highly parallel compute operations to be performed by an array of GPUs. In at least one embodiment, the GPGPU 1830 may be directly linked to other instances of the GPGPU 1830 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 to enable connection with a host processor. In at least one embodiment, the host interface 1832 is a PCIe interface. In at least one embodiment, the host interface 1832 may be a vendor-specific communication interface or fabric. In at least one embodiment, the GPGPU 1830 receives commands from the host processor and distributes execution threads associated with those commands across the set of compute clusters 1836A-1836H using a global scheduler 1834. In at least one embodiment, the compute clusters 1836A-1836H share a cache memory 1838. In at least one embodiment, the cache memory 1838 can serve as a higher-level cache for the cache memories within the compute clusters 1836A-1836H. In at least one embodiment, the GPGPU 1830 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, the GPGPU 1830 includes hardware for executing one or more instructions that, when executed, cause the GPGPU 1830 to perform the various operations described above in conjunction with FIGS. 1-7.

[0114] In at least one embodiment, GPGPU 1830 includes memory 1844A-1844B coupled to compute clusters 1836A-1836H via a set of memory controllers 1842A-1842B. In at least one embodiment, memory 1844A-1844B can include various types of memory devices, including DRAM or graphics random access memory such as synchronous graphics random access memory ("SGRAM"), including graphics double data rate ("GDDR") memory.

[0115] In at least one embodiment, compute clusters 1836A-1836H each include a set of graphics cores, such as graphics core 1800 of FIG. 18A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for computations associated with CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, and a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0116] In at least one embodiment, multiple instances of GPGPU 1830 may be configured to operate as a compute cluster. The compute clusters 1836A-1836H may implement any technically feasible communication technique for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 1830 communicate via host interface 1832. In at least one embodiment, GPGPU 1830 includes an I / O hub 1839 that couples GPGPU 1830 to a GPU link 1840 that enables direct connection to other instances of GPGPU 1830. In at least one embodiment, GPU link 1840 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1830. In at least one embodiment, GPU link 1840 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs 1830 or parallel processors. In at least one embodiment, multiple instances of GPGPU 1830 are located in separate data processing systems and communicate via a network device accessible via host interface 1832. In at least one embodiment, GPU link 1840 may be configured to allow connection to a host processor in addition to, or as an alternative to, host interface 1832. In at least one embodiment, GPGPU 1830 may be configured to execute CUDA programs.

[0117] 19A illustrates a parallel processor 1900, according to at least one embodiment. In at least one embodiment, various components of parallel processor 1900 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (“ASIC”), or an FPGA.

[0118] In at least one embodiment, parallel processor 1900 includes parallel processing units 1902. In at least one embodiment, parallel processing units 1902 include I / O units 1904 that enable communication with other devices, including other instances of parallel processing units 1902. In at least one embodiment, I / O units 1904 may be directly connected to other devices. In at least one embodiment, I / O units 1904 connect to other devices through the use of a hub or switch interface, such as memory hub 1905. In at least one embodiment, the connection between memory hub 1905 and I / O units 1904 forms a communication link. In at least one embodiment, I / O units 1904 connect to host interface 1906 and memory crossbar 1916, where host interface 1906 receives commands intended to perform processing operations and memory crossbar 1916 receives commands intended to perform memory operations. In at least one embodiment, parallel processor 1900 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with Figures 1-7. In at least one embodiment, parallel processor 1900 includes hardware for executing one or more instructions that, when executed, cause parallel processor 1900 to perform the various operations described above in conjunction with Figures 1-7.

[0119] In at least one embodiment, when host interface 1906 receives command buffers via I / O unit 1904, host interface 1906 can direct work operations to implement those commands to front end 1908. In at least one embodiment, front end 1908 is coupled to scheduler 1910, which is configured to distribute commands or other work items to processing array 1912. In at least one embodiment, scheduler 1910 ensures that processing array 1912 is properly configured and in a valid state before tasks are distributed to processing array 1912. In at least one embodiment, scheduler 1910 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1910 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, allowing rapid preemption and context switching of threads executing on the processing array 1912. In at least one embodiment, host software can present workloads for scheduling on the processing array 1912 via one of multiple graphics processing bells. In at least one embodiment, the workloads can then be automatically distributed across the processing array 1912 by scheduler 1910 logic within the microcontroller that includes the scheduler 1910.

[0120] In at least one embodiment, processing array 1912 may include up to “N” clusters (e.g., cluster 1914A, cluster 1914B through cluster 1914N). In at least one embodiment, each cluster 1914A-1914N of processing array 1912 may execute multiple concurrent threads. In at least one embodiment, scheduler 1910 may allocate work to clusters 1914A-1914N of processing array 1912 using various scheduling and / or work distribution algorithms, which may vary depending on the workload occurring for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 1910 or may be partially assisted by compiler logic during compilation of program logic configured for execution by processing array 1912. In at least one embodiment, different clusters 1914A-1914N of processing array 1912 may be allocated to process different types of programs or perform different types of computations.

[0121] In at least one embodiment, processing array 1912 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 1912 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing array 1912 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0122] In at least one embodiment, processing array 1912 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 1912 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing array 1912 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 1902 may transfer data from system memory via I / O unit 1904 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1922) during processing and then written back to system memory.

[0123] In at least one embodiment, when parallel processing unit 1902 is used to perform graphics processing, scheduler 1910 may be configured to divide the processing workload into tasks of approximately equal size to better enable distribution of graphics processing operations to multiple clusters 1914A-1914N of processing array 1912. In at least one embodiment, portions of processing array 1912 may be configured to perform different types of processing. For example, in at least one embodiment, to produce a rendered image for display, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data produced by one or more of clusters 1914A-1914N may be stored in a buffer to allow the intermediate data to be transmitted between clusters 1914A-1914N for further processing.

[0124] In at least one embodiment, processing array 1912 may receive processing tasks to be performed via scheduler 1910, which receives commands defining the processing tasks from front end 1908. In at least one embodiment, a processing task may include an index of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how the data should be processed (e.g., which program should be executed). In at least one embodiment, scheduler 1910 may be configured to fetch the index corresponding to the task or may receive the index from front end 1908. In at least one embodiment, front end 1908 may be configured to ensure that processing array 1912 is configured to a valid state before a workload specified by an incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated.

[0125] In at least one embodiment, each of one or more instances of parallel processing unit 1902 may be coupled to parallel processor memory 1922. In at least one embodiment, parallel processor memory 1922 may be accessed via memory crossbar 1916, which may receive memory requests from processing array 1912 as well as I / O unit 1904. In at least one embodiment, memory crossbar 1916 may access parallel processor memory 1922 via memory interface 1918. In at least one embodiment, memory interface 1918 may include multiple partition units (e.g., partition unit 1920A, partition unit 1920B through partition unit 1920N), each of which may be coupled to a portion (e.g., a memory unit) of parallel processor memory 1922. In at least one embodiment, the number of partition units 1920A-1920N is configured to be equal to the number of memory units, such that a first partition unit 1920A has a corresponding first memory unit 1924A, a second partition unit 1920B has a corresponding memory unit 1924B, and an Nth partition unit 1920N has a corresponding Nth memory unit 1924N. In at least one embodiment, the number of partition units 1920A-1920N may not be equal to the number of memory devices.

[0126] In at least one embodiment, the memory units 1924A-1924N may include various types of memory devices, including DRAM or graphics random access memory, such as SGRAM, including GDDR memory. In at least one embodiment, the memory units 1924A-1924N may also include 3D stacked memory, including but not limited to high bandwidth memory (“HBM”). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 1922, render targets, such as frame buffers or texture maps, may be stored across the memory units 1924A-1924N, allowing the partition units 1920A-1920N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 1922 may be eliminated in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

[0127] In at least one embodiment, any one of the clusters 1914A-1914N of the processing array 1912 can process data that is to be written to any one of the memory units 1924A-1924N in the parallel processor memory 1922. In at least one embodiment, the memory crossbar 1916 can be configured to forward the output of each cluster 1914A-1914N to any partition unit 1920A-1920N that can perform additional processing operations on the output, or to another cluster 1914A-1914N. In at least one embodiment, each cluster 1914A-1914N can communicate with a memory interface 1918 through the memory crossbar 1916 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 1916 has a connection to a memory interface 1918 for communicating with I / O units 1904, as well as a connection to a local instance of parallel processor memory 1922, which allows processing units in different clusters 1914A-1914N to communicate with system memory or other memory not local to the parallel processing units 1902. In at least one embodiment, memory crossbar 1916 can use virtual channels to separate traffic streams between clusters 1914A-1914N and partition units 1920A-1920N.

[0128] In at least one embodiment, multiple instances of parallel processing unit 1902 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 1902 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1902 may include higher precision floating-point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 1902 or parallel processor 1900 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0129] FIG. 19B illustrates a processing cluster 1994, according to at least one embodiment. In at least one embodiment, the processing cluster 1994 is included within a parallel processing unit. In at least one embodiment, the processing cluster 1994 is one of the processing clusters 1914A-1914N of FIG. 19. In at least one embodiment, the processing cluster 1994 may be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, a single instruction, multiple data ("SIMD") instruction issue technique is used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, a single instruction, multiple thread ("SIMT") technique is used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines in each processing cluster 1994. In at least one embodiment, processing cluster 1994 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with Figures 1-7. In at least one embodiment, processing cluster 1994 includes hardware for executing one or more instructions that, when executed, cause processing cluster 1994 to perform the various operations described above in conjunction with Figures 1-7.

[0130] In at least one embodiment, operation of the processing cluster 1994 may be controlled via a pipeline manager 1932 that distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1932 receives instructions from the scheduler 1910 of FIG. 19 and manages the execution of those instructions via the graphics multiprocessor 1934 and / or the texture unit 1936. In at least one embodiment, the graphics multiprocessor 1934 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within the processing cluster 1994. In at least one embodiment, one or more instances of the graphics multiprocessor 1934 may be included within the processing cluster 1994. In at least one embodiment, the graphics multiprocessor 1934 may process data, and a data crossbar 1940 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 1932 can facilitate the distribution of the processed data by specifying a destination for the processed data to be distributed through the data crossbar 1940.

[0131] In at least one embodiment, each graphics multiprocessor 1934 in a processing cluster 1994 may include an identical set of function execution logic (e.g., arithmetic logic units, load / store units (“LSUs”), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner such that new instructions may be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and computation of various algebraic functions. In at least one embodiment, the same function unit hardware may be utilized to perform different operations, and any combination of function units may be present.

[0132] In at least one embodiment, instructions sent to a processing cluster 1994 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread in a thread group may be assigned to a different processing engine in the graphics multiprocessor 1934. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in the graphics multiprocessor 1934. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during a cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in the graphics multiprocessor 1934. In at least one embodiment, when a thread group includes more threads than the number of processing engines in the graphics multiprocessor 1934, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on the graphics multiprocessor 1934.

[0133] In at least one embodiment, the graphics multiprocessor 1934 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1934 can forgo internal cache and use cache memory (e.g., L1 cache 1948) within the processing cluster 1994. In at least one embodiment, each graphics multiprocessor 1934 also has access to a level 2 (“L2”) cache within a partition unit (e.g., partition units 1920A-1920N in FIG. 19A ), which is shared among all processing clusters 1994 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1934 can also access off-chip global memory, which can include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing unit 1902 can be used as global memory. In at least one embodiment, the processing cluster 1994 includes multiple instances of the graphics multiprocessor 1934, and the graphics multiprocessors 1934 can share common instructions and data, which can be stored in the L1 cache 1948.

[0134] In at least one embodiment, each processing cluster 1994 may include an MMU 1945 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1945 may reside in memory interface 1918 of FIG. 19 . In at least one embodiment, MMU 1945 includes a set of page table entries (“PTEs”) used to map virtual addresses to physical addresses of tiles and optionally cache line indices. In at least one embodiment, MMU 1945 may include an address translation lookaside buffer (“TLB”) or cache, which may reside in graphics multiprocessor 1934, L1 cache 1948, or processing cluster 1994. In at least one embodiment, physical addresses are processed to distribute surface data access locality and enable efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0135] In at least one embodiment, processing cluster 1994 may be configured such that each graphics multiprocessor 1934 is coupled to a texture unit 1936 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 1934 and fetched as needed from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1934 outputs processed tasks to data crossbar 1940 to provide the processed tasks to another processing cluster 1994 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 1916. In at least one embodiment, a pre-raster operation unit (“pre-ROP”) 1942 is configured to receive data from the graphics multiprocessor 1934 and direct the data to a ROP unit, which may be co-located with a partition unit as described herein (e.g., partition units 1920A-1920N of FIG. 19 ). In at least one embodiment, pre-ROP 1942 may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0136] FIG. 19C illustrates a graphics multiprocessor 1996 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 1996 is the graphics multiprocessor 1934 of FIG. 19B. In at least one embodiment, the graphics multiprocessor 1996 couples to the pipeline manager 1932 of the processing cluster 1994. In at least one embodiment, the graphics multiprocessor 1996 has an execution pipeline including, but not limited to, an instruction cache 1952, an instruction unit 1954, an address mapping unit 1956, a register file 1958, one or more GPGPU cores 1962, and one or more LSUs 1966. The GPGPU cores 1962 and LSUs 1966 are coupled to a cache memory 1972 and a shared memory 1970 via a memory and cache interconnect 1968. In at least one embodiment, graphics multiprocessor 1996 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with Figures 1-7. In at least one embodiment, graphics multiprocessor 1996 includes hardware for executing one or more instructions that, when executed, cause graphics multiprocessor 1996 to perform the various operations described above in conjunction with Figures 1-7.

[0137] In at least one embodiment, instruction cache 1952 receives a stream of instructions to execute from pipeline manager 1932. In at least one embodiment, instructions are cached in instruction cache 1952 and dispatched for execution by instruction unit 1954. In at least one embodiment, instruction unit 1954 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group assigned to a different execution unit within GPGPU core 1962. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying an address in the unified address space. In at least one embodiment, address mapping unit 1956 can be used to translate addresses in the unified address space into individual memory addresses that can be accessed by LSU 1966.

[0138] In at least one embodiment, register file 1958 provides a set of registers to the functional units of graphics multiprocessor 1996. In at least one embodiment, register file 1958 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU core 1962, LSU 1966) of graphics multiprocessor 1996. In at least one embodiment, register file 1958 is divided among each of the functional units such that each functional unit is allocated a dedicated portion of register file 1958. In at least one embodiment, register file 1958 is divided among different thread groups being executed by graphics multiprocessor 1996.

[0139] In at least one embodiment, the GPGPU cores 1962 may each include an FPU and / or integer ALU used to execute instructions for the graphics multiprocessor 1996. The GPGPU cores 1962 may be of similar or different architectures. In at least one embodiment, a first portion of the GPGPU core 1962 includes a single-precision FPU and integer ALU, and a second portion of the GPGPU core 1962 includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or may enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1996 may additionally include one or more fixed-function or special-function units for performing specific functions, such as rectangle copy operations or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1962 may also include fixed or special-function logic.

[0140] In at least one embodiment, GPGPU core 1962 includes SIMD logic capable of performing a single instruction on multiple data sets. In at least one embodiment, GPGPU core 1962 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU core 1962 may be generated at compile time by a shader compiler or automatically generated when executing a program written and compiled for a single program multiple data (“SPMD”) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logical unit.

[0141] In at least one embodiment, memory and cache interconnect 1968 is an interconnect network connecting each functional unit of graphics multiprocessor 1996 to register file 1958 and shared memory 1970. In at least one embodiment, memory and cache interconnect 1968 is a crossbar interconnect that allows LSU 1966 to implement load and store operations between shared memory 1970 and register file 1958. In at least one embodiment, register file 1958 can operate at the same frequency as GPGPU cores 1962, and therefore data transfers between GPGPU cores 1962 and register file 1958 are very low latency. In at least one embodiment, shared memory 1970 can be used to enable communication between threads executing on functional units within graphics multiprocessor 1996. In at least one embodiment, cache memory 1972 can be used as a data cache, for example, to cache texture data communicated between functional units and texture unit 1936. In at least one embodiment, shared memory 1970 can also be used as a managed program cache. In at least one embodiment, threads executing on GPGPU cores 1962 can programmatically store data in the shared memory in addition to the automatically cached data stored in cache memory 1972.

[0142] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated in the same package or chip as the cores and communicatively coupled to the cores via a processor bus / interconnect internal to the package or chip. In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in a WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0143] FIG. 20 illustrates a graphics processor 2000 according to at least one embodiment. In at least one embodiment, the graphics processor 2000 includes a ring interconnect 2002, a pipeline front end 2004, a media engine 2037, and graphics cores 2080A-2080N. In at least one embodiment, the ring interconnect 2002 couples the graphics processor 2000 to other graphics processors or other processing units, including one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2000 is one of many processors incorporated within a multi-core processing system. In at least one embodiment, the graphics processor 2000 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, graphics processor 2000 includes hardware for executing one or more instructions that, when executed, cause graphics processor 2000 to perform the various operations described above in conjunction with FIGS. 1-7.

[0144] In at least one embodiment, graphics processor 2000 receives batches of commands via ring interconnect 2002. In at least one embodiment, the incoming commands are interpreted by command streamer 2003 in pipeline front end 2004. In at least one embodiment, graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via graphics core(s) 2080A-2080N. In at least one embodiment, for 3D geometry processing commands, command streamer 2003 supplies the commands to geometry pipeline 2036. In at least one embodiment, for at least some media processing commands, command streamer 2003 supplies the commands to video front end 2034, which couples to media engine 2037. In at least one embodiment, the media engine 2037 includes a video quality engine ("VQE") 2030 for video and image post-processing and a multi-format encode / decode ("MFX") engine 2033 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2036 and the media engine 2037 each spawn execution threads for thread execution resources provided by at least one graphics core 2080A.

[0145] In at least one embodiment, graphics processor 2000 includes scalable thread execution resources characterized by modular graphics cores 2080A-2080N (sometimes referred to as core slices), each having multiple sub-cores 2050A-2050N, 2060A-2060N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2000 can have any number of graphics cores 2080A-2080N. In at least one embodiment, graphics processor 2000 includes graphics core 2080A having at least a first sub-core 2050A and a second sub-core 2060A. In at least one embodiment, graphics processor 2000 is a low-power processor with a single sub-core (e.g., sub-core 2050A). In at least one embodiment, graphics processor 2000 includes multiple graphics cores 2080A-2080N, each including a first set of sub-cores 2050A-2050N and a second set of sub-cores 2060A-2060N. In at least one embodiment, each sub-core in first sub-cores 2050A-2050N includes at least a first set of execution units ("EUs") 2052A-2052N and media / texture samplers 2054A-2054N. In at least one embodiment, each sub-core in second sub-cores 2060A-2060N includes at least a second set of execution units 2062A-2062N and samplers 2064A-2064N. In at least one embodiment, each sub-core 2050A-2050N, 2060A-2060N shares a set of shared resources 2070A-2070N. In at least one embodiment, the shared resources 2070 include shared cache memory and pixel operating logic.

[0146] FIG. 21 illustrates a processor 2100 according to at least one embodiment. In at least one embodiment, the processor 2100 may include logic circuitry for implementing instructions, including, but not limited to, x86 instructions, ARM instructions, special instructions for ASICs, etc. In at least one embodiment, the processor 2100 may include registers for storing packed data, such as 64-bit wide MMX registers in a microprocessor enabled with MMX™ technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point formats, may operate on packed data elements with SIMD and streaming SIMD extension (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processor 2110 may execute instructions to accelerate CUDA programs. In at least one embodiment, processor 2100 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with Figures 1-7. In at least one embodiment, processor 2100 includes hardware for executing one or more instructions that, when executed, cause processor 2100 to perform the various operations described above in conjunction with Figures 1-7.

[0147] In at least one embodiment, processor 2100 includes an in-order front end (“front end”) 2101 for fetching instructions to be executed and preparing instructions to be used later in the processor pipeline. In at least one embodiment, front end 2101 may include several units. In at least one embodiment, an instruction prefetcher 2126 fetches instructions from memory and feeds the instructions to an instruction decoder 2128, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2128 decodes received instructions into one or more operations called “microinstructions” or “micro-operations” (also called “micro-ops” or “uops”) for execution. In at least one embodiment, instruction decoder 2128 parses instructions into opcodes and corresponding data and control fields that can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 2130 may assemble decoded uops into program-order sequences, or traces, for execution in uop queue 2134. In at least one embodiment, when trace cache 2130 encounters a complex instruction, microcode ROM 2132 provides the uops necessary to complete the operation.

[0148] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2128 may access the microcode ROM 2132 to implement the instruction. In at least one embodiment, an instruction may be decoded into a fewer number of micro-ops for processing in the instruction decoder 2128. In at least one embodiment, an instruction may be stored in the microcode ROM 2132 if several micro-ops are required to accomplish the operation. In at least one embodiment, the trace cache 2130 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 2132. In at least one embodiment, after the microcode ROM 2132 finishes sequencing micro-ops for an instruction, the machine front end 2101 may resume fetching micro-ops from the trace cache 2130.

[0149] In at least one embodiment, an out-of-order execution engine (“out-of-order engine”) 2103 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has several buffers to smooth the flow of instructions and reorder them to optimize performance as they move down the pipeline and are scheduled for execution. The out-of-order execution engine 2103 includes, but is not limited to, an allocator / register renamer 2140, a memory uop queue 2142, an integer / floating point uop queue 2144, a memory scheduler 2146, a fast scheduler 2102, a slow / general purpose floating point scheduler (“slow / general purpose FP scheduler”) 2104, and a simple floating point scheduler (“simple FP scheduler”) 2106. In at least one embodiment, the fast scheduler 2102, the slow / general purpose floating point scheduler 2104, and the simple floating point scheduler 2106 are also collectively referred to herein as "uop schedulers 2102, 2104, 2106." The allocator / register renamer 2140 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, the allocator / register renamer 2140 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 2140 also allocates an entry for each uop in one of two uop queues: memory uop queue 2142 for memory operations and integer / floating point uop queue 2144 for non-memory operations, before memory scheduler 2146 and uop schedulers 2102, 2104, 2106. In at least one embodiment, uop schedulers 2102, 2104, 2106 determine when uops are ready to execute based on the readiness of their dependent input register operand sources and the availability of execution resources required by the uops to complete their operations.In at least one embodiment, the fast scheduler 2102 of at least one embodiment may schedule every half of a main clock cycle, and the slow / general purpose floating point scheduler 2104 and simple floating point scheduler 2106 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2102, 2104, 2106 arbitrate for dispatch ports to schedule uops for execution.

[0150] In at least one embodiment, execution block 2111 includes, but is not limited to, integer register file / bypass network 2108, floating point register file / bypass network (“FP register file / bypass network”) 2110, address generation units (“AGUs”) 2112 and 2114, fast ALUs 2116 and 2118, slow ALU 2120, floating point ALU (“FP”) 2122, and floating point move unit (“FP move”) 2124. In at least one embodiment, integer register file / bypass network 2108 and floating point register file / bypass network 2110 are also referred to herein as “register files 2108, 2110.” In at least one embodiment, AGUs 2112 and 2114, fast ALUs 2116 and 2118, slow ALU 2120, floating-point ALU 2122, and floating-point move unit 2124 are also referred to herein as "execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124." In at least one embodiment, an execution block may include any number and type of register files (including, but not limited to, zero), bypass networks, address generation units, and execution units, in any combination.

[0151] In at least one embodiment, the register files 2108, 2110 may be located between the uop schedulers 2102, 2104, 2106 and the execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124. In at least one embodiment, the integer register file / bypass network 2108 performs integer operations. In at least one embodiment, the floating point register file / bypass network 2110 performs floating point operations. In at least one embodiment, each of the register files 2108, 2110 may include, but is not limited to, a bypass network that may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, the register files 2108, 2110 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2108 may include, but is not limited to, two separate register files: one register file for lower 32-bit data and a second register file for higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64 to 128 bits wide, so floating-point register file / bypass network 2110 may include, but is not limited to, 128-bit wide entries.

[0152] In at least one embodiment, execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124 may execute instructions. In at least one embodiment, register files 2108 and 2110 store integer and floating-point data operand values ​​that microinstructions need to execute. In at least one embodiment, processor 2100 may include, but is not limited to, any number and combination of execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124. In at least one embodiment, floating-point ALU 2122 and floating-point move unit 2124 may perform floating-point, MMX, SIMD, AVX, and SSE, or other operations. In at least one embodiment, the floating-point ALU 2122 may include a 64-bit floating-point divider for performing, but not limited to, division, square root, and remainder micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the high-speed ALUs 2116, 2118. In at least one embodiment, the high-speed ALUs 2116, 2118 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the low-speed ALU 2120 may include integer execution hardware for long-latency type operations such as, but not limited to, multipliers, shifts, flag logic, and branching, so that most complex integer operations proceed to the low-speed ALU 2120. In at least one embodiment, memory load / store operations may be performed by the AGUs 2112, 2114. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, floating-point ALU 2122 and floating-point move unit 2124 may be implemented to support various operands having various bit widths.In at least one embodiment, the floating-point ALU 2122 and floating-point move unit 2124 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0153] In at least one embodiment, the uop schedulers 2102, 2104, 2106 dispatch dependent operations before the parent load finishes executing. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 2100, the processor 2100 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline that have passed the scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0154] In at least one embodiment, the term “register” may refer to an on-board processor storage location that may be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuit elements within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0155] FIG. 22 illustrates a processor 2200 according to at least one embodiment. In at least one embodiment, the processor 2200 includes, without limitation, one or more processor cores (“cores”) 2202A-2202N, an integrated memory controller 2214, and an integrated graphics processor 2208. In at least one embodiment, the processor 2200 may include additional cores, up to an additional processor core 2202N, represented by a dashed box. In at least one embodiment, the processor cores 2202A-2202N each include one or more internal cache units 2204A-2204N. In at least one embodiment, each processor core also has access to one or more shared cache units 2206. In at least one embodiment, the processor 2200 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, processor 2200 includes hardware for executing one or more instructions that, when executed, cause processor 2200 to perform the various operations described above in conjunction with FIGS. 1-7.

[0156] In at least one embodiment, the internal cache units 2204A-2204N and the shared cache unit 2206 represent a cache memory hierarchy within the processor 2200. In at least one embodiment, the cache memory units 2204A-2204N may include at least one level of instruction and data cache within each processor core, and one or more levels of shared mid-level cache, such as L2, L3, level 4 (“L4”), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In at least one embodiment, cache coherency logic maintains coherency between the various cache units 2206 and 2204A-2204N.

[0157] In at least one embodiment, processor 2200 may also include a set of one or more bus controller units 2216 and a system agent core 2210. In at least one embodiment, one or more bus controller units 2216 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, system agent core 2210 provides management functionality for various processor components. In at least one embodiment, system agent core 2210 includes one or more integrated memory controllers 2214 for managing access to various external memory devices (not shown).

[0158] In at least one embodiment, one or more of processor cores 2202A-2202N include support for simultaneous multithreading. In at least one embodiment, system agent core 2210 includes components for coordinating and operating processor cores 2202A-2202N during multithreaded processing. In at least one embodiment, system agent core 2210 may additionally include a power control unit (“PCU”), which includes logic and components for adjusting the power state of one or more of processor cores 2202A-2202N and graphics processor 2208.

[0159] In at least one embodiment, processor 2200 additionally includes a graphics processor 2208 for performing graphics processing operations. In at least one embodiment, graphics processor 2208 couples to a system agent core 2210 that includes a shared cache unit 2206 and one or more integrated memory controllers 2214. In at least one embodiment, system agent core 2210 also includes a display controller 2211 for driving graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2211 may also be a separate module coupled to graphics processor 2208 via at least one interconnect or may be incorporated within graphics processor 2208.

[0160] In at least one embodiment, a ring-based interconnect unit 2212 is used to couple the internal components of processor 2200. In at least one embodiment, alternative interconnect units such as a point-to-point interconnect, a switched interconnect, or other techniques may be used. In at least one embodiment, graphics processor 2208 couples to ring interconnect 2212 via I / O link 2213.

[0161] In at least one embodiment, I / O link 2213 represents at least one of several types of I / O interconnect, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2218, such as an eDRAM module. In at least one embodiment, each of processor cores 2202A-2202N and graphics processor 2208 use embedded memory module 2218 as a shared LLC.

[0162] In at least one embodiment, processor cores 2202A-2202N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, processor cores 2202A-2202N are heterogeneous in terms of ISA, where one or more of processor cores 2202A-2202N execute a common instruction set and one or more other of processor cores 2202A-2202N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 2202A-2202N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are combined with one or more cores with lower power consumption. In at least one embodiment, processor 2200 may be implemented on one or more chips or as an SoC integrated circuit.

[0163] FIG. 23 illustrates a graphics processor core 2300 according to at least one described embodiment. In at least one embodiment, the graphics processor core 2300 is included within a graphics core array. In at least one embodiment, the graphics processor core 2300, sometimes referred to as a core slice, may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2300 is an example of a graphics core slice, and the graphics processors described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2300 may include a fixed function block 2330 coupled with multiple sub-cores 2301A-2301F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed-function logic. In at least one embodiment, the graphics processor core 2300 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, graphics processor core 2300 includes hardware for executing one or more instructions that, when executed, cause graphics processor core 2300 to perform the various operations described above in conjunction with FIGS. 1-7.

[0164] In at least one embodiment, fixed function block 2330 includes a geometry / fixed function pipeline 2336 that may be shared by all sub-cores in graphics processor 2300, e.g., in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 2336 includes a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0165] In at least one embodiment, fixed function block 2330 also includes a graphics SoC interface 2337, a graphics microcontroller 2338, and a media pipeline 2339. Graphics SoC interface 2337 provides an interface between graphics core 2300 and other processor cores within the SoC integrated circuit. In at least one embodiment, graphics microcontroller 2338 is a programmable sub-processor that is configurable to manage various functions of graphics processor 2300, including thread dispatch, scheduling, and preemption. In at least one embodiment, media pipeline 2339 includes logic for facilitating decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2339 implements media operations via requests to compute logic or sampling logic within sub-cores 2301-2301F.

[0166] In at least one embodiment, SoC interface 2337 enables graphics core 2300 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or on-package DRAM. In at least one embodiment, SoC interface 2337 can also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enable and / or implement global memory atomics that may be shared between graphics core 2300 and a CPU within the SoC. In at least one embodiment, SoC interface 2337 can also implement power management controls for graphics core 2300 and enable an interface between the graphics core 2300 clock domain and other clock domains within the SoC. In at least one embodiment, SoC interface 2337 enables receipt of command buffers from a command streamer and global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores in the graphics processor. In at least one embodiment, the commands and instructions may be dispatched to a media pipeline 2339 when a media operation is to be performed, or to a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 2336, geometry and fixed function pipeline 2314) when a graphics processing operation is to be performed.

[0167] In at least one embodiment, graphics microcontroller 2338 can be configured to perform various scheduling and management tasks for graphics core 2300. In at least one embodiment, graphics microcontroller 2338 can perform graphics and / or compute workload scheduling for various graphics parallel engines in execution unit (EU) arrays 2302A-2302F, 2304A-2304F within sub-cores 2301A-2301F. In at least one embodiment, host software running on a CPU core of an SoC including graphics core 2300 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to a command streamer, preempting existing workloads running on the engines, monitoring the progress of the workload, and notifying host software when the workload is complete. In at least one embodiment, graphics microcontroller 2338 can also facilitate low power or idle states for graphics core 2300, providing graphics core 2300 with the ability to save and restore registers within graphics core 2300 across low power state transitions independent of the operating system and / or graphics driver software on the system.

[0168] In at least one embodiment, graphics core 2300 may have up to N modular sub-cores, more or fewer than the illustrated sub-cores 2301A-2301F. For each set of N sub-cores, in at least one embodiment, graphics core 2300 may also include shared function logic 2310, shared and / or cache memory 2312, geometry / fixed function pipeline 2314, and additional fixed function logic 2316 for accelerating various graphics and compute processing operations. In at least one embodiment, shared function logic 2310 may include logic units (e.g., sampler, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores in graphics core 2300. Shared and / or cache memory 2312 may be an LLC for the N sub-cores 2301A-2301F in graphics core 2300 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2314 may be included in place of geometry / fixed function pipeline 2336 in fixed function block 2330 and may include the same or similar logical units.

[0169] In at least one embodiment, graphics core 2300 includes additional fixed function logic 2316, which can include various fixed-function acceleration logic for use by graphics core 2300. In at least one embodiment, additional fixed function logic 2316 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines: a full geometry pipeline in geometry / fixed function pipeline 2316, 2336, and a cull pipeline, where the cull pipeline is an additional geometry pipeline that can be included in additional fixed function logic 2316. In at least one embodiment, the cull pipeline is a scaled-down version of the full geometry pipeline. In at least one embodiment, the full pipeline and the cull pipeline can run different instances of an application, each instance having a separate context. In at least one embodiment, position-only shading can hide long cull runs of truncated triangles, which allows shading to complete faster in some instances. For example, in at least one embodiment, the cull pipeline fetches and shades vertex position attributes without rasterizing and rendering pixels to the frame buffer, allowing the cull pipeline logic in the additional fixed-function logic 2316 to execute position shaders in parallel with the main application and produce critical results faster than the full pipeline. In at least one embodiment, the cull pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether they are culled. In at least one embodiment, the full pipeline (which may be referred to in this instance as the replay pipeline) can consume the visibility information and shade only visible triangles, skipping over culled triangles, which are ultimately passed to the rasterization phase.

[0170] In at least one embodiment, the additional fixed function logic 2316 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, to accelerate CUDA programs.

[0171] In at least one embodiment, each graphics sub-core 2301A-2301F includes a set of execution resources that can be used to perform graphics operations, media operations, and compute operations in response to requests by a graphics pipeline, a media pipeline, or a shader program. In at least one embodiment, the graphics sub-cores 2301A-2301F include a plurality of EU arrays 2302A-2302F, 2304A-2304F, thread dispatch and inter-thread communication (“TD / IC”) logic 2303A-2303F, 3D (e.g., texture) samplers 2305A-2305F, media samplers 2306A-2306F, shader processors 2307A-2307F, and shared local memory (“SLM”) 2308A-2308F. The EU arrays 2302A-2302F, 2304A-2304F each include multiple execution units, which are GPGPUs capable of performing floating-point and integer / fixed-point logic operations in service of graphics, media, or compute operations, including graphics, media, or compute shader programs. In at least one embodiment, the TD / IC logic 2303A-2303F performs local thread dispatch and thread control operations for the execution units within a sub-core and facilitates communication between threads executing on the execution units of a sub-core. In at least one embodiment, the 3D samplers 2305A-2305F can read textures or other 3D graphics-related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sample state and texture format associated with a given texture. In at least one embodiment, media samplers 2306A-2306F can perform similar read operations based on the type and format associated with the media data.In at least one embodiment, each graphics sub-core 2301A-2301F can alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each of the sub-cores 2301A-2301F can utilize shared local memory 2308A-2308F within each sub-core to allow threads executing within a thread group to execute using a common pool of on-chip memory.

[0172] FIG. 24 illustrates a parallel processing unit (“PPU”) 2400 according to at least one embodiment. In at least one embodiment, the PPU 2400 comprises machine-readable code that, when executed by the PPU 2400, causes the PPU 2400 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2400 is a multi-threaded processor, which is implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) in parallel on multiple threads. In at least one embodiment, a thread refers to a thread of execution, which is an instantiation of a set of instructions configured to be executed by the PPU 2400. In at least one embodiment, the PPU 2400 is a GPU configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as an LCD device. In at least one embodiment, the PPU 2400 is utilized to perform computations such as linear algebra operations and machine learning operations. FIG. 24 depicts an exemplary parallel processor for illustrative purposes only and should be construed as a non-limiting example of a processor architecture that may be implemented in at least one embodiment. In at least one embodiment, the PPU 2400 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, the PPU 2400 includes hardware for executing one or more instructions that, when executed, cause the PPU 2400 to perform the various operations described above in conjunction with FIGS. 1-7.

[0173] In at least one embodiment, one or more PPUs 2400 are configured to accelerate high performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2400 are configured to accelerate CUDA programs. In at least one embodiment, the PPUs 2400 include, but are not limited to, an I / O unit 2406, a front end unit 2410, a scheduler unit 2412, a work distribution unit 2414, a hub 2416, a crossbar ("Xbar") 2420, one or more general processing clusters ("GPC") 2418, and one or more partition units ("memory partition units") 2422. In at least one embodiment, the PPU 2400 is connected to a host processor or other PPUs 2400 via one or more high-speed GPU interconnects (“GPU interconnects”) 2408. In at least one embodiment, the PPU 2400 is connected to a host processor or other peripheral devices via a system bus or interconnect 2402. In at least one embodiment, the PPU 2400 is connected to local memory comprising one or more memory devices (“memory”) 2404. In at least one embodiment, the memory devices 2404 include, but are not limited to, one or more dynamic random access memory (DRAM) devices. In at least one embodiment, the one or more DRAM devices are configured and / or configurable as a high-bandwidth memory (“HBM”) subsystem with multiple DRAM dies stacked within each device.

[0174] In at least one embodiment, the high-speed GPU interconnect 2408 may refer to a wire-based, multi-lane communication link used by the system to scale and include one or more PPUs 2400 in combination with one or more CPUs, supporting cache coherence between the PPUs 2400 and the CPUs and CPU mastering. In at least one embodiment, data and / or commands are transmitted by the high-speed GPU interconnect 2408 through a hub 2416 to and from other units of the PPU 2400, such as one or more copy engines, a video encoder, a video decoder, a power management unit, and other components that may not be explicitly shown in FIG. 24 .

[0175] In at least one embodiment, I / O unit 2406 is configured to receive and send communications (e.g., commands, data) from a host processor (not shown in FIG. 24 ) via system bus 2402. In at least one embodiment, I / O unit 2406 communicates with the host processor directly via system bus 2402 or through one or more intermediary devices, such as a memory bridge. In at least one embodiment, I / O unit 2406 may communicate with one or more other processors, such as one or more of PPUs 2400, via system bus 2402. In at least one embodiment, I / O unit 2406 implements a PCIe interface for communication over the PCIe bus. In at least one embodiment, I / O unit 2406 implements an interface for communicating with external devices.

[0176] In at least one embodiment, I / O unit 2406 decodes packets received via system bus 2402. In at least one embodiment, at least some of the packets represent commands configured to cause PPU 2400 to perform various operations. In at least one embodiment, I / O unit 2406 transmits the decoded commands to various other units of PPU 2400 specified by the commands. In at least one embodiment, the commands are transmitted to front end unit 2410 and / or to hub 2416 or other units of PPU 2400, such as one or more copy engines, video encoders, video decoders, or power management units (not explicitly shown in FIG. 24 ). In at least one embodiment, I / O unit 2406 is configured to route communications to and between various logical units of PPU 2400.

[0177] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 2400 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., writeable / readable) by both the host processor and the PPU 2400, and the host interface unit may be configured to access the buffer in system memory connected to the system bus 2402 via memory requests sent by the I / O unit 2406 over the system bus 2402. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer to the start of the command stream to the PPU 2400, whereupon the front end unit 2410 receives the pointer to one or more command streams and manages the one or more command streams, reading commands from the command streams and forwarding the commands to various units of the PPU 2400.

[0178] In at least one embodiment, front end unit 2410 is coupled to a scheduler unit 2412 that configures various GPCs 2418 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 2412 is configured to track state information related to the various tasks managed by scheduler unit 2412, where the state information may indicate which of GPCs 2418 a task is assigned to, whether the task is active or inactive, the priority level associated with the task, etc. In at least one embodiment, scheduler unit 2412 manages the execution of multiple tasks on one or more of GPCs 2418.

[0179] In at least one embodiment, scheduler unit 2412 is coupled to a work distribution unit 2414 configured to dispatch tasks for execution on GPCs 2418. In at least one embodiment, work distribution unit 2414 tracks the number of scheduled tasks received from scheduler unit 2412, and work distribution unit 2414 manages a pending task pool and an active task pool for each of GPCs 2418. In at least one embodiment, the pending task pool may comprise a number of slots (e.g., 32 slots) containing tasks assigned to be processed by a particular GPC 2418, and the active task pool may comprise a number of slots (e.g., 4 slots) for tasks being actively processed by the GPC 2418, such that when one of the GPCs 2418 completes execution of a task, the task is removed from the active task pool for the GPC 2418 and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC 2418. In at least one embodiment, when an active task is idle on GPC2418, such as while waiting for a data dependency to be resolved, the active task is evicted from GPC2418 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on GPC2418.

[0180] In at least one embodiment, work distribution unit 2414 communicates with one or more GPCs 2418 via X-bar 2420. In at least one embodiment, X-bar 2420 is an interconnection network coupling many units of PPU 2400 to other units of PPU 2400 and may be configured to couple work distribution unit 2414 to a particular GPC 2418. In at least one embodiment, one or more other units of PPU 2400 may also be connected to X-bar 2420 via hub 2416.

[0181] In at least one embodiment, tasks are managed by scheduler unit 2412 and dispatched by work distribution unit 2414 to one of GPCs 2418. GPC 2418 is configured to process the task and produce a result. In at least one embodiment, the result may be consumed by other tasks within GPC 2418, routed to a different GPC 2418 via Xbar 2420, or stored in memory 2404. In at least one embodiment, the result may be written to memory 2404 via partition unit 2422, which implements a memory interface for reading and writing data to / from memory 2404. In at least one embodiment, the result may be sent to another PPU 2404 or a CPU via high-speed GPU interconnect 2408. In at least one embodiment, the PPU 2400 includes U partition units 2422 equal to, but not limited to, the number of distinct individual memory devices 2404 coupled to the PPU 2400 .

[0182] In at least one embodiment, the host processor executes a driver kernel, which implements an application programming interface ("API") that allows one or more applications running on the host processor to schedule operations for execution on the PPU 2400. In at least one embodiment, multiple compute applications are executed concurrently by the PPU 2400, which provides isolation, quality of service ("QoS"), and independent address spaces for the multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 2400, and the driver kernel outputs the tasks to one or more streams that are processed by the PPU 2400. In at least one embodiment, each task comprises one or more groups of participating threads, which may be referred to as a warp. In at least one embodiment, a warp comprises multiple participating threads (e.g., 32 threads) that may be executed in parallel. In at least one embodiment, cooperating threads can refer to multiple threads that contain instructions to perform a task and exchange data through a shared memory.

[0183] FIG. 25 illustrates a GPC 2500 according to at least one embodiment. In at least one embodiment, the GPC 2500 is the GPC 2418 of FIG. 24. In at least one embodiment, each GPC 2500 includes several hardware units for processing tasks, including, but not limited to, a pipeline manager 2502, a pre-raster operation unit (“PROP”) 2504, a raster engine 2508, a work distribution crossbar (“WDX”) 2516, an MMU 2518, one or more data processing clusters (“DPCs”) 2506, and any suitable combination of parts. In at least one embodiment, the GPC 2500 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, GPC2500 includes hardware for executing one or more instructions that, when executed, cause GPC2500 to perform the various operations described above in conjunction with Figures 1-7.

[0184] In at least one embodiment, operation of the GPC 2500 is controlled by a pipeline manager 2502. In at least one embodiment, the pipeline manager 2502 manages the configuration of one or more DPCs 2506 to process tasks allocated to the GPC 2500. In at least one embodiment, the pipeline manager 2502 configures at least one of the one or more DPCs 2506 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 2506 is configured to execute vertex shader programs on a programmable streaming multiprocessor (“SM”) 2514. In at least one embodiment, pipeline manager 2502 is configured to route packets received from the work distribution unit to the appropriate logical unit within GPC 2500; in at least one embodiment, some packets may be routed to a fixed function hardware unit in PROP 2504 and / or to raster engine 2508, while other packets may be routed to DPC 2506 for processing by primitive engine 2512 or SM 2514. In at least one embodiment, pipeline manager 2502 configures at least one of DPC 2506 to implement a computing pipeline. In at least one embodiment, pipeline manager 2502 configures at least one of DPC 2506 to execute at least a portion of a CUDA program.

[0185] In at least one embodiment, the PROP unit 2504 is configured to route data generated by the raster engine 2508 and the DPC 2506 to a raster operation ("ROP") unit in a partition unit, such as the memory partition unit 2422 described in more detail above in conjunction with FIG. 24. In at least one embodiment, the PROP unit 2504 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, the raster engine 2508 includes several fixed-function hardware units configured to perform various raster operations, including, but not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile coalescing engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices. The plane equations are sent to a coarse raster engine to generate coverage information for the primitives (e.g., x, y coverage masks for tiles). The output of the coarse raster engine is sent to a culling engine to cull fragments associated with primitives that fail a z-test and to a clipping engine to clip fragments that are outside the view frustum. In at least one embodiment, fragments that pass clipping and culling are passed to a fine raster engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. In at least one embodiment, the output of the raster engine 2508 includes fragments to be processed by any suitable entity, such as by a fragment shader implemented within the DPC 2506.

[0186] In at least one embodiment, each DPC 2506 included in GPC 2500 includes, but is not limited to, an M-Pipe Controller (“MPC”) 2510, a Primitive Engine 2512, one or more SMs 2514, and any suitable combination thereof. In at least one embodiment, MPC 2510 controls the operation of DPC 2506, routing packets received from pipeline manager 2502 to the appropriate units in DPC 2506. In at least one embodiment, packets related to vertices are routed to primitive engine 2512, which is configured to fetch vertex attributes associated with the vertices from memory; in contrast, packets related to shader programs may be sent to SM 2514.

[0187] In at least one embodiment, SM2514 includes a programmable streaming processor configured to process tasks represented by, but not limited to, several threads. In at least one embodiment, SM2514 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular group of threads and implements a SIMD architecture, where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same set of instructions. In at least one embodiment, all threads in a group of threads execute the same instructions. In at least one embodiment, SM2514 implements a SIMT architecture, where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but individual threads in a group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp to enable concurrent processing between warps and serial execution within a warp when threads within a warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread to allow equal concurrency among all threads, within and between warps. In at least one embodiment, execution state is maintained for each individual thread, so that threads executing the same instructions can converge and execute in parallel for better efficiency. At least one embodiment of SM2514 is described in further detail in conjunction with FIG. 26.

[0188] In at least one embodiment, MMU 2518 provides an interface between GPC 2500 and a memory partition unit (e.g., partition unit 2422 of FIG. 24), and MMU 2518 provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, MMU 2518 provides one or more translation lookaside buffers (TLBs) for performing translations from virtual addresses to physical addresses in memory.

[0189] Figure 26 illustrates a streaming multiprocessor ("SM") 2600, according to at least one embodiment. In at least one embodiment, the SM 2600 is the SM 2514 of Figure 25. In at least one embodiment, the SM 2600 includes, without limitation, an instruction cache 2602, one or more scheduler units 2604, a register file 2608, one or more processing cores ("cores") 2610, one or more special function units ("SFUs") 2612, one or more LSUs 2614, an interconnect network 2616, a shared memory / L1 cache 2618, and any suitable combination thereof. In at least one embodiment, the work distribution unit dispatches tasks for execution on the GPCs of the parallel processing unit (PPU), with each task being assigned to a particular data processing cluster (DPC) within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 2600. In at least one embodiment, the scheduler unit 2604 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to the SMs 2600. In at least one embodiment, the scheduler unit 2604 schedules the thread blocks for execution as warps of parallel threads, with each thread block being assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, scheduler unit 2604 manages multiple different thread blocks, allocates warps to the different thread blocks, and then dispatches instructions from multiple different interlocking groups to various functional units (e.g., processing cores 2610, SFUs 2612, and LSUs 2614) during each clock cycle. In at least one embodiment, SM 2600 includes hardware components for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7.In at least one embodiment, SM2600 includes hardware for executing one or more instructions that, when executed, cause SM2600 to perform the various operations described above in conjunction with FIGS. 1-7.

[0190] In at least one embodiment, a "coordination group" may refer to a programming model for organizing groups of communicating threads, where the programming model allows developers to express the granularity at which threads are communicating, enabling richer and more efficient expression of parallel decompositions. In at least one embodiment, a coordination invocation API supports synchronization between thread blocks for the execution of parallel algorithms. In at least one embodiment, traditional programming model APIs provide a single simple construct for synchronizing coordinated threads, i.e., a barrier across all threads in a thread block (e.g., the syncthreads() function). However, in at least one embodiment, a programmer may define groups of threads at a granularity finer than a thread block and synchronize within the defined group, enabling higher performance, design flexibility, and software reuse in the form of a collective group-wide functional interface. In at least one embodiment, coordination groups allow programmers to explicitly define groups of threads at sub-block and multi-block granularity and perform collective operations, such as synchronization, on threads in the coordination group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize within their local context without having to make assumptions about convergence. In at least one embodiment, the interlocking group primitive enables new patterns of interlocking parallelism, including, but not limited to, producer-consumer parallelism, opportunistic parallelism, and global synchronization across a grid of thread blocks.

[0191] In at least one embodiment, the dispatch unit 2606 is configured to send instructions to one or more of the functional units, and the scheduler unit 2604 includes, without limitation, two dispatch units 2606, allowing two different instructions from the same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit 2604 includes a single dispatch unit 2606 or additional dispatch units 2606.

[0192] In at least one embodiment, each SM2600 includes, in at least one embodiment, a register file 2608 that provides a set of registers to the functional units of the SM2600. In at least one embodiment, the register file 2608 is divided among each of the functional units such that each functional unit is allocated a dedicated portion of the register file 2608. In at least one embodiment, the register file 2608 is divided among the different warps being executed by the SM2600, and the register file 2608 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM2600 includes, in at least one embodiment, a plurality of, inclusive of L, processing cores 2610. In at least one embodiment, the SM2600 includes, inclusive of L, a number of individual processing cores 2610 (e.g., 128 or more). In at least one embodiment, each processing core 2610 includes, but is not limited to, fully pipelined, single-precision, double-precision, and / or mixed-precision processing units, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, processing core 2610 includes, but is not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

[0193] In at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 2610. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0194] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating-point matrices, and sum matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor cores operate on 16-bit floating-point input data with a 32-bit floating-point sum. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations, resulting in a full-precision product, which is then added using 32-bit floating-point addition with other intermediate products for a 4x4x4 matrix multiplication. In at least one embodiment, the tensor cores are used to perform much larger two-dimensional or even higher-dimensional matrix operations that build up from these smaller elements. In at least one embodiment, an API such as the CUDA-C++ API exposes specialized matrix load, matrix multiply-and-add, and matrix store operations to efficiently use the tensor cores from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the warp-level interface assumes a matrix of size 16x16 that spans all 32 threads of a warp.

[0195] In at least one embodiment, each SM2600 includes M SFUs2612 that perform special functions (e.g., but not limited to, attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs2612 include, but are not limited to, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs2612 include, but are not limited to, a texture unit configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load texture maps (e.g., 2D arrays of texels) from memory and sample texture maps to produce sampled texture values ​​for use in shader programs executed by the SM2600. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 2618. In at least one embodiment, the texture unit implements texture operations such as filtering operations using mip maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM2600 includes, but is not limited to, two texture units.

[0196] In at least one embodiment, each SM 2600 includes, but is not limited to, N LSUs 2614 that implement load and store operations between shared memory / L1 cache 2618 and register file 2608. In at least one embodiment, each SM 2600 includes, but is not limited to, an interconnection network 2616 that connects each of the functional units to register file 2608 and connects LSUs 2614 to register file 2608 and shared memory / L1 cache 2618. In at least one embodiment, interconnection network 2616 is a crossbar that can be configured to connect any of the functional units to any of the registers in register file 2608 and connect LSUs 2614 to memory locations in register file 2608 and shared memory / L1 cache 2618.

[0197] In at least one embodiment, shared memory / L1 cache 2618 is an array of on-chip memory that enables data storage and communication between SM2600 and the primitive engines and between threads in SM2600. In at least one embodiment, shared memory / L1 cache 2618 has, but is not limited to, 128 KB of storage capacity and is in the path from SM2600 to the partition unit. In at least one embodiment, shared memory / L1 cache 2618 is used to cache reads and writes. In at least one embodiment, one or more of shared memory / L1 cache 2618, L2 cache, and memory are backing stores.

[0198] In at least one embodiment, combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity is used as a cache or available for use by programs that do not use shared memory, such as when the shared memory is configured to use half the capacity and texture and load / store operations can use the remaining capacity. In at least one embodiment, the integration within the shared memory / L1 cache 2618 allows the shared memory / L1 cache 2618 to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth, low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computation, a simpler configuration may be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed, creating a much simpler programming model. In at least one embodiment, and in the general-purpose parallel computation configuration, the work distribution unit directly assigns and distributes blocks of threads to the DPCs. In at least one embodiment, blocked threads execute the same program using unique thread IDs in computations to ensure each thread produces unique results, use SM2600 to execute the program and perform computations, use shared memory / L1 cache 2618 to communicate between threads, and use LSU2614 to read and write global memory through shared memory / L1 cache 2618 and memory partition unit 2614. In at least one embodiment, when configured for general-purpose parallel computation, SM2600 writes commands that scheduler unit 2604 can use to launch new work on DPCs.

[0199] In at least one embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smart phone (e.g., a wireless handheld device), a PDA, a digital camera, a vehicle, a head-mounted display, a handheld electronic device, etc. In at least one embodiment, the PPU is embodied on a single semiconductor substrate. In at least one embodiment, the PPU is included in an SoC with one or more other devices, such as additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.

[0200] In at least one embodiment, the PPU may be included on a graphics card that includes one or more memory devices. In at least one embodiment, the graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, the PPU may be an integrated GPU ("iGPU") included in the chipset of the motherboard.

[0201] Software Constructs for General-Purpose Computing The following diagram describes an exemplary software construct for implementing at least one embodiment, but is not limited to this embodiment.

[0202] FIG. 27 illustrates a software stack for a programming platform, according to at least one embodiment. In at least one embodiment, the programming platform is a platform for leveraging hardware on a computing system to accelerate computational tasks. In at least one embodiment, the programming platform may be accessible to software developers through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform may be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL™ is developed by the Khronos group), SYCL, or the Intel One API. In at least one embodiment, software stack 2700 includes instructions for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, software stack 2700 includes one or more instructions that, when executed, cause one or more processors and / or integrated circuits to perform the various operations described above in conjunction with Figures 1-7.

[0203] In at least one embodiment, programming platform software stack 2700 provides an execution environment for application 2701. In at least one embodiment, application 2701 may include any computer software capable of being run on software stack 2700. In at least one embodiment, application 2701 may include, but is not limited to, an artificial intelligence (“AI”) / machine learning (“ML”) application, a high performance computing (“HPC”) application, a virtual desktop infrastructure (“VDI”), or a data center workload.

[0204] In at least one embodiment, application 2701 and software stack 2700 may run on hardware 2707. In at least one embodiment, hardware 2707 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of compute devices supporting a programming platform. In at least one embodiment, such as in the case of CUDA, software stack 2700 may be vendor-specific and compatible only with devices from a particular vendor(s). In at least one embodiment, such as in the case of OpenCL, software stack 2700 may be used with devices from different vendors. In at least one embodiment, hardware 2707 includes a host connected to another device that may be accessed to perform computational tasks via application programming interface (“API”) calls. In at least one embodiment, in contrast to a host in hardware 2707, which may include, but is not limited to, a CPU (but may also include a compute device) and its memory, a device in hardware 2707 may include, but is not limited to, a GPU, FPGA, AI engine, or other compute device (but may also include a CPU) and its memory.

[0205] In at least one embodiment, the programming platform's software stack 2700 includes, but is not limited to, several libraries 2703, a runtime 2705, and a device kernel driver 2706. In at least one embodiment, each of the libraries 2703 may include data and programming code used by a computer program and utilized during software development. In at least one embodiment, the libraries 2703 may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 2703 include functionality optimized for execution on one or more types of devices. In at least one embodiment, the libraries 2703 may include, but are not limited to, functionality for performing mathematics, deep learning, and / or other types of operations on the device. In at least one embodiment, the libraries 2703 are associated with corresponding APIs 2702, which may include one or more APIs that expose the functionality implemented in the libraries 2703.

[0206] In at least one embodiment, application 2701 is written as source code that is compiled into executable code, as described in more detail below in conjunction with FIGS. 32-34. In at least one embodiment, the executable code of application 2701 may run, at least in part, on an execution environment provided by software stack 2700. In at least one embodiment, during execution of application 2701, code that needs to run on the device, as opposed to the host, may be reached. In at least one embodiment, in such cases, runtime 2705 may be called to load and launch the requisite code on the device. In at least one embodiment, runtime 2705 may include any technically feasible runtime system capable of supporting execution of application S01.

[0207] In at least one embodiment, runtime 2705 is implemented as one or more runtime libraries associated with corresponding API(s), shown as API(s) 2704. In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory, as well as transferring data between host and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching functions on the device (sometimes referred to as "kernels" when the functions are global functions callable from the host) and setting attribute values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0208] In at least one embodiment, the runtime library and corresponding API(s) 2704 may be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs may expose a low-level set of functionality for fine-grained control of the device, while another (or any number of) APIs may expose a higher-level set of such functionality. In at least one embodiment, a high-level runtime API may be built on top of the low-level API. In at least one embodiment, one or more of the runtime APIs may be language-specific APIs layered on top of a language-agnostic runtime API.

[0209] In at least one embodiment, device kernel driver 2706 is configured to facilitate communication with the underlying device. In at least one embodiment, device kernel driver 2706 may provide low-level functionality upon which APIs, such as API(s) 2704 and / or other software rely. In at least one embodiment, device kernel driver 2706 may be configured to compile intermediate representation (“IR”) code into binary code at runtime. In at least one embodiment, in the case of CUDA, device kernel driver 2706 may compile non-hardware-specific Parallel Thread Execution (“PTX”) IR code into binary code for a particular target device at runtime (with caching of the compiled binary code), which may be referred to as “finalizing” the code. In at least one embodiment, doing so may allow the finalized code to run on the target device, which may not have been present when the source code was initially compiled into PTX code. Alternatively, in at least one embodiment, the device source code may be compiled into binary code offline without requiring the device kernel driver 2706 to compile the IR code at run time.

[0210] FIG. 28 illustrates a CUDA implementation of the software stack 2700 of FIG. 27 , according to at least one embodiment. In at least one embodiment, the CUDA software stack 2800, upon which an application 2801 may be launched, includes a CUDA library 2803, a CUDA runtime 2805, a CUDA driver 2807, and a device kernel driver 2808. In at least one embodiment, the CUDA software stack 2800 executes on hardware 2809, which may include a GPU that supports CUDA and is developed by NVIDIA Corporation of Santa Clara, California. In at least one embodiment, the CUDA software stack 2800 includes instructions for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, the CUDA software stack 2800 includes one or more instructions that, when executed, cause one or more processors and / or integrated circuits described herein to perform the various operations described above in conjunction with Figures 1-7.

[0211] In at least one embodiment, application 2801, CUDA runtime 2805, and device kernel driver 2808 may perform functionality similar to application 2701, runtime 2705, and device kernel driver 2706, respectively, described above in conjunction with FIG. 27. In at least one embodiment, CUDA driver 2807 includes a library (libcuda.so) that implements CUDA driver API 2806. In at least one embodiment, similar to CUDA runtime API 2804 implemented by the CUDA runtime library (cudart), CUDA driver API 2806 may expose functionality for, among other things, but not limited to, memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 2806 differs from the CUDA runtime API 2804 in that the CUDA runtime API 2804 simplifies device code management by providing implicit initialization, context management (similar to processes), and module management (similar to dynamically loaded libraries). In at least one embodiment, in contrast to the high-level CUDA runtime API 2804, the CUDA driver API 2806 is a low-level API that provides more fine-grained control of the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 2806 may expose functionality for context management not exposed by the CUDA runtime API 2804. In at least one embodiment, the CUDA driver API 2806 is also language-independent, e.g., supports OpenCL in addition to the CUDA runtime API 2804. Additionally, in at least one embodiment, the development libraries including the CUDA runtime 2805 may be considered separate from the driver components including the user-mode CUDA driver 2807 and the kernel-mode device driver 2808 (sometimes referred to as the "display" driver).

[0212] In at least one embodiment, CUDA libraries 2803 may include, but are not limited to, mathematics libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries that may be utilized by parallel computing applications, such as application 2801. In at least one embodiment, CUDA libraries 2803 may include, among other things, mathematics libraries, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subprograms (“BLAS”) for performing linear algebra operations, the cuFFT library for computing fast Fourier transforms (“FFTs”), and the cuRAND library for generating random numbers. In at least one embodiment, CUDA libraries 2803 may include, among other deep learning libraries, such as the cuDNN library of primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference.

[0213] FIG. 29 illustrates a ROCm implementation of software stack 2700 of FIG. 27 , according to at least one embodiment. In at least one embodiment, ROCm software stack 2900, upon which application 2901 may be launched, includes language runtime 2903, system runtime 2905, thunk 2907, and ROCm kernel driver 2908. In at least one embodiment, ROCm software stack 2900 executes on hardware 2909, which may include a GPU that supports ROCm and is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, ROCm software stack 2900 includes instructions for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7 . In at least one embodiment, the ROCm software stack 2900 includes one or more instructions that, when executed, cause one or more processors and / or integrated circuits, such as those described herein, as well as any other processors and / or integrated circuits, to perform various operations described above in conjunction with FIGS. 1-7.

[0214] In at least one embodiment, application 2901 may perform functionality similar to application 2701 described above in conjunction with FIG. 27. Additionally, in at least one embodiment, language runtime 2903 and system runtime 2905 may perform functionality similar to runtime 2705 described above in conjunction with FIG. 27. In at least one embodiment, language runtime 2903 and system runtime 2905 differ in that system runtime 2905 is a language-independent runtime that implements ROCr system runtime API 2904 and utilizes the Heterogeneous System Architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user-mode API that exposes an interface for accessing and interacting with an AMD GPU, including functions for, among other things, memory management, execution control via architected dispatch of the kernel, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, language runtime 2903, as opposed to system runtime 2905, is an implementation of a language-specific runtime API 2902 layered on top of ROCr system runtime API 2904. In at least one embodiment, the language runtime API may include, but is not limited to, the Heterogeneous Compute Interface for Portability ("HIP") language runtime API, the Heterogeneous Compute Compiler ("HCC") language runtime API, or the OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA facilities, and in at least one embodiment, the HIP language runtime API includes functionality similar to the functionality of CUDA runtime API 2804 described above in conjunction with FIG. 28, such as functionality for memory management, execution control, device management, error handling, and synchronization, among others.

[0215] In at least one embodiment, thunk (ROCt) 2907 is an interface 2906 that can be used to interact with an underlying ROCm driver 2908. In at least one embodiment, ROCm driver 2908 is a ROCk driver that is a combination of an AMDGPU driver and an HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that implements functionality similar to device kernel driver 2706 described above in conjunction with FIG. 27. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more effectively share system resources through hardware features.

[0216] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 2900 above the language runtime 2903 and may provide functionality similar to the CUDA library 2803 described above in conjunction with Figure 28. In at least one embodiment, the various libraries may include, but are not limited to, mathematics, deep learning, and / or other libraries, such as, among others, a hipBLAS library that implements functionality similar to that of CUDA cuBLAS, a rocFFT library for computing FFTs that are similar to CUDA cuFFT, and the like.

[0217] Figure 30 illustrates an OpenCL implementation of software stack 2700 of Figure 27, according to at least one embodiment. In at least one embodiment, OpenCL software stack 3000, upon which application 3001 may be launched, includes OpenCL framework 3010, OpenCL runtime 3006, and driver 3007. In at least one embodiment, OpenCL software stack 3000 executes on non-vendor-specific hardware 2809. In at least one embodiment, OpenCL is supported by devices developed by different vendors, and therefore, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0218] In at least one embodiment, application 3001, OpenCL runtime 3006, device kernel driver 3007, and hardware 3008 may perform functionality similar to application 2701, runtime 2705, device kernel driver 2706, and hardware 2707, respectively, described above in conjunction with FIG. 27. In at least one embodiment, application 3001 further includes an OpenCL kernel 3002 having code to be executed on the device. In at least one embodiment, OpenCL software stack 3000 includes instructions for implementing the various components and / or performing various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, OpenCL software stack 3000 includes one or more instructions that, when executed, cause one or more processors and / or integrated circuits, such as those described herein, as well as any other processors and / or integrated circuits, to perform the various operations described above in conjunction with FIGS. 1-7.

[0219] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 3003 and runtime API 3005. In at least one embodiment, the runtime API 3005 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device may be associated with a respective context, and the runtime API 3005 may use each context to manage command queues, program objects, and kernel objects for that device, among other things, and share memory objects. In at least one embodiment, the platform API 3003 exposes functions that allow device contexts to be used to, among other things, select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. In at least one embodiment, the OpenCL framework also provides various built-in functions (not shown), including, among other things, mathematical functions, relational functions, and image processing functions.

[0220] In at least one embodiment, a compiler 3004 is also included in OpenCL framework 3010. In at least one embodiment, source code may be compiled offline prior to executing the application or online while the application is running. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment may be compiled online by compiler 3004, and compiler 3304 is included to represent any number of compilers that may be used to compile source code and / or IR code into binary code, such as Standard Portable Intermediate Representation ("SPIR-V") code. Alternatively, in at least one embodiment, OpenCL applications may be compiled offline prior to executing such applications.

[0221] FIG. 31 illustrates software supported by a programming platform, according to at least one embodiment. In at least one embodiment, programming platform 3104 is configured to support various programming models 3103, middleware and / or libraries 3102, and frameworks 3101 upon which application 3100 may rely. In at least one embodiment, application 3100 may be an AI / ML application implemented using a deep learning framework, such as MXNet, PyTorch, or TensorFlow, which may rely on libraries, such as cuDNN, the NVIDIA Collective Communications Library (“NCCL”), and / or the NVIDA Developer Data Loading Library (“DALI®”) CUDA library, to provide accelerated computing on the underlying hardware. In at least one embodiment, programming platform 3104 includes instructions for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, the programming platform 3104 includes one or more instructions that, when executed, cause one or more processors and / or integrated circuits, such as those described herein, as well as any other processors and / or integrated circuits, to perform various operations described above in conjunction with FIGS. 1-7.

[0222] In at least one embodiment, programming platform 3104 may be one of the CUDA, ROCm, or OpenCL platforms described above in conjunction with Figures 28, 29, and 30, respectively. In at least one embodiment, programming platform 3104 supports multiple programming models 3103, which are abstractions of the underlying computing system that allow expression of algorithms and data structures. In at least one embodiment, programming model 3103 may expose features of the underlying hardware to improve performance. In at least one embodiment, programming model 3103 may include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multi-Processing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute.

[0223] In at least one embodiment, libraries and / or middleware 3102 provide implementations of the abstractions in programming model 3104. In at least one embodiment, such libraries include data and programming code that can be used by computer programs and utilized during software development. In at least one embodiment, such middleware includes software that provides services to applications beyond software available from programming platform 3104. In at least one embodiment, libraries and / or middleware 3102 may include, but are not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, libraries and / or middleware 3102 may include NCCL and ROCm Communication Collectives Library ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration, and / or Eigen libraries for linear algebra, matrix and vector operations, geometric transforms, numerical solvers, and related algorithms.

[0224] In at least one embodiment, application frameworks 3101 rely on libraries and / or middleware 3102. In at least one embodiment, each of application frameworks 3101 is a software framework used to implement a standard structure of application software. Returning to the AI / ML example described above, in at least one embodiment, the AI / ML application may be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or the MxNet deep learning framework.

[0225] Figure 32 illustrates compiling code for execution on one of the programming platforms of Figures 27-30, according to at least one embodiment. In at least one embodiment, compiler 3201 receives source code 3200, which includes both host code and device code. In at least one embodiment, compiler 3201 is configured to convert source code 3200 into host executable code 3202 for execution on the host and device executable code 3203 for execution on the device. In at least one embodiment, source code 3200 may be compiled either offline prior to execution of the application or online while the application is running.

[0226] In at least one embodiment, source code 3200 may include code in any programming language supported by compiler 3201, such as C++, C, Fortran, etc. In at least one embodiment, source code 3200 may be included in a single source file having a mixture of host code and device code, with the location of the device code indicated therein. In at least one embodiment, the single source file may be a .cu file containing CUDA code or a .hip.cpp file containing HIP code. Alternatively, in at least one embodiment, source code 3200 may include multiple source code files rather than a single source file in which the host code and device code are separated.

[0227] In at least one embodiment, compiler 3201 is configured to compile source code 3200 into host executable code 3202 for execution on the host and device executable code 3203 for execution on the device. In at least one embodiment, compiler 3201 performs operations including parsing source code 3200 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment in which source code 3200 comprises a single source file, compiler 3201 may separate the device code from the host code in such single source file, compile the device code and host code into device executable code 3203 and host executable code 3202, respectively, and link the device executable code 3203 and host executable code 3202 together in the single file, as described in more detail below with respect to FIG.

[0228] In at least one embodiment, host executable code 3202 and device executable code 3203 may be in any suitable format, such as binary code and / or IR code. In at least one embodiment, in the case of CUDA, host executable code 3202 may include native object code and device executable code 3203 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host executable code 3202 and device executable code 3203 may include target binary code.

[0229] FIG. 33 is a more detailed diagram of compiling code for execution on one of the programming platforms of FIGS. 27-30 , according to at least one embodiment. In at least one embodiment, compiler 3301 is configured to receive source code 3300, compile source code 3300, and output executable file 3310. In at least one embodiment, source code 3300 is a single source file, such as a .cu file, a .hip.cpp file, or another format file, that contains both host code and device code. In at least one embodiment, compiler 3301 may be, but is not limited to, the NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in a .cu file or the HIP compiler for compiling HIP code in a .hip.cpp file.

[0230] In at least one embodiment, compiler 3301 includes compiler front end 3302, host compiler 3305, device compiler 3306, and linker 3309. In at least one embodiment, compiler front end 3302 is configured to separate device code 3304 from host code 3303 in source code 3300. In at least one embodiment, device code 3304 is compiled by device compiler 3306 into device executable code 3308, which may include binary code or IR code, as described. In at least one embodiment, separately, host code 3303 is compiled by host compiler 3305 into host executable code 3307. In at least one embodiment, for NVCC, host compiler 3305 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3306 may be, but is not limited to, a Low Level Virtual Machine ("LLVM")-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both host compiler 3305 and device compiler 3306 may be, but are not limited to, LLVM-based compilers that output target binary code.

[0231] In at least one embodiment, after compiling source code 3300 into host executable code 3307 and device executable code 3308, linker 3309 links host executable code 3307 and device executable code 3308 together in executable file 3310. In at least one embodiment, the native object code for the host and the PTX or binary code for the device may be linked together in an Executable and Linkable Format (“ELF”) file, which is a container format used to store object code.

[0232] 34 illustrates translating source code prior to compiling the source code, according to at least one embodiment. In at least one embodiment, source code 3400 is passed through translation tool 3401, which translates source code 3400 into translated source code 3402. In at least one embodiment, compiler 3403 is used to compile translated source code 3402 into host executable code 3404 and device executable code 3405, in a process similar to the compilation of source code 3200 by compiler 3201 into host executable code 3202 and device executable code 3203, as described above in conjunction with FIG. 32.

[0233] In at least one embodiment, the translation performed by translation tool 3401 is used to port source code 3400 for execution in an environment different from the environment in which it was originally intended to run. In at least one embodiment, translation tool 3401 may include, but is not limited to, a HIP translator used to "hipify" CUDA code targeted for a CUDA platform into HIP code that can be compiled and executed on the ROCm platform. In at least one embodiment, the translation of source code 3400 may include parsing source code 3400 and converting calls to API(s) provided by one programming model (e.g., CUDA) into corresponding calls to API(s) provided by another programming model (e.g., HIP), as described in more detail below in conjunction with Figures 35A-36. Returning to the example of hipfifying CUDA code, in at least one embodiment, calls to the CUDA runtime API, CUDA driver API, and / or CUDA libraries may be converted to corresponding HIP API calls. In at least one embodiment, the automatic translation performed by translation tool 3401 may sometimes be incomplete and require additional manual effort to fully port source code 3400.

[0234] Configuring GPUs for general-purpose computing The following diagram describes an exemplary architecture for compiling and executing compute source code according to, but not limited to, at least one embodiment.

[0235] 35A illustrates a system 35A00 configured to compile and execute CUDA source code 3510 using different types of processing units, according to at least one embodiment. In at least one embodiment, system 35A00 includes, but is not limited to, CUDA source code 3510, CUDA compiler 3550, host executable code 3570(1), host executable code 3570(2), CUDA device executable code 3584, CPU 3590, CUDA-enabled GPU 3594, GPU 3592, CUDA-to-HIP translation tool 3520, HIP source code 3530, HIP compiler driver 3540, HCC 3560, and HCC device executable code 3582. In at least one embodiment, system 35A00 includes instructions for implementing the various components and / or performing the various operations described above in conjunction with FIGS. 1-7. In at least one embodiment, system 35A00 includes one or more instructions that, when executed, cause one or more processors and / or integrated circuits, such as those described herein, as well as any other processors and / or integrated circuits, to perform various operations described above in conjunction with Figures 1-7.

[0236] In at least one embodiment, the CUDA source code 3510 is a set of human-readable code in the CUDA programming language. In at least one embodiment, the CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension to the C++ programming language, including, but not limited to, mechanisms for defining device code and distinguishing device code from host code. In at least one embodiment, the device code is source code that is executable in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3590, GPU 35192, or another GPGPU. In at least one embodiment, the host code is source code that is executable on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU 3590.

[0237] In at least one embodiment, CUDA source code 3510 includes, but is not limited to, any number (including zero) of global functions 3512, any number (including zero) of device functions 3514, any number (including zero) of host functions 3516, and any number (including zero) of host / device functions 3518. In at least one embodiment, global functions 3512, device functions 3514, host functions 3516, and host / device functions 3518 may be intermixed in CUDA source code 3510. In at least one embodiment, each of global functions 3512 is executable on a device and callable from a host. In at least one embodiment, one or more of global functions 3512 may therefore serve as entry points to a device. In at least one embodiment, each of global functions 3512 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more of the global functions 3512 define a kernel, which is executable on a device and callable from such a device. In at least one embodiment, the kernel is executed N times in parallel by N different threads on the device during execution, where N is any positive integer.

[0238] In at least one embodiment, each of the device functions 3514 executes on a device and is callable only from such device. In at least one embodiment, each of the host functions 3516 executes on a host and is callable only from such host. In at least one embodiment, each of the host / device functions 3516 defines both a host version of the function that executes on a host and is callable only from such host, and a device version of the function that executes on a device and is callable only from such device.

[0239] In at least one embodiment, CUDA source code 3510 may include, but is not limited to, any number of calls to any number of functions defined via CUDA runtime API 3502. In at least one embodiment, CUDA runtime API 3502 may include, but is not limited to, any number of functions that execute on the host to allocate and deallocate device memory, transfer data between host memory and device memory, manage systems with multiple devices, etc. In at least one embodiment, CUDA source code 3510 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed for use by CUDA code. In at least one embodiment, a CUDA API may include, but is not limited to, CUDA runtime API 3502, a CUDA driver API, an API for any number of CUDA libraries, etc. In at least one embodiment, and relative to the CUDA runtime API 3502, the CUDA driver API is a lower level API, but provides finer grained control of the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, etc.

[0240] In at least one embodiment, CUDA compiler 3550 compiles input CUDA code (e.g., CUDA source code 3510) to generate host executable code 3570(1) and CUDA device executable code 3584. In at least one embodiment, CUDA compiler 3550 is NVCC. In at least one embodiment, host executable code 3570(1) is a compiled version of host code contained in the input source code that is executable on CPU 3590. In at least one embodiment, CPU 3590 can be any processor optimized for sequential instruction processing.

[0241] In at least one embodiment, the CUDA device executable code 3584 is a compiled version of device code included in the input source code that is executable on a CUDA-enabled GPU 3594. In at least one embodiment, the CUDA device executable code 3584 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3584 includes IR code, such as, but not limited to, PTX code, which is further compiled at runtime by a device driver into binary code for a particular target device (e.g., a CUDA-enabled GPU 3594). In at least one embodiment, the CUDA-enabled GPU 3594 can be any processor that is optimized for parallel instruction processing and supports CUDA. In at least one embodiment, the CUDA-enabled GPU 3594 is developed by NVIDIA Corporation of Santa Clara, California.

[0242] In at least one embodiment, CUDA to HIP translation tool 3520 is configured to translate CUDA source code 3510 into functionally similar HIP source code 3530. In at least one embodiment, HIP source code 3530 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension to the C++ programming language that includes, but is not limited to, a functionally similar version of CUDA mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, a mechanism(s) for defining global functions 3512, but such HIP programming languages ​​may lack support for dynamic parallelism, and therefore, global functions 3512 defined in the HIP code may only be callable from the host.

[0243] In at least one embodiment, HIP source code 3530 includes, but is not limited to, any number of global functions 3512 (including zero), any number of device functions 3514 (including zero), any number of host functions 3516 (including zero), and any number of host / device functions 3518 (including zero). In at least one embodiment, HIP source code 3530 may also include any number of calls to any number of functions specified in HIP runtime API 3532. In at least one embodiment, HIP runtime API 3532 includes, but is not limited to, functionally similar versions of a subset of functions included in CUDA runtime API 3502. In at least one embodiment, HIP source code 3530 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, the HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, the HIP APIs include, but are not limited to, a HIP runtime API 3532, a HIP driver API, an API for any number of HIP libraries, an API for any number of ROCm libraries, and the like.

[0244] In at least one embodiment, the CUDA to HIP translation tool 3520 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax and converts any number of other CUDA calls in the CUDA code into any number of other functionally similar HIP calls. In at least one embodiment, the CUDA calls are calls to functions specified in the CUDA API and the HIP calls are calls to functions specified in the HIP API. In at least one embodiment, the CUDA to HIP translation tool 3520 converts any number of calls to functions specified in the CUDA runtime API 3502 into any number of calls to functions specified in the HIP runtime API 3532.

[0245] In at least one embodiment, the CUDA to HIP translation tool 3520 is a tool known as hipify-perl, which performs a text-based translation process. In at least one embodiment, the CUDA to HIP translation tool 3520 is a tool known as hipify-clang, which performs a more complex and robust translation process for hipify-perl that involves parsing the CUDA code using clang (a compiler front end) and then translating the resulting symbols. In at least one embodiment, properly converting the CUDA code to HIP code may require modifications (e.g., manual edits) in addition to the modifications performed by the CUDA to HIP translation tool 3520.

[0246] In at least one embodiment, HIP compiler driver 3540 is a front end that determines a target device 3546 and then configures a compiler compatible with target device 3546 to compile HIP source code 3530. In at least one embodiment, target device 3546 is a processor optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver 3540 may determine target device 3546 in any technically feasible manner.

[0247] In at least one embodiment, if target device 3546 is compatible with CUDA (e.g., CUDA-enabled GPU 3594), HIP compiler driver 3540 generates HIP / NVCC compile commands 3542. In at least one embodiment, and as described in more detail in conjunction with FIG. 35B, HIP / NVCC compile commands 3542 configure CUDA compiler 3550 to compile HIP source code 3530 using, without limitation, HIP-to-CUDA translation headers and CUDA runtime libraries. In at least one embodiment, and in response to HIP / NVCC compile commands 3542, CUDA compiler 3550 generates host executable code 3570(1) and CUDA device executable code 3584.

[0248] In at least one embodiment, if target device 3546 is not CUDA compatible, HIP compiler driver 3540 generates HIP / HCC compile commands 3544. In at least one embodiment, and as described in more detail in conjunction with FIG. 35C , HIP / HCC compile commands 3544 configure HCC 3560 to compile HIP source code 3530 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment, and in response to HIP / HCC compile commands 3544, HCC 3560 generates host executable code 3570(2) and HCC device executable code 3582. In at least one embodiment, HCC device executable code 3582 is a compiled version of device code included in HIP source code 3530 that is executable on GPU 3592. In at least one embodiment, the GPU3592 may be any processor that is optimized for parallel instruction processing, is not CUDA compatible, and is HCC compatible. In at least one embodiment, the GPU3592 is developed by AMD Corporation of Santa Clara, Calif. In at least one embodiment, the GPU3592 is a non-CUDA GPU3592.

[0249] For illustrative purposes only, three different flows that may be implemented in at least one embodiment for compiling CUDA source code 3510 for execution on a CPU 3590 and different devices are illustrated in Figure 35A. In at least one embodiment, a direct CUDA flow compiles CUDA source code 3510 for execution on a CPU 3590 and a CUDA-enabled GPU 3594 without translating the CUDA source code 3510 into HIP source code 3530. In at least one embodiment, an indirect CUDA flow translates CUDA source code 3510 into HIP source code 3530 and then compiles HIP source code 3530 for execution on a CPU 3590 and a CUDA-enabled GPU 3594. In at least one embodiment, the CUDA / HCC flow translates CUDA source code 3510 into HIP source code 3530 and then compiles the HIP source code 3530 for execution on the CPU 3590 and GPU 3592.

[0250] A direct CUDA flow that may be implemented in at least one embodiment is illustrated via dashed lines and a series of bubbles annotated A1-A3. In at least one embodiment, and as illustrated by the bubble annotated A1, a CUDA compiler 3550 receives CUDA source code 3510 and a CUDA compile command 3548 that configures the CUDA compiler 3550 to compile the CUDA source code 3510. In at least one embodiment, the CUDA source code 3510 used in the direct CUDA flow is written in the CUDA programming language, which is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3548, the CUDA compiler 3550 generates host executable code 3570(1) and CUDA device executable code 3584 (illustrated by the bubble annotated A2). In at least one embodiment, and as illustrated by the bubble annotated A3, host executable code 3570(1) and CUDA device executable code 3584 may execute on CPU 3590 and CUDA-enabled GPU 3594, respectively. In at least one embodiment, CUDA device executable code 3584 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3584 includes, but is not limited to, PTX code, which is further compiled at runtime into binary code for a particular target device.

[0251] An indirect CUDA flow that may be implemented in at least one embodiment is illustrated via a dotted line and a series of bubbles annotated B1-B6. In at least one embodiment, and as illustrated by the bubble annotated B1, a CUDA to HIP translation tool 3520 receives CUDA source code 3510. In at least one embodiment, and as illustrated by the bubble annotated B2, the CUDA to HIP translation tool 3520 translates the CUDA source code 3510 into HIP source code 3530. In at least one embodiment, and as illustrated by the bubble annotated B3, a HIP compiler driver 3540 receives the HIP source code 3530 and determines that a target device 3546 is CUDA-capable.

[0252] In at least one embodiment, and as illustrated by the bubble annotated B4, HIP compiler driver 3540 generates HIP / NVCC compile commands 3542 and sends both HIP / NVCC compile commands 3542 and HIP source code 3530 to CUDA compiler 3550. In at least one embodiment, and as described in more detail in conjunction with FIG. 35B, HIP / NVCC compile commands 3542 configure CUDA compiler 3550 to compile HIP source code 3530 using, but not limited to, HIP-to-CUDA translation headers and CUDA runtime libraries. In at least one embodiment, and in response to HIP / NVCC compile commands 3542, CUDA compiler 3550 generates host executable code 3570(1) and CUDA device executable code 3584 (illustrated by the bubble annotated B5). In at least one embodiment, and as illustrated by the bubble annotated B6, host executable code 3570(1) and CUDA device executable code 3584 may execute on CPU 3590 and CUDA-enabled GPU 3594, respectively. In at least one embodiment, CUDA device executable code 3584 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3584 includes, but is not limited to, PTX code, which is further compiled at runtime into binary code for a particular target device.

[0253] A CUDA / HCC flow that may be implemented in at least one embodiment is illustrated via a solid line and a series of bubbles annotated C1-C6. In at least one embodiment, and as illustrated by the bubble annotated C1, a CUDA to HIP translation tool 3520 receives CUDA source code 3510. In at least one embodiment, and as illustrated by the bubble annotated C2, the CUDA to HIP translation tool 3520 translates the CUDA source code 3510 into HIP source code 3530. In at least one embodiment, and as illustrated by the bubble annotated C3, a HIP compiler driver 3540 receives the HIP source code 3530 and determines that the target device 3546 is not CUDA-capable.

[0254] In at least one embodiment, HIP compiler driver 3540 generates HIP / HCC compile command 3544 and sends both HIP / HCC compile command 3544 and HIP source code 3530 to HCC 3560 (illustrated by the bubble annotated C4). In at least one embodiment, and as described in more detail in conjunction with FIG. 35C, HIP / HCC compile command 3544 configures HCC 3560 to compile HIP source code 3530 using, without limitation, HCC headers and HIP / HCC runtime libraries. In at least one embodiment, and in response to HIP / HCC compile command 3544, HCC 3560 generates host executable code 3570(2) and HCC device executable code 3582 (illustrated by the bubble annotated C5). In at least one embodiment, and as illustrated by the bubble annotated C6, host executable code 3570(2) and HCC device executable code 3582 may execute on CPU 3590 and GPU 3592, respectively.

[0255] In at least one embodiment, after CUDA source code 3510 is translated into HIP source code 3530, HIP compiler driver 3540 can then be used to generate executable code for either CUDA-enabled GPU 3594 or GPU 3592 without re-running CUDA-to-HIP translation tool 3520. In at least one embodiment, CUDA-to-HIP translation tool 3520 translates CUDA source code 3510 into HIP source code 3530, which is then stored in memory. In at least one embodiment, HIP compiler driver 3540 then configures HCC 3560 to generate host executable code 3570(2) and HCC device executable code 3582 based on HIP source code 3530. In at least one embodiment, the HIP compiler driver 3540 then configures the CUDA compiler 3550 to generate host executable code 3570(1) and CUDA device executable code 3584 based on the stored HIP source code 3530.

[0256] Figure 35B illustrates a system 3504 configured to compile and execute the CUDA source code 3510 of Figure 35A using a CPU 3590 and a CUDA-enabled GPU 3594, according to at least one embodiment. In at least one embodiment, system 3504 includes, but is not limited to, CUDA source code 3510, a CUDA-to-HIP translation tool 3520, HIP source code 3530, a HIP compiler driver 3540, a CUDA compiler 3550, host executable code 3570(1), CUDA device executable code 3584, a CPU 3590, and a CUDA-enabled GPU 3594. In at least one embodiment, system 3504 includes instructions for implementing the various components and / or performing the various operations described above in conjunction with Figures 1-7. In at least one embodiment, system 3504 includes one or more instructions that, when executed, cause one or more processors and / or integrated circuits, such as those described herein, as well as any other processors and / or integrated circuits, to perform various operations described above in conjunction with FIGS. 1-7.

[0257] In at least one embodiment, and as previously described herein in conjunction with Figure 35A, CUDA source code 3510 includes, but is not limited to, any number (including zero) of global functions 3512, any number (including zero) of device functions 3514, any number (including zero) of host functions 3516, and any number (including zero) of host / device functions 3518. In at least one embodiment, CUDA source code 3510 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0258] In at least one embodiment, CUDA to HIP translation tool 3520 translates CUDA source code 3510 into HIP source code 3530. In at least one embodiment, CUDA to HIP translation tool 3520 converts each kernel call in CUDA source code 3510 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in CUDA source code 3510 into any number of other functionally similar HIP calls.

[0259] In at least one embodiment, HIP compiler driver 3540 determines that target device 3546 is CUDA-enabled and generates HIP / NVCC compile commands 3542. In at least one embodiment, HIP compiler driver 3540 then configures CUDA compiler 3550 via HIP / NVCC compile commands 3542 to compile HIP source code 3530. In at least one embodiment, HIP compiler driver 3540, as part of configuring CUDA compiler 3550, provides access to a HIP-to-CUDA translation header 3552. In at least one embodiment, HIP-to-CUDA translation header 3552 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs into any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, CUDA compiler 3550 uses HIP-to-CUDA translation header 3552 in conjunction with CUDA runtime library 3554 corresponding to CUDA runtime API 3502 to generate host executable code 3570(1) and CUDA device executable code 3584. In at least one embodiment, host executable code 3570(1) and CUDA device executable code 3584 may then be executed on CPU 3590 and CUDA-enabled GPU 3594, respectively. In at least one embodiment, CUDA device executable code 3584 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3584 includes, but is not limited to, PTX code and is further compiled at runtime into binary code for a particular target device.

[0260] Figure 35C illustrates a system 3506 configured to compile and execute the CUDA source code 3510 of Figure 35A using a CPU 3590 and a non-CUDA GPU 3592, according to at least one embodiment. In at least one embodiment, system 3506 includes, but is not limited to, CUDA source code 3510, a CUDA to HIP translation tool 3520, HIP source code 3530, a HIP compiler driver 3540, an HCC 3560, host executable code 3570(2), an HCC device executable code 3582, a CPU 3590, and a GPU 3592.

[0261] In at least one embodiment, and as previously described herein in conjunction with Figure 35A, CUDA source code 3510 includes, but is not limited to, any number (including zero) of global functions 3512, any number (including zero) of device functions 3514, any number (including zero) of host functions 3516, and any number (including zero) of host / device functions 3518. In at least one embodiment, CUDA source code 3510 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0262] In at least one embodiment, CUDA to HIP translation tool 3520 translates CUDA source code 3510 into HIP source code 3530. In at least one embodiment, CUDA to HIP translation tool 3520 converts each kernel call in CUDA source code 3510 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in source code 3510 into any number of other functionally similar HIP calls.

[0263] In at least one embodiment, HIP compiler driver 3540 then determines that target device 3546 is not CUDA-enabled and generates HIP / HCC compile commands 3544. In at least one embodiment, HIP compiler driver 3540 then configures HCC 3560 to execute HIP / HCC compile commands 3544 to compile HIP source code 3530. In at least one embodiment, HIP / HCC compile commands 3544 configure HCC 3560 to use, without limitation, HIP / HCC runtime library 3558 and HCC headers 3556 to generate host executable code 3570(2) and HCC device executable code 3582. In at least one embodiment, HIP / HCC runtime library 3558 corresponds to HIP runtime API 3532. In at least one embodiment, HCC header 3556 includes, without limitation, any number and type of interoperability mechanisms for the HIP and HCC. In at least one embodiment, host executable code 3570(2) and HCC device executable code 3582 may execute on CPU 3590 and GPU 3592, respectively.

[0264] FIG. 36 illustrates an exemplary kernel translated by the CUDA to HIP translation tool 3520 of FIG. 35C , according to at least one embodiment. In at least one embodiment, the CUDA source code 3510 partitions the overall problem that a given kernel is designed to solve into relatively coarse-grained subproblems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads. In at least one embodiment, each subproblem is partitioned into relatively finer pieces that can be solved in parallel and in concert by threads within a thread block. In at least one embodiment, threads within a thread block can coordinate by sharing data through shared memory and by synchronizing execution to coordinate memory accesses.

[0265] In at least one embodiment, the CUDA source code 3510 organizes the thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks, where in at least one embodiment each thread block includes, but is not limited to, any number of threads and the grid includes, but is not limited to, any number of thread blocks.

[0266] In at least one embodiment, a kernel is a function in device code that is defined using the "__global__" declaration specifier. In at least one embodiment, the dimensions of the grid in which the kernel will execute for a given kernel call and associated stream are specified using CUDA kernel invocation syntax 3610. In at least one embodiment, CUDA kernel invocation syntax 3610 includes the following syntax: "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream> >>(KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<<...>>>" construct inserted between the kernel name ("KernelName") and the parenthesized list of kernel arguments ("KernelArguments"). In at least one embodiment, CUDA kernel launch syntax 3610 includes, but is not limited to, CUDA launch function syntax instead of execution configuration syntax.

[0267] In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure including, but not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing a kernel is given a unique thread ID that is accessible within the kernel through a built-in variable (e.g., "threadIdx").

[0268] In at least one embodiment, and with respect to CUDA kernel invocation syntax 3610, "SharedMemorySize" is an optional argument that specifies the number of bytes in shared memory that will be dynamically allocated per thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment, and with respect to CUDA kernel invocation syntax 3610, SharedMemorySize defaults to 0. In at least one embodiment, and with respect to CUDA kernel invocation syntax 3610, "Stream" is an optional argument that specifies the associated stream and defaults to 0 to specify the default stream. In at least one embodiment, a stream is a sequence of commands (possibly issued by different host threads) that execute in order. In at least one embodiment, different streams may execute commands out of order or concurrently with respect to each other.

[0269] In at least one embodiment, CUDA source code 3510 includes, but is not limited to, a kernel definition and a main function for an exemplary kernel "MatAdd." In at least one embodiment, the main function is host code that executes on the host and includes, but is not limited to, a kernel call that causes the kernel MatAdd to execute on the device. In at least one embodiment, and as shown, the kernel MatAdd adds two matrices A and B of size N×N, where N is a positive integer, and stores the result in matrix C. In at least one embodiment, the main function defines a threadsPerBlock variable as 16×16 and a numBlocks variable as N / 16×N / 16. In at least one embodiment, the main function then defines the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A,B,C);." In at least one embodiment, and in accordance with CUDA kernel invocation syntax 3610, the kernel MatAdd is executed using a grid of thread blocks having dimensions N / 16 x N / 16, where each thread block has dimensions 16 x 16. In at least one embodiment, each thread block includes 256 threads, and the grid is created with enough blocks to have one thread per matrix element, and each thread in such grid executes the kernel MatAdd to perform one pairwise addition.

[0270] In at least one embodiment, while translating CUDA source code 3510 into HIP source code 3530, CUDA to HIP translation tool 3520 translates each kernel call in CUDA source code 3510 from CUDA kernel launch syntax 3610 to HIP kernel launch syntax 3620 and converts any number of other CUDA calls in source code 3510 into any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax 3620 is specified as "hipLaunchKernelGGL(KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);". In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments have the same meaning in HIP kernel invocation syntax 3620 as in CUDA kernel invocation syntax 3610 (described earlier herein). In at least one embodiment, the arguments SharedMemorySize and Stream are required in HIP kernel invocation syntax 3620 and optional in CUDA kernel invocation syntax 3610.

[0271] In at least one embodiment, the portion of HIP source code 3530 illustrated in FIG. 36 is identical to the portion of CUDA source code 3510 illustrated in FIG. 36, except for the kernel call that causes kernel MatAdd to execute on the device. In at least one embodiment, kernel MatAdd is defined in HIP source code 3530 with the same "__global__" declaration specifier that kernel MatAdd is defined in CUDA source code 3510. In at least one embodiment, the kernel call in HIP source code 3530 is "hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);", while the corresponding kernel call in CUDA source code 3510 is "MatAdd<<<numBlocks,threadsPerBlock> >>(A,B,C);".

[0272] FIG. 37 illustrates the non-CUDA GPU 3592 of FIG. 35C in more detail, according to at least one embodiment. In at least one embodiment, the GPU 3592 is developed by AMD Corporation of Santa Clara. In at least one embodiment, the GPU 3592 may be configured to perform compute operations in a highly parallel manner. In at least one embodiment, the GPU 3592 is configured to execute graphics pipeline operations such as drawing commands, pixel operations, geometric calculations, and other operations related to rendering an image to a display. In at least one embodiment, the GPU 3592 is configured to execute non-graphics related operations. In at least one embodiment, the GPU 3592 is configured to execute both graphics related and non-graphics related operations. In at least one embodiment, the GPU 3592 may be configured to execute device code included in the HIP source code 3530.

[0273] In at least one embodiment, GPU 3592 includes, but is not limited to, a number of programmable processing units 3720, a command processor 3710, an L2 cache 3722, a memory controller 3770, a DMA engine 3780(1), a system memory controller 3782, a DMA engine 3780(2), and a GPU controller 3784. In at least one embodiment, each programmable processing unit 3720 includes, but is not limited to, a workload manager 3730 and a number of compute units 3740. In at least one embodiment, command processor 3710 reads commands from one or more command queues (not shown) and distributes the commands to workload manager 3730. In at least one embodiment, for each programmable processing unit 3720, the associated workload manager 3730 distributes work to the compute units 3740 included in the programmable processing unit 3720. In at least one embodiment, each compute unit 3740 may execute any number of thread blocks, but each thread block executes on a single compute unit 3740. In at least one embodiment, a workgroup is a thread block.

[0274] In at least one embodiment, each compute unit 3740 includes, but is not limited to, any number of SIMD units 3750 and shared memory 3760. In at least one embodiment, each SIMD unit 3750 may implement a SIMD architecture and be configured to perform operations in parallel. In at least one embodiment, each SIMD unit 3750 includes, but is not limited to, a vector ALU 3752 and a vector register file 3754. In at least one embodiment, each SIMD unit 3750 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication may be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via shared memory 3760.

[0275] In at least one embodiment, the programmable processing units 3720 are referred to as "shader engines." In at least one embodiment, each programmable processing unit 3720 includes any amount of dedicated graphics hardware in addition to, but not limited to, compute units 3740. In at least one embodiment, each programmable processing unit 3720 includes, but is not limited to, any number of geometry processors (including zero), any number of rasterizers (including zero), any number of render back ends (including zero), a workload manager 3730, and any number of compute units 3740.

[0276] In at least one embodiment, the compute units 3740 share an L2 cache 3722. In at least one embodiment, the L2 cache 3722 is partitioned. In at least one embodiment, the GPU memory 3790 is accessible by all of the compute units 3740 in the GPU 3592. In at least one embodiment, the memory controller 3770 and the system memory controller 3782 facilitate data transfers between the GPU 3592 and a host, and the DMA engine 3780(1) enables asynchronous memory transfers between the GPU 3592 and such a host. In at least one embodiment, the memory controller 3770 and the GPU controller 3784 facilitate data transfers between the GPU 3592 and other GPUs 3592, and the DMA engine 3780(2) enables asynchronous memory transfers between the GPU 3592 and other GPUs 3592.

[0277] In at least one embodiment, the GPU 3592 includes any quantity and type of system interconnects facilitating data and control transmission across any number and type of directly or indirectly linked components, which may be internal or external to the GPU 3592. In at least one embodiment, the GPU 3592 includes any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices, including, but not limited to, any number of display engines and any number of multimedia engines. In at least one embodiment, the GPU 3592 implements a memory subsystem, including, but not limited to, any quantity and type of memory controllers (e.g., memory controller 3770 and system memory controller 3782) and memory devices (e.g., shared memory 3760), which may be dedicated to one component or shared among multiple components. In at least one embodiment, the GPU 3592 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 3722), each of which may be private to or shared among any number of components (e.g., SIMD unit 3750, compute unit 3740, and programmable processing unit 3720).

[0278] FIG. 38 illustrates how threads of an exemplary CUDA grid 3820 are mapped to the different compute units 3740 of FIG. 37, according to at least one embodiment. In at least one embodiment, and for illustrative purposes only, the grid 3820 has a GridSize of BX×BY×1 and a BlockSize of TX×TY×1. In at least one embodiment, the grid 3820 therefore includes, but is not limited to, (BX*BY) thread blocks 3830, and each thread block 3830 includes, but is not limited to, (TX*TY) threads 3840. The threads 3840 are illustrated in FIG. 38 as squiggly arrows.

[0279] In at least one embodiment, grid 3820 is mapped to programmable processing unit 3720(1), which includes, but is not limited to, compute units 3740(1) through 3740(C). In at least one embodiment, and as shown, (BJ*BY) thread blocks 3830 are mapped to compute unit 3740(1), and the remaining thread blocks 3830 are mapped to compute unit 3740(2). In at least one embodiment, each thread block 3830 may include, but is not limited to, any number of warps, with each warp mapped to a different SIMD unit 3750 in FIG. 37.

[0280] In at least one embodiment, warps in a given thread block 3830 may synchronize with each other and communicate through shared memory 3760 included in the associated compute unit 3740. For example, and in at least one embodiment, warps in thread block 3830(BJ,1) may synchronize with each other and communicate through shared memory 3760(1). For example, and in at least one embodiment, warps in thread block 3830(BJ+1,1) may synchronize with each other and communicate through shared memory 3760(2).

[0281] Figure 39 illustrates how to migrate existing CUDA code to Data Parallel C++ code, according to at least one embodiment. Data Parallel C++ (DPC++) may refer to an open, standards-based alternative to single-architecture, proprietary languages, allowing developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and to perform custom tuning for specific accelerators. DPC++ uses similar and / or identical C and C++ constructs that conform to ISO C++, with which developers may be familiar. DPC++ incorporates the SYCL standard from the Khronos Group to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer based on the underlying concepts, portability, and efficiency of OpenCL, allowing code for heterogeneous processors to be written in a "single-source" style using standard C++. SYCL can enable single-source development, where C++ template functions contain both host and device code, allowing developers to build complex algorithms using OpenCL acceleration and then reuse them across their source code for different types of data.

[0282] In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code that can be deployed across a variety of hardware targets. In at least one embodiment, a DPC++ compiler is used to generate DPC++ applications that can be deployed across a variety of hardware targets, and DPC++ compatibility tools can be used to migrate CUDA applications to DPC++ multi-platform programs. In at least one embodiment, a DPC++ base toolkit includes a DPC++ compiler for deploying applications across a variety of hardware targets, a DPC++ library for increasing productivity and performance across CPUs, GPUs, and FPGAs, a DPC++ compatibility tool for migrating CUDA applications to multi-platform applications, or any suitable combination thereof.

[0283] In at least one embodiment, the DPC++ programming model is utilized solely for one or more aspects related to programming the CPU and accelerator by using modern C++ features to express parallelism using a programming language called Data Parallel C++. The DPC++ programming language is utilized for code reuse for the host (e.g., CPU) and accelerator (e.g., GPU or FPGA), using a single source language, and execution and memory dependencies can be clearly communicated. Mapping within the DPC++ code can be used to migrate applications to run on the hardware or set of hardware devices that best accelerate the workload. Even on platforms that do not have available accelerators, a host may be available to simplify development and debugging of device code.

[0284] In at least one embodiment, CUDA source code 3900 is provided as input to a DPC++ compatibility tool 3902 to generate a human-readable DPC++ 3904. In at least one embodiment, the human-readable DPC++ 3904 includes inline comments generated by the DPC++ compatibility tool 3902 that guide the developer as to how and / or where to modify the DPC++ code to complete the coding and tuning for desired performance 3906, thereby generating DPC++ source code 3908.

[0285] In at least one embodiment, CUDA source code 3900 is or includes a set of human-readable source code in the CUDA programming language. In at least one embodiment, CUDA source code 3900 is human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension to the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing device code from host code. In at least one embodiment, device code is source code that, after compilation, is executable on a device (e.g., a GPU or FPGA) and may run on one or more processor cores of the device or may include a more parallelizable workflow. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU, GPU, or another GPGPU. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In at least one embodiment, some or all of the host code and device code may execute in parallel across the CPU and GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. The CUDA source code 3900 described with respect to FIG. 39 may follow CUDA source code described elsewhere herein.

[0286] In at least one embodiment, DPC++ compatibility tool 3902 refers to an executable tool, program, application, or any other suitable type of tool used to facilitate the migration of CUDA source code 3900 to DPC++ source code 3908. In at least one embodiment, DPC++ compatibility tool 3902 is a command-line based code migration tool available as part of the DPC++ toolkit used to port existing CUDA source to DPC++. In at least one embodiment, DPC++ compatibility tool 3902 converts some or all of the source code of a CUDA application from CUDA to DPC++ and generates a resulting file written at least partially in DPC++, called a human-readable DPC++ 3904. In at least one embodiment, the human-readable DPC++ 3904 includes comments generated by DPC++ compatibility tool 3902 to indicate where user intervention may be required. In at least one embodiment, user intervention is required when the CUDA source code 3900 calls a CUDA API that does not have a similar DPC++ API; other instances where user intervention is required are described in more detail below.

[0287] In at least one embodiment, a workflow for migrating CUDA source code 3900 (e.g., an application or portion thereof) includes creating one or more compilation database files, migrating CUDA to DPC++ using a DPC++ compatibility tool 3902, completing and validating the migration, thereby generating DPC++ source code 3908, and compiling the DPC++ source code 3908 with a DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts commands used when a Makefile executes and stores them in a compilation database file. In at least one embodiment, the file is stored in JSON format. In at least one embodiment, an intercept-built command converts Makefile commands into DPC compatibility commands.

[0288] In at least one embodiment, intercept-build is a utility script that intercepts the build process, captures compilation options, macro definitions, and include paths, and writes this data to a compilation database file. In at least one embodiment, the compilation database file is a JSON file. In at least one embodiment, the DPC++ compatibility tool 3902 parses the compilation database and applies options when migrating input sources. In at least one embodiment, use of intercept-build is optional but highly recommended for Make or CMake-based environments. In at least one embodiment, the migration database includes commands, directories, and files, where the commands may include required compilation flags, the directories may include paths to header files, and the files may include paths to CUDA files.

[0289] In at least one embodiment, the DPC++ compatibility tool 3902 migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ whenever possible. In at least one embodiment, the DPC++ compatibility tool 3902 is available as part of a tool kit. In at least one embodiment, the DPC++ tool kit includes an intercept-build tool. In at least one embodiment, the intercept-built tool creates a compilation database that captures compilation commands to migrate CUDA files. In at least one embodiment, the compilation database generated by the intercept-built tool is used by the DPC++ compatibility tool 3902 to migrate the CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, the DPC++ compatibility tool 3902 generates a human-readable DPC++ 3904, which may be DPC++ code that, when generated by the DPC++ compatibility tool 3902, may not compile with the DPC++ compiler and may require additional plumbing to identify portions of code that were not correctly migrated, which may involve manual intervention, such as by a developer. In at least one embodiment, the DPC++ compatibility tool 3902 provides hints or tools embedded in the code to help the developer manually migrate additional code that may not be automatically migrated. In at least one embodiment, migration is a one-time activity for a source file, project, or application.

[0290] In at least one embodiment, the DPC++ compatibility tool 39002 may successfully migrate all portions of CUDA code to DPC++, with only an optional step to manually review and tune the performance of the generated DPC++ source code. In at least one embodiment, the DPC++ compatibility tool 3902 directly generates DPC++ source code 3908 that is compiled by a DPC++ compiler without requiring or utilizing human intervention to modify the DPC++ code generated by the DPC++ compatibility tool 3902. In at least one embodiment, the DPC++ compatibility tool generates compilable DPC++ code that may be optionally tuned by a developer for performance, readability, maintainability, various other considerations, or any combination thereof.

[0291] In at least one embodiment, one or more CUDA source files are at least partially migrated to DPC++ source files using DPC++ compatibility tool 3902. In at least one embodiment, the CUDA source code includes one or more header files, which may include CUDA header files. In at least one embodiment, the CUDA source files include<cuda.h> Header files can be used to print text<stdio.h> In at least one embodiment, a portion of a vector addition kernel CUDA source file may be written as follows or related to the following:

number

number

[0292] In at least one embodiment, and with respect to the CUDA source files presented above, the DPC++ compatibility tool 3902 parses the CUDA source code and replaces header files with appropriate DPC++ and SYCL header files. In at least one embodiment, the DPC++ header files include helper declarations. In CUDA, there is the concept of a thread ID; correspondingly, in DPC++ or SYCL, there is a local identifier for each element.

[0293] In at least one embodiment, and with respect to the CUDA source file presented above, there are two vectors A and B that are initialized, and the vector addition result is put into vector C as part of VectorAddKernel(). In at least one embodiment, DPC++ compatibility tool 3902 converts CUDA thread IDs used to index work elements to SYCL standard addressing for work elements via local IDs as part of migrating CUDA code to DPC++ code. In at least one embodiment, the DPC++ code generated by DPC++ compatibility tool 3902 can be optimized, for example, by reducing the dimensionality of nd_item, thereby increasing memory and / or processor utilization.

[0294] In at least one embodiment, and with respect to the CUDA source files presented above, memory allocation is migrated. In at least one embodiment, cudaMalloc() is migrated to a unified shared memory SYCL call malloc_device(), to which a device and context are passed, relying on SYCL concepts such as platform, device, context, and queue. In at least one embodiment, a SYCL platform can have multiple devices (e.g., host and GPU devices), a device can have multiple queues to which jobs can be submitted, each device can have a context, and a context can have multiple devices and manage shared memory objects.

[0295] In at least one embodiment, and with respect to the CUDA source file presented above, the main() function invokes or calls VectorAddKernel() to add two vectors A and B together and store the result in vector C. In at least one embodiment, the CUDA code to invoke VectorAddKernel() is replaced by DPC++ code to submit the kernel to a command queue for execution. In at least one embodiment, the command group handler cgh passes the data, synchronization, and computation to be submitted to the queue, and parallel_for is called for the number of global elements and the number of work items in the work group for which VectorAddKernel() is called.

[0296] In at least one embodiment, and with respect to the CUDA source files presented above, CUDA calls for copying device memory and then freeing memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing a vector of floating-point variables) is migrated as is without modification by DPC++ compatibility tool 3902. In at least one embodiment, DPC++ compatibility tool 3902 modifies CUDA APIs for memory setup and / or host calls to execute the kernel on the acceleration device. In at least one embodiment, and with respect to the CUDA source files presented above, a corresponding human-readable DPC++ 3904 (which may be compiled, for example) is written as follows or relates to the following:

number

number

number

[0297] In at least one embodiment, human-readable DPC+ 3904 refers to the output generated by DPC++ compatibility tool 3902 and may be optimized in one way or another. In at least one embodiment, human-readable DPC+ 3904 generated by DPC++ compatibility tool 3902 may be manually edited by a developer after migration to make it more maintainable, for performance, or other considerations. In at least one embodiment, DPC++ code generated by DPC++ compatibility tool 3902, such as the disclosed DPC++, may be optimized by removing repeated calls to get_current_device() and / or get_default_context() for each malloc_device() call. In at least one embodiment, the DPC++ code generated above uses a three-dimensional nd_range, which may be refactored to use only a single dimension, thereby reducing memory usage. In at least one embodiment, a developer may manually edit the DPC++ code generated by DPC++ compatibility tool 3902 and replace the use of uniform shared memory with accessors. In at least one e...

Claims

1. One or more circuits that execute an application programming interface (API) and provide one or more addresses of data referenced by said API. Equipped with The one or more API calls cause one or more APIs or other software libraries to determine one of whether one or more memory blocks, regions, and / or pools of memory of one or more devices indicated by the one or more device identifier parameters are currently shareable, whether they will become shareable, and whether they were shareable during execution of the one or more software modules.

2. 2. The processor of claim 1, wherein the API receives, as input, a memory address and indicates the one or more addresses by providing an identifier of the one or more addresses as a result of the one or more addresses including the memory address.

3. 2. The processor of claim 1, wherein the API indicates a null data value if one or more addresses of the data referenced by the API do not include an address indicated as a parameter to the API.

4. The processor of claim 1 , wherein the processor further executes a driver for implementing the API.

5. 2. The processor of claim 1, wherein the API indicates one or more addresses of the data referenced by the API in response to one or more API calls that indicate one or more data values ​​that include one or more addresses within one or more blocks of memory.

6. The processor of claim 1 , wherein the one or more addresses indicate blocks of memory usable by one or more graphics processing units (GPUs).

7. 2. The processor of claim 1, wherein the one or more addresses of the data referenced by the API comprise one or more memory pools containing one or more blocks of memory allocated using one or more stream order memory allocators.

8. One or more processors that execute an application programming interface (API) to indicate one or more addresses of data referenced by said API. Equipped with A system in which the one or more API calls cause one or more APIs or other software libraries to determine one of whether one or more memory blocks, regions, and / or pools of memory of one or more devices indicated by one or more device identifier parameters are currently shareable, whether they will become shareable, and whether they were shareable during execution of the one or more software modules.

9. 9. The system of claim 8, wherein the API receives one or more parameters indicating one or more memory locations, and the API indicates one or more addresses of the data to which the API refers based, at least in part, on the one or more addresses that include the one or more memory locations.

10. 9. The system of claim 8, wherein the API indicates a null data value if one or more addresses of the data referenced by the API do not include one or more memory locations indicated as parameters to the API.

11. 9. The system of claim 8, wherein the one or more processors further execute one or more drivers, the one or more drivers executing the API in response to one or more API calls.

12. 9. The system of claim 8, wherein the API indicates one or more addresses of the data referenced by the API in response to one or more API calls that indicate one or more data values ​​that include one or more addresses within one or more blocks of memory.

13. 9. The system of claim 8, wherein the one or more addresses of the data referenced by the API indicate one or more blocks of memory usable by one or more graphics processing units (GPUs).

14. 9. The system of claim 8, wherein the one or more addresses of the data referenced by the API indicate one or more blocks of memory allocable using one or more stream order memory allocators.

15. A machine-readable medium storing one or more application programming interfaces (APIs) that, when executed at least in part by one or more processors, cause the one or more processors to at least: indicating one or more addresses of data referenced by the one or more APIs; A machine-readable medium, in which the one or more API calls cause one or more APIs or other software libraries to determine one of whether one or more memory blocks, regions, and / or pools of memory of one or more devices indicated by one or more device identifier parameters are currently shareable, whether they will become shareable, and whether they were shareable during execution of the one or more software modules.

16. 16. The machine-readable medium of claim 15, wherein the one or more APIs receive, as a result of one or more API calls, one or more data values ​​that indicate one or more memory locations, and the one or more processors indicate one or more addresses of the data referenced by the APIs based, at least in part, on the one or more addresses that include the one or more memory locations.

17. 16. The machine-readable medium of claim 15, wherein the one or more processors indicate a null data value if one or more addresses of the data referenced by the one or more APIs do not include one or more other addresses indicated as one or more parameters to the one or more APIs.

18. 16. The machine-readable medium of claim 15, further comprising instructions that, when executed by the one or more processors, cause the one or more processors to execute one or more drivers, wherein the one or more drivers cause the one or more processors to indicate the one or more addresses in response to one or more API calls to the one or more APIs.

19. 16. The machine-readable medium of claim 15, wherein the one or more APIs indicate one or more addresses of the data referenced by the one or more APIs in response to one or more API calls to the one or more APIs, the one or more API calls including data indicating one or more addresses within one or more blocks of memory.

20. 16. The machine-readable medium of claim 15, wherein one or more addresses of the data referenced by the one or more APIs indicate regions of one or more memories usable by one or more graphics processing units (GPUs).

21. 16. The machine-readable medium of claim 15, wherein one or more addresses of the data referenced by the one or more APIs indicate one or more regions of memory allocable using one or more asynchronous allocators.

22. indicating, by an application programming interface (API), one or more addresses of data to which said API refers; Including, A method in which one or more API calls cause one or more APIs or other software libraries to determine one of whether one or more memory blocks, regions, and / or pools of memory of one or more devices indicated by one or more device identifier parameters are currently shareable, whether they will become shareable, and whether they were shareable during execution of one or more software modules.

23. 23. The method of claim 22, further comprising indicating the one or more addresses in response to one or more API calls to the API, the API calls including one or more data values ​​indicating one or more memory locations.

24. 23. The method of claim 22, further comprising: indicating the one or more addresses in response to the one or more addresses comprising one or more memory locations indicated to the API as parameters of one or more API calls.

25. 23. The method of claim 22, wherein the one or more addresses of the data referenced by the API indicate one or more blocks of memory usable by one or more graphics processing units (GPUs).

26. 23. The method of claim 22, further comprising: receiving, by the API, one or more data values ​​indicating one or more memory locations as a result of one or more API calls; and indicating one or more addresses of the data referenced by the API based, at least in part, on the one or more addresses that include the one or more memory locations.

27. 23. The method of claim 22, further comprising indicating a null data value if the one or more addresses of the data referenced by the API do not include one or more other addresses indicated to the API as one or more parameters.

28. 23. The method of claim 22, wherein the one or more addresses of the data referenced by the API indicate one or more pools of memory allocable using one or more stream order memory allocators.

Images